diff --git a/bsp/stm32f107/drivers/stm32_eth.c b/bsp/stm32f107/drivers/stm32_eth.c index 06b10afdc7dc07d8ff0ea79fa6f83f8b4460fa41..f0de9a60d396f11ad02f13992113f913f21c0c56 100644 --- a/bsp/stm32f107/drivers/stm32_eth.c +++ b/bsp/stm32f107/drivers/stm32_eth.c @@ -23,10 +23,10 @@ #include "stm32f10x_rcc.h" /* STM32F107 ETH dirver options */ -#define CHECKSUM_BY_HARDWARE -#define MII_MODE /* MII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */ -//#define RMII_MODE /* RMII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */ - +#define CHECKSUM_BY_HARDWARE 1 /* 0: disable. 1: use hardware checksum. */ +#define RMII_MODE 0 /* 0: MII MODE, 1: RMII MODE. */ +#define STM32_ETH_IO_REMAP 1 /* 0: default, 1: remap RXD to PDx. */ +#define USE_MCO 1 /* 0: disable, 1: PA8(MCO) out 25Mhz(MII) or 50Mhz(RMII). */ /** @addtogroup STM32_ETH_Driver * @brief ETH driver modules @@ -124,8 +124,8 @@ ETH_DMADESCTypeDef *DMAPTPRxDescToGet; */ void ETH_DeInit(void) { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE); } /** @@ -138,216 +138,216 @@ void ETH_DeInit(void) */ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct) { - uint32_t tmpreg = 0; - __IO uint32_t i = 0; - RCC_ClocksTypeDef rcc_clocks; - uint32_t hclk = 60000000; - __IO uint32_t timeout = 0; - - /* Check the parameters */ - /* MAC --------------------------*/ - assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation)); - assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog)); - assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber)); - assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap)); - assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense)); - assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed)); - assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn)); - assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode)); - assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode)); - assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload)); - assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission)); - assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip)); - assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit)); - assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck)); - assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll)); - assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter)); - assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames)); - assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception)); - assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter)); - assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); - assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); - assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter)); - assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime)); - assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause)); - assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold)); - assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect)); - assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl)); - assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl)); - assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison)); - assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier)); - /* DMA --------------------------*/ - assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame)); - assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward)); - assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame)); - assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward)); - assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl)); - assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames)); - assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames)); - assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl)); - assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate)); - assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats)); - assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst)); - assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength)); - assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); - assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); - assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); - - /*-------------------------------- MAC Config ------------------------------*/ - /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/ - /* Get the ETHERNET MACMIIAR value */ - tmpreg = ETH->MACMIIAR; - /* Clear CSR Clock Range CR[2:0] bits */ - tmpreg &= MACMIIAR_CR_MASK; - /* Get hclk frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - hclk = rcc_clocks.HCLK_Frequency; - /* Set CR bits depending on hclk value */ - if((hclk >= 20000000)&&(hclk < 35000000)) - { - /* CSR Clock Range between 20-35 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; - } - else if((hclk >= 35000000)&&(hclk < 60000000)) - { - /* CSR Clock Range between 35-60 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } - else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */ - { - /* CSR Clock Range between 60-72 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; - } - /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - ETH->MACMIIAR = (uint32_t)tmpreg; - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = ETH->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= MACCR_CLEAR_MASK; - /* Set the WD bit according to ETH_Watchdog value */ - /* Set the JD: bit according to ETH_Jabber value */ - /* Set the IFG bit according to ETH_InterFrameGap value */ - /* Set the DCRS bit according to ETH_CarrierSense value */ - /* Set the FES bit according to ETH_Speed value */ - /* Set the DO bit according to ETH_ReceiveOwn value */ - /* Set the LM bit according to ETH_LoopbackMode value */ - /* Set the DM bit according to ETH_Mode value */ - /* Set the IPC bit according to ETH_ChecksumOffload value */ - /* Set the DR bit according to ETH_RetryTransmission value */ - /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ - /* Set the BL bit according to ETH_BackOffLimit value */ - /* Set the DC bit according to ETH_DeferralCheck value */ - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | - ETH_InitStruct->ETH_Jabber | - ETH_InitStruct->ETH_InterFrameGap | - ETH_InitStruct->ETH_CarrierSense | - ETH_InitStruct->ETH_Speed | - ETH_InitStruct->ETH_ReceiveOwn | - ETH_InitStruct->ETH_LoopbackMode | - ETH_InitStruct->ETH_Mode | - ETH_InitStruct->ETH_ChecksumOffload | - ETH_InitStruct->ETH_RetryTransmission | - ETH_InitStruct->ETH_AutomaticPadCRCStrip | - ETH_InitStruct->ETH_BackOffLimit | - ETH_InitStruct->ETH_DeferralCheck); - /* Write to ETHERNET MACCR */ - ETH->MACCR = (uint32_t)tmpreg; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Set the RA bit according to ETH_ReceiveAll value */ - /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */ - /* Set the PCF bit according to ETH_PassControlFrames value */ - /* Set the DBF bit according to ETH_BroadcastFramesReception value */ - /* Set the DAIF bit according to ETH_DestinationAddrFilter value */ - /* Set the PR bit according to ETH_PromiscuousMode value */ - /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */ - /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | - ETH_InitStruct->ETH_SourceAddrFilter | - ETH_InitStruct->ETH_PassControlFrames | - ETH_InitStruct->ETH_BroadcastFramesReception | - ETH_InitStruct->ETH_DestinationAddrFilter | - ETH_InitStruct->ETH_PromiscuousMode | - ETH_InitStruct->ETH_MulticastFramesFilter | - ETH_InitStruct->ETH_UnicastFramesFilter); - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ - /* Write to ETHERNET MACHTHR */ - ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; - /* Write to ETHERNET MACHTLR */ - ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - /* Get the ETHERNET MACFCR value */ - tmpreg = ETH->MACFCR; - /* Clear xx bits */ - tmpreg &= MACFCR_CLEAR_MASK; - - /* Set the PT bit according to ETH_PauseTime value */ - /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ - /* Set the PLT bit according to ETH_PauseLowThreshold value */ - /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */ - /* Set the RFE bit according to ETH_ReceiveFlowControl value */ - /* Set the TFE bit according to ETH_TransmitFlowControl value */ - tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | - ETH_InitStruct->ETH_ZeroQuantaPause | - ETH_InitStruct->ETH_PauseLowThreshold | - ETH_InitStruct->ETH_UnicastPauseFrameDetect | - ETH_InitStruct->ETH_ReceiveFlowControl | - ETH_InitStruct->ETH_TransmitFlowControl); - /* Write to ETHERNET MACFCR */ - ETH->MACFCR = (uint32_t)tmpreg; - /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - /* Set the ETV bit according to ETH_VLANTagComparison value */ - /* Set the VL bit according to ETH_VLANTagIdentifier value */ - ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | - ETH_InitStruct->ETH_VLANTagIdentifier); - - /*-------------------------------- DMA Config ------------------------------*/ - /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ - /* Get the ETHERNET DMAOMR value */ - tmpreg = ETH->DMAOMR; - /* Clear xx bits */ - tmpreg &= DMAOMR_CLEAR_MASK; - - /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ - /* Set the RSF bit according to ETH_ReceiveStoreForward value */ - /* Set the DFF bit according to ETH_FlushReceivedFrame value */ - /* Set the TSF bit according to ETH_TransmitStoreForward value */ - /* Set the TTC bit according to ETH_TransmitThresholdControl value */ - /* Set the FEF bit according to ETH_ForwardErrorFrames value */ - /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */ - /* Set the RTC bit according to ETH_ReceiveThresholdControl value */ - /* Set the OSF bit according to ETH_SecondFrameOperate value */ - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | - ETH_InitStruct->ETH_ReceiveStoreForward | - ETH_InitStruct->ETH_FlushReceivedFrame | - ETH_InitStruct->ETH_TransmitStoreForward | - ETH_InitStruct->ETH_TransmitThresholdControl | - ETH_InitStruct->ETH_ForwardErrorFrames | - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | - ETH_InitStruct->ETH_ReceiveThresholdControl | - ETH_InitStruct->ETH_SecondFrameOperate); - /* Write to ETHERNET DMAOMR */ - ETH->DMAOMR = (uint32_t)tmpreg; - - /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - /* Set the AAL bit according to ETH_AddressAlignedBeats value */ - /* Set the FB bit according to ETH_FixedBurst value */ - /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */ - /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */ - /* Set the DSL bit according to ETH_DesciptorSkipLength value */ - /* Set the PR and DA bits according to ETH_DMAArbitration value */ - ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | - ETH_InitStruct->ETH_FixedBurst | - ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - ETH_InitStruct->ETH_TxDMABurstLength | - (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | - ETH_InitStruct->ETH_DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - /* Return Ethernet configuration success */ - return ETH_SUCCESS; + uint32_t tmpreg = 0; + __IO uint32_t i = 0; + RCC_ClocksTypeDef rcc_clocks; + uint32_t hclk = 60000000; + __IO uint32_t timeout = 0; + + /* Check the parameters */ + /* MAC --------------------------*/ + assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation)); + assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog)); + assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense)); + assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed)); + assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode)); + assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission)); + assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck)); + assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll)); + assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter)); + assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception)); + assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter)); + assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime)); + assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect)); + assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl)); + assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier)); + /* DMA --------------------------*/ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward)); + assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame)); + assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate)); + assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst)); + assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength)); + assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); + + /*-------------------------------- MAC Config ------------------------------*/ + /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= MACMIIAR_CR_MASK; + /* Get hclk frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + hclk = rcc_clocks.HCLK_Frequency; + /* Set CR bits depending on hclk value */ + if((hclk >= 20000000)&&(hclk < 35000000)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; + } + else if((hclk >= 35000000)&&(hclk < 60000000)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; + } + else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */ + { + /* CSR Clock Range between 60-72 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + ETH->MACMIIAR = (uint32_t)tmpreg; + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = ETH->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= MACCR_CLEAR_MASK; + /* Set the WD bit according to ETH_Watchdog value */ + /* Set the JD: bit according to ETH_Jabber value */ + /* Set the IFG bit according to ETH_InterFrameGap value */ + /* Set the DCRS bit according to ETH_CarrierSense value */ + /* Set the FES bit according to ETH_Speed value */ + /* Set the DO bit according to ETH_ReceiveOwn value */ + /* Set the LM bit according to ETH_LoopbackMode value */ + /* Set the DM bit according to ETH_Mode value */ + /* Set the IPC bit according to ETH_ChecksumOffload value */ + /* Set the DR bit according to ETH_RetryTransmission value */ + /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH_BackOffLimit value */ + /* Set the DC bit according to ETH_DeferralCheck value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | + ETH_InitStruct->ETH_Jabber | + ETH_InitStruct->ETH_InterFrameGap | + ETH_InitStruct->ETH_CarrierSense | + ETH_InitStruct->ETH_Speed | + ETH_InitStruct->ETH_ReceiveOwn | + ETH_InitStruct->ETH_LoopbackMode | + ETH_InitStruct->ETH_Mode | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_RetryTransmission | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_BackOffLimit | + ETH_InitStruct->ETH_DeferralCheck); + /* Write to ETHERNET MACCR */ + ETH->MACCR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Set the RA bit according to ETH_ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */ + /* Set the PCF bit according to ETH_PassControlFrames value */ + /* Set the DBF bit according to ETH_BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH_DestinationAddrFilter value */ + /* Set the PR bit according to ETH_PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | + ETH_InitStruct->ETH_SourceAddrFilter | + ETH_InitStruct->ETH_PassControlFrames | + ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_DestinationAddrFilter | + ETH_InitStruct->ETH_PromiscuousMode | + ETH_InitStruct->ETH_MulticastFramesFilter | + ETH_InitStruct->ETH_UnicastFramesFilter); + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; + /* Write to ETHERNET MACHTLR */ + ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + /* Get the ETHERNET MACFCR value */ + tmpreg = ETH->MACFCR; + /* Clear xx bits */ + tmpreg &= MACFCR_CLEAR_MASK; + + /* Set the PT bit according to ETH_PauseTime value */ + /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ + /* Set the PLT bit according to ETH_PauseLowThreshold value */ + /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH_ReceiveFlowControl value */ + /* Set the TFE bit according to ETH_TransmitFlowControl value */ + tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | + ETH_InitStruct->ETH_ZeroQuantaPause | + ETH_InitStruct->ETH_PauseLowThreshold | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_ReceiveFlowControl | + ETH_InitStruct->ETH_TransmitFlowControl); + /* Write to ETHERNET MACFCR */ + ETH->MACFCR = (uint32_t)tmpreg; + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ + /* Set the ETV bit according to ETH_VLANTagComparison value */ + /* Set the VL bit according to ETH_VLANTagIdentifier value */ + ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | + ETH_InitStruct->ETH_VLANTagIdentifier); + + /*-------------------------------- DMA Config ------------------------------*/ + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg = ETH->DMAOMR; + /* Clear xx bits */ + tmpreg &= DMAOMR_CLEAR_MASK; + + /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH_ReceiveStoreForward value */ + /* Set the DFF bit according to ETH_FlushReceivedFrame value */ + /* Set the TSF bit according to ETH_TransmitStoreForward value */ + /* Set the TTC bit according to ETH_TransmitThresholdControl value */ + /* Set the FEF bit according to ETH_ForwardErrorFrames value */ + /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH_ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH_SecondFrameOperate value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | + ETH_InitStruct->ETH_ReceiveStoreForward | + ETH_InitStruct->ETH_FlushReceivedFrame | + ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_TransmitThresholdControl | + ETH_InitStruct->ETH_ForwardErrorFrames | + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | + ETH_InitStruct->ETH_ReceiveThresholdControl | + ETH_InitStruct->ETH_SecondFrameOperate); + /* Write to ETHERNET DMAOMR */ + ETH->DMAOMR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + /* Set the AAL bit according to ETH_AddressAlignedBeats value */ + /* Set the FB bit according to ETH_FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */ + /* Set the DSL bit according to ETH_DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH_DMAArbitration value */ + ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | + ETH_InitStruct->ETH_FixedBurst | + ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + ETH_InitStruct->ETH_TxDMABurstLength | + (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | + ETH_InitStruct->ETH_DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + /* Return Ethernet configuration success */ + return ETH_SUCCESS; } /** @@ -357,56 +357,56 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct) */ void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) { - /* ETH_InitStruct members default value */ - /*------------------------ MAC -----------------------------------*/ - ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; - ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; - ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; - ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; - ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; - ETH_InitStruct->ETH_Speed = ETH_Speed_10M; - ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; - ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; - ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; - ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; - ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; - ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; - ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; - ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; - ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; - ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; - ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; - ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; - ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; - ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; - ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; - ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; - ETH_InitStruct->ETH_HashTableHigh = 0x0; - ETH_InitStruct->ETH_HashTableLow = 0x0; - ETH_InitStruct->ETH_PauseTime = 0x0; - ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; - ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; - ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; - ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; - ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; - ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; - ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; - /*------------------------ DMA -----------------------------------*/ - ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; - ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; - ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable; - ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; - ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; - ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; - ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; - ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; - ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; - ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; - ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; - ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; - ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; - ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; + /* ETH_InitStruct members default value */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; } /** @@ -416,17 +416,17 @@ void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) */ void ETH_Start(void) { - /* Enable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionCmd(ENABLE); - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(); - /* Enable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionCmd(ENABLE); + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionCmd(ENABLE); + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(); + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionCmd(ENABLE); - /* Start DMA transmission */ - ETH_DMATransmissionCmd(ENABLE); - /* Start DMA reception */ - ETH_DMAReceptionCmd(ENABLE); + /* Start DMA transmission */ + ETH_DMATransmissionCmd(ENABLE); + /* Start DMA reception */ + ETH_DMAReceptionCmd(ENABLE); } /** @@ -438,58 +438,58 @@ void ETH_Start(void) */ uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) { - uint32_t offset = 0; - - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) - { - /* Return ERROR: OWN bit set */ - return ETH_ERROR; - } - - /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ - for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); - } - - /* Setting the Frame Length: bits[12:0] */ - DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); - /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ - DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - ETH->DMASR = ETH_DMASR_TBUS; - /* Resume DMA transmission*/ - ETH->DMATPDR = 0; - } + uint32_t offset = 0; - /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ - /* Chained Mode */ - if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) - { - /* Selects the next DMA Tx descriptor list for next buffer to send */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); - } - else /* Ring Mode */ - { - if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) { - /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + /* Return ERROR: OWN bit set */ + return ETH_ERROR; } - else + + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetDMABMR & ETH_DMABMR_DSL) >> 2)); + (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); } - } - /* Return SUCCESS */ - return ETH_SUCCESS; + + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; } /** @@ -500,66 +500,66 @@ uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) */ uint32_t ETH_HandleRxPkt(uint8_t *ppkt) { - uint32_t offset = 0, framelength = 0; - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) - { - /* Return error: OWN bit set */ - return ETH_ERROR; - } - - if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) - { - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ - for(offset=0; offsetBuffer1Addr) + offset)); - } - } - else - { - /* Return ERROR */ - framelength = ETH_ERROR; - } - /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMARxDescToGet->Status = ETH_DMARxDesc_OWN; - - /* When Rx Buffer unavailable flag is set: clear it and resume reception */ - if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) - { - /* Clear RBUS ETHERNET DMA flag */ - ETH->DMASR = ETH_DMASR_RBUS; - /* Resume DMA reception */ - ETH->DMARPDR = 0; - } - - /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ - /* Chained Mode */ - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - { - /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); - } - else /* Ring Mode */ - { - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) - { - /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } } else { - /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + /* Return ERROR */ + framelength = ETH_ERROR; } - } + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; - /* Return Frame Length/ERROR */ - return (framelength); + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + /* Return Frame Length/ERROR */ + return (framelength); } /** @@ -569,18 +569,18 @@ uint32_t ETH_HandleRxPkt(uint8_t *ppkt) */ uint32_t ETH_GetRxPktSize(void) { - uint32_t frameLength = 0; - if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) - { - /* Get the size of the packet: including 4 bytes of the CRC */ - frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); - } + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the size of the packet: including 4 bytes of the CRC */ + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } - /* Return Frame Length */ - return frameLength; + /* Return Frame Length */ + return frameLength; } /** @@ -590,28 +590,28 @@ uint32_t ETH_GetRxPktSize(void) */ void ETH_DropRxPkt(void) { - /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMARxDescToGet->Status = ETH_DMARxDesc_OWN; - /* Chained Mode */ - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - { - /* Selects the next DMA Rx descriptor list for next buffer read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); - } - else /* Ring Mode */ - { - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) - { - /* Selects the next DMA Rx descriptor list for next buffer read: this will - be the first Rx descriptor in this case */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); } - else + else /* Ring Mode */ { - /* Selects the next DMA Rx descriptor list for next buffer read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read: this will + be the first Rx descriptor in this case */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } } - } } /*--------------------------------- PHY ------------------------------------*/ @@ -630,37 +630,38 @@ void ETH_DropRxPkt(void) */ uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) { - uint32_t tmpreg = 0; -__IO uint32_t timeout = 0; - /* Check the parameters */ - assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); - assert_param(IS_ETH_PHY_REG(PHYReg)); - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = ETH->MACMIIAR; - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~MACMIIAR_CR_MASK; - /* Prepare the MII address register value */ - tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - /* Write the result value into the MII Address register */ - ETH->MACMIIAR = tmpreg; - /* Check for the Busy flag */ - do - { - timeout++; + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ tmpreg = ETH->MACMIIAR; - } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); - /* Return ERROR in case of timeout */ - if(timeout == PHY_READ_TO) - { - return (uint16_t)ETH_ERROR; - } + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_MASK; + /* Prepare the MII address register value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } + while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } - /* Return data register value */ - return (uint16_t)(ETH->MACMIIDR); + /* Return data register value */ + return (uint16_t)(ETH->MACMIIDR); } /** @@ -677,39 +678,40 @@ __IO uint32_t timeout = 0; */ uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) { - uint32_t tmpreg = 0; - __IO uint32_t timeout = 0; - /* Check the parameters */ - assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); - assert_param(IS_ETH_PHY_REG(PHYReg)); - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = ETH->MACMIIAR; - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~MACMIIAR_CR_MASK; - /* Prepare the MII register address value */ - tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - /* Give the value to the MII data register */ - ETH->MACMIIDR = PHYValue; - /* Write the result value into the MII Address register */ - ETH->MACMIIAR = tmpreg; - /* Check for the Busy flag */ - do - { - timeout++; + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ tmpreg = ETH->MACMIIAR; - } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); - /* Return ERROR in case of timeout */ - if(timeout == PHY_WRITE_TO) - { - return ETH_ERROR; - } + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_MASK; + /* Prepare the MII register address value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Give the value to the MII data register */ + ETH->MACMIIDR = PHYValue; + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } + while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_WRITE_TO) + { + return ETH_ERROR; + } - /* Return SUCCESS */ - return ETH_SUCCESS; + /* Return SUCCESS */ + return ETH_SUCCESS; } /** @@ -725,34 +727,34 @@ uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHY */ uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) { - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the PHY configuration to update it */ - tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); - - if (NewState != DISABLE) - { - /* Enable the PHY loopback mode */ - tmpreg |= PHY_Loopback; - } - else - { - /* Disable the PHY loopback mode: normal mode */ - tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); - } - /* Update the PHY control register with the new configuration */ - if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) - { - return ETH_SUCCESS; - } - else - { - /* Return SUCCESS */ - return ETH_ERROR; - } + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the PHY configuration to update it */ + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if (NewState != DISABLE) + { + /* Enable the PHY loopback mode */ + tmpreg |= PHY_Loopback; + } + else + { + /* Disable the PHY loopback mode: normal mode */ + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + /* Update the PHY control register with the new configuration */ + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + /* Return SUCCESS */ + return ETH_ERROR; + } } /*--------------------------------- MAC ------------------------------------*/ @@ -764,19 +766,19 @@ uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) */ void ETH_MACTransmissionCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the MAC transmission */ - ETH->MACCR |= ETH_MACCR_TE; - } - else - { - /* Disable the MAC transmission */ - ETH->MACCR &= ~ETH_MACCR_TE; - } + if (NewState != DISABLE) + { + /* Enable the MAC transmission */ + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + /* Disable the MAC transmission */ + ETH->MACCR &= ~ETH_MACCR_TE; + } } /** @@ -787,19 +789,19 @@ void ETH_MACTransmissionCmd(FunctionalState NewState) */ void ETH_MACReceptionCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the MAC reception */ - ETH->MACCR |= ETH_MACCR_RE; - } - else - { - /* Disable the MAC reception */ - ETH->MACCR &= ~ETH_MACCR_RE; - } + if (NewState != DISABLE) + { + /* Enable the MAC reception */ + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + /* Disable the MAC reception */ + ETH->MACCR &= ~ETH_MACCR_RE; + } } /** @@ -809,17 +811,17 @@ void ETH_MACReceptionCmd(FunctionalState NewState) */ FlagStatus ETH_GetFlowControlBusyStatus(void) { - FlagStatus bitstatus = RESET; - /* The Flow Control register should not be written to until this bit is cleared */ - if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + FlagStatus bitstatus = RESET; + /* The Flow Control register should not be written to until this bit is cleared */ + if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -829,8 +831,8 @@ FlagStatus ETH_GetFlowControlBusyStatus(void) */ void ETH_InitiatePauseControlFrame(void) { - /* When Set In full duplex MAC initiates pause control frame */ - ETH->MACFCR |= ETH_MACFCR_FCBBPA; + /* When Set In full duplex MAC initiates pause control frame */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; } /** @@ -841,21 +843,21 @@ void ETH_InitiatePauseControlFrame(void) */ void ETH_BackPressureActivationCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Activate the MAC BackPressure operation */ - /* In Half duplex: during backpressure, when the MAC receives a new frame, - the transmitter starts sending a JAM pattern resulting in a collision */ - ETH->MACFCR |= ETH_MACFCR_FCBBPA; - } - else - { - /* Desactivate the MAC BackPressure operation */ - ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; - } + if (NewState != DISABLE) + { + /* Activate the MAC BackPressure operation */ + /* In Half duplex: during backpressure, when the MAC receives a new frame, + the transmitter starts sending a JAM pattern resulting in a collision */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + /* Desactivate the MAC BackPressure operation */ + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } } /** @@ -871,18 +873,18 @@ void ETH_BackPressureActivationCmd(FunctionalState NewState) */ FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) { - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); - if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); + if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -898,18 +900,18 @@ FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) */ ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) { - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); - if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); + if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -925,20 +927,20 @@ ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) */ void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_ETH_MAC_IT(ETH_MAC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_ETH_MAC_IT(ETH_MAC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ETHERNET MAC interrupts */ - ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); - } - else - { - /* Disable the selected ETHERNET MAC interrupts */ - ETH->MACIMR |= ETH_MAC_IT; - } + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC interrupts */ + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + /* Disable the selected ETHERNET MAC interrupts */ + ETH->MACIMR |= ETH_MAC_IT; + } } /** @@ -954,19 +956,19 @@ void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) */ void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) { - uint32_t tmpreg; - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - /* Calculate the selectecd MAC address high register */ - tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; - /* Load the selectecd MAC address high register */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; - /* Calculate the selectecd MAC address low register */ - tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + /* Calculate the selectecd MAC address high register */ + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + /* Load the selectecd MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; + /* Calculate the selectecd MAC address low register */ + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; - /* Load the selectecd MAC address low register */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; + /* Load the selectecd MAC address low register */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; } /** @@ -982,23 +984,23 @@ void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) */ void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) { - uint32_t tmpreg; - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - /* Get the selectecd MAC address high register */ - tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)); + /* Get the selectecd MAC address high register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)); - /* Calculate the selectecd MAC address buffer */ - Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); - Addr[4] = (tmpreg & (uint8_t)0xFF); - /* Load the selectecd MAC address low register */ - tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)); - /* Calculate the selectecd MAC address buffer */ - Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); - Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); - Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF); - Addr[0] = (tmpreg & (uint8_t)0xFF); + /* Calculate the selectecd MAC address buffer */ + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + /* Load the selectecd MAC address low register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)); + /* Calculate the selectecd MAC address buffer */ + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); } /** @@ -1015,20 +1017,20 @@ void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) */ void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ETHERNET MAC address for perfect filtering */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; - } - else - { - /* Disable the selected ETHERNET MAC address for perfect filtering */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE); - } + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + /* Disable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE); + } } /** @@ -1048,22 +1050,22 @@ void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) */ void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) { - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); - assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter)); + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter)); - if (Filter != ETH_MAC_AddressFilter_DA) - { - /* The selected ETHERNET MAC address is used to compare with the SA fields of the - received frame. */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; - } - else - { - /* The selected ETHERNET MAC address is used to compare with the DA fields of the - received frame. */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA); - } + if (Filter != ETH_MAC_AddressFilter_DA) + { + /* The selected ETHERNET MAC address is used to compare with the SA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + /* The selected ETHERNET MAC address is used to compare with the DA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA); + } } /** @@ -1085,14 +1087,14 @@ void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) */ void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) { - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); - assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); - /* Clear MBC bits in the selected MAC address high register */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); - /* Set the selected Filetr mask bytes */ - (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; + /* Clear MBC bits in the selected MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); + /* Set the selected Filetr mask bytes */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; } /*------------------------ DMA Tx/Rx Desciptors -----------------------------*/ @@ -1105,37 +1107,37 @@ void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) */ void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) { - uint32_t i = 0; - ETH_DMADESCTypeDef *DMATxDesc; + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; - /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ - DMATxDescToSet = DMATxDescTab; - /* Fill each DMATxDesc descriptor with the right values */ - for(i=0; i < TxBuffCount; i++) - { - /* Get the pointer on the ith member of the Tx Desc list */ - DMATxDesc = DMATxDescTab + i; - /* Set Second Address Chained bit */ - DMATxDesc->Status = ETH_DMATxDesc_TCH; + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Second Address Chained bit */ + DMATxDesc->Status = ETH_DMATxDesc_TCH; - /* Set Buffer1 address pointer */ - DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); - /* Initialize the next descriptor with the Next Desciptor Polling Enable */ - if(i < (TxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } } - } - /* Set Transmit Desciptor List Address Register */ - ETH->DMATDLAR = (uint32_t) DMATxDescTab; + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; } /** @@ -1150,33 +1152,33 @@ void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, u */ void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) { - uint32_t i = 0; - ETH_DMADESCTypeDef *DMATxDesc; + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; - /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ - DMATxDescToSet = DMATxDescTab; - /* Fill each DMATxDesc descriptor with the right values */ - for(i=0; i < TxBuffCount; i++) - { - /* Get the pointer on the ith member of the Tx Desc list */ - DMATxDesc = DMATxDescTab + i; - /* Set Buffer1 address pointer */ - DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]); + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]); - /* Set Buffer2 address pointer */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]); + /* Set Buffer2 address pointer */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]); - /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base - address of the list, creating a Desciptor Ring */ - if(i == (TxBuffCount-1)) - { - /* Set Transmit End of Ring bit */ - DMATxDesc->Status = ETH_DMATxDesc_TER; + /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (TxBuffCount-1)) + { + /* Set Transmit End of Ring bit */ + DMATxDesc->Status = ETH_DMATxDesc_TER; + } } - } - /* Set Transmit Desciptor List Address Register */ - ETH->DMATDLAR = (uint32_t) DMATxDescTab; + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; } /** @@ -1212,19 +1214,19 @@ void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, u */ FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) { - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag)); + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag)); - if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -1234,8 +1236,8 @@ FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ET */ uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) { - /* Return the Receive descriptor frame length */ - return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); + /* Return the Receive descriptor frame length */ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); } /** @@ -1245,8 +1247,8 @@ uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) */ void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) { - /* Set the DMA Tx Desc Own bit */ - DMATxDesc->Status |= ETH_DMATxDesc_OWN; + /* Set the DMA Tx Desc Own bit */ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; } /** @@ -1258,19 +1260,19 @@ void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) */ void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DMA Tx Desc Transmit interrupt */ - DMATxDesc->Status |= ETH_DMATxDesc_IC; - } - else - { - /* Disable the DMA Tx Desc Transmit interrupt */ - DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC); - } + if (NewState != DISABLE) + { + /* Enable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + /* Disable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC); + } } /** @@ -1284,11 +1286,11 @@ void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalStat */ void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) { - /* Check the parameters */ - assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment)); + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment)); - /* Selects the DMA Tx Desc Frame segment */ - DMATxDesc->Status |= DMATxDesc_FrameSegment; + /* Selects the DMA Tx Desc Frame segment */ + DMATxDesc->Status |= DMATxDesc_FrameSegment; } /** @@ -1304,11 +1306,11 @@ void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMA */ void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) { - /* Check the parameters */ - assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum)); + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum)); - /* Set the selected DMA Tx desc checksum insertion control */ - DMATxDesc->Status |= DMATxDesc_Checksum; + /* Set the selected DMA Tx desc checksum insertion control */ + DMATxDesc->Status |= DMATxDesc_Checksum; } /** @@ -1320,19 +1322,19 @@ void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_ */ void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA Tx Desc CRC */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); - } - else - { - /* Disable the selected DMA Tx Desc CRC */ - DMATxDesc->Status |= ETH_DMATxDesc_DC; - } + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc CRC */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + /* Disable the selected DMA Tx Desc CRC */ + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } } /** @@ -1344,19 +1346,19 @@ void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState */ void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA Tx Desc end of ring */ - DMATxDesc->Status |= ETH_DMATxDesc_TER; - } - else - { - /* Disable the selected DMA Tx Desc end of ring */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); - } + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + /* Disable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } } /** @@ -1368,19 +1370,19 @@ void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState Ne */ void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA Tx Desc second address chained */ - DMATxDesc->Status |= ETH_DMATxDesc_TCH; - } - else - { - /* Disable the selected DMA Tx Desc second address chained */ - DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); - } + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + /* Disable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); + } } /** @@ -1392,19 +1394,19 @@ void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, Functio */ void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); - } - else - { - /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ - DMATxDesc->Status |= ETH_DMATxDesc_DP; - } + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } } /** @@ -1416,19 +1418,19 @@ void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, Functional */ void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA Tx Desc time stamp */ - DMATxDesc->Status |= ETH_DMATxDesc_TTSE; - } - else - { - /* Disable the selected DMA Tx Desc time stamp */ - DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); - } + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + /* Disable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); + } } /** @@ -1440,12 +1442,12 @@ void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState Ne */ void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) { - /* Check the parameters */ - assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1)); - assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1)); + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); - /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ - DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); + /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); } /** @@ -1457,39 +1459,39 @@ void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t Buffe */ void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) { - uint32_t i = 0; - ETH_DMADESCTypeDef *DMARxDesc; + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; - /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ - DMARxDescToGet = DMARxDescTab; - /* Fill each DMARxDesc descriptor with the right values */ - for(i=0; i < RxBuffCount; i++) - { - /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; - /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = ETH_DMARxDesc_OWN; - - /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; - /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); - - /* Initialize the next descriptor with the Next Desciptor Polling Enable */ - if(i < (RxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); - } - else + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } } - } - /* Set Receive Desciptor List Address Register */ - ETH->DMARDLAR = (uint32_t) DMARxDescTab; + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; } /** @@ -1504,36 +1506,36 @@ void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, u */ void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) { - uint32_t i = 0; - ETH_DMADESCTypeDef *DMARxDesc; - /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ - DMARxDescToGet = DMARxDescTab; - /* Fill each DMARxDesc descriptor with the right values */ - for(i=0; i < RxBuffCount; i++) - { - /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; - /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = ETH_DMARxDesc_OWN; - /* Set Buffer1 size */ - DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; - /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); - - /* Set Buffer2 address pointer */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); - - /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base - address of the list, creating a Desciptor Ring */ - if(i == (RxBuffCount-1)) + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) { - /* Set Receive End of Ring bit */ - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + /* Set Buffer1 size */ + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (RxBuffCount-1)) + { + /* Set Receive End of Ring bit */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } } - } - /* Set Receive Desciptor List Address Register */ - ETH->DMARDLAR = (uint32_t) DMARxDescTab; + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; } /** @@ -1563,18 +1565,18 @@ void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, u */ FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) { - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag)); - if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag)); + if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -1584,8 +1586,8 @@ FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ET */ void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) { - /* Set the DMA Rx Desc Own bit */ - DMARxDesc->Status |= ETH_DMARxDesc_OWN; + /* Set the DMA Rx Desc Own bit */ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; } /** @@ -1595,8 +1597,8 @@ void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) */ uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) { - /* Return the Receive descriptor frame length */ - return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); + /* Return the Receive descriptor frame length */ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); } /** @@ -1608,19 +1610,19 @@ uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) */ void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DMA Rx Desc receive interrupt */ - DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC); - } - else - { - /* Disable the DMA Rx Desc receive interrupt */ - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; - } + if (NewState != DISABLE) + { + /* Enable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + /* Disable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } } /** @@ -1632,19 +1634,19 @@ void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState */ void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA Rx Desc end of ring */ - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; - } - else - { - /* Disable the selected DMA Rx Desc end of ring */ - DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); - } + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + /* Disable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); + } } /** @@ -1656,19 +1658,19 @@ void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState Ne */ void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA Rx Desc second address chained */ - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; - } - else - { - /* Disable the selected DMA Rx Desc second address chained */ - DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); - } + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + /* Disable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); + } } /** @@ -1682,19 +1684,19 @@ void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, Functio */ uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) { - /* Check the parameters */ - assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); + /* Check the parameters */ + assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); - if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) - { - /* Return the DMA Rx Desc buffer2 size */ - return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); - } - else - { - /* Return the DMA Rx Desc buffer1 size */ - return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); - } + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + /* Return the DMA Rx Desc buffer2 size */ + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); + } + else + { + /* Return the DMA Rx Desc buffer1 size */ + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } } /*--------------------------------- DMA ------------------------------------*/ @@ -1705,9 +1707,9 @@ uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMAR */ void ETH_SoftwareReset(void) { - /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ - /* After reset all the registers holds their respective reset values */ - ETH->DMABMR |= ETH_DMABMR_SR; + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + ETH->DMABMR |= ETH_DMABMR_SR; } /** @@ -1717,16 +1719,16 @@ void ETH_SoftwareReset(void) */ FlagStatus ETH_GetSoftwareResetStatus(void) { - FlagStatus bitstatus = RESET; - if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -1758,18 +1760,18 @@ FlagStatus ETH_GetSoftwareResetStatus(void) */ FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) { - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG)); - if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG)); + if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -1795,11 +1797,11 @@ FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) */ void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) { - /* Check the parameters */ - assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); + /* Check the parameters */ + assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); - /* Clear the selected ETHERNET DMA FLAG */ - ETH->DMASR = (uint32_t) ETH_DMA_FLAG; + /* Clear the selected ETHERNET DMA FLAG */ + ETH->DMASR = (uint32_t) ETH_DMA_FLAG; } /** @@ -1828,18 +1830,18 @@ void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) */ ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) { - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT)); - if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT)); + if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -1865,11 +1867,11 @@ ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) */ void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) { - /* Check the parameters */ - assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); - /* Clear the selected ETHERNET DMA IT */ - ETH->DMASR = (uint32_t) ETH_DMA_IT; + /* Clear the selected ETHERNET DMA IT */ + ETH->DMASR = (uint32_t) ETH_DMA_IT; } /** @@ -1886,7 +1888,7 @@ void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) */ uint32_t ETH_GetTransmitProcessState(void) { - return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); } /** @@ -1903,7 +1905,7 @@ uint32_t ETH_GetTransmitProcessState(void) */ uint32_t ETH_GetReceiveProcessState(void) { - return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); } /** @@ -1913,8 +1915,8 @@ uint32_t ETH_GetReceiveProcessState(void) */ void ETH_FlushTransmitFIFO(void) { - /* Set the Flush Transmit FIFO bit */ - ETH->DMAOMR |= ETH_DMAOMR_FTF; + /* Set the Flush Transmit FIFO bit */ + ETH->DMAOMR |= ETH_DMAOMR_FTF; } /** @@ -1924,16 +1926,16 @@ void ETH_FlushTransmitFIFO(void) */ FlagStatus ETH_GetFlushTransmitFIFOStatus(void) { - FlagStatus bitstatus = RESET; - if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + FlagStatus bitstatus = RESET; + if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -1944,19 +1946,19 @@ FlagStatus ETH_GetFlushTransmitFIFOStatus(void) */ void ETH_DMATransmissionCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DMA transmission */ - ETH->DMAOMR |= ETH_DMAOMR_ST; - } - else - { - /* Disable the DMA transmission */ - ETH->DMAOMR &= ~ETH_DMAOMR_ST; - } + if (NewState != DISABLE) + { + /* Enable the DMA transmission */ + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + /* Disable the DMA transmission */ + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } } /** @@ -1967,19 +1969,19 @@ void ETH_DMATransmissionCmd(FunctionalState NewState) */ void ETH_DMAReceptionCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DMA reception */ - ETH->DMAOMR |= ETH_DMAOMR_SR; - } - else - { - /* Disable the DMA reception */ - ETH->DMAOMR &= ~ETH_DMAOMR_SR; - } + if (NewState != DISABLE) + { + /* Enable the DMA reception */ + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + /* Disable the DMA reception */ + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } } /** @@ -2008,20 +2010,20 @@ void ETH_DMAReceptionCmd(FunctionalState NewState) */ void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ETHERNET DMA interrupts */ - ETH->DMAIER |= ETH_DMA_IT; - } - else - { - /* Disable the selected ETHERNET DMA interrupts */ - ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT); - } + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET DMA interrupts */ + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + /* Disable the selected ETHERNET DMA interrupts */ + ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT); + } } /** @@ -2034,19 +2036,19 @@ void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) */ FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) { - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); - if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -2056,7 +2058,7 @@ FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) */ uint32_t ETH_GetRxOverflowMissedFrameCounter(void) { - return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); } /** @@ -2066,7 +2068,7 @@ uint32_t ETH_GetRxOverflowMissedFrameCounter(void) */ uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) { - return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); } /** @@ -2076,7 +2078,7 @@ uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) */ uint32_t ETH_GetCurrentTxDescStartAddress(void) { - return ((uint32_t)(ETH->DMACHTDR)); + return ((uint32_t)(ETH->DMACHTDR)); } /** @@ -2086,7 +2088,7 @@ uint32_t ETH_GetCurrentTxDescStartAddress(void) */ uint32_t ETH_GetCurrentRxDescStartAddress(void) { - return ((uint32_t)(ETH->DMACHRDR)); + return ((uint32_t)(ETH->DMACHRDR)); } /** @@ -2096,7 +2098,7 @@ uint32_t ETH_GetCurrentRxDescStartAddress(void) */ uint32_t ETH_GetCurrentTxBufferAddress(void) { - return ((uint32_t)(ETH->DMACHTBAR)); + return ((uint32_t)(ETH->DMACHTBAR)); } /** @@ -2106,7 +2108,7 @@ uint32_t ETH_GetCurrentTxBufferAddress(void) */ uint32_t ETH_GetCurrentRxBufferAddress(void) { - return ((uint32_t)(ETH->DMACHRBAR)); + return ((uint32_t)(ETH->DMACHRBAR)); } /** @@ -2117,7 +2119,7 @@ uint32_t ETH_GetCurrentRxBufferAddress(void) */ void ETH_ResumeDMATransmission(void) { - ETH->DMATPDR = 0; + ETH->DMATPDR = 0; } /** @@ -2128,7 +2130,7 @@ void ETH_ResumeDMATransmission(void) */ void ETH_ResumeDMAReception(void) { - ETH->DMARPDR = 0; + ETH->DMARPDR = 0; } /*--------------------------------- PMT ------------------------------------*/ @@ -2139,8 +2141,8 @@ void ETH_ResumeDMAReception(void) */ void ETH_ResetWakeUpFrameFilterRegisterPointer(void) { - /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; + /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; } /** @@ -2150,14 +2152,14 @@ void ETH_ResetWakeUpFrameFilterRegisterPointer(void) */ void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) { - uint32_t i = 0; + uint32_t i = 0; - /* Fill Remote Wake-up Frame Filter register with Buffer data */ - for(i =0; iMACRWUFFR = Buffer[i]; - } + /* Fill Remote Wake-up Frame Filter register with Buffer data */ + for(i =0; iMACRWUFFR = Buffer[i]; + } } /** @@ -2169,19 +2171,19 @@ void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) */ void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the MAC Global Unicast Wake-Up */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; - } - else - { - /* Disable the MAC Global Unicast Wake-Up */ - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; - } + if (NewState != DISABLE) + { + /* Enable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + /* Disable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } } /** @@ -2195,19 +2197,19 @@ void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) */ FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) { - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); - if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -2218,19 +2220,19 @@ FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) */ void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the MAC Wake-Up Frame Detection */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; - } - else - { - /* Disable the MAC Wake-Up Frame Detection */ - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; - } + if (NewState != DISABLE) + { + /* Enable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + /* Disable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } } /** @@ -2241,19 +2243,19 @@ void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) */ void ETH_MagicPacketDetectionCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the MAC Magic Packet Detection */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; - } - else - { - /* Disable the MAC Magic Packet Detection */ - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; - } + if (NewState != DISABLE) + { + /* Enable the MAC Magic Packet Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + /* Disable the MAC Magic Packet Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } } /** @@ -2264,20 +2266,20 @@ void ETH_MagicPacketDetectionCmd(FunctionalState NewState) */ void ETH_PowerDownCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the MAC Power Down */ - /* This puts the MAC in power down mode */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; - } - else - { - /* Disable the MAC Power Down */ - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; - } + if (NewState != DISABLE) + { + /* Enable the MAC Power Down */ + /* This puts the MAC in power down mode */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + /* Disable the MAC Power Down */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } } /*--------------------------------- MMC ------------------------------------*/ @@ -2289,19 +2291,19 @@ void ETH_PowerDownCmd(FunctionalState NewState) */ void ETH_MMCCounterFreezeCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the MMC Counter Freeze */ - ETH->MMCCR |= ETH_MMCCR_MCF; - } - else - { - /* Disable the MMC Counter Freeze */ - ETH->MMCCR &= ~ETH_MMCCR_MCF; - } + if (NewState != DISABLE) + { + /* Enable the MMC Counter Freeze */ + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + /* Disable the MMC Counter Freeze */ + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } } /** @@ -2312,19 +2314,19 @@ void ETH_MMCCounterFreezeCmd(FunctionalState NewState) */ void ETH_MMCResetOnReadCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the MMC Counter reset on read */ - ETH->MMCCR |= ETH_MMCCR_ROR; - } - else - { - /* Disable the MMC Counter reset on read */ - ETH->MMCCR &= ~ETH_MMCCR_ROR; - } + if (NewState != DISABLE) + { + /* Enable the MMC Counter reset on read */ + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + /* Disable the MMC Counter reset on read */ + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } } /** @@ -2335,19 +2337,19 @@ void ETH_MMCResetOnReadCmd(FunctionalState NewState) */ void ETH_MMCCounterRolloverCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Disable the MMC Counter Stop Rollover */ - ETH->MMCCR &= ~ETH_MMCCR_CSR; - } - else - { - /* Enable the MMC Counter Stop Rollover */ - ETH->MMCCR |= ETH_MMCCR_CSR; - } + if (NewState != DISABLE) + { + /* Disable the MMC Counter Stop Rollover */ + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + /* Enable the MMC Counter Stop Rollover */ + ETH->MMCCR |= ETH_MMCCR_CSR; + } } /** @@ -2357,8 +2359,8 @@ void ETH_MMCCounterRolloverCmd(FunctionalState NewState) */ void ETH_MMCCountersReset(void) { - /* Resets the MMC Counters */ - ETH->MMCCR |= ETH_MMCCR_CR; + /* Resets the MMC Counters */ + ETH->MMCCR |= ETH_MMCCR_CR; } /** @@ -2378,41 +2380,41 @@ void ETH_MMCCountersReset(void) */ void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) - { - /* Remove egister mak from IT */ - ETH_MMC_IT &= 0xEFFFFFFF; - - /* ETHERNET MMC Rx interrupts selected */ - if (NewState != DISABLE) - { - /* Enable the selected ETHERNET MMC interrupts */ - ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT); - } - else - { - /* Disable the selected ETHERNET MMC interrupts */ - ETH->MMCRIMR |= ETH_MMC_IT; - } - } - else - { - /* ETHERNET MMC Tx interrupts selected */ - if (NewState != DISABLE) + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) { - /* Enable the selected ETHERNET MMC interrupts */ - ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT); + /* Remove egister mak from IT */ + ETH_MMC_IT &= 0xEFFFFFFF; + + /* ETHERNET MMC Rx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR |= ETH_MMC_IT; + } } else { - /* Disable the selected ETHERNET MMC interrupts */ - ETH->MMCTIMR |= ETH_MMC_IT; + /* ETHERNET MMC Tx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR |= ETH_MMC_IT; + } } - } } /** @@ -2429,38 +2431,38 @@ void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) */ ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) { - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); - if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) - { - /* ETHERNET MMC Rx interrupts selected */ - /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ - if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) { - bitstatus = RESET; - } - } - else - { - /* ETHERNET MMC Tx interrupts selected */ - /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ - if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) - { - bitstatus = SET; + /* ETHERNET MMC Rx interrupts selected */ + /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ + if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } } else { - bitstatus = RESET; + /* ETHERNET MMC Tx interrupts selected */ + /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ + if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } } - } - return bitstatus; + return bitstatus; } /** @@ -2482,11 +2484,11 @@ ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) */ uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) { - /* Check the parameters */ - assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); + /* Check the parameters */ + assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); - /* Return the selected register value */ - return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); } /*--------------------------------- PTP ------------------------------------*/ @@ -2497,8 +2499,8 @@ uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) */ void ETH_EnablePTPTimeStampAddend(void) { - /* Enable the PTP block update with the Time Stamp Addend register value */ - ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; + /* Enable the PTP block update with the Time Stamp Addend register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; } /** @@ -2508,8 +2510,8 @@ void ETH_EnablePTPTimeStampAddend(void) */ void ETH_EnablePTPTimeStampInterruptTrigger(void) { - /* Enable the PTP target time interrupt */ - ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; + /* Enable the PTP target time interrupt */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; } /** @@ -2519,8 +2521,8 @@ void ETH_EnablePTPTimeStampInterruptTrigger(void) */ void ETH_EnablePTPTimeStampUpdate(void) { - /* Enable the PTP system time update with the Time Stamp Update register value */ - ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; + /* Enable the PTP system time update with the Time Stamp Update register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; } /** @@ -2530,8 +2532,8 @@ void ETH_EnablePTPTimeStampUpdate(void) */ void ETH_InitializePTPTimeStamp(void) { - /* Initialize the PTP Time Stamp */ - ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; + /* Initialize the PTP Time Stamp */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; } /** @@ -2544,19 +2546,19 @@ void ETH_InitializePTPTimeStamp(void) */ void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) { - /* Check the parameters */ - assert_param(IS_ETH_PTP_UPDATE(UpdateMethod)); + /* Check the parameters */ + assert_param(IS_ETH_PTP_UPDATE(UpdateMethod)); - if (UpdateMethod != ETH_PTP_CoarseUpdate) - { - /* Enable the PTP Fine Update method */ - ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; - } - else - { - /* Disable the PTP Coarse Update method */ - ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); - } + if (UpdateMethod != ETH_PTP_CoarseUpdate) + { + /* Enable the PTP Fine Update method */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + /* Disable the PTP Coarse Update method */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } } /** @@ -2567,19 +2569,19 @@ void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) */ void ETH_PTPTimeStampCmd(FunctionalState NewState) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the PTP time stamp for transmit and receive frames */ - ETH->PTPTSCR |= ETH_PTPTSCR_TSE; - } - else - { - /* Disable the PTP time stamp for transmit and receive frames */ - ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); - } + if (NewState != DISABLE) + { + /* Enable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + /* Disable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } } /** @@ -2594,19 +2596,19 @@ void ETH_PTPTimeStampCmd(FunctionalState NewState) */ FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) { - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG)); + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG)); - if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; } /** @@ -2616,10 +2618,10 @@ FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) */ void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) { - /* Check the parameters */ - assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue)); - /* Set the PTP Sub-Second Increment Register */ - ETH->PTPSSIR = SubSecondValue; + /* Check the parameters */ + assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue)); + /* Set the PTP Sub-Second Increment Register */ + ETH->PTPSSIR = SubSecondValue; } /** @@ -2635,14 +2637,14 @@ void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) */ void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) { - /* Check the parameters */ - assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); - assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); - /* Set the PTP Time Update High Register */ - ETH->PTPTSHUR = SecondValue; + /* Check the parameters */ + assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); + assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); + /* Set the PTP Time Update High Register */ + ETH->PTPTSHUR = SecondValue; - /* Set the PTP Time Update Low Register with sign */ - ETH->PTPTSLUR = Sign | SubSecondValue; + /* Set the PTP Time Update Low Register with sign */ + ETH->PTPTSLUR = Sign | SubSecondValue; } /** @@ -2652,8 +2654,8 @@ void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t Sub */ void ETH_SetPTPTimeStampAddend(uint32_t Value) { - /* Set the PTP Time Stamp Addend Register */ - ETH->PTPTSAR = Value; + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; } /** @@ -2664,10 +2666,10 @@ void ETH_SetPTPTimeStampAddend(uint32_t Value) */ void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) { - /* Set the PTP Target Time High Register */ - ETH->PTPTTHR = HighValue; - /* Set the PTP Target Time Low Register */ - ETH->PTPTTLR = LowValue; + /* Set the PTP Target Time High Register */ + ETH->PTPTTHR = HighValue; + /* Set the PTP Target Time Low Register */ + ETH->PTPTTLR = LowValue; } /** @@ -2687,11 +2689,11 @@ void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) */ uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) { - /* Check the parameters */ - assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg)); + /* Check the parameters */ + assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg)); - /* Return the selected register value */ - return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); } /** @@ -2705,43 +2707,43 @@ uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) { - uint32_t i = 0; - ETH_DMADESCTypeDef *DMATxDesc; + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; - /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ - DMATxDescToSet = DMATxDescTab; - DMAPTPTxDescToSet = DMAPTPTxDescTab; - /* Fill each DMATxDesc descriptor with the right values */ - for(i=0; i < TxBuffCount; i++) - { - /* Get the pointer on the ith member of the Tx Desc list */ - DMATxDesc = DMATxDescTab+i; - /* Set Second Address Chained bit and enable PTP */ - DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab+i; + /* Set Second Address Chained bit and enable PTP */ + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; - /* Set Buffer1 address pointer */ - DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); - /* Initialize the next descriptor with the Next Desciptor Polling Enable */ - if(i < (TxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */ + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; } - /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */ - (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; - (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; - } - /* Store on the last DMAPTPTxDescTab desc status record the first list address */ - (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab; + /* Store on the last DMAPTPTxDescTab desc status record the first list address */ + (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab; - /* Set Transmit Desciptor List Address Register */ - ETH->DMATDLAR = (uint32_t) DMATxDescTab; + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; } /** @@ -2755,45 +2757,45 @@ void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCType void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) { - uint32_t i = 0; - ETH_DMADESCTypeDef *DMARxDesc; - - /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ - DMARxDescToGet = DMARxDescTab; - DMAPTPRxDescToGet = DMAPTPRxDescTab; - /* Fill each DMARxDesc descriptor with the right values */ - for(i=0; i < RxBuffCount; i++) - { - /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; - /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = ETH_DMARxDesc_OWN; - - /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; - /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; - /* Initialize the next descriptor with the Next Desciptor Polling Enable */ - if(i < (RxBuffCount-1)) + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) { - /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */ + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; } - /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */ - (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; - (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; - } - /* Store on the last DMAPTPRxDescTab desc status record the first list address */ - (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab; + /* Store on the last DMAPTPRxDescTab desc status record the first list address */ + (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab; - /* Set Receive Desciptor List Address Register */ - ETH->DMARDLAR = (uint32_t) DMARxDescTab; + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; } /** @@ -2806,79 +2808,80 @@ void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCType */ uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) { - uint32_t offset = 0, timeout = 0; - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) - { - /* Return ERROR: OWN bit set */ - return ETH_ERROR; - } - /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ - for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); - } - /* Setting the Frame Length: bits[12:0] */ - DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); - /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ - DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - ETH->DMASR = ETH_DMASR_TBUS; - /* Resume DMA transmission*/ - ETH->DMATPDR = 0; - } - /* Wait for ETH_DMATxDesc_TTSS flag to be set */ - do - { - timeout++; - } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); - /* Return ERROR in case of timeout */ - if(timeout == PHY_READ_TO) - { - return ETH_ERROR; - } - /* Clear the DMATxDescToSet status register TTSS flag */ - DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; - *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; - *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; - /* Update the ENET DMA current descriptor */ - /* Chained Mode */ - if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) - { - /* Selects the next DMA Tx descriptor list for next buffer read */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr); - if(DMAPTPTxDescToSet->Status != 0) - { - DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status); + uint32_t offset = 0, timeout = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; } - else + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + /* Wait for ETH_DMATxDesc_TTSS flag to be set */ + do { - DMAPTPTxDescToSet++; + timeout++; } - } - else /* Ring Mode */ - { - if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) { - /* Selects the next DMA Tx descriptor list for next buffer read: this will - be the first Tx descriptor in this case */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); - DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + return ETH_ERROR; } - else + /* Clear the DMATxDescToSet status register TTSS flag */ + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + /* Update the ENET DMA current descriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr); + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else /* Ring Mode */ { - /* Selects the next DMA Tx descriptor list for next buffer read */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read: this will + be the first Tx descriptor in this case */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } } - } - /* Return SUCCESS */ - return ETH_SUCCESS; + /* Return SUCCESS */ + return ETH_SUCCESS; } /** @@ -2890,72 +2893,72 @@ uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTx */ uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) { - uint32_t offset = 0, framelength = 0; - /* Check if the descriptor is owned by the ENET or CPU */ - if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) - { - /* Return error: OWN bit set */ - return ETH_ERROR; - } - if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) - { - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ - for(offset=0; offsetBuffer1Addr) + offset)); - } - } - else - { - /* Return ERROR */ - framelength = ETH_ERROR; - } - /* When Rx Buffer unavailable flag is set: clear it and resume reception */ - if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) - { - /* Clear RBUS ETHERNET DMA flag */ - ETH->DMASR = ETH_DMASR_RBUS; - /* Resume DMA reception */ - ETH->DMARPDR = 0; - } - *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; - *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; - /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; - /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ - /* Chained Mode */ - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - { - /* Selects the next DMA Rx descriptor list for next buffer read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr); - if(DMAPTPRxDescToGet->Status != 0) - { - DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status); + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ENET or CPU */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } } else { - DMAPTPRxDescToGet++; + /* Return ERROR */ + framelength = ETH_ERROR; } - } - else /* Ring Mode */ - { - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) { - /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; } - else + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr); + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else /* Ring Mode */ { - /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } } - } - /* Return Frame Length/ERROR */ - return (framelength); + /* Return Frame Length/ERROR */ + return (framelength); } /** @@ -2983,7 +2986,32 @@ uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) #define STM32_ETH_TRACE rt_kprintf #else #define STM32_ETH_TRACE(...) -#endif +#endif /* ETH_DEBUG */ + +#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) +static void packet_dump(const char * msg, const struct pbuf* p) +{ + rt_uint32_t i; + rt_uint8_t *ptr = p->payload; + + STM32_ETH_TRACE("%s %d byte\n", msg, p->tot_len); + + for(i=0; itot_len; i++) + { + if( (i%8) == 0 ) + { + STM32_ETH_TRACE(" "); + } + if( (i%16) == 0 ) + { + STM32_ETH_TRACE("\r\n"); + } + STM32_ETH_TRACE("%02x ",*ptr); + ptr++; + } + STM32_ETH_TRACE("\n\n"); +} +#endif /* dump */ #define ETH_RXBUFNB 4 #define ETH_TXBUFNB 2 @@ -3011,8 +3039,8 @@ void ETH_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - /* get DMA IT status */ - status = ETH->DMASR; + /* get DMA IT status */ + status = ETH->DMASR; if ( (status & ETH_DMA_IT_R) != (u32)RESET ) /* packet receiption */ { @@ -3086,46 +3114,46 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; -#ifdef CHECKSUM_BY_HARDWARE +#if CHECKSUM_BY_HARDWARE ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; -#endif +#endif /* CHECKSUM_BY_HARDWARE */ - /*------------------------ DMA -----------------------------------*/ + /*------------------------ DMA -----------------------------------*/ - /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: - the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, - if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ - ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; - ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: + the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, + if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ + ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; + ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; - ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; - ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; - ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable; - ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; - ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; - ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; - ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; - ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1; + ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable; + ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; + ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; + ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; + ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1; - /* Configure ETHERNET */ - Value = ETH_Init(Ð_InitStructure); + /* Configure ETHERNET */ + Value = ETH_Init(Ð_InitStructure); - /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */ - ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE); + /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */ + ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE); - /* Initialize Tx Descriptors list: Chain Mode */ - ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); - /* Initialize Rx Descriptors list: Chain Mode */ - ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); + /* Initialize Tx Descriptors list: Chain Mode */ + ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); + /* Initialize Rx Descriptors list: Chain Mode */ + ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); - /* MAC address configuration */ - ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]); + /* MAC address configuration */ + ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]); - /* Enable MAC and DMA transmission and reception */ - ETH_Start(); + /* Enable MAC and DMA transmission and reception */ + ETH_Start(); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag) @@ -3175,7 +3203,7 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p) rt_uint32_t offset; /* get free tx buffer */ - { + { rt_err_t result; result = rt_sem_take(&tx_buf_free, 2); if (result != RT_EOK) return -RT_ERROR; @@ -3202,35 +3230,17 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p) } #ifdef ETH_TX_DUMP - { - rt_uint32_t i; - rt_uint8_t *ptr = (rt_uint8_t*)(DMATxDescToSet->Buffer1Addr); - - STM32_ETH_TRACE("tx_dump:"); - for(i=0; itot_len; i++) - { - if( (i%8) == 0 ) - { - STM32_ETH_TRACE(" "); - } - if( (i%16) == 0 ) - { - STM32_ETH_TRACE("\r\n"); - } - STM32_ETH_TRACE("%02x ",*ptr); - ptr++; - } - STM32_ETH_TRACE("\r\ndump done!\r\n"); - } + packet_dump("TX dump", p); #endif - /* Setting the Frame Length: bits[12:0] */ - DMATxDescToSet->ControlBufferSize = (p->tot_len & ETH_DMATxDesc_TBS1); - /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ - DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (p->tot_len & ETH_DMATxDesc_TBS1); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; /* Enable TX Completion Interrupt */ DMATxDescToSet->Status |= ETH_DMATxDesc_IC; -#ifdef CHECKSUM_BY_HARDWARE + +#if CHECKSUM_BY_HARDWARE DMATxDescToSet->Status |= ETH_DMATxDesc_ChecksumTCPUDPICMPFull; /* clean ICMP checksum STM32F need */ { @@ -3247,7 +3257,8 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p) } } } -#endif +#endif /* CHECKSUM_BY_HARDWARE */ + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ @@ -3272,7 +3283,7 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p) struct pbuf *rt_stm32_eth_rx(rt_device_t dev) { struct pbuf* p; - rt_uint32_t offset = 0, framelength = 0; + rt_uint32_t framelength = 0; /* init p pointer */ p = RT_NULL; @@ -3292,25 +3303,21 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM); if (p != RT_NULL) { - rt_uint8_t* ptr; + const char * from; struct pbuf* q; - rt_size_t len; + + from = (const char *)(DMARxDescToGet->Buffer1Addr); for (q = p; q != RT_NULL; q= q->next) { - ptr = q->payload; - len = q->len; - /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ - while (len) - { - *ptr = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset)); - - offset ++; - ptr ++; - len --; - } + memcpy(q->payload, from, q->len); + from += q->len; } + +#ifdef ETH_RX_DUMP + packet_dump("RX dump", p); +#endif /* ETH_RX_DUMP */ } } @@ -3356,9 +3363,9 @@ static void RCC_Configuration(void) RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | RCC_AHBPeriph_ETH_MAC_Tx | RCC_AHBPeriph_ETH_MAC_Rx, ENABLE); - /* Enable GPIOs clocks */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | - RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE| RCC_APB2Periph_AFIO, ENABLE); + /* Enable GPIOs clocks */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | + RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE| RCC_APB2Periph_AFIO, ENABLE); } static void NVIC_Configuration(void) @@ -3375,112 +3382,195 @@ static void NVIC_Configuration(void) /* * GPIO Configuration for ETH + AF Output Push Pull: + - ETH_MDC : PC1 + - ETH_MDIO : PA2 + - ETH_TX_EN : PB11 + - ETH_TXD0 : PB12 + - ETH_TXD1 : PB13 + - ETH_TXD2 : PC2 + - ETH_TXD3 : PB8 + - ETH_PPS_OUT / ETH_RMII_PPS_OUT: PB5 + + Input (Reset Value): + - ETH_MII_TX_CLK: PC3 + - ETH_MII_RX_CLK / ETH_RMII_REF_CLK: PA1 + - ETH_MII_CRS: PA0 + - ETH_MII_COL: PA3 + - ETH_MII_RX_DV / ETH_RMII_CRS_DV: PA7 + - ETH_MII_RXD0: PC4 + - ETH_MII_RXD1: PC5 + - ETH_MII_RXD2: PB0 + - ETH_MII_RXD3: PB1 + - ETH_MII_RX_ER: PB10 + + *************************************** + For Remapped Ethernet pins + ******************************************* + Input (Reset Value): + - ETH_MII_RX_DV / ETH_RMII_CRS_DV: PD8 + - ETH_MII_RXD0 / ETH_RMII_RXD0: PD9 + - ETH_MII_RXD1 / ETH_RMII_RXD1: PD10 + - ETH_MII_RXD2: PD11 + - ETH_MII_RXD3: PD12 */ static void GPIO_Configuration(void) { - GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + +#if STM32_ETH_IO_REMAP + /* ETHERNET pins remapp in STM3210C-EVAL board: RX_DV and RxD[3:0] */ + GPIO_PinRemapConfig(GPIO_Remap_ETH, ENABLE); +#endif /* STM32_ETH_IO_REMAP */ - /* ETHERNET pins remapp in STM3210C-EVAL board: RX_DV and RxD[3:0] */ - GPIO_PinRemapConfig(GPIO_Remap_ETH, ENABLE); + /* MII/RMII Media interface selection */ +#if (RMII_MODE == 0) /* Mode MII. */ + GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII); +#elif (RMII_MODE == 1) /* Mode RMII. */ + GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII); +#endif /* RMII_MODE */ - /* MII/RMII Media interface selection */ -#ifdef MII_MODE /* Mode MII with STM3210C-EVAL */ - GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII); + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - /* Get HSE clock = 25MHz on PA8 pin(MCO) */ - RCC_MCOConfig(RCC_MCO_HSE); + /* MDIO */ + { + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; -#elif defined RMII_MODE /* Mode RMII with STM3210C-EVAL */ - GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII); + /* MDC */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_Init(GPIOC, &GPIO_InitStructure); - /* Get HSE clock = 25MHz on PA8 pin(MCO) */ - /* set PLL3 clock output to 50MHz (25MHz /5 *10 =50MHz) */ - RCC_PLL3Config(RCC_PLL3Mul_10); - /* Enable PLL3 */ - RCC_PLL3Cmd(ENABLE); - /* Wait till PLL3 is ready */ - while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET) - {} + /* MDIO */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_Init(GPIOA, &GPIO_InitStructure); + } /* MDIO */ - /* Get clock PLL3 clock on PA8 pin */ - RCC_MCOConfig(RCC_MCO_PLL3CLK); -#endif + /* TXD */ + { + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + + /* TX_EN */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* TXD0 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* TXD1 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13; + GPIO_Init(GPIOB, &GPIO_InitStructure); - /* ETHERNET pins configuration */ - /* AF Output Push Pull: - - ETH_MII_MDIO / ETH_RMII_MDIO: PA2 - - ETH_MII_MDC / ETH_RMII_MDC: PC1 - - ETH_MII_TXD2: PC2 - - ETH_MII_TX_EN / ETH_RMII_TX_EN: PB11 - - ETH_MII_TXD0 / ETH_RMII_TXD0: PB12 - - ETH_MII_TXD1 / ETH_RMII_TXD1: PB13 - - ETH_MII_PPS_OUT / ETH_RMII_PPS_OUT: PB5 - - ETH_MII_TXD3: PB8 */ - - /* Configure PA2 as alternate function push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* Configure PC1, PC2 and PC3 as alternate function push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* Configure PB5, PB8, PB11, PB12 and PB13 as alternate function push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 | - GPIO_Pin_12 | GPIO_Pin_13; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - /**************************************************************/ - /* For Remapped Ethernet pins */ - /*************************************************************/ - /* Input (Reset Value): - - ETH_MII_CRS CRS: PA0 - - ETH_MII_RX_CLK / ETH_RMII_REF_CLK: PA1 - - ETH_MII_COL: PA3 - - ETH_MII_RX_DV / ETH_RMII_CRS_DV: PD8 - - ETH_MII_TX_CLK: PC3 - - ETH_MII_RXD0 / ETH_RMII_RXD0: PD9 - - ETH_MII_RXD1 / ETH_RMII_RXD1: PD10 - - ETH_MII_RXD2: PD11 - - ETH_MII_RXD3: PD12 - - ETH_MII_RX_ER: PB10 */ - - /* Configure PA0, PA1 and PA3 as input */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* Configure PB10 as input */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - /* Configure PC3 as input */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* Configure PD8, PD9, PD10, PD11 and PD12 as input */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOD, &GPIO_InitStructure); /**/ - - /* MCO pin configuration------------------------------------------------- */ - /* Configure MCO (PA8) as alternate function push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); +#if (RMII_MODE == 0) + /* TXD2 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* TXD3 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* TX_CLK */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; + GPIO_Init(GPIOC, &GPIO_InitStructure); +#endif /* RMII_MODE */ + } /* TXD */ + + /* RXD */ + { + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + +#if (STM32_ETH_IO_REMAP == 0) + /* RX_DV/CRS_DV */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* RXD0 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* RXD1 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_Init(GPIOC, &GPIO_InitStructure); + +#if (RMII_MODE == 0) + /* RXD2 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* RXD3 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_Init(GPIOB, &GPIO_InitStructure); +#endif /* RMII_MODE */ +#else + /* RX_DV/CRS_DV */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* RXD0 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* RXD1 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#if (RMII_MODE == 0) + /* RXD2 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* RXD3 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_Init(GPIOD, &GPIO_InitStructure); +#endif /* RMII_MODE */ +#endif /* STM32_ETH_IO_REMAP */ + +#if (RMII_MODE == 0) + /* CRS */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* COL */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* RX_CLK */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* RX_ER */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_Init(GPIOB, &GPIO_InitStructure); +#endif /* RMII_MODE */ + } /* RXD */ + +#if (USE_MCO == 1) +#if (RMII_MODE == 0) /* Mode MII. */ + /* Get HSE clock = 25MHz on PA8 pin(MCO) */ + RCC_MCOConfig(RCC_MCO_HSE); +#elif (RMII_MODE == 1) /* Mode RMII. */ + /* Get HSE clock = 25MHz on PA8 pin(MCO) */ + /* set PLL3 clock output to 50MHz (25MHz /5 *10 =50MHz) */ + RCC_PLL3Config(RCC_PLL3Mul_10); + /* Enable PLL3 */ + RCC_PLL3Cmd(ENABLE); + /* Wait till PLL3 is ready */ + while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET) + {} + + /* Get clock PLL3 clock on PA8 pin */ + RCC_MCOConfig(RCC_MCO_PLL3CLK); +#endif /* RMII_MODE */ + + /* MCO pin configuration------------------------------------------------- */ + /* Configure MCO (PA8) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); +#endif /* USE_MCO */ } void rt_hw_stm32_eth_init() @@ -3516,3 +3606,56 @@ void rt_hw_stm32_eth_init() eth_device_init(&(stm32_eth_device.parent), "e0"); } +#ifdef RT_USING_FINSH +#include +static void phy_search(void) +{ + int i; + int value; + + for(i=0; i<32; i++) + { + value = ETH_ReadPHYRegister(i, 2); + rt_kprintf("addr %02d: %04X\n", i, value); + } +} +FINSH_FUNCTION_EXPORT(phy_search, search phy use MDIO); + +static void phy_dump(int addr) +{ + int i; + int value; + + rt_kprintf("dump phy addr %d\n", addr); + + for(i=0; i<32; i++) + { + value = ETH_ReadPHYRegister(addr, i); + rt_kprintf("reg %02d: %04X\n", i, value); + } +} +FINSH_FUNCTION_EXPORT(phy_dump, dump PHY register); + +static void phy_write(int addr, int reg, int value) +{ + ETH_WritePHYRegister(addr, reg ,value); +} +FINSH_FUNCTION_EXPORT(phy_write, write PHY register); + +static void emac_dump(int addr) +{ + int i; + int value; + int *p = (int *)ETH; + + rt_kprintf("dump EAMC reg %d\n", addr); + + for(i=0; i