diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig index 01752dad9428b7b74af918f80b0d1db0549c2c86..decdf156d7787954ceb54263632c07c3d421e649 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig @@ -167,11 +167,16 @@ menu "On-chip Peripheral Drivers" default n endif - config BSP_USING_ONCHIP_RTC + menuconfig BSP_USING_ONCHIP_RTC bool "Enable RTC" select RT_USING_RTC select RT_USING_LIBC default n + if BSP_USING_ONCHIP_RTC + config RTC_USING_INTERNAL_CLK + bool "Using internal clock RTC" + default y + endif menuconfig BSP_USING_ADC bool "Enable ADC" diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py index b70a0dc654e965785938950ca8808da2cae6ff8a..0642f6429a3953b3d7080ad5776001c4fb370d33 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py +++ b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py @@ -41,7 +41,7 @@ if PLATFORM == 'gcc': # DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -fsingle-precision-constant' DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32' # CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields' - CFLAGS = DEVICE + CFLAGS = DEVICE + ' -D_USE_LONG_TIME_T' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' CPATH = '' diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c index 99483cb5442f21c6f06a8e8122f446bcb0096084..4f462e90406ad6503df78e12e36743ca0b2bd95a 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2021-01-28 greedyhao first version + * 2021-03-19 iysheng modify just set time first power up */ #include "board.h" @@ -95,30 +96,44 @@ uint8_t irtc_sfr_read(uint32_t cmd) IRTC_EXIT_CRITICAL(); } +static void _init_rtc_clock(void) +{ + uint8_t rtccon0; + uint8_t rtccon2; + + rtccon0 = irtc_sfr_read(RTCCON0_CMD); + rtccon2 = irtc_sfr_read(RTCCON2_CMD); +#ifdef RTC_USING_INTERNAL_CLK + rtccon0 &= ~RTC_CON0_XOSC32K_ENABLE; + rtccon0 |= RTC_CON0_INTERNAL_32K; + rtccon2 | RTC_CON2_32K_SELECT; +#else + rtccon0 |= RTC_CON0_XOSC32K_ENABLE; + rtccon0 &= ~RTC_CON0_INTERNAL_32K; + rtccon2 & ~RTC_CON2_32K_SELECT; +#endif + irtc_sfr_write(RTCCON0_CMD, rtccon0); + irtc_sfr_write(RTCCON2_CMD, rtccon2); +} + void hal_rtc_init(void) { time_t sec = 0; struct tm tm_new = {0}; + uint8_t temp; - uint8_t temp = irtc_sfr_read(RTCCON0_CMD); - temp &= ~RTC_CON0_XOSC32K_ENABLE; - temp |= RTC_CON0_EXTERNAL_32K; - irtc_sfr_write(RTCCON0_CMD, temp); - temp = irtc_sfr_read(RTCCON2_CMD); - irtc_sfr_write(RTCCON2_CMD, temp | RTC_CON2_32K_SELECT); - + _init_rtc_clock(); temp = irtc_sfr_read(RTCCON0_CMD); - if (temp & BIT(7)) { - temp &= ~BIT(7); + if (temp & RTC_CON0_PWRUP_FIRST) { + temp &= ~RTC_CON0_PWRUP_FIRST; irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */ - } + tm_new.tm_mday = 29; + tm_new.tm_mon = 1 - 1; + tm_new.tm_year = 2021 - 1900; + sec = timegm(&tm_new); - tm_new.tm_mday = 29; - tm_new.tm_mon = 1 - 1; - tm_new.tm_year = 2021 - 1900; - sec = timegm(&tm_new); - - irtc_time_write(RTCCNT_CMD, sec); + irtc_time_write(RTCCNT_CMD, sec); + } } /************** HAL End *******************/ diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h index 6c128567b59168a140f62788bf65b1cc7206cf06..483f3e3f42c1a439744f4fbbe7cb7896cd45f909 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h @@ -34,7 +34,7 @@ enum // RTCCON0 #define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */ -#define RTC_CON0_EXTERNAL_32K (0x01u << 6) /*!< External 32K select */ +#define RTC_CON0_INTERNAL_32K (0x01u << 6) /*!< Internal 32K select */ #define RTC_CON0_VDD_ENABLE (0x01u << 5) /*!< RTC VDD12 enable */ #define RTC_CON0_BG_ENABLE (0x01u << 4) /*!< BG enable */ #define RTC_CON0_LVD_OUTPUT_ENABLE (0x01u << 3) /*!< LVD output enable */