diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index c6b9930c9008041033d37b72c0f85d5845616383..f6499505c32a5508ca26b9c0bc11435798d9cda2 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -32,14 +32,14 @@ jobs: - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "imxrt/imxrt1052-fire-pro", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "imxrt/imxrt1052-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "lm3s8962", RTT_TOOL_CHAIN: "sourcery-arm"} @@ -55,7 +55,7 @@ jobs: - {RTT_BSP: "lpc2148", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "lpc2478", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "lpc5410x", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"} - {RTT_BSP: "ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"} - {RTT_BSP: "mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"} @@ -63,10 +63,10 @@ jobs: - {RTT_BSP: "mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f091-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-atk-warshipv3", RTT_TOOL_CHAIN: "sourcery-arm"} @@ -81,7 +81,7 @@ jobs: - {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f410-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f411-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f411-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} @@ -91,45 +91,46 @@ jobs: - {RTT_BSP: "stm32/stm32f429-armfly-v6", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f429-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f429-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32h743-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32h743-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32h747-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32l4r9-st-eval", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32l010-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32l053-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "zynq7000", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "swm320", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "zynq7000", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"} steps: - uses: actions/checkout@v2 - name: Set up Python @@ -144,13 +145,13 @@ jobs: sudo apt-get -qq install gcc-multilib libsdl-dev scons echo "RTT_ROOT=${{ github.workspace }}" >> $GITHUB_ENV echo "RTT_CC=gcc" >> $GITHUB_ENV - + - name: Install Arm ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }} shell: bash run: | - wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 - sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt + wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 + sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin" >> $GITHUB_ENV @@ -158,8 +159,8 @@ jobs: if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }} shell: bash run: | - wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 - sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt + wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 + sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt /opt/mips-2016.05/bin/mips-sde-elf-gcc --version echo "RTT_EXEC_PATH=/opt/mips-2016.05/bin" >> $GITHUB_ENV diff --git a/bsp/swm320/.config b/bsp/swm320/.config new file mode 100644 index 0000000000000000000000000000000000000000..55292559108b71d1f945a42c09140c98eb4cb2a3 --- /dev/null +++ b/bsp/swm320/.config @@ -0,0 +1,534 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_SWM320=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_CRC is not set + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_EXT_SRAM is not set +# CONFIG_BSP_USING_NOR_FLASH is not set + +# +# Offboard Peripheral Drivers +# diff --git a/bsp/swm320/Kconfig b/bsp/swm320/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..126a6a1f5c39eafee5b8ad26d6e846340febf88c --- /dev/null +++ b/bsp/swm320/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "drivers/Kconfig" + +config SOC_SWM320 + bool + select ARCH_ARM_CORTEX_M4 + default y diff --git a/bsp/swm320/README.md b/bsp/swm320/README.md new file mode 100644 index 0000000000000000000000000000000000000000..356c4c7b157c8f322382ff6398d5bbbd64dace5a --- /dev/null +++ b/bsp/swm320/README.md @@ -0,0 +1,169 @@ +# SWM320 BSP 说明 + +标签： SYNWIT、Cortex-M4、SWM320、国产MCU + +--- + +## 简介 + +本文档为SWM320开发板提供的 BSP (板级支持包) 说明。 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +## 芯片介绍 + +- 内核 + - 32位ARM® Cortex™-M4 内核 + - 24位系统定时器 + - 工作频率最高120MHz + - 硬件单周期乘法 + - 集成嵌套向量中断控制器（NVIC），提供最多240个、8级可配置优先级的中断 + - 通过SWD接口烧录 +- 内置LDO + - 供电电压范围为2.0V至3.6V +- 片上SRAM存储器 + - 128KB +- 片上FLASH存储器 + - 128KB/256KB/512KB + - 支持用户定制ISP（在系统编程）更新用户程序 +- 串行接口 + - UART模块，具有独立8字节FIFO，最高支持主时钟16分频 + - SPI模块，具有8字节独立FIFO，支持SPI、SSI协议，支持Master/slave模式 + - I2C模块，支持7位、10位地址方式，支持Master/slave模式 + - CAN模块，支持协议2.0A(11Bit标识符)和2.0B（29Bit标识符） +- PWM控制模块 + - 12通道16位PWM产生器 + - 可设置高电平结束或周期开始两种条件触发中断 + - 具有普通、互补、中心对称等多种输出模式 + - 支持死区控制 + - ADC采样触发 +- 定时器模块 + - 6路32位通用定时器 + - 具备独立中断 + - 可做计数器使用 + - 支持输入单脉冲捕获功能 + - 32位看门狗定时器，溢出后可配置触发中断或复位芯片 +- RTC模块 + - 可自由设置日期（年、月、周、日）和时间（时、分、秒） + - 可自由设置闹钟（周、时、分、秒） + - 自动识别当前设置年份是否为闰年 + - 支持RTC中断从Sleep模式下唤醒芯片 +- DMA模块 + - 支持存储器到存储器之间的数据搬运 +- SRAMC模块 + - 支持8位数据位宽和16位数据位宽的外部SRAM存储器 + - 最大支持24位地址线 +- SDRAMC模块 + - 支持16Bit位宽的SDRAM + - 支持兼容PC133标准的SDRAM颗粒 + - 支持2MB到32MB的外部SDRAM颗粒 +- NORFLC模块 + - 支持并行NOR FLASH接口 + - 支持8位数据位宽和16位数据位宽的外部NOR FLASH存储器 + - 最大支持24位地址线 +- SDIO接口模块 + - 支持标准SDIO接口协议 +- TFT-LCD驱动模块 + - 支持SYNC接口的外部LCD扩展 + - 支持最高分辨率1024*768，实际分辨率可以配置 + - 输出数据宽度16Bit + - 支持横屏和竖屏模式 +- GPIO + - 最多可达100个GPIO + - 可配置2种IO模式 + - 上拉输入 + - 下拉输入 + - 灵活的中断配置 + - 触发类型设置（边沿检测、电平检测） + - 触发电平设置（高电平、低电平） + - 触发边沿设置（上升沿、下降沿、双边沿） +- 模拟外设 + - 最多2个12位8通道高精度SAR ADC + - 采样率高达1M SPS + - 内建参考电压 + - 支持single、scan两种模式 + - 独立的结果寄存器 + - 提供独立FIFO + - 可由软件、PWM触发 +- 欠压检测（BOD） + - 支持欠压检测 + - 支持欠压中断和复位选择 +- 时钟源 + - 20MHz/40MHz精度可达1%的片内时钟源 + - 32K片内时钟源 + - 2～32MHz片外晶振 + +芯片更多详细信息请参考[华芯微特技术支持][http://www.synwit.cn/support-1/3.html]。 + +## 编译说明 + +本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 Jlink 仿真器下载程序，在通过 Jlink 连接开发板到 PC 的基础上，点击下载按钮即可下载程序到开发板 + +推荐熟悉 RT_Thread 的用户使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到 `bsp/swm320` 目录中，运行以下命令： + +`scons` + +来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中 rtthread.bin 可以烧写到设备中运行。 + +## 烧写及执行 + +### 硬件连接 + +- 使用 USB B-Type 数据线连接开发板到 PC（注意：需要下载安装串口驱动支持 CH340 芯片，使用 MDK5 需要安装 SWM320 相关的 pack）。 + + > USB B-Type 数据线用于串口通讯，同时供电 + +- 使用 Jlink 连接开发板到 PC （需要 Jlink 驱动） + +将串口 0 引脚为：`[PA2/PA3]`和 USB 转串口模块 P2 相连，串口配置方式为115200-N-8-1。 + +当使用 [env工具](https://www.rt-thread.org/page/download.html) 正确编译产生出rtthread.bin映像文件后，可以使用 ISP 的方式来烧写到设备中。 + +**建议使用 keil 软件直接下载**。ISP 下载较复杂。 + +### 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到板子上的蓝色LED闪烁。串口打印RT-Thread的启动logo信息： + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Dec 11 2018 + 2006 - 2018 Copyright by rt-thread team +msh /> +``` +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :----------------------------------- | +| GPIO | 支持 | PA0, PA1... PP23 ---> PIN: 0, 1...100 | +| UART | 支持 | UART0/1/2/3 | +| ADC | 支持 | ADC0/1 | +| TIM | 支持 | TIM0/1/2/3/4/5 | +| I2C | 支持 | 软件 I2C0/1 | +| PWM | 支持 | PWM0/1/2/3/4/5 | +| RTC | 支持 | RTC | +| SPI | 支持 | SPI0/1 | +| WDT | 支持 | WDT | +| CRC | 支持 | CRC | +| SDIO | 支持 | SDIO | +| SRAM | 支持 | SRAM | +| NOR FLASH | 支持 | NOR FLASH | +| CAN | 暂不支持 | | + +## 维护人信息 + +- [yanmowudi](https://github.com/yanmowudi) +- [邮箱](lik@synwit.cn) + +## 参考资料 + +* [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) + +* [SWM320数据手册](http://www.synwit.cn/support-1/3.html) diff --git a/bsp/swm320/SConscript b/bsp/swm320/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c7ef7659ecea92b1dd9b71a97736a8552ee02551 --- /dev/null +++ b/bsp/swm320/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/swm320/SConstruct b/bsp/swm320/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..c11cd41bc7d150d6dd91a74af9433a4a2d291f6a --- /dev/null +++ b/bsp/swm320/SConstruct @@ -0,0 +1,41 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] + +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/swm320/applications/SConscript b/bsp/swm320/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..7eaae20596155f1f6f8abfad0cbce927626cbfbc --- /dev/null +++ b/bsp/swm320/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = Glob('*.c') + Glob('*.cpp') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/swm320/applications/main.c b/bsp/swm320/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..62e1250eb274298702eb522f6b0d4c9321de0afa --- /dev/null +++ b/bsp/swm320/applications/main.c @@ -0,0 +1,574 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include + +#define LED_PIN 21 + +int main(void) +{ + int count = 1; + + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + while (count++) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(1000); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(1000); + } + + return RT_EOK; +} + +// #ifdef RT_USING_PIN +// #define KEY1_PIN 25 +// void key1_cb(void *args) +// { +// rt_kprintf("key1 irq!\n"); +// } +// static int pin_sample(int argc, char *argv[]) +// { +// rt_pin_mode(KEY1_PIN, PIN_IRQ_MODE_FALLING); +// rt_pin_attach_irq(KEY1_PIN, PIN_IRQ_MODE_FALLING, key1_cb, RT_NULL); +// rt_pin_irq_enable(KEY1_PIN, PIN_IRQ_ENABLE); + +// return RT_EOK; +// } +// MSH_CMD_EXPORT(pin_sample, pin sample); +// #endif + +#ifdef RT_USING_ADC +#define ADC_DEV_NAME "adc0" +#define ADC_DEV_CHANNEL 0 +#define REFER_VOLTAGE 330 +#define CONVERT_BITS (1 << 12) + +static int adc_vol_sample(int argc, char *argv[]) +{ + rt_adc_device_t adc_dev; + rt_uint32_t value, vol; + rt_err_t ret = RT_EOK; + + adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME); + if (adc_dev == RT_NULL) + { + rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME); + return RT_ERROR; + } + + while (1) + { + ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); + value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); + rt_kprintf("the value is :%d,", value); + vol = value * REFER_VOLTAGE / CONVERT_BITS; + rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + rt_thread_mdelay(500); + ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); + } + + return ret; +} +MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); +#endif + +#ifdef RT_USING_HWTIMER +#define HWTIMER_DEV_NAME "timer0" + +static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) +{ + rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("tick is :%d !\n", rt_tick_get()); + + return 0; +} + +static int hwtimer_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_hwtimerval_t timeout_s; + rt_device_t hw_dev = RT_NULL; + rt_hwtimer_mode_t mode; + + hw_dev = rt_device_find(HWTIMER_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + return RT_ERROR; + } + + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + return ret; + } + + rt_device_set_rx_indicate(hw_dev, timeout_cb); + + mode = HWTIMER_MODE_PERIOD; + //mode = HWTIMER_MODE_ONESHOT; + ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + if (ret != RT_EOK) + { + rt_kprintf("set mode failed! ret is :%d\n", ret); + return ret; + } + + timeout_s.sec = 2; + timeout_s.usec = 0; + + if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + { + rt_kprintf("set timeout value failed\n"); + return RT_ERROR; + } + + rt_thread_mdelay(3500); + + rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} +MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +#endif + +#ifdef RT_USING_PWM +#define PWM_DEV_NAME "pwm0" /* PWM???? */ +#define PWM_DEV_CHANNEL 0 /* PWM?? */ + +struct rt_device_pwm *pwm_dev; /* PWM???? */ + +static int pwm_sample(int argc, char *argv[]) +{ + rt_uint32_t period, pulse; + + period = 500000; /* ???0.5ms,?????ns */ + pulse = 250000; /* PWM?????,?????ns */ + + pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); + if (pwm_dev == RT_NULL) + { + rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME); + return RT_ERROR; + } + + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL); + return RT_EOK; +} +MSH_CMD_EXPORT(pwm_sample, pwm sample); +#endif + +#ifdef RT_USING_RTC +static int rtc_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + time_t now; + + ret = set_date(2020, 6, 15); + if (ret != RT_EOK) + { + rt_kprintf("set RTC date failed\n"); + return ret; + } + + ret = set_time(11, 15, 50); + if (ret != RT_EOK) + { + rt_kprintf("set RTC time failed\n"); + return ret; + } + + rt_thread_mdelay(3000); + now = time(RT_NULL); + rt_kprintf("%s\n", ctime(&now)); + + return ret; +} +MSH_CMD_EXPORT(rtc_sample, rtc sample); +#endif + +#ifdef RT_USING_WDT +#define WDT_DEVICE_NAME "wdt" + +static rt_device_t wdg_dev; + +static void idle_hook(void) +{ + rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, NULL); + rt_kprintf("feed the dog!\n "); +} + +static int wdt_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t timeout = 1; + char device_name[RT_NAME_MAX]; + + if (argc == 2) + { + rt_strncpy(device_name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(device_name, WDT_DEVICE_NAME, RT_NAME_MAX); + } + wdg_dev = rt_device_find(device_name); + if (!wdg_dev) + { + rt_kprintf("find %s failed!\n", device_name); + return RT_ERROR; + } + ret = rt_device_init(wdg_dev); + if (ret != RT_EOK) + { + rt_kprintf("initialize %s failed!\n", device_name); + return RT_ERROR; + } + ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout); + if (ret != RT_EOK) + { + rt_kprintf("set %s timeout failed!\n", device_name); + return RT_ERROR; + } + ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL); + if (ret != RT_EOK) + { + rt_kprintf("start %s failed!\n", device_name); + return -RT_ERROR; + } + // rt_thread_idle_sethook(idle_hook); + + return ret; +} +MSH_CMD_EXPORT(wdt_sample, wdt sample); +#endif + +#ifdef RT_USING_SPI +#define W25Q_SPI_DEVICE_NAME "spi00" +#define W25Q_FLASH_NAME "norflash0" + +#include "drv_spi.h" +#include "spi_flash_sfud.h" +#include "dfs_posix.h" + +static int rt_hw_spi_flash_init(void) +{ + rt_hw_spi_device_attach("spi0", "spi00", GPIOA, PIN12); + + if (RT_NULL == rt_sfud_flash_probe(W25Q_FLASH_NAME, W25Q_SPI_DEVICE_NAME)) + { + return -RT_ERROR; + }; + + return RT_EOK; +} +/* ???????? */ +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); + +static void spi_w25q_sample(int argc, char *argv[]) +{ + struct rt_spi_device *spi_dev_w25q; + char name[RT_NAME_MAX]; + rt_uint8_t w25x_read_id = 0x90; + rt_uint8_t id[5] = {0}; + + if (argc == 2) + { + rt_strncpy(name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(name, W25Q_SPI_DEVICE_NAME, RT_NAME_MAX); + } + + /* ?? spi ???????? */ + spi_dev_w25q = (struct rt_spi_device *)rt_device_find(name); + struct rt_spi_configuration cfg; + cfg.data_width = 8; + cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB; + cfg.max_hz = 20 * 1000 * 1000; /* 20M */ + + rt_spi_configure(spi_dev_w25q, &cfg); + if (!spi_dev_w25q) + { + rt_kprintf("spi sample run failed! can't find %s device!\n", name); + } + else + { + /* ??1:?? rt_spi_send_then_recv()??????ID */ + rt_spi_send_then_recv(spi_dev_w25q, &w25x_read_id, 1, id, 5); + rt_kprintf("use rt_spi_send_then_recv() read w25q ID is:%x%x\n", id[3], id[4]); + + /* ??2:?? rt_spi_transfer_message()??????ID */ + struct rt_spi_message msg1, msg2; + + msg1.send_buf = &w25x_read_id; + msg1.recv_buf = RT_NULL; + msg1.length = 1; + msg1.cs_take = 1; + msg1.cs_release = 0; + msg1.next = &msg2; + + msg2.send_buf = RT_NULL; + msg2.recv_buf = id; + msg2.length = 5; + msg2.cs_take = 0; + msg2.cs_release = 1; + msg2.next = RT_NULL; + + rt_spi_transfer_message(spi_dev_w25q, &msg1); + rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]); + } +} +static void spi_flash_elmfat_sample(void) +{ + int fd, size; + struct statfs elm_stat; + char str[] = "elmfat mount to W25Q flash.\r\n", buf[80]; + + if (dfs_mkfs("elm", W25Q_FLASH_NAME) == 0) + rt_kprintf("make elmfat filesystem success.\n"); + + if (dfs_mount(W25Q_FLASH_NAME, "/", "elm", 0, 0) == 0) + rt_kprintf("elmfat filesystem mount success.\n"); + + if (statfs("/", &elm_stat) == 0) + rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n", + elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree); + + if (mkdir("/user", 0x777) == 0) + rt_kprintf("make a directory: '/user'.\n"); + + rt_kprintf("Write string '%s' to /user/test.txt.\n", str); + + /* ????????????,??????????????*/ + fd = open("/user/test.txt", O_WRONLY | O_CREAT); + if (fd >= 0) + { + if (write(fd, str, sizeof(str)) == sizeof(str)) + rt_kprintf("Write data done.\n"); + + close(fd); + } + + /* ????????? */ + fd = open("/user/test.txt", O_RDONLY); + if (fd >= 0) + { + size = read(fd, buf, sizeof(buf)); + + close(fd); + + if (size == sizeof(str)) + rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf); + } +} +MSH_CMD_EXPORT(spi_flash_elmfat_sample, spi flash elmfat sample); +MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample); +#endif + +//#ifdef RT_USING_SPI +//#define SD_SPI_DEVICE_NAME "spi10" +//#define SDCARD_NAME "sd0" + +//#include "drv_spi.h" +//#include "dfs_posix.h" +//#include "spi_msd.h" + +//static int rt_hw_spi1_tfcard(void) +//{ +// rt_hw_spi_device_attach("spi1", SD_SPI_DEVICE_NAME, GPIOB, PIN6); +// return msd_init(SDCARD_NAME, SD_SPI_DEVICE_NAME); +//} +//INIT_DEVICE_EXPORT(rt_hw_spi1_tfcard); + +//static void elmfat_sample(void) +//{ +// int fd, size; +// struct statfs elm_stat; +// char str[] = "elmfat mount to sdcard.\r\n", buf[80]; + +// if (dfs_mkfs("elm", SDCARD_NAME) == 0) +// rt_kprintf("make elmfat filesystem success.\n"); + +// if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0) +// rt_kprintf("elmfat filesystem mount success.\n"); + +// if (statfs("/", &elm_stat) == 0) +// rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n", +// elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree); + +// if (mkdir("/user", 0x777) == 0) +// rt_kprintf("make a directory: '/user'.\n"); + +// rt_kprintf("Write string '%s' to /user/test.txt.\n", str); + +// fd = open("/user/test.txt", O_WRONLY | O_CREAT); +// if (fd >= 0) +// { +// if (write(fd, str, sizeof(str)) == sizeof(str)) +// rt_kprintf("Write data done.\n"); + +// close(fd); +// } + +// fd = open("/user/test.txt", O_RDONLY); +// if (fd >= 0) +// { +// size = read(fd, buf, sizeof(buf)); + +// close(fd); + +// if (size == sizeof(str)) +// rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf); +// } +//} +//MSH_CMD_EXPORT(elmfat_sample, elmfat sample); +//#endif + +#ifdef RT_USING_SDIO +#define SDCARD_NAME "sd0" + +#include "dfs_posix.h" + +static void sdio_elmfat_sample(void) +{ + int fd, size; + struct statfs elm_stat; + char str[] = "elmfat mount to sdcard.\n", buf[80]; + + if (dfs_mkfs("elm", SDCARD_NAME) == 0) + rt_kprintf("make elmfat filesystem success.\n"); + + if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0) + rt_kprintf("elmfat filesystem mount success.\n"); + + if (statfs("/", &elm_stat) == 0) + rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n", + elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree); + + if (mkdir("/user", 0x777) == 0) + rt_kprintf("make a directory: '/user'.\n"); + + rt_kprintf("Write string '%s' to /user/test.txt.\n", str); + + fd = open("/user/test.txt", O_WRONLY | O_CREAT); + if (fd >= 0) + { + if (write(fd, str, sizeof(str)) == sizeof(str)) + rt_kprintf("Write data done.\n"); + + close(fd); + } + + fd = open("/user/test.txt", O_RDONLY); + if (fd >= 0) + { + size = read(fd, buf, sizeof(buf)); + + close(fd); + + if (size == sizeof(str)) + rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf); + } +} +MSH_CMD_EXPORT(sdio_elmfat_sample, sdio elmfat sample); +#endif + +#ifdef RT_USING_HWCRYPTO +static void crypto_sample(void) +{ + rt_uint8_t temp[] = {0, 1, 2, 3, 4, 5, 6, 7}; + struct rt_hwcrypto_ctx *ctx; + rt_uint32_t result = 0; + struct hwcrypto_crc_cfg cfg = + { + .last_val = 0x0, + .poly = 0x04C11DB7, + .width = 8, + .xorout = 0x00000000, + .flags = 0, + }; + + ctx = rt_hwcrypto_crc_create(rt_hwcrypto_dev_default(), HWCRYPTO_CRC_CRC32); + rt_hwcrypto_crc_cfg(ctx, &cfg); + result = rt_hwcrypto_crc_update(ctx, temp, sizeof(temp)); + rt_kprintf("result: 0x%08x \n", result); + rt_hwcrypto_crc_destroy(ctx); +} +MSH_CMD_EXPORT(crypto_sample, crypto sample); +#endif + +#ifdef BSP_USING_NOR_FLASH +#define NORFLASH_DEV_NAME "nor" +static int norflash_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_device_t hw_dev = RT_NULL; + + hw_dev = rt_device_find(NORFLASH_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("norflash sample run failed! can't find %s device!\n", NORFLASH_DEV_NAME); + return RT_ERROR; + } + else + { + rt_kprintf("norflash sample run success! find %s device!\n", NORFLASH_DEV_NAME); + } + + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", NORFLASH_DEV_NAME); + return ret; + } + else + { + rt_kprintf("open %s device success!\n", NORFLASH_DEV_NAME); + } + + struct rt_mtd_nor_device *hw_nor; + hw_nor = RT_MTD_NOR_DEVICE(hw_dev); + long id = hw_nor->ops->read_id(hw_nor); + rt_kprintf("id = %08x!\n", id); + // rt_device_set_rx_indicate(hw_dev, timeout_cb); + + // mode = HWTIMER_MODE_PERIOD; + // //mode = HWTIMER_MODE_ONESHOT; + // ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + // if (ret != RT_EOK) + // { + // rt_kprintf("set mode failed! ret is :%d\n", ret); + // return ret; + // } + + // timeout_s.sec = 2; + // timeout_s.usec = 0; + + // if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + // { + // rt_kprintf("set timeout value failed\n"); + // return RT_ERROR; + // } + + // rt_thread_mdelay(3500); + + // rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + // rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} +MSH_CMD_EXPORT(norflash_sample, norflash sample); +#endif diff --git a/bsp/swm320/drivers/Kconfig b/bsp/swm320/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..cd638055a6b0490dbfd13a400e3005fdb8070069 --- /dev/null +++ b/bsp/swm320/drivers/Kconfig @@ -0,0 +1,306 @@ +menu "Hardware Drivers Config" + +config SOC_SWM320 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0 (A2/RX,A3/TX)" + default y + config BSP_USING_UART1 + bool "Enable UART1 (C2/RX,C3/TX)" + default n + config BSP_USING_UART2 + bool "Enable UART2 (C4/RX,C5/TX)" + default n + config BSP_USING_UART3 + bool "Enable UART3 (C6/RX,C7/TX)" + default n + endif + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + if BSP_USING_ADC0 + config BSP_USING_ADC0_CHN0 + bool "Enable ADC0_CHN0" + default n + config BSP_USING_ADC0_CHN1 + bool "Enable ADC0_CHN1" + default n + config BSP_USING_ADC0_CHN2 + bool "Enable ADC0_CHN2" + default n + config BSP_USING_ADC0_CHN3 + bool "Enable ADC0_CHN3" + default n + config BSP_USING_ADC0_CHN4 + bool "Enable ADC0_CHN4(A12)" + default n + config BSP_USING_ADC0_CHN5 + bool "Enable ADC0_CHN5(A11)" + default n + config BSP_USING_ADC0_CHN6 + bool "Enable ADC0_CHN6(A10)" + default n + config BSP_USING_ADC0_CHN7 + bool "Enable ADC0_CHN7(A9)" + default n + endif + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + if BSP_USING_ADC1 + config BSP_USING_ADC1_CHN0 + bool "Enable ADC1_CHN0(C7)" + default n + config BSP_USING_ADC1_CHN1 + bool "Enable ADC1_CHN1(C6)" + default n + config BSP_USING_ADC1_CHN2 + bool "Enable ADC1_CHN2(C5)" + default n + config BSP_USING_ADC1_CHN3 + bool "Enable ADC1_CHN3(C4)" + default n + config BSP_USING_ADC1_CHN4 + bool "Enable ADC1_CHN4(N0)" + default n + config BSP_USING_ADC1_CHN5 + bool "Enable ADC1_CHN5(N1)" + default n + config BSP_USING_ADC1_CHN6 + bool "Enable ADC1_CHN6(N2)" + default n + config BSP_USING_ADC1_CHN7 + bool "Enable ADC1_CHN7" + default n + endif + endif + + menuconfig BSP_USING_TIM + bool "Enable HWTIMER" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM0 + bool "Enable TIM0" + default n + config BSP_USING_TIM1 + bool "Enable TIM1" + default n + config BSP_USING_TIM2 + bool "Enable TIM2" + default n + config BSP_USING_TIM3 + bool "Enable TIM3" + default n + + config BSP_USING_TIM4 + bool "Enable TIM4" + default n + config BSP_USING_TIM5 + bool "Enable TIM5" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default n + if BSP_USING_I2C0 + comment "Notice: PC2 --> 28; PC3 --> 29" + config BSP_I2C0_SCL_PIN + int "I2C0 scl pin number" + range 0 99 + default 28 + config BSP_I2C0_SDA_PIN + int "I2C0 sda pin number" + range 0 99 + default 29 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + comment "Notice: PC6 --> 32; PC7 --> 33" + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 0 99 + default 32 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 99 + default 33 + endif + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable PWM0" + default n + if BSP_USING_PWM0 + config BSP_USING_PWM0A + bool "Enable PWM0A (C2)" + default n + config BSP_USING_PWM0B + bool "Enable PWM0B (C4)" + default n + endif + config BSP_USING_PWM1 + bool "Enable PWM1" + default n + if BSP_USING_PWM1 + config BSP_USING_PWM1A + bool "Enable PWM1A (C3)" + default n + config BSP_USING_PWM1B + bool "Enable PWM1B (C5)" + default n + endif + config BSP_USING_PWM2 + bool "Enable PWM2" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2A + bool "Enable PWM2A (N4)" + default n + config BSP_USING_PWM2B + bool "Enable PWM2B (N6)" + default n + endif + config BSP_USING_PWM3 + bool "Enable PWM3" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3A + bool "Enable PWM3A (N3)" + default n + config BSP_USING_PWM3B + bool "Enable PWM3B (N5)" + default n + endif + config BSP_USING_PWM4 + bool "Enable PWM4" + default n + if BSP_USING_PWM4 + config BSP_USING_PWM4A + bool "Enable PWM4A (N8)" + default n + config BSP_USING_PWM4B + bool "Enable PWM4B (N10)" + default n + endif + config BSP_USING_PWM5 + bool "Enable PWM5" + default n + if BSP_USING_PWM5 + config BSP_USING_PWM5A + bool "Enable PWM5A (N7)" + default n + config BSP_USING_PWM5B + bool "Enable PWM5B (N9)" + default n + endif + endif + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 BUS(CS/A12,MISO/A11,MOSI/A10,CLK/A9)" + default n + + config BSP_USING_SPI1 + bool "Enable SPI1 BUS(CS/C4,MISO/C5,MOSI/C6,CLK/C7)" + default n + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_CRC + bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_CRC + default n +endmenu + +menu "Onboard Peripheral Drivers" + config BSP_USING_SDIO + bool "Enable SDCARD (sdio)" + select RT_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + + menuconfig BSP_USING_EXT_SRAM + bool "Enable external sram" + select RT_USING_MEMHEAP + select RT_USING_MEMHEAP_AS_HEAP + default n + if BSP_USING_EXT_SRAM + config BSP_EXT_SRAM_SIZE + hex "external sram size" + default 0x100000 + endif + + menuconfig BSP_USING_NOR_FLASH + bool "Enable mtd nor flash" + select RT_USING_MTD_NOR + select PKG_USING_FTL_SRC + default n + if BSP_USING_NOR_FLASH + config BSP_NOR_FLASH_SIZE + hex "mtd nor flash size" + default 0x1000000 + config BSP_NOR_FLASH_SECTOR_SIZE + hex "mtd nor flsah sector" + default 0x10000 + endif +endmenu + +menu "Offboard Peripheral Drivers" + +endmenu + +endmenu diff --git a/bsp/swm320/drivers/SConscript b/bsp/swm320/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..cddf8cc0b743b7456f03ec10b3c7fda73e405397 --- /dev/null +++ b/bsp/swm320/drivers/SConscript @@ -0,0 +1,52 @@ +from building import * + +cwd = GetCurrentDir() + +CPPPATH = [cwd] + +src = Split(''' + board.c + ''') + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_uart.c'] + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['drv_adc.c'] + +if GetDepend(['RT_USING_HWTIMER']): + src += ['drv_hwtimer.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['drv_soft_i2c.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drv_pwm.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['drv_rtc.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['drv_wdt.c'] + +if GetDepend(['RT_USING_SDIO']): + src += ['drv_sdio.c'] + +if GetDepend(['RT_USING_HWCRYPTO']): + src += ['drv_crypto.c'] + +if GetDepend(['BSP_USING_EXT_SRAM']): + src += ['drv_sram.c'] + +if GetDepend(['BSP_USING_NOR_FLASH']): + src += ['drv_nor_flash.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/swm320/drivers/board.c b/bsp/swm320/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..16675e7a3d3bcb758f9daaf69338aeae71b830f3 --- /dev/null +++ b/bsp/swm320/drivers/board.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include "board.h" + +static void bsp_clock_config(void) +{ + SystemInit(); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + SysTick->CTRL |= 0x00000004UL; +} +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void rt_hw_board_init() +{ + bsp_clock_config(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} diff --git a/bsp/swm320/drivers/board.h b/bsp/swm320/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..223018920fed39dd08c5f8784eff7c16440f222e --- /dev/null +++ b/bsp/swm320/drivers/board.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define SRAM_BASE 0x20000000 +#define SRAM_SIZE 0x20000 +#define SRAM_END (SRAM_BASE + SRAM_SIZE) + +#ifdef BSP_USING_EXT_SRAM +#define EXT_SRAM_BASE SRAMM_BASE +#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE +#define EXT_SRAM_BEGIN EXT_SRAM_BASE +#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) +#endif + +#if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END SRAM_END +#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN) + + void rt_hw_board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/swm320/drivers/drv_adc.c b/bsp/swm320/drivers/drv_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..fa557fda4664024c5c332c616b8ed5b9f539380e --- /dev/null +++ b/bsp/swm320/drivers/drv_adc.c @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-5-26 lik first version + */ + +#include "drv_adc.h" + +#ifdef RT_USING_ADC +#ifdef BSP_USING_ADC + +//#define DRV_DEBUG +#define LOG_TAG "drv.adc" +#include + +static struct swm_adc_cfg adc_cfg[] = + { +#ifdef BSP_USING_ADC0 + ADC0_CFG, +#endif +#ifdef BSP_USING_ADC1 + ADC1_CFG, +#endif + +}; + +static struct swm_adc adc_drv[sizeof(adc_cfg) / sizeof(adc_cfg[0])]; + +static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled) +{ + struct swm_adc_cfg *cfg = RT_NULL; + RT_ASSERT(adc_device != RT_NULL); + cfg = adc_device->parent.user_data; + + if (enabled) + { + ADC_Open(cfg->ADCx); + } + else + { + ADC_Close(cfg->ADCx); + } + + return RT_EOK; +} + +static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel) +{ + rt_uint32_t swm_channel = 0; + + switch (channel) + { + case 0: + swm_channel = ADC_CH0; + break; + case 1: + swm_channel = ADC_CH1; + break; + case 2: + swm_channel = ADC_CH2; + break; + case 3: + swm_channel = ADC_CH3; + break; + case 4: + swm_channel = ADC_CH4; + break; + case 5: + swm_channel = ADC_CH5; + break; + case 6: + swm_channel = ADC_CH6; + break; + case 7: + swm_channel = ADC_CH7; + break; + } + + return swm_channel; +} + +static rt_err_t swm_get_adc_value(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value) +{ + uint32_t adc_chn; + struct swm_adc_cfg *cfg = RT_NULL; + RT_ASSERT(adc_device != RT_NULL); + RT_ASSERT(value != RT_NULL); + cfg = adc_device->parent.user_data; + + if (channel < 8) + { + /* set stm32 ADC channel */ + adc_chn = swm_adc_get_channel(channel); + } + else + { + LOG_E("ADC channel must be between 0 and 7."); + return -RT_ERROR; + } + + /* start ADC */ + ADC_Start(cfg->ADCx); + /* Wait for the ADC to convert */ + while ((cfg->ADCx->CH[channel].STAT & 0x01) == 0) + ; + + /* get ADC value */ + *value = (rt_uint32_t)ADC_Read(cfg->ADCx, adc_chn); + + return RT_EOK; +} + +static const struct rt_adc_ops swm_adc_ops = + { + .enabled = swm_adc_enabled, + .convert = swm_get_adc_value, +}; + +static int rt_hw_adc_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(adc_cfg) / sizeof(adc_cfg[0]); i++) + { + /* ADC init */ + adc_drv[i].cfg = &adc_cfg[i]; + + if (adc_drv[i].cfg->ADCx == ADC0) + { +#ifdef BSP_USING_ADC0_CHN0 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0; +#endif +#ifdef BSP_USING_ADC0_CHN1 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1; +#endif +#ifdef BSP_USING_ADC0_CHN2 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2; +#endif +#ifdef BSP_USING_ADC0_CHN3 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3; +#endif +#ifdef BSP_USING_ADC0_CHN4 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4; + PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_IN4, 0); //PA.12 => ADC0.CH4 +#endif +#ifdef BSP_USING_ADC0_CHN5 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5; + PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC0_IN5, 0); //PA.11 => ADC0.CH5 +#endif +#ifdef BSP_USING_ADC0_CHN6 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6; + PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_IN6, 0); //PA.10 => ADC0.CH6 +#endif +#ifdef BSP_USING_ADC0_CHN7 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7; + PORT_Init(PORTA, PIN9, PORTA_PIN9_ADC0_IN7, 0); //PA.9 => ADC0.CH7 +#endif + } + else if (adc_drv[i].cfg->ADCx == ADC1) + { +#ifdef BSP_USING_ADC1_CHN0 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0; + PORT_Init(PORTC, PIN7, PORTC_PIN7_ADC1_IN0, 0); //PC.7 => ADC1.CH0 +#endif +#ifdef BSP_USING_ADC1_CHN1 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1; + PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC1_IN1, 0); //PC.6 => ADC1.CH1 +#endif +#ifdef BSP_USING_ADC1_CHN2 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2; + PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC1_IN2, 0); //PC.5 => ADC1.CH2 +#endif +#ifdef BSP_USING_ADC1_CHN3 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3; + PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC1_IN3, 0); //PC.4 => ADC1.CH3 +#endif +#ifdef BSP_USING_ADC1_CHN4 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4; + PORT_Init(PORTN, PIN0, PORTN_PIN0_ADC1_IN4, 0); //PN.0 => ADC1.CH4 +#endif +#ifdef BSP_USING_ADC1_CHN5 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5; + PORT_Init(PORTN, PIN1, PORTN_PIN1_ADC1_IN5, 0); //PN.1 => ADC1.CH5 +#endif +#ifdef BSP_USING_ADC1_CHN6 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6; + PORT_Init(PORTN, PIN2, PORTN_PIN2_ADC1_IN6, 0); //PN.2 => ADC1.CH6 +#endif +#ifdef BSP_USING_ADC1_CHN7 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7; +#endif + } + + ADC_Init(adc_drv[i].cfg->ADCx, &(adc_drv[i].cfg->adc_initstruct)); + ADC_Open(adc_drv[i].cfg->ADCx); + /* register ADC device */ + if (rt_hw_adc_register(&adc_drv[i].adc_device, adc_drv[i].cfg->name, &swm_adc_ops, adc_drv[i].cfg) == RT_EOK) + { + LOG_D("%s init success", adc_drv[i].cfg->name); + } + else + { + LOG_E("%s register failed", adc_drv[i].cfg->name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_adc_init); +#endif /* BSP_USING_ADC */ +#endif /* RT_USING_ADC */ diff --git a/bsp/swm320/drivers/drv_adc.h b/bsp/swm320/drivers/drv_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..04cf20713719343966a7f649911177eeb2866ea0 --- /dev/null +++ b/bsp/swm320/drivers/drv_adc.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-5-26 lik first version + */ + +#ifndef __DRV_ADC_H__ +#define __DRV_ADC_H__ + +#include "board.h" + +struct swm_adc_cfg +{ + const char *name; + ADC_TypeDef *ADCx; + ADC_InitStructure adc_initstruct; +}; + +struct swm_adc +{ + struct swm_adc_cfg *cfg; + struct rt_adc_device adc_device; +}; + +#ifdef BSP_USING_ADC0 +#ifndef ADC0_CFG +#define ADC0_CFG \ + { \ + .name = "adc0", \ + .ADCx = ADC0, \ + .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \ + .adc_initstruct.clk_div = 25, \ + .adc_initstruct.pga_ref = PGA_REF_INTERNAL, \ + .adc_initstruct.channels = 0, \ + .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \ + .adc_initstruct.trig_src = ADC_TRIGSRC_SW, \ + .adc_initstruct.Continue = 0, \ + .adc_initstruct.EOC_IEn = 0, \ + .adc_initstruct.OVF_IEn = 0, \ + .adc_initstruct.HFULL_IEn = 0, \ + .adc_initstruct.FULL_IEn = 0, \ + } +#endif /* ADC0_CFG */ +#endif /* BSP_USING_ADC0 */ + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_CFG +#define ADC1_CFG \ + { \ + .name = "adc1", \ + .ADCx = ADC1, \ + .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \ + .adc_initstruct.clk_div = 25, \ + .adc_initstruct.pga_ref = PGA_REF_INTERNAL, \ + .adc_initstruct.channels = 0, \ + .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \ + .adc_initstruct.trig_src = ADC_TRIGSRC_SW, \ + .adc_initstruct.Continue = 0, \ + .adc_initstruct.EOC_IEn = 0, \ + .adc_initstruct.OVF_IEn = 0, \ + .adc_initstruct.HFULL_IEn = 0, \ + .adc_initstruct.FULL_IEn = 0, \ + } +#endif /* ADC1_CFG */ +#endif /* BSP_USING_ADC1 */ + +#endif /* __DRV_ADC_H__ */ diff --git a/bsp/swm320/drivers/drv_crypto.c b/bsp/swm320/drivers/drv_crypto.c new file mode 100644 index 0000000000000000000000000000000000000000..32d4ecd98a1ad52d01eb720598d39c104ec4d932 --- /dev/null +++ b/bsp/swm320/drivers/drv_crypto.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#include "drv_crypto.h" +#include + +#ifdef RT_USING_HWCRYPTO + +struct swm_hwcrypto_device +{ + struct rt_hwcrypto_device dev; + struct rt_mutex mutex; +}; + +#ifdef BSP_USING_CRC + +struct hash_ctx_des +{ + struct swm_crc_cfg contex; +}; + +static struct hwcrypto_crc_cfg crc_backup_cfg; + +static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length) +{ + rt_uint32_t result = 0; + struct swm_hwcrypto_device *swm_hw_dev = (struct swm_hwcrypto_device *)ctx->parent.device->user_data; + + struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->parent.contex); + + rt_mutex_take(&swm_hw_dev->mutex, RT_WAITING_FOREVER); + + if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0) + { + hw_crc_cfg->CRCx = CRC; + + hw_crc_cfg->inival = ctx->crc_cfg.last_val; + + switch (ctx->crc_cfg.width) + { + case 8: + hw_crc_cfg->crc_inbits = 2; + break; + case 16: + hw_crc_cfg->crc_inbits = 1; + break; + case 32: + hw_crc_cfg->crc_inbits = 0; + break; + default: + goto _exit; + } + switch (ctx->crc_cfg.poly) + { + case 0x1021: + hw_crc_cfg->crc_1632 = 1; + break; + case 0x04C11DB7: + hw_crc_cfg->crc_1632 = 0; + break; + default: + goto _exit; + } + + hw_crc_cfg->crc_out_not = 0; + + switch (ctx->crc_cfg.flags) + { + case 0: + case CRC_FLAG_REFIN: + hw_crc_cfg->crc_out_rev = 0; + break; + case CRC_FLAG_REFOUT: + case CRC_FLAG_REFIN | CRC_FLAG_REFOUT: + hw_crc_cfg->crc_out_rev = 1; + break; + default: + goto _exit; + } + + CRC_Init(hw_crc_cfg->CRCx, (hw_crc_cfg->crc_inbits << 1) | hw_crc_cfg->crc_1632, hw_crc_cfg->crc_out_not, hw_crc_cfg->crc_out_rev, hw_crc_cfg->inival); + memcpy(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)); + } + + for (uint32_t i = 0; i < length; i++) + CRC_Write((uint32_t)in[i]); + result = CRC_Result(); + + ctx->crc_cfg.last_val = result; + + crc_backup_cfg.last_val = ctx->crc_cfg.last_val; + result = (result ? result ^ (ctx->crc_cfg.xorout) : result); + +_exit: + rt_mutex_release(&swm_hw_dev->mutex); + + return result; +} + +static const struct hwcrypto_crc_ops crc_ops = + { + .update = _crc_update, +}; + +static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) +{ + rt_err_t res = RT_EOK; + + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + { + struct swm_crc_cfg *contex = rt_calloc(1, sizeof(struct swm_crc_cfg)); + if (RT_NULL == contex) + { + res = -RT_ERROR; + break; + } + contex->CRCx = DEFAULT_CRC; + contex->inival = DEFAULT_INIVAL; + contex->crc_inbits = DEFAULT_INBITS; + contex->crc_1632 = DEFAULT_CRC1632; + contex->crc_out_not = DEFAULT_OUT_NOT; + contex->crc_out_rev = DEFAULT_OUT_REV; + + ctx->contex = contex; + ((struct hwcrypto_crc *)ctx)->ops = &crc_ops; + break; + } +#endif /* BSP_USING_CRC */ + default: + res = -RT_ERROR; + break; + } + return res; +} + +static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx) +{ + struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex); + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk; + break; +#endif /* BSP_USING_CRC */ + default: + break; + } + + rt_free(ctx->contex); +} + +static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src) +{ + rt_err_t res = RT_EOK; + + switch (src->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + if (des->contex && src->contex) + { + rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des)); + } + break; +#endif /* BSP_USING_CRC */ + default: + res = -RT_ERROR; + break; + } + return res; +} + +static void _crypto_reset(struct rt_hwcrypto_ctx *ctx) +{ + struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex); + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk; + break; +#endif /* BSP_USING_CRC */ + default: + break; + } +} + +static const struct rt_hwcrypto_ops _ops = + { + .create = _crypto_create, + .destroy = _crypto_destroy, + .copy = _crypto_clone, + .reset = _crypto_reset, +}; + +int rt_hw_crypto_init(void) +{ + static struct swm_hwcrypto_device _crypto_dev; + rt_uint32_t cpuid[2] = {0}; + + _crypto_dev.dev.ops = &_ops; + + cpuid[0] = SCB->CPUID; + _crypto_dev.dev.id = 0; + rt_memcpy(&_crypto_dev.dev.id, cpuid, 8); + + _crypto_dev.dev.user_data = &_crypto_dev; + + if (rt_hwcrypto_register(&_crypto_dev.dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK) + { + return -1; + } + rt_mutex_init(&_crypto_dev.mutex, RT_HWCRYPTO_DEFAULT_NAME, RT_IPC_FLAG_FIFO); + return 0; +} +INIT_BOARD_EXPORT(rt_hw_crypto_init); + +#endif /* BSP_USING_WDT */ +#endif /* RT_USING_WDT */ diff --git a/bsp/swm320/drivers/drv_crypto.h b/bsp/swm320/drivers/drv_crypto.h new file mode 100644 index 0000000000000000000000000000000000000000..3f301f45533c87b450a276bbe3606d3138435c80 --- /dev/null +++ b/bsp/swm320/drivers/drv_crypto.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#ifndef __DRV_CRYPTO_H__ +#define __DRV_CRYPTO_H__ + +#include "board.h" + +/* swm config class */ +struct swm_crc_cfg +{ + CRC_TypeDef *CRCx; + uint32_t inival; + uint8_t crc_inbits; + uint8_t crc_1632; + uint8_t crc_out_not; + uint8_t crc_out_rev; +}; + +#ifdef BSP_USING_CRC + +#define DEFAULT_CRC (CRC) +#define DEFAULT_INIVAL (0x00000000) +#define DEFAULT_INBITS (2) +#define DEFAULT_CRC1632 (0) +#define DEFAULT_OUT_NOT (0) +#define DEFAULT_OUT_REV (0) + +#endif /* BSP_USING_CRC */ + +int rt_hw_crypto_init(void); + +#endif /* __DRV_CRYPTO_H__ */ diff --git a/bsp/swm320/drivers/drv_gpio.c b/bsp/swm320/drivers/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..482ffb5e7f72ed324ace7077472dc69fe671e135 --- /dev/null +++ b/bsp/swm320/drivers/drv_gpio.c @@ -0,0 +1,527 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee fix bug + * 2020-07-10 lik rewrite + */ + +#include "drv_gpio.h" + +#ifdef RT_USING_PIN +#ifdef BSP_USING_GPIO + +static const struct swm_pin_index pins[] = + { + __SWM_PIN(0, A, 0), + __SWM_PIN(1, A, 1), + __SWM_PIN(2, A, 2), + __SWM_PIN(3, A, 3), + __SWM_PIN(4, A, 4), + __SWM_PIN(5, A, 5), + __SWM_PIN(6, A, 6), + __SWM_PIN(7, A, 7), + __SWM_PIN(8, A, 8), + __SWM_PIN(9, A, 9), + __SWM_PIN(10, A, 10), + __SWM_PIN(11, A, 11), + __SWM_PIN(12, A, 12), + + __SWM_PIN(13, B, 0), + __SWM_PIN(14, B, 1), + __SWM_PIN(15, B, 2), + __SWM_PIN(16, B, 3), + __SWM_PIN(17, B, 4), + __SWM_PIN(18, B, 5), + __SWM_PIN(19, B, 6), + __SWM_PIN(20, B, 7), + __SWM_PIN(21, B, 8), + __SWM_PIN(22, B, 9), + __SWM_PIN(23, B, 10), + __SWM_PIN(24, B, 11), + __SWM_PIN(25, B, 12), + + __SWM_PIN(26, C, 0), + __SWM_PIN(27, C, 1), + __SWM_PIN(28, C, 2), + __SWM_PIN(29, C, 3), + __SWM_PIN(30, C, 4), + __SWM_PIN(31, C, 5), + __SWM_PIN(32, C, 6), + __SWM_PIN(33, C, 7), + + __SWM_PIN(34, M, 0), + __SWM_PIN(35, M, 1), + __SWM_PIN(36, M, 2), + __SWM_PIN(37, M, 3), + __SWM_PIN(38, M, 4), + __SWM_PIN(39, M, 5), + __SWM_PIN(40, M, 6), + __SWM_PIN(41, M, 7), + __SWM_PIN(42, M, 8), + __SWM_PIN(43, M, 9), + __SWM_PIN(44, M, 10), + __SWM_PIN(45, M, 11), + __SWM_PIN(46, M, 12), + __SWM_PIN(47, M, 13), + __SWM_PIN(48, M, 14), + __SWM_PIN(49, M, 15), + __SWM_PIN(50, M, 16), + __SWM_PIN(51, M, 17), + __SWM_PIN(52, M, 18), + __SWM_PIN(53, M, 19), + __SWM_PIN(54, M, 20), + __SWM_PIN(55, M, 21), + + __SWM_PIN(56, N, 0), + __SWM_PIN(57, N, 1), + __SWM_PIN(58, N, 2), + __SWM_PIN(59, N, 3), + __SWM_PIN(60, N, 4), + __SWM_PIN(61, N, 5), + __SWM_PIN(62, N, 6), + __SWM_PIN(63, N, 7), + __SWM_PIN(64, N, 8), + __SWM_PIN(65, N, 9), + __SWM_PIN(66, N, 10), + __SWM_PIN(67, N, 11), + __SWM_PIN(68, N, 12), + __SWM_PIN(69, N, 13), + __SWM_PIN(70, N, 14), + __SWM_PIN(71, N, 15), + __SWM_PIN(72, N, 16), + __SWM_PIN(73, N, 17), + __SWM_PIN(74, N, 18), + __SWM_PIN(75, N, 19), + + __SWM_PIN(76, P, 0), + __SWM_PIN(77, P, 1), + __SWM_PIN(78, P, 2), + __SWM_PIN(79, P, 3), + __SWM_PIN(80, P, 4), + __SWM_PIN(81, P, 5), + __SWM_PIN(82, P, 6), + __SWM_PIN(83, P, 7), + __SWM_PIN(84, P, 8), + __SWM_PIN(85, P, 9), + __SWM_PIN(86, P, 10), + __SWM_PIN(87, P, 11), + __SWM_PIN(88, P, 12), + __SWM_PIN(89, P, 13), + __SWM_PIN(90, P, 14), + __SWM_PIN(91, P, 15), + __SWM_PIN(92, P, 16), + __SWM_PIN(93, P, 17), + __SWM_PIN(94, P, 18), + __SWM_PIN(95, P, 19), + __SWM_PIN(96, P, 20), + __SWM_PIN(97, P, 21), + __SWM_PIN(98, P, 22), + __SWM_PIN(99, P, 23)}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = + { + {0, 0, RT_NULL, RT_NULL}, + {1, 0, RT_NULL, RT_NULL}, + {2, 0, RT_NULL, RT_NULL}, + {3, 0, RT_NULL, RT_NULL}, + {4, 0, RT_NULL, RT_NULL}, + {5, 0, RT_NULL, RT_NULL}, + {6, 0, RT_NULL, RT_NULL}, + {7, 0, RT_NULL, RT_NULL}, + {8, 0, RT_NULL, RT_NULL}, + {9, 0, RT_NULL, RT_NULL}, + {10, 0, RT_NULL, RT_NULL}, + {11, 0, RT_NULL, RT_NULL}, + {12, 0, RT_NULL, RT_NULL}, + {13, 0, RT_NULL, RT_NULL}, + {14, 0, RT_NULL, RT_NULL}, + {15, 0, RT_NULL, RT_NULL}, + {16, 0, RT_NULL, RT_NULL}, + {17, 0, RT_NULL, RT_NULL}, + {18, 0, RT_NULL, RT_NULL}, + {19, 0, RT_NULL, RT_NULL}, + {20, 0, RT_NULL, RT_NULL}, + {21, 0, RT_NULL, RT_NULL}, + {22, 0, RT_NULL, RT_NULL}, + {23, 0, RT_NULL, RT_NULL}, + {24, 0, RT_NULL, RT_NULL}, + {25, 0, RT_NULL, RT_NULL}, + {26, 0, RT_NULL, RT_NULL}, + {27, 0, RT_NULL, RT_NULL}, + {28, 0, RT_NULL, RT_NULL}, + {29, 0, RT_NULL, RT_NULL}, + {30, 0, RT_NULL, RT_NULL}, + {31, 0, RT_NULL, RT_NULL}, + {32, 0, RT_NULL, RT_NULL}, + {33, 0, RT_NULL, RT_NULL}, + {34, 0, RT_NULL, RT_NULL}, + {35, 0, RT_NULL, RT_NULL}, + {36, 0, RT_NULL, RT_NULL}, + {37, 0, RT_NULL, RT_NULL}, + {38, 0, RT_NULL, RT_NULL}, + {39, 0, RT_NULL, RT_NULL}, + {40, 0, RT_NULL, RT_NULL}, + {41, 0, RT_NULL, RT_NULL}, + {42, 0, RT_NULL, RT_NULL}, + {43, 0, RT_NULL, RT_NULL}, + {44, 0, RT_NULL, RT_NULL}, + {45, 0, RT_NULL, RT_NULL}, + {46, 0, RT_NULL, RT_NULL}, + {47, 0, RT_NULL, RT_NULL}, + {48, 0, RT_NULL, RT_NULL}, + {49, 0, RT_NULL, RT_NULL}, + {50, 0, RT_NULL, RT_NULL}, + {51, 0, RT_NULL, RT_NULL}, + {52, 0, RT_NULL, RT_NULL}, + {53, 0, RT_NULL, RT_NULL}, + {54, 0, RT_NULL, RT_NULL}, + {55, 0, RT_NULL, RT_NULL}, + {56, 0, RT_NULL, RT_NULL}, + {57, 0, RT_NULL, RT_NULL}, + {58, 0, RT_NULL, RT_NULL}, + {59, 0, RT_NULL, RT_NULL}, + {60, 0, RT_NULL, RT_NULL}, + {61, 0, RT_NULL, RT_NULL}, + {62, 0, RT_NULL, RT_NULL}, + {63, 0, RT_NULL, RT_NULL}, + {64, 0, RT_NULL, RT_NULL}, + {65, 0, RT_NULL, RT_NULL}, + {66, 0, RT_NULL, RT_NULL}, + {67, 0, RT_NULL, RT_NULL}, + {68, 0, RT_NULL, RT_NULL}, + {69, 0, RT_NULL, RT_NULL}, + {70, 0, RT_NULL, RT_NULL}, + {71, 0, RT_NULL, RT_NULL}, + {72, 0, RT_NULL, RT_NULL}, + {73, 0, RT_NULL, RT_NULL}, + {74, 0, RT_NULL, RT_NULL}, + {75, 0, RT_NULL, RT_NULL}, + {76, 0, RT_NULL, RT_NULL}, + {77, 0, RT_NULL, RT_NULL}, + {78, 0, RT_NULL, RT_NULL}, + {79, 0, RT_NULL, RT_NULL}, + {80, 0, RT_NULL, RT_NULL}, + {81, 0, RT_NULL, RT_NULL}, + {82, 0, RT_NULL, RT_NULL}, + {83, 0, RT_NULL, RT_NULL}, + {84, 0, RT_NULL, RT_NULL}, + {85, 0, RT_NULL, RT_NULL}, + {86, 0, RT_NULL, RT_NULL}, + {87, 0, RT_NULL, RT_NULL}, + {88, 0, RT_NULL, RT_NULL}, + {89, 0, RT_NULL, RT_NULL}, + {90, 0, RT_NULL, RT_NULL}, + {91, 0, RT_NULL, RT_NULL}, + {92, 0, RT_NULL, RT_NULL}, + {93, 0, RT_NULL, RT_NULL}, + {94, 0, RT_NULL, RT_NULL}, + {95, 0, RT_NULL, RT_NULL}, + {96, 0, RT_NULL, RT_NULL}, + {97, 0, RT_NULL, RT_NULL}, + {98, 0, RT_NULL, RT_NULL}, + {99, 0, RT_NULL, RT_NULL}}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static const struct swm_pin_index *get_pin(uint8_t pin) +{ + const struct swm_pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->gpio == GPIO0) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +} + +static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct swm_pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + if (value) + { + GPIO_SetBit(index->gpio, index->pin); + } + else + { + GPIO_ClrBit(index->gpio, index->pin); + } +} + +static int swm_pin_read(rt_device_t dev, rt_base_t pin) +{ + const struct swm_pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return PIN_LOW; + } + return (int)GPIO_GetBit(index->gpio, index->pin); +} + +static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct swm_pin_index *index; + int dir = 0; + int pull_up = 0; + int pull_down = 0; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + /* Configure GPIO_InitStructure */ + switch (mode) + { + case PIN_MODE_OUTPUT: + /* output setting */ + dir = 1; + break; + case PIN_MODE_INPUT: + /* input setting: not pull. */ + dir = 0; + break; + case PIN_MODE_INPUT_PULLUP: + /* input setting: pull up. */ + dir = 0; + pull_up = 1; + break; + case PIN_MODE_INPUT_PULLDOWN: + /* input setting: pull down. */ + dir = 0; + pull_down = 1; + break; + case PIN_MODE_OUTPUT_OD: + /* output setting: od. */ + dir = 1; + pull_up = 1; + break; + } + + GPIO_Init(index->gpio, index->pin, dir, pull_up, pull_down); +} + +static rt_err_t swm_pin_attach_irq(struct rt_device *device, + rt_int32_t pin, + rt_uint32_t mode, + void (*hdr)(void *args), + void *args) +{ + const struct swm_pin_index *index; + rt_base_t level; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[pin].pin == pin && + pin_irq_hdr_tab[pin].mode == mode && + pin_irq_hdr_tab[pin].hdr == hdr && + pin_irq_hdr_tab[pin].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[pin].pin = pin; + pin_irq_hdr_tab[pin].mode = mode; + pin_irq_hdr_tab[pin].hdr = hdr; + pin_irq_hdr_tab[pin].args = args; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct swm_pin_index *index; + rt_base_t level; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + pin_irq_hdr_tab[pin].mode = 0; + pin_irq_hdr_tab[pin].hdr = RT_NULL; + pin_irq_hdr_tab[pin].args = RT_NULL; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t swm_pin_irq_enable(struct rt_device *device, + rt_base_t pin, + rt_uint32_t enabled) +{ + const struct swm_pin_index *index; + rt_base_t level = 0; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + switch (pin_irq_hdr_tab[pin].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_Init(index->gpio, index->pin, 0, 0, 1); + EXTI_Init(index->gpio, index->pin, EXTI_RISE_EDGE); + break; + case PIN_IRQ_MODE_FALLING: + GPIO_Init(index->gpio, index->pin, 0, 1, 0); + EXTI_Init(index->gpio, index->pin, EXTI_FALL_EDGE); + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_Init(index->gpio, index->pin, 0, 1, 1); + EXTI_Init(index->gpio, index->pin, EXTI_BOTH_EDGE); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + GPIO_Init(index->gpio, index->pin, 0, 0, 1); + EXTI_Init(index->gpio, index->pin, EXTI_HIGH_LEVEL); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + GPIO_Init(index->gpio, index->pin, 0, 1, 0); + EXTI_Init(index->gpio, index->pin, EXTI_LOW_LEVEL); + break; + default: + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + NVIC_EnableIRQ(index->irq); + EXTI_Open(index->gpio, index->pin); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + level = rt_hw_interrupt_disable(); + NVIC_DisableIRQ(index->irq); + EXTI_Close(index->gpio, index->pin); + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops swm_pin_ops = + { + .pin_mode = swm_pin_mode, + .pin_write = swm_pin_write, + .pin_read = swm_pin_read, + .pin_attach_irq = swm_pin_attach_irq, + .pin_detach_irq = swm_pin_detach_irq, + .pin_irq_enable = swm_pin_irq_enable}; + +static void rt_hw_pin_isr(GPIO_TypeDef *GPIOx) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + const struct swm_pin_index *pin; + + if (init == 0) + { + init = 1; + for (pin = &pins[0]; + pin->index < ITEM_NUM(pins); + pin++) + { + if (pin->gpio == GPIOx) + { + gpio[index] = pin->index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (EXTI_State(pin->gpio, pin->pin)) + { + EXTI_Clear(pin->gpio, pin->pin); + if (pin_irq_hdr_tab[pin->index].hdr) + { + pin_irq_hdr_tab[pin->index].hdr(pin_irq_hdr_tab[pin->index].args); + } + } + } +} +void GPIOA_Handler(void) +{ + rt_interrupt_enter(); + rt_hw_pin_isr(GPIOA); + rt_interrupt_leave(); +} + +void GPIOB_Handler(void) +{ + rt_interrupt_enter(); + rt_hw_pin_isr(GPIOB); + rt_interrupt_leave(); +} + +void GPIOC_Handler(void) +{ + rt_interrupt_enter(); + rt_hw_pin_isr(GPIOC); + rt_interrupt_leave(); +} + +void GPIOM_Handler(void) +{ + rt_interrupt_enter(); + rt_hw_pin_isr(GPIOM); + rt_interrupt_leave(); +} + +void GPION_Handler(void) +{ + rt_interrupt_enter(); + rt_hw_pin_isr(GPION); + rt_interrupt_leave(); +} + +void GPIOP_Handler(void) +{ + rt_interrupt_enter(); + rt_hw_pin_isr(GPIOP); + rt_interrupt_leave(); +} + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &swm_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* BSP_USING_GPIO */ +#endif /* RT_USING_PIN */ diff --git a/bsp/swm320/drivers/drv_gpio.h b/bsp/swm320/drivers/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..9e67c2127f3a983a47426034f3f8f29745bcf046 --- /dev/null +++ b/bsp/swm320/drivers/drv_gpio.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include "board.h" + +#define __SWM_PIN(index, gpio, pin_index) \ + { \ + index, GPIO##gpio, PIN##pin_index, GPIO##gpio##_IRQn \ + } +#define GPIO0 ((GPIO_TypeDef *)(0)) +#define GPIO0_IRQn (GPIOA0_IRQn) + +struct swm_pin_index +{ + uint32_t index; + GPIO_TypeDef *gpio; + uint32_t pin; + IRQn_Type irq; +}; +typedef struct swm_pin_index pin_t; + +int rt_hw_pin_init(void); + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/swm320/drivers/drv_hwtimer.c b/bsp/swm320/drivers/drv_hwtimer.c new file mode 100644 index 0000000000000000000000000000000000000000..6881b7170e51fbce343438b3fa99a4f8e108672e --- /dev/null +++ b/bsp/swm320/drivers/drv_hwtimer.c @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file + */ + +#include "drv_hwtimer.h" + +#ifdef RT_USING_HWTIMER +#ifdef BSP_USING_TIM + +enum +{ +#ifdef BSP_USING_TIM0 + TIM0_INDEX, +#endif +#ifdef BSP_USING_TIM1 + TIM1_INDEX, +#endif +#ifdef BSP_USING_TIM2 + TIM2_INDEX, +#endif +#ifdef BSP_USING_TIM3 + TIM3_INDEX, +#endif +#ifdef BSP_USING_TIM4 + TIM4_INDEX, +#endif +#ifdef BSP_USING_TIM5 + TIM5_INDEX, +#endif +}; + +static struct swm_hwtimer_cfg hwtimer_cfg[] = + { +#ifdef BSP_USING_TIM0 + TIM0_CFG, +#endif +#ifdef BSP_USING_TIM1 + TIM1_CFG, +#endif +#ifdef BSP_USING_TIM2 + TIM2_CFG, +#endif +#ifdef BSP_USING_TIM3 + TIM3_CFG, +#endif +#ifdef BSP_USING_TIM4 + TIM4_CFG, +#endif +#ifdef BSP_USING_TIM5 + TIM5_CFG, +#endif +}; + +static struct swm_hwtimer hwtimer_drv[sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0])] = {0}; + +static void swm_timer_init(struct rt_hwtimer_device *timer_device, rt_uint32_t state) +{ + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + + if (state) + { + cfg = timer_device->parent.user_data; + TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1); + timer_device->freq = SystemCoreClock; + } +} + +static rt_err_t swm_timer_start(rt_hwtimer_t *timer_device, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +{ + rt_err_t result = RT_EOK; + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; + + if (opmode == HWTIMER_MODE_ONESHOT) + { + /* set timer to single mode */ + timer_device->mode = HWTIMER_MODE_ONESHOT; + } + else + { + timer_device->mode = HWTIMER_MODE_PERIOD; + } + TIMR_SetPeriod(cfg->TIMRx, cnt); + TIMR_Stop(cfg->TIMRx); + TIMR_Start(cfg->TIMRx); + + return result; +} + +static void swm_timer_stop(rt_hwtimer_t *timer_device) +{ + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; + + /* stop timer */ + TIMR_Stop(cfg->TIMRx); +} + +static rt_uint32_t swm_timer_count_get(rt_hwtimer_t *timer_device) +{ + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; + + return TIMR_GetCurValue(cfg->TIMRx); +} + +static rt_err_t swm_timer_ctrl(rt_hwtimer_t *timer_device, rt_uint32_t cmd, void *args) +{ + struct swm_hwtimer_cfg *cfg = RT_NULL; + rt_err_t result = RT_EOK; + RT_ASSERT(timer_device != RT_NULL); + RT_ASSERT(args != RT_NULL); + cfg = timer_device->parent.user_data; + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + rt_uint32_t freq; + freq = *(rt_uint32_t *)args; + + TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1); + } + break; + default: + { + result = -RT_ENOSYS; + } + break; + } + + return result; +} + +static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; + +static struct rt_hwtimer_ops swm_hwtimer_ops = + { + .init = swm_timer_init, + .start = swm_timer_start, + .stop = swm_timer_stop, + .count_get = swm_timer_count_get, + .control = swm_timer_ctrl}; + +void rt_hw_hwtimer_isr(rt_hwtimer_t *timer_device) +{ + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; + + TIMR_INTClr(cfg->TIMRx); + rt_device_hwtimer_isr(timer_device); +} +#ifdef BSP_USING_TIM0 +void TIMR0_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM0_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM0 + +#ifdef BSP_USING_TIM1 +void TIMR1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM1_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM1 + +#ifdef BSP_USING_TIM2 +void TIMR2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM2_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM2 + +#ifdef BSP_USING_TIM3 +void TIMR3_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM3_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM3 + +#ifdef BSP_USING_TIM4 +void TIMR4_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM4_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM4 + +#ifdef BSP_USING_TIM5 +void TIMR5_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM5_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM5 + +static int rt_hw_hwtimer_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0]); i++) + { + hwtimer_drv[i].cfg = &hwtimer_cfg[i]; + hwtimer_drv[i].time_device.info = &_info; + hwtimer_drv[i].time_device.ops = &swm_hwtimer_ops; + if (rt_device_hwtimer_register(&hwtimer_drv[i].time_device, hwtimer_drv[i].cfg->name, hwtimer_drv[i].cfg) == RT_EOK) + { + ; + } + else + { + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_hwtimer_init); + +#endif /* BSP_USING_TIM */ +#endif /* RT_USING_HWTIMER */ diff --git a/bsp/swm320/drivers/drv_hwtimer.h b/bsp/swm320/drivers/drv_hwtimer.h new file mode 100644 index 0000000000000000000000000000000000000000..05d586ac443f90e7d31c26a4425128f9c245d81d --- /dev/null +++ b/bsp/swm320/drivers/drv_hwtimer.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_HWTIMER_H__ +#define __DRV_HWTIMER_H__ + +#include "board.h" + +struct swm_hwtimer_cfg +{ + char *name; + TIMR_TypeDef *TIMRx; +}; + +struct swm_hwtimer +{ + struct swm_hwtimer_cfg *cfg; + rt_hwtimer_t time_device; +}; + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 120000000, \ + .minfreq = 120000000, \ + .maxcnt = 0xFFFFFFFF, \ + .cntmode = HWTIMER_CNTMODE_DW, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM0 +#ifndef TIM0_CFG +#define TIM0_CFG \ + { \ + .name = "timer0", \ + .TIMRx = TIMR0, \ + } +#endif /* TIM0_CFG */ +#endif /* BSP_USING_TIM0 */ + +#ifdef BSP_USING_TIM1 +#ifndef TIM1_CFG +#define TIM1_CFG \ + { \ + .name = "timer1", \ + .TIMRx = TIMR1, \ + } +#endif /* TIM1_CFG */ +#endif /* BSP_USING_TIM1 */ + +#ifdef BSP_USING_TIM2 +#ifndef TIM2_CFG +#define TIM2_CFG \ + { \ + .name = "timer2", \ + .TIMRx = TIMR2, \ + } +#endif /* TIM2_CFG */ +#endif /* BSP_USING_TIM2 */ + +#ifdef BSP_USING_TIM3 +#ifndef TIM3_CFG +#define TIM3_CFG \ + { \ + .name = "timer3", \ + .TIMRx = TIMR3, \ + } +#endif /* TIM3_CFG */ +#endif /* BSP_USING_TIM3 */ + +#ifdef BSP_USING_TIM4 +#ifndef TIM4_CFG +#define TIM4_CFG \ + { \ + .name = "timer4", \ + .TIMRx = TIMR4, \ + } +#endif /* TIM4_CFG */ +#endif /* BSP_USING_TIM4 */ + +#ifdef BSP_USING_TIM5 +#ifndef TIM5_CFG +#define TIM5_CFG \ + { \ + .name = "timer5", \ + .TIMRx = TIMR5, \ + } +#endif /* TIM5_CFG */ +#endif /* BSP_USING_TIM5 */ + +int rt_hw_hwtimer_init(void); + +#endif /* __DRV_HWTIMER_H__ */ diff --git a/bsp/swm320/drivers/drv_log.h b/bsp/swm320/drivers/drv_log.h new file mode 100644 index 0000000000000000000000000000000000000000..71ee310d3a10cd4f0fa2a2e4f96954ec032d4cdb --- /dev/null +++ b/bsp/swm320/drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-15 SummerGift first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/swm320/drivers/drv_nor_flash.c b/bsp/swm320/drivers/drv_nor_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..6940cd54d0f80f1bc31659ae29af31680fbbebc7 --- /dev/null +++ b/bsp/swm320/drivers/drv_nor_flash.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik rewrite + */ + +#include "drv_nor_flash.h" + +#ifdef BSP_USING_NOR_FLASH + +#define DRV_DEBUG +#define LOG_TAG "drv.norflash" +#include + +static struct rt_mutex flash_lock; + +/* RT-Thread MTD device interface */ +static long swm_norflash_read_id(struct rt_mtd_nor_device *device) +{ + return 0xdeadbeef; +} + +static rt_size_t swm_norflash_read(struct rt_mtd_nor_device *device, + rt_off_t position, + rt_uint8_t *data, + rt_uint32_t size) +{ + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); + memcpy(data, ((const void *)(NORFLM_BASE + position)), size); + rt_mutex_release(&flash_lock); + return size; +} + +static rt_size_t swm_norflash_write(struct rt_mtd_nor_device *device, + rt_off_t position, + const rt_uint8_t *data, + rt_uint32_t size) +{ + rt_size_t i; + const rt_uint16_t *hwdata = (const rt_uint16_t *)data; + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); + for (i = 0; i < size / 2; i++) + { + NORFL_Write(position, hwdata[i]); + position += 2; + } + rt_mutex_release(&flash_lock); + return size; +} + +static rt_err_t swm_norflash_erase_block(struct rt_mtd_nor_device *device, + rt_off_t offset, + rt_uint32_t length) +{ + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); + NORFL_SectorErase(offset); + rt_mutex_release(&flash_lock); + return RT_EOK; +} + +const static struct rt_mtd_nor_driver_ops mtd_ops = + { + swm_norflash_read_id, + swm_norflash_read, + swm_norflash_write, + swm_norflash_erase_block}; + +static struct rt_mtd_nor_device mtd; +int rt_hw_norflash_init(void) +{ + NORFL_InitStructure NORFL_InitStruct; + + PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23 + PORT->PORTP_SEL1 = 0xAAAA; + + PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0 + PORT->PORTM_INEN = 0xFFFF; + + PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN、PM17 => WEN、PM18 => NORFL_CSN、PM19 => SDRAM_CSN、PM20 => SRAM_CSN、PM21 => SDRAM_CKE + + NORFL_InitStruct.DataWidth = 16; + NORFL_InitStruct.WELowPulseTime = 5; + NORFL_InitStruct.OEPreValidTime = 12; + NORFL_InitStruct.OperFinishIEn = 0; + NORFL_InitStruct.OperTimeoutIEn = 0; + NORFL_Init(&NORFL_InitStruct); + + /* set page size and block size */ + mtd.block_size = BLOCK_SIZE; /* 64kByte */ + mtd.ops = &mtd_ops; + + /* initialize mutex */ + if (rt_mutex_init(&flash_lock, "nor", RT_IPC_FLAG_FIFO) != RT_EOK) + { + rt_kprintf("init sd lock mutex failed\n"); + return -RT_ERROR; + } + mtd.block_start = 0; + mtd.block_end = BLOCK_COUNTER; + + /* register MTD device */ + rt_mtd_nor_register_device("nor", &mtd); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_norflash_init); + +#endif /* BSP_USING_NOR_FLASH */ diff --git a/bsp/swm320/drivers/drv_nor_flash.h b/bsp/swm320/drivers/drv_nor_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..170917c44d906616df0d9b1f5777a8a17299b0ca --- /dev/null +++ b/bsp/swm320/drivers/drv_nor_flash.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef DRV_NOR_FLASH_H__ +#define DRV_NOR_FLASH_H__ + +#include "board.h" + +#define BLOCK_SIZE (64 * 1024) +#define FLASH_SIZE (BSP_NOR_FLASH_SIZE) +#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE) + +int rt_hw_norflash_init(void); + +#endif diff --git a/bsp/swm320/drivers/drv_pwm.c b/bsp/swm320/drivers/drv_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..23b2aeca0f741da7a221b3022c7bed7317123286 --- /dev/null +++ b/bsp/swm320/drivers/drv_pwm.c @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file + */ + +#include "drv_pwm.h" + +#ifdef RT_USING_PWM +#ifdef BSP_USING_PWM + +//#define DRV_DEBUG +#define LOG_TAG "drv.pwm" +#include + +#define MIN_PERIOD 2 +#define MIN_PULSE 1 + +static struct swm_pwm_cfg pwm_cfg[] = + { +#ifdef BSP_USING_PWM0 + PWM0_CFG, +#endif +#ifdef BSP_USING_PWM1 + PWM1_CFG, +#endif +#ifdef BSP_USING_PWM2 + PWM2_CFG, +#endif +#ifdef BSP_USING_PWM3 + PWM3_CFG, +#endif +#ifdef BSP_USING_PWM4 + PWM4_CFG, +#endif +#ifdef BSP_USING_PWM5 + PWM5_CFG, +#endif +}; + +static struct swm_pwm pwm_drv[sizeof(pwm_cfg) / sizeof(pwm_cfg[0])] = {0}; + +static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg); +static struct rt_pwm_ops pwm_ops = + { + swm_pwm_control}; + +static rt_err_t swm_pwm_enable(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + struct swm_pwm_cfg *cfg = RT_NULL; + RT_ASSERT(pwm_device != RT_NULL); + cfg = pwm_device->parent.user_data; + + if (!enable) + { + if (PWM_CH_A == configuration->channel) + { + PWM_Stop(cfg->PWMx, 1, 0); + } + if (PWM_CH_B == configuration->channel) + { + PWM_Stop(cfg->PWMx, 0, 1); + } + } + else + { + if (PWM_CH_A == configuration->channel) + { + PWM_Start(cfg->PWMx, 1, 0); + } + if (PWM_CH_B == configuration->channel) + { + PWM_Start(cfg->PWMx, 0, 1); + } + } + + return RT_EOK; +} + +static rt_err_t swm_pwm_get(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration) +{ + rt_uint64_t tim_clock; + tim_clock = SystemCoreClock / 8; + + struct swm_pwm_cfg *cfg = RT_NULL; + RT_ASSERT(pwm_device != RT_NULL); + cfg = pwm_device->parent.user_data; + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + tim_clock /= 1000000UL; + configuration->period = PWM_GetCycle(cfg->PWMx, configuration->channel) * 1000UL / tim_clock; + configuration->pulse = PWM_GetHDuty(cfg->PWMx, configuration->channel) * 1000UL / tim_clock; + + return RT_EOK; +} + +static rt_err_t swm_pwm_set(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + rt_uint64_t tim_clock; + tim_clock = SystemCoreClock / 8; + + struct swm_pwm_cfg *cfg = RT_NULL; + RT_ASSERT(pwm_device != RT_NULL); + cfg = pwm_device->parent.user_data; + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + /* when SystemCoreClock = 120MHz, configuration->period max 4.369ms */ + /* when SystemCoreClock = 20MHz, configuration->period max 26.214ms */ + tim_clock /= 1000000UL; + period = (unsigned long long)configuration->period * tim_clock / 1000ULL; + pulse = (unsigned long long)configuration->pulse * tim_clock / 1000ULL; + if (period < MIN_PERIOD) + { + period = MIN_PERIOD; + } + if (pulse < MIN_PULSE) + { + pulse = MIN_PULSE; + } + PWM_SetCycle(cfg->PWMx, configuration->channel, period); + PWM_SetHDuty(cfg->PWMx, configuration->channel, pulse); + + return RT_EOK; +} + +static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg) +{ + RT_ASSERT(pwm_device != RT_NULL); + + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return swm_pwm_enable(pwm_device, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return swm_pwm_enable(pwm_device, configuration, RT_FALSE); + case PWM_CMD_SET: + return swm_pwm_set(pwm_device, configuration); + case PWM_CMD_GET: + return swm_pwm_get(pwm_device, configuration); + default: + return RT_EINVAL; + } +} + +int rt_hw_pwm_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(pwm_cfg) / sizeof(pwm_cfg[0]); i++) + { + pwm_drv[i].cfg = &pwm_cfg[i]; + + if (pwm_drv[i].cfg->PWMx == PWM0) + { +#ifdef BSP_USING_PWM0A + PORT_Init(PORTC, PIN2, FUNMUX0_PWM0A_OUT, 0); +#endif +#ifdef BSP_USING_PWM0B + PORT_Init(PORTC, PIN4, FUNMUX0_PWM0B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM1) + { +#ifdef BSP_USING_PWM1A + PORT_Init(PORTC, PIN3, FUNMUX1_PWM1A_OUT, 0); +#endif +#ifdef BSP_USING_PWM1B + PORT_Init(PORTC, PIN5, FUNMUX1_PWM1B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM2) + { +#ifdef BSP_USING_PWM2A + PORT_Init(PORTN, PIN4, FUNMUX0_PWM2A_OUT, 0); +#endif +#ifdef BSP_USING_PWM2B + PORT_Init(PORTN, PIN6, FUNMUX0_PWM2B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM3) + { +#ifdef BSP_USING_PWM3A + PORT_Init(PORTN, PIN3, FUNMUX1_PWM3A_OUT, 0); +#endif +#ifdef BSP_USING_PWM3B + PORT_Init(PORTN, PIN5, FUNMUX1_PWM3B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM4) + { +#ifdef BSP_USING_PWM4A + PORT_Init(PORTN, PIN8, FUNMUX0_PWM4A_OUT, 0); +#endif +#ifdef BSP_USING_PWM4B + PORT_Init(PORTN, PIN10, FUNMUX0_PWM4B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM5) + { +#ifdef BSP_USING_PWM5A + PORT_Init(PORTN, PIN7, FUNMUX1_PWM5A_OUT, 0); +#endif +#ifdef BSP_USING_PWM5B + PORT_Init(PORTN, PIN9, FUNMUX1_PWM5B_OUT, 0); +#endif + } + + PWM_Init(pwm_drv[i].cfg->PWMx, &(pwm_drv[i].cfg->pwm_initstruct)); + if (rt_device_pwm_register(&pwm_drv[i].pwm_device, pwm_drv[i].cfg->name, &pwm_ops, pwm_drv[i].cfg) == RT_EOK) + { + LOG_D("%s register success", pwm_drv[i].cfg->name); + } + else + { + LOG_E("%s register failed", pwm_drv[i].cfg->name); + result = -RT_ERROR; + } + } + return result; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif /* BSP_USING_PWM */ +#endif /* RT_USING_PWM */ diff --git a/bsp/swm320/drivers/drv_pwm.h b/bsp/swm320/drivers/drv_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..0e27cb2e7b0ffefa2efddac6061e97df1806def2 --- /dev/null +++ b/bsp/swm320/drivers/drv_pwm.h @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_PWM_H__ +#define __DRV_PWM_H__ + +#include "board.h" + +struct swm_pwm_cfg +{ + const char *name; + PWM_TypeDef *PWMx; + PWM_InitStructure pwm_initstruct; +}; + +struct swm_pwm +{ + struct swm_pwm_cfg *cfg; + struct rt_device_pwm pwm_device; +}; + +#ifdef BSP_USING_PWM0 +#ifndef PWM0_CFG +#define PWM0_CFG \ + { \ + .name = "pwm0", \ + .PWMx = PWM0, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM0_CFG */ +#endif /* BSP_USING_PWM0 */ + +#ifdef BSP_USING_PWM1 +#ifndef PWM1_CFG +#define PWM1_CFG \ + { \ + .name = "pwm1", \ + .PWMx = PWM1, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM1_CFG */ +#endif /* BSP_USING_PWM1 */ + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CFG +#define PWM2_CFG \ + { \ + .name = "pwm2", \ + .PWMx = PWM2, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM2_CFG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CFG +#define PWM3_CFG \ + { \ + .name = "pwm3", \ + .PWMx = PWM3, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM3_CFG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CFG +#define PWM4_CFG \ + { \ + .name = "pwm4", \ + .PWMx = PWM4, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM4_CFG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CFG +#define PWM5_CFG \ + { \ + .name = "pwm5", \ + .PWMx = PWM5, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM5_CFG */ +#endif /* BSP_USING_PWM5 */ + +int rt_hw_pwm_init(void); + +#endif /* __DRV_PWM_H__ */ diff --git a/bsp/swm320/drivers/drv_rtc.c b/bsp/swm320/drivers/drv_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..c8c80ed4ca7a7344ad6e06002c71945cb8226557 --- /dev/null +++ b/bsp/swm320/drivers/drv_rtc.c @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file + */ + +#include "drv_rtc.h" + +#ifdef RT_USING_RTC +#ifdef BSP_USING_RTC + +//#define DRV_DEBUG +#define LOG_TAG "drv.rtc" +#include + +static struct rt_device rtc_device; + +static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) +{ + uint32_t i, cnt = 0; + const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + + for (i = 1; i < month; i++) + cnt += daysOfMonth[i]; + + cnt += date; + + if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3)) + cnt += 1; + + cnt += (year - 1901) * 365; + + for (i = 1901; i < year; i++) + { + if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0))) + cnt += 1; + } + + return (cnt + 1) % 7; +} + +static time_t swm_get_rtc_time_stamp(void) +{ + RTC_DateTime get_datetime = {0}; + struct tm tm_new; + + RTC_GetDateTime(RTC, &get_datetime); + + tm_new.tm_sec = get_datetime.Second; + tm_new.tm_min = get_datetime.Minute; + tm_new.tm_hour = get_datetime.Hour; + tm_new.tm_mday = get_datetime.Date; + tm_new.tm_mon = get_datetime.Month - 1; + tm_new.tm_year = get_datetime.Year - 1900; + + LOG_D("get rtc time."); + return mktime(&tm_new); +} +static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp) +{ + RTC_DateTime set_datetime = {0}; + struct tm *p_tm; + + p_tm = gmtime(&time_stamp); + + set_datetime.Second = p_tm->tm_sec; + set_datetime.Minute = p_tm->tm_min; + set_datetime.Hour = p_tm->tm_hour; + set_datetime.Date = p_tm->tm_mday; + set_datetime.Month = p_tm->tm_mon + 1; + set_datetime.Year = p_tm->tm_year + 1900; + // datetime.Day = p_tm->tm_wday; + + RTC_Stop(RTC); + while (RTC->CFGABLE == 0) + ; + RTC->MINSEC = (set_datetime.Second << RTC_MINSEC_SEC_Pos) | + (set_datetime.Minute << RTC_MINSEC_MIN_Pos); + RTC->DATHUR = (set_datetime.Hour << RTC_DATHUR_HOUR_Pos) | + ((set_datetime.Date) << RTC_DATHUR_DATE_Pos); + RTC->MONDAY = (calcWeekDay(set_datetime.Year, set_datetime.Month, set_datetime.Date) + << RTC_MONDAY_DAY_Pos) | + ((set_datetime.Month) << RTC_MONDAY_MON_Pos); + RTC->YEAR = set_datetime.Year - 1901; + RTC->LOAD = 1 << RTC_LOAD_TIME_Pos; + RTC_Start(RTC); + + LOG_D("set rtc time."); + return RT_EOK; +} + +static rt_err_t swm_rtc_control(rt_device_t rtc_device, int cmd, void *args) +{ + rt_err_t result = RT_EOK; + RT_ASSERT(rtc_device != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + *(rt_uint32_t *)args = swm_get_rtc_time_stamp(); + LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); + break; + case RT_DEVICE_CTRL_RTC_SET_TIME: + if (swm_set_rtc_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; + } + LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); + break; + default: + break; + } + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops swm_rtc_ops = + { + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + swm_rtc_control}; +#endif + +static void swm_rtc_init(void) +{ + RTC_InitStructure rtc_initstruct; + + rtc_initstruct.Year = 2020; + rtc_initstruct.Month = 6; + rtc_initstruct.Date = 8; + rtc_initstruct.Hour = 12; + rtc_initstruct.Minute = 0; + rtc_initstruct.Second = 0; + rtc_initstruct.SecondIEn = 0; + rtc_initstruct.MinuteIEn = 0; + RTC_Init(RTC, &rtc_initstruct); + RTC_Start(RTC); +} + +static rt_err_t rt_hw_rtc_register(rt_device_t rtc_device, const char *name, rt_uint32_t flag) +{ + RT_ASSERT(rtc_device != RT_NULL); + + swm_rtc_init(); + +#ifdef RT_USING_DEVICE_OPS + rtc_device->ops = &swm_rtc_ops; +#else + rtc_device->init = RT_NULL; + rtc_device->open = RT_NULL; + rtc_device->close = RT_NULL; + rtc_device->read = RT_NULL; + rtc_device->write = RT_NULL; + rtc_device->control = swm_rtc_control; +#endif + rtc_device->type = RT_Device_Class_RTC; + rtc_device->rx_indicate = RT_NULL; + rtc_device->tx_complete = RT_NULL; + rtc_device->user_data = RT_NULL; + + /* register a character device */ + return rt_device_register(rtc_device, name, flag); +} + +int rt_hw_rtc_init(void) +{ + rt_err_t result; + result = rt_hw_rtc_register(&rtc_device, "rtc", RT_DEVICE_FLAG_RDWR); + if (result != RT_EOK) + { + LOG_E("rtc register err code: %d", result); + return result; + } + LOG_D("rtc init success"); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_RTC */ +#endif /* RT_USING_RTC */ diff --git a/bsp/swm320/drivers/drv_rtc.h b/bsp/swm320/drivers/drv_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..7a649c98af8ad7385c823abd44fd5370f791dd2d --- /dev/null +++ b/bsp/swm320/drivers/drv_rtc.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_RTC_H__ +#define __DRV_RTC_H__ + +#include "board.h" + +int rt_hw_rtc_init(void); + +#endif /* __DRV_RTC_H__ */ diff --git a/bsp/swm320/drivers/drv_sdio.c b/bsp/swm320/drivers/drv_sdio.c new file mode 100644 index 0000000000000000000000000000000000000000..ee59594e60d7037c2ccf31bc1a7545df85184322 --- /dev/null +++ b/bsp/swm320/drivers/drv_sdio.c @@ -0,0 +1,664 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#include "drv_sdio.h" + +#ifdef RT_USING_SDIO +#ifdef BSP_USING_SDIO + +//#define DRV_DEBUG +#define LOG_TAG "drv.sdio" +#include + +static struct rt_mmcsd_host *host; + +#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) +#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex); + +struct rthw_sdio +{ + struct rt_mmcsd_host *host; + struct swm_sdio_des sdio_des; + struct rt_event event; + struct rt_mutex mutex; + struct sdio_pkg *pkg; +}; + +ALIGN(SDIO_ALIGN_LEN) +static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; + +/** + * @brief This function wait sdio completed. + * @param sdio rthw_sdio + * @retval None + */ +static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) +{ + rt_uint32_t status; + struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + + if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + rt_tick_from_millisecond(5000), &status) != RT_EOK) + { + LOG_E("wait completed timeout"); + cmd->err = -RT_ETIMEOUT; + return; + } + + if (sdio->pkg == RT_NULL) + { + return; + } + + if (resp_type(cmd) == RESP_NONE) + { + ; + } + else if (resp_type(cmd) == RESP_R2) + { + cmd->resp[0] = (hw_sdio->RESP[3] << 8) + ((hw_sdio->RESP[2] >> 24) & 0xFF); + cmd->resp[1] = (hw_sdio->RESP[2] << 8) + ((hw_sdio->RESP[1] >> 24) & 0xFF); + cmd->resp[2] = (hw_sdio->RESP[1] << 8) + ((hw_sdio->RESP[0] >> 24) & 0xFF); + cmd->resp[3] = (hw_sdio->RESP[0] << 8) + 0x00; + } + else + { + cmd->resp[0] = hw_sdio->RESP[0]; + } + + if (status & SDIO_IF_ERROR_Msk) + { + if ((status & SDIO_IF_CMDCRCERR_Msk) && (resp_type(cmd) & (RESP_R3 | RESP_R4))) + { + cmd->err = RT_EOK; + } + else + { + cmd->err = -RT_ERROR; + } + + if (status & SDIO_IF_CMDTIMEOUT_Msk) + { + cmd->err = -RT_ETIMEOUT; + } + + if (status & SDIO_IF_DATCRCERR_Msk) + { + data->err = -RT_ERROR; + } + + if (status & SDIO_IF_DATTIMEOUT_Msk) + { + data->err = -RT_ETIMEOUT; + } + + if (cmd->err == RT_EOK) + { + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } + else + { + LOG_D("err:0x%08x, %s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d", + status, + status == 0 ? "NULL" : "", + cmd->cmd_code, + cmd->arg, + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0); + } + } + else + { + cmd->err = RT_EOK; + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } +} + +/** + * @brief This function transfer data by dma. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_transfer(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_data *data; + int size; + void *buff; + + if ((RT_NULL == pkg) || (RT_NULL == sdio)) + { + LOG_E("rthw_sdio_transfer invalid args"); + return; + } + + data = pkg->cmd->data; + if (RT_NULL == data) + { + LOG_E("rthw_sdio_transfer invalid args"); + return; + } + + buff = pkg->buff; + if (RT_NULL == buff) + { + LOG_E("rthw_sdio_transfer invalid args"); + return; + } + + size = data->blks * data->blksize; + + if (data->flags & DATA_DIR_WRITE) + { + sdio->sdio_des.txconfig(pkg, (rt_uint32_t *)buff, size); + } + else if (data->flags & DATA_DIR_READ) + { + sdio->sdio_des.rxconfig(pkg, (rt_uint32_t *)buff, size); + } +} + +/** + * @brief This function send command. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t reg_cmd; + + /* save pkg */ + sdio->pkg = pkg; + + LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d", + cmd->cmd_code, + cmd->arg, + resp_type(cmd) == RESP_NONE ? "NONE" : "", + resp_type(cmd) == RESP_R1 ? "R1" : "", + resp_type(cmd) == RESP_R1B ? "R1B" : "", + resp_type(cmd) == RESP_R2 ? "R2" : "", + resp_type(cmd) == RESP_R3 ? "R3" : "", + resp_type(cmd) == RESP_R4 ? "R4" : "", + resp_type(cmd) == RESP_R5 ? "R5" : "", + resp_type(cmd) == RESP_R6 ? "R6" : "", + resp_type(cmd) == RESP_R7 ? "R7" : "", + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0); + + /* config cmd reg */ + reg_cmd = (cmd->cmd_code << SDIO_CMD_CMDINDX_Pos) | + (0 << SDIO_CMD_CMDTYPE_Pos) | + (0 << SDIO_CMD_IDXCHECK_Pos) | + (0 << SDIO_CMD_CRCCHECK_Pos) | + (0 << SDIO_CMD_DMAEN_Pos); + if (resp_type(cmd) == RESP_NONE) + reg_cmd |= SD_RESP_NO << SDIO_CMD_RESPTYPE_Pos; + else if (resp_type(cmd) == RESP_R2) + reg_cmd |= SD_RESP_128b << SDIO_CMD_RESPTYPE_Pos; + else + reg_cmd |= SD_RESP_32b << SDIO_CMD_RESPTYPE_Pos; + + /* config data reg */ + if (data != RT_NULL) + { + rt_uint32_t dir = 0; + dir = (data->flags & DATA_DIR_READ) ? 1 : 0; + + hw_sdio->BLK = (data->blks << SDIO_BLK_COUNT_Pos) | (data->blksize << SDIO_BLK_SIZE_Pos); + + reg_cmd |= (1 << SDIO_CMD_HAVEDATA_Pos) | + (dir << SDIO_CMD_DIRREAD_Pos) | + ((data->blks > 1) << SDIO_CMD_MULTBLK_Pos) | + ((data->blks > 1) << SDIO_CMD_BLKCNTEN_Pos) | + (0 << SDIO_CMD_AUTOCMD12_Pos); + } + else + { + reg_cmd |= (0 << SDIO_CMD_HAVEDATA_Pos); + } + + if (cmd->cmd_code != SD_IO_SEND_OP_COND) + { + /* send cmd */ + hw_sdio->ARG = cmd->arg; + hw_sdio->CMD = reg_cmd; + } + + /* transfer config */ + if (data != RT_NULL) + { + rthw_sdio_transfer(sdio, pkg); + } + + /* wait completed */ + rthw_sdio_wait_completed(sdio); + + /* clear pkg */ + sdio->pkg = RT_NULL; +} + +/** + * @brief This function send sdio request. + * @param sdio rthw_sdio + * @param req request + * @retval None + */ +static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdio_pkg pkg; + struct rthw_sdio *sdio = host->private_data; + struct rt_mmcsd_data *data; + + RTHW_SDIO_LOCK(sdio); + + if (req->cmd != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + data = req->cmd->data; + pkg.cmd = req->cmd; + + if (data != RT_NULL) + { + rt_uint32_t size = data->blks * data->blksize; + + RT_ASSERT(size <= SDIO_BUFF_SIZE); + + pkg.buff = data->buf; + if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)) + { + pkg.buff = cache_buf; + if (data->flags & DATA_DIR_WRITE) + { + rt_memcpy(cache_buf, data->buf, size); + } + } + } + + rthw_sdio_send_command(sdio, &pkg); + + if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))) + { + rt_memcpy(data->buf, cache_buf, data->blksize * data->blks); + } + } + + if (req->stop != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + pkg.cmd = req->stop; + rthw_sdio_send_command(sdio, &pkg); + } + + RTHW_SDIO_UNLOCK(sdio); + + mmcsd_req_complete(sdio->host); +} + +/** + * @brief This function config sdio. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval None + */ +static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + rt_uint32_t clkcr, div, clk_src; + rt_uint32_t clk = io_cfg->clock; + struct rthw_sdio *sdio = host->private_data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + + clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio); + if (clk_src < 400 * 1000) + { + LOG_E("The clock rate is too low! rata:%d", clk_src); + return; + } + + if (clk > host->freq_max) + clk = host->freq_max; + + if (clk > clk_src) + { + LOG_W("Setting rate is greater than clock source rate."); + clk = clk_src; + } + + LOG_D("clk:%d width:%s%s%s power:%s%s%s", + clk, + io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""); + + RTHW_SDIO_LOCK(sdio); + + hw_sdio->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | (7 << SDIO_CR1_VOLT_Pos); + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) + { + hw_sdio->CR1 |= (1 << SDIO_CR1_8BIT_Pos); + } + else + { + hw_sdio->CR1 &= ~SDIO_CR1_8BIT_Msk; + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + hw_sdio->CR1 |= (1 << SDIO_CR1_4BIT_Pos); + } + else + { + hw_sdio->CR1 &= ~SDIO_CR1_4BIT_Msk; + } + } + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + hw_sdio->CR1 &= ~SDIO_CR1_PWRON_Msk; + break; + case MMCSD_POWER_UP: + case MMCSD_POWER_ON: + hw_sdio->CR1 |= (1 << SDIO_CR1_PWRON_Pos); + break; + default: + LOG_W("unknown power_mode %d", io_cfg->power_mode); + break; + } + + div = clk_src / clk; + if ((clk == 0) || (div == 0)) + { + clkcr = 0; + } + else + { + if (div > 128) + clkcr = 0x80; + else if (div > 64) + clkcr = 0x40; + else if (div > 32) + clkcr = 0x20; + else if (div > 16) + clkcr = 0x10; + else if (div > 8) + clkcr = 0x08; + else if (div > 4) + clkcr = 0x04; + else if (div > 2) + clkcr = 0x02; + else if (div > 1) + clkcr = 0x01; + else + clkcr = 0x00; + } + + SDIO->CR2 = (1 << SDIO_CR2_CLKEN_Pos) | + (1 << SDIO_CR2_SDCLKEN_Pos) | + (clkcr << SDIO_CR2_SDCLKDIV_Pos) | + (0xC << SDIO_CR2_TIMEOUT_Pos); // 2**25 SDIO_CLK + + while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0) + ; + + RTHW_SDIO_UNLOCK(sdio); +} + +/** + * @brief This function delect sdcard. + * @param host rt_mmcsd_host + * @retval 0x01 + */ +static rt_int32_t rthw_sdio_delect(struct rt_mmcsd_host *host) +{ + LOG_D("try to detect device"); + return 0x01; +} + +/** + * @brief This function update sdio interrupt. + * @param host rt_mmcsd_host + * @param enable + * @retval None + */ +void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) +{ + struct rthw_sdio *sdio = host->private_data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + + if (enable) + { + LOG_D("enable sdio irq"); + hw_sdio->IFE = 0xFFFFFFFF; + hw_sdio->IE = 0xFFFF000F; + } + else + { + LOG_D("disable sdio irq"); + hw_sdio->IFE &= ~0xFFFFFFFF; + hw_sdio->IE &= ~0xFFFFFFFF; + } +} + +static const struct rt_mmcsd_host_ops swm_sdio_ops = + { + rthw_sdio_request, + rthw_sdio_iocfg, + rthw_sdio_delect, + rthw_sdio_irq_update, +}; + +struct rt_mmcsd_host *sdio_host_create(struct swm_sdio_des *sdio_des) +{ + struct rt_mmcsd_host *host; + struct rthw_sdio *sdio = RT_NULL; + + if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL)) + { + LOG_E("L:%d F:%s %s %s %s", + (sdio_des == RT_NULL ? "sdio_des is NULL" : ""), + (sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""), + (sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "")); + return RT_NULL; + } + + sdio = rt_malloc(sizeof(struct rthw_sdio)); + if (sdio == RT_NULL) + { + LOG_E("L:%d F:%s malloc rthw_sdio fail"); + return RT_NULL; + } + rt_memset(sdio, 0, sizeof(struct rthw_sdio)); + + host = mmcsd_alloc_host(); + if (host == RT_NULL) + { + LOG_E("L:%d F:%s mmcsd alloc host fail"); + rt_free(sdio); + return RT_NULL; + } + + rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct swm_sdio_des)); + + rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO); + + /* set host defautl attributes */ + host->ops = &swm_sdio_ops; + host->freq_min = 400 * 1000; + host->freq_max = SDIO_MAX_FREQ; + host->valid_ocr = 0X00FFFF80; /* The voltage range supported is 1.65v-3.6v */ +#ifndef SDIO_USING_1_BIT + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#else + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#endif + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; + host->max_blk_count = 512; + + /* link up host and sdio */ + sdio->host = host; + host->private_data = sdio; + + rthw_sdio_irq_update(host, 1); + + /* ready to change */ + mmcsd_change(host); + + return host; +} + +static rt_uint32_t swm_sdio_clock_get(SDIO_TypeDef *hw_sdio) +{ + uint32_t prediv = ((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos); + return (SystemCoreClock / (1 << prediv)); +} + +static rt_err_t swm_sdio_rxconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int size) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + for (uint32_t i = 0; i < data->blks; i++) + { + while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_BUFRDRDY_Msk; + for (uint32_t j = 0; j < data->blksize / 4; j++) + buff[j] = SDIO->DATA; + } + return RT_EOK; +} + +static rt_err_t swm_sdio_txconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int size) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + for (uint32_t i = 0; i < data->blks; i++) + { + while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_BUFWRRDY_Msk; + for (uint32_t j = 0; j < data->blksize / 4; j++) + SDIO->DATA = buff[j]; + } + return RT_EOK; +} + +/** + * @brief This function interrupt process function. + * @param host rt_mmcsd_host + * @retval None + */ +void rthw_sdio_irq_process(struct rt_mmcsd_host *host) +{ + int complete = 0; + struct rthw_sdio *sdio = host->private_data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t intstatus = hw_sdio->IF; + + if (intstatus & SDIO_IF_ERROR_Msk) + { + hw_sdio->IF = 0xFFFFFFFF; + complete = 1; + } + else + { + if (intstatus & SDIO_IF_CMDDONE_Msk) + { + hw_sdio->IF = SDIO_IF_CMDDONE_Msk; + if (sdio->pkg != RT_NULL) + { + if (!sdio->pkg->cmd->data) + { + complete = 1; + } + } + } + + if (intstatus & SDIO_IF_TRXDONE_Msk) + { + hw_sdio->IF = SDIO_IF_TRXDONE_Msk; + complete = 1; + } + } + + if (complete) + { + rt_event_send(&sdio->event, intstatus); + } +} + +void SDIO_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host); + /* leave interrupt */ + rt_interrupt_leave(); +} + +int rt_hw_sdio_init(void) +{ + struct swm_sdio_des sdio_des; + +#if 1 + PORT_Init(PORTB, PIN1, PORTB_PIN1_SD_CLK, 0); + PORT_Init(PORTB, PIN2, PORTB_PIN2_SD_CMD, 1); + PORT_Init(PORTB, PIN3, PORTB_PIN3_SD_D0, 1); + PORT_Init(PORTB, PIN4, PORTB_PIN4_SD_D1, 1); + PORT_Init(PORTB, PIN5, PORTB_PIN5_SD_D2, 1); + PORT_Init(PORTB, PIN6, PORTB_PIN6_SD_D3, 1); +#else + PORT_Init(PORTP, PIN11, PORTP_PIN11_SD_CLK, 0); + PORT_Init(PORTP, PIN10, PORTP_PIN10_SD_CMD, 1); + PORT_Init(PORTP, PIN9, PORTP_PIN9_SD_D0, 1); + PORT_Init(PORTP, PIN8, PORTP_PIN8_SD_D1, 1); + PORT_Init(PORTP, PIN7, PORTP_PIN7_SD_D2, 1); + PORT_Init(PORTP, PIN6, PORTP_PIN6_SD_D3, 1); +#endif + NVIC_EnableIRQ(SDIO_IRQn); + SYS->CLKDIV &= ~SYS_CLKDIV_SDIO_Msk; + if (SystemCoreClock > 80000000) //SDIO时钟需要小于52MHz + SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4 + else + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2 + + SYS->CLKEN |= (0x01 << SYS_CLKEN_SDIO_Pos); + + SDIO->CR2 = (1 << SDIO_CR2_RSTALL_Pos); + + NVIC_EnableIRQ(SDIO_IRQn); + sdio_des.clk_get = swm_sdio_clock_get; + sdio_des.hw_sdio = SDIO; + sdio_des.rxconfig = swm_sdio_rxconfig; + sdio_des.txconfig = swm_sdio_txconfig; + + host = sdio_host_create(&sdio_des); + if (host == RT_NULL) + { + LOG_E("host create fail"); + return -1; + } + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_sdio_init); + +#endif /* BSP_USING_SDIO */ +#endif /* RT_USING_SDIO */ diff --git a/bsp/swm320/drivers/drv_sdio.h b/bsp/swm320/drivers/drv_sdio.h new file mode 100644 index 0000000000000000000000000000000000000000..16f2420344f0216ff5e582cfc86f6a68219d12d3 --- /dev/null +++ b/bsp/swm320/drivers/drv_sdio.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ + +#include "board.h" + +#define SDIO_BUFF_SIZE 4096 +#define SDIO_ALIGN_LEN 4 + +#ifndef SDIO_MAX_FREQ +#define SDIO_MAX_FREQ (30000000) +#endif + +struct sdio_pkg +{ + struct rt_mmcsd_cmd *cmd; + void *buff; + rt_uint32_t flag; +}; + +typedef rt_err_t (*sdio_txconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size); +typedef rt_err_t (*sdio_rxconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size); +typedef rt_uint32_t (*sdio_clk_get)(SDIO_TypeDef *hw_sdio); + +struct swm_sdio_des +{ + SDIO_TypeDef *hw_sdio; + sdio_txconfig txconfig; + sdio_rxconfig rxconfig; + sdio_clk_get clk_get; +}; + +#endif /* __DRV_SDIO_H__ */ diff --git a/bsp/swm320/drivers/drv_soft_i2c.c b/bsp/swm320/drivers/drv_soft_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..d63b7ca35c775666e7819ab5898e93fd6cef4291 --- /dev/null +++ b/bsp/swm320/drivers/drv_soft_i2c.c @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik rewrite + */ + +#include "drv_soft_i2c.h" + +#ifdef RT_USING_I2C +#ifdef BSP_USING_I2C + +/*************************************************************** +*!!!!!!!!!!!!!!!!!!!!!!!!!!!!NOTICE!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +*In order to use swm drv_soft_i2c,you need to commented out +line 114 (SDA_H(ops);) and line 167 (SDA_H(ops);) in i2c-bit-ops.c +At the same time, add one line (SDA_L(ops);)after line 154 (SCL_L(ops);) +in i2c-bit-ops.c +***************************************************************/ + +//#define DRV_DEBUG +#define LOG_TAG "drv.i2c" +#include + +#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1) +#error "Please define at least one BSP_USING_I2Cx" +/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */ +#endif + +static const struct swm_soft_i2c_cfg soft_i2c_cfg[] = + { +#ifdef BSP_USING_I2C0 + I2C0_BUS_CFG, +#endif +#ifdef BSP_USING_I2C1 + I2C1_BUS_CFG, +#endif +}; + +static struct swm_i2c i2c_drv[sizeof(soft_i2c_cfg) / sizeof(soft_i2c_cfg[0])]; + +/** + * This function initializes the i2c pin. + * + * @param swm i2c dirver class. + */ +static void swm_i2c_gpio_init(struct swm_i2c *i2c) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)i2c->ops.data; + + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +/** + * This function sets the sda pin. + * + * @param swm config class. + * @param The sda pin state. + */ +static void swm_set_sda(void *data, rt_int32_t state) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + if (state) + { + rt_pin_write(cfg->sda, PIN_HIGH); + } + else + { + rt_pin_write(cfg->sda, PIN_LOW); + } +} + +/** + * This function sets the scl pin. + * + * @param swm config class. + * @param The scl pin state. + */ +static void swm_set_scl(void *data, rt_int32_t state) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + if (state) + { + rt_pin_write(cfg->scl, PIN_HIGH); + } + else + { + rt_pin_write(cfg->scl, PIN_LOW); + } +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t swm_get_sda(void *data) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->sda, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(cfg->sda); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t swm_get_scl(void *data) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->scl, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(cfg->scl); +} + +/** + * The time delay function. + * + * @param microseconds. + */ +static void swm_udelay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +static const struct rt_i2c_bit_ops swm_bit_ops = + { + .data = RT_NULL, + .set_sda = swm_set_sda, + .set_scl = swm_set_scl, + .get_sda = swm_get_sda, + .get_scl = swm_get_scl, + .udelay = swm_udelay, + .delay_us = 1, + .timeout = 100}; + +/* I2C initialization function */ +int rt_hw_i2c_init(void) +{ + rt_err_t result; + + for (int i = 0; i < sizeof(i2c_drv) / sizeof(struct swm_i2c); i++) + { + i2c_drv[i].ops = swm_bit_ops; + i2c_drv[i].ops.data = (void *)&soft_i2c_cfg[i]; + i2c_drv[i].i2c2_bus.priv = &i2c_drv[i].ops; + swm_i2c_gpio_init(&i2c_drv[i]); + result = rt_i2c_bit_add_bus(&i2c_drv[i].i2c2_bus, soft_i2c_cfg[i].name); + RT_ASSERT(result == RT_EOK); + + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + soft_i2c_cfg[i].name, + soft_i2c_cfg[i].scl, + soft_i2c_cfg[i].sda); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); +#endif /* BSP_USING_I2C */ +#endif /* RT_USING_I2C */ diff --git a/bsp/swm320/drivers/drv_soft_i2c.h b/bsp/swm320/drivers/drv_soft_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..f22922c7d0ac43c6e906f5996427cba061f6bda0 --- /dev/null +++ b/bsp/swm320/drivers/drv_soft_i2c.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_SOFT_I2C_H__ +#define __DRV_SOFT_I2C_H__ + +#include "board.h" + +/* swm config class */ +struct swm_soft_i2c_cfg +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *name; +}; +/* swm i2c dirver class */ +struct swm_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c2_bus; +}; + +#ifdef BSP_USING_I2C0 +#define I2C0_BUS_CFG \ + { \ + .scl = BSP_I2C0_SCL_PIN, \ + .sda = BSP_I2C0_SDA_PIN, \ + .name = "i2c0", \ + } +#endif + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CFG \ + { \ + .scl = BSP_I2C1_SCL_PIN, \ + .sda = BSP_I2C1_SDA_PIN, \ + .name = "i2c1", \ + } +#endif + +int rt_hw_i2c_init(void); + +#endif /* __DRV_SOFT_I2C_H__ */ diff --git a/bsp/swm320/drivers/drv_spi.c b/bsp/swm320/drivers/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..36b16aa5c8f688eb7fd4b284ea86a2f3e7ebfd0c --- /dev/null +++ b/bsp/swm320/drivers/drv_spi.c @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik format file + */ + +#include "drv_spi.h" + +#ifdef RT_USING_SPI +#ifdef BSP_USING_SPI + +//#define DRV_DEBUG +#define LOG_TAG "drv.spi" +#include + +static struct swm_spi_cfg spi_cfg[] = + { +#ifdef BSP_USING_SPI0 + SPI0_BUS_CONFIG, +#endif +#ifdef BSP_USING_SPI1 + SPI1_BUS_CONFIG, +#endif +}; + +static struct swm_spi spi_bus_drv[sizeof(spi_cfg) / sizeof(spi_cfg[0])] = {0}; + +static rt_err_t swm_spi_init(struct swm_spi *spi_drv, struct rt_spi_configuration *configure) +{ + RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT(configure != RT_NULL); + + struct swm_spi_cfg *cfg = spi_drv->cfg; + + if (configure->mode & RT_SPI_SLAVE) + { + cfg->spi_initstruct.Master = 0; + } + else + { + cfg->spi_initstruct.Master = 1; + } + + if (configure->mode & RT_SPI_3WIRE) + { + return RT_EINVAL; + } + + if (configure->data_width == 8) + { + cfg->spi_initstruct.WordSize = 8; + } + else if (configure->data_width == 16) + { + cfg->spi_initstruct.WordSize = 16; + } + else + { + return RT_EIO; + } + + if (configure->mode & RT_SPI_CPHA) + { + cfg->spi_initstruct.SampleEdge = SPI_SECOND_EDGE; + } + else + { + cfg->spi_initstruct.SampleEdge = SPI_FIRST_EDGE; + } + + if (configure->mode & RT_SPI_CPOL) + { + cfg->spi_initstruct.IdleLevel = SPI_HIGH_LEVEL; + } + else + { + cfg->spi_initstruct.IdleLevel = SPI_LOW_LEVEL; + } + + if (configure->max_hz >= SystemCoreClock / 4) + { + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_4; + } + else if (configure->max_hz >= SystemCoreClock / 8) + { + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_8; + } + else if (configure->max_hz >= SystemCoreClock / 16) + { + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_16; + } + else if (configure->max_hz >= SystemCoreClock / 32) + { + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_32; + } + else if (configure->max_hz >= SystemCoreClock / 64) + { + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_64; + } + else if (configure->max_hz >= SystemCoreClock / 128) + { + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_128; + } + else if (configure->max_hz >= SystemCoreClock / 256) + { + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_256; + } + else + { + /* min prescaler 512 */ + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_512; + } + + SPI_Init(cfg->SPIx, &(cfg->spi_initstruct)); + SPI_Open(cfg->SPIx); + LOG_D("%s init done", cfg->name); + return RT_EOK; +} + +#define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2) +#define SPISEND_1(reg, ptr, datalen) \ + do \ + { \ + if (datalen == 8) \ + { \ + (reg) = *(rt_uint8_t *)(ptr); \ + } \ + else \ + { \ + (reg) = *(rt_uint16_t *)(ptr); \ + } \ + } while (0) +#define SPIRECV_1(reg, ptr, datalen) \ + do \ + { \ + if (datalen == 8) \ + { \ + *(rt_uint8_t *)(ptr) = (reg); \ + } \ + else \ + { \ + *(rt_uint16_t *)(ptr) = reg; \ + } \ + } while (0) + +static rt_err_t spitxrx1b(struct swm_spi *spi_drv, void *rcvb, const void *sndb) +{ + rt_uint32_t padrcv = 0; + rt_uint32_t padsnd = 0xFF; + if (!rcvb && !sndb) + { + return RT_ERROR; + } + if (!rcvb) + { + rcvb = &padrcv; + } + if (!sndb) + { + sndb = &padsnd; + } + while (SPI_IsTXFull(spi_drv->cfg->SPIx)) + ; + SPISEND_1(spi_drv->cfg->SPIx->DATA, sndb, spi_drv->cfg->spi_initstruct.WordSize); + while (SPI_IsRXEmpty(spi_drv->cfg->SPIx)) + ; + SPIRECV_1(spi_drv->cfg->SPIx->DATA, rcvb, spi_drv->cfg->spi_initstruct.WordSize); + return RT_EOK; +} + +static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_err_t res; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message != RT_NULL); + + struct swm_spi *spi_drv = rt_container_of(device->bus, struct swm_spi, spi_bus); + struct swm_spi_cfg *cfg = spi_drv->cfg; + struct swm_spi_cs *cs = device->parent.user_data; + + if (message->cs_take) + { + GPIO_ClrBit(cs->GPIOx, cs->gpio_pin); + } + + LOG_D("%s transfer prepare and start", cfg->name); + LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", + cfg->name, (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length); + + const rt_uint8_t *sndb = message->send_buf; + rt_uint8_t *rcvb = message->recv_buf; + rt_int32_t length = message->length; + + while (length) + { + res = spitxrx1b(spi_drv, rcvb, sndb); + if (rcvb) + { + rcvb += SPISTEP(cfg->spi_initstruct.WordSize); + } + if (sndb) + { + sndb += SPISTEP(cfg->spi_initstruct.WordSize); + } + if (res != RT_EOK) + { + break; + } + length--; + } + /* Wait until Busy flag is reset before disabling SPI */ + while (!SPI_IsTXEmpty(cfg->SPIx) && !SPI_IsRXEmpty(cfg->SPIx)) + ; + if (message->cs_release) + { + GPIO_SetBit(cs->GPIOx, cs->gpio_pin); + } + return message->length - length; +} + +static rt_err_t swm_spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configure) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configure != RT_NULL); + + struct swm_spi *spi_drv = rt_container_of(device->bus, struct swm_spi, spi_bus); + spi_drv->configure = configure; + + return swm_spi_init(spi_drv, configure); +} +const static struct rt_spi_ops swm_spi_ops = + { + .configure = swm_spi_configure, + .xfer = swm_spi_xfer, +}; + +//cannot be used before completion init +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint32_t cs_gpio_pin) +{ + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + struct swm_spi_cs *cs_pin; + + GPIO_Init(cs_gpiox, cs_gpio_pin, 1, 0, 0); + GPIO_SetBit(cs_gpiox, cs_gpio_pin); + + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + cs_pin = (struct swm_spi_cs *)rt_malloc(sizeof(struct swm_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->GPIOx = cs_gpiox; + cs_pin->gpio_pin = cs_gpio_pin; + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + if (result != RT_EOK) + { + LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + RT_ASSERT(result == RT_EOK); + LOG_D("%s attach to %s done", device_name, bus_name); + return result; +} + +int rt_hw_spi_init(void) +{ + rt_err_t result; + +#ifdef BSP_USING_SPI0 + PORT_Init(PORTA, PIN9, FUNMUX1_SPI0_SCLK, 0); + PORT_Init(PORTA, PIN10, FUNMUX0_SPI0_MOSI, 0); + PORT_Init(PORTA, PIN11, FUNMUX1_SPI0_MISO, 1); +#endif //BSP_USING_SPI0 + +#ifdef BSP_USING_SPI1 + PORT_Init(PORTC, PIN7, FUNMUX1_SPI1_SCLK, 0); + PORT_Init(PORTC, PIN6, FUNMUX0_SPI1_MOSI, 0); + PORT_Init(PORTC, PIN5, FUNMUX1_SPI1_MISO, 1); +#endif //BSP_USING_SPI1 + for (int i = 0; i < sizeof(spi_cfg) / sizeof(spi_cfg[0]); i++) + { + spi_bus_drv[i].cfg = &spi_cfg[i]; + spi_bus_drv[i].spi_bus.parent.user_data = &spi_cfg[i]; + result = rt_spi_bus_register(&spi_bus_drv[i].spi_bus, spi_cfg[i].name, &swm_spi_ops); + RT_ASSERT(result == RT_EOK); + + LOG_D("%s bus init done", spi_config[i].bus_name); + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif /* BSP_USING_SPI */ +#endif /* RT_USING_SPI */ diff --git a/bsp/swm320/drivers/drv_spi.h b/bsp/swm320/drivers/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..7af96779d241a1a8d4d55caccda634dbb6b2467e --- /dev/null +++ b/bsp/swm320/drivers/drv_spi.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include "board.h" + +struct swm_spi_cs +{ + GPIO_TypeDef *GPIOx; + uint32_t gpio_pin; +}; + +struct swm_spi_cfg +{ + const char *name; + SPI_TypeDef *SPIx; + SPI_InitStructure spi_initstruct; +}; + +/* swm spi dirver class */ +struct swm_spi +{ + struct swm_spi_cfg *cfg; + struct rt_spi_configuration *configure; + struct rt_spi_bus spi_bus; +}; + +#ifdef BSP_USING_SPI0 +#ifndef SPI0_BUS_CONFIG +#define SPI0_BUS_CONFIG \ + { \ + .name = "spi0", \ + .SPIx = SPI0, \ + .spi_initstruct.clkDiv = SPI_CLKDIV_32, \ + .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \ + .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \ + .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL, \ + .spi_initstruct.WordSize = 8, \ + .spi_initstruct.Master = 1, \ + .spi_initstruct.RXHFullIEn = 0, \ + .spi_initstruct.TXEmptyIEn = 0, \ + .spi_initstruct.TXCompleteIEn = 0, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .name = "spi1", \ + .SPIx = SPI1, \ + .spi_initstruct.clkDiv = SPI_CLKDIV_32, \ + .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \ + .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \ + .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL, \ + .spi_initstruct.WordSize = 8, \ + .spi_initstruct.Master = 1, \ + .spi_initstruct.RXHFullIEn = 0, \ + .spi_initstruct.TXEmptyIEn = 0, \ + .spi_initstruct.TXCompleteIEn = 0, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +//cannot be used before completion init +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *GPIOx, uint32_t n); +int rt_hw_spi_init(void); + +#endif /* __DRV_SPI_H__ */ diff --git a/bsp/swm320/drivers/drv_sram.c b/bsp/swm320/drivers/drv_sram.c new file mode 100644 index 0000000000000000000000000000000000000000..90c2d9467692caa18a94739e8ca1db1525813621 --- /dev/null +++ b/bsp/swm320/drivers/drv_sram.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik rewrite + */ + +#include "drv_sram.h" + +#ifdef BSP_USING_EXT_SRAM + +#define DRV_DEBUG +#define LOG_TAG "drv.ext_sram" +#include + +#ifdef RT_USING_MEMHEAP_AS_HEAP +static struct rt_memheap system_heap; +#endif + +static int rt_hw_sram_init(void) +{ + SRAM_InitStructure SRAM_InitStruct; + + PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23 + PORT->PORTP_SEL1 = 0xAAAA; + + PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0 + PORT->PORTM_INEN = 0xFFFF; + + PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN,PM17 => WEN,PM18 => NORFL_CSN,PM19 => SDRAM_CSN,PM20 => SRAM_CSN,PM21 => SDRAM_CKE + + SRAM_InitStruct.ClkDiv = SRAM_CLKDIV_8; + SRAM_InitStruct.DataWidth = SRAM_DATAWIDTH_16; + SRAM_Init(&SRAM_InitStruct); + +#ifdef RT_USING_MEMHEAP_AS_HEAP + /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */ + rt_memheap_init(&system_heap, "sram", (void *)EXT_SRAM_BEGIN, EXT_SRAM_SIZE); +#endif + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_sram_init); + +#endif /* BSP_USING_EXT_SRAM */ diff --git a/bsp/swm320/drivers/drv_sram.h b/bsp/swm320/drivers/drv_sram.h new file mode 100644 index 0000000000000000000000000000000000000000..043de498e21b77c18f67d378e2935b58e30e8397 --- /dev/null +++ b/bsp/swm320/drivers/drv_sram.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef DRV_SRAM_H__ +#define DRV_SRAM_H__ + +#include "board.h" + +#define EXT_SRAM_BASE SRAMM_BASE +#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE +#define EXT_SRAM_BEGIN EXT_SRAM_BASE +#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) + +int rt_hw_sram_init(void); + +#endif diff --git a/bsp/swm320/drivers/drv_uart.c b/bsp/swm320/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..d193eb12380c669506eaa0da8d5304caebdaa447 --- /dev/null +++ b/bsp/swm320/drivers/drv_uart.c @@ -0,0 +1,284 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik format file + */ + +#include "drv_uart.h" + +#ifdef RT_USING_SERIAL +#ifdef BSP_USING_UART + +//#define DRV_DEBUG +#define LOG_TAG "drv.uart" +#include + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \ + !defined(BSP_USING_UART3) +#error "Please define at least one BSP_USING_UARTx" +/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +enum +{ +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +}; + +static struct swm_uart_cfg uart_cfg[] = + { +#ifdef BSP_USING_UART0 + UART0_CFG, +#endif +#ifdef BSP_USING_UART1 + UART1_CFG, +#endif +#ifdef BSP_USING_UART2 + UART2_CFG, +#endif +#ifdef BSP_USING_UART3 + UART3_CFG, +#endif +}; + +static struct swm_uart uart_drv[sizeof(uart_cfg) / sizeof(uart_cfg[0])] = {0}; + +static rt_err_t swm_uart_init(struct rt_serial_device *serial_device, struct serial_configure *configure) +{ + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + RT_ASSERT(configure != RT_NULL); + cfg = serial_device->parent.user_data; + + cfg->uart_initstruct.Baudrate = configure->baud_rate; + switch (configure->data_bits) + { + case DATA_BITS_8: + cfg->uart_initstruct.DataBits = UART_DATA_8BIT; + break; + case DATA_BITS_9: + cfg->uart_initstruct.DataBits = UART_DATA_9BIT; + break; + default: + cfg->uart_initstruct.DataBits = UART_DATA_8BIT; + break; + } + switch (configure->stop_bits) + { + case STOP_BITS_1: + cfg->uart_initstruct.StopBits = UART_STOP_1BIT; + break; + case STOP_BITS_2: + cfg->uart_initstruct.StopBits = UART_STOP_2BIT; + break; + default: + cfg->uart_initstruct.StopBits = UART_STOP_1BIT; + break; + } + switch (configure->parity) + { + case PARITY_NONE: + cfg->uart_initstruct.Parity = UART_PARITY_NONE; + break; + case PARITY_ODD: + cfg->uart_initstruct.Parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + cfg->uart_initstruct.Parity = UART_PARITY_EVEN; + break; + default: + cfg->uart_initstruct.Parity = UART_PARITY_NONE; + break; + } + switch ((uint32_t)cfg->UARTx) + { + case ((uint32_t)UART0): + PORT_Init(PORTA, PIN2, FUNMUX0_UART0_RXD, 1); + PORT_Init(PORTA, PIN3, FUNMUX1_UART0_TXD, 0); + break; + case ((uint32_t)UART1): + PORT_Init(PORTC, PIN2, FUNMUX0_UART1_RXD, 1); + PORT_Init(PORTC, PIN3, FUNMUX1_UART1_TXD, 0); + break; + case ((uint32_t)UART2): + PORT_Init(PORTC, PIN4, FUNMUX0_UART2_RXD, 1); + PORT_Init(PORTC, PIN5, FUNMUX1_UART2_TXD, 0); + break; + case ((uint32_t)UART3): + PORT_Init(PORTC, PIN6, FUNMUX0_UART3_RXD, 1); + PORT_Init(PORTC, PIN7, FUNMUX1_UART3_TXD, 0); + break; + default: + break; + } + UART_Init(cfg->UARTx, &(cfg->uart_initstruct)); + UART_Open(cfg->UARTx); + return RT_EOK; +} + +static rt_err_t swm_uart_control(struct rt_serial_device *serial_device, int cmd, void *arg) +{ + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(cfg->irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(cfg->irq); + break; + } + return RT_EOK; +} + +static int swm_uart_putc(struct rt_serial_device *serial_device, char c) +{ + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + while (UART_IsTXFIFOFull(cfg->UARTx)) + ; + UART_WriteByte(cfg->UARTx, c); + while (UART_IsTXBusy(cfg->UARTx)) + ; + return 1; +} + +static int swm_uart_getc(struct rt_serial_device *serial_device) +{ + int ch; + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + ch = -1; + if (UART_IsRXFIFOEmpty(cfg->UARTx) == 0) + { + UART_ReadByte(cfg->UARTx, (uint32_t *)&ch); + } + return ch; +} + +static const struct rt_uart_ops swm_uart_ops = + { + .configure = swm_uart_init, + .control = swm_uart_control, + .putc = swm_uart_putc, + .getc = swm_uart_getc, + .dma_transmit = RT_NULL}; + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void rt_hw_uart_isr(struct rt_serial_device *serial_device) +{ + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + /* UART in mode Receiver -------------------------------------------------*/ + if (UART_INTRXThresholdStat(cfg->UARTx) || UART_INTTimeoutStat(cfg->UARTx)) + { + rt_hw_serial_isr(serial_device, RT_SERIAL_EVENT_RX_IND); + } +} + +#if defined(BSP_USING_UART0) +void UART0_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART0_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +void UART1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART1_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void UART2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART2_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +void UART3_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART3_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +int rt_hw_uart_init(void) +{ + struct serial_configure cfg = RT_SERIAL_CONFIG_DEFAULT; + int i = 0; + rt_err_t result = RT_EOK; + + for (i = 0; i < sizeof(uart_cfg) / sizeof(uart_cfg[0]); i++) + { + uart_drv[i].cfg = &uart_cfg[i]; + uart_drv[i].serial_device.ops = &swm_uart_ops; + uart_drv[i].serial_device.config = cfg; + /* register UART device */ + result = rt_hw_serial_register(&uart_drv[i].serial_device, uart_drv[i].cfg->name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart_drv[i].cfg); + RT_ASSERT(result == RT_EOK); + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* BSP_USING_UART */ +#endif /* RT_USING_SERIAL */ diff --git a/bsp/swm320/drivers/drv_uart.h b/bsp/swm320/drivers/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..66c6535a5b4741dd6168948619d5d98af5b5c64a --- /dev/null +++ b/bsp/swm320/drivers/drv_uart.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include "board.h" + +/* swm config class */ +struct swm_uart_cfg +{ + const char *name; + UART_TypeDef *UARTx; + IRQn_Type irq; + UART_InitStructure uart_initstruct; +}; + +/* swm uart dirver class */ +struct swm_uart +{ + struct swm_uart_cfg *cfg; + struct rt_serial_device serial_device; +}; + +#ifdef BSP_USING_UART0 +#ifndef UART0_CFG +#define UART0_CFG \ + { \ + .name = "uart0", \ + .UARTx = UART0, \ + .irq = UART0_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART0_CFG */ +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 +#ifndef UART1_CFG +#define UART1_CFG \ + { \ + .name = "uart1", \ + .UARTx = UART1, \ + .irq = UART1_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART1_CFG */ +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 +#ifndef UART2_CFG +#define UART2_CFG \ + { \ + .name = "uart2", \ + .UARTx = UART2, \ + .irq = UART2_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART2_CFG */ +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 +#ifndef UART3_CFG +#define UART3_CFG \ + { \ + .name = "uart3", \ + .UARTx = UART3, \ + .irq = UART3_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART3_CFG */ +#endif /* BSP_USING_UART3 */ + +int rt_hw_serial_init(void); + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/swm320/drivers/drv_wdt.c b/bsp/swm320/drivers/drv_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..36d5fde26d0ecf8b1f886819121938717ecd13a0 --- /dev/null +++ b/bsp/swm320/drivers/drv_wdt.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file + */ + +#include "drv_wdt.h" + +#ifdef RT_USING_WDT +#ifdef BSP_USING_WDT +//#define DRV_DEBUG +#define LOG_TAG "drv.wdt" +#include + +static struct swm_wdt_cfg wdt_cfg = + { + .name = "wdt", + .WDTx = WDT, +}; + +static struct swm_wdt wdt_drv; + +static rt_err_t swm_wdt_init(rt_watchdog_t *wdt_device) +{ + return RT_EOK; +} + +static rt_err_t swm_wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg) +{ + struct swm_wdt_cfg *cfg; + RT_ASSERT(wdt_device != RT_NULL); + cfg = wdt_device->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + WDT_Feed(cfg->WDTx); + break; + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + WDT_Init(cfg->WDTx, (SystemCoreClock * (*(rt_uint32_t *)arg)), WDT_MODE_RESET); + break; + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + *(rt_uint32_t *)arg = (cfg->WDTx->LOAD) / SystemCoreClock; + break; + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + *(rt_uint32_t *)arg = WDT_GetValue(cfg->WDTx) / SystemCoreClock; + break; + case RT_DEVICE_CTRL_WDT_START: + WDT_Start(cfg->WDTx); + break; + case RT_DEVICE_CTRL_WDT_STOP: + WDT_Stop(cfg->WDTx); + break; + default: + LOG_W("This command is not supported."); + return -RT_ERROR; + } + + return RT_EOK; +} + +const static struct rt_watchdog_ops swm_wdt_ops = + { + swm_wdt_init, + swm_wdt_control}; + +int rt_hw_wdt_init(void) +{ + wdt_drv.cfg = &wdt_cfg; + wdt_drv.wdt_device.ops = &swm_wdt_ops; + + if (rt_hw_watchdog_register(&wdt_drv.wdt_device, wdt_drv.cfg->name, RT_DEVICE_FLAG_RDWR, wdt_drv.cfg) != RT_EOK) + { + LOG_E("wdt device register failed."); + return -RT_ERROR; + } + LOG_D("wdt device register success."); + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_wdt_init); + +#endif /* BSP_USING_WDT */ +#endif /* RT_USING_WDT */ diff --git a/bsp/swm320/drivers/drv_wdt.h b/bsp/swm320/drivers/drv_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..28be110f016e60d1d5f240fcc9392339962eaf9a --- /dev/null +++ b/bsp/swm320/drivers/drv_wdt.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_WDT_H__ +#define __DRV_WDT_H__ + +#include "board.h" + +struct swm_wdt_cfg +{ + const char *name; + WDT_TypeDef *WDTx; +}; + +struct swm_wdt +{ + struct swm_wdt_cfg *cfg; + struct rt_watchdog_device wdt_device; +}; + +int rt_hw_wdt_init(void); + +#endif /* __DRV_WDT_H__ */ diff --git a/bsp/swm320/drivers/linker_scripts/link.icf b/bsp/swm320/drivers/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..4d4eb646235816e2f84be5d89f1faba1e60b9bf6 --- /dev/null +++ b/bsp/swm320/drivers/linker_scripts/link.icf @@ -0,0 +1,62 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x0; +define symbol __ICFEDIT_region_IROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region EROM_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__] + | mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__] + | mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] + | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] + | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +do not initialize { section .noinit }; +initialize by copy { readwrite }; +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in IROM_region { readonly }; +place in EROM_region { readonly section application_specific_ro }; +place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; +place in ERAM_region { readwrite section application_specific_rw }; \ No newline at end of file diff --git a/bsp/swm320/drivers/linker_scripts/link.lds b/bsp/swm320/drivers/linker_scripts/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..34fc394ae721b916b490b0cadd1389a334d9de0a --- /dev/null +++ b/bsp/swm320/drivers/linker_scripts/link.lds @@ -0,0 +1,71 @@ +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Specify the memory areas */ +MEMORY +{ + ROM (arx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* 512k */ + RAM (arw) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* 128k */ +} + +/* Define output sections */ +SECTIONS +{ + . = ORIGIN(ROM); + .text : + { + KEEP(*(.isr_vector)) + + *(.text) + *(.text*) + *(.rodata*) + } > ROM + + . = ALIGN(4); + __data_load__ = LOADADDR(.data); + + . = ALIGN(4); + .data : + { + __data_start__ = .; + + *(.data) + *(.data*) + + . = ALIGN(4); + __data_end__ = .; + } > RAM AT> ROM + + . = ALIGN(4); + .bss : + { + __bss_start__ = .; + + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > RAM + . = ALIGN(4); + + .heap : + { + end = .; + __HeapBase = .; + + *(.heap) + } > RAM + + /* .stack_dummy section doesn't contains any symbols. + * It is only used for linker to calculate size of stack sections */ + .stack_dummy : + { + *(.stack) + } > RAM + + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/bsp/swm320/drivers/linker_scripts/link.sct b/bsp/swm320/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..c7363fec458c791af052822fb60d7220f2771ef0 --- /dev/null +++ b/bsp/swm320/drivers/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00080000 { ; load region size_region + ER_IROM1 0x00000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/swm320/keilkill.bat b/bsp/swm320/keilkill.bat new file mode 100644 index 0000000000000000000000000000000000000000..52d5f3375a5fa94213a003080e79c7a6932dc707 --- /dev/null +++ b/bsp/swm320/keilkill.bat @@ -0,0 +1,37 @@ +del *.bak /s +del *.ddk /s +del *.edk /s +del *.lst /s +::del *.lnp /s +del *.mpf /s +del *.mpj /s +del *.obj /s +del *.omf /s +::del *.opt /s ::不允许删除JLINK的设置 +del *.plg /s +del *.rpt /s +del *.tmp /s +::del *.__i /s +::del *._ia /s +del *.crf /s +del *.o /s +del *.d /s +del *.axf /s +del *.tra /s +del *.dep /s +::del JLinkLog.txt /s + +del *.iex /s +del *.htm /s +::del *.sct /s +del *.map /s + +del *.whsj2 /s +del *.SYNWIT_Lik /s +del *.whsj2 /s +del *.scvd /s + +rmdir /s/q .git +rmdir /s/q .vscode + +exit diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/arm_common_tables.h b/bsp/swm320/libraries/CMSIS/CoreSupport/arm_common_tables.h new file mode 100644 index 0000000000000000000000000000000000000000..76aadca49019898d4c20e3ffedf2b669d253d032 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +//extern const q31_t realCoefAQ31[1024]; +//extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/arm_const_structs.h b/bsp/swm320/libraries/CMSIS/CoreSupport/arm_const_structs.h new file mode 100644 index 0000000000000000000000000000000000000000..217f1d50e260786f734f1d914c26d096348bc142 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/arm_math.h b/bsp/swm320/libraries/CMSIS/CoreSupport/arm_math.h new file mode 100644 index 0000000000000000000000000000000000000000..f06a0713eb80a6a827b50ae0ad37be7eee6ba650 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/arm_math.h @@ -0,0 +1,7538 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvproj + * + * + * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2014 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY + #elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + + ((q15_t) x * (q15_t) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//SMMLA +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) //Keil + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0.h b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0.h new file mode 100644 index 0000000000000000000000000000000000000000..5186cb4838824e99fef56f62e62a67adad2cc7a0 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0.h @@ -0,0 +1,711 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0plus.h b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0plus.h new file mode 100644 index 0000000000000000000000000000000000000000..17e43984fcf972bf1c642c5e3bb73e8285e6ef82 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0plus.h @@ -0,0 +1,822 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm3.h b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm3.h new file mode 100644 index 0000000000000000000000000000000000000000..e1357c6735b08ad88891018172c28d0b9065a4f7 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm3.h @@ -0,0 +1,1650 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm4.h b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm4.h new file mode 100644 index 0000000000000000000000000000000000000000..bb6be1305d27ead1551fe349d1805002f167a384 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm4.h @@ -0,0 +1,1802 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm7.h b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm7.h new file mode 100644 index 0000000000000000000000000000000000000000..242540f8b118737d72138b75e0aba05a3c647f18 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm7.h @@ -0,0 +1,2221 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 01. September 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000 + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0 + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0 + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0 + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/* Cache Level ID register */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* Cache Type register */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ + +/* Cache Size ID Register */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ + +/* Cache Size Selection Register */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ + +/* Instruction Tightly-Coupled Memory Control Register*/ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Registers */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ + +/* AHBS control register */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## Cache functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) + + +/** \brief Enable I-Cache + + The function turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable I-Cache + + The function turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate I-Cache + + The function invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); + #endif +} + + +/** \brief Enable D-Cache + + The function turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + __DSB(); + + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable D-Cache + + The function turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate D-Cache + + The function invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean D-Cache + + The function cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean & Invalidate D-Cache + + The function cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cmFunc.h b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cmFunc.h new file mode 100644 index 0000000000000000000000000000000000000000..01089f1333bd097ac99868e007c84e1cb6ef85a6 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cmInstr.h b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cmInstr.h new file mode 100644 index 0000000000000000000000000000000000000000..d14110b2abd16c8d93acece894985d4fe2841cb0 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cmSimd.h b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cmSimd.h new file mode 100644 index 0000000000000000000000000000000000000000..ee58eee56dd773194d453098a7f632aabf9610c0 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cmSimd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/swm320/libraries/CMSIS/DeviceSupport/SWM320.h b/bsp/swm320/libraries/CMSIS/DeviceSupport/SWM320.h new file mode 100644 index 0000000000000000000000000000000000000000..55eb7812f072415707464e457ed7f2869ccaa1c7 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/DeviceSupport/SWM320.h @@ -0,0 +1,3567 @@ +#ifndef __SWM320_H__ +#define __SWM320_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ +typedef enum IRQn +{ + /****** Cortex-M0 Processor Exceptions Numbers **********************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** Cortex-M4 specific Interrupt Numbers ************************************************/ + GPIOA0_IRQn = 0, + GPIOA1_IRQn = 1, + GPIOA2_IRQn = 2, + GPIOA3_IRQn = 3, + GPIOA4_IRQn = 4, + GPIOA5_IRQn = 5, + GPIOA6_IRQn = 6, + GPIOA7_IRQn = 7, + GPIOB0_IRQn = 8, + GPIOB1_IRQn = 9, + GPIOB2_IRQn = 10, + GPIOB3_IRQn = 11, + GPIOB4_IRQn = 12, + GPIOB5_IRQn = 13, + GPIOB6_IRQn = 14, + GPIOB7_IRQn = 15, + GPIOC0_IRQn = 16, + GPIOC1_IRQn = 17, + GPIOC2_IRQn = 18, + GPIOC3_IRQn = 19, + GPIOC4_IRQn = 20, + GPIOC5_IRQn = 21, + GPIOC6_IRQn = 22, + GPIOC7_IRQn = 23, + GPIOM0_IRQn = 24, + GPIOM1_IRQn = 25, + GPIOM2_IRQn = 26, + GPIOM3_IRQn = 27, + GPIOM4_IRQn = 28, + GPIOM5_IRQn = 29, + GPIOM6_IRQn = 30, + GPIOM7_IRQn = 31, + DMA_IRQn = 32, + LCD_IRQn = 33, + NORFLC_IRQn = 34, + CAN_IRQn = 35, + PULSE_IRQn = 36, + WDT_IRQn = 37, + PWM_IRQn = 38, + UART0_IRQn = 39, + UART1_IRQn = 40, + UART2_IRQn = 41, + UART3_IRQn = 42, + UART4_IRQn = 43, + I2C0_IRQn = 44, + I2C1_IRQn = 45, + SPI0_IRQn = 46, + ADC0_IRQn = 47, + RTC_IRQn = 48, + BOD_IRQn = 49, + SDIO_IRQn = 50, + GPIOA_IRQn = 51, + GPIOB_IRQn = 52, + GPIOC_IRQn = 53, + GPIOM_IRQn = 54, + GPION_IRQn = 55, + GPIOP_IRQn = 56, + ADC1_IRQn = 57, + FPU_IRQn = 58, + SPI1_IRQn = 59, + TIMR0_IRQn = 60, + TIMR1_IRQn = 61, + TIMR2_IRQn = 62, + TIMR3_IRQn = 63, + TIMR4_IRQn = 64, + TIMR5_IRQn = 65, +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< SWM320 provides an MPU */ +#define __NVIC_PRIO_BITS 3 /*!< SWM320 uses 3 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0 /*!< FPU present */ + +#if defined(__CC_ARM) +#pragma anon_unions +#endif + +#include +#include "core_cm4.h" /* Cortex-M0 processor and core peripherals */ +#include "system_SWM320.h" + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +typedef struct +{ + __IO uint32_t CLKSEL; //Clock Select + + __IO uint32_t CLKDIV; + + __IO uint32_t CLKEN; //Clock Enable + + __IO uint32_t SLEEP; + + uint32_t RESERVED0[6]; + + __IO uint32_t RTCBKP_ISO; //[0] 1 RTC备份电源域处于隔离状态 0 RTC备份电源域可访问 + + __IO uint32_t RTCWKEN; //[0] 1 使能RTC唤醒功能 + + uint32_t RESERVED[52 + 64]; + + __IO uint32_t PAWKEN; //Port A Wakeup Enable + __IO uint32_t PBWKEN; + __IO uint32_t PCWKEN; + + uint32_t RESERVED2[1 + 4]; + + __IO uint32_t PAWKSR; //Port A Wakeup Status Register，写1清零 + __IO uint32_t PBWKSR; + __IO uint32_t PCWKSR; + + uint32_t RESERVED3[64 - 10]; + + __IO uint32_t RSTCR; //Reset Control Register + __IO uint32_t RSTSR; //Reset Status Register + + uint32_t RESERVED4[61 + 64]; + + __IO uint32_t BKP[3]; //数据备份寄存器 + + //RTC Power Domain: 0x4001E000 + uint32_t RESERVED5[(0x4001E000 - 0x40000508) / 4 - 1]; + + __IO uint32_t RTCBKP[8]; //RTC电源域数据备份寄存器 + + __IO uint32_t LRCCR; //Low speed RC Control Register + __IO uint32_t LRCTRIM0; //Low speed RC Trim + __IO uint32_t LRCTRIM1; + + uint32_t RESERVED6; + + __IO uint32_t RTCLDOTRIM; //RTC Power Domain LDO Trim + + //Analog Control: 0x40031000 + uint32_t RESERVED7[(0x40031000 - 0x4001E030) / 4 - 1]; + + __IO uint32_t HRCCR; //High speed RC Control Register + + uint32_t RESERVED8[7]; + + __IO uint32_t XTALCR; + + __IO uint32_t PLLCR; + __IO uint32_t PLLDIV; + __IO uint32_t PLLSET; + __IO uint32_t PLLLOCK; //[0] 1 PLL已锁定 + + __IO uint32_t BODIE; + __IO uint32_t BODIF; + + __IO uint32_t ADC1IN7; +} SYS_TypeDef; + +#define SYS_CLKSEL_LFCK_Pos 0 //Low Frequency Clock Source 0 LRC 1 PLL +#define SYS_CLKSEL_LFCK_Msk (0x01 << SYS_CLKSEL_LFCK_Pos) +#define SYS_CLKSEL_HFCK_Pos 1 //High Frequency Clock Source 0 HRC 1 XTAL +#define SYS_CLKSEL_HFCK_Msk (0x01 << SYS_CLKSEL_HFCK_Pos) +#define SYS_CLKSEL_SYS_Pos 2 //系统时钟选择 0 LFCK 1 HFCK +#define SYS_CLKSEL_SYS_Msk (0x01 << SYS_CLKSEL_SYS_Pos) + +#define SYS_CLKDIV_SYS_Pos 0 //系统时钟分频 0 1分频 1 2分频 +#define SYS_CLKDIV_SYS_Msk (0x01 << SYS_CLKDIV_SYS_Pos) +#define SYS_CLKDIV_PWM_Pos 1 //PWM 时钟分频 0 1分频 1 8分频 +#define SYS_CLKDIV_PWM_Msk (0x01 << SYS_CLKDIV_PWM_Pos) +#define SYS_CLKDIV_SDRAM_Pos 2 //SDRAM时钟分频 0 1分频 1 2分频 2 4分频 +#define SYS_CLKDIV_SDRAM_Msk (0x03 << SYS_CLKDIV_SDRAM_Pos) +#define SYS_CLKDIV_SDIO_Pos 4 //SDIO时钟分频 0 1分频 1 2分频 2 4分频 3 8分频 +#define SYS_CLKDIV_SDIO_Msk (0x03 << SYS_CLKDIV_SDIO_Pos) + +#define SYS_CLKEN_GPIOA_Pos 0 +#define SYS_CLKEN_GPIOA_Msk (0x01 << SYS_CLKEN_GPIOA_Pos) +#define SYS_CLKEN_GPIOB_Pos 1 +#define SYS_CLKEN_GPIOB_Msk (0x01 << SYS_CLKEN_GPIOB_Pos) +#define SYS_CLKEN_GPIOC_Pos 2 +#define SYS_CLKEN_GPIOC_Msk (0x01 << SYS_CLKEN_GPIOC_Pos) +#define SYS_CLKEN_GPIOM_Pos 4 +#define SYS_CLKEN_GPIOM_Msk (0x01 << SYS_CLKEN_GPIOM_Pos) +#define SYS_CLKEN_GPION_Pos 5 +#define SYS_CLKEN_GPION_Msk (0x01 << SYS_CLKEN_GPION_Pos) +#define SYS_CLKEN_TIMR_Pos 6 +#define SYS_CLKEN_TIMR_Msk (0x01 << SYS_CLKEN_TIMR_Pos) +#define SYS_CLKEN_WDT_Pos 7 +#define SYS_CLKEN_WDT_Msk (0x01 << SYS_CLKEN_WDT_Pos) +#define SYS_CLKEN_ADC0_Pos 8 +#define SYS_CLKEN_ADC0_Msk (0x01 << SYS_CLKEN_ADC0_Pos) +#define SYS_CLKEN_PWM_Pos 9 +#define SYS_CLKEN_PWM_Msk (0x01 << SYS_CLKEN_PWM_Pos) +#define SYS_CLKEN_RTC_Pos 10 +#define SYS_CLKEN_RTC_Msk (0x01 << SYS_CLKEN_RTC_Pos) +#define SYS_CLKEN_UART0_Pos 11 +#define SYS_CLKEN_UART0_Msk (0x01 << SYS_CLKEN_UART0_Pos) +#define SYS_CLKEN_UART1_Pos 12 +#define SYS_CLKEN_UART1_Msk (0x01 << SYS_CLKEN_UART1_Pos) +#define SYS_CLKEN_UART2_Pos 13 +#define SYS_CLKEN_UART2_Msk (0x01 << SYS_CLKEN_UART2_Pos) +#define SYS_CLKEN_UART3_Pos 14 +#define SYS_CLKEN_UART3_Msk (0x01 << SYS_CLKEN_UART3_Pos) +#define SYS_CLKEN_UART4_Pos 15 +#define SYS_CLKEN_UART4_Msk (0x01 << SYS_CLKEN_UART4_Pos) +#define SYS_CLKEN_SPI0_Pos 16 +#define SYS_CLKEN_SPI0_Msk (0x01 << SYS_CLKEN_SPI0_Pos) +#define SYS_CLKEN_I2C0_Pos 17 +#define SYS_CLKEN_I2C0_Msk (0x01 << SYS_CLKEN_I2C0_Pos) +#define SYS_CLKEN_I2C1_Pos 18 +#define SYS_CLKEN_I2C1_Msk (0x01 << SYS_CLKEN_I2C1_Pos) +#define SYS_CLKEN_I2C2_Pos 19 +#define SYS_CLKEN_I2C2_Msk (0x01 << SYS_CLKEN_I2C2_Pos) +#define SYS_CLKEN_LCD_Pos 20 +#define SYS_CLKEN_LCD_Msk (0x01 << SYS_CLKEN_LCD_Pos) +#define SYS_CLKEN_GPIOP_Pos 21 +#define SYS_CLKEN_GPIOP_Msk (0x01 << SYS_CLKEN_GPIOP_Pos) +#define SYS_CLKEN_ANAC_Pos 22 //模拟控制单元时钟使能 +#define SYS_CLKEN_ANAC_Msk (0x01 << SYS_CLKEN_ANAC_Pos) +#define SYS_CLKEN_CRC_Pos 23 +#define SYS_CLKEN_CRC_Msk (0x01 << SYS_CLKEN_CRC_Pos) +#define SYS_CLKEN_RTCBKP_Pos 24 +#define SYS_CLKEN_RTCBKP_Msk (0x01 << SYS_CLKEN_RTCBKP_Pos) +#define SYS_CLKEN_CAN_Pos 25 +#define SYS_CLKEN_CAN_Msk (0x01 << SYS_CLKEN_CAN_Pos) +#define SYS_CLKEN_SDRAM_Pos 26 +#define SYS_CLKEN_SDRAM_Msk (0x01 << SYS_CLKEN_SDRAM_Pos) +#define SYS_CLKEN_NORFL_Pos 27 //NOR Flash +#define SYS_CLKEN_NORFL_Msk (0x01 << SYS_CLKEN_NORFL_Pos) +#define SYS_CLKEN_RAMC_Pos 28 +#define SYS_CLKEN_RAMC_Msk (0x01 << SYS_CLKEN_RAMC_Pos) +#define SYS_CLKEN_SDIO_Pos 29 +#define SYS_CLKEN_SDIO_Msk (0x01 << SYS_CLKEN_SDIO_Pos) +#define SYS_CLKEN_ADC1_Pos 30 +#define SYS_CLKEN_ADC1_Msk (0x01 << SYS_CLKEN_ADC1_Pos) +#define SYS_CLKEN_ALIVE_Pos 31 //CHIPALIVE电源域系统时钟使能 +#define SYS_CLKEN_ALIVE_Msk (0x01 << SYS_CLKEN_ALIVE_Pos) + +#define SYS_SLEEP_SLEEP_Pos 0 //将该位置1后，系统将进入SLEEP模式 +#define SYS_SLEEP_SLEEP_Msk (0x01 << SYS_SLEEP_SLEEP_Pos) +#define SYS_SLEEP_DEEP_Pos 1 //将该位置1后，系统将进入STOP SLEEP模式 +#define SYS_SLEEP_DEEP_Msk (0x01 << SYS_SLEEP_DEEP_Pos) + +#define SYS_RSTCR_SYS_Pos 0 //写1进行系统复位，硬件自动清零 +#define SYS_RSTCR_SYS_Msk (0x01 << SYS_RSTCR_SYS_Pos) +#define SYS_RSTCR_FLASH_Pos 1 //写1对FLASH控制器进行一次复位，硬件自动清零 +#define SYS_RSTCR_FLASH_Msk (0x01 << SYS_RSTCR_FLASH_Pos) +#define SYS_RSTCR_PWM_Pos 2 //写1对PWM进行一次复位，硬件自动清零 +#define SYS_RSTCR_PWM_Msk (0x01 << SYS_RSTCR_PWM_Pos) +#define SYS_RSTCR_CPU_Pos 3 //写1对CPU进行一次复位，硬件自动清零 +#define SYS_RSTCR_CPU_Msk (0x01 << SYS_RSTCR_CPU_Pos) +#define SYS_RSTCR_DMA_Pos 4 //写1对DMA进行一次复位，硬件自动清零 +#define SYS_RSTCR_DMA_Msk (0x01 << SYS_RSTCR_DMA_Pos) +#define SYS_RSTCR_NORFLASH_Pos 5 //写1对NOR Flash控制器进行一次复位，硬件自动清零 +#define SYS_RSTCR_NORFLASH_Msk (0x01 << SYS_RSTCR_NORFLASH_Pos) +#define SYS_RSTCR_SRAM_Pos 6 //写1对SRAM控制器进行一次复位，硬件自动清零 +#define SYS_RSTCR_SRAM_Msk (0x01 << SYS_RSTCR_SRAM_Pos) +#define SYS_RSTCR_SDRAM_Pos 7 //写1对SDRAM控制器进行一次复位，硬件自动清零 +#define SYS_RSTCR_SDRAM_Msk (0x01 << SYS_RSTCR_SDRAM_Pos) +#define SYS_RSTCR_SDIO_Pos 8 //写1对SDIO进行一次复位，硬件自动清零 +#define SYS_RSTCR_SDIO_Msk (0x01 << SYS_RSTCR_SDIO_Pos) +#define SYS_RSTCR_LCD_Pos 9 //写1对LCD进行一次复位，硬件自动清零 +#define SYS_RSTCR_LCD_Msk (0x01 << SYS_RSTCR_LCD_Pos) +#define SYS_RSTCR_CAN_Pos 10 //写1对CAN进行一次复位，硬件自动清零 +#define SYS_RSTCR_CAN_Msk (0x01 << SYS_RSTCR_CAN_Pos) + +#define SYS_RSTSR_POR_Pos 0 //1 出现过POR复位，写1清零 +#define SYS_RSTSR_POR_Msk (0x01 << SYS_RSTSR_POR_Pos) +#define SYS_RSTSR_BOD_Pos 1 //1 出现过BOD复位，写1清零 +#define SYS_RSTSR_BOD_Msk (0x01 << SYS_RSTSR_BOD_Pos) +#define SYS_RSTSR_PIN_Pos 2 //1 出现过外部引脚复位，写1清零 +#define SYS_RSTSR_PIN_Msk (0x01 << SYS_RSTSR_PIN_Pos) +#define SYS_RSTSR_WDT_Pos 3 //1 出现过WDT复位，写1清零 +#define SYS_RSTSR_WDT_Msk (0x01 << SYS_RSTSR_WDT_Pos) +#define SYS_RSTSR_SWRST_Pos 4 //Software Reset, 1 出现过软件复位，写1清零 +#define SYS_RSTSR_SWRST_Msk (0x01 << SYS_RSTSR_SWRST_Pos) + +#define SYS_LRCCR_OFF_Pos 0 //Low Speed RC Off +#define SYS_LRCCR_OFF_Msk (0x01 << SYS_LRCCR_OFF_Pos) + +#define SYS_LRCTRIM0_R_Pos 0 //LRC粗调控制位 +#define SYS_LRCTRIM0_R_Msk (0x7FFF << SYS_LRCTRIM0_R_Pos) +#define SYS_LRCTRIM0_M_Pos 15 //LRC中调控制位 +#define SYS_LRCTRIM0_M_Msk (0x3F << SYS_LRCTRIM2_M_Pos) +#define SYS_LRCTRIM0_F_Pos 21 //LRC细调控制位 +#define SYS_LRCTRIM0_F_Msk (0x7FF << SYS_LRCTRIM0_F_Pos) + +#define SYS_LRCTRIM1_U_Pos 0 //LRC U调控制位 +#define SYS_LRCTRIM1_U_Msk (0x7FFF << SYS_LRCTRIM1_U_Pos) + +#define SYS_HRCCR_DBL_Pos 0 //Double Frequency 0 20MHz 1 40MHz +#define SYS_HRCCR_DBL_Msk (0x01 << SYS_HRCCR_DBL_Pos) +#define SYS_HRCCR_OFF_Pos 1 //High speed RC Off +#define SYS_HRCCR_OFF_Msk (0x01 << SYS_HRCCR_OFF_Pos) + +#define SYS_XTALCR_EN_Pos 0 +#define SYS_XTALCR_EN_Msk (0x01 << SYS_XTALCR_EN_Pos) + +#define SYS_PLLCR_OUTEN_Pos 0 //只能LOCK后设置 +#define SYS_PLLCR_OUTEN_Msk (0x01 << SYS_PLLCR_OUTEN_Pos) +#define SYS_PLLCR_INSEL_Pos 1 //0 XTAL 1 HRC +#define SYS_PLLCR_INSEL_Msk (0x01 << SYS_PLLCR_INSEL_Pos) +#define SYS_PLLCR_OFF_Pos 2 +#define SYS_PLLCR_OFF_Msk (0x01 << SYS_PLLCR_OFF_Pos) + +#define SYS_PLLDIV_FBDIV_Pos 0 //PLL FeedBack分频寄存器 \ + //VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV \ + //PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV +#define SYS_PLLDIV_FBDIV_Msk (0x1FF << SYS_PLLDIV_FBDIV_Pos) +#define SYS_PLLDIV_ADDIV_Pos 9 //ADC时钟基（即VCO输出分频后的时钟）经ADDIV分频后作为ADC的转换时钟 +#define SYS_PLLDIV_ADDIV_Msk (0x1F << SYS_PLLDIV_ADDIV_Pos) +#define SYS_PLLDIV_ADVCO_Pos 14 //0 VCO输出16分频作为ADC时钟基 1 VCO输出经过32分频作为ADC时钟基 2 VCO输出经过64分频作为ADC时钟基 +#define SYS_PLLDIV_ADVCO_Msk (0x03 << SYS_PLLDIV_ADVCO_Pos) +#define SYS_PLLDIV_INDIV_Pos 16 //PLL 输入源时钟分频 +#define SYS_PLLDIV_INDIV_Msk (0x1F << SYS_PLLDIV_INDIV_Pos) +#define SYS_PLLDIV_OUTDIV_Pos 24 //PLL 输出分频，0 8分频 1 4分频 0 2分频 +#define SYS_PLLDIV_OUTDIV_Msk (0x03 << SYS_PLLDIV_OUTDIV_Pos) + +#define SYS_PLLSET_LPFBW_Pos 0 //PLL Low Pass Filter Bandwidth +#define SYS_PLLSET_LPFBW_Msk (0x0F << SYS_PLLSET_LPFBW_Pos) +#define SYS_PLLSET_BIASADJ_Pos 4 //PLL Current Bias Adjustment +#define SYS_PLLSET_BIASADJ_Msk (0x03 << SYS_PLLSET_BIASADJ_Pos) +#define SYS_PLLSET_REFVSEL_Pos 6 //PLL Reference Voltage Select +#define SYS_PLLSET_REFVSEL_Msk (0x03 << SYS_PLLSET_REFVSEL_Pos) +#define SYS_PLLSET_CHPADJL_Pos 8 //PLL charge pump LSB current Adjustment +#define SYS_PLLSET_CHPADJL_Msk (0x07 << SYS_PLLSET_CHPADJL_Pos) +#define SYS_PLLSET_CHPADJM_Pos 11 //PLL charge pump MSB current Adjustment +#define SYS_PLLSET_CHPADJM_Msk (0x03 << SYS_PLLSET_CHPADJM_Pos) + +#define SYS_BODIE_2V2_Pos 1 //BOD 2.2V等级触发中断使能 +#define SYS_BODIE_2V2_Msk (0x01 << SYS_BODIE_2V2_Pos) + +#define SYS_BODIF_2V2_Pos 1 //BOD 2.2V等级触发中断状态，写1清零 +#define SYS_BODIF_2V2_Msk (0x01 << SYS_BODIF_2V2_Pos) + +#define SYS_ADC1IN7_SEL_Pos 0 //ADC1模块模拟通道7，1 温度传感器 2 电池电压 3 RTC电源域BG 4 主电源域BG 5 PDM33 +#define SYS_ADC1IN7_SEL_Msk (0x0F << SYS_ADC1IN7_SEL_Pos) +#define SYS_ADC1IN7_IOON_Pos 4 //ADC1模块模拟通道7所用IO开关 +#define SYS_ADC1IN7_IOON_Msk (0x01 << SYS_ADC1IN7_IOON_Pos) + +typedef struct +{ + __IO uint32_t PORTA_SEL; //给PORTA_SEL[2n+2:2n]赋相应的值，将PORTA.PINn引脚配置成GPIO、模拟、数字等功能 + //当赋值为PORTA_PINn_FUNMUX时，PORTA.PINn引脚可通过PORTA_MUX寄存器连接到各种数字外设 + __IO uint32_t PORTB_SEL; + + __IO uint32_t PORTC_SEL; + + uint32_t RESERVED[5]; + + __IO uint32_t PORTM_SEL0; + + __IO uint32_t PORTM_SEL1; + + uint32_t RESERVED2[2]; + + __IO uint32_t PORTN_SEL0; + + __IO uint32_t PORTN_SEL1; + + uint32_t RESERVED3[2]; + + __IO uint32_t PORTP_SEL0; + + __IO uint32_t PORTP_SEL1; + + uint32_t RESERVED4[46]; + + __IO uint32_t PORTA_MUX0; + + __IO uint32_t PORTA_MUX1; + + uint32_t RESERVED5[2]; + + __IO uint32_t PORTB_MUX0; + + __IO uint32_t PORTB_MUX1; + + uint32_t RESERVED6[2]; + + __IO uint32_t PORTC_MUX0; + + __IO uint32_t PORTC_MUX1; + + uint32_t RESERVED7[14]; + + __IO uint32_t PORTM_MUX0; + + __IO uint32_t PORTM_MUX1; + + __IO uint32_t PORTM_MUX2; + + __IO uint32_t PORTM_MUX3; + + __IO uint32_t PORTN_MUX0; + + __IO uint32_t PORTN_MUX1; + + __IO uint32_t PORTN_MUX2; + + uint32_t RESERVED8; + + __IO uint32_t PORTP_MUX0; + + __IO uint32_t PORTP_MUX1; + + __IO uint32_t PORTP_MUX2; + + __IO uint32_t PORTP_MUX3; + + uint32_t RESERVED9[28]; + + __IO uint32_t PORTA_PULLU; //上拉使能 + + uint32_t RESERVED10[3]; + + __IO uint32_t PORTC_PULLU; + + uint32_t RESERVED11[3]; + + __IO uint32_t PORTM_PULLU; + + uint32_t RESERVED12[3]; + + __IO uint32_t PORTP_PULLU; + + uint32_t RESERVED13[51]; + + __IO uint32_t PORTB_PULLD; //下拉使能 + + uint32_t RESERVED14[3]; + + __IO uint32_t PORTD_PULLD; + + uint32_t RESERVED15[3]; + + __IO uint32_t PORTN_PULLD; + + uint32_t RESERVED16[135]; + + __IO uint32_t PORTM_DRIVS; //驱动强度 + + uint32_t RESERVED17[3]; + + __IO uint32_t PORTN_DRIVS; + + uint32_t RESERVED18[3]; + + __IO uint32_t PORTP_DRIVS; + + uint32_t RESERVED19[39]; + + __IO uint32_t PORTA_INEN; //输入使能 + + uint32_t RESERVED20[3]; + + __IO uint32_t PORTB_INEN; + + uint32_t RESERVED21[3]; + + __IO uint32_t PORTC_INEN; + + uint32_t RESERVED22[7]; + + __IO uint32_t PORTM_INEN; + + uint32_t RESERVED23[3]; + + __IO uint32_t PORTN_INEN; + + uint32_t RESERVED24[3]; + + __IO uint32_t PORTP_INEN; +} PORT_TypeDef; + +#define PORT_PORTA_PULLU_PIN0_Pos 0 +#define PORT_PORTA_PULLU_PIN0_Msk (0x01 << PORT_PORTA_PULLU_PIN0_Pos) +#define PORT_PORTA_PULLU_PIN1_Pos 1 +#define PORT_PORTA_PULLU_PIN1_Msk (0x01 << PORT_PORTA_PULLU_PIN1_Pos) +#define PORT_PORTA_PULLU_PIN2_Pos 2 +#define PORT_PORTA_PULLU_PIN2_Msk (0x01 << PORT_PORTA_PULLU_PIN2_Pos) +#define PORT_PORTA_PULLU_PIN3_Pos 3 +#define PORT_PORTA_PULLU_PIN3_Msk (0x01 << PORT_PORTA_PULLU_PIN3_Pos) +#define PORT_PORTA_PULLU_PIN4_Pos 4 +#define PORT_PORTA_PULLU_PIN4_Msk (0x01 << PORT_PORTA_PULLU_PIN4_Pos) +#define PORT_PORTA_PULLU_PIN5_Pos 5 +#define PORT_PORTA_PULLU_PIN5_Msk (0x01 << PORT_PORTA_PULLU_PIN5_Pos) +#define PORT_PORTA_PULLU_PIN6_Pos 6 +#define PORT_PORTA_PULLU_PIN6_Msk (0x01 << PORT_PORTA_PULLU_PIN6_Pos) +#define PORT_PORTA_PULLU_PIN7_Pos 7 +#define PORT_PORTA_PULLU_PIN7_Msk (0x01 << PORT_PORTA_PULLU_PIN7_Pos) +#define PORT_PORTA_PULLU_PIN8_Pos 8 +#define PORT_PORTA_PULLU_PIN8_Msk (0x01 << PORT_PORTA_PULLU_PIN8_Pos) +#define PORT_PORTA_PULLU_PIN9_Pos 9 +#define PORT_PORTA_PULLU_PIN9_Msk (0x01 << PORT_PORTA_PULLU_PIN9_Pos) +#define PORT_PORTA_PULLU_PIN10_Pos 10 +#define PORT_PORTA_PULLU_PIN10_Msk (0x01 << PORT_PORTA_PULLU_PIN10_Pos) +#define PORT_PORTA_PULLU_PIN11_Pos 11 +#define PORT_PORTA_PULLU_PIN11_Msk (0x01 << PORT_PORTA_PULLU_PIN11_Pos) +#define PORT_PORTA_PULLU_PIN12_Pos 12 +#define PORT_PORTA_PULLU_PIN12_Msk (0x01 << PORT_PORTA_PULLU_PIN12_Pos) +#define PORT_PORTA_PULLU_PIN13_Pos 13 +#define PORT_PORTA_PULLU_PIN13_Msk (0x01 << PORT_PORTA_PULLU_PIN13_Pos) +#define PORT_PORTA_PULLU_PIN14_Pos 14 +#define PORT_PORTA_PULLU_PIN14_Msk (0x01 << PORT_PORTA_PULLU_PIN14_Pos) +#define PORT_PORTA_PULLU_PIN15_Pos 15 +#define PORT_PORTA_PULLU_PIN15_Msk (0x01 << PORT_PORTA_PULLU_PIN15_Pos) + +#define PORT_PORTC_PULLU_PIN0_Pos 0 +#define PORT_PORTC_PULLU_PIN0_Msk (0x01 << PORT_PORTC_PULLU_PIN0_Pos) +#define PORT_PORTC_PULLU_PIN1_Pos 1 +#define PORT_PORTC_PULLU_PIN1_Msk (0x01 << PORT_PORTC_PULLU_PIN1_Pos) +#define PORT_PORTC_PULLU_PIN2_Pos 2 +#define PORT_PORTC_PULLU_PIN2_Msk (0x01 << PORT_PORTC_PULLU_PIN2_Pos) +#define PORT_PORTC_PULLU_PIN3_Pos 3 +#define PORT_PORTC_PULLU_PIN3_Msk (0x01 << PORT_PORTC_PULLU_PIN3_Pos) +#define PORT_PORTC_PULLU_PIN4_Pos 4 +#define PORT_PORTC_PULLU_PIN4_Msk (0x01 << PORT_PORTC_PULLU_PIN4_Pos) +#define PORT_PORTC_PULLU_PIN5_Pos 5 +#define PORT_PORTC_PULLU_PIN5_Msk (0x01 << PORT_PORTC_PULLU_PIN5_Pos) +#define PORT_PORTC_PULLU_PIN6_Pos 6 +#define PORT_PORTC_PULLU_PIN6_Msk (0x01 << PORT_PORTC_PULLU_PIN6_Pos) +#define PORT_PORTC_PULLU_PIN7_Pos 7 +#define PORT_PORTC_PULLU_PIN7_Msk (0x01 << PORT_PORTC_PULLU_PIN7_Pos) +#define PORT_PORTC_PULLU_PIN8_Pos 8 +#define PORT_PORTC_PULLU_PIN8_Msk (0x01 << PORT_PORTC_PULLU_PIN8_Pos) +#define PORT_PORTC_PULLU_PIN9_Pos 9 +#define PORT_PORTC_PULLU_PIN9_Msk (0x01 << PORT_PORTC_PULLU_PIN9_Pos) +#define PORT_PORTC_PULLU_PIN10_Pos 10 +#define PORT_PORTC_PULLU_PIN10_Msk (0x01 << PORT_PORTC_PULLU_PIN10_Pos) +#define PORT_PORTC_PULLU_PIN11_Pos 11 +#define PORT_PORTC_PULLU_PIN11_Msk (0x01 << PORT_PORTC_PULLU_PIN11_Pos) +#define PORT_PORTC_PULLU_PIN12_Pos 12 +#define PORT_PORTC_PULLU_PIN12_Msk (0x01 << PORT_PORTC_PULLU_PIN12_Pos) +#define PORT_PORTC_PULLU_PIN13_Pos 13 +#define PORT_PORTC_PULLU_PIN13_Msk (0x01 << PORT_PORTC_PULLU_PIN13_Pos) +#define PORT_PORTC_PULLU_PIN14_Pos 14 +#define PORT_PORTC_PULLU_PIN14_Msk (0x01 << PORT_PORTC_PULLU_PIN14_Pos) +#define PORT_PORTC_PULLU_PIN15_Pos 15 +#define PORT_PORTC_PULLU_PIN15_Msk (0x01 << PORT_PORTC_PULLU_PIN15_Pos) + +#define PORT_PORTM_PULLU_PIN0_Pos 0 +#define PORT_PORTM_PULLU_PIN0_Msk (0x01 << PORT_PORTM_PULLU_PIN0_Pos) +#define PORT_PORTM_PULLU_PIN1_Pos 1 +#define PORT_PORTM_PULLU_PIN1_Msk (0x01 << PORT_PORTM_PULLU_PIN1_Pos) +#define PORT_PORTM_PULLU_PIN2_Pos 2 +#define PORT_PORTM_PULLU_PIN2_Msk (0x01 << PORT_PORTM_PULLU_PIN2_Pos) +#define PORT_PORTM_PULLU_PIN3_Pos 3 +#define PORT_PORTM_PULLU_PIN3_Msk (0x01 << PORT_PORTM_PULLU_PIN3_Pos) +#define PORT_PORTM_PULLU_PIN4_Pos 4 +#define PORT_PORTM_PULLU_PIN4_Msk (0x01 << PORT_PORTM_PULLU_PIN4_Pos) +#define PORT_PORTM_PULLU_PIN5_Pos 5 +#define PORT_PORTM_PULLU_PIN5_Msk (0x01 << PORT_PORTM_PULLU_PIN5_Pos) +#define PORT_PORTM_PULLU_PIN6_Pos 6 +#define PORT_PORTM_PULLU_PIN6_Msk (0x01 << PORT_PORTM_PULLU_PIN6_Pos) +#define PORT_PORTM_PULLU_PIN7_Pos 7 +#define PORT_PORTM_PULLU_PIN7_Msk (0x01 << PORT_PORTM_PULLU_PIN7_Pos) +#define PORT_PORTM_PULLU_PIN8_Pos 8 +#define PORT_PORTM_PULLU_PIN8_Msk (0x01 << PORT_PORTM_PULLU_PIN8_Pos) +#define PORT_PORTM_PULLU_PIN9_Pos 9 +#define PORT_PORTM_PULLU_PIN9_Msk (0x01 << PORT_PORTM_PULLU_PIN9_Pos) +#define PORT_PORTM_PULLU_PIN10_Pos 10 +#define PORT_PORTM_PULLU_PIN10_Msk (0x01 << PORT_PORTM_PULLU_PIN10_Pos) +#define PORT_PORTM_PULLU_PIN11_Pos 11 +#define PORT_PORTM_PULLU_PIN11_Msk (0x01 << PORT_PORTM_PULLU_PIN11_Pos) +#define PORT_PORTM_PULLU_PIN12_Pos 12 +#define PORT_PORTM_PULLU_PIN12_Msk (0x01 << PORT_PORTM_PULLU_PIN12_Pos) +#define PORT_PORTM_PULLU_PIN13_Pos 13 +#define PORT_PORTM_PULLU_PIN13_Msk (0x01 << PORT_PORTM_PULLU_PIN13_Pos) +#define PORT_PORTM_PULLU_PIN14_Pos 14 +#define PORT_PORTM_PULLU_PIN14_Msk (0x01 << PORT_PORTM_PULLU_PIN14_Pos) +#define PORT_PORTM_PULLU_PIN15_Pos 15 +#define PORT_PORTM_PULLU_PIN15_Msk (0x01 << PORT_PORTM_PULLU_PIN15_Pos) +#define PORT_PORTM_PULLU_PIN16_Pos 16 +#define PORT_PORTM_PULLU_PIN16_Msk (0x01 << PORT_PORTM_PULLU_PIN16_Pos) +#define PORT_PORTM_PULLU_PIN17_Pos 17 +#define PORT_PORTM_PULLU_PIN17_Msk (0x01 << PORT_PORTM_PULLU_PIN17_Pos) +#define PORT_PORTM_PULLU_PIN18_Pos 18 +#define PORT_PORTM_PULLU_PIN18_Msk (0x01 << PORT_PORTM_PULLU_PIN18_Pos) +#define PORT_PORTM_PULLU_PIN19_Pos 19 +#define PORT_PORTM_PULLU_PIN19_Msk (0x01 << PORT_PORTM_PULLU_PIN19_Pos) +#define PORT_PORTM_PULLU_PIN20_Pos 20 +#define PORT_PORTM_PULLU_PIN20_Msk (0x01 << PORT_PORTM_PULLU_PIN20_Pos) +#define PORT_PORTM_PULLU_PIN21_Pos 21 +#define PORT_PORTM_PULLU_PIN21_Msk (0x01 << PORT_PORTM_PULLU_PIN21_Pos) +#define PORT_PORTM_PULLU_PIN22_Pos 22 +#define PORT_PORTM_PULLU_PIN22_Msk (0x01 << PORT_PORTM_PULLU_PIN22_Pos) +#define PORT_PORTM_PULLU_PIN23_Pos 23 +#define PORT_PORTM_PULLU_PIN23_Msk (0x01 << PORT_PORTM_PULLU_PIN23_Pos) + +#define PORT_PORTP_PULLU_PIN0_Pos 0 +#define PORT_PORTP_PULLU_PIN0_Msk (0x01 << PORT_PORTP_PULLU_PIN0_Pos) +#define PORT_PORTP_PULLU_PIN1_Pos 1 +#define PORT_PORTP_PULLU_PIN1_Msk (0x01 << PORT_PORTP_PULLU_PIN1_Pos) +#define PORT_PORTP_PULLU_PIN2_Pos 2 +#define PORT_PORTP_PULLU_PIN2_Msk (0x01 << PORT_PORTP_PULLU_PIN2_Pos) +#define PORT_PORTP_PULLU_PIN3_Pos 3 +#define PORT_PORTP_PULLU_PIN3_Msk (0x01 << PORT_PORTP_PULLU_PIN3_Pos) +#define PORT_PORTP_PULLU_PIN4_Pos 4 +#define PORT_PORTP_PULLU_PIN4_Msk (0x01 << PORT_PORTP_PULLU_PIN4_Pos) +#define PORT_PORTP_PULLU_PIN5_Pos 5 +#define PORT_PORTP_PULLU_PIN5_Msk (0x01 << PORT_PORTP_PULLU_PIN5_Pos) +#define PORT_PORTP_PULLU_PIN6_Pos 6 +#define PORT_PORTP_PULLU_PIN6_Msk (0x01 << PORT_PORTP_PULLU_PIN6_Pos) +#define PORT_PORTP_PULLU_PIN7_Pos 7 +#define PORT_PORTP_PULLU_PIN7_Msk (0x01 << PORT_PORTP_PULLU_PIN7_Pos) +#define PORT_PORTP_PULLU_PIN8_Pos 8 +#define PORT_PORTP_PULLU_PIN8_Msk (0x01 << PORT_PORTP_PULLU_PIN8_Pos) +#define PORT_PORTP_PULLU_PIN9_Pos 9 +#define PORT_PORTP_PULLU_PIN9_Msk (0x01 << PORT_PORTP_PULLU_PIN9_Pos) +#define PORT_PORTP_PULLU_PIN10_Pos 10 +#define PORT_PORTP_PULLU_PIN10_Msk (0x01 << PORT_PORTP_PULLU_PIN10_Pos) +#define PORT_PORTP_PULLU_PIN11_Pos 11 +#define PORT_PORTP_PULLU_PIN11_Msk (0x01 << PORT_PORTP_PULLU_PIN11_Pos) +#define PORT_PORTP_PULLU_PIN12_Pos 12 +#define PORT_PORTP_PULLU_PIN12_Msk (0x01 << PORT_PORTP_PULLU_PIN12_Pos) +#define PORT_PORTP_PULLU_PIN13_Pos 13 +#define PORT_PORTP_PULLU_PIN13_Msk (0x01 << PORT_PORTP_PULLU_PIN13_Pos) +#define PORT_PORTP_PULLU_PIN14_Pos 14 +#define PORT_PORTP_PULLU_PIN14_Msk (0x01 << PORT_PORTP_PULLU_PIN14_Pos) +#define PORT_PORTP_PULLU_PIN15_Pos 15 +#define PORT_PORTP_PULLU_PIN15_Msk (0x01 << PORT_PORTP_PULLU_PIN15_Pos) +#define PORT_PORTP_PULLU_PIN16_Pos 16 +#define PORT_PORTP_PULLU_PIN16_Msk (0x01 << PORT_PORTP_PULLU_PIN16_Pos) +#define PORT_PORTP_PULLU_PIN17_Pos 17 +#define PORT_PORTP_PULLU_PIN17_Msk (0x01 << PORT_PORTP_PULLU_PIN17_Pos) +#define PORT_PORTP_PULLU_PIN18_Pos 18 +#define PORT_PORTP_PULLU_PIN18_Msk (0x01 << PORT_PORTP_PULLU_PIN18_Pos) +#define PORT_PORTP_PULLU_PIN19_Pos 19 +#define PORT_PORTP_PULLU_PIN19_Msk (0x01 << PORT_PORTP_PULLU_PIN19_Pos) +#define PORT_PORTP_PULLU_PIN20_Pos 20 +#define PORT_PORTP_PULLU_PIN20_Msk (0x01 << PORT_PORTP_PULLU_PIN20_Pos) +#define PORT_PORTP_PULLU_PIN21_Pos 21 +#define PORT_PORTP_PULLU_PIN21_Msk (0x01 << PORT_PORTP_PULLU_PIN21_Pos) +#define PORT_PORTP_PULLU_PIN22_Pos 22 +#define PORT_PORTP_PULLU_PIN22_Msk (0x01 << PORT_PORTP_PULLU_PIN22_Pos) +#define PORT_PORTP_PULLU_PIN23_Pos 23 +#define PORT_PORTP_PULLU_PIN23_Msk (0x01 << PORT_PORTP_PULLU_PIN23_Pos) + +#define PORT_PORTB_PULLD_PIN0_Pos 0 +#define PORT_PORTB_PULLD_PIN0_Msk (0x01 << PORT_PORTB_PULLD_PIN0_Pos) +#define PORT_PORTB_PULLD_PIN1_Pos 1 +#define PORT_PORTB_PULLD_PIN1_Msk (0x01 << PORT_PORTB_PULLD_PIN1_Pos) +#define PORT_PORTB_PULLD_PIN2_Pos 2 +#define PORT_PORTB_PULLD_PIN2_Msk (0x01 << PORT_PORTB_PULLD_PIN2_Pos) +#define PORT_PORTB_PULLD_PIN3_Pos 3 +#define PORT_PORTB_PULLD_PIN3_Msk (0x01 << PORT_PORTB_PULLD_PIN3_Pos) +#define PORT_PORTB_PULLD_PIN4_Pos 4 +#define PORT_PORTB_PULLD_PIN4_Msk (0x01 << PORT_PORTB_PULLD_PIN4_Pos) +#define PORT_PORTB_PULLD_PIN5_Pos 5 +#define PORT_PORTB_PULLD_PIN5_Msk (0x01 << PORT_PORTB_PULLD_PIN5_Pos) +#define PORT_PORTB_PULLD_PIN6_Pos 6 +#define PORT_PORTB_PULLD_PIN6_Msk (0x01 << PORT_PORTB_PULLD_PIN6_Pos) +#define PORT_PORTB_PULLD_PIN7_Pos 7 +#define PORT_PORTB_PULLD_PIN7_Msk (0x01 << PORT_PORTB_PULLD_PIN7_Pos) +#define PORT_PORTB_PULLD_PIN8_Pos 8 +#define PORT_PORTB_PULLD_PIN8_Msk (0x01 << PORT_PORTB_PULLD_PIN8_Pos) +#define PORT_PORTB_PULLD_PIN9_Pos 9 +#define PORT_PORTB_PULLD_PIN9_Msk (0x01 << PORT_PORTB_PULLD_PIN9_Pos) +#define PORT_PORTB_PULLD_PIN10_Pos 10 +#define PORT_PORTB_PULLD_PIN10_Msk (0x01 << PORT_PORTB_PULLD_PIN10_Pos) +#define PORT_PORTB_PULLD_PIN11_Pos 11 +#define PORT_PORTB_PULLD_PIN11_Msk (0x01 << PORT_PORTB_PULLD_PIN11_Pos) +#define PORT_PORTB_PULLD_PIN12_Pos 12 +#define PORT_PORTB_PULLD_PIN12_Msk (0x01 << PORT_PORTB_PULLD_PIN12_Pos) +#define PORT_PORTB_PULLD_PIN13_Pos 13 +#define PORT_PORTB_PULLD_PIN13_Msk (0x01 << PORT_PORTB_PULLD_PIN13_Pos) +#define PORT_PORTB_PULLD_PIN14_Pos 14 +#define PORT_PORTB_PULLD_PIN14_Msk (0x01 << PORT_PORTB_PULLD_PIN14_Pos) +#define PORT_PORTB_PULLD_PIN15_Pos 15 +#define PORT_PORTB_PULLD_PIN15_Msk (0x01 << PORT_PORTB_PULLD_PIN15_Pos) + +#define PORT_PORTN_PULLD_PIN0_Pos 0 +#define PORT_PORTN_PULLD_PIN0_Msk (0x01 << PORT_PORTN_PULLD_PIN0_Pos) +#define PORT_PORTN_PULLD_PIN1_Pos 1 +#define PORT_PORTN_PULLD_PIN1_Msk (0x01 << PORT_PORTN_PULLD_PIN1_Pos) +#define PORT_PORTN_PULLD_PIN2_Pos 2 +#define PORT_PORTN_PULLD_PIN2_Msk (0x01 << PORT_PORTN_PULLD_PIN2_Pos) +#define PORT_PORTN_PULLD_PIN3_Pos 3 +#define PORT_PORTN_PULLD_PIN3_Msk (0x01 << PORT_PORTN_PULLD_PIN3_Pos) +#define PORT_PORTN_PULLD_PIN4_Pos 4 +#define PORT_PORTN_PULLD_PIN4_Msk (0x01 << PORT_PORTN_PULLD_PIN4_Pos) +#define PORT_PORTN_PULLD_PIN5_Pos 5 +#define PORT_PORTN_PULLD_PIN5_Msk (0x01 << PORT_PORTN_PULLD_PIN5_Pos) +#define PORT_PORTN_PULLD_PIN6_Pos 6 +#define PORT_PORTN_PULLD_PIN6_Msk (0x01 << PORT_PORTN_PULLD_PIN6_Pos) +#define PORT_PORTN_PULLD_PIN7_Pos 7 +#define PORT_PORTN_PULLD_PIN7_Msk (0x01 << PORT_PORTN_PULLD_PIN7_Pos) +#define PORT_PORTN_PULLD_PIN8_Pos 8 +#define PORT_PORTN_PULLD_PIN8_Msk (0x01 << PORT_PORTN_PULLD_PIN8_Pos) +#define PORT_PORTN_PULLD_PIN9_Pos 9 +#define PORT_PORTN_PULLD_PIN9_Msk (0x01 << PORT_PORTN_PULLD_PIN9_Pos) +#define PORT_PORTN_PULLD_PIN10_Pos 10 +#define PORT_PORTN_PULLD_PIN10_Msk (0x01 << PORT_PORTN_PULLD_PIN10_Pos) +#define PORT_PORTN_PULLD_PIN11_Pos 11 +#define PORT_PORTN_PULLD_PIN11_Msk (0x01 << PORT_PORTN_PULLD_PIN11_Pos) +#define PORT_PORTN_PULLD_PIN12_Pos 12 +#define PORT_PORTN_PULLD_PIN12_Msk (0x01 << PORT_PORTN_PULLD_PIN12_Pos) +#define PORT_PORTN_PULLD_PIN13_Pos 13 +#define PORT_PORTN_PULLD_PIN13_Msk (0x01 << PORT_PORTN_PULLD_PIN13_Pos) +#define PORT_PORTN_PULLD_PIN14_Pos 14 +#define PORT_PORTN_PULLD_PIN14_Msk (0x01 << PORT_PORTN_PULLD_PIN14_Pos) +#define PORT_PORTN_PULLD_PIN15_Pos 15 +#define PORT_PORTN_PULLD_PIN15_Msk (0x01 << PORT_PORTN_PULLD_PIN15_Pos) +#define PORT_PORTN_PULLD_PIN16_Pos 16 +#define PORT_PORTN_PULLD_PIN16_Msk (0x01 << PORT_PORTN_PULLD_PIN16_Pos) +#define PORT_PORTN_PULLD_PIN17_Pos 17 +#define PORT_PORTN_PULLD_PIN17_Msk (0x01 << PORT_PORTN_PULLD_PIN17_Pos) +#define PORT_PORTN_PULLD_PIN18_Pos 18 +#define PORT_PORTN_PULLD_PIN18_Msk (0x01 << PORT_PORTN_PULLD_PIN18_Pos) +#define PORT_PORTN_PULLD_PIN19_Pos 19 +#define PORT_PORTN_PULLD_PIN19_Msk (0x01 << PORT_PORTN_PULLD_PIN19_Pos) +#define PORT_PORTN_PULLD_PIN20_Pos 20 +#define PORT_PORTN_PULLD_PIN20_Msk (0x01 << PORT_PORTN_PULLD_PIN20_Pos) +#define PORT_PORTN_PULLD_PIN21_Pos 21 +#define PORT_PORTN_PULLD_PIN21_Msk (0x01 << PORT_PORTN_PULLD_PIN21_Pos) +#define PORT_PORTN_PULLD_PIN22_Pos 22 +#define PORT_PORTN_PULLD_PIN22_Msk (0x01 << PORT_PORTN_PULLD_PIN22_Pos) +#define PORT_PORTN_PULLD_PIN23_Pos 23 +#define PORT_PORTN_PULLD_PIN23_Msk (0x01 << PORT_PORTN_PULLD_PIN23_Pos) + +#define PORT_PORTM_DRIVS_PIN0_Pos 0 +#define PORT_PORTM_DRIVS_PIN0_Msk (0x01 << PORT_PORTM_DRIVS_PIN0_Pos) +#define PORT_PORTM_DRIVS_PIN1_Pos 1 +#define PORT_PORTM_DRIVS_PIN1_Msk (0x01 << PORT_PORTM_DRIVS_PIN1_Pos) +#define PORT_PORTM_DRIVS_PIN2_Pos 2 +#define PORT_PORTM_DRIVS_PIN2_Msk (0x01 << PORT_PORTM_DRIVS_PIN2_Pos) +#define PORT_PORTM_DRIVS_PIN3_Pos 3 +#define PORT_PORTM_DRIVS_PIN3_Msk (0x01 << PORT_PORTM_DRIVS_PIN3_Pos) +#define PORT_PORTM_DRIVS_PIN4_Pos 4 +#define PORT_PORTM_DRIVS_PIN4_Msk (0x01 << PORT_PORTM_DRIVS_PIN4_Pos) +#define PORT_PORTM_DRIVS_PIN5_Pos 5 +#define PORT_PORTM_DRIVS_PIN5_Msk (0x01 << PORT_PORTM_DRIVS_PIN5_Pos) +#define PORT_PORTM_DRIVS_PIN6_Pos 6 +#define PORT_PORTM_DRIVS_PIN6_Msk (0x01 << PORT_PORTM_DRIVS_PIN6_Pos) +#define PORT_PORTM_DRIVS_PIN7_Pos 7 +#define PORT_PORTM_DRIVS_PIN7_Msk (0x01 << PORT_PORTM_DRIVS_PIN7_Pos) +#define PORT_PORTM_DRIVS_PIN8_Pos 8 +#define PORT_PORTM_DRIVS_PIN8_Msk (0x01 << PORT_PORTM_DRIVS_PIN8_Pos) +#define PORT_PORTM_DRIVS_PIN9_Pos 9 +#define PORT_PORTM_DRIVS_PIN9_Msk (0x01 << PORT_PORTM_DRIVS_PIN9_Pos) +#define PORT_PORTM_DRIVS_PIN10_Pos 10 +#define PORT_PORTM_DRIVS_PIN10_Msk (0x01 << PORT_PORTM_DRIVS_PIN10_Pos) +#define PORT_PORTM_DRIVS_PIN11_Pos 11 +#define PORT_PORTM_DRIVS_PIN11_Msk (0x01 << PORT_PORTM_DRIVS_PIN11_Pos) +#define PORT_PORTM_DRIVS_PIN12_Pos 12 +#define PORT_PORTM_DRIVS_PIN12_Msk (0x01 << PORT_PORTM_DRIVS_PIN12_Pos) +#define PORT_PORTM_DRIVS_PIN13_Pos 13 +#define PORT_PORTM_DRIVS_PIN13_Msk (0x01 << PORT_PORTM_DRIVS_PIN13_Pos) +#define PORT_PORTM_DRIVS_PIN14_Pos 14 +#define PORT_PORTM_DRIVS_PIN14_Msk (0x01 << PORT_PORTM_DRIVS_PIN14_Pos) +#define PORT_PORTM_DRIVS_PIN15_Pos 15 +#define PORT_PORTM_DRIVS_PIN15_Msk (0x01 << PORT_PORTM_DRIVS_PIN15_Pos) +#define PORT_PORTM_DRIVS_PIN16_Pos 16 +#define PORT_PORTM_DRIVS_PIN16_Msk (0x01 << PORT_PORTM_DRIVS_PIN16_Pos) +#define PORT_PORTM_DRIVS_PIN17_Pos 17 +#define PORT_PORTM_DRIVS_PIN17_Msk (0x01 << PORT_PORTM_DRIVS_PIN17_Pos) +#define PORT_PORTM_DRIVS_PIN18_Pos 18 +#define PORT_PORTM_DRIVS_PIN18_Msk (0x01 << PORT_PORTM_DRIVS_PIN18_Pos) +#define PORT_PORTM_DRIVS_PIN19_Pos 19 +#define PORT_PORTM_DRIVS_PIN19_Msk (0x01 << PORT_PORTM_DRIVS_PIN19_Pos) +#define PORT_PORTM_DRIVS_PIN20_Pos 20 +#define PORT_PORTM_DRIVS_PIN20_Msk (0x01 << PORT_PORTM_DRIVS_PIN20_Pos) +#define PORT_PORTM_DRIVS_PIN21_Pos 21 +#define PORT_PORTM_DRIVS_PIN21_Msk (0x01 << PORT_PORTM_DRIVS_PIN21_Pos) +#define PORT_PORTM_DRIVS_PIN22_Pos 22 +#define PORT_PORTM_DRIVS_PIN22_Msk (0x01 << PORT_PORTM_DRIVS_PIN22_Pos) +#define PORT_PORTM_DRIVS_PIN23_Pos 23 +#define PORT_PORTM_DRIVS_PIN23_Msk (0x01 << PORT_PORTM_DRIVS_PIN23_Pos) + +#define PORT_PORTN_DRIVS_PIN0_Pos 0 +#define PORT_PORTN_DRIVS_PIN0_Msk (0x01 << PORT_PORTN_DRIVS_PIN0_Pos) +#define PORT_PORTN_DRIVS_PIN1_Pos 1 +#define PORT_PORTN_DRIVS_PIN1_Msk (0x01 << PORT_PORTN_DRIVS_PIN1_Pos) +#define PORT_PORTN_DRIVS_PIN2_Pos 2 +#define PORT_PORTN_DRIVS_PIN2_Msk (0x01 << PORT_PORTN_DRIVS_PIN2_Pos) +#define PORT_PORTN_DRIVS_PIN3_Pos 3 +#define PORT_PORTN_DRIVS_PIN3_Msk (0x01 << PORT_PORTN_DRIVS_PIN3_Pos) +#define PORT_PORTN_DRIVS_PIN4_Pos 4 +#define PORT_PORTN_DRIVS_PIN4_Msk (0x01 << PORT_PORTN_DRIVS_PIN4_Pos) +#define PORT_PORTN_DRIVS_PIN5_Pos 5 +#define PORT_PORTN_DRIVS_PIN5_Msk (0x01 << PORT_PORTN_DRIVS_PIN5_Pos) +#define PORT_PORTN_DRIVS_PIN6_Pos 6 +#define PORT_PORTN_DRIVS_PIN6_Msk (0x01 << PORT_PORTN_DRIVS_PIN6_Pos) +#define PORT_PORTN_DRIVS_PIN7_Pos 7 +#define PORT_PORTN_DRIVS_PIN7_Msk (0x01 << PORT_PORTN_DRIVS_PIN7_Pos) +#define PORT_PORTN_DRIVS_PIN8_Pos 8 +#define PORT_PORTN_DRIVS_PIN8_Msk (0x01 << PORT_PORTN_DRIVS_PIN8_Pos) +#define PORT_PORTN_DRIVS_PIN9_Pos 9 +#define PORT_PORTN_DRIVS_PIN9_Msk (0x01 << PORT_PORTN_DRIVS_PIN9_Pos) +#define PORT_PORTN_DRIVS_PIN10_Pos 10 +#define PORT_PORTN_DRIVS_PIN10_Msk (0x01 << PORT_PORTN_DRIVS_PIN10_Pos) +#define PORT_PORTN_DRIVS_PIN11_Pos 11 +#define PORT_PORTN_DRIVS_PIN11_Msk (0x01 << PORT_PORTN_DRIVS_PIN11_Pos) +#define PORT_PORTN_DRIVS_PIN12_Pos 12 +#define PORT_PORTN_DRIVS_PIN12_Msk (0x01 << PORT_PORTN_DRIVS_PIN12_Pos) +#define PORT_PORTN_DRIVS_PIN13_Pos 13 +#define PORT_PORTN_DRIVS_PIN13_Msk (0x01 << PORT_PORTN_DRIVS_PIN13_Pos) +#define PORT_PORTN_DRIVS_PIN14_Pos 14 +#define PORT_PORTN_DRIVS_PIN14_Msk (0x01 << PORT_PORTN_DRIVS_PIN14_Pos) +#define PORT_PORTN_DRIVS_PIN15_Pos 15 +#define PORT_PORTN_DRIVS_PIN15_Msk (0x01 << PORT_PORTN_DRIVS_PIN15_Pos) +#define PORT_PORTN_DRIVS_PIN16_Pos 16 +#define PORT_PORTN_DRIVS_PIN16_Msk (0x01 << PORT_PORTN_DRIVS_PIN16_Pos) +#define PORT_PORTN_DRIVS_PIN17_Pos 17 +#define PORT_PORTN_DRIVS_PIN17_Msk (0x01 << PORT_PORTN_DRIVS_PIN17_Pos) +#define PORT_PORTN_DRIVS_PIN18_Pos 18 +#define PORT_PORTN_DRIVS_PIN18_Msk (0x01 << PORT_PORTN_DRIVS_PIN18_Pos) +#define PORT_PORTN_DRIVS_PIN19_Pos 19 +#define PORT_PORTN_DRIVS_PIN19_Msk (0x01 << PORT_PORTN_DRIVS_PIN19_Pos) +#define PORT_PORTN_DRIVS_PIN20_Pos 20 +#define PORT_PORTN_DRIVS_PIN20_Msk (0x01 << PORT_PORTN_DRIVS_PIN20_Pos) +#define PORT_PORTN_DRIVS_PIN21_Pos 21 +#define PORT_PORTN_DRIVS_PIN21_Msk (0x01 << PORT_PORTN_DRIVS_PIN21_Pos) +#define PORT_PORTN_DRIVS_PIN22_Pos 22 +#define PORT_PORTN_DRIVS_PIN22_Msk (0x01 << PORT_PORTN_DRIVS_PIN22_Pos) +#define PORT_PORTN_DRIVS_PIN23_Pos 23 +#define PORT_PORTN_DRIVS_PIN23_Msk (0x01 << PORT_PORTN_DRIVS_PIN23_Pos) + +#define PORT_PORTP_DRIVS_PIN0_Pos 0 +#define PORT_PORTP_DRIVS_PIN0_Msk (0x01 << PORT_PORTP_DRIVS_PIN0_Pos) +#define PORT_PORTP_DRIVS_PIN1_Pos 1 +#define PORT_PORTP_DRIVS_PIN1_Msk (0x01 << PORT_PORTP_DRIVS_PIN1_Pos) +#define PORT_PORTP_DRIVS_PIN2_Pos 2 +#define PORT_PORTP_DRIVS_PIN2_Msk (0x01 << PORT_PORTP_DRIVS_PIN2_Pos) +#define PORT_PORTP_DRIVS_PIN3_Pos 3 +#define PORT_PORTP_DRIVS_PIN3_Msk (0x01 << PORT_PORTP_DRIVS_PIN3_Pos) +#define PORT_PORTP_DRIVS_PIN4_Pos 4 +#define PORT_PORTP_DRIVS_PIN4_Msk (0x01 << PORT_PORTP_DRIVS_PIN4_Pos) +#define PORT_PORTP_DRIVS_PIN5_Pos 5 +#define PORT_PORTP_DRIVS_PIN5_Msk (0x01 << PORT_PORTP_DRIVS_PIN5_Pos) +#define PORT_PORTP_DRIVS_PIN6_Pos 6 +#define PORT_PORTP_DRIVS_PIN6_Msk (0x01 << PORT_PORTP_DRIVS_PIN6_Pos) +#define PORT_PORTP_DRIVS_PIN7_Pos 7 +#define PORT_PORTP_DRIVS_PIN7_Msk (0x01 << PORT_PORTP_DRIVS_PIN7_Pos) +#define PORT_PORTP_DRIVS_PIN8_Pos 8 +#define PORT_PORTP_DRIVS_PIN8_Msk (0x01 << PORT_PORTP_DRIVS_PIN8_Pos) +#define PORT_PORTP_DRIVS_PIN9_Pos 9 +#define PORT_PORTP_DRIVS_PIN9_Msk (0x01 << PORT_PORTP_DRIVS_PIN9_Pos) +#define PORT_PORTP_DRIVS_PIN10_Pos 10 +#define PORT_PORTP_DRIVS_PIN10_Msk (0x01 << PORT_PORTP_DRIVS_PIN10_Pos) +#define PORT_PORTP_DRIVS_PIN11_Pos 11 +#define PORT_PORTP_DRIVS_PIN11_Msk (0x01 << PORT_PORTP_DRIVS_PIN11_Pos) +#define PORT_PORTP_DRIVS_PIN12_Pos 12 +#define PORT_PORTP_DRIVS_PIN12_Msk (0x01 << PORT_PORTP_DRIVS_PIN12_Pos) +#define PORT_PORTP_DRIVS_PIN13_Pos 13 +#define PORT_PORTP_DRIVS_PIN13_Msk (0x01 << PORT_PORTP_DRIVS_PIN13_Pos) +#define PORT_PORTP_DRIVS_PIN14_Pos 14 +#define PORT_PORTP_DRIVS_PIN14_Msk (0x01 << PORT_PORTP_DRIVS_PIN14_Pos) +#define PORT_PORTP_DRIVS_PIN15_Pos 15 +#define PORT_PORTP_DRIVS_PIN15_Msk (0x01 << PORT_PORTP_DRIVS_PIN15_Pos) +#define PORT_PORTP_DRIVS_PIN16_Pos 16 +#define PORT_PORTP_DRIVS_PIN16_Msk (0x01 << PORT_PORTP_DRIVS_PIN16_Pos) +#define PORT_PORTP_DRIVS_PIN17_Pos 17 +#define PORT_PORTP_DRIVS_PIN17_Msk (0x01 << PORT_PORTP_DRIVS_PIN17_Pos) +#define PORT_PORTP_DRIVS_PIN18_Pos 18 +#define PORT_PORTP_DRIVS_PIN18_Msk (0x01 << PORT_PORTP_DRIVS_PIN18_Pos) +#define PORT_PORTP_DRIVS_PIN19_Pos 19 +#define PORT_PORTP_DRIVS_PIN19_Msk (0x01 << PORT_PORTP_DRIVS_PIN19_Pos) +#define PORT_PORTP_DRIVS_PIN20_Pos 20 +#define PORT_PORTP_DRIVS_PIN20_Msk (0x01 << PORT_PORTP_DRIVS_PIN20_Pos) +#define PORT_PORTP_DRIVS_PIN21_Pos 21 +#define PORT_PORTP_DRIVS_PIN21_Msk (0x01 << PORT_PORTP_DRIVS_PIN21_Pos) +#define PORT_PORTP_DRIVS_PIN22_Pos 22 +#define PORT_PORTP_DRIVS_PIN22_Msk (0x01 << PORT_PORTP_DRIVS_PIN22_Pos) +#define PORT_PORTP_DRIVS_PIN23_Pos 23 +#define PORT_PORTP_DRIVS_PIN23_Msk (0x01 << PORT_PORTP_DRIVS_PIN23_Pos) + +#define PORT_PORTA_INEN_PIN0_Pos 0 +#define PORT_PORTA_INEN_PIN0_Msk (0x01 << PORT_PORTA_INEN_PIN0_Pos) +#define PORT_PORTA_INEN_PIN1_Pos 1 +#define PORT_PORTA_INEN_PIN1_Msk (0x01 << PORT_PORTA_INEN_PIN1_Pos) +#define PORT_PORTA_INEN_PIN2_Pos 2 +#define PORT_PORTA_INEN_PIN2_Msk (0x01 << PORT_PORTA_INEN_PIN2_Pos) +#define PORT_PORTA_INEN_PIN3_Pos 3 +#define PORT_PORTA_INEN_PIN3_Msk (0x01 << PORT_PORTA_INEN_PIN3_Pos) +#define PORT_PORTA_INEN_PIN4_Pos 4 +#define PORT_PORTA_INEN_PIN4_Msk (0x01 << PORT_PORTA_INEN_PIN4_Pos) +#define PORT_PORTA_INEN_PIN5_Pos 5 +#define PORT_PORTA_INEN_PIN5_Msk (0x01 << PORT_PORTA_INEN_PIN5_Pos) +#define PORT_PORTA_INEN_PIN6_Pos 6 +#define PORT_PORTA_INEN_PIN6_Msk (0x01 << PORT_PORTA_INEN_PIN6_Pos) +#define PORT_PORTA_INEN_PIN7_Pos 7 +#define PORT_PORTA_INEN_PIN7_Msk (0x01 << PORT_PORTA_INEN_PIN7_Pos) +#define PORT_PORTA_INEN_PIN8_Pos 8 +#define PORT_PORTA_INEN_PIN8_Msk (0x01 << PORT_PORTA_INEN_PIN8_Pos) +#define PORT_PORTA_INEN_PIN9_Pos 9 +#define PORT_PORTA_INEN_PIN9_Msk (0x01 << PORT_PORTA_INEN_PIN9_Pos) +#define PORT_PORTA_INEN_PIN10_Pos 10 +#define PORT_PORTA_INEN_PIN10_Msk (0x01 << PORT_PORTA_INEN_PIN10_Pos) +#define PORT_PORTA_INEN_PIN11_Pos 11 +#define PORT_PORTA_INEN_PIN11_Msk (0x01 << PORT_PORTA_INEN_PIN11_Pos) +#define PORT_PORTA_INEN_PIN12_Pos 12 +#define PORT_PORTA_INEN_PIN12_Msk (0x01 << PORT_PORTA_INEN_PIN12_Pos) +#define PORT_PORTA_INEN_PIN13_Pos 13 +#define PORT_PORTA_INEN_PIN13_Msk (0x01 << PORT_PORTA_INEN_PIN13_Pos) +#define PORT_PORTA_INEN_PIN14_Pos 14 +#define PORT_PORTA_INEN_PIN14_Msk (0x01 << PORT_PORTA_INEN_PIN14_Pos) +#define PORT_PORTA_INEN_PIN15_Pos 15 +#define PORT_PORTA_INEN_PIN15_Msk (0x01 << PORT_PORTA_INEN_PIN15_Pos) + +#define PORT_PORTB_INEN_PIN0_Pos 0 +#define PORT_PORTB_INEN_PIN0_Msk (0x01 << PORT_PORTB_INEN_PIN0_Pos) +#define PORT_PORTB_INEN_PIN1_Pos 1 +#define PORT_PORTB_INEN_PIN1_Msk (0x01 << PORT_PORTB_INEN_PIN1_Pos) +#define PORT_PORTB_INEN_PIN2_Pos 2 +#define PORT_PORTB_INEN_PIN2_Msk (0x01 << PORT_PORTB_INEN_PIN2_Pos) +#define PORT_PORTB_INEN_PIN3_Pos 3 +#define PORT_PORTB_INEN_PIN3_Msk (0x01 << PORT_PORTB_INEN_PIN3_Pos) +#define PORT_PORTB_INEN_PIN4_Pos 4 +#define PORT_PORTB_INEN_PIN4_Msk (0x01 << PORT_PORTB_INEN_PIN4_Pos) +#define PORT_PORTB_INEN_PIN5_Pos 5 +#define PORT_PORTB_INEN_PIN5_Msk (0x01 << PORT_PORTB_INEN_PIN5_Pos) +#define PORT_PORTB_INEN_PIN6_Pos 6 +#define PORT_PORTB_INEN_PIN6_Msk (0x01 << PORT_PORTB_INEN_PIN6_Pos) +#define PORT_PORTB_INEN_PIN7_Pos 7 +#define PORT_PORTB_INEN_PIN7_Msk (0x01 << PORT_PORTB_INEN_PIN7_Pos) +#define PORT_PORTB_INEN_PIN8_Pos 8 +#define PORT_PORTB_INEN_PIN8_Msk (0x01 << PORT_PORTB_INEN_PIN8_Pos) +#define PORT_PORTB_INEN_PIN9_Pos 9 +#define PORT_PORTB_INEN_PIN9_Msk (0x01 << PORT_PORTB_INEN_PIN9_Pos) +#define PORT_PORTB_INEN_PIN10_Pos 10 +#define PORT_PORTB_INEN_PIN10_Msk (0x01 << PORT_PORTB_INEN_PIN10_Pos) +#define PORT_PORTB_INEN_PIN11_Pos 11 +#define PORT_PORTB_INEN_PIN11_Msk (0x01 << PORT_PORTB_INEN_PIN11_Pos) +#define PORT_PORTB_INEN_PIN12_Pos 12 +#define PORT_PORTB_INEN_PIN12_Msk (0x01 << PORT_PORTB_INEN_PIN12_Pos) +#define PORT_PORTB_INEN_PIN13_Pos 13 +#define PORT_PORTB_INEN_PIN13_Msk (0x01 << PORT_PORTB_INEN_PIN13_Pos) +#define PORT_PORTB_INEN_PIN14_Pos 14 +#define PORT_PORTB_INEN_PIN14_Msk (0x01 << PORT_PORTB_INEN_PIN14_Pos) +#define PORT_PORTB_INEN_PIN15_Pos 15 +#define PORT_PORTB_INEN_PIN15_Msk (0x01 << PORT_PORTB_INEN_PIN15_Pos) + +#define PORT_PORTC_INEN_PIN0_Pos 0 +#define PORT_PORTC_INEN_PIN0_Msk (0x01 << PORT_PORTC_INEN_PIN0_Pos) +#define PORT_PORTC_INEN_PIN1_Pos 1 +#define PORT_PORTC_INEN_PIN1_Msk (0x01 << PORT_PORTC_INEN_PIN1_Pos) +#define PORT_PORTC_INEN_PIN2_Pos 2 +#define PORT_PORTC_INEN_PIN2_Msk (0x01 << PORT_PORTC_INEN_PIN2_Pos) +#define PORT_PORTC_INEN_PIN3_Pos 3 +#define PORT_PORTC_INEN_PIN3_Msk (0x01 << PORT_PORTC_INEN_PIN3_Pos) +#define PORT_PORTC_INEN_PIN4_Pos 4 +#define PORT_PORTC_INEN_PIN4_Msk (0x01 << PORT_PORTC_INEN_PIN4_Pos) +#define PORT_PORTC_INEN_PIN5_Pos 5 +#define PORT_PORTC_INEN_PIN5_Msk (0x01 << PORT_PORTC_INEN_PIN5_Pos) +#define PORT_PORTC_INEN_PIN6_Pos 6 +#define PORT_PORTC_INEN_PIN6_Msk (0x01 << PORT_PORTC_INEN_PIN6_Pos) +#define PORT_PORTC_INEN_PIN7_Pos 7 +#define PORT_PORTC_INEN_PIN7_Msk (0x01 << PORT_PORTC_INEN_PIN7_Pos) +#define PORT_PORTC_INEN_PIN8_Pos 8 +#define PORT_PORTC_INEN_PIN8_Msk (0x01 << PORT_PORTC_INEN_PIN8_Pos) +#define PORT_PORTC_INEN_PIN9_Pos 9 +#define PORT_PORTC_INEN_PIN9_Msk (0x01 << PORT_PORTC_INEN_PIN9_Pos) +#define PORT_PORTC_INEN_PIN10_Pos 10 +#define PORT_PORTC_INEN_PIN10_Msk (0x01 << PORT_PORTC_INEN_PIN10_Pos) +#define PORT_PORTC_INEN_PIN11_Pos 11 +#define PORT_PORTC_INEN_PIN11_Msk (0x01 << PORT_PORTC_INEN_PIN11_Pos) +#define PORT_PORTC_INEN_PIN12_Pos 12 +#define PORT_PORTC_INEN_PIN12_Msk (0x01 << PORT_PORTC_INEN_PIN12_Pos) +#define PORT_PORTC_INEN_PIN13_Pos 13 +#define PORT_PORTC_INEN_PIN13_Msk (0x01 << PORT_PORTC_INEN_PIN13_Pos) +#define PORT_PORTC_INEN_PIN14_Pos 14 +#define PORT_PORTC_INEN_PIN14_Msk (0x01 << PORT_PORTC_INEN_PIN14_Pos) +#define PORT_PORTC_INEN_PIN15_Pos 15 +#define PORT_PORTC_INEN_PIN15_Msk (0x01 << PORT_PORTC_INEN_PIN15_Pos) + +#define PORT_PORTM_INEN_PIN0_Pos 0 +#define PORT_PORTM_INEN_PIN0_Msk (0x01 << PORT_PORTM_INEN_PIN0_Pos) +#define PORT_PORTM_INEN_PIN1_Pos 1 +#define PORT_PORTM_INEN_PIN1_Msk (0x01 << PORT_PORTM_INEN_PIN1_Pos) +#define PORT_PORTM_INEN_PIN2_Pos 2 +#define PORT_PORTM_INEN_PIN2_Msk (0x01 << PORT_PORTM_INEN_PIN2_Pos) +#define PORT_PORTM_INEN_PIN3_Pos 3 +#define PORT_PORTM_INEN_PIN3_Msk (0x01 << PORT_PORTM_INEN_PIN3_Pos) +#define PORT_PORTM_INEN_PIN4_Pos 4 +#define PORT_PORTM_INEN_PIN4_Msk (0x01 << PORT_PORTM_INEN_PIN4_Pos) +#define PORT_PORTM_INEN_PIN5_Pos 5 +#define PORT_PORTM_INEN_PIN5_Msk (0x01 << PORT_PORTM_INEN_PIN5_Pos) +#define PORT_PORTM_INEN_PIN6_Pos 6 +#define PORT_PORTM_INEN_PIN6_Msk (0x01 << PORT_PORTM_INEN_PIN6_Pos) +#define PORT_PORTM_INEN_PIN7_Pos 7 +#define PORT_PORTM_INEN_PIN7_Msk (0x01 << PORT_PORTM_INEN_PIN7_Pos) +#define PORT_PORTM_INEN_PIN8_Pos 8 +#define PORT_PORTM_INEN_PIN8_Msk (0x01 << PORT_PORTM_INEN_PIN8_Pos) +#define PORT_PORTM_INEN_PIN9_Pos 9 +#define PORT_PORTM_INEN_PIN9_Msk (0x01 << PORT_PORTM_INEN_PIN9_Pos) +#define PORT_PORTM_INEN_PIN10_Pos 10 +#define PORT_PORTM_INEN_PIN10_Msk (0x01 << PORT_PORTM_INEN_PIN10_Pos) +#define PORT_PORTM_INEN_PIN11_Pos 11 +#define PORT_PORTM_INEN_PIN11_Msk (0x01 << PORT_PORTM_INEN_PIN11_Pos) +#define PORT_PORTM_INEN_PIN12_Pos 12 +#define PORT_PORTM_INEN_PIN12_Msk (0x01 << PORT_PORTM_INEN_PIN12_Pos) +#define PORT_PORTM_INEN_PIN13_Pos 13 +#define PORT_PORTM_INEN_PIN13_Msk (0x01 << PORT_PORTM_INEN_PIN13_Pos) +#define PORT_PORTM_INEN_PIN14_Pos 14 +#define PORT_PORTM_INEN_PIN14_Msk (0x01 << PORT_PORTM_INEN_PIN14_Pos) +#define PORT_PORTM_INEN_PIN15_Pos 15 +#define PORT_PORTM_INEN_PIN15_Msk (0x01 << PORT_PORTM_INEN_PIN15_Pos) +#define PORT_PORTM_INEN_PIN16_Pos 16 +#define PORT_PORTM_INEN_PIN16_Msk (0x01 << PORT_PORTM_INEN_PIN16_Pos) +#define PORT_PORTM_INEN_PIN17_Pos 17 +#define PORT_PORTM_INEN_PIN17_Msk (0x01 << PORT_PORTM_INEN_PIN17_Pos) +#define PORT_PORTM_INEN_PIN18_Pos 18 +#define PORT_PORTM_INEN_PIN18_Msk (0x01 << PORT_PORTM_INEN_PIN18_Pos) +#define PORT_PORTM_INEN_PIN19_Pos 19 +#define PORT_PORTM_INEN_PIN19_Msk (0x01 << PORT_PORTM_INEN_PIN19_Pos) +#define PORT_PORTM_INEN_PIN20_Pos 20 +#define PORT_PORTM_INEN_PIN20_Msk (0x01 << PORT_PORTM_INEN_PIN20_Pos) +#define PORT_PORTM_INEN_PIN21_Pos 21 +#define PORT_PORTM_INEN_PIN21_Msk (0x01 << PORT_PORTM_INEN_PIN21_Pos) +#define PORT_PORTM_INEN_PIN22_Pos 22 +#define PORT_PORTM_INEN_PIN22_Msk (0x01 << PORT_PORTM_INEN_PIN22_Pos) +#define PORT_PORTM_INEN_PIN23_Pos 23 +#define PORT_PORTM_INEN_PIN23_Msk (0x01 << PORT_PORTM_INEN_PIN23_Pos) + +#define PORT_PORTN_INEN_PIN0_Pos 0 +#define PORT_PORTN_INEN_PIN0_Msk (0x01 << PORT_PORTN_INEN_PIN0_Pos) +#define PORT_PORTN_INEN_PIN1_Pos 1 +#define PORT_PORTN_INEN_PIN1_Msk (0x01 << PORT_PORTN_INEN_PIN1_Pos) +#define PORT_PORTN_INEN_PIN2_Pos 2 +#define PORT_PORTN_INEN_PIN2_Msk (0x01 << PORT_PORTN_INEN_PIN2_Pos) +#define PORT_PORTN_INEN_PIN3_Pos 3 +#define PORT_PORTN_INEN_PIN3_Msk (0x01 << PORT_PORTN_INEN_PIN3_Pos) +#define PORT_PORTN_INEN_PIN4_Pos 4 +#define PORT_PORTN_INEN_PIN4_Msk (0x01 << PORT_PORTN_INEN_PIN4_Pos) +#define PORT_PORTN_INEN_PIN5_Pos 5 +#define PORT_PORTN_INEN_PIN5_Msk (0x01 << PORT_PORTN_INEN_PIN5_Pos) +#define PORT_PORTN_INEN_PIN6_Pos 6 +#define PORT_PORTN_INEN_PIN6_Msk (0x01 << PORT_PORTN_INEN_PIN6_Pos) +#define PORT_PORTN_INEN_PIN7_Pos 7 +#define PORT_PORTN_INEN_PIN7_Msk (0x01 << PORT_PORTN_INEN_PIN7_Pos) +#define PORT_PORTN_INEN_PIN8_Pos 8 +#define PORT_PORTN_INEN_PIN8_Msk (0x01 << PORT_PORTN_INEN_PIN8_Pos) +#define PORT_PORTN_INEN_PIN9_Pos 9 +#define PORT_PORTN_INEN_PIN9_Msk (0x01 << PORT_PORTN_INEN_PIN9_Pos) +#define PORT_PORTN_INEN_PIN10_Pos 10 +#define PORT_PORTN_INEN_PIN10_Msk (0x01 << PORT_PORTN_INEN_PIN10_Pos) +#define PORT_PORTN_INEN_PIN11_Pos 11 +#define PORT_PORTN_INEN_PIN11_Msk (0x01 << PORT_PORTN_INEN_PIN11_Pos) +#define PORT_PORTN_INEN_PIN12_Pos 12 +#define PORT_PORTN_INEN_PIN12_Msk (0x01 << PORT_PORTN_INEN_PIN12_Pos) +#define PORT_PORTN_INEN_PIN13_Pos 13 +#define PORT_PORTN_INEN_PIN13_Msk (0x01 << PORT_PORTN_INEN_PIN13_Pos) +#define PORT_PORTN_INEN_PIN14_Pos 14 +#define PORT_PORTN_INEN_PIN14_Msk (0x01 << PORT_PORTN_INEN_PIN14_Pos) +#define PORT_PORTN_INEN_PIN15_Pos 15 +#define PORT_PORTN_INEN_PIN15_Msk (0x01 << PORT_PORTN_INEN_PIN15_Pos) +#define PORT_PORTN_INEN_PIN16_Pos 16 +#define PORT_PORTN_INEN_PIN16_Msk (0x01 << PORT_PORTN_INEN_PIN16_Pos) +#define PORT_PORTN_INEN_PIN17_Pos 17 +#define PORT_PORTN_INEN_PIN17_Msk (0x01 << PORT_PORTN_INEN_PIN17_Pos) +#define PORT_PORTN_INEN_PIN18_Pos 18 +#define PORT_PORTN_INEN_PIN18_Msk (0x01 << PORT_PORTN_INEN_PIN18_Pos) +#define PORT_PORTN_INEN_PIN19_Pos 19 +#define PORT_PORTN_INEN_PIN19_Msk (0x01 << PORT_PORTN_INEN_PIN19_Pos) +#define PORT_PORTN_INEN_PIN20_Pos 20 +#define PORT_PORTN_INEN_PIN20_Msk (0x01 << PORT_PORTN_INEN_PIN20_Pos) +#define PORT_PORTN_INEN_PIN21_Pos 21 +#define PORT_PORTN_INEN_PIN21_Msk (0x01 << PORT_PORTN_INEN_PIN21_Pos) +#define PORT_PORTN_INEN_PIN22_Pos 22 +#define PORT_PORTN_INEN_PIN22_Msk (0x01 << PORT_PORTN_INEN_PIN22_Pos) +#define PORT_PORTN_INEN_PIN23_Pos 23 +#define PORT_PORTN_INEN_PIN23_Msk (0x01 << PORT_PORTN_INEN_PIN23_Pos) + +#define PORT_PORTP_INEN_PIN0_Pos 0 +#define PORT_PORTP_INEN_PIN0_Msk (0x01 << PORT_PORTP_INEN_PIN0_Pos) +#define PORT_PORTP_INEN_PIN1_Pos 1 +#define PORT_PORTP_INEN_PIN1_Msk (0x01 << PORT_PORTP_INEN_PIN1_Pos) +#define PORT_PORTP_INEN_PIN2_Pos 2 +#define PORT_PORTP_INEN_PIN2_Msk (0x01 << PORT_PORTP_INEN_PIN2_Pos) +#define PORT_PORTP_INEN_PIN3_Pos 3 +#define PORT_PORTP_INEN_PIN3_Msk (0x01 << PORT_PORTP_INEN_PIN3_Pos) +#define PORT_PORTP_INEN_PIN4_Pos 4 +#define PORT_PORTP_INEN_PIN4_Msk (0x01 << PORT_PORTP_INEN_PIN4_Pos) +#define PORT_PORTP_INEN_PIN5_Pos 5 +#define PORT_PORTP_INEN_PIN5_Msk (0x01 << PORT_PORTP_INEN_PIN5_Pos) +#define PORT_PORTP_INEN_PIN6_Pos 6 +#define PORT_PORTP_INEN_PIN6_Msk (0x01 << PORT_PORTP_INEN_PIN6_Pos) +#define PORT_PORTP_INEN_PIN7_Pos 7 +#define PORT_PORTP_INEN_PIN7_Msk (0x01 << PORT_PORTP_INEN_PIN7_Pos) +#define PORT_PORTP_INEN_PIN8_Pos 8 +#define PORT_PORTP_INEN_PIN8_Msk (0x01 << PORT_PORTP_INEN_PIN8_Pos) +#define PORT_PORTP_INEN_PIN9_Pos 9 +#define PORT_PORTP_INEN_PIN9_Msk (0x01 << PORT_PORTP_INEN_PIN9_Pos) +#define PORT_PORTP_INEN_PIN10_Pos 10 +#define PORT_PORTP_INEN_PIN10_Msk (0x01 << PORT_PORTP_INEN_PIN10_Pos) +#define PORT_PORTP_INEN_PIN11_Pos 11 +#define PORT_PORTP_INEN_PIN11_Msk (0x01 << PORT_PORTP_INEN_PIN11_Pos) +#define PORT_PORTP_INEN_PIN12_Pos 12 +#define PORT_PORTP_INEN_PIN12_Msk (0x01 << PORT_PORTP_INEN_PIN12_Pos) +#define PORT_PORTP_INEN_PIN13_Pos 13 +#define PORT_PORTP_INEN_PIN13_Msk (0x01 << PORT_PORTP_INEN_PIN13_Pos) +#define PORT_PORTP_INEN_PIN14_Pos 14 +#define PORT_PORTP_INEN_PIN14_Msk (0x01 << PORT_PORTP_INEN_PIN14_Pos) +#define PORT_PORTP_INEN_PIN15_Pos 15 +#define PORT_PORTP_INEN_PIN15_Msk (0x01 << PORT_PORTP_INEN_PIN15_Pos) +#define PORT_PORTP_INEN_PIN16_Pos 16 +#define PORT_PORTP_INEN_PIN16_Msk (0x01 << PORT_PORTP_INEN_PIN16_Pos) +#define PORT_PORTP_INEN_PIN17_Pos 17 +#define PORT_PORTP_INEN_PIN17_Msk (0x01 << PORT_PORTP_INEN_PIN17_Pos) +#define PORT_PORTP_INEN_PIN18_Pos 18 +#define PORT_PORTP_INEN_PIN18_Msk (0x01 << PORT_PORTP_INEN_PIN18_Pos) +#define PORT_PORTP_INEN_PIN19_Pos 19 +#define PORT_PORTP_INEN_PIN19_Msk (0x01 << PORT_PORTP_INEN_PIN19_Pos) +#define PORT_PORTP_INEN_PIN20_Pos 20 +#define PORT_PORTP_INEN_PIN20_Msk (0x01 << PORT_PORTP_INEN_PIN20_Pos) +#define PORT_PORTP_INEN_PIN21_Pos 21 +#define PORT_PORTP_INEN_PIN21_Msk (0x01 << PORT_PORTP_INEN_PIN21_Pos) +#define PORT_PORTP_INEN_PIN22_Pos 22 +#define PORT_PORTP_INEN_PIN22_Msk (0x01 << PORT_PORTP_INEN_PIN22_Pos) +#define PORT_PORTP_INEN_PIN23_Pos 23 +#define PORT_PORTP_INEN_PIN23_Msk (0x01 << PORT_PORTP_INEN_PIN23_Pos) + +typedef struct +{ + __IO uint32_t DATA; +#define PIN0 0 +#define PIN1 1 +#define PIN2 2 +#define PIN3 3 +#define PIN4 4 +#define PIN5 5 +#define PIN6 6 +#define PIN7 7 +#define PIN8 8 +#define PIN9 9 +#define PIN10 10 +#define PIN11 11 +#define PIN12 12 +#define PIN13 13 +#define PIN14 14 +#define PIN15 15 +#define PIN16 16 +#define PIN17 17 +#define PIN18 18 +#define PIN19 19 +#define PIN20 20 +#define PIN21 21 +#define PIN22 22 +#define PIN23 23 +#define PIN24 24 + + __IO uint32_t DIR; //0 输入 1 输出 + + __IO uint32_t INTLVLTRG; //Interrupt Level Trigger 1 电平触发中断 0 边沿触发中断 + + __IO uint32_t INTBE; //Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择 + + __IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable 1 上升沿/高电平触发中断 0 下降沿/低电平触发中断 + + __IO uint32_t INTEN; //1 中断使能 0 中断禁止 + + __IO uint32_t INTRAWSTAT; //中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件 0 没有检测到中断触发条件 + + __IO uint32_t INTSTAT; //INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0 + + __IO uint32_t INTCLR; //写1清除中断标志，只对边沿触发中断有用 +} GPIO_TypeDef; + +#define GPIO_DATA_PIN0_Pos 0 +#define GPIO_DATA_PIN0_Msk (0x01 << GPIO_DATA_PIN0_Pos) +#define GPIO_DATA_PIN1_Pos 1 +#define GPIO_DATA_PIN1_Msk (0x01 << GPIO_DATA_PIN1_Pos) +#define GPIO_DATA_PIN2_Pos 2 +#define GPIO_DATA_PIN2_Msk (0x01 << GPIO_DATA_PIN2_Pos) +#define GPIO_DATA_PIN3_Pos 3 +#define GPIO_DATA_PIN3_Msk (0x01 << GPIO_DATA_PIN3_Pos) +#define GPIO_DATA_PIN4_Pos 4 +#define GPIO_DATA_PIN4_Msk (0x01 << GPIO_DATA_PIN4_Pos) +#define GPIO_DATA_PIN5_Pos 5 +#define GPIO_DATA_PIN5_Msk (0x01 << GPIO_DATA_PIN5_Pos) +#define GPIO_DATA_PIN6_Pos 6 +#define GPIO_DATA_PIN6_Msk (0x01 << GPIO_DATA_PIN6_Pos) +#define GPIO_DATA_PIN7_Pos 7 +#define GPIO_DATA_PIN7_Msk (0x01 << GPIO_DATA_PIN7_Pos) +#define GPIO_DATA_PIN8_Pos 8 +#define GPIO_DATA_PIN8_Msk (0x01 << GPIO_DATA_PIN8_Pos) +#define GPIO_DATA_PIN9_Pos 9 +#define GPIO_DATA_PIN9_Msk (0x01 << GPIO_DATA_PIN9_Pos) +#define GPIO_DATA_PIN10_Pos 10 +#define GPIO_DATA_PIN10_Msk (0x01 << GPIO_DATA_PIN10_Pos) +#define GPIO_DATA_PIN11_Pos 11 +#define GPIO_DATA_PIN11_Msk (0x01 << GPIO_DATA_PIN11_Pos) +#define GPIO_DATA_PIN12_Pos 12 +#define GPIO_DATA_PIN12_Msk (0x01 << GPIO_DATA_PIN12_Pos) +#define GPIO_DATA_PIN13_Pos 13 +#define GPIO_DATA_PIN13_Msk (0x01 << GPIO_DATA_PIN13_Pos) +#define GPIO_DATA_PIN14_Pos 14 +#define GPIO_DATA_PIN14_Msk (0x01 << GPIO_DATA_PIN14_Pos) +#define GPIO_DATA_PIN15_Pos 15 +#define GPIO_DATA_PIN15_Msk (0x01 << GPIO_DATA_PIN15_Pos) +#define GPIO_DATA_PIN16_Pos 16 +#define GPIO_DATA_PIN16_Msk (0x01 << GPIO_DATA_PIN16_Pos) +#define GPIO_DATA_PIN17_Pos 17 +#define GPIO_DATA_PIN17_Msk (0x01 << GPIO_DATA_PIN17_Pos) +#define GPIO_DATA_PIN18_Pos 18 +#define GPIO_DATA_PIN18_Msk (0x01 << GPIO_DATA_PIN18_Pos) +#define GPIO_DATA_PIN19_Pos 19 +#define GPIO_DATA_PIN19_Msk (0x01 << GPIO_DATA_PIN19_Pos) +#define GPIO_DATA_PIN20_Pos 20 +#define GPIO_DATA_PIN20_Msk (0x01 << GPIO_DATA_PIN20_Pos) +#define GPIO_DATA_PIN21_Pos 21 +#define GPIO_DATA_PIN21_Msk (0x01 << GPIO_DATA_PIN21_Pos) +#define GPIO_DATA_PIN22_Pos 22 +#define GPIO_DATA_PIN22_Msk (0x01 << GPIO_DATA_PIN22_Pos) +#define GPIO_DATA_PIN23_Pos 23 +#define GPIO_DATA_PIN23_Msk (0x01 << GPIO_DATA_PIN23_Pos) + +#define GPIO_DIR_PIN0_Pos 0 +#define GPIO_DIR_PIN0_Msk (0x01 << GPIO_DIR_PIN0_Pos) +#define GPIO_DIR_PIN1_Pos 1 +#define GPIO_DIR_PIN1_Msk (0x01 << GPIO_DIR_PIN1_Pos) +#define GPIO_DIR_PIN2_Pos 2 +#define GPIO_DIR_PIN2_Msk (0x01 << GPIO_DIR_PIN2_Pos) +#define GPIO_DIR_PIN3_Pos 3 +#define GPIO_DIR_PIN3_Msk (0x01 << GPIO_DIR_PIN3_Pos) +#define GPIO_DIR_PIN4_Pos 4 +#define GPIO_DIR_PIN4_Msk (0x01 << GPIO_DIR_PIN4_Pos) +#define GPIO_DIR_PIN5_Pos 5 +#define GPIO_DIR_PIN5_Msk (0x01 << GPIO_DIR_PIN5_Pos) +#define GPIO_DIR_PIN6_Pos 6 +#define GPIO_DIR_PIN6_Msk (0x01 << GPIO_DIR_PIN6_Pos) +#define GPIO_DIR_PIN7_Pos 7 +#define GPIO_DIR_PIN7_Msk (0x01 << GPIO_DIR_PIN7_Pos) +#define GPIO_DIR_PIN8_Pos 8 +#define GPIO_DIR_PIN8_Msk (0x01 << GPIO_DIR_PIN8_Pos) +#define GPIO_DIR_PIN9_Pos 9 +#define GPIO_DIR_PIN9_Msk (0x01 << GPIO_DIR_PIN9_Pos) +#define GPIO_DIR_PIN10_Pos 10 +#define GPIO_DIR_PIN10_Msk (0x01 << GPIO_DIR_PIN10_Pos) +#define GPIO_DIR_PIN11_Pos 11 +#define GPIO_DIR_PIN11_Msk (0x01 << GPIO_DIR_PIN11_Pos) +#define GPIO_DIR_PIN12_Pos 12 +#define GPIO_DIR_PIN12_Msk (0x01 << GPIO_DIR_PIN12_Pos) +#define GPIO_DIR_PIN13_Pos 13 +#define GPIO_DIR_PIN13_Msk (0x01 << GPIO_DIR_PIN13_Pos) +#define GPIO_DIR_PIN14_Pos 14 +#define GPIO_DIR_PIN14_Msk (0x01 << GPIO_DIR_PIN14_Pos) +#define GPIO_DIR_PIN15_Pos 15 +#define GPIO_DIR_PIN15_Msk (0x01 << GPIO_DIR_PIN15_Pos) +#define GPIO_DIR_PIN16_Pos 16 +#define GPIO_DIR_PIN16_Msk (0x01 << GPIO_DIR_PIN16_Pos) +#define GPIO_DIR_PIN17_Pos 17 +#define GPIO_DIR_PIN17_Msk (0x01 << GPIO_DIR_PIN17_Pos) +#define GPIO_DIR_PIN18_Pos 18 +#define GPIO_DIR_PIN18_Msk (0x01 << GPIO_DIR_PIN18_Pos) +#define GPIO_DIR_PIN19_Pos 19 +#define GPIO_DIR_PIN19_Msk (0x01 << GPIO_DIR_PIN19_Pos) +#define GPIO_DIR_PIN20_Pos 20 +#define GPIO_DIR_PIN20_Msk (0x01 << GPIO_DIR_PIN20_Pos) +#define GPIO_DIR_PIN21_Pos 21 +#define GPIO_DIR_PIN21_Msk (0x01 << GPIO_DIR_PIN21_Pos) +#define GPIO_DIR_PIN22_Pos 22 +#define GPIO_DIR_PIN22_Msk (0x01 << GPIO_DIR_PIN22_Pos) +#define GPIO_DIR_PIN23_Pos 23 +#define GPIO_DIR_PIN23_Msk (0x01 << GPIO_DIR_PIN23_Pos) + +#define GPIO_INTLVLTRG_PIN0_Pos 0 +#define GPIO_INTLVLTRG_PIN0_Msk (0x01 << GPIO_INTLVLTRG_PIN0_Pos) +#define GPIO_INTLVLTRG_PIN1_Pos 1 +#define GPIO_INTLVLTRG_PIN1_Msk (0x01 << GPIO_INTLVLTRG_PIN1_Pos) +#define GPIO_INTLVLTRG_PIN2_Pos 2 +#define GPIO_INTLVLTRG_PIN2_Msk (0x01 << GPIO_INTLVLTRG_PIN2_Pos) +#define GPIO_INTLVLTRG_PIN3_Pos 3 +#define GPIO_INTLVLTRG_PIN3_Msk (0x01 << GPIO_INTLVLTRG_PIN3_Pos) +#define GPIO_INTLVLTRG_PIN4_Pos 4 +#define GPIO_INTLVLTRG_PIN4_Msk (0x01 << GPIO_INTLVLTRG_PIN4_Pos) +#define GPIO_INTLVLTRG_PIN5_Pos 5 +#define GPIO_INTLVLTRG_PIN5_Msk (0x01 << GPIO_INTLVLTRG_PIN5_Pos) +#define GPIO_INTLVLTRG_PIN6_Pos 6 +#define GPIO_INTLVLTRG_PIN6_Msk (0x01 << GPIO_INTLVLTRG_PIN6_Pos) +#define GPIO_INTLVLTRG_PIN7_Pos 7 +#define GPIO_INTLVLTRG_PIN7_Msk (0x01 << GPIO_INTLVLTRG_PIN7_Pos) +#define GPIO_INTLVLTRG_PIN8_Pos 8 +#define GPIO_INTLVLTRG_PIN8_Msk (0x01 << GPIO_INTLVLTRG_PIN8_Pos) +#define GPIO_INTLVLTRG_PIN9_Pos 9 +#define GPIO_INTLVLTRG_PIN9_Msk (0x01 << GPIO_INTLVLTRG_PIN9_Pos) +#define GPIO_INTLVLTRG_PIN10_Pos 10 +#define GPIO_INTLVLTRG_PIN10_Msk (0x01 << GPIO_INTLVLTRG_PIN10_Pos) +#define GPIO_INTLVLTRG_PIN11_Pos 11 +#define GPIO_INTLVLTRG_PIN11_Msk (0x01 << GPIO_INTLVLTRG_PIN11_Pos) +#define GPIO_INTLVLTRG_PIN12_Pos 12 +#define GPIO_INTLVLTRG_PIN12_Msk (0x01 << GPIO_INTLVLTRG_PIN12_Pos) +#define GPIO_INTLVLTRG_PIN13_Pos 13 +#define GPIO_INTLVLTRG_PIN13_Msk (0x01 << GPIO_INTLVLTRG_PIN13_Pos) +#define GPIO_INTLVLTRG_PIN14_Pos 14 +#define GPIO_INTLVLTRG_PIN14_Msk (0x01 << GPIO_INTLVLTRG_PIN14_Pos) +#define GPIO_INTLVLTRG_PIN15_Pos 15 +#define GPIO_INTLVLTRG_PIN15_Msk (0x01 << GPIO_INTLVLTRG_PIN15_Pos) +#define GPIO_INTLVLTRG_PIN16_Pos 16 +#define GPIO_INTLVLTRG_PIN16_Msk (0x01 << GPIO_INTLVLTRG_PIN16_Pos) +#define GPIO_INTLVLTRG_PIN17_Pos 17 +#define GPIO_INTLVLTRG_PIN17_Msk (0x01 << GPIO_INTLVLTRG_PIN17_Pos) +#define GPIO_INTLVLTRG_PIN18_Pos 18 +#define GPIO_INTLVLTRG_PIN18_Msk (0x01 << GPIO_INTLVLTRG_PIN18_Pos) +#define GPIO_INTLVLTRG_PIN19_Pos 19 +#define GPIO_INTLVLTRG_PIN19_Msk (0x01 << GPIO_INTLVLTRG_PIN19_Pos) +#define GPIO_INTLVLTRG_PIN20_Pos 20 +#define GPIO_INTLVLTRG_PIN20_Msk (0x01 << GPIO_INTLVLTRG_PIN20_Pos) +#define GPIO_INTLVLTRG_PIN21_Pos 21 +#define GPIO_INTLVLTRG_PIN21_Msk (0x01 << GPIO_INTLVLTRG_PIN21_Pos) +#define GPIO_INTLVLTRG_PIN22_Pos 22 +#define GPIO_INTLVLTRG_PIN22_Msk (0x01 << GPIO_INTLVLTRG_PIN22_Pos) +#define GPIO_INTLVLTRG_PIN23_Pos 23 +#define GPIO_INTLVLTRG_PIN23_Msk (0x01 << GPIO_INTLVLTRG_PIN23_Pos) + +#define GPIO_INTBE_PIN0_Pos 0 +#define GPIO_INTBE_PIN0_Msk (0x01 << GPIO_INTBE_PIN0_Pos) +#define GPIO_INTBE_PIN1_Pos 1 +#define GPIO_INTBE_PIN1_Msk (0x01 << GPIO_INTBE_PIN1_Pos) +#define GPIO_INTBE_PIN2_Pos 2 +#define GPIO_INTBE_PIN2_Msk (0x01 << GPIO_INTBE_PIN2_Pos) +#define GPIO_INTBE_PIN3_Pos 3 +#define GPIO_INTBE_PIN3_Msk (0x01 << GPIO_INTBE_PIN3_Pos) +#define GPIO_INTBE_PIN4_Pos 4 +#define GPIO_INTBE_PIN4_Msk (0x01 << GPIO_INTBE_PIN4_Pos) +#define GPIO_INTBE_PIN5_Pos 5 +#define GPIO_INTBE_PIN5_Msk (0x01 << GPIO_INTBE_PIN5_Pos) +#define GPIO_INTBE_PIN6_Pos 6 +#define GPIO_INTBE_PIN6_Msk (0x01 << GPIO_INTBE_PIN6_Pos) +#define GPIO_INTBE_PIN7_Pos 7 +#define GPIO_INTBE_PIN7_Msk (0x01 << GPIO_INTBE_PIN7_Pos) +#define GPIO_INTBE_PIN8_Pos 8 +#define GPIO_INTBE_PIN8_Msk (0x01 << GPIO_INTBE_PIN8_Pos) +#define GPIO_INTBE_PIN9_Pos 9 +#define GPIO_INTBE_PIN9_Msk (0x01 << GPIO_INTBE_PIN9_Pos) +#define GPIO_INTBE_PIN10_Pos 10 +#define GPIO_INTBE_PIN10_Msk (0x01 << GPIO_INTBE_PIN10_Pos) +#define GPIO_INTBE_PIN11_Pos 11 +#define GPIO_INTBE_PIN11_Msk (0x01 << GPIO_INTBE_PIN11_Pos) +#define GPIO_INTBE_PIN12_Pos 12 +#define GPIO_INTBE_PIN12_Msk (0x01 << GPIO_INTBE_PIN12_Pos) +#define GPIO_INTBE_PIN13_Pos 13 +#define GPIO_INTBE_PIN13_Msk (0x01 << GPIO_INTBE_PIN13_Pos) +#define GPIO_INTBE_PIN14_Pos 14 +#define GPIO_INTBE_PIN14_Msk (0x01 << GPIO_INTBE_PIN14_Pos) +#define GPIO_INTBE_PIN15_Pos 15 +#define GPIO_INTBE_PIN15_Msk (0x01 << GPIO_INTBE_PIN15_Pos) +#define GPIO_INTBE_PIN16_Pos 16 +#define GPIO_INTBE_PIN16_Msk (0x01 << GPIO_INTBE_PIN16_Pos) +#define GPIO_INTBE_PIN17_Pos 17 +#define GPIO_INTBE_PIN17_Msk (0x01 << GPIO_INTBE_PIN17_Pos) +#define GPIO_INTBE_PIN18_Pos 18 +#define GPIO_INTBE_PIN18_Msk (0x01 << GPIO_INTBE_PIN18_Pos) +#define GPIO_INTBE_PIN19_Pos 19 +#define GPIO_INTBE_PIN19_Msk (0x01 << GPIO_INTBE_PIN19_Pos) +#define GPIO_INTBE_PIN20_Pos 20 +#define GPIO_INTBE_PIN20_Msk (0x01 << GPIO_INTBE_PIN20_Pos) +#define GPIO_INTBE_PIN21_Pos 21 +#define GPIO_INTBE_PIN21_Msk (0x01 << GPIO_INTBE_PIN21_Pos) +#define GPIO_INTBE_PIN22_Pos 22 +#define GPIO_INTBE_PIN22_Msk (0x01 << GPIO_INTBE_PIN22_Pos) +#define GPIO_INTBE_PIN23_Pos 23 +#define GPIO_INTBE_PIN23_Msk (0x01 << GPIO_INTBE_PIN23_Pos) + +#define GPIO_INTRISEEN_PIN0_Pos 0 +#define GPIO_INTRISEEN_PIN0_Msk (0x01 << GPIO_INTRISEEN_PIN0_Pos) +#define GPIO_INTRISEEN_PIN1_Pos 1 +#define GPIO_INTRISEEN_PIN1_Msk (0x01 << GPIO_INTRISEEN_PIN1_Pos) +#define GPIO_INTRISEEN_PIN2_Pos 2 +#define GPIO_INTRISEEN_PIN2_Msk (0x01 << GPIO_INTRISEEN_PIN2_Pos) +#define GPIO_INTRISEEN_PIN3_Pos 3 +#define GPIO_INTRISEEN_PIN3_Msk (0x01 << GPIO_INTRISEEN_PIN3_Pos) +#define GPIO_INTRISEEN_PIN4_Pos 4 +#define GPIO_INTRISEEN_PIN4_Msk (0x01 << GPIO_INTRISEEN_PIN4_Pos) +#define GPIO_INTRISEEN_PIN5_Pos 5 +#define GPIO_INTRISEEN_PIN5_Msk (0x01 << GPIO_INTRISEEN_PIN5_Pos) +#define GPIO_INTRISEEN_PIN6_Pos 6 +#define GPIO_INTRISEEN_PIN6_Msk (0x01 << GPIO_INTRISEEN_PIN6_Pos) +#define GPIO_INTRISEEN_PIN7_Pos 7 +#define GPIO_INTRISEEN_PIN7_Msk (0x01 << GPIO_INTRISEEN_PIN7_Pos) +#define GPIO_INTRISEEN_PIN8_Pos 8 +#define GPIO_INTRISEEN_PIN8_Msk (0x01 << GPIO_INTRISEEN_PIN8_Pos) +#define GPIO_INTRISEEN_PIN9_Pos 9 +#define GPIO_INTRISEEN_PIN9_Msk (0x01 << GPIO_INTRISEEN_PIN9_Pos) +#define GPIO_INTRISEEN_PIN10_Pos 10 +#define GPIO_INTRISEEN_PIN10_Msk (0x01 << GPIO_INTRISEEN_PIN10_Pos) +#define GPIO_INTRISEEN_PIN11_Pos 11 +#define GPIO_INTRISEEN_PIN11_Msk (0x01 << GPIO_INTRISEEN_PIN11_Pos) +#define GPIO_INTRISEEN_PIN12_Pos 12 +#define GPIO_INTRISEEN_PIN12_Msk (0x01 << GPIO_INTRISEEN_PIN12_Pos) +#define GPIO_INTRISEEN_PIN13_Pos 13 +#define GPIO_INTRISEEN_PIN13_Msk (0x01 << GPIO_INTRISEEN_PIN13_Pos) +#define GPIO_INTRISEEN_PIN14_Pos 14 +#define GPIO_INTRISEEN_PIN14_Msk (0x01 << GPIO_INTRISEEN_PIN14_Pos) +#define GPIO_INTRISEEN_PIN15_Pos 15 +#define GPIO_INTRISEEN_PIN15_Msk (0x01 << GPIO_INTRISEEN_PIN15_Pos) +#define GPIO_INTRISEEN_PIN16_Pos 16 +#define GPIO_INTRISEEN_PIN16_Msk (0x01 << GPIO_INTRISEEN_PIN16_Pos) +#define GPIO_INTRISEEN_PIN17_Pos 17 +#define GPIO_INTRISEEN_PIN17_Msk (0x01 << GPIO_INTRISEEN_PIN17_Pos) +#define GPIO_INTRISEEN_PIN18_Pos 18 +#define GPIO_INTRISEEN_PIN18_Msk (0x01 << GPIO_INTRISEEN_PIN18_Pos) +#define GPIO_INTRISEEN_PIN19_Pos 19 +#define GPIO_INTRISEEN_PIN19_Msk (0x01 << GPIO_INTRISEEN_PIN19_Pos) +#define GPIO_INTRISEEN_PIN20_Pos 20 +#define GPIO_INTRISEEN_PIN20_Msk (0x01 << GPIO_INTRISEEN_PIN20_Pos) +#define GPIO_INTRISEEN_PIN21_Pos 21 +#define GPIO_INTRISEEN_PIN21_Msk (0x01 << GPIO_INTRISEEN_PIN21_Pos) +#define GPIO_INTRISEEN_PIN22_Pos 22 +#define GPIO_INTRISEEN_PIN22_Msk (0x01 << GPIO_INTRISEEN_PIN22_Pos) +#define GPIO_INTRISEEN_PIN23_Pos 23 +#define GPIO_INTRISEEN_PIN23_Msk (0x01 << GPIO_INTRISEEN_PIN23_Pos) + +#define GPIO_INTEN_PIN0_Pos 0 +#define GPIO_INTEN_PIN0_Msk (0x01 << GPIO_INTEN_PIN0_Pos) +#define GPIO_INTEN_PIN1_Pos 1 +#define GPIO_INTEN_PIN1_Msk (0x01 << GPIO_INTEN_PIN1_Pos) +#define GPIO_INTEN_PIN2_Pos 2 +#define GPIO_INTEN_PIN2_Msk (0x01 << GPIO_INTEN_PIN2_Pos) +#define GPIO_INTEN_PIN3_Pos 3 +#define GPIO_INTEN_PIN3_Msk (0x01 << GPIO_INTEN_PIN3_Pos) +#define GPIO_INTEN_PIN4_Pos 4 +#define GPIO_INTEN_PIN4_Msk (0x01 << GPIO_INTEN_PIN4_Pos) +#define GPIO_INTEN_PIN5_Pos 5 +#define GPIO_INTEN_PIN5_Msk (0x01 << GPIO_INTEN_PIN5_Pos) +#define GPIO_INTEN_PIN6_Pos 6 +#define GPIO_INTEN_PIN6_Msk (0x01 << GPIO_INTEN_PIN6_Pos) +#define GPIO_INTEN_PIN7_Pos 7 +#define GPIO_INTEN_PIN7_Msk (0x01 << GPIO_INTEN_PIN7_Pos) +#define GPIO_INTEN_PIN8_Pos 8 +#define GPIO_INTEN_PIN8_Msk (0x01 << GPIO_INTEN_PIN8_Pos) +#define GPIO_INTEN_PIN9_Pos 9 +#define GPIO_INTEN_PIN9_Msk (0x01 << GPIO_INTEN_PIN9_Pos) +#define GPIO_INTEN_PIN10_Pos 10 +#define GPIO_INTEN_PIN10_Msk (0x01 << GPIO_INTEN_PIN10_Pos) +#define GPIO_INTEN_PIN11_Pos 11 +#define GPIO_INTEN_PIN11_Msk (0x01 << GPIO_INTEN_PIN11_Pos) +#define GPIO_INTEN_PIN12_Pos 12 +#define GPIO_INTEN_PIN12_Msk (0x01 << GPIO_INTEN_PIN12_Pos) +#define GPIO_INTEN_PIN13_Pos 13 +#define GPIO_INTEN_PIN13_Msk (0x01 << GPIO_INTEN_PIN13_Pos) +#define GPIO_INTEN_PIN14_Pos 14 +#define GPIO_INTEN_PIN14_Msk (0x01 << GPIO_INTEN_PIN14_Pos) +#define GPIO_INTEN_PIN15_Pos 15 +#define GPIO_INTEN_PIN15_Msk (0x01 << GPIO_INTEN_PIN15_Pos) +#define GPIO_INTEN_PIN16_Pos 16 +#define GPIO_INTEN_PIN16_Msk (0x01 << GPIO_INTEN_PIN16_Pos) +#define GPIO_INTEN_PIN17_Pos 17 +#define GPIO_INTEN_PIN17_Msk (0x01 << GPIO_INTEN_PIN17_Pos) +#define GPIO_INTEN_PIN18_Pos 18 +#define GPIO_INTEN_PIN18_Msk (0x01 << GPIO_INTEN_PIN18_Pos) +#define GPIO_INTEN_PIN19_Pos 19 +#define GPIO_INTEN_PIN19_Msk (0x01 << GPIO_INTEN_PIN19_Pos) +#define GPIO_INTEN_PIN20_Pos 20 +#define GPIO_INTEN_PIN20_Msk (0x01 << GPIO_INTEN_PIN20_Pos) +#define GPIO_INTEN_PIN21_Pos 21 +#define GPIO_INTEN_PIN21_Msk (0x01 << GPIO_INTEN_PIN21_Pos) +#define GPIO_INTEN_PIN22_Pos 22 +#define GPIO_INTEN_PIN22_Msk (0x01 << GPIO_INTEN_PIN22_Pos) +#define GPIO_INTEN_PIN23_Pos 23 +#define GPIO_INTEN_PIN23_Msk (0x01 << GPIO_INTEN_PIN23_Pos) + +#define GPIO_INTRAWSTAT_PIN0_Pos 0 +#define GPIO_INTRAWSTAT_PIN0_Msk (0x01 << GPIO_INTRAWSTAT_PIN0_Pos) +#define GPIO_INTRAWSTAT_PIN1_Pos 1 +#define GPIO_INTRAWSTAT_PIN1_Msk (0x01 << GPIO_INTRAWSTAT_PIN1_Pos) +#define GPIO_INTRAWSTAT_PIN2_Pos 2 +#define GPIO_INTRAWSTAT_PIN2_Msk (0x01 << GPIO_INTRAWSTAT_PIN2_Pos) +#define GPIO_INTRAWSTAT_PIN3_Pos 3 +#define GPIO_INTRAWSTAT_PIN3_Msk (0x01 << GPIO_INTRAWSTAT_PIN3_Pos) +#define GPIO_INTRAWSTAT_PIN4_Pos 4 +#define GPIO_INTRAWSTAT_PIN4_Msk (0x01 << GPIO_INTRAWSTAT_PIN4_Pos) +#define GPIO_INTRAWSTAT_PIN5_Pos 5 +#define GPIO_INTRAWSTAT_PIN5_Msk (0x01 << GPIO_INTRAWSTAT_PIN5_Pos) +#define GPIO_INTRAWSTAT_PIN6_Pos 6 +#define GPIO_INTRAWSTAT_PIN6_Msk (0x01 << GPIO_INTRAWSTAT_PIN6_Pos) +#define GPIO_INTRAWSTAT_PIN7_Pos 7 +#define GPIO_INTRAWSTAT_PIN7_Msk (0x01 << GPIO_INTRAWSTAT_PIN7_Pos) +#define GPIO_INTRAWSTAT_PIN8_Pos 8 +#define GPIO_INTRAWSTAT_PIN8_Msk (0x01 << GPIO_INTRAWSTAT_PIN8_Pos) +#define GPIO_INTRAWSTAT_PIN9_Pos 9 +#define GPIO_INTRAWSTAT_PIN9_Msk (0x01 << GPIO_INTRAWSTAT_PIN9_Pos) +#define GPIO_INTRAWSTAT_PIN10_Pos 10 +#define GPIO_INTRAWSTAT_PIN10_Msk (0x01 << GPIO_INTRAWSTAT_PIN10_Pos) +#define GPIO_INTRAWSTAT_PIN11_Pos 11 +#define GPIO_INTRAWSTAT_PIN11_Msk (0x01 << GPIO_INTRAWSTAT_PIN11_Pos) +#define GPIO_INTRAWSTAT_PIN12_Pos 12 +#define GPIO_INTRAWSTAT_PIN12_Msk (0x01 << GPIO_INTRAWSTAT_PIN12_Pos) +#define GPIO_INTRAWSTAT_PIN13_Pos 13 +#define GPIO_INTRAWSTAT_PIN13_Msk (0x01 << GPIO_INTRAWSTAT_PIN13_Pos) +#define GPIO_INTRAWSTAT_PIN14_Pos 14 +#define GPIO_INTRAWSTAT_PIN14_Msk (0x01 << GPIO_INTRAWSTAT_PIN14_Pos) +#define GPIO_INTRAWSTAT_PIN15_Pos 15 +#define GPIO_INTRAWSTAT_PIN15_Msk (0x01 << GPIO_INTRAWSTAT_PIN15_Pos) +#define GPIO_INTRAWSTAT_PIN16_Pos 16 +#define GPIO_INTRAWSTAT_PIN16_Msk (0x01 << GPIO_INTRAWSTAT_PIN16_Pos) +#define GPIO_INTRAWSTAT_PIN17_Pos 17 +#define GPIO_INTRAWSTAT_PIN17_Msk (0x01 << GPIO_INTRAWSTAT_PIN17_Pos) +#define GPIO_INTRAWSTAT_PIN18_Pos 18 +#define GPIO_INTRAWSTAT_PIN18_Msk (0x01 << GPIO_INTRAWSTAT_PIN18_Pos) +#define GPIO_INTRAWSTAT_PIN19_Pos 19 +#define GPIO_INTRAWSTAT_PIN19_Msk (0x01 << GPIO_INTRAWSTAT_PIN19_Pos) +#define GPIO_INTRAWSTAT_PIN20_Pos 20 +#define GPIO_INTRAWSTAT_PIN20_Msk (0x01 << GPIO_INTRAWSTAT_PIN20_Pos) +#define GPIO_INTRAWSTAT_PIN21_Pos 21 +#define GPIO_INTRAWSTAT_PIN21_Msk (0x01 << GPIO_INTRAWSTAT_PIN21_Pos) +#define GPIO_INTRAWSTAT_PIN22_Pos 22 +#define GPIO_INTRAWSTAT_PIN22_Msk (0x01 << GPIO_INTRAWSTAT_PIN22_Pos) +#define GPIO_INTRAWSTAT_PIN23_Pos 23 +#define GPIO_INTRAWSTAT_PIN23_Msk (0x01 << GPIO_INTRAWSTAT_PIN23_Pos) + +#define GPIO_INTSTAT_PIN0_Pos 0 +#define GPIO_INTSTAT_PIN0_Msk (0x01 << GPIO_INTSTAT_PIN0_Pos) +#define GPIO_INTSTAT_PIN1_Pos 1 +#define GPIO_INTSTAT_PIN1_Msk (0x01 << GPIO_INTSTAT_PIN1_Pos) +#define GPIO_INTSTAT_PIN2_Pos 2 +#define GPIO_INTSTAT_PIN2_Msk (0x01 << GPIO_INTSTAT_PIN2_Pos) +#define GPIO_INTSTAT_PIN3_Pos 3 +#define GPIO_INTSTAT_PIN3_Msk (0x01 << GPIO_INTSTAT_PIN3_Pos) +#define GPIO_INTSTAT_PIN4_Pos 4 +#define GPIO_INTSTAT_PIN4_Msk (0x01 << GPIO_INTSTAT_PIN4_Pos) +#define GPIO_INTSTAT_PIN5_Pos 5 +#define GPIO_INTSTAT_PIN5_Msk (0x01 << GPIO_INTSTAT_PIN5_Pos) +#define GPIO_INTSTAT_PIN6_Pos 6 +#define GPIO_INTSTAT_PIN6_Msk (0x01 << GPIO_INTSTAT_PIN6_Pos) +#define GPIO_INTSTAT_PIN7_Pos 7 +#define GPIO_INTSTAT_PIN7_Msk (0x01 << GPIO_INTSTAT_PIN7_Pos) +#define GPIO_INTSTAT_PIN8_Pos 8 +#define GPIO_INTSTAT_PIN8_Msk (0x01 << GPIO_INTSTAT_PIN8_Pos) +#define GPIO_INTSTAT_PIN9_Pos 9 +#define GPIO_INTSTAT_PIN9_Msk (0x01 << GPIO_INTSTAT_PIN9_Pos) +#define GPIO_INTSTAT_PIN10_Pos 10 +#define GPIO_INTSTAT_PIN10_Msk (0x01 << GPIO_INTSTAT_PIN10_Pos) +#define GPIO_INTSTAT_PIN11_Pos 11 +#define GPIO_INTSTAT_PIN11_Msk (0x01 << GPIO_INTSTAT_PIN11_Pos) +#define GPIO_INTSTAT_PIN12_Pos 12 +#define GPIO_INTSTAT_PIN12_Msk (0x01 << GPIO_INTSTAT_PIN12_Pos) +#define GPIO_INTSTAT_PIN13_Pos 13 +#define GPIO_INTSTAT_PIN13_Msk (0x01 << GPIO_INTSTAT_PIN13_Pos) +#define GPIO_INTSTAT_PIN14_Pos 14 +#define GPIO_INTSTAT_PIN14_Msk (0x01 << GPIO_INTSTAT_PIN14_Pos) +#define GPIO_INTSTAT_PIN15_Pos 15 +#define GPIO_INTSTAT_PIN15_Msk (0x01 << GPIO_INTSTAT_PIN15_Pos) +#define GPIO_INTSTAT_PIN16_Pos 16 +#define GPIO_INTSTAT_PIN16_Msk (0x01 << GPIO_INTSTAT_PIN16_Pos) +#define GPIO_INTSTAT_PIN17_Pos 17 +#define GPIO_INTSTAT_PIN17_Msk (0x01 << GPIO_INTSTAT_PIN17_Pos) +#define GPIO_INTSTAT_PIN18_Pos 18 +#define GPIO_INTSTAT_PIN18_Msk (0x01 << GPIO_INTSTAT_PIN18_Pos) +#define GPIO_INTSTAT_PIN19_Pos 19 +#define GPIO_INTSTAT_PIN19_Msk (0x01 << GPIO_INTSTAT_PIN19_Pos) +#define GPIO_INTSTAT_PIN20_Pos 20 +#define GPIO_INTSTAT_PIN20_Msk (0x01 << GPIO_INTSTAT_PIN20_Pos) +#define GPIO_INTSTAT_PIN21_Pos 21 +#define GPIO_INTSTAT_PIN21_Msk (0x01 << GPIO_INTSTAT_PIN21_Pos) +#define GPIO_INTSTAT_PIN22_Pos 22 +#define GPIO_INTSTAT_PIN22_Msk (0x01 << GPIO_INTSTAT_PIN22_Pos) +#define GPIO_INTSTAT_PIN23_Pos 23 +#define GPIO_INTSTAT_PIN23_Msk (0x01 << GPIO_INTSTAT_PIN23_Pos) + +#define GPIO_INTCLR_PIN0_Pos 0 +#define GPIO_INTCLR_PIN0_Msk (0x01 << GPIO_INTCLR_PIN0_Pos) +#define GPIO_INTCLR_PIN1_Pos 1 +#define GPIO_INTCLR_PIN1_Msk (0x01 << GPIO_INTCLR_PIN1_Pos) +#define GPIO_INTCLR_PIN2_Pos 2 +#define GPIO_INTCLR_PIN2_Msk (0x01 << GPIO_INTCLR_PIN2_Pos) +#define GPIO_INTCLR_PIN3_Pos 3 +#define GPIO_INTCLR_PIN3_Msk (0x01 << GPIO_INTCLR_PIN3_Pos) +#define GPIO_INTCLR_PIN4_Pos 4 +#define GPIO_INTCLR_PIN4_Msk (0x01 << GPIO_INTCLR_PIN4_Pos) +#define GPIO_INTCLR_PIN5_Pos 5 +#define GPIO_INTCLR_PIN5_Msk (0x01 << GPIO_INTCLR_PIN5_Pos) +#define GPIO_INTCLR_PIN6_Pos 6 +#define GPIO_INTCLR_PIN6_Msk (0x01 << GPIO_INTCLR_PIN6_Pos) +#define GPIO_INTCLR_PIN7_Pos 7 +#define GPIO_INTCLR_PIN7_Msk (0x01 << GPIO_INTCLR_PIN7_Pos) +#define GPIO_INTCLR_PIN8_Pos 8 +#define GPIO_INTCLR_PIN8_Msk (0x01 << GPIO_INTCLR_PIN8_Pos) +#define GPIO_INTCLR_PIN9_Pos 9 +#define GPIO_INTCLR_PIN9_Msk (0x01 << GPIO_INTCLR_PIN9_Pos) +#define GPIO_INTCLR_PIN10_Pos 10 +#define GPIO_INTCLR_PIN10_Msk (0x01 << GPIO_INTCLR_PIN10_Pos) +#define GPIO_INTCLR_PIN11_Pos 11 +#define GPIO_INTCLR_PIN11_Msk (0x01 << GPIO_INTCLR_PIN11_Pos) +#define GPIO_INTCLR_PIN12_Pos 12 +#define GPIO_INTCLR_PIN12_Msk (0x01 << GPIO_INTCLR_PIN12_Pos) +#define GPIO_INTCLR_PIN13_Pos 13 +#define GPIO_INTCLR_PIN13_Msk (0x01 << GPIO_INTCLR_PIN13_Pos) +#define GPIO_INTCLR_PIN14_Pos 14 +#define GPIO_INTCLR_PIN14_Msk (0x01 << GPIO_INTCLR_PIN14_Pos) +#define GPIO_INTCLR_PIN15_Pos 15 +#define GPIO_INTCLR_PIN15_Msk (0x01 << GPIO_INTCLR_PIN15_Pos) +#define GPIO_INTCLR_PIN16_Pos 16 +#define GPIO_INTCLR_PIN16_Msk (0x01 << GPIO_INTCLR_PIN16_Pos) +#define GPIO_INTCLR_PIN17_Pos 17 +#define GPIO_INTCLR_PIN17_Msk (0x01 << GPIO_INTCLR_PIN17_Pos) +#define GPIO_INTCLR_PIN18_Pos 18 +#define GPIO_INTCLR_PIN18_Msk (0x01 << GPIO_INTCLR_PIN18_Pos) +#define GPIO_INTCLR_PIN19_Pos 19 +#define GPIO_INTCLR_PIN19_Msk (0x01 << GPIO_INTCLR_PIN19_Pos) +#define GPIO_INTCLR_PIN20_Pos 20 +#define GPIO_INTCLR_PIN20_Msk (0x01 << GPIO_INTCLR_PIN20_Pos) +#define GPIO_INTCLR_PIN21_Pos 21 +#define GPIO_INTCLR_PIN21_Msk (0x01 << GPIO_INTCLR_PIN21_Pos) +#define GPIO_INTCLR_PIN22_Pos 22 +#define GPIO_INTCLR_PIN22_Msk (0x01 << GPIO_INTCLR_PIN22_Pos) +#define GPIO_INTCLR_PIN23_Pos 23 +#define GPIO_INTCLR_PIN23_Msk (0x01 << GPIO_INTCLR_PIN23_Pos) + +typedef struct +{ + __IO uint32_t LDVAL; //定时器加载值，使能后定时器从此数值开始向下递减计数 + + __I uint32_t CVAL; //定时器当前值，LDVAL-CVAL 可计算出计时时长 + + __IO uint32_t CTRL; +} TIMR_TypeDef; + +#define TIMR_CTRL_EN_Pos 0 //此位赋1导致TIMR从LDVAL开始向下递减计数 +#define TIMR_CTRL_EN_Msk (0x01 << TIMR_CTRL_EN_Pos) +#define TIMR_CTRL_CLKSRC_Pos 1 //时钟源：0 内部系统时钟 1 外部引脚脉冲计数 +#define TIMR_CTRL_CLKSRC_Msk (0x01 << TIMR_CTRL_CLKSRC_Pos) +#define TIMR_CTRL_CASCADE_Pos 2 //1 TIMRx的计数时钟为TIMRx-1的溢出信号 +#define TIMR_CTRL_CASCADE_Msk (0x01 << TIMR_CTRL_CASCADE_Pos) + +typedef struct +{ + __IO uint32_t PCTRL; //Pulse Control，脉宽测量模块控制寄存器 + + __I uint32_t PCVAL; //脉宽测量定时器当前值 + + uint32_t RESERVED[2]; + + __IO uint32_t IE; + + __IO uint32_t IF; + + __IO uint32_t HALT; +} TIMRG_TypeDef; + +#define TIMRG_PCTRL_EN_Pos 0 //开始测量脉宽，脉宽内32位计数器从0开始向上计数 +#define TIMRG_PCTRL_EN_Msk (0x01 << TIMRG_PCTRL_EN_Pos) +#define TIMRG_PCTRL_HIGH_Pos 1 //0 测量低电平长度 1 测量高电平长度 +#define TIMRG_PCTRL_HIGH_Msk (0x01 << TIMRG_PCTRL_HIGH_Pos) +#define TIMRG_PCTRL_CLKSRC_Pos 2 //时钟源：0 内部系统时钟 1 脉宽测量模块变成一个计数器，不再具有脉宽测量功能 +#define TIMRG_PCTRL_CLKSRC_Msk (0x01 << TIMRG_PCTRL_CLKSRC_Pos) + +#define TIMRG_IE_TIMR0_Pos 0 +#define TIMRG_IE_TIMR0_Msk (0x01 << TIMRG_IE_TIMR0_Pos) +#define TIMRG_IE_TIMR1_Pos 1 +#define TIMRG_IE_TIMR1_Msk (0x01 << TIMRG_IE_TIMR1_Pos) +#define TIMRG_IE_TIMR2_Pos 2 +#define TIMRG_IE_TIMR2_Msk (0x01 << TIMRG_IE_TIMR2_Pos) +#define TIMRG_IE_TIMR3_Pos 3 +#define TIMRG_IE_TIMR3_Msk (0x01 << TIMRG_IE_TIMR3_Pos) +#define TIMRG_IE_TIMR4_Pos 4 +#define TIMRG_IE_TIMR4_Msk (0x01 << TIMRG_IE_TIMR4_Pos) +#define TIMRG_IE_TIMR5_Pos 5 +#define TIMRG_IE_TIMR5_Msk (0x01 << TIMRG_IE_TIMR5_Pos) +#define TIMRG_IE_PULSE_Pos 16 +#define TIMRG_IE_PULSE_Msk (0x01 << TIMRG_IE_PULSE_Pos) + +#define TIMRG_IF_TIMR0_Pos 0 //写1清零 +#define TIMRG_IF_TIMR0_Msk (0x01 << TIMRG_IF_TIMR0_Pos) +#define TIMRG_IF_TIMR1_Pos 1 +#define TIMRG_IF_TIMR1_Msk (0x01 << TIMRG_IF_TIMR1_Pos) +#define TIMRG_IF_TIMR2_Pos 2 +#define TIMRG_IF_TIMR2_Msk (0x01 << TIMRG_IF_TIMR2_Pos) +#define TIMRG_IF_TIMR3_Pos 3 +#define TIMRG_IF_TIMR3_Msk (0x01 << TIMRG_IF_TIMR3_Pos) +#define TIMRG_IF_TIMR4_Pos 4 +#define TIMRG_IF_TIMR4_Msk (0x01 << TIMRG_IF_TIMR4_Pos) +#define TIMRG_IF_TIMR5_Pos 5 +#define TIMRG_IF_TIMR5_Msk (0x01 << TIMRG_IF_TIMR5_Pos) +#define TIMRG_IF_PULSE_Pos 16 +#define TIMRG_IF_PULSE_Msk (0x01 << TIMRG_IF_PULSE_Pos) + +#define TIMRG_HALT_TIMR0_Pos 0 //1 暂停计数 +#define TIMRG_HALT_TIMR0_Msk (0x01 << TIMRG_HALT_TIMR0_Pos) +#define TIMRG_HALT_TIMR1_Pos 1 +#define TIMRG_HALT_TIMR1_Msk (0x01 << TIMRG_HALT_TIMR1_Pos) +#define TIMRG_HALT_TIMR2_Pos 2 +#define TIMRG_HALT_TIMR2_Msk (0x01 << TIMRG_HALT_TIMR2_Pos) +#define TIMRG_HALT_TIMR3_Pos 3 +#define TIMRG_HALT_TIMR3_Msk (0x01 << TIMRG_HALT_TIMR3_Pos) +#define TIMRG_HALT_TIMR4_Pos 4 +#define TIMRG_HALT_TIMR4_Msk (0x01 << TIMRG_HALT_TIMR4_Pos) +#define TIMRG_HALT_TIMR5_Pos 5 +#define TIMRG_HALT_TIMR5_Msk (0x01 << TIMRG_HALT_TIMR5_Pos) + +typedef struct +{ + __IO uint32_t DATA; + + __IO uint32_t CTRL; + + __IO uint32_t BAUD; + + __IO uint32_t FIFO; + + __IO uint32_t LINCR; + + union { + __IO uint32_t CTSCR; + + __IO uint32_t RTSCR; + }; +} UART_TypeDef; + +#define UART_DATA_DATA_Pos 0 +#define UART_DATA_DATA_Msk (0x1FF << UART_DATA_DATA_Pos) +#define UART_DATA_VALID_Pos 9 //当DATA字段有有效的接收数据时，该位硬件置1，读取数据后自动清零 +#define UART_DATA_VALID_Msk (0x01 << UART_DATA_VALID_Pos) +#define UART_DATA_PAERR_Pos 10 //Parity Error +#define UART_DATA_PAERR_Msk (0x01 << UART_DATA_PAERR_Pos) + +#define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 正在发送数据 1 空闲状态，没有数据发送 +#define UART_CTRL_TXIDLE_Msk (0x01 << UART_CTRL_TXIDLE_Pos) +#define UART_CTRL_TXFF_Pos 1 //TX FIFO Full +#define UART_CTRL_TXFF_Msk (0x01 << UART_CTRL_TXFF_Pos) +#define UART_CTRL_TXIE_Pos 2 //TX 中断使能: 1 TX FF 中数据少于设定个数时产生中断 +#define UART_CTRL_TXIE_Msk (0x01 << UART_CTRL_TXIE_Pos) +#define UART_CTRL_RXNE_Pos 3 //RX FIFO Not Empty +#define UART_CTRL_RXNE_Msk (0x01 << UART_CTRL_RXNE_Pos) +#define UART_CTRL_RXIE_Pos 4 //RX 中断使能: 1 RX FF 中数据达到设定个数时产生中断 +#define UART_CTRL_RXIE_Msk (0x01 << UART_CTRL_RXIE_Pos) +#define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflow，写1清零 +#define UART_CTRL_RXOV_Msk (0x01 << UART_CTRL_RXOV_Pos) +#define UART_CTRL_TXDOIE_Pos 6 //TX Done 中断使能，发送FIFO空且发送发送移位寄存器已将最后一位发送出去 +#define UART_CTRL_TXDOIE_Msk (0x01 << UART_CTRL_TXDOIE_Pos) +#define UART_CTRL_EN_Pos 9 +#define UART_CTRL_EN_Msk (0x01 << UART_CTRL_EN_Pos) +#define UART_CTRL_LOOP_Pos 10 +#define UART_CTRL_LOOP_Msk (0x01 << UART_CTRL_LOOP_Pos) +#define UART_CTRL_BAUDEN_Pos 13 //必须写1 +#define UART_CTRL_BAUDEN_Msk (0x01 << UART_CTRL_BAUDEN_Pos) +#define UART_CTRL_TOIE_Pos 14 //TimeOut 中断使能，接收到上个字符后，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据 +#define UART_CTRL_TOIE_Msk (0x01 << UART_CTRL_TOIE_Pos) +#define UART_CTRL_BRKDET_Pos 15 //LIN Break Detect，检测到LIN Break，即RX线上检测到连续11位低电平 +#define UART_CTRL_BRKDET_Msk (0x01 << UART_CTRL_BRKDET_Pos) +#define UART_CTRL_BRKIE_Pos 16 //LIN Break Detect 中断使能 +#define UART_CTRL_BRKIE_Msk (0x01 << UART_CTRL_BRKIE_Pos) +#define UART_CTRL_GENBRK_Pos 17 //Generate LIN Break，发送LIN Break +#define UART_CTRL_GENBRK_Msk (0x01 << UART_CTRL_GENBRK_Pos) +#define UART_CTRL_DATA9b_Pos 18 //1 9位数据位 0 8位数据位 +#define UART_CTRL_DATA9b_Msk (0x01 << UART_CTRL_DATA9b_Pos) +#define UART_CTRL_PARITY_Pos 19 //000 无校验 001 奇校验 011 偶校验 101 固定为1 111 固定为0 +#define UART_CTRL_PARITY_Msk (0x07 << UART_CTRL_PARITY_Pos) +#define UART_CTRL_STOP2b_Pos 22 //1 2位停止位 0 1位停止位 +#define UART_CTRL_STOP2b_Msk (0x03 << UART_CTRL_STOP2b_Pos) +#define UART_CTRL_TOTIME_Pos 24 //TimeOut 时长 = TOTIME/(BAUDRAUD/10) 秒 +#define UART_CTRL_TOTIME_Msk (0xFFu << UART_CTRL_TOTIME_Pos) + +#define UART_BAUD_BAUD_Pos 0 //串口波特率 = SYS_Freq/16/BAUD - 1 +#define UART_BAUD_BAUD_Msk (0x3FFF << UART_BAUD_BAUD_Pos) +#define UART_BAUD_TXD_Pos 14 //通过此位可直接读取串口TXD引脚上的电平 +#define UART_BAUD_TXD_Msk (0x01 << UART_BAUD_TXD_Pos) +#define UART_BAUD_RXD_Pos 15 //通过此位可直接读取串口RXD引脚上的电平 +#define UART_BAUD_RXD_Msk (0x01 << UART_BAUD_RXD_Pos) +#define UART_BAUD_RXTOIF_Pos 16 //接收&超时的中断标志 = RXIF | TOIF +#define UART_BAUD_RXTOIF_Msk (0x01 << UART_BAUD_RXTOIF_Pos) +#define UART_BAUD_TXIF_Pos 17 //发送中断标志 = TXTHRF & TXIE +#define UART_BAUD_TXIF_Msk (0x01 << UART_BAUD_TXIF_Pos) +#define UART_BAUD_BRKIF_Pos 18 //LIN Break Detect 中断标志，检测到LIN Break时若BRKIE=1，此位由硬件置位 +#define UART_BAUD_BRKIF_Msk (0x01 << UART_BAUD_BRKIF_Pos) +#define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold Flag，RX FIFO中数据达到设定个数（RXLVL >= RXTHR）时硬件置1 +#define UART_BAUD_RXTHRF_Msk (0x01 << UART_BAUD_RXTHRF_Pos) +#define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold Flag，TX FIFO中数据少于设定个数（TXLVL <= TXTHR）时硬件置1 +#define UART_BAUD_TXTHRF_Msk (0x01 << UART_BAUD_TXTHRF_Pos) +#define UART_BAUD_TOIF_Pos 21 //TimeOut 中断标志，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据时若TOIE=1，此位由硬件置位 +#define UART_BAUD_TOIF_Msk (0x01 << UART_BAUD_TOIF_Pos) +#define UART_BAUD_RXIF_Pos 22 //接收中断标志 = RXTHRF & RXIE +#define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos) +#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable，写1启动自动波特率校准，完成后自动清零 +#define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos) +#define UART_BAUD_ABRBIT_Pos 24 //Auto Baudrate Bit，用于计算波特率的检测位长，0 1位，通过测起始位 脉宽计算波特率，要求发送端发送0xFF \ + // 1 2位，通过测起始位加1位数据位脉宽计算波特率，要求发送端发送0xFE \ + // 1 4位，通过测起始位加3位数据位脉宽计算波特率，要求发送端发送0xF8 \ + // 1 8位，通过测起始位加7位数据位脉宽计算波特率，要求发送端发送0x80 +#define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos) +#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error，0 自动波特率校准成功 1 自动波特率校准失败 +#define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos) +#define UART_BAUD_TXDOIF_Pos 27 //TX Done 中断标志，发送FIFO空且发送发送移位寄存器已将最后一位发送出去 +#define UART_BAUD_TXDOIF_Msk (0x01 << UART_BAUD_TXDOIF_Pos) + +#define UART_FIFO_RXLVL_Pos 0 //RX FIFO Level，RX FIFO 中字符个数 +#define UART_FIFO_RXLVL_Msk (0xFF << UART_FIFO_RXLVL_Pos) +#define UART_FIFO_TXLVL_Pos 8 //TX FIFO Level，TX FIFO 中字符个数 +#define UART_FIFO_TXLVL_Msk (0xFF << UART_FIFO_TXLVL_Pos) +#define UART_FIFO_RXTHR_Pos 16 //RX FIFO Threshold，RX中断触发门限，中断使能时 RXLVL >= RXTHR 触发RX中断 +#define UART_FIFO_RXTHR_Msk (0xFF << UART_FIFO_RXTHR_Pos) +#define UART_FIFO_TXTHR_Pos 24 //TX FIFO Threshold，TX中断触发门限，中断使能时 TXLVL <= TXTHR 触发TX中断 +#define UART_FIFO_TXTHR_Msk (0xFFu << UART_FIFO_TXTHR_Pos) + +#define UART_LINCR_BRKDETIE_Pos 0 //检测到LIN Break中断使能 +#define UART_LINCR_BRKDETIE_Msk (0x01 << UART_LINCR_BRKDETIE_Pos) +#define UART_LINCR_BRKDETIF_Pos 1 //检测到LIN Break中断状态 +#define UART_LINCR_BRKDETIF_Msk (0x01 << UART_LINCR_BRKDETIF_Pos) +#define UART_LINCR_GENBRKIE_Pos 2 //发送LIN Break完成中断使能 +#define UART_LINCR_GENBRKIE_Msk (0x01 << UART_LINCR_GENBRKIE_Pos) +#define UART_LINCR_GENBRKIF_Pos 3 //发送LIN Break完成中断状态 +#define UART_LINCR_GENBRKIF_Msk (0x01 << UART_LINCR_GENBRKIF_Pos) +#define UART_LINCR_GENBRK_Pos 4 //发送LIN Break，发送完成自动清零 +#define UART_LINCR_GENBRK_Msk (0x01 << UART_LINCR_GENBRK_Pos) + +#define UART_CTSCR_EN_Pos 0 //CTS流控使能 +#define UART_CTSCR_EN_Msk (0x01 << UART_CTSCR_EN_Pos) +#define UART_CTSCR_POL_Pos 2 //CTS信号极性，0 低有效，CTS输入为低表示可以发送数据 +#define UART_CTSCR_POL_Msk (0x01 << UART_CTSCR_POL_Pos) +#define UART_CTSCR_STAT_Pos 7 //CTS信号的当前状态 +#define UART_CTSCR_STAT_Msk (0x01 << UART_CTSCR_STAT_Pos) + +#define UART_RTSCR_EN_Pos 1 //RTS流控使能 +#define UART_RTSCR_EN_Msk (0x01 << UART_RTSCR_EN_Pos) +#define UART_RTSCR_POL_Pos 3 //RTS信号极性 0 低有效，RTS输入为低表示可以接收数据 +#define UART_RTSCR_POL_Msk (0x01 << UART_RTSCR_POL_Pos) +#define UART_RTSCR_THR_Pos 4 //RTS流控的触发阈值 0 1字节 1 2字节 2 4字节 3 6字节 +#define UART_RTSCR_THR_Msk (0x07 << UART_RTSCR_THR_Pos) +#define UART_RTSCR_STAT_Pos 8 //RTS信号的当前状态 +#define UART_RTSCR_STAT_Msk (0x01 << UART_RTSCR_STAT_Pos) + +typedef struct +{ + __IO uint32_t CTRL; + + __IO uint32_t DATA; + + __IO uint32_t STAT; + + __IO uint32_t IE; + + __IO uint32_t IF; +} SPI_TypeDef; + +#define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPI工作时钟 = SYS_Freq/pow(2, CLKDIV+2) +#define SPI_CTRL_CLKDIV_Msk (0x07 << SPI_CTRL_CLKDIV_Pos) +#define SPI_CTRL_EN_Pos 3 +#define SPI_CTRL_EN_Msk (0x01 << SPI_CTRL_EN_Pos) +#define SPI_CTRL_SIZE_Pos 4 //Data Size Select, 取值3--15，表示4--16位 +#define SPI_CTRL_SIZE_Msk (0x0F << SPI_CTRL_SIZE_Pos) +#define SPI_CTRL_CPHA_Pos 8 //0 在SCLK的第一个跳变沿采样数据 1 在SCLK的第二个跳变沿采样数据 +#define SPI_CTRL_CPHA_Msk (0x01 << SPI_CTRL_CPHA_Pos) +#define SPI_CTRL_CPOL_Pos 9 //0 空闲状态下SCLK为低电平 1 空闲状态下SCLK为高电平 +#define SPI_CTRL_CPOL_Msk (0x01 << SPI_CTRL_CPOL_Pos) +#define SPI_CTRL_FFS_Pos 10 //Frame Format Select, 0 SPI 1 TI SSI 2 SPI 3 SPI +#define SPI_CTRL_FFS_Msk (0x03 << SPI_CTRL_FFS_Pos) +#define SPI_CTRL_MSTR_Pos 12 //Master, 1 主模式 0 从模式 +#define SPI_CTRL_MSTR_Msk (0x01 << SPI_CTRL_MSTR_Pos) +#define SPI_CTRL_FAST_Pos 13 //1 SPI工作时钟 = SYS_Freq/2 0 SPI工作时钟由SPI->CTRL.CLKDIV设置 +#define SPI_CTRL_FAST_Msk (0x01 << SPI_CTRL_FAST_Pos) +#define SPI_CTRL_FILTE_Pos 16 //1 对SPI输入信号进行去抖操作 0 对SPI输入信号不进行去抖操作 +#define SPI_CTRL_FILTE_Msk (0x01 << SPI_CTRL_FILTE_Pos) +#define SPI_CTRL_SSN_H_Pos 17 //0 传输过程中SSN始终为0 1 传输过程中每字符之间会将SSN拉高半个SCLK周期 +#define SPI_CTRL_SSN_H_Msk (0x01 << SPI_CTRL_SSN_H_Pos) +#define SPI_CTRL_TFCLR_Pos 24 //TX FIFO Clear +#define SPI_CTRL_TFCLR_Msk (0x01 << SPI_CTRL_TFCLR_Pos) +#define SPI_CTRL_RFCLR_Pos 25 //RX FIFO Clear +#define SPI_CTRL_RFCLR_Msk (0x01 << SPI_CTRL_RFCLR_Pos) + +#define SPI_STAT_WTC_Pos 0 //Word Transmit Complete，每传输完成一个数据字由硬件置1，软件写1清零 +#define SPI_STAT_WTC_Msk (0x01 << SPI_STAT_WTC_Pos) +#define SPI_STAT_TFE_Pos 1 //发送FIFO Empty +#define SPI_STAT_TFE_Msk (0x01 << SPI_STAT_TFE_Pos) +#define SPI_STAT_TFNF_Pos 2 //发送FIFO Not Full +#define SPI_STAT_TFNF_Msk (0x01 << SPI_STAT_TFNF_Pos) +#define SPI_STAT_RFNE_Pos 3 //接收FIFO Not Empty +#define SPI_STAT_RFNE_Msk (0x01 << SPI_STAT_RFNE_Pos) +#define SPI_STAT_RFF_Pos 4 //接收FIFO Full +#define SPI_STAT_RFF_Msk (0x01 << SPI_STAT_RFF_Pos) +#define SPI_STAT_RFOVF_Pos 5 //接收FIFO Overflow +#define SPI_STAT_RFOVF_Msk (0x01 << SPI_STAT_RFOVF_Pos) +#define SPI_STAT_TFLVL_Pos 6 //发送FIFO中数据个数， 0 TFNF=0时表示FIFO内有8个数据，TFNF=1时表示FIFO内有0个数据 1--7 FIFO内有1--7个数据 +#define SPI_STAT_TFLVL_Msk (0x07 << SPI_STAT_TFLVL_Pos) +#define SPI_STAT_RFLVL_Pos 9 //接收FIFO中数据个数， 0 RFF=1时表示FIFO内有8个数据， RFF=0时表示FIFO内有0个数据 1--7 FIFO内有1--7个数据 +#define SPI_STAT_RFLVL_Msk (0x07 << SPI_STAT_RFLVL_Pos) +#define SPI_STAT_BUSY_Pos 15 +#define SPI_STAT_BUSY_Msk (0x01 << SPI_STAT_BUSY_Pos) + +#define SPI_IE_RFOVF_Pos 0 +#define SPI_IE_RFOVF_Msk (0x01 << SPI_IE_RFOVF_Pos) +#define SPI_IE_RFF_Pos 1 +#define SPI_IE_RFF_Msk (0x01 << SPI_IE_RFF_Pos) +#define SPI_IE_RFHF_Pos 2 +#define SPI_IE_RFHF_Msk (0x01 << SPI_IE_RFHF_Pos) +#define SPI_IE_TFE_Pos 3 +#define SPI_IE_TFE_Msk (0x01 << SPI_IE_TFE_Pos) +#define SPI_IE_TFHF_Pos 4 +#define SPI_IE_TFHF_Msk (0x01 << SPI_IE_TFHF_Pos) +#define SPI_IE_WTC_Pos 8 //Word Transmit Complete +#define SPI_IE_WTC_Msk (0x01 << SPI_IE_WTC_Pos) +#define SPI_IE_FTC_Pos 9 //Frame Transmit Complete +#define SPI_IE_FTC_Msk (0x01 << SPI_IE_FTC_Pos) + +#define SPI_IF_RFOVF_Pos 0 //写1清零 +#define SPI_IF_RFOVF_Msk (0x01 << SPI_IF_RFOVF_Pos) +#define SPI_IF_RFF_Pos 1 +#define SPI_IF_RFF_Msk (0x01 << SPI_IF_RFF_Pos) +#define SPI_IF_RFHF_Pos 2 +#define SPI_IF_RFHF_Msk (0x01 << SPI_IF_RFHF_Pos) +#define SPI_IF_TFE_Pos 3 +#define SPI_IF_TFE_Msk (0x01 << SPI_IF_TFE_Pos) +#define SPI_IF_TFHF_Pos 4 +#define SPI_IF_TFHF_Msk (0x01 << SPI_IF_TFHF_Pos) +#define SPI_IF_WTC_Pos 8 //Word Transmit Complete，每传输完成一个数据字由硬件置1 +#define SPI_IF_WTC_Msk (0x01 << SPI_IF_WTC_Pos) +#define SPI_IF_FTC_Pos 9 //Frame Transmit Complete，WTC置位时若TX FIFO是空的，则FTC置位 +#define SPI_IF_FTC_Msk (0x01 << SPI_IF_FTC_Pos) + +typedef struct +{ + __IO uint32_t CLKDIV; //[15:0] 须将内部工作频率分到SCL频率的5倍，即CLKDIV = SYS_Freq/5/SCL_Freq - 1 + + __IO uint32_t CTRL; + + __IO uint32_t MSTDAT; + + __IO uint32_t MSTCMD; + + __IO uint32_t SLVCR; + + __IO uint32_t SLVIF; + + __IO uint32_t SLVTX; + + __IO uint32_t SLVRX; +} I2C_TypeDef; + +#define I2C_CTRL_MSTIE_Pos 6 +#define I2C_CTRL_MSTIE_Msk (0x01 << I2C_CTRL_MSTIE_Pos) +#define I2C_CTRL_EN_Pos 7 +#define I2C_CTRL_EN_Msk (0x01 << I2C_CTRL_EN_Pos) + +#define I2C_MSTCMD_IF_Pos 0 //1 有等待处理的中断，写1清零 有两种情况下此位硬件置位：1、一个字节传输完成 2、总线访问权丢失 +#define I2C_MSTCMD_IF_Msk (0x01 << I2C_MSTCMD_IF_Pos) +#define I2C_MSTCMD_TIP_Pos 1 //Transmission In Process +#define I2C_MSTCMD_TIP_Msk (0x01 << I2C_MSTCMD_TIP_Pos) +#define I2C_MSTCMD_ACK_Pos 3 //接收模式下，0 向发送端反馈ACK 1 向发送端反馈NACK +#define I2C_MSTCMD_ACK_Msk (0x01 << I2C_MSTCMD_ACK_Pos) +#define I2C_MSTCMD_WR_Pos 4 // 向Slave写数据时，把这一位写1，自动清零 +#define I2C_MSTCMD_WR_Msk (0x01 << I2C_MSTCMD_WR_Pos) +#define I2C_MSTCMD_RD_Pos 5 //写：从Slave读数据时，把这一位写1，自动清零 读：当I2C模块失去总线的访问权时硬件置1 +#define I2C_MSTCMD_RD_Msk (0x01 << I2C_MSTCMD_RD_Pos) +#define I2C_MSTCMD_BUSY_Pos 6 //读：当检测到START之后，这一位变1；当检测到STOP之后，这一位变0 +#define I2C_MSTCMD_BUSY_Msk (0x01 << I2C_MSTCMD_BUSY_Pos) +#define I2C_MSTCMD_STO_Pos 6 //写：产生STOP，自动清零 +#define I2C_MSTCMD_STO_Msk (0x01 << I2C_MSTCMD_STO_Pos) +#define I2C_MSTCMD_RXACK_Pos 7 //读：接收到的Slave的ACK位，0 收到ACK 1 收到NACK +#define I2C_MSTCMD_RXACK_Msk (0x01 << I2C_MSTCMD_RXACK_Pos) +#define I2C_MSTCMD_STA_Pos 7 //写：产生START，自动清零 +#define I2C_MSTCMD_STA_Msk (0x01 << I2C_MSTCMD_STA_Pos) + +#define I2C_SLVCR_IM_RXEND_Pos 0 //接收完成中断禁止 +#define I2C_SLVCR_IM_RXEND_Msk (0x01 << I2C_SLVCR_IM_RXEND_Pos) +#define I2C_SLVCR_IM_TXEND_Pos 1 //发送完成中断禁止 +#define I2C_SLVCR_IM_TXEND_Msk (0x01 << I2C_SLVCR_IM_TXEND_Pos) +#define I2C_SLVCR_IM_STADET_Pos 2 //检测到起始中断禁止 +#define I2C_SLVCR_IM_STADET_Msk (0x01 << I2C_SLVCR_IM_STADET_Pos) +#define I2C_SLVCR_IM_STODET_Pos 3 //检测到停止中断禁止 +#define I2C_SLVCR_IM_STODET_Msk (0x01 << I2C_SLVCR_IM_STODET_Pos) +#define I2C_SLVCR_IM_RDREQ_Pos 4 //接收到读请求中断禁止 +#define I2C_SLVCR_IM_RDREQ_Msk (0x01 << I2C_SLVCR_IM_RDREQ_Pos) +#define I2C_SLVCR_IM_WRREQ_Pos 5 //接收到写请求中断禁止 +#define I2C_SLVCR_IM_WRREQ_Msk (0x01 << I2C_SLVCR_IM_WRREQ_Pos) +#define I2C_SLVCR_ADDR7b_Pos 16 //1 7位地址模式 0 10位地址模式 +#define I2C_SLVCR_ADDR7b_Msk (0x01 << I2C_SLVCR_ADDR7b_Pos) +#define I2C_SLVCR_ACK_Pos 17 //1 应答ACK 0 应答NACK +#define I2C_SLVCR_ACK_Msk (0x01 << I2C_SLVCR_ACK_Pos) +#define I2C_SLVCR_SLAVE_Pos 18 //1 从机模式 0 主机模式 +#define I2C_SLVCR_SLAVE_Msk (0x01 << I2C_SLVCR_SLAVE_Pos) +#define I2C_SLVCR_DEBOUNCE_Pos 19 //去抖动使能 +#define I2C_SLVCR_DEBOUNCE_Msk (0x01 << I2C_SLVCR_DEBOUNCE_Pos) +#define I2C_SLVCR_ADDR_Pos 20 //从机地址 +#define I2C_SLVCR_ADDR_Msk (0x3FF << I2C_SLVCR_ADDR_Pos) + +#define I2C_SLVIF_RXEND_Pos 0 //接收完成中断标志，写1清零 +#define I2C_SLVIF_RXEND_Msk (0x01 << I2C_SLVIF_RXEND_Pos) +#define I2C_SLVIF_TXEND_Pos 1 //发送完成中断标志，写1清零 +#define I2C_SLVIF_TXEND_Msk (0x01 << I2C_SLVIF_TXEND_Pos) +#define I2C_SLVIF_STADET_Pos 2 //检测到起始中断标志，写1清零 +#define I2C_SLVIF_STADET_Msk (0x01 << I2C_SLVIF_STADET_Pos) +#define I2C_SLVIF_STODET_Pos 3 //检测到停止中断标志，写1清零 +#define I2C_SLVIF_STODET_Msk (0x01 << I2C_SLVIF_STODET_Pos) +#define I2C_SLVIF_RDREQ_Pos 4 //接收到读请求中断标志 +#define I2C_SLVIF_RDREQ_Msk (0x01 << I2C_SLVIF_RDREQ_Pos) +#define I2C_SLVIF_WRREQ_Pos 5 //接收到写请求中断标志 +#define I2C_SLVIF_WRREQ_Msk (0x01 << I2C_SLVIF_WRREQ_Pos) +#define I2C_SLVIF_ACTIVE_Pos 6 //slave 有效 +#define I2C_SLVIF_ACTIVE_Msk (0x01 << I2C_SLVIF_ACTIVE_Pos) + +typedef struct +{ + __IO uint32_t CTRL; + + __IO uint32_t START; + + __IO uint32_t IE; + + __IO uint32_t IF; + + struct + { + __IO uint32_t STAT; + + __IO uint32_t DATA; + + uint32_t RESERVED[2]; + } CH[8]; + + __IO uint32_t CTRL1; + + __IO uint32_t CTRL2; + + uint32_t RESERVED[2]; + + __IO uint32_t CALIBSET; + + __IO uint32_t CALIBEN; +} ADC_TypeDef; + +#define ADC_CTRL_CH0_Pos 0 //通道选中 +#define ADC_CTRL_CH0_Msk (0x01 << ADC_CTRL_CH0_Pos) +#define ADC_CTRL_CH1_Pos 1 +#define ADC_CTRL_CH1_Msk (0x01 << ADC_CTRL_CH1_Pos) +#define ADC_CTRL_CH2_Pos 2 +#define ADC_CTRL_CH2_Msk (0x01 << ADC_CTRL_CH2_Pos) +#define ADC_CTRL_CH3_Pos 3 +#define ADC_CTRL_CH3_Msk (0x01 << ADC_CTRL_CH3_Pos) +#define ADC_CTRL_CH4_Pos 4 +#define ADC_CTRL_CH4_Msk (0x01 << ADC_CTRL_CH4_Pos) +#define ADC_CTRL_CH5_Pos 5 +#define ADC_CTRL_CH5_Msk (0x01 << ADC_CTRL_CH5_Pos) +#define ADC_CTRL_CH6_Pos 6 +#define ADC_CTRL_CH6_Msk (0x01 << ADC_CTRL_CH6_Pos) +#define ADC_CTRL_CH7_Pos 7 +#define ADC_CTRL_CH7_Msk (0x01 << ADC_CTRL_CH7_Pos) +#define ADC_CTRL_AVG_Pos 8 //0 1次采样 1 2次采样取平均值 3 4次采样取平均值 7 8次采样取平均值 15 16次采样取平均值 +#define ADC_CTRL_AVG_Msk (0x0F << ADC_CTRL_AVG_Pos) +#define ADC_CTRL_EN_Pos 12 +#define ADC_CTRL_EN_Msk (0x01 << ADC_CTRL_EN_Pos) +#define ADC_CTRL_CONT_Pos 13 //Continuous conversion，只在软件启动模式下有效，0 单次转换，转换完成后START位自动清除停止转换 +#define ADC_CTRL_CONT_Msk (0x01 << ADC_CTRL_CONT_Pos) // 1 连续转换，启动后一直采样、转换，直到软件清除START位 +#define ADC_CTRL_TRIG_Pos 14 //转换触发方式：0 软件启动转换 1 PWM触发 +#define ADC_CTRL_TRIG_Msk (0x01 << ADC_CTRL_TRIG_Pos) +#define ADC_CTRL_CLKSRC_Pos 15 //0 VCO 1 HRC +#define ADC_CTRL_CLKSRC_Msk (0x01 << ADC_CTRL_CLKSRC_Pos) +#define ADC_CTRL_FIFOCLR_Pos 24 //[24] CH0_FIFO_CLR [25] CH1_FIFO_CLR ... [31] CH7_FIFO_CLR +#define ADC_CTRL_FIFOCLR_Msk (0xFFu << ADC_CTRL_FIFOCLR_Pos) + +#define ADC_START_GO_Pos 0 //软件触发模式下，写1启动ADC采样和转换，在单次模式下转换完成后硬件自动清零，在扫描模式下必须软件写0停止ADC转换 +#define ADC_START_GO_Msk (0x01 << ADC_START_GO_Pos) +#define ADC_START_BUSY_Pos 4 +#define ADC_START_BUSY_Msk (0x01 << ADC_START_BUSY_Pos) + +#define ADC_IE_CH0EOC_Pos 0 //End Of Convertion +#define ADC_IE_CH0EOC_Msk (0x01 << ADC_IE_CH0EOC_Pos) +#define ADC_IE_CH0OVF_Pos 1 //Overflow +#define ADC_IE_CH0OVF_Msk (0x01 << ADC_IE_CH0OVF_Pos) +#define ADC_IE_CH0HFULL_Pos 2 //FIFO Half Full +#define ADC_IE_CH0HFULL_Msk (0x01 << ADC_IE_CH0HFULL_Pos) +#define ADC_IE_CH0FULL_Pos 3 //FIFO Full +#define ADC_IE_CH0FULL_Msk (0x01 << ADC_IE_CH0FULL_Pos) +#define ADC_IE_CH1EOC_Pos 4 +#define ADC_IE_CH1EOC_Msk (0x01 << ADC_IE_CH1EOC_Pos) +#define ADC_IE_CH1OVF_Pos 5 +#define ADC_IE_CH1OVF_Msk (0x01 << ADC_IE_CH1OVF_Pos) +#define ADC_IE_CH1HFULL_Pos 6 +#define ADC_IE_CH1HFULL_Msk (0x01 << ADC_IE_CH1HFULL_Pos) +#define ADC_IE_CH1FULL_Pos 7 +#define ADC_IE_CH1FULL_Msk (0x01 << ADC_IE_CH1FULL_Pos) +#define ADC_IE_CH2EOC_Pos 8 +#define ADC_IE_CH2EOC_Msk (0x01 << ADC_IE_CH2EOC_Pos) +#define ADC_IE_CH2OVF_Pos 9 +#define ADC_IE_CH2OVF_Msk (0x01 << ADC_IE_CH2OVF_Pos) +#define ADC_IE_CH2HFULL_Pos 10 +#define ADC_IE_CH2HFULL_Msk (0x01 << ADC_IE_CH2HFULL_Pos) +#define ADC_IE_CH2FULL_Pos 11 +#define ADC_IE_CH2FULL_Msk (0x01 << ADC_IE_CH2FULL_Pos) +#define ADC_IE_CH3EOC_Pos 12 +#define ADC_IE_CH3EOC_Msk (0x01 << ADC_IE_CH3EOC_Pos) +#define ADC_IE_CH3OVF_Pos 13 +#define ADC_IE_CH3OVF_Msk (0x01 << ADC_IE_CH3OVF_Pos) +#define ADC_IE_CH3HFULL_Pos 14 +#define ADC_IE_CH3HFULL_Msk (0x01 << ADC_IE_CH3HFULL_Pos) +#define ADC_IE_CH3FULL_Pos 15 +#define ADC_IE_CH3FULL_Msk (0x01 << ADC_IE_CH3FULL_Pos) +#define ADC_IE_CH4EOC_Pos 16 +#define ADC_IE_CH4EOC_Msk (0x01 << ADC_IE_CH4EOC_Pos) +#define ADC_IE_CH4OVF_Pos 17 +#define ADC_IE_CH4OVF_Msk (0x01 << ADC_IE_CH4OVF_Pos) +#define ADC_IE_CH4HFULL_Pos 18 +#define ADC_IE_CH4HFULL_Msk (0x01 << ADC_IE_CH4HFULL_Pos) +#define ADC_IE_CH4FULL_Pos 19 +#define ADC_IE_CH4FULL_Msk (0x01 << ADC_IE_CH4FULL_Pos) +#define ADC_IE_CH5EOC_Pos 20 +#define ADC_IE_CH5EOC_Msk (0x01 << ADC_IE_CH5EOC_Pos) +#define ADC_IE_CH5OVF_Pos 21 +#define ADC_IE_CH5OVF_Msk (0x01 << ADC_IE_CH5OVF_Pos) +#define ADC_IE_CH5HFULL_Pos 22 +#define ADC_IE_CH5HFULL_Msk (0x01 << ADC_IE_CH5HFULL_Pos) +#define ADC_IE_CH5FULL_Pos 23 +#define ADC_IE_CH5FULL_Msk (0x01 << ADC_IE_CH5FULL_Pos) +#define ADC_IE_CH6EOC_Pos 24 +#define ADC_IE_CH6EOC_Msk (0x01 << ADC_IE_CH6EOC_Pos) +#define ADC_IE_CH6OVF_Pos 25 +#define ADC_IE_CH6OVF_Msk (0x01 << ADC_IE_CH6OVF_Pos) +#define ADC_IE_CH6HFULL_Pos 26 +#define ADC_IE_CH6HFULL_Msk (0x01 << ADC_IE_CH6HFULL_Pos) +#define ADC_IE_CH6FULL_Pos 27 +#define ADC_IE_CH6FULL_Msk (0x01 << ADC_IE_CH6FULL_Pos) +#define ADC_IE_CH7EOC_Pos 28 +#define ADC_IE_CH7EOC_Msk (0x01 << ADC_IE_CH7EOC_Pos) +#define ADC_IE_CH7OVF_Pos 29 +#define ADC_IE_CH7OVF_Msk (0x01 << ADC_IE_CH7OVF_Pos) +#define ADC_IE_CH7HFULL_Pos 30 +#define ADC_IE_CH7HFULL_Msk (0x01 << ADC_IE_CH7HFULL_Pos) +#define ADC_IE_CH7FULL_Pos 31 +#define ADC_IE_CH7FULL_Msk (0x01u << ADC_IE_CH7FULL_Pos) + +#define ADC_IF_CH0EOC_Pos 0 //写1清零 +#define ADC_IF_CH0EOC_Msk (0x01 << ADC_IF_CH0EOC_Pos) +#define ADC_IF_CH0OVF_Pos 1 //写1清零 +#define ADC_IF_CH0OVF_Msk (0x01 << ADC_IF_CH0OVF_Pos) +#define ADC_IF_CH0HFULL_Pos 2 //写1清零 +#define ADC_IF_CH0HFULL_Msk (0x01 << ADC_IF_CH0HFULL_Pos) +#define ADC_IF_CH0FULL_Pos 3 //写1清零 +#define ADC_IF_CH0FULL_Msk (0x01 << ADC_IF_CH0FULL_Pos) +#define ADC_IF_CH1EOC_Pos 4 +#define ADC_IF_CH1EOC_Msk (0x01 << ADC_IF_CH1EOC_Pos) +#define ADC_IF_CH1OVF_Pos 5 +#define ADC_IF_CH1OVF_Msk (0x01 << ADC_IF_CH1OVF_Pos) +#define ADC_IF_CH1HFULL_Pos 6 +#define ADC_IF_CH1HFULL_Msk (0x01 << ADC_IF_CH1HFULL_Pos) +#define ADC_IF_CH1FULL_Pos 7 +#define ADC_IF_CH1FULL_Msk (0x01 << ADC_IF_CH1FULL_Pos) +#define ADC_IF_CH2EOC_Pos 8 +#define ADC_IF_CH2EOC_Msk (0x01 << ADC_IF_CH2EOC_Pos) +#define ADC_IF_CH2OVF_Pos 9 +#define ADC_IF_CH2OVF_Msk (0x01 << ADC_IF_CH2OVF_Pos) +#define ADC_IF_CH2HFULL_Pos 10 +#define ADC_IF_CH2HFULL_Msk (0x01 << ADC_IF_CH2HFULL_Pos) +#define ADC_IF_CH2FULL_Pos 11 +#define ADC_IF_CH2FULL_Msk (0x01 << ADC_IF_CH2FULL_Pos) +#define ADC_IF_CH3EOC_Pos 12 +#define ADC_IF_CH3EOC_Msk (0x01 << ADC_IF_CH3EOC_Pos) +#define ADC_IF_CH3OVF_Pos 13 +#define ADC_IF_CH3OVF_Msk (0x01 << ADC_IF_CH3OVF_Pos) +#define ADC_IF_CH3HFULL_Pos 14 +#define ADC_IF_CH3HFULL_Msk (0x01 << ADC_IF_CH3HFULL_Pos) +#define ADC_IF_CH3FULL_Pos 15 +#define ADC_IF_CH3FULL_Msk (0x01 << ADC_IF_CH3FULL_Pos) +#define ADC_IF_CH4EOC_Pos 16 +#define ADC_IF_CH4EOC_Msk (0x01 << ADC_IF_CH4EOC_Pos) +#define ADC_IF_CH4OVF_Pos 17 +#define ADC_IF_CH4OVF_Msk (0x01 << ADC_IF_CH4OVF_Pos) +#define ADC_IF_CH4HFULL_Pos 18 +#define ADC_IF_CH4HFULL_Msk (0x01 << ADC_IF_CH4HFULL_Pos) +#define ADC_IF_CH4FULL_Pos 19 +#define ADC_IF_CH4FULL_Msk (0x01 << ADC_IF_CH4FULL_Pos) +#define ADC_IF_CH5EOC_Pos 20 +#define ADC_IF_CH5EOC_Msk (0x01 << ADC_IF_CH5EOC_Pos) +#define ADC_IF_CH5OVF_Pos 21 +#define ADC_IF_CH5OVF_Msk (0x01 << ADC_IF_CH5OVF_Pos) +#define ADC_IF_CH5HFULL_Pos 22 +#define ADC_IF_CH5HFULL_Msk (0x01 << ADC_IF_CH5HFULL_Pos) +#define ADC_IF_CH5FULL_Pos 23 +#define ADC_IF_CH5FULL_Msk (0x01 << ADC_IF_CH5FULL_Pos) +#define ADC_IF_CH6EOC_Pos 24 +#define ADC_IF_CH6EOC_Msk (0x01 << ADC_IF_CH6EOC_Pos) +#define ADC_IF_CH6OVF_Pos 25 +#define ADC_IF_CH6OVF_Msk (0x01 << ADC_IF_CH6OVF_Pos) +#define ADC_IF_CH6HFULL_Pos 26 +#define ADC_IF_CH6HFULL_Msk (0x01 << ADC_IF_CH6HFULL_Pos) +#define ADC_IF_CH6FULL_Pos 27 +#define ADC_IF_CH6FULL_Msk (0x01 << ADC_IF_CH6FULL_Pos) +#define ADC_IF_CH7EOC_Pos 28 +#define ADC_IF_CH7EOC_Msk (0x01 << ADC_IF_CH7EOC_Pos) +#define ADC_IF_CH7OVF_Pos 29 +#define ADC_IF_CH7OVF_Msk (0x01 << ADC_IF_CH7OVF_Pos) +#define ADC_IF_CH7HFULL_Pos 30 +#define ADC_IF_CH7HFULL_Msk (0x01 << ADC_IF_CH7HFULL_Pos) +#define ADC_IF_CH7FULL_Pos 31 +#define ADC_IF_CH7FULL_Msk (0x01 << ADC_IF_CH7FULL_Pos) + +#define ADC_STAT_EOC_Pos 0 //写1清零 +#define ADC_STAT_EOC_Msk (0x01 << ADC_STAT_EOC_Pos) +#define ADC_STAT_OVF_Pos 1 //读数据寄存器清除 +#define ADC_STAT_OVF_Msk (0x01 << ADC_STAT_OVF_Pos) +#define ADC_STAT_HFULL_Pos 2 +#define ADC_STAT_HFULL_Msk (0x01 << ADC_STAT_HFULL_Pos) +#define ADC_STAT_FULL_Pos 3 +#define ADC_STAT_FULL_Msk (0x01 << ADC_STAT_FULL_Pos) +#define ADC_STAT_EMPTY_Pos 4 +#define ADC_STAT_EMPTY_Msk (0x01 << ADC_STAT_EMPTY_Pos) + +#define ADC_CTRL1_RIN_Pos 4 //输入阻抗：0 无穷大 1 105K 2 90K 3 75K 4 60K 5 45K 6 30K 7 15K +#define ADC_CTRL1_RIN_Msk (0x07 << ADC_CTRL1_RIN_Pos) + +#define ADC_CTRL2_RESET_Pos 0 //数字电路复位 +#define ADC_CTRL2_RESET_Msk (0x01 << ADC_CTRL2_RESET_Pos) +#define ADC_CTRL2_ADCEVCM_Pos 1 //ADC External VCM，ADC与PGA输出共模电平选择 +#define ADC_CTRL2_ADCEVCM_Msk (0x01 << ADC_CTRL2_ADCEVCM_Pos) +#define ADC_CTRL2_PGAIVCM_Pos 2 //PGA Internal VCM，PGA输入共模电平选择 +#define ADC_CTRL2_PGAIVCM_Msk (0x01 << ADC_CTRL2_PGAIVCM_Pos) +#define ADC_CTRL2_PGAGAIN_Pos 3 //0 25.1dB 1 21.6dB 2 11.1dB 3 3.5dB 4 0dB(1.8V) 5 -2.9dB 6 -5.3dB +#define ADC_CTRL2_PGAGAIN_Msk (0x07 << ADC_CTRL2_PGAGAIN_Pos) +#define ADC_CTRL2_REFPOUT_Pos 23 //1 ADC 内部 1.2V REFP电压输出到外部REFP引脚，用于测量，或在需要1.2V外部REFP时节省成本 +#define ADC_CTRL2_REFPOUT_Msk (0x01 << ADC_CTRL2_REFPOUT_Pos +#define ADC_CTRL2_CLKDIV_Pos 24 //时钟分频，只在时钟源为HRC时有效 +#define ADC_CTRL2_CLKDIV_Msk (0x1F << ADC_CTRL2_CLKDIV_Pos) +#define ADC_CTRL2_PGAVCM_Pos 29 +#define ADC_CTRL2_PGAVCM_Msk (0x07u << ADC_CTRL2_PGAVCM_Pos) + +#define ADC_CALIBSET_OFFSET_Pos 0 +#define ADC_CALIBSET_OFFSET_Msk (0x1FF << ADC_CALIBSET_OFFSET_Pos) +#define ADC_CALIBSET_K_Pos 16 +#define ADC_CALIBSET_K_Msk (0x1FF << ADC_CALIBSET_K_Pos) + +#define ADC_CALIBEN_OFFSET_Pos 0 +#define ADC_CALIBEN_OFFSET_Msk (0x01 << ADC_CALIBEN_OFFSET_Pos) +#define ADC_CALIBEN_K_Pos 1 +#define ADC_CALIBEN_K_Msk (0x01 << ADC_CALIBEN_K_Pos) + +typedef struct +{ + __IO uint32_t MODE; //0 普通模式，A、B两路输出互相独立 + //1 互补模式，A、B两路输出都由PERA、HIGHA控制，B路输出与A路输出极性相反，且DZA、DZB控制A、B路输出上升沿推迟时间 + //2 单次模式，同普通模式，但一个周期后自动停止 + //3 对称模式，A、B两路输出互相独立，以两个计数周期产生一个波形输出周期，分辨率提升一倍、频率降低一倍 + //4 对称互补模式，对称模式和互补模式的综合 + + __IO uint32_t PERA; //[15:0] 周期 + + __IO uint32_t HIGHA; //[15:0] 高电平持续时长 + + __IO uint32_t DZA; //[9:0] 死区，即上升沿推迟时长，必须小于HIGHA + + __IO uint32_t PERB; + + __IO uint32_t HIGHB; + + __IO uint32_t DZB; + + __IO uint32_t INIOUT; //Init Output level，初始输出电平 +} PWM_TypeDef; + +#define PWM_INIOUT_PWMA_Pos 0 +#define PWM_INIOUT_PWMA_Msk (0x01 << PWM_INIOUT_PWMA_Pos) +#define PWM_INIOUT_PWMB_Pos 1 +#define PWM_INIOUT_PWMB_Msk (0x01 << PWM_INIOUT_PWMB_Pos) + +typedef struct +{ + __IO uint32_t FORCEH; + + __IO uint32_t ADTRG0A; + __IO uint32_t ADTRG0B; + + __IO uint32_t ADTRG1A; + __IO uint32_t ADTRG1B; + + __IO uint32_t ADTRG2A; + __IO uint32_t ADTRG2B; + + __IO uint32_t ADTRG3A; + __IO uint32_t ADTRG3B; + + __IO uint32_t ADTRG4A; + __IO uint32_t ADTRG4B; + + __IO uint32_t ADTRG5A; + __IO uint32_t ADTRG5B; + + uint32_t RESERVED[3]; + + __IO uint32_t HALT; //刹车控制 + + __IO uint32_t CHEN; + + __IO uint32_t IE; + + __IO uint32_t IF; + + __IO uint32_t IM; //Interrupt Mask + + __IO uint32_t IRS; //Interrupt Raw Stat +} PWMG_TypeDef; + +#define PWMG_FORCEH_PWM0_Pos 0 +#define PWMG_FORCEH_PWM0_Msk (0x01 << PWMG_FORCEH_PWM0_Pos) +#define PWMG_FORCEH_PWM1_Pos 1 +#define PWMG_FORCEH_PWM1_Msk (0x01 << PWMG_FORCEH_PWM1_Pos) +#define PWMG_FORCEH_PWM2_Pos 2 +#define PWMG_FORCEH_PWM2_Msk (0x01 << PWMG_FORCEH_PWM2_Pos) +#define PWMG_FORCEH_PWM3_Pos 3 +#define PWMG_FORCEH_PWM3_Msk (0x01 << PWMG_FORCEH_PWM3_Pos) +#define PWMG_FORCEH_PWM4_Pos 4 +#define PWMG_FORCEH_PWM4_Msk (0x01 << PWMG_FORCEH_PWM4_Pos) +#define PWMG_FORCEH_PWM5_Pos 5 +#define PWMG_FORCEH_PWM5_Msk (0x01 << PWMG_FORCEH_PWM5_Pos) + +#define PWMG_ADTRG_VALUE_Pos 0 +#define PWMG_ADTRG_VALUE_Msk (0xFFFF << PWMG_ADTRG0A_VALUE_Pos) +#define PWMG_ADTRG_EVEN_Pos 16 //1 偶数周期生效 0 奇数周期生效 +#define PWMG_ADTRG_EVEN_Msk (0x01 << PWMG_ADTRG0A_EVEN_Pos) +#define PWMG_ADTRG_EN_Pos 17 +#define PWMG_ADTRG_EN_Msk (0x01 << PWMG_ADTRG0A_EN_Pos) + +#define PWMG_HALT_EN_Pos 0 +#define PWMG_HALT_EN_Msk (0x01 << PWMG_HALT_EN_Pos) +#define PWMG_HALT_PWM0_Pos 1 +#define PWMG_HALT_PWM0_Msk (0x01 << PWMG_HALT_PWM0_Pos) +#define PWMG_HALT_PWM1_Pos 2 +#define PWMG_HALT_PWM1_Msk (0x01 << PWMG_HALT_PWM1_Pos) +#define PWMG_HALT_PWM2_Pos 3 +#define PWMG_HALT_PWM2_Msk (0x01 << PWMG_HALT_PWM2_Pos) +#define PWMG_HALT_PWM3_Pos 4 +#define PWMG_HALT_PWM3_Msk (0x01 << PWMG_HALT_PWM3_Pos) +#define PWMG_HALT_PWM4_Pos 5 +#define PWMG_HALT_PWM4_Msk (0x01 << PWMG_HALT_PWM4_Pos) +#define PWMG_HALT_PWM5_Pos 6 +#define PWMG_HALT_PWM5_Msk (0x01 << PWMG_HALT_PWM5_Pos) +#define PWMG_HALT_STOPCNT_Pos 7 //1 刹车时将PWM计数器清零，停止计数 0 刹车时，PWM计数器继续计数 +#define PWMG_HALT_STOPCNT_Msk (0x01 << PWMG_HALT_STOPCNT_Pos) +#define PWMG_HALT_INLVL_Pos 8 //1 刹车输入高电平有效 +#define PWMG_HALT_INLVL_Msk (0x01 << PWMG_HALT_INLVL_Pos) +#define PWMG_HALT_OUTLVL_Pos 9 //1 刹车过程中输出高电平 +#define PWMG_HALT_OUTLVL_Msk (0x01 << PWMG_HALT_OUTLVL_Pos) +#define PWMG_HALT_STAT_Pos 10 //1 正在刹车 +#define PWMG_HALT_STAT_Msk (0x01 << PWMG_HALT_STAT_Pos) + +#define PWMG_CHEN_PWM0A_Pos 0 +#define PWMG_CHEN_PWM0A_Msk (0x01 << PWMG_CHEN_PWM0A_Pos) +#define PWMG_CHEN_PWM0B_Pos 1 +#define PWMG_CHEN_PWM0B_Msk (0x01 << PWMG_CHEN_PWM0B_Pos) +#define PWMG_CHEN_PWM1A_Pos 2 +#define PWMG_CHEN_PWM1A_Msk (0x01 << PWMG_CHEN_PWM1A_Pos) +#define PWMG_CHEN_PWM1B_Pos 3 +#define PWMG_CHEN_PWM1B_Msk (0x01 << PWMG_CHEN_PWM1B_Pos) +#define PWMG_CHEN_PWM2A_Pos 4 +#define PWMG_CHEN_PWM2A_Msk (0x01 << PWMG_CHEN_PWM2A_Pos) +#define PWMG_CHEN_PWM2B_Pos 5 +#define PWMG_CHEN_PWM2B_Msk (0x01 << PWMG_CHEN_PWM2B_Pos) +#define PWMG_CHEN_PWM3A_Pos 6 +#define PWMG_CHEN_PWM3A_Msk (0x01 << PWMG_CHEN_PWM3A_Pos) +#define PWMG_CHEN_PWM3B_Pos 7 +#define PWMG_CHEN_PWM3B_Msk (0x01 << PWMG_CHEN_PWM3B_Pos) +#define PWMG_CHEN_PWM4A_Pos 8 +#define PWMG_CHEN_PWM4A_Msk (0x01 << PWMG_CHEN_PWM4A_Pos) +#define PWMG_CHEN_PWM4B_Pos 9 +#define PWMG_CHEN_PWM4B_Msk (0x01 << PWMG_CHEN_PWM4B_Pos) +#define PWMG_CHEN_PWM5A_Pos 10 +#define PWMG_CHEN_PWM5A_Msk (0x01 << PWMG_CHEN_PWM5A_Pos) +#define PWMG_CHEN_PWM5B_Pos 11 +#define PWMG_CHEN_PWM5B_Msk (0x01 << PWMG_CHEN_PWM5B_Pos) + +#define PWMG_IE_NEWP0A_Pos 0 +#define PWMG_IE_NEWP0A_Msk (0x01 << PWMG_IE_NEWP0A_Pos) +#define PWMG_IE_NEWP0B_Pos 1 +#define PWMG_IE_NEWP0B_Msk (0x01 << PWMG_IE_NEWP0B_Pos) +#define PWMG_IE_NEWP1A_Pos 2 +#define PWMG_IE_NEWP1A_Msk (0x01 << PWMG_IE_NEWP1A_Pos) +#define PWMG_IE_NEWP1B_Pos 3 +#define PWMG_IE_NEWP1B_Msk (0x01 << PWMG_IE_NEWP1B_Pos) +#define PWMG_IE_NEWP2A_Pos 4 +#define PWMG_IE_NEWP2A_Msk (0x01 << PWMG_IE_NEWP2A_Pos) +#define PWMG_IE_NEWP2B_Pos 5 +#define PWMG_IE_NEWP2B_Msk (0x01 << PWMG_IE_NEWP2B_Pos) +#define PWMG_IE_NEWP3A_Pos 6 +#define PWMG_IE_NEWP3A_Msk (0x01 << PWMG_IE_NEWP3A_Pos) +#define PWMG_IE_NEWP3B_Pos 7 +#define PWMG_IE_NEWP3B_Msk (0x01 << PWMG_IE_NEWP3B_Pos) +#define PWMG_IE_NEWP4A_Pos 8 +#define PWMG_IE_NEWP4A_Msk (0x01 << PWMG_IE_NEWP4A_Pos) +#define PWMG_IE_NEWP4B_Pos 9 +#define PWMG_IE_NEWP4B_Msk (0x01 << PWMG_IE_NEWP4B_Pos) +#define PWMG_IE_NEWP5A_Pos 10 +#define PWMG_IE_NEWP5A_Msk (0x01 << PWMG_IE_NEWP5A_Pos) +#define PWMG_IE_NEWP5B_Pos 11 +#define PWMG_IE_NEWP5B_Msk (0x01 << PWMG_IE_NEWP5B_Pos) +#define PWMG_IE_HEND0A_Pos 12 +#define PWMG_IE_HEND0A_Msk (0x01 << PWMG_IE_HEND0A_Pos) +#define PWMG_IE_HEND0B_Pos 13 +#define PWMG_IE_HEND0B_Msk (0x01 << PWMG_IE_HEND0B_Pos) +#define PWMG_IE_HEND1A_Pos 14 +#define PWMG_IE_HEND1A_Msk (0x01 << PWMG_IE_HEND1A_Pos) +#define PWMG_IE_HEND1B_Pos 15 +#define PWMG_IE_HEND1B_Msk (0x01 << PWMG_IE_HEND1B_Pos) +#define PWMG_IE_HEND2A_Pos 16 +#define PWMG_IE_HEND2A_Msk (0x01 << PWMG_IE_HEND2A_Pos) +#define PWMG_IE_HEND2B_Pos 17 +#define PWMG_IE_HEND2B_Msk (0x01 << PWMG_IE_HEND2B_Pos) +#define PWMG_IE_HEND3A_Pos 18 +#define PWMG_IE_HEND3A_Msk (0x01 << PWMG_IE_HEND3A_Pos) +#define PWMG_IE_HEND3B_Pos 19 +#define PWMG_IE_HEND3B_Msk (0x01 << PWMG_IE_HEND3B_Pos) +#define PWMG_IE_HEND4A_Pos 20 +#define PWMG_IE_HEND4A_Msk (0x01 << PWMG_IE_HEND4A_Pos) +#define PWMG_IE_HEND4B_Pos 21 +#define PWMG_IE_HEND4B_Msk (0x01 << PWMG_IE_HEND4B_Pos) +#define PWMG_IE_HEND5A_Pos 22 +#define PWMG_IE_HEND5A_Msk (0x01 << PWMG_IE_HEND5A_Pos) +#define PWMG_IE_HEND5B_Pos 23 +#define PWMG_IE_HEND5B_Msk (0x01 << PWMG_IE_HEND5B_Pos) +#define PWMG_IE_HALT_Pos 24 +#define PWMG_IE_HALT_Msk (0x01 << PWMG_IE_HALT_Pos) + +#define PWMG_IF_NEWP0A_Pos 0 +#define PWMG_IF_NEWP0A_Msk (0x01 << PWMG_IF_NEWP0A_Pos) +#define PWMG_IF_NEWP0B_Pos 1 +#define PWMG_IF_NEWP0B_Msk (0x01 << PWMG_IF_NEWP0B_Pos) +#define PWMG_IF_NEWP1A_Pos 2 +#define PWMG_IF_NEWP1A_Msk (0x01 << PWMG_IF_NEWP1A_Pos) +#define PWMG_IF_NEWP1B_Pos 3 +#define PWMG_IF_NEWP1B_Msk (0x01 << PWMG_IF_NEWP1B_Pos) +#define PWMG_IF_NEWP2A_Pos 4 +#define PWMG_IF_NEWP2A_Msk (0x01 << PWMG_IF_NEWP2A_Pos) +#define PWMG_IF_NEWP2B_Pos 5 +#define PWMG_IF_NEWP2B_Msk (0x01 << PWMG_IF_NEWP2B_Pos) +#define PWMG_IF_NEWP3A_Pos 6 +#define PWMG_IF_NEWP3A_Msk (0x01 << PWMG_IF_NEWP3A_Pos) +#define PWMG_IF_NEWP3B_Pos 7 +#define PWMG_IF_NEWP3B_Msk (0x01 << PWMG_IF_NEWP3B_Pos) +#define PWMG_IF_NEWP4A_Pos 8 +#define PWMG_IF_NEWP4A_Msk (0x01 << PWMG_IF_NEWP4A_Pos) +#define PWMG_IF_NEWP4B_Pos 9 +#define PWMG_IF_NEWP4B_Msk (0x01 << PWMG_IF_NEWP4B_Pos) +#define PWMG_IF_NEWP5A_Pos 10 +#define PWMG_IF_NEWP5A_Msk (0x01 << PWMG_IF_NEWP5A_Pos) +#define PWMG_IF_NEWP5B_Pos 11 +#define PWMG_IF_NEWP5B_Msk (0x01 << PWMG_IF_NEWP5B_Pos) +#define PWMG_IF_HEND0A_Pos 12 +#define PWMG_IF_HEND0A_Msk (0x01 << PWMG_IF_HEND0A_Pos) +#define PWMG_IF_HEND0B_Pos 13 +#define PWMG_IF_HEND0B_Msk (0x01 << PWMG_IF_HEND0B_Pos) +#define PWMG_IF_HEND1A_Pos 14 +#define PWMG_IF_HEND1A_Msk (0x01 << PWMG_IF_HEND1A_Pos) +#define PWMG_IF_HEND1B_Pos 15 +#define PWMG_IF_HEND1B_Msk (0x01 << PWMG_IF_HEND1B_Pos) +#define PWMG_IF_HEND2A_Pos 16 +#define PWMG_IF_HEND2A_Msk (0x01 << PWMG_IF_HEND2A_Pos) +#define PWMG_IF_HEND2B_Pos 17 +#define PWMG_IF_HEND2B_Msk (0x01 << PWMG_IF_HEND2B_Pos) +#define PWMG_IF_HEND3A_Pos 18 +#define PWMG_IF_HEND3A_Msk (0x01 << PWMG_IF_HEND3A_Pos) +#define PWMG_IF_HEND3B_Pos 19 +#define PWMG_IF_HEND3B_Msk (0x01 << PWMG_IF_HEND3B_Pos) +#define PWMG_IF_HEND4A_Pos 20 +#define PWMG_IF_HEND4A_Msk (0x01 << PWMG_IF_HEND4A_Pos) +#define PWMG_IF_HEND4B_Pos 21 +#define PWMG_IF_HEND4B_Msk (0x01 << PWMG_IF_HEND4B_Pos) +#define PWMG_IF_HEND5A_Pos 22 +#define PWMG_IF_HEND5A_Msk (0x01 << PWMG_IF_HEND5A_Pos) +#define PWMG_IF_HEND5B_Pos 23 +#define PWMG_IF_HEND5B_Msk (0x01 << PWMG_IF_HEND5B_Pos) +#define PWMG_IF_HALT_Pos 24 +#define PWMG_IF_HALT_Msk (0x01 << PWMG_IF_HALT_Pos) + +#define PWMG_IM_NEWP0A_Pos 0 //Interrupt Mask +#define PWMG_IM_NEWP0A_Msk (0x01 << PWMG_IM_NEWP0A_Pos) +#define PWMG_IM_NEWP0B_Pos 1 +#define PWMG_IM_NEWP0B_Msk (0x01 << PWMG_IM_NEWP0B_Pos) +#define PWMG_IM_NEWP1A_Pos 2 +#define PWMG_IM_NEWP1A_Msk (0x01 << PWMG_IM_NEWP1A_Pos) +#define PWMG_IM_NEWP1B_Pos 3 +#define PWMG_IM_NEWP1B_Msk (0x01 << PWMG_IM_NEWP1B_Pos) +#define PWMG_IM_NEWP2A_Pos 4 +#define PWMG_IM_NEWP2A_Msk (0x01 << PWMG_IM_NEWP2A_Pos) +#define PWMG_IM_NEWP2B_Pos 5 +#define PWMG_IM_NEWP2B_Msk (0x01 << PWMG_IM_NEWP2B_Pos) +#define PWMG_IM_NEWP3A_Pos 6 +#define PWMG_IM_NEWP3A_Msk (0x01 << PWMG_IM_NEWP3A_Pos) +#define PWMG_IM_NEWP3B_Pos 7 +#define PWMG_IM_NEWP3B_Msk (0x01 << PWMG_IM_NEWP3B_Pos) +#define PWMG_IM_NEWP4A_Pos 8 +#define PWMG_IM_NEWP4A_Msk (0x01 << PWMG_IM_NEWP4A_Pos) +#define PWMG_IM_NEWP4B_Pos 9 +#define PWMG_IM_NEWP4B_Msk (0x01 << PWMG_IM_NEWP4B_Pos) +#define PWMG_IM_NEWP5A_Pos 10 +#define PWMG_IM_NEWP5A_Msk (0x01 << PWMG_IM_NEWP5A_Pos) +#define PWMG_IM_NEWP5B_Pos 11 +#define PWMG_IM_NEWP5B_Msk (0x01 << PWMG_IM_NEWP5B_Pos) +#define PWMG_IM_HEND0A_Pos 12 +#define PWMG_IM_HEND0A_Msk (0x01 << PWMG_IM_HEND0A_Pos) +#define PWMG_IM_HEND0B_Pos 13 +#define PWMG_IM_HEND0B_Msk (0x01 << PWMG_IM_HEND0B_Pos) +#define PWMG_IM_HEND1A_Pos 14 +#define PWMG_IM_HEND1A_Msk (0x01 << PWMG_IM_HEND1A_Pos) +#define PWMG_IM_HEND1B_Pos 15 +#define PWMG_IM_HEND1B_Msk (0x01 << PWMG_IM_HEND1B_Pos) +#define PWMG_IM_HEND2A_Pos 16 +#define PWMG_IM_HEND2A_Msk (0x01 << PWMG_IM_HEND2A_Pos) +#define PWMG_IM_HEND2B_Pos 17 +#define PWMG_IM_HEND2B_Msk (0x01 << PWMG_IM_HEND2B_Pos) +#define PWMG_IM_HEND3A_Pos 18 +#define PWMG_IM_HEND3A_Msk (0x01 << PWMG_IM_HEND3A_Pos) +#define PWMG_IM_HEND3B_Pos 19 +#define PWMG_IM_HEND3B_Msk (0x01 << PWMG_IM_HEND3B_Pos) +#define PWMG_IM_HEND4A_Pos 20 +#define PWMG_IM_HEND4A_Msk (0x01 << PWMG_IM_HEND4A_Pos) +#define PWMG_IM_HEND4B_Pos 21 +#define PWMG_IM_HEND4B_Msk (0x01 << PWMG_IM_HEND4B_Pos) +#define PWMG_IM_HEND5A_Pos 22 +#define PWMG_IM_HEND5A_Msk (0x01 << PWMG_IM_HEND5A_Pos) +#define PWMG_IM_HEND5B_Pos 23 +#define PWMG_IM_HEND5B_Msk (0x01 << PWMG_IM_HEND5B_Pos) +#define PWMG_IM_HALT_Pos 24 +#define PWMG_IM_HALT_Msk (0x01 << PWMG_IM_HALT_Pos) + +#define PWMG_IRS_NEWP0A_Pos 0 //Interrupt Raw State +#define PWMG_IRS_NEWP0A_Msk (0x01 << PWMG_IRS_NEWP0A_Pos) +#define PWMG_IRS_NEWP0B_Pos 1 +#define PWMG_IRS_NEWP0B_Msk (0x01 << PWMG_IRS_NEWP0B_Pos) +#define PWMG_IRS_NEWP1A_Pos 2 +#define PWMG_IRS_NEWP1A_Msk (0x01 << PWMG_IRS_NEWP1A_Pos) +#define PWMG_IRS_NEWP1B_Pos 3 +#define PWMG_IRS_NEWP1B_Msk (0x01 << PWMG_IRS_NEWP1B_Pos) +#define PWMG_IRS_NEWP2A_Pos 4 +#define PWMG_IRS_NEWP2A_Msk (0x01 << PWMG_IRS_NEWP2A_Pos) +#define PWMG_IRS_NEWP2B_Pos 5 +#define PWMG_IRS_NEWP2B_Msk (0x01 << PWMG_IRS_NEWP2B_Pos) +#define PWMG_IRS_NEWP3A_Pos 6 +#define PWMG_IRS_NEWP3A_Msk (0x01 << PWMG_IRS_NEWP3A_Pos) +#define PWMG_IRS_NEWP3B_Pos 7 +#define PWMG_IRS_NEWP3B_Msk (0x01 << PWMG_IRS_NEWP3B_Pos) +#define PWMG_IRS_NEWP4A_Pos 8 +#define PWMG_IRS_NEWP4A_Msk (0x01 << PWMG_IRS_NEWP4A_Pos) +#define PWMG_IRS_NEWP4B_Pos 9 +#define PWMG_IRS_NEWP4B_Msk (0x01 << PWMG_IRS_NEWP4B_Pos) +#define PWMG_IRS_NEWP5A_Pos 10 +#define PWMG_IRS_NEWP5A_Msk (0x01 << PWMG_IRS_NEWP5A_Pos) +#define PWMG_IRS_NEWP5B_Pos 11 +#define PWMG_IRS_NEWP5B_Msk (0x01 << PWMG_IRS_NEWP5B_Pos) +#define PWMG_IRS_HEND0A_Pos 12 +#define PWMG_IRS_HEND0A_Msk (0x01 << PWMG_IRS_HEND0A_Pos) +#define PWMG_IRS_HEND0B_Pos 13 +#define PWMG_IRS_HEND0B_Msk (0x01 << PWMG_IRS_HEND0B_Pos) +#define PWMG_IRS_HEND1A_Pos 14 +#define PWMG_IRS_HEND1A_Msk (0x01 << PWMG_IRS_HEND1A_Pos) +#define PWMG_IRS_HEND1B_Pos 15 +#define PWMG_IRS_HEND1B_Msk (0x01 << PWMG_IRS_HEND1B_Pos) +#define PWMG_IRS_HEND2A_Pos 16 +#define PWMG_IRS_HEND2A_Msk (0x01 << PWMG_IRS_HEND2A_Pos) +#define PWMG_IRS_HEND2B_Pos 17 +#define PWMG_IRS_HEND2B_Msk (0x01 << PWMG_IRS_HEND2B_Pos) +#define PWMG_IRS_HEND3A_Pos 18 +#define PWMG_IRS_HEND3A_Msk (0x01 << PWMG_IRS_HEND3A_Pos) +#define PWMG_IRS_HEND3B_Pos 19 +#define PWMG_IRS_HEND3B_Msk (0x01 << PWMG_IRS_HEND3B_Pos) +#define PWMG_IRS_HEND4A_Pos 20 +#define PWMG_IRS_HEND4A_Msk (0x01 << PWMG_IRS_HEND4A_Pos) +#define PWMG_IRS_HEND4B_Pos 21 +#define PWMG_IRS_HEND4B_Msk (0x01 << PWMG_IRS_HEND4B_Pos) +#define PWMG_IRS_HEND5A_Pos 22 +#define PWMG_IRS_HEND5A_Msk (0x01 << PWMG_IRS_HEND5A_Pos) +#define PWMG_IRS_HEND5B_Pos 23 +#define PWMG_IRS_HEND5B_Msk (0x01 << PWMG_IRS_HEND5B_Pos) +#define PWMG_IRS_HALT_Pos 24 +#define PWMG_IRS_HALT_Msk (0x01 << PWMG_IRS_HALT_Pos) + +typedef struct +{ + __IO uint32_t EN; //[0] ENABLE + + __IO uint32_t IE; //只有为1时，IF[CHx]在DMA传输结束时才能变为1，否则将一直保持在0 + + __IO uint32_t IM; //当为1时，即使IF[CHx]为1，dma_int也不会因此变1 + + __IO uint32_t IF; //写1清零 + + uint32_t RESERVED[12]; + + struct + { + __IO uint32_t CR; + + __IO uint32_t AM; //Adress Mode + + __IO uint32_t SRC; + + __IO uint32_t SRCSGADDR1; //只在Scatter Gather模式下使用 + + __IO uint32_t SRCSGADDR2; //只在Scatter Gather模式下使用 + + __IO uint32_t SRCSGADDR3; //只在Scatter Gather模式下使用 + + __IO uint32_t SRCSGLEN; //只在Scatter Gather模式下使用 + + __IO uint32_t DST; + + __IO uint32_t DSTSGADDR1; //只在Scatter Gather模式下使用 + + __IO uint32_t DSTSGADDR2; //只在Scatter Gather模式下使用 + + __IO uint32_t DSTSGADDR3; //只在Scatter Gather模式下使用 + + __IO uint32_t DSTSGLEN; //只在Scatter Gather模式下使用 + + uint32_t RESERVED[4]; + } CH[3]; +} DMA_TypeDef; + +#define DMA_IE_CH0_Pos 0 +#define DMA_IE_CH0_Msk (0x01 << DMA_IE_CH0_Pos) +#define DMA_IE_CH1_Pos 1 +#define DMA_IE_CH1_Msk (0x01 << DMA_IE_CH1_Pos) +#define DMA_IE_CH2_Pos 2 +#define DMA_IE_CH2_Msk (0x01 << DMA_IE_CH2_Pos) +#define DMA_IE_CH3_Pos 3 +#define DMA_IE_CH3_Msk (0x01 << DMA_IE_CH3_Pos) +#define DMA_IE_CH4_Pos 4 +#define DMA_IE_CH4_Msk (0x01 << DMA_IE_CH4_Pos) +#define DMA_IE_CH5_Pos 5 +#define DMA_IE_CH5_Msk (0x01 << DMA_IE_CH5_Pos) +#define DMA_IE_CH6_Pos 6 +#define DMA_IE_CH6_Msk (0x01 << DMA_IE_CH6_Pos) +#define DMA_IE_CH7_Pos 7 +#define DMA_IE_CH7_Msk (0x01 << DMA_IE_CH7_Pos) + +#define DMA_IM_CH0_Pos 0 +#define DMA_IM_CH0_Msk (0x01 << DMA_IM_CH0_Pos) +#define DMA_IM_CH1_Pos 1 +#define DMA_IM_CH1_Msk (0x01 << DMA_IM_CH1_Pos) +#define DMA_IM_CH2_Pos 2 +#define DMA_IM_CH2_Msk (0x01 << DMA_IM_CH2_Pos) +#define DMA_IM_CH3_Pos 3 +#define DMA_IM_CH3_Msk (0x01 << DMA_IM_CH3_Pos) +#define DMA_IM_CH4_Pos 4 +#define DMA_IM_CH4_Msk (0x01 << DMA_IM_CH4_Pos) +#define DMA_IM_CH5_Pos 5 +#define DMA_IM_CH5_Msk (0x01 << DMA_IM_CH5_Pos) +#define DMA_IM_CH6_Pos 6 +#define DMA_IM_CH6_Msk (0x01 << DMA_IM_CH6_Pos) +#define DMA_IM_CH7_Pos 7 +#define DMA_IM_CH7_Msk (0x01 << DMA_IM_CH7_Pos) + +#define DMA_IF_CH0_Pos 0 +#define DMA_IF_CH0_Msk (0x01 << DMA_IF_CH0_Pos) +#define DMA_IF_CH1_Pos 1 +#define DMA_IF_CH1_Msk (0x01 << DMA_IF_CH1_Pos) +#define DMA_IF_CH2_Pos 2 +#define DMA_IF_CH2_Msk (0x01 << DMA_IF_CH2_Pos) +#define DMA_IF_CH3_Pos 3 +#define DMA_IF_CH3_Msk (0x01 << DMA_IF_CH3_Pos) +#define DMA_IF_CH4_Pos 4 +#define DMA_IF_CH4_Msk (0x01 << DMA_IF_CH4_Pos) +#define DMA_IF_CH5_Pos 5 +#define DMA_IF_CH5_Msk (0x01 << DMA_IF_CH5_Pos) +#define DMA_IF_CH6_Pos 6 +#define DMA_IF_CH6_Msk (0x01 << DMA_IF_CH6_Pos) +#define DMA_IF_CH7_Pos 7 +#define DMA_IF_CH7_Msk (0x01 << DMA_IF_CH7_Pos) + +#define DMA_CR_LEN_Pos 0 //此通道传输总长度，0对应1字节，最大4096字节 +#define DMA_CR_LEN_Msk (0xFFF << DMA_CR_LEN_Pos) +#define DMA_CR_RXEN_Pos 16 +#define DMA_CR_RXEN_Msk (0x01 << DMA_CR_RXEN_Pos) +#define DMA_CR_TXEN_Pos 17 +#define DMA_CR_TXEN_Msk (0x01 << DMA_CR_TXEN_Pos) +#define DMA_CR_AUTORE_Pos 18 //Auto Restart, 通道在传输完成后，是否自动重新启动 +#define DMA_CR_AUTORE_Msk (0x01 << DMA_CR_AUTORE_Pos) + +#define DMA_AM_SRCAM_Pos 0 //Address Mode 0 地址固定 1 地址递增 2 scatter gather模式 +#define DMA_AM_SRCAM_Msk (0x03 << DMA_AM_SRCAM_Pos) +#define DMA_AM_DSTAM_Pos 8 +#define DMA_AM_DSTAM_Msk (0x03 << DMA_AM_DSTAM_Pos) +#define DMA_AM_BURST_Pos 16 +#define DMA_AM_BURST_Msk (0x01 << DMA_AM_BURST_Pos) + +typedef struct +{ + __IO uint32_t CR; //Control Register + + __O uint32_t CMD; //Command Register + + __I uint32_t SR; //Status Register + + __I uint32_t IF; //Interrupt Flag + + __IO uint32_t IE; //Interrupt Enable + + uint32_t RESERVED; + + __IO uint32_t BT0; //Bit Time Register 0 + + __IO uint32_t BT1; //Bit Time Register 1 + + uint32_t RESERVED2[3]; + + __I uint32_t ALC; //Arbitration Lost Capture, 仲裁丢失捕捉 + + __I uint32_t ECC; //Error code capture, 错误代码捕捉 + + __IO uint32_t EWLIM; //Error Warning Limit, 错误报警限制 + + __IO uint32_t RXERR; //RX错误计数 + + __IO uint32_t TXERR; //TX错误计数 + + union { + struct + { //在复位时可读写，正常工作模式下不可访问 + __IO uint32_t ACR[4]; //Acceptance Check Register, 验收寄存器 + + __IO uint32_t AMR[4]; //Acceptance Mask Register, 验收屏蔽寄存器；对应位写0，ID必须和验收寄存器匹配 + + uint32_t RESERVED[5]; + } FILTER; + + union { //在正常工作模式下可读写，复位时不可访问 + struct + { + __O uint32_t INFO; + + __O uint32_t DATA[12]; + } TXFRAME; + + struct + { + __I uint32_t INFO; + + __I uint32_t DATA[12]; + } RXFRAME; + }; + }; + + __I uint32_t RMCNT; //Receive Message Count + + uint32_t RESERVED3[66]; + + struct + { //TXFRAME的读接口 + __I uint32_t INFO; + + __I uint32_t DATA[12]; + } TXFRAME_R; +} CAN_TypeDef; + +#define CAN_CR_RST_Pos 0 +#define CAN_CR_RST_Msk (0x01 << CAN_CR_RST_Pos) +#define CAN_CR_LOM_Pos 1 //Listen Only Mode +#define CAN_CR_LOM_Msk (0x01 << CAN_CR_LOM_Pos) +#define CAN_CR_STM_Pos 2 //Self Test Mode, 此模式下即使没有应答，CAN控制器也可以成功发送 +#define CAN_CR_STM_Msk (0x01 << CAN_CR_STM_Pos) +#define CAN_CR_AFM_Pos 3 //Acceptance Filter Mode, 1 单个验收滤波器（32位） 0 两个验收滤波器（16位） +#define CAN_CR_AFM_Msk (0x01 << CAN_CR_AFM_Pos) +#define CAN_CR_SLEEP_Pos 4 //写1进入睡眠模式，有总线活动或中断时唤醒并自动清零此位 +#define CAN_CR_SLEEP_Msk (0x01 << CAN_CR_SLEEP_Pos) + +#define CAN_CMD_TXREQ_Pos 0 //Transmission Request +#define CAN_CMD_TXREQ_Msk (0x01 << CAN_CMD_TXREQ_Pos) +#define CAN_CMD_ABTTX_Pos 1 //Abort Transmission +#define CAN_CMD_ABTTX_Msk (0x01 << CAN_CMD_ABTTX_Pos) +#define CAN_CMD_RRB_Pos 2 //Release Receive Buffer +#define CAN_CMD_RRB_Msk (0x01 << CAN_CMD_RRB_Pos) +#define CAN_CMD_CLROV_Pos 3 //Clear Data Overrun +#define CAN_CMD_CLROV_Msk (0x01 << CAN_CMD_CLROV_Pos) +#define CAN_CMD_SRR_Pos 4 //Self Reception Request +#define CAN_CMD_SRR_Msk (0x01 << CAN_CMD_SRR_Pos) + +#define CAN_SR_RXDA_Pos 0 //Receive Data Available，接收FIFO中有完整消息可以读取 +#define CAN_SR_RXDA_Msk (0x01 << CAN_SR_RXDA_Pos) +#define CAN_SR_RXOV_Pos 1 //Receive FIFO Overrun，新接收的信息由于接收FIFO已满而丢掉 +#define CAN_SR_RXOV_Msk (0x01 << CAN_SR_RXOV_Pos) +#define CAN_SR_TXBR_Pos 2 //Transmit Buffer Release，0 正在处理前面的发送，现在不能写新的消息 1 可以写入新的消息发送 +#define CAN_SR_TXBR_Msk (0x01 << CAN_SR_TXBR_Pos) +#define CAN_SR_TXOK_Pos 3 //Transmit OK，successfully completed +#define CAN_SR_TXOK_Msk (0x01 << CAN_SR_TXOK_Pos) +#define CAN_SR_RXBUSY_Pos 4 //Receive Busy，正在接收 +#define CAN_SR_RXBUSY_Msk (0x01 << CAN_SR_RXBUSY_Pos) +#define CAN_SR_TXBUSY_Pos 5 //Transmit Busy，正在发送 +#define CAN_SR_TXBUSY_Msk (0x01 << CAN_SR_TXBUSY_Pos) +#define CAN_SR_ERRWARN_Pos 6 //1 至少一个错误计数器达到 Warning Limit +#define CAN_SR_ERRWARN_Msk (0x01 << CAN_SR_ERRWARN_Pos) +#define CAN_SR_BUSOFF_Pos 7 //1 CAN 控制器处于总线关闭状态，没有参与到总线活动 +#define CAN_SR_BUSOFF_Msk (0x01 << CAN_SR_BUSOFF_Pos) + +#define CAN_IF_RXDA_Pos 0 //IF.RXDA = SR.RXDA & IE.RXDA +#define CAN_IF_RXDA_Msk (0x01 << CAN_IF_RXDA_Pos) +#define CAN_IF_TXBR_Pos 1 //当IE.TXBR=1时，SR.TXBR由0变成1将置位此位 +#define CAN_IF_TXBR_Msk (0x01 << CAN_IF_TXBR_Pos) +#define CAN_IF_ERRWARN_Pos 2 //当IE.ERRWARN=1时，SR.ERRWARN或SR.BUSOFF 0-to-1 或 1-to-0将置位此位 +#define CAN_IF_ERRWARN_Msk (0x01 << CAN_IF_ERRWARN_Pos) +#define CAN_IF_RXOV_Pos 3 //IF.RXOV = SR.RXOV & IE.RXOV +#define CAN_IF_RXOV_Msk (0x01 << CAN_IF_RXOV_Pos) +#define CAN_IF_WKUP_Pos 4 //当IE.WKUP=1时，在睡眠模式下的CAN控制器检测到总线活动时硬件置位 +#define CAN_IF_WKUP_Msk (0x01 << CAN_IF_WKUP_Pos) +#define CAN_IF_ERRPASS_Pos 5 // +#define CAN_IF_ERRPASS_Msk (0x01 << CAN_IF_ERRPASS_Pos) +#define CAN_IF_ARBLOST_Pos 6 //Arbitration Lost，当IE.ARBLOST=1时，CAN控制器丢失仲裁变成接收方时硬件置位 +#define CAN_IF_ARBLOST_Msk (0x01 << CAN_IF_ARBLOST_Pos) +#define CAN_IF_BUSERR_Pos 7 //当IE.BUSERR=1时，CAN控制器检测到总线错误时硬件置位 +#define CAN_IF_BUSERR_Msk (0x01 << CAN_IF_BUSERR_Pos) + +#define CAN_IE_RXDA_Pos 0 +#define CAN_IE_RXDA_Msk (0x01 << CAN_IE_RXDA_Pos) +#define CAN_IE_TXBR_Pos 1 +#define CAN_IE_TXBR_Msk (0x01 << CAN_IE_TXBR_Pos) +#define CAN_IE_ERRWARN_Pos 2 +#define CAN_IE_ERRWARN_Msk (0x01 << CAN_IE_ERRWARN_Pos) +#define CAN_IE_RXOV_Pos 3 +#define CAN_IE_RXOV_Msk (0x01 << CAN_IE_RXOV_Pos) +#define CAN_IE_WKUP_Pos 4 +#define CAN_IE_WKUP_Msk (0x01 << CAN_IE_WKUP_Pos) +#define CAN_IE_ERRPASS_Pos 5 +#define CAN_IE_ERRPASS_Msk (0x01 << CAN_IE_ERRPASS_Pos) +#define CAN_IE_ARBLOST_Pos 6 +#define CAN_IE_ARBLOST_Msk (0x01 << CAN_IE_ARBLOST_Pos) +#define CAN_IE_BUSERR_Pos 7 +#define CAN_IE_BUSERR_Msk (0x01 << CAN_IE_BUSERR_Pos) + +#define CAN_BT0_BRP_Pos 0 //Baud Rate Prescaler，CAN时间单位=2*Tsysclk*(BRP+1) +#define CAN_BT0_BRP_Msk (0x3F << CAN_BT0_BRP_Pos) +#define CAN_BT0_SJW_Pos 6 //Synchronization Jump Width +#define CAN_BT0_SJW_Msk (0x03 << CAN_BT0_SJW_Pos) + +#define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CAN时间单位 * (TSEG1+1) +#define CAN_BT1_TSEG1_Msk (0x0F << CAN_BT1_TSEG1_Pos) +#define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CAN时间单位 * (TSEG2+1) +#define CAN_BT1_TSEG2_Msk (0x07 << CAN_BT1_TSEG2_Pos) +#define CAN_BT1_SAM_Pos 7 //采样次数 0: sampled once 1: sampled three times +#define CAN_BT1_SAM_Msk (0x01 << CAN_BT1_SAM_Pos) + +#define CAN_ECC_SEGCODE_Pos 0 //Segment Code +#define CAN_ECC_SEGCODE_Msk (0x1F << CAN_ECC_SEGCODE_Pos) +#define CAN_ECC_DIR_Pos 5 //0 error occurred during transmission 1 during reception +#define CAN_ECC_DIR_Msk (0x01 << CAN_ECC_DIR_Pos) +#define CAN_ECC_ERRCODE_Pos 6 //Error Code：0 Bit error 1 Form error 2 Stuff error 3 other error +#define CAN_ECC_ERRCODE_Msk (0x03 << CAN_ECC_ERRCODE_Pos) + +#define CAN_INFO_DLC_Pos 0 //Data Length Control +#define CAN_INFO_DLC_Msk (0x0F << CAN_INFO_DLC_Pos) +#define CAN_INFO_RTR_Pos 6 //Remote Frame，1 远程帧 0 数据帧 +#define CAN_INFO_RTR_Msk (0x01 << CAN_INFO_RTR_Pos) +#define CAN_INFO_FF_Pos 7 //Frame Format，0 标准帧格式 1 扩展帧格式 +#define CAN_INFO_FF_Msk (0x01 << CAN_INFO_FF_Pos) + +typedef struct +{ + __IO uint32_t IE; //[0] 为0的时候，IF[0]维持为0 + + __IO uint32_t IF; //[0] 当完成指定长度的数据传输时置1，写1清零 + + __IO uint32_t IM; //[0] 当该寄存器为1时，LCDC的中断不会输出给系统的中断控制寄存器 + + __IO uint32_t START; + + __IO uint32_t SRCADDR; //数据源地址寄存器，必须字对齐（即地址的低2位必须是0） + + __IO uint32_t CR0; + + __IO uint32_t CR1; + + __IO uint32_t PRECMDV; //在MPU接口中，发送数据前，RS拉低的那一拍，数据总线上的值 +} LCD_TypeDef; + +#define LCD_START_MPUEN_Pos 0 //0 RGB接口 1 MPU接口 +#define LCD_START_MPUEN_Msk (0x01 << LCD_START_MPUEN_Pos) +#define LCD_START_GO_Pos 1 //写1开始传输数据，数据传输结束后自动清零 +#define LCD_START_GO_Msk (0x01 << LCD_START_GO_Pos) +#define LCD_START_BURST_Pos 2 +#define LCD_START_BURST_Msk (0x01 << LCD_START_BURST_Pos) + +#define LCD_CR0_VPIX_Pos 0 //当portrait为0时，表示垂直方向的像素个数，0表示1个，最大为767 \ + //当portrait为1时，表示水平方向的像素个数，0表示1个，最大为767 +#define LCD_CR0_VPIX_Msk (0x3FF << LCD_CR0_VPIX_Pos) +#define LCD_CR0_HPIX_Pos 10 //当portrait为0时，表示水平方向的像素个数，0表示1个，最大为1023 \ + //当portrait为1时，表示垂直方向的像素个数，0表示1个，最大为1023 +#define LCD_CR0_HPIX_Msk (0x3FF << LCD_CR0_HPIX_Pos) +#define LCD_CR0_DCLK_Pos 20 //0 DOTCLK一直翻转 1 DOTCLK在空闲时停在1 +#define LCD_CR0_DCLK_Msk (0x01 << LCD_CR0_DCLK_Pos) +#define LCD_CR0_HLOW_Pos 21 //输出HSYNC低电平持续多少个DOTCLK周期，0表示1个周期 +#define LCD_CR0_HLOW_Msk (0x03 << LCD_CR0_HLOW_Pos) + +#define LCD_CR1_VFP_Pos 1 +#define LCD_CR1_VFP_Msk (0x07 << LCD_CR1_VFP_Pos) +#define LCD_CR1_VBP_Pos 4 +#define LCD_CR1_VBP_Msk (0x1F << LCD_CR1_VBP_Pos) +#define LCD_CR1_HFP_Pos 9 +#define LCD_CR1_HFP_Msk (0x1F << LCD_CR1_HFP_Pos) +#define LCD_CR1_HBP_Pos 14 +#define LCD_CR1_HBP_Msk (0x7F << LCD_CR1_HBP_Pos) +#define LCD_CR1_DCLKDIV_Pos 21 //DOTCLK相对于模块时钟的分频比，0表示2分频，1表示4分频 ... +#define LCD_CR1_DCLKDIV_Msk (0x1F << LCD_CR1_DCLKDIV_Pos) +#define LCD_CR1_DCLKINV_Pos 26 //1 输出DOTCLK反向，应用于用DOTCLK下降沿采样数据的屏 +#define LCD_CR1_DCLKINV_Msk (0x01 << LCD_CR1_DCLKINV_Pos) + +typedef struct +{ + __IO uint32_t DMA_MEM_ADDR; + + __IO uint32_t BLK; //Block Size and Count + + __IO uint32_t ARG; //Argument + + __IO uint32_t CMD; //Command + + __IO uint32_t RESP[4]; //Response + + __IO uint32_t DATA; + + __IO uint32_t STAT; + + __IO uint32_t CR1; + + __IO uint32_t CR2; + + __IO uint32_t IF; + + __IO uint32_t IFE; //Interrupt Flag Enable + + __IO uint32_t IE; //Interrupt Enalbe + + __IO uint32_t CMD12ERR; + + __IO uint32_t INFO; + + __IO uint32_t MAXCURR; +} SDIO_TypeDef; + +#define SDIO_BLK_SIZE_Pos 0 //0x200 512字节 0x400 1024字节 0x800 2048字节 +#define SDIO_BLK_SIZE_Msk (0xFFF << SDIO_BLK_SIZE_Pos) +#define SDIO_BLK_COUNT_Pos 16 //0 Stop Transfer 1 1块 2 2块 ... ... +#define SDIO_BLK_COUNT_Msk (0xFFF << SDIO_BLK_COUNT_Pos) + +#define SDIO_CMD_DMAEN_Pos 0 +#define SDIO_CMD_DMAEN_Msk (0x01 << SDIO_CMD_DMAEN_Pos) +#define SDIO_CMD_BLKCNTEN_Pos 1 +#define SDIO_CMD_BLKCNTEN_Msk (0x01 << SDIO_CMD_BLKCNTEN_Pos) +#define SDIO_CMD_AUTOCMD12_Pos 2 +#define SDIO_CMD_AUTOCMD12_Msk (0x01 << SDIO_CMD_AUTOCMD12_Pos) +#define SDIO_CMD_DIRREAD_Pos 4 //0 Write, Host to Card 1 Read, Card to Host +#define SDIO_CMD_DIRREAD_Msk (0x01 << SDIO_CMD_DIRREAD_Pos) +#define SDIO_CMD_MULTBLK_Pos 5 //0 Single Block 1 Multiple Block +#define SDIO_CMD_MULTBLK_Msk (0x01 << SDIO_CMD_MULTBLK_Pos) +#define SDIO_CMD_RESPTYPE_Pos 16 //响应类型，0 无响应 1 136位响应 2 48位响应 3 48位响应，Busy after response +#define SDIO_CMD_RESPTYPE_Msk (0x03 << SDIO_CMD_RESPTYPE_Pos) +#define SDIO_CMD_CRCCHECK_Pos 19 //Command CRC Check Enable +#define SDIO_CMD_CRCCHECK_Msk (0x01 << SDIO_CMD_CRCCHECK_Pos) +#define SDIO_CMD_IDXCHECK_Pos 20 //Command Index Check Enable +#define SDIO_CMD_IDXCHECK_Msk (0x01 << SDIO_CMD_IDXCHECK_Pos) +#define SDIO_CMD_HAVEDATA_Pos 21 //0 No Data Present 1 Data Present +#define SDIO_CMD_HAVEDATA_Msk (0x01 << SDIO_CMD_HAVEDATA_Pos) +#define SDIO_CMD_CMDTYPE_Pos 22 //0 NORMAL 1 SUSPEND 2 RESUME 3 ABORT +#define SDIO_CMD_CMDTYPE_Msk (0x03 << SDIO_CMD_CMDTYPE_Pos) +#define SDIO_CMD_CMDINDX_Pos 24 //Command Index，CMD0-63、ACMD0-63 +#define SDIO_CMD_CMDINDX_Msk (0x3F << SDIO_CMD_CMDINDX_Pos) + +#define SDIO_CR1_4BIT_Pos 1 //1 4 bit mode 0 1 bit mode +#define SDIO_CR1_4BIT_Msk (0x01 << SDIO_CR1_4BIT_Pos) +#define SDIO_CR1_8BIT_Pos 5 //1 8 bit mode is selected 0 8 bit mode is not selected +#define SDIO_CR1_8BIT_Msk (0x01 << SDIO_CR1_8BIT_Pos) +#define SDIO_CR1_CDBIT_Pos 6 //0 No Card 1 Card Inserted +#define SDIO_CR1_CDBIT_Msk (0x01 << SDIO_CR1_CDBIT_Pos) +#define SDIO_CR1_CDSRC_Pos 7 //Card Detect Source, 1 CR1.CDBIT位 0 SD_Detect引脚 +#define SDIO_CR1_CDSRC_Msk (0x01 << SDIO_CR1_CDSRC_Pos) +#define SDIO_CR1_PWRON_Pos 8 //1 Power on 0 Power off +#define SDIO_CR1_PWRON_Msk (0x01 << SDIO_CR1_PWRON_Pos) +#define SDIO_CR1_VOLT_Pos 9 //7 3.3V 6 3.0V 5 1.8V +#define SDIO_CR1_VOLT_Msk (0x07 << SDIO_CR1_VOLT_Pos) + +#define SDIO_CR2_CLKEN_Pos 0 //Internal Clock Enable +#define SDIO_CR2_CLKEN_Msk (0x01 << SDIO_CR2_CLKEN_Pos) +#define SDIO_CR2_CLKRDY_Pos 1 //Internal Clock Stable/Ready +#define SDIO_CR2_CLKRDY_Msk (0x01 << SDIO_CR2_CLKRDY_Pos) +#define SDIO_CR2_SDCLKEN_Pos 2 //SDCLK Enable +#define SDIO_CR2_SDCLKEN_Msk (0x01 << SDIO_CR2_SDCLKEN_Pos) +#define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 不分频 0x01 2分频 0x02 4分频 0x04 8分频 0x08 16分频 ... 0x80 256分频 +#define SDIO_CR2_SDCLKDIV_Msk (0xFF << SDIO_CR2_SDCLKDIV_Pos) +#define SDIO_CR2_TIMEOUT_Pos 16 //0 TMCLK*2^13 1 TMCLK*2^14 ... 14 TMCLK*2^27 +#define SDIO_CR2_TIMEOUT_Msk (0x0F << SDIO_CR2_TIMEOUT_Pos) +#define SDIO_CR2_RSTALL_Pos 24 //Software Reset for All +#define SDIO_CR2_RSTALL_Msk (0x01 << SDIO_CR2_RSTALL_Pos) +#define SDIO_CR2_RSTCMD_Pos 25 //Software Reset for CMD Line +#define SDIO_CR2_RSTCMD_Msk (0x01 << SDIO_CR2_RSTCMD_Pos) +#define SDIO_CR2_RSTDAT_Pos 26 //Software Reset for DAT Line +#define SDIO_CR2_RSTDAT_Msk (0x01 << SDIO_CR2_RSTDAT_Pos) + +#define SDIO_IF_CMDDONE_Pos 0 +#define SDIO_IF_CMDDONE_Msk (0x01 << SDIO_IF_CMDDONE_Pos) +#define SDIO_IF_TRXDONE_Pos 1 +#define SDIO_IF_TRXDONE_Msk (0x01 << SDIO_IF_TRXDONE_Pos) +#define SDIO_IF_BLKGAP_Pos 2 +#define SDIO_IF_BLKGAP_Msk (0x01 << SDIO_IF_BLKGAP_Pos) +#define SDIO_IF_DMADONE_Pos 3 +#define SDIO_IF_DMADONE_Msk (0x01 << SDIO_IF_DMADONE_Pos) +#define SDIO_IF_BUFWRRDY_Pos 4 +#define SDIO_IF_BUFWRRDY_Msk (0x01 << SDIO_IF_BUFWRRDY_Pos) +#define SDIO_IF_BUFRDRDY_Pos 5 +#define SDIO_IF_BUFRDRDY_Msk (0x01 << SDIO_IF_BUFRDRDY_Pos) +#define SDIO_IF_CARDINSR_Pos 6 +#define SDIO_IF_CARDINSR_Msk (0x01 << SDIO_IF_CARDINSR_Pos) +#define SDIO_IF_CARDRMOV_Pos 7 +#define SDIO_IF_CARDRMOV_Msk (0x01 << SDIO_IF_CARDRMOV_Pos) +#define SDIO_IF_CARD_Pos 8 +#define SDIO_IF_CARD_Msk (0x01 << SDIO_IF_CARD_Pos) +#define SDIO_IF_ERROR_Pos 15 +#define SDIO_IF_ERROR_Msk (0x01 << SDIO_IF_ERROR_Pos) +#define SDIO_IF_CMDTIMEOUT_Pos 16 +#define SDIO_IF_CMDTIMEOUT_Msk (0x01 << SDIO_IF_CMDTIMEOUT_Pos) +#define SDIO_IF_CMDCRCERR_Pos 17 +#define SDIO_IF_CMDCRCERR_Msk (0x01 << SDIO_IF_CMDCRCERR_Pos) +#define SDIO_IF_CMDENDERR_Pos 18 +#define SDIO_IF_CMDENDERR_Msk (0x01 << SDIO_IF_CMDENDCERR_Pos) +#define SDIO_IF_CMDIDXERR_Pos 19 +#define SDIO_IF_CMDIDXERR_Msk (0x01 << SDIO_IF_CMDIDXCERR_Pos) +#define SDIO_IF_DATTIMEOUT_Pos 20 +#define SDIO_IF_DATTIMEOUT_Msk (0x01 << SDIO_IF_DATTIMEOUT_Pos) +#define SDIO_IF_DATCRCERR_Pos 21 +#define SDIO_IF_DATCRCERR_Msk (0x01 << SDIO_IF_DATCRCERR_Pos) +#define SDIO_IF_DATENDERR_Pos 22 +#define SDIO_IF_DATENDERR_Msk (0x01 << SDIO_IF_DATENDCERR_Pos) +#define SDIO_IF_CURLIMERR_Pos 23 +#define SDIO_IF_CURLIMERR_Msk (0x01 << SDIO_IF_CURLIMERR_Pos) +#define SDIO_IF_CMD12ERR_Pos 24 +#define SDIO_IF_CMD12ERR_Msk (0x01 << SDIO_IF_CMD12ERR_Pos) +#define SDIO_IF_DMAERR_Pos 25 +#define SDIO_IF_DMAERR_Msk (0x01 << SDIO_IF_DMAERR_Pos) +#define SDIO_IF_RESPERR_Pos 28 +#define SDIO_IF_RESPERR_Msk (0x01 << SDIO_IF_RESPERR_Pos) + +#define SDIO_IE_CMDDONE_Pos 0 //Command Complete Status Enable +#define SDIO_IE_CMDDONE_Msk (0x01 << SDIO_IE_CMDDONE_Pos) +#define SDIO_IE_TRXDONE_Pos 1 //Transfer Complete Status Enable +#define SDIO_IE_TRXDONE_Msk (0x01 << SDIO_IE_TRXDONE_Pos) +#define SDIO_IE_BLKGAP_Pos 2 //Block Gap Event Status Enable +#define SDIO_IE_BLKGAP_Msk (0x01 << SDIO_IE_BLKGAP_Pos) +#define SDIO_IE_DMADONE_Pos 3 //DMA Interrupt Status Enable +#define SDIO_IE_DMADONE_Msk (0x01 << SDIO_IE_DMADONE_Pos) +#define SDIO_IE_BUFWRRDY_Pos 4 //Buffer Write Ready Status Enable +#define SDIO_IE_BUFWRRDY_Msk (0x01 << SDIO_IE_BUFWRRDY_Pos) +#define SDIO_IE_BUFRDRDY_Pos 5 //Buffer Read Ready Status Enable +#define SDIO_IE_BUFRDRDY_Msk (0x01 << SDIO_IE_BUFRDRDY_Pos) +#define SDIO_IE_CARDINSR_Pos 6 //Card Insertion Status Enable +#define SDIO_IE_CARDINSR_Msk (0x01 << SDIO_IE_CARDINSR_Pos) +#define SDIO_IE_CARDRMOV_Pos 7 //Card Removal Status Enable +#define SDIO_IE_CARDRMOV_Msk (0x01 << SDIO_IE_CARDRMOV_Pos) +#define SDIO_IE_CARD_Pos 8 +#define SDIO_IE_CARD_Msk (0x01 << SDIO_IE_CARD_Pos) +#define SDIO_IE_CMDTIMEOUT_Pos 16 //Command Timeout Error Status Enable +#define SDIO_IE_CMDTIMEOUT_Msk (0x01 << SDIO_IE_CMDTIMEOUT_Pos) +#define SDIO_IE_CMDCRCERR_Pos 17 //Command CRC Error Status Enable +#define SDIO_IE_CMDCRCERR_Msk (0x01 << SDIO_IE_CMDCRCERR_Pos) +#define SDIO_IE_CMDENDERR_Pos 18 //Command End Bit Error Status Enable +#define SDIO_IE_CMDENDERR_Msk (0x01 << SDIO_IE_CMDENDCERR_Pos) +#define SDIO_IE_CMDIDXERR_Pos 19 //Command Index Error Status Enable +#define SDIO_IE_CMDIDXERR_Msk (0x01 << SDIO_IE_CMDIDXCERR_Pos) +#define SDIO_IE_DATTIMEOUT_Pos 20 //Data Timeout Error Status Enable +#define SDIO_IE_DATTIMEOUT_Msk (0x01 << SDIO_IE_DATTIMEOUT_Pos) +#define SDIO_IE_DATCRCERR_Pos 21 //Data CRC Error Status Enable +#define SDIO_IE_DATCRCERR_Msk (0x01 << SDIO_IE_DATCRCERR_Pos) +#define SDIO_IE_DATENDERR_Pos 22 //Data End Bit Error Status Enable +#define SDIO_IE_DATENDERR_Msk (0x01 << SDIO_IE_DATENDCERR_Pos) +#define SDIO_IE_CURLIMERR_Pos 23 //Current Limit Error Status Enable +#define SDIO_IE_CURLIMERR_Msk (0x01 << SDIO_IE_CURLIMERR_Pos) +#define SDIO_IE_CMD12ERR_Pos 24 //Auto CMD12 Error Status Enable +#define SDIO_IE_CMD12ERR_Msk (0x01 << SDIO_IE_CMD12ERR_Pos) +#define SDIO_IE_DMAERR_Pos 25 //ADMA Error Status Enable +#define SDIO_IE_DMAERR_Msk (0x01 << SDIO_IE_DMAERR_Pos) +#define SDIO_IE_RESPERR_Pos 28 //Target Response Error Status Enable +#define SDIO_IE_RESPERR_Msk (0x01 << SDIO_IE_RESPERR_Pos) + +#define SDIO_IM_CMDDONE_Pos 0 +#define SDIO_IM_CMDDONE_Msk (0x01 << SDIO_IM_CMDDONE_Pos) +#define SDIO_IM_TRXDONE_Pos 1 +#define SDIO_IM_TRXDONE_Msk (0x01 << SDIO_IM_TRXDONE_Pos) +#define SDIO_IM_BLKGAP_Pos 2 +#define SDIO_IM_BLKGAP_Msk (0x01 << SDIO_IM_BLKGAP_Pos) +#define SDIO_IM_DMADONE_Pos 3 +#define SDIO_IM_DMADONE_Msk (0x01 << SDIO_IM_DMADONE_Pos) +#define SDIO_IM_BUFWRRDY_Pos 4 +#define SDIO_IM_BUFWRRDY_Msk (0x01 << SDIO_IM_BUFWRRDY_Pos) +#define SDIO_IM_BUFRDRDY_Pos 5 +#define SDIO_IM_BUFRDRDY_Msk (0x01 << SDIO_IM_BUFRDRDY_Pos) +#define SDIO_IM_CARDINSR_Pos 6 +#define SDIO_IM_CARDINSR_Msk (0x01 << SDIO_IM_CARDINSR_Pos) +#define SDIO_IM_CARDRMOV_Pos 7 +#define SDIO_IM_CARDRMOV_Msk (0x01 << SDIO_IM_CARDRMOV_Pos) +#define SDIO_IM_CARD_Pos 8 +#define SDIO_IM_CARD_Msk (0x01 << SDIO_IM_CARD_Pos) +#define SDIO_IM_CMDTIMEOUT_Pos 16 +#define SDIO_IM_CMDTIMEOUT_Msk (0x01 << SDIO_IM_CMDTIMEOUT_Pos) +#define SDIO_IM_CMDCRCERR_Pos 17 +#define SDIO_IM_CMDCRCERR_Msk (0x01 << SDIO_IM_CMDCRCERR_Pos) +#define SDIO_IM_CMDENDERR_Pos 18 +#define SDIO_IM_CMDENDERR_Msk (0x01 << SDIO_IM_CMDENDCERR_Pos) +#define SDIO_IM_CMDIDXERR_Pos 19 +#define SDIO_IM_CMDIDXERR_Msk (0x01 << SDIO_IM_CMDIDXCERR_Pos) +#define SDIO_IM_DATTIMEOUT_Pos 20 +#define SDIO_IM_DATTIMEOUT_Msk (0x01 << SDIO_IM_DATTIMEOUT_Pos) +#define SDIO_IM_DATCRCERR_Pos 21 +#define SDIO_IM_DATCRCERR_Msk (0x01 << SDIO_IM_DATCRCERR_Pos) +#define SDIO_IM_DATENDERR_Pos 22 +#define SDIO_IM_DATENDERR_Msk (0x01 << SDIO_IM_DATENDCERR_Pos) +#define SDIO_IM_CURLIMERR_Pos 23 +#define SDIO_IM_CURLIMERR_Msk (0x01 << SDIO_IM_CURLIMERR_Pos) +#define SDIO_IM_CMD12ERR_Pos 24 +#define SDIO_IM_CMD12ERR_Msk (0x01 << SDIO_IM_CMD12ERR_Pos) +#define SDIO_IM_DMAERR_Pos 25 +#define SDIO_IM_DMAERR_Msk (0x01 << SDIO_IM_DMAERR_Pos) +#define SDIO_IM_RESPERR_Pos 28 +#define SDIO_IM_RESPERR_Msk (0x01 << SDIO_IM_RESPERR_Pos) + +typedef struct +{ + __IO uint32_t DATA; + __IO uint32_t ADDR; + __IO uint32_t _ERASE; //和mmcsd_cmd.h(59)名字冲突，这里修改为_ERASE + __IO uint32_t CACHE; + __IO uint32_t CFG0; + __IO uint32_t CFG1; + __IO uint32_t CFG2; + __IO uint32_t CFG3; + __IO uint32_t STAT; +} FLASH_Typedef; + +#define FLASH_ERASE_REQ_Pos 31 +#define FLASH_ERASE_REQ_Msk (0x01u << FLASH_ERASE_REQ_Pos) + +#define FLASH_CACHE_PROG_Pos 2 +#define FLASH_CACHE_PROG_Msk (0x01 << FLASH_CACHE_PROG_Pos) +#define FLASH_CACHE_CLEAR_Pos 3 +#define FLASH_CACHE_CLEAR_Msk (0x01 << FLASH_CACHE_CLEAR_Pos) + +#define FLASH_STAT_ERASE_GOING_Pos 0 +#define FLASH_STAT_ERASE_GOING_Msk (0X01 << FLASH_STAT_ERASE_GOING_Pos) +#define FLASH_STAT_PROG_GOING_Pos 1 +#define FLASH_STAT_PROG_GOING_Msk (0x01 << FLASH_STAT_PROG_GOING_Pos) +#define FALSH_STAT_FIFO_EMPTY_Pos 3 +#define FLASH_STAT_FIFO_EMPTY_Msk (0x01 << FALSH_STAT_FIFO_EMPTY_Pos) +#define FALSH_STAT_FIFO_FULL_Pos 4 +#define FLASH_STAT_FIFO_FULL_Msk (0x01 << FALSH_STAT_FIFO_FULL_Pos) + +typedef struct +{ + __IO uint32_t CR; +} SRAMC_TypeDef; + +#define SRAMC_CR_RWTIME_Pos 0 //读写操作持续多少个时钟周期。0表示1个时钟周期。最小设置为4 +#define SRAMC_CR_RWTIME_Msk (0x0F << SRAMC_CR_RWTIME_Pos) +#define SRAMC_CR_BYTEIF_Pos 4 //外部SRAM数据宽度，0 16位 1 8位 +#define SRAMC_CR_BYTEIF_Msk (0x01 << SRAMC_CR_BYTEIF_Pos) +#define SRAMC_CR_HBLBDIS_Pos 5 //1 ADDR[23:22]为地址线 0 ADDR[23]为高字节使能，ADDR[22]为低字节使能 +#define SRAMC_CR_HBLBDIS_Msk (0x01 << SRAMC_CR_HBLBDIS_Pos) + +typedef struct +{ + __IO uint32_t CR0; + + __IO uint32_t CR1; + + __IO uint32_t REFRESH; + + __IO uint32_t NOPNUM; //[15:0] 初始化完成后，在正常操作之前，发送多少个NOP命令 + + __IO uint32_t LATCH; + + __IO uint32_t REFDONE; //[0] Frefresh Done，上电初始化完成 +} SDRAMC_TypeDef; + +#define SDRAMC_CR0_BURSTLEN_Pos 0 //必须取2，表示Burst Length为4 +#define SDRAMC_CR0_BURSTLEN_Msk (0x07 << SDRAMC_CR0_BURSTLEN_Pos) +#define SDRAMC_CR0_CASDELAY_Pos 4 //CAS Latency， 2 2 3 3 +#define SDRAMC_CR0_CASDELAY_Msk (0x07 << SDRAMC_CR0_CASDELAY_Pos) + +#define SDRAMC_CR1_TRP_Pos 0 +#define SDRAMC_CR1_TRP_Msk (0x07 << SDRAMC_CR1_TRP_Pos) +#define SDRAMC_CR1_TRCD_Pos 3 +#define SDRAMC_CR1_TRCD_Msk (0x07 << SDRAMC_CR1_TRCD_Pos) +#define SDRAMC_CR1_TRC_Pos 6 +#define SDRAMC_CR1_TRC_Msk (0x0F << SDRAMC_CR1_TRC_Pos) +#define SDRAMC_CR1_TRAS_Pos 10 +#define SDRAMC_CR1_TRAS_Msk (0x07 << SDRAMC_CR1_TRAS_Pos) +#define SDRAMC_CR1_TRRD_Pos 13 +#define SDRAMC_CR1_TRRD_Msk (0x03 << SDRAMC_CR1_TRRD_Pos) +#define SDRAMC_CR1_TMRD_Pos 15 +#define SDRAMC_CR1_TMRD_Msk (0x07 << SDRAMC_CR1_TMRD_Pos) +#define SDRAMC_CR1_32BIT_Pos 18 //SDRAMC的接口数据位宽，1 32bit 0 16bit +#define SDRAMC_CR1_32BIT_Msk (0x01 << SDRAMC_CR1_32BIT_Pos) +#define SDRAMC_CR1_BANK_Pos 19 //SDRAM每个颗粒有几个bank，0 2 banks 1 4 banks +#define SDRAMC_CR1_BANK_Msk (0x01 << SDRAMC_CR1_BANK_Pos) +#define SDRAMC_CR1_CELL32BIT_Pos 20 //SDRAM颗粒的位宽，1 32bit 0 16bit +#define SDRAMC_CR1_CELL32BIT_Msk (0x01 << SDRAMC_CR1_CELL32BIT_Pos) +#define SDRAMC_CR1_CELLSIZE_Pos 21 //SDRAM颗粒的容量，0 64Mb 1 128Mb 2 256Mb 3 16Mb +#define SDRAMC_CR1_CELLSIZE_Msk (0x03 << SDRAMC_CR1_CELLSIZE_Pos) +#define SDRAMC_CR1_HIGHSPEED_Pos 23 //当hclk大于100MHz时，这一位必须配置为1，否则为0 +#define SDRAMC_CR1_HIGHSPEED_Msk (0x01 << SDRAMC_CR1_HIGHSPEED_Pos) + +#define SDRAMC_REFRESH_RATE_Pos 0 +#define SDRAMC_REFRESH_RATE_Msk (0xFFF << SDRAMC_REFRESH_RATE_Pos) +#define SDRAMC_REFRESH_EN_Pos 12 +#define SDRAMC_REFRESH_EN_Msk (0x01 << SDRAMC_REFRESH_EN_Pos) + +#define SDRAMC_LATCH_INEDGE_Pos 0 //哪个沿来锁存从SDRAM中读回的数据，0 上升沿 1 下降沿 +#define SDRAMC_LATCH_INEDGE_Msk (0x01 << SDRAMC_LATCH_INEDGE_Pos) +#define SDRAMC_LATCH_OUTEDGE_Pos 1 //哪个沿去锁存送给SDRAM的数据，1 上升沿 0 下降沿 +#define SDRAMC_LATCH_OUTEDGE_Msk (0x01 << SDRAMC_LATCH_OUTEDGE_Pos) +#define SDRAMC_LATCH_WAITST_Pos 2 +#define SDRAMC_LATCH_WAITST_Msk (0x01 << SDRAMC_LATCH_WAITST_Pos) + +typedef struct +{ + __IO uint32_t IE; + + __IO uint32_t IF; //写1清零 + + __IO uint32_t IM; + + __IO uint32_t CR; + + __IO uint32_t ADDR; + + __IO uint32_t CMD; +} NORFLC_TypeDef; + +#define NORFLC_IE_FINISH_Pos 0 +#define NORFLC_IE_FINISH_Msk (0x01 << NORFLC_IE_FINISH_Pos) +#define NORFLC_IE_TIMEOUT_Pos 1 +#define NORFLC_IE_TIMEOUT_Msk (0x01 << NORFLC_IE_TIMEOUT_Pos) + +#define NORFLC_IF_FINISH_Pos 0 +#define NORFLC_IF_FINISH_Msk (0x01 << NORFLC_IF_FINISH_Pos) +#define NORFLC_IF_TIMEOUT_Pos 1 +#define NORFLC_IF_TIMEOUT_Msk (0x01 << NORFLC_IF_TIMEOUT_Pos) + +#define NORFLC_IM_FINISH_Pos 0 +#define NORFLC_IM_FINISH_Msk (0x01 << NORFLC_IM_FINISH_Pos) +#define NORFLC_IM_TIMEOUT_Pos 1 +#define NORFLC_IM_TIMEOUT_Msk (0x01 << NORFLC_IM_TIMEOUT_Pos) + +#define NORFLC_CR_RDTIME_Pos 0 //Oen下降沿后多少个时钟周期后采样读回的数据。0表示1个时钟周期 +#define NORFLC_CR_RDTIME_Msk (0x1F << NORFLC_CR_RDTIME_Pos) +#define NORFLC_CR_WRTIME_Pos 5 //输出Wen的低电平宽度。0表示1个时钟周期 +#define NORFLC_CR_WRTIME_Msk (0x07 << NORFLC_CR_WRTIME_Pos) +#define NORFLC_CR_BYTEIF_Pos 8 //外部NOR FLASH数据宽度，1 8位 0 16位 +#define NORFLC_CR_BYTEIF_Msk (0x01 << NORFLC_CR_BYTEIF_Pos) + +#define NORFLC_CMD_DATA_Pos 0 //在PROGRAM命令中，DATA是要写入NOR FLASH的数据；在READ命令中，DATA是从NOR FLASH读回的数据 +#define NORFLC_CMD_DATA_Msk (0xFFFF << NORFLC_CMD_DATA_Pos) +#define NORFLC_CMD_CMD_Pos 16 //需要执行的命令，0 READ 1 RESET 2 AUTOMATIC SELECT 3 PROGRAM 4 CHIP ERASE 5 SECTOR ERASE +#define NORFLC_CMD_CMD_Msk (0x07 << NORFLC_CMD_CMD_Pos) + +typedef struct +{ + __IO uint32_t CR; + + __O uint32_t DATAIN; + + __IO uint32_t INIVAL; + + __I uint32_t RESULT; +} CRC_TypeDef; + +#define CRC_CR_EN_Pos 0 +#define CRC_CR_EN_Msk (0x01 << CRC_CR_EN_Pos) +#define CRC_CR_OREV_Pos 1 //输出结果是否翻转 +#define CRC_CR_OREV_Msk (0x01 << CRC_CR_OREV_Pos) +#define CRC_CR_ONOT_Pos 2 //输出结果是否取反 +#define CRC_CR_ONOT_Msk (0x01 << CRC_CR_ONOT_Pos) +#define CRC_CR_CRC16_Pos 3 //1 CRC16 0 CRC32 +#define CRC_CR_CRC16_Msk (0x01 << CRC_CR_CRC16_Pos) +#define CRC_CR_IBITS_Pos 4 //输入数据有效位数 0 32位 1 16位 2 8位 +#define CRC_CR_IBITS_Msk (0x03 << CRC_CR_IBITS_Pos) + +typedef struct +{ + __IO uint32_t MINSEC; //分秒计数 + + __IO uint32_t DATHUR; //日时计数 + + __IO uint32_t MONDAY; //月周计数 + + __IO uint32_t YEAR; //[11:0] 年计数，支持1901-2199 + + __IO uint32_t MINSECAL; //分秒闹铃设置 + + __IO uint32_t DAYHURAL; //周时闹铃设置 + + __IO uint32_t LOAD; //将设置寄存器中的值同步到RTC中，同步完成自动清零 + + __IO uint32_t IE; + + __IO uint32_t IF; //写1清零 + + __IO uint32_t EN; //[0] 1 RTC使能 + + __IO uint32_t CFGABLE; //[0] 1 RTC可配置 + + __IO uint32_t TRIM; //时钟调整 + + __IO uint32_t TRIMM; //时钟微调整 +} RTC_TypeDef; + +#define RTC_LOAD_TIME_Pos 0 +#define RTC_LOAD_TIME_Msk (0x01 << RTC_LOAD_TIME_Pos) +#define RTC_LOAD_ALARM_Pos 1 +#define RTC_LOAD_ALARM_Msk (0x01 << RTC_LOAD_ALARM_Pos) + +#define RTC_MINSEC_SEC_Pos 0 //秒计数，取值0--59 +#define RTC_MINSEC_SEC_Msk (0x3F << RTC_MINSEC_SEC_Pos) +#define RTC_MINSEC_MIN_Pos 6 //分钟计数，取值0--59 +#define RTC_MINSEC_MIN_Msk (0x3F << RTC_MINSEC_MIN_Pos) + +#define RTC_DATHUR_HOUR_Pos 0 //小时计数，取值0--23 +#define RTC_DATHUR_HOUR_Msk (0x1F << RTC_DATHUR_HOUR_Pos) +#define RTC_DATHUR_DATE_Pos 5 //date of month，取值1--31 +#define RTC_DATHUR_DATE_Msk (0x1F << RTC_DATHUR_DATE_Pos) + +#define RTC_MONDAY_DAY_Pos 0 //day of week，取值0--6 +#define RTC_MONDAY_DAY_Msk (0x07 << RTC_MONDAY_DAY_Pos) +#define RTC_MONDAY_MON_Pos 3 //月份计数，取值1--12 +#define RTC_MONDAY_MON_Msk (0x0F << RTC_MONDAY_MON_Pos) + +#define RTC_MINSECAL_SEC_Pos 0 //闹钟秒设置 +#define RTC_MINSECAL_SEC_Msk (0x3F << RTC_MINSECAL_SEC_Pos) +#define RTC_MINSECAL_MIN_Pos 6 //闹钟分钟设置 +#define RTC_MINSECAL_MIN_Msk (0x3F << RTC_MINSECAL_MIN_Pos) + +#define RTC_DAYHURAL_HOUR_Pos 0 //闹钟小时设置 +#define RTC_DAYHURAL_HOUR_Msk (0x1F << RTC_DAYHURAL_HOUR_Pos) +#define RTC_DAYHURAL_SUN_Pos 5 //周日闹钟有效 +#define RTC_DAYHURAL_SUN_Msk (0x01 << RTC_DAYHURAL_SUN_Pos) +#define RTC_DAYHURAL_MON_Pos 6 //周一闹钟有效 +#define RTC_DAYHURAL_MON_Msk (0x01 << RTC_DAYHURAL_MON_Pos) +#define RTC_DAYHURAL_TUE_Pos 7 //周二闹钟有效 +#define RTC_DAYHURAL_TUE_Msk (0x01 << RTC_DAYHURAL_TUE_Pos) +#define RTC_DAYHURAL_WED_Pos 8 //周三闹钟有效 +#define RTC_DAYHURAL_WED_Msk (0x01 << RTC_DAYHURAL_WED_Pos) +#define RTC_DAYHURAL_THU_Pos 9 //周四闹钟有效 +#define RTC_DAYHURAL_THU_Msk (0x01 << RTC_DAYHURAL_THU_Pos) +#define RTC_DAYHURAL_FRI_Pos 10 //周五闹钟有效 +#define RTC_DAYHURAL_FRI_Msk (0x01 << RTC_DAYHURAL_FRI_Pos) +#define RTC_DAYHURAL_SAT_Pos 11 //周六闹钟有效 +#define RTC_DAYHURAL_SAT_Msk (0x01 << RTC_DAYHURAL_SAT_Pos) + +#define RTC_IE_SEC_Pos 0 //秒中断使能 +#define RTC_IE_SEC_Msk (0x01 << RTC_IE_SEC_Pos) +#define RTC_IE_MIN_Pos 1 +#define RTC_IE_MIN_Msk (0x01 << RTC_IE_MIN_Pos) +#define RTC_IE_HOUR_Pos 2 +#define RTC_IE_HOUR_Msk (0x01 << RTC_IE_HOUR_Pos) +#define RTC_IE_DATE_Pos 3 +#define RTC_IE_DATE_Msk (0x01 << RTC_IE_DATE_Pos) +#define RTC_IE_ALARM_Pos 4 +#define RTC_IE_ALARM_Msk (0x01 << RTC_IE_ALARM_Pos) + +#define RTC_IF_SEC_Pos 0 //写1清零 +#define RTC_IF_SEC_Msk (0x01 << RTC_IF_SEC_Pos) +#define RTC_IF_MIN_Pos 1 +#define RTC_IF_MIN_Msk (0x01 << RTC_IF_MIN_Pos) +#define RTC_IF_HOUR_Pos 2 +#define RTC_IF_HOUR_Msk (0x01 << RTC_IF_HOUR_Pos) +#define RTC_IF_DATE_Pos 3 +#define RTC_IF_DATE_Msk (0x01 << RTC_IF_DATE_Pos) +#define RTC_IF_ALARM_Pos 4 +#define RTC_IF_ALARM_Msk (0x01 << RTC_IF_ALARM_Pos) + +#define RTC_TRIM_ADJ_Pos 0 //用于调整BASECNT的计数周期，默认为32768，如果DEC为1，则计数周期调整为32768-ADJ，否则调整为32768+ADJ +#define RTC_TRIM_ADJ_Msk (0xFF << RTC_TRIM_ADJ_Pos) +#define RTC_TRIM_DEC_Pos 8 +#define RTC_TRIM_DEC_Msk (0x01 << RTC_TRIM_DEC_Pos) + +#define RTC_TRIMM_CYCLE_Pos 0 //用于计数周期微调，如果INC为1，则第n个计数周期调整为(32768±ADJ)+1,否则调整为(32768±ADJ)-1 \ + //cycles=0时，不进行微调整；cycles=1，则n为2；cycles=7，则n为8；以此类推 +#define RTC_TRIMM_CYCLE_Msk (0x07 << RTC_TRIMM_CYCLE_Pos) +#define RTC_TRIMM_INC_Pos 3 +#define RTC_TRIMM_INC_Msk (0x01 << RTC_TRIMM_INC_Pos) + +typedef struct +{ + __IO uint32_t LOAD; //喂狗使计数器装载LOAD值 + + __I uint32_t VALUE; + + __IO uint32_t CR; + + __IO uint32_t IF; //计数到0时硬件置位，软件写1清除标志 + + __IO uint32_t FEED; //写0x55喂狗 +} WDT_TypeDef; + +#define WDT_CR_EN_Pos 0 +#define WDT_CR_EN_Msk (0x01 << WDT_CR_EN_Pos) +#define WDT_CR_RSTEN_Pos 1 +#define WDT_CR_RSTEN_Msk (0x01 << WDT_CR_RSTEN_Pos) + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +#define RAM_BASE 0x20000000 +#define AHB_BASE 0x40000000 +#define APB_BASE 0x40010000 + +#define NORFLC_BASE 0x60000000 +#define NORFLM_BASE 0x61000000 + +#define SRAMC_BASE 0x68000000 +#define SRAMM_BASE 0x69000000 + +#define SDRAMC_BASE 0x78000000 +#define SDRAMM_BASE 0x70000000 + +/* AHB Peripheral memory map */ +#define SYS_BASE (AHB_BASE + 0x00000) + +#define DMA_BASE (AHB_BASE + 0x01000) + +#define LCD_BASE (AHB_BASE + 0x02000) + +#define CRC_BASE (AHB_BASE + 0x03000) + +#define SDIO_BASE (AHB_BASE + 0x04000) + +/* APB Peripheral memory map */ +#define PORT_BASE (APB_BASE + 0x00000) + +#define GPIOA_BASE (APB_BASE + 0x01000) +#define GPIOB_BASE (APB_BASE + 0x02000) +#define GPIOC_BASE (APB_BASE + 0x03000) +#define GPIOD_BASE (APB_BASE + 0x04000) +#define GPIOM_BASE (APB_BASE + 0x05000) +#define GPION_BASE (APB_BASE + 0x06000) +#define GPIOP_BASE (APB_BASE + 0x08000) + +#define TIMR0_BASE (APB_BASE + 0x07000) +#define TIMR1_BASE (APB_BASE + 0x0700C) +#define TIMR2_BASE (APB_BASE + 0x07018) +#define TIMR3_BASE (APB_BASE + 0x07024) +#define TIMR4_BASE (APB_BASE + 0x07030) +#define TIMR5_BASE (APB_BASE + 0x0703C) +#define TIMRG_BASE (APB_BASE + 0x07060) + +#define WDT_BASE (APB_BASE + 0x09000) + +#define PWM0_BASE (APB_BASE + 0x0A000) +#define PWM1_BASE (APB_BASE + 0x0A020) +#define PWM2_BASE (APB_BASE + 0x0A040) +#define PWM3_BASE (APB_BASE + 0x0A060) +#define PWM4_BASE (APB_BASE + 0x0A080) +#define PWM5_BASE (APB_BASE + 0x0A0A0) +#define PWMG_BASE (APB_BASE + 0x0A180) + +#define RTC_BASE (APB_BASE + 0x0B000) + +#define ADC0_BASE (APB_BASE + 0x0C000) +#define ADC1_BASE (APB_BASE + 0x0D000) + +#define FLASH_BASE (APB_BASE + 0x0F000) + +#define UART0_BASE (APB_BASE + 0x10000) +#define UART1_BASE (APB_BASE + 0x11000) +#define UART2_BASE (APB_BASE + 0x12000) +#define UART3_BASE (APB_BASE + 0x13000) + +#define I2C0_BASE (APB_BASE + 0x18000) +#define I2C1_BASE (APB_BASE + 0x19000) + +#define SPI0_BASE (APB_BASE + 0x1C000) +#define SPI1_BASE (APB_BASE + 0x1D000) + +#define CAN_BASE (APB_BASE + 0x20000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define SYS ((SYS_TypeDef *)SYS_BASE) + +#define PORT ((PORT_TypeDef *)PORT_BASE) + +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOM ((GPIO_TypeDef *)GPIOM_BASE) +#define GPION ((GPIO_TypeDef *)GPION_BASE) +#define GPIOP ((GPIO_TypeDef *)GPIOP_BASE) + +#define TIMR0 ((TIMR_TypeDef *)TIMR0_BASE) +#define TIMR1 ((TIMR_TypeDef *)TIMR1_BASE) +#define TIMR2 ((TIMR_TypeDef *)TIMR2_BASE) +#define TIMR3 ((TIMR_TypeDef *)TIMR3_BASE) +#define TIMR4 ((TIMR_TypeDef *)TIMR4_BASE) +#define TIMR5 ((TIMR_TypeDef *)TIMR5_BASE) +#define TIMRG ((TIMRG_TypeDef *)TIMRG_BASE) + +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define UART3 ((UART_TypeDef *)UART3_BASE) + +#define SPI0 ((SPI_TypeDef *)SPI0_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) + +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) + +#define ADC0 ((ADC_TypeDef *)ADC0_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) + +#define PWM0 ((PWM_TypeDef *)PWM0_BASE) +#define PWM1 ((PWM_TypeDef *)PWM1_BASE) +#define PWM2 ((PWM_TypeDef *)PWM2_BASE) +#define PWM3 ((PWM_TypeDef *)PWM3_BASE) +#define PWM4 ((PWM_TypeDef *)PWM4_BASE) +#define PWM5 ((PWM_TypeDef *)PWM5_BASE) +#define PWMG ((PWMG_TypeDef *)PWMG_BASE) + +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) + +#define DMA ((DMA_TypeDef *)DMA_BASE) + +#define CAN ((CAN_TypeDef *)CAN_BASE) + +#define LCD ((LCD_TypeDef *)LCD_BASE) + +#define CRC ((CRC_TypeDef *)CRC_BASE) + +#define RTC ((RTC_TypeDef *)RTC_BASE) + +#define WDT ((WDT_TypeDef *)WDT_BASE) + +#define FLASH ((FLASH_Typedef *)FLASH_BASE) + +#define SRAMC ((SRAMC_TypeDef *)SRAMC_BASE) + +#define NORFLC ((NORFLC_TypeDef *)NORFLC_BASE) + +#define SDRAMC ((SDRAMC_TypeDef *)SDRAMC_BASE) + +typedef void (*Func_void_void)(void); + +#include "SWM320_port.h" +#include "SWM320_gpio.h" +#include "SWM320_exti.h" +#include "SWM320_timr.h" +#include "SWM320_uart.h" +#include "SWM320_spi.h" +#include "SWM320_i2c.h" +#include "SWM320_pwm.h" +#include "SWM320_adc.h" +#include "SWM320_dma.h" +#include "SWM320_lcd.h" +#include "SWM320_can.h" +#include "SWM320_sdio.h" +#include "SWM320_flash.h" +#include "SWM320_norflash.h" +#include "SWM320_sdram.h" +#include "SWM320_sram.h" +#include "SWM320_crc.h" +#include "SWM320_rtc.h" +#include "SWM320_wdt.h" + +#endif //__SWM320_H__ diff --git a/bsp/swm320/libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s b/bsp/swm320/libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s new file mode 100644 index 0000000000000000000000000000000000000000..72562473f2f6efc34bc2a32af9c3957beec35283 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s @@ -0,0 +1,558 @@ +;****************************************************************************************************************************************** +; ļ: startup_SWM320.s +; ˵: SWM2400Ƭļ +; ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +; ע: +; 汾: V1.1.0 20171025 +; ¼: +; +; +;****************************************************************************************************************************************** +; @attention +; +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +; -ECTION WITH THEIR PRODUCTS. +; +; COPYRIGHT 2012 Synwit Technology +;****************************************************************************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD GPIOA0_Handler + DCD GPIOA1_Handler + DCD GPIOA2_Handler + DCD GPIOA3_Handler + DCD GPIOA4_Handler + DCD GPIOA5_Handler + DCD GPIOA6_Handler + DCD GPIOA7_Handler + DCD GPIOB0_Handler + DCD GPIOB1_Handler + DCD GPIOB2_Handler + DCD GPIOB3_Handler + DCD GPIOB4_Handler + DCD GPIOB5_Handler + DCD GPIOB6_Handler + DCD GPIOB7_Handler + DCD GPIOC0_Handler + DCD GPIOC1_Handler + DCD GPIOC2_Handler + DCD GPIOC3_Handler + DCD GPIOC4_Handler + DCD GPIOC5_Handler + DCD GPIOC6_Handler + DCD GPIOC7_Handler + DCD GPIOM0_Handler + DCD GPIOM1_Handler + DCD GPIOM2_Handler + DCD GPIOM3_Handler + DCD GPIOM4_Handler + DCD GPIOM5_Handler + DCD GPIOM6_Handler + DCD GPIOM7_Handler + DCD DMA_Handler + DCD LCD_Handler + DCD NORFLC_Handler + DCD CAN_Handler + DCD PULSE_Handler + DCD WDT_Handler + DCD PWM_Handler + DCD UART0_Handler + DCD UART1_Handler + DCD UART2_Handler + DCD UART3_Handler + DCD 0 + DCD I2C0_Handler + DCD I2C1_Handler + DCD SPI0_Handler + DCD ADC0_Handler + DCD RTC_Handler + DCD BOD_Handler + DCD SDIO_Handler + DCD GPIOA_Handler + DCD GPIOB_Handler + DCD GPIOC_Handler + DCD GPIOM_Handler + DCD GPION_Handler + DCD GPIOP_Handler + DCD ADC1_Handler + DCD FPU_Handler + DCD SPI1_Handler + DCD TIMR0_Handler + DCD TIMR1_Handler + DCD TIMR2_Handler + DCD TIMR3_Handler + DCD TIMR4_Handler + DCD TIMR5_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + + + AREA |.text|, CODE, READONLY + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +GPIOA0_Handler PROC + EXPORT GPIOA0_Handler [WEAK] + B . + ENDP + +GPIOA1_Handler PROC + EXPORT GPIOA1_Handler [WEAK] + B . + ENDP + +GPIOA2_Handler PROC + EXPORT GPIOA2_Handler [WEAK] + B . + ENDP + +GPIOA3_Handler PROC + EXPORT GPIOA3_Handler [WEAK] + B . + ENDP + +GPIOA4_Handler PROC + EXPORT GPIOA4_Handler [WEAK] + B . + ENDP + +GPIOA5_Handler PROC + EXPORT GPIOA5_Handler [WEAK] + B . + ENDP + +GPIOA6_Handler PROC + EXPORT GPIOA6_Handler [WEAK] + B . + ENDP + +GPIOA7_Handler PROC + EXPORT GPIOA7_Handler [WEAK] + B . + ENDP + +GPIOB0_Handler PROC + EXPORT GPIOB0_Handler [WEAK] + B . + ENDP + +GPIOB1_Handler PROC + EXPORT GPIOB1_Handler [WEAK] + B . + ENDP + +GPIOB2_Handler PROC + EXPORT GPIOB2_Handler [WEAK] + B . + ENDP + +GPIOB3_Handler PROC + EXPORT GPIOB3_Handler [WEAK] + B . + ENDP + +GPIOB4_Handler PROC + EXPORT GPIOB4_Handler [WEAK] + B . + ENDP + +GPIOB5_Handler PROC + EXPORT GPIOB5_Handler [WEAK] + B . + ENDP + +GPIOB6_Handler PROC + EXPORT GPIOB6_Handler [WEAK] + B . + ENDP + +GPIOB7_Handler PROC + EXPORT GPIOB7_Handler [WEAK] + B . + ENDP + +GPIOC0_Handler PROC + EXPORT GPIOC0_Handler [WEAK] + B . + ENDP + +GPIOC1_Handler PROC + EXPORT GPIOC1_Handler [WEAK] + B . + ENDP + +GPIOC2_Handler PROC + EXPORT GPIOC2_Handler [WEAK] + B . + ENDP + +GPIOC3_Handler PROC + EXPORT GPIOC3_Handler [WEAK] + B . + ENDP + +GPIOC4_Handler PROC + EXPORT GPIOC4_Handler [WEAK] + B . + ENDP + +GPIOC5_Handler PROC + EXPORT GPIOC5_Handler [WEAK] + B . + ENDP + +GPIOC6_Handler PROC + EXPORT GPIOC6_Handler [WEAK] + B . + ENDP + +GPIOC7_Handler PROC + EXPORT GPIOC7_Handler [WEAK] + B . + ENDP + +GPIOM0_Handler PROC + EXPORT GPIOM0_Handler [WEAK] + B . + ENDP + +GPIOM1_Handler PROC + EXPORT GPIOM1_Handler [WEAK] + B . + ENDP + +GPIOM2_Handler PROC + EXPORT GPIOM2_Handler [WEAK] + B . + ENDP + +GPIOM3_Handler PROC + EXPORT GPIOM3_Handler [WEAK] + B . + ENDP + +GPIOM4_Handler PROC + EXPORT GPIOM4_Handler [WEAK] + B . + ENDP + +GPIOM5_Handler PROC + EXPORT GPIOM5_Handler [WEAK] + B . + ENDP + +GPIOM6_Handler PROC + EXPORT GPIOM6_Handler [WEAK] + B . + ENDP + +GPIOM7_Handler PROC + EXPORT GPIOM7_Handler [WEAK] + B . + ENDP + +DMA_Handler PROC + EXPORT DMA_Handler [WEAK] + B . + ENDP + +LCD_Handler PROC + EXPORT LCD_Handler [WEAK] + B . + ENDP + +NORFLC_Handler PROC + EXPORT NORFLC_Handler [WEAK] + B . + ENDP + +CAN_Handler PROC + EXPORT CAN_Handler [WEAK] + B . + ENDP + +PULSE_Handler PROC + EXPORT PULSE_Handler [WEAK] + B . + ENDP + +WDT_Handler PROC + EXPORT WDT_Handler [WEAK] + B . + ENDP + +PWM_Handler PROC + EXPORT PWM_Handler [WEAK] + B . + ENDP + +UART0_Handler PROC + EXPORT UART0_Handler [WEAK] + B . + ENDP + +UART1_Handler PROC + EXPORT UART1_Handler [WEAK] + B . + ENDP + +UART2_Handler PROC + EXPORT UART2_Handler [WEAK] + B . + ENDP + +UART3_Handler PROC + EXPORT UART3_Handler [WEAK] + B . + ENDP + +I2C0_Handler PROC + EXPORT I2C0_Handler [WEAK] + B . + ENDP + +I2C1_Handler PROC + EXPORT I2C1_Handler [WEAK] + B . + ENDP + +SPI0_Handler PROC + EXPORT SPI0_Handler [WEAK] + B . + ENDP + +ADC0_Handler PROC + EXPORT ADC0_Handler [WEAK] + B . + ENDP + +RTC_Handler PROC + EXPORT RTC_Handler [WEAK] + B . + ENDP + +BOD_Handler PROC + EXPORT BOD_Handler [WEAK] + B . + ENDP + +SDIO_Handler PROC + EXPORT SDIO_Handler [WEAK] + B . + ENDP + +GPIOA_Handler PROC + EXPORT GPIOA_Handler [WEAK] + B . + ENDP + +GPIOB_Handler PROC + EXPORT GPIOB_Handler [WEAK] + B . + ENDP + +GPIOC_Handler PROC + EXPORT GPIOC_Handler [WEAK] + B . + ENDP + +GPIOM_Handler PROC + EXPORT GPIOM_Handler [WEAK] + B . + ENDP + +GPION_Handler PROC + EXPORT GPION_Handler [WEAK] + B . + ENDP + +GPIOP_Handler PROC + EXPORT GPIOP_Handler [WEAK] + B . + ENDP + +ADC1_Handler PROC + EXPORT ADC1_Handler [WEAK] + B . + ENDP + +FPU_Handler PROC + EXPORT FPU_Handler [WEAK] + B . + ENDP + +SPI1_Handler PROC + EXPORT SPI1_Handler [WEAK] + B . + ENDP + +TIMR0_Handler PROC + EXPORT TIMR0_Handler [WEAK] + B . + ENDP + +TIMR1_Handler PROC + EXPORT TIMR1_Handler [WEAK] + B . + ENDP + +TIMR2_Handler PROC + EXPORT TIMR2_Handler [WEAK] + B . + ENDP + +TIMR3_Handler PROC + EXPORT TIMR3_Handler [WEAK] + B . + ENDP + +TIMR4_Handler PROC + EXPORT TIMR4_Handler [WEAK] + B . + ENDP + +TIMR5_Handler PROC + EXPORT TIMR5_Handler [WEAK] + B . + ENDP + + ALIGN + + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/swm320/libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s b/bsp/swm320/libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s new file mode 100644 index 0000000000000000000000000000000000000000..9d8742e9694ba9c03fd1b082e3339aabf0a06858 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s @@ -0,0 +1,242 @@ + .syntax unified + .arch armv7-m + .thumb + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward */ + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space 0x4000 +__StackTop: + + + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space 0x4000 +__HeapLimit: + + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemManage_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long DebugMon_Handler + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + /* External interrupts */ + .long GPIOA0_Handler + .long GPIOA1_Handler + .long GPIOA2_Handler + .long GPIOA3_Handler + .long GPIOA4_Handler + .long GPIOA5_Handler + .long GPIOA6_Handler + .long GPIOA7_Handler + .long GPIOB0_Handler + .long GPIOB1_Handler + .long GPIOB2_Handler + .long GPIOB3_Handler + .long GPIOB4_Handler + .long GPIOB5_Handler + .long GPIOB6_Handler + .long GPIOB7_Handler + .long GPIOC0_Handler + .long GPIOC1_Handler + .long GPIOC2_Handler + .long GPIOC3_Handler + .long GPIOC4_Handler + .long GPIOC5_Handler + .long GPIOC6_Handler + .long GPIOC7_Handler + .long GPIOM0_Handler + .long GPIOM1_Handler + .long GPIOM2_Handler + .long GPIOM3_Handler + .long GPIOM4_Handler + .long GPIOM5_Handler + .long GPIOM6_Handler + .long GPIOM7_Handler + .long DMA_Handler + .long LCD_Handler + .long NORFLC_Handler + .long CAN_Handler + .long PULSE_Handler + .long WDT_Handler + .long PWM_Handler + .long UART0_Handler + .long UART1_Handler + .long UART2_Handler + .long UART3_Handler + .long Default_Handler + .long I2C0_Handler + .long I2C1_Handler + .long SPI0_Handler + .long ADC0_Handler + .long RTC_Handler + .long BOD_Handler + .long SDIO_Handler + .long GPIOA_Handler + .long GPIOB_Handler + .long GPIOC_Handler + .long GPIOM_Handler + .long GPION_Handler + .long GPIOP_Handler + .long ADC1_Handler + .long FPU_Handler + .long SPI1_Handler + .long TIMR0_Handler + .long TIMR1_Handler + .long TIMR2_Handler + .long TIMR3_Handler + .long TIMR4_Handler + .long TIMR5_Handler + + .section .text.Reset_Handler + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by symbols evaluated in linker script. */ + ldr sp, =__StackTop /* set stack pointer */ + + ldr r1, =__data_load__ + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.Lflash_to_ram_loop: + cmp r2, r3 + ittt lo + ldrlo r0, [r1], #4 + strlo r0, [r2], #4 + blo .Lflash_to_ram_loop + + + ldr r2, =__bss_start__ + ldr r3, =__bss_end__ + +.Lbss_to_ram_loop: + cmp r2, r3 + ittt lo + movlo r0, #0 + strlo r0, [r2], #4 + blo .Lbss_to_ram_loop + + ldr r0, =main + bx r0 + .pool + + + .text +/* Macro to define default handlers. + Default handler will be weak symbol and just dead loops. */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + + def_default_handler GPIOA0_Handler + def_default_handler GPIOA1_Handler + def_default_handler GPIOA2_Handler + def_default_handler GPIOA3_Handler + def_default_handler GPIOA4_Handler + def_default_handler GPIOA5_Handler + def_default_handler GPIOA6_Handler + def_default_handler GPIOA7_Handler + def_default_handler GPIOB0_Handler + def_default_handler GPIOB1_Handler + def_default_handler GPIOB2_Handler + def_default_handler GPIOB3_Handler + def_default_handler GPIOB4_Handler + def_default_handler GPIOB5_Handler + def_default_handler GPIOB6_Handler + def_default_handler GPIOB7_Handler + def_default_handler GPIOC0_Handler + def_default_handler GPIOC1_Handler + def_default_handler GPIOC2_Handler + def_default_handler GPIOC3_Handler + def_default_handler GPIOC4_Handler + def_default_handler GPIOC5_Handler + def_default_handler GPIOC6_Handler + def_default_handler GPIOC7_Handler + def_default_handler GPIOM0_Handler + def_default_handler GPIOM1_Handler + def_default_handler GPIOM2_Handler + def_default_handler GPIOM3_Handler + def_default_handler GPIOM4_Handler + def_default_handler GPIOM5_Handler + def_default_handler GPIOM6_Handler + def_default_handler GPIOM7_Handler + def_default_handler DMA_Handler + def_default_handler LCD_Handler + def_default_handler NORFLC_Handler + def_default_handler CAN_Handler + def_default_handler PULSE_Handler + def_default_handler WDT_Handler + def_default_handler PWM_Handler + def_default_handler UART0_Handler + def_default_handler UART1_Handler + def_default_handler UART2_Handler + def_default_handler UART3_Handler + def_default_handler I2C0_Handler + def_default_handler I2C1_Handler + def_default_handler SPI0_Handler + def_default_handler ADC0_Handler + def_default_handler RTC_Handler + def_default_handler BOD_Handler + def_default_handler SDIO_Handler + def_default_handler GPIOA_Handler + def_default_handler GPIOB_Handler + def_default_handler GPIOC_Handler + def_default_handler GPIOM_Handler + def_default_handler GPION_Handler + def_default_handler GPIOP_Handler + def_default_handler ADC1_Handler + def_default_handler FPU_Handler + def_default_handler SPI1_Handler + def_default_handler TIMR0_Handler + def_default_handler TIMR1_Handler + def_default_handler TIMR2_Handler + def_default_handler TIMR3_Handler + def_default_handler TIMR4_Handler + def_default_handler TIMR5_Handler + + def_default_handler Default_Handler + + .end diff --git a/bsp/swm320/libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s b/bsp/swm320/libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s new file mode 100644 index 0000000000000000000000000000000000000000..7463384892d6edc5621d4d5d71454a7509038206 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s @@ -0,0 +1,500 @@ +;****************************************************************************************************************************************** +; 文件名称: startup_SWM2400.s +; 功能说明: SWM2400单片机的启动文件 +; 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +; 注意事项: +; 版本日期: V1.0.0 2016年1月30日 +; 升级记录: +; +; +;****************************************************************************************************************************************** +; @attention +; +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +; -ECTION WITH THEIR PRODUCTS. +; +; COPYRIGHT 2012 Synwit Technology +;****************************************************************************************************************************************** + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD GPIOA0_Handler + DCD GPIOA1_Handler + DCD GPIOA2_Handler + DCD GPIOA3_Handler + DCD GPIOA4_Handler + DCD GPIOA5_Handler + DCD GPIOA6_Handler + DCD GPIOA7_Handler + DCD GPIOB0_Handler + DCD GPIOB1_Handler + DCD GPIOB2_Handler + DCD GPIOB3_Handler + DCD GPIOB4_Handler + DCD GPIOB5_Handler + DCD GPIOB6_Handler + DCD GPIOB7_Handler + DCD GPIOC0_Handler + DCD GPIOC1_Handler + DCD GPIOC2_Handler + DCD GPIOC3_Handler + DCD GPIOC4_Handler + DCD GPIOC5_Handler + DCD GPIOC6_Handler + DCD GPIOC7_Handler + DCD GPIOM0_Handler + DCD GPIOM1_Handler + DCD GPIOM2_Handler + DCD GPIOM3_Handler + DCD GPIOM4_Handler + DCD GPIOM5_Handler + DCD GPIOM6_Handler + DCD GPIOM7_Handler + DCD DMA_Handler + DCD LCD_Handler + DCD NORFLC_Handler + DCD CAN_Handler + DCD PULSE_Handler + DCD WDT_Handler + DCD PWM_Handler + DCD UART0_Handler + DCD UART1_Handler + DCD UART2_Handler + DCD UART3_Handler + DCD 0 + DCD I2C0_Handler + DCD I2C1_Handler + DCD SPI0_Handler + DCD ADC0_Handler + DCD RTC_Handler + DCD BOD_Handler + DCD SDIO_Handler + DCD GPIOA_Handler + DCD GPIOB_Handler + DCD GPIOC_Handler + DCD GPIOM_Handler + DCD GPION_Handler + DCD GPIOP_Handler + DCD ADC1_Handler + DCD FPU_Handler + DCD SPI1_Handler + DCD TIMR0_Handler + DCD TIMR1_Handler + DCD TIMR2_Handler + DCD TIMR3_Handler + DCD TIMR4_Handler + DCD TIMR5_Handler + + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK GPIOA0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA0_Handler + B GPIOA0_Handler + + PUBWEAK GPIOA1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA1_Handler + B GPIOA1_Handler + + PUBWEAK GPIOA2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA2_Handler + B GPIOA2_Handler + + PUBWEAK GPIOA3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA3_Handler + B GPIOA3_Handler + + PUBWEAK GPIOA4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA4_Handler + B GPIOA4_Handler + + PUBWEAK GPIOA5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA5_Handler + B GPIOA5_Handler + + PUBWEAK GPIOA6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA6_Handler + B GPIOA6_Handler + + PUBWEAK GPIOA7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA7_Handler + B GPIOA7_Handler + + PUBWEAK GPIOB0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB0_Handler + B GPIOB0_Handler + + PUBWEAK GPIOB1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB1_Handler + B GPIOB1_Handler + + PUBWEAK GPIOB2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB2_Handler + B GPIOB2_Handler + + PUBWEAK GPIOB3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB3_Handler + B GPIOB3_Handler + + PUBWEAK GPIOB4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB4_Handler + B GPIOB4_Handler + + PUBWEAK GPIOB5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB5_Handler + B GPIOB5_Handler + + PUBWEAK GPIOB6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB6_Handler + B GPIOB6_Handler + + PUBWEAK GPIOB7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB7_Handler + B GPIOB7_Handler + + PUBWEAK GPIOC0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC0_Handler + B GPIOC0_Handler + + PUBWEAK GPIOC1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC1_Handler + B GPIOC1_Handler + + PUBWEAK GPIOC2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC2_Handler + B GPIOC2_Handler + + PUBWEAK GPIOC3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC3_Handler + B GPIOC3_Handler + + PUBWEAK GPIOC4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC4_Handler + B GPIOC4_Handler + + PUBWEAK GPIOC5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC5_Handler + B GPIOC5_Handler + + PUBWEAK GPIOC6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC6_Handler + B GPIOC6_Handler + + PUBWEAK GPIOC7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC7_Handler + B GPIOC7_Handler + + PUBWEAK GPIOM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM0_Handler + B GPIOM0_Handler + + PUBWEAK GPIOM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM1_Handler + B GPIOM1_Handler + + PUBWEAK GPIOM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM2_Handler + B GPIOM2_Handler + + PUBWEAK GPIOM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM3_Handler + B GPIOM3_Handler + + PUBWEAK GPIOM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM4_Handler + B GPIOM4_Handler + + PUBWEAK GPIOM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM5_Handler + B GPIOM5_Handler + + PUBWEAK GPIOM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM6_Handler + B GPIOM6_Handler + + PUBWEAK GPIOM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM7_Handler + B GPIOM7_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK LCD_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_Handler + B LCD_Handler + + PUBWEAK NORFLC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NORFLC_Handler + B NORFLC_Handler + + PUBWEAK CAN_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_Handler + B CAN_Handler + + PUBWEAK PULSE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PULSE_Handler + B PULSE_Handler + + PUBWEAK WDT_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT_Handler + B WDT_Handler + + PUBWEAK PWM_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM_Handler + B PWM_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK UART3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART3_Handler + B UART3_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK SPI0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_Handler + B SPI0_Handler + + PUBWEAK ADC0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_Handler + B ADC0_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK BOD_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BOD_Handler + B BOD_Handler + + PUBWEAK SDIO_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_Handler + B SDIO_Handler + + PUBWEAK GPIOA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA_Handler + B GPIOA_Handler + + PUBWEAK GPIOB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB_Handler + B GPIOB_Handler + + PUBWEAK GPIOC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC_Handler + B GPIOC_Handler + + PUBWEAK GPIOM_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM_Handler + B GPIOM_Handler + + PUBWEAK GPION_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPION_Handler + B GPION_Handler + + PUBWEAK GPIOP_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOP_Handler + B GPIOP_Handler + + PUBWEAK ADC1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_Handler + B ADC1_Handler + + PUBWEAK FPU_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_Handler + B FPU_Handler + + PUBWEAK SPI1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_Handler + B SPI1_Handler + + PUBWEAK TIMR0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR0_Handler + B TIMR0_Handler + + PUBWEAK TIMR1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR1_Handler + B TIMR1_Handler + + PUBWEAK TIMR2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR2_Handler + B TIMR2_Handler + + PUBWEAK TIMR3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR3_Handler + B TIMR3_Handler + + PUBWEAK TIMR4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR4_Handler + B TIMR4_Handler + + PUBWEAK TIMR5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR5_Handler + B TIMR5_Handler + + + END diff --git a/bsp/swm320/libraries/CMSIS/DeviceSupport/system_SWM320.c b/bsp/swm320/libraries/CMSIS/DeviceSupport/system_SWM320.c new file mode 100644 index 0000000000000000000000000000000000000000..c367b17d1127febd8b5cb9d189972beea2d7d86b --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/DeviceSupport/system_SWM320.c @@ -0,0 +1,262 @@ +/****************************************************************************************************************************************** +* 文件名称: system_SWM320.c +* 功能说明: SWM320单片机的时钟设置 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include +#include "SWM320.h" + +/****************************************************************************************************************************************** + * 系统时钟设定 + *****************************************************************************************************************************************/ +#define SYS_CLK_20MHz 0 //0 内部高频20MHz RC振荡器 +#define SYS_CLK_40MHz 1 //1 内部高频40MHz RC振荡器 +#define SYS_CLK_32KHz 2 //2 内部低频32KHz RC振荡器 +#define SYS_CLK_XTAL 3 //3 外部晶体振荡器（2-30MHz） +#define SYS_CLK_PLL 4 //4 片内锁相环输出 + +#define SYS_CLK SYS_CLK_PLL + +#define SYS_CLK_DIV_1 0 +#define SYS_CLK_DIV_2 1 + +#define SYS_CLK_DIV SYS_CLK_DIV_1 + +#define __HSI (20000000UL) //高速内部时钟 +#define __LSI (32000UL) //低速内部时钟 +#define __HSE (20000000UL) //高速外部时钟 + +/********************************** PLL 设定 ********************************************** + * VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV + * PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV + *****************************************************************************************/ +#define SYS_PLL_SRC SYS_CLK_20MHz //可取值SYS_CLK_20MHz、SYS_CLK_XTAL + +#define PLL_IN_DIV 5 + +#define PLL_FB_DIV 60 + +#define PLL_OUT_DIV8 0 +#define PLL_OUT_DIV4 1 +#define PLL_OUT_DIV2 2 + +#define PLL_OUT_DIV PLL_OUT_DIV8 + +uint32_t SystemCoreClock = __HSI; //System Clock Frequency (Core Clock) +uint32_t CyclesPerUs = (__HSI / 1000000); //Cycles per micro second + +/****************************************************************************************************************************************** +* 函数名称: +* 功能说明: This function is used to update the variable SystemCoreClock and must be called whenever the core clock is changed +* 输 入: +* 输 出: +* 注意事项: +******************************************************************************************************************************************/ +void SystemCoreClockUpdate(void) +{ + if (SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) //SYS_CLK <= HFCK + { + if (SYS->CLKSEL & SYS_CLKSEL_HFCK_Msk) //HFCK <= XTAL + { + SystemCoreClock = __HSE; + } + else //HFCK <= HRC + { + if (SYS->HRCCR & SYS_HRCCR_DBL_Msk) //HRC = 40MHz + { + SystemCoreClock = __HSI * 2; + } + else //HRC = 20MHz + { + SystemCoreClock = __HSI; + } + } + } + else //SYS_CLK <= LFCK + { + if (SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) //LFCK <= PLL + { + if (SYS->PLLCR & SYS_PLLCR_INSEL_Msk) //PLL_SRC <= HRC + { + SystemCoreClock = __HSI; + } + else //PLL_SRC <= XTAL + { + SystemCoreClock = __HSE; + } + + SystemCoreClock = SystemCoreClock / PLL_IN_DIV * PLL_FB_DIV * 4 / (2 << (2 - PLL_OUT_DIV)); + } + else //LFCK <= LRC + { + SystemCoreClock = __LSI; + } + } + + if (SYS->CLKDIV & SYS_CLKDIV_SYS_Msk) + SystemCoreClock /= 2; + + CyclesPerUs = SystemCoreClock / 1000000; +} + +/****************************************************************************************************************************************** +* 函数名称: +* 功能说明: The necessary initializaiton of systerm +* 输 入: +* 输 出: +* 注意事项: +******************************************************************************************************************************************/ +void SystemInit(void) +{ + SYS->CLKEN |= (1 << SYS_CLKEN_ANAC_Pos); + + switch (SYS_CLK) + { + case SYS_CLK_20MHz: //0 内部高频20MHz RC振荡器 + switchCLK_20MHz(); + break; + + case SYS_CLK_40MHz: //1 内部高频40MHz RC振荡器 + switchCLK_40MHz(); + break; + + case SYS_CLK_32KHz: //2 内部低频32KHz RC振荡器 + switchCLK_32KHz(); + break; + + case SYS_CLK_XTAL: //3 外部晶体振荡器（2-30MHz） + switchCLK_XTAL(); + break; + + case SYS_CLK_PLL: //4 片内锁相环输出 + switchCLK_PLL(); + break; + } + + SYS->CLKDIV &= ~SYS_CLKDIV_SYS_Msk; + SYS->CLKDIV |= (SYS_CLK_DIV << SYS_CLKDIV_SYS_Pos); + + SystemCoreClockUpdate(); +} + +void switchCLK_20MHz(void) +{ + uint32_t i; + + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz + + for (i = 0; i < 1000; i++) + __NOP(); + + SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK +} + +void switchCLK_40MHz(void) +{ + uint32_t i; + + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz + + for (i = 0; i < 1000; i++) + __NOP(); + + SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK +} + +void switchCLK_32KHz(void) +{ + uint32_t i; + + SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); + + SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); + + for (i = 0; i < 100; i++) + __NOP(); + + SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC + SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK +} + +void switchCLK_XTAL(void) +{ + uint32_t i; + + SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); + + for (i = 0; i < 1000; i++) + __NOP(); + + SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK +} + +void switchCLK_PLL(void) +{ + uint32_t i; + + PLLInit(); + SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos); + + for (i = 0; i < 10000; i++) + __NOP(); + + SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK <= PLL + SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK +} + +void PLLInit(void) +{ + uint32_t i; + + if (SYS_PLL_SRC == SYS_CLK_20MHz) + { + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz + + for (i = 0; i < 1000; i++) + __NOP(); + + SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC + } + else if (SYS_PLL_SRC == SYS_CLK_XTAL) + { + SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); + + for (i = 0; i < 20000; i++) + ; + + SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL + } + + SYS->PLLDIV &= ~(SYS_PLLDIV_INDIV_Msk | + SYS_PLLDIV_FBDIV_Msk | + SYS_PLLDIV_OUTDIV_Msk); + SYS->PLLDIV |= (PLL_IN_DIV << SYS_PLLDIV_INDIV_Pos) | + (PLL_FB_DIV << SYS_PLLDIV_FBDIV_Pos) | + (PLL_OUT_DIV << SYS_PLLDIV_OUTDIV_Pos); + + SYS->PLLCR &= ~(1 << SYS_PLLCR_OFF_Pos); + + while (SYS->PLLLOCK == 0) + ; //等待PLL锁定 +} diff --git a/bsp/swm320/libraries/CMSIS/DeviceSupport/system_SWM320.h b/bsp/swm320/libraries/CMSIS/DeviceSupport/system_SWM320.h new file mode 100644 index 0000000000000000000000000000000000000000..4db7f29433bf25dbe05cdb3a3347d997921865d2 --- /dev/null +++ b/bsp/swm320/libraries/CMSIS/DeviceSupport/system_SWM320.h @@ -0,0 +1,28 @@ +#ifndef __SYSTEM_SWM320_H__ +#define __SYSTEM_SWM320_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + extern uint32_t CyclesPerUs; // Cycles per micro second + + extern void SystemInit(void); + + extern void SystemCoreClockUpdate(void); + + extern void switchCLK_20MHz(void); + extern void switchCLK_40MHz(void); + extern void switchCLK_32KHz(void); + extern void switchCLK_XTAL(void); + extern void switchCLK_PLL(void); + + extern void PLLInit(void); + +#ifdef __cplusplus +} +#endif + +#endif //__SYSTEM_SWM320_H__ diff --git a/bsp/swm320/libraries/SConscript b/bsp/swm320/libraries/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..92c6725dced5260180c0436c96f8dc977249f016 --- /dev/null +++ b/bsp/swm320/libraries/SConscript @@ -0,0 +1,17 @@ +from building import * +import rtconfig +cwd = GetCurrentDir() +src = Glob('CMSIS/DeviceSupport/*.c') +CPPPATH = [cwd + '/CMSIS/CoreSupport', cwd + '/CMSIS/DeviceSupport', cwd + '/SWM320_StdPeriph_Driver'] + +src += Glob('SWM320_StdPeriph_Driver/*.c') + +if rtconfig.CROSS_TOOL == 'gcc': + src += ['CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['CMSIS/DeviceSupport/startup/arm/startup_SWM320.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['CMSIS/DeviceSupport/startup/iar/startup_SWM320.s'] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_adc.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..7f5f64e84ea47bcab00b56a172e83619ff83c949 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_adc.c @@ -0,0 +1,510 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_adc.c +* ˵: SWM320ƬADCģת +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_adc.h" + + +/****************************************************************************************************************************************** +* : ADC_Init() +* ˵: ADCģתʼ +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* ADC_InitStructure * initStruct ADCضֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void ADC_Init(ADC_TypeDef * ADCx, ADC_InitStructure * initStruct) +{ + switch((uint32_t)ADCx) + { + case ((uint32_t)ADC0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_ADC0_Pos); + break; + + case ((uint32_t)ADC1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_ADC1_Pos); + break; + } + + ADC_Close(ADCx); //һЩؼĴֻADCرʱ + + if(initStruct->clk_src == ADC_CLKSRC_HRC) + { + ADCx->CTRL |= (1 << ADC_CTRL_CLKSRC_Pos); + + ADCx->CTRL2 &= ~ADC_CTRL2_CLKDIV_Msk; + ADCx->CTRL2 |= (initStruct->clk_div << ADC_CTRL2_CLKDIV_Pos); + } + else + { + if(SYS->PLLCR & SYS_PLLCR_OFF_Msk) PLLInit(); + + ADCx->CTRL &= ~(1 << ADC_CTRL_CLKSRC_Pos); + + SYS->PLLDIV &= ~SYS_PLLDIV_ADVCO_Msk; + SYS->PLLDIV |= ((initStruct->clk_src - 2) << SYS_PLLDIV_ADVCO_Pos); + + SYS->PLLDIV &= ~SYS_PLLDIV_ADDIV_Msk; + SYS->PLLDIV |= (initStruct->clk_div << SYS_PLLDIV_ADDIV_Pos); + } + + ADCx->CALIBSET = (ADCx == ADC0) ? SYS->BKP[0] : SYS->BKP[1]; + ADCx->CALIBEN = (1 << ADC_CALIBEN_OFFSET_Pos) | (1 << ADC_CALIBEN_K_Pos); + + ADCx->CTRL2 &= ~(ADC_CTRL2_ADCEVCM_Msk | ADC_CTRL2_PGAIVCM_Msk | ADC_CTRL2_PGAGAIN_Msk | ADC_CTRL2_PGAVCM_Msk); + ADCx->CTRL2 |= (0 << ADC_CTRL2_ADCEVCM_Pos) | + (initStruct->pga_ref << ADC_CTRL2_PGAIVCM_Pos) | + (6 << ADC_CTRL2_PGAGAIN_Pos) | + ((uint32_t)6 << ADC_CTRL2_PGAVCM_Pos); + + ADCx->CTRL &= ~( 0xFF << ADC_CTRL_CH0_Pos); + ADCx->CTRL |= (initStruct->channels << ADC_CTRL_CH0_Pos); + + ADCx->CTRL &= ~(ADC_CTRL_AVG_Msk | ADC_CTRL_TRIG_Msk | ADC_CTRL_CONT_Msk); + ADCx->CTRL |= (initStruct->samplAvg << ADC_CTRL_AVG_Pos) | + (initStruct->trig_src << ADC_CTRL_TRIG_Pos) | + (initStruct->Continue << ADC_CTRL_CONT_Pos); + + ADCx->IF = 0xFFFFFFFF; //жϱ־ + + ADCx->IE &= ~(ADC_IE_CH0EOC_Msk | ADC_IE_CH1EOC_Msk | ADC_IE_CH2EOC_Msk | ADC_IE_CH3EOC_Msk | + ADC_IE_CH4EOC_Msk | ADC_IE_CH5EOC_Msk | ADC_IE_CH6EOC_Msk | ADC_IE_CH7EOC_Msk); + ADCx->IE |= (((initStruct->EOC_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7EOC_Pos); + + ADCx->IE &= ~(ADC_IE_CH0OVF_Msk | ADC_IE_CH1OVF_Msk | ADC_IE_CH2OVF_Msk | ADC_IE_CH3OVF_Msk | + ADC_IE_CH4OVF_Msk | ADC_IE_CH5OVF_Msk | ADC_IE_CH6OVF_Msk | ADC_IE_CH7OVF_Msk); + ADCx->IE |= (((initStruct->OVF_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7OVF_Pos); + + ADCx->IE &= ~(ADC_IE_CH0HFULL_Msk | ADC_IE_CH1HFULL_Msk | ADC_IE_CH2HFULL_Msk | ADC_IE_CH3HFULL_Msk | + ADC_IE_CH4HFULL_Msk | ADC_IE_CH5HFULL_Msk | ADC_IE_CH6HFULL_Msk | ADC_IE_CH7HFULL_Msk); + ADCx->IE |= (((initStruct->HFULL_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7HFULL_Pos); + + ADCx->IE &= ~(uint32_t)(ADC_IE_CH0FULL_Msk | ADC_IE_CH1FULL_Msk | ADC_IE_CH2FULL_Msk | ADC_IE_CH3FULL_Msk | + ADC_IE_CH4FULL_Msk | ADC_IE_CH5FULL_Msk | ADC_IE_CH6FULL_Msk | ADC_IE_CH7FULL_Msk); + ADCx->IE |= (((initStruct->FULL_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7FULL_Pos); + + switch((uint32_t)ADCx) + { + case ((uint32_t)ADC0): + if(initStruct->EOC_IEn | initStruct->OVF_IEn | initStruct->HFULL_IEn | initStruct->FULL_IEn) + { + NVIC_EnableIRQ(ADC0_IRQn); + } + else + { + NVIC_DisableIRQ(ADC0_IRQn); + } + break; + + case ((uint32_t)ADC1): + if(initStruct->EOC_IEn | initStruct->OVF_IEn | initStruct->HFULL_IEn | initStruct->FULL_IEn) + { + NVIC_EnableIRQ(ADC1_IRQn); + } + else + { + NVIC_DisableIRQ(ADC1_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : ADC_Open() +* ˵: ADCӲADCת +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* : +* ע: +******************************************************************************************************************************************/ +void ADC_Open(ADC_TypeDef * ADCx) +{ + ADCx->CTRL |= (0x01 << ADC_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : ADC_Close() +* ˵: ADCرգ޷ӲADCת +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* : +* ע: +******************************************************************************************************************************************/ +void ADC_Close(ADC_TypeDef * ADCx) +{ + ADCx->CTRL &= ~(0x01 << ADC_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : ADC_Start() +* ˵: ģʽADCת +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* : +* ע: +******************************************************************************************************************************************/ +void ADC_Start(ADC_TypeDef * ADCx) +{ + ADCx->START |= (0x01 << ADC_START_GO_Pos); +} + +/****************************************************************************************************************************************** +* : ADC_Stop() +* ˵: ģʽֹͣADCת +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* : +* ע: +******************************************************************************************************************************************/ +void ADC_Stop(ADC_TypeDef * ADCx) +{ + ADCx->START &= ~(0x01 << ADC_START_GO_Pos); +} + +static uint32_t chn2idx(uint32_t chn) +{ + uint32_t idx = 0; + + switch(chn) + { + case 0x01: idx = 0; break; + case 0x02: idx = 1; break; + case 0x04: idx = 2; break; + case 0x08: idx = 3; break; + case 0x10: idx = 4; break; + case 0x20: idx = 5; break; + case 0x40: idx = 6; break; + case 0x80: idx = 7; break; + } + + return idx; +} + +/****************************************************************************************************************************************** +* : ADC_Read() +* ˵: ָͨȡת +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪȡתͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : uint32_t ȡת +* ע: +******************************************************************************************************************************************/ +uint32_t ADC_Read(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t dat = 0; + uint32_t idx = chn2idx(chn); + + dat = ADCx->CH[idx].DATA; + + ADCx->CH[idx].STAT = 0x01; //EOC־ + + return dat; +} + +/****************************************************************************************************************************************** +* : ADC_IsEOC() +* ˵: ָͨǷEnd Of Conversion +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn Ҫѯ״̬ͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : uint32_t 1 ͨת 0 ͨδת +* ע: +******************************************************************************************************************************************/ +uint32_t ADC_IsEOC(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->CH[idx].STAT & ADC_STAT_EOC_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : ADC_ChnSelect() +* ˵: ADCͨѡͨģתѡͨͨβת +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chns ҪѡͨͨЧֵADC_CH0ADC_CH1... ... ADC_CH7ϣλ㣩 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_ChnSelect(ADC_TypeDef * ADCx, uint32_t chns) +{ + ADCx->CTRL &= ~(0xFF << ADC_CTRL_CH0_Pos); + ADCx->CTRL |= (chns << ADC_CTRL_CH0_Pos); +} + + +/****************************************************************************************************************************************** +* : ADC_IntEOCEn() +* ˵: תжʹ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntEOCEn(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx*4)); +} + +/****************************************************************************************************************************************** +* : ADC_IntEOCDis() +* ˵: תжϽֹ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntEOCDis(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx*4)); +} + +/****************************************************************************************************************************************** +* : ADC_IntEOCClr() +* ˵: תжϱ־ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntEOCClr(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx*4)); +} + +/****************************************************************************************************************************************** +* : ADC_IntEOCStat() +* ˵: תж״̬ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪѯͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : uint32_t 1 ͨת 0 ͨδת +* ע: +******************************************************************************************************************************************/ +uint32_t ADC_IntEOCStat(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx*4))) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : ADC_IntOVFEn() +* ˵: жʹ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntOVFEn(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx*4+1)); +} + +/****************************************************************************************************************************************** +* : ADC_IntOVFDis() +* ˵: жϽֹ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntOVFDis(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx*4+1)); +} + +/****************************************************************************************************************************************** +* : ADC_IntOVFClr() +* ˵: жϱ־ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntOVFClr(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx*4+1)); +} + +/****************************************************************************************************************************************** +* : ADC_IntOVFStat() +* ˵: ж״̬ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪѯͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : uint32_t 1 ͨת 0 ͨδת +* ע: +******************************************************************************************************************************************/ +uint32_t ADC_IntOVFStat(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx*4+1))) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : ADC_IntHFULLEn() +* ˵: FIFOжʹ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntHFULLEn(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx*4+2)); +} + +/****************************************************************************************************************************************** +* : ADC_IntHFULLDis() +* ˵: FIFOжϽֹ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntHFULLDis(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx*4+2)); +} + +/****************************************************************************************************************************************** +* : ADC_IntHFULLClr() +* ˵: FIFOжϱ־ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntHFULLClr(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx*4+2)); +} + +/****************************************************************************************************************************************** +* : ADC_IntHFULLStat() +* ˵: FIFOж״̬ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪѯͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : uint32_t 1 ͨת 0 ͨδת +* ע: +******************************************************************************************************************************************/ +uint32_t ADC_IntHFULLStat(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx*4+2))) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : ADC_IntFULLEn() +* ˵: FIFOжʹ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntFULLEn(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx*4+3)); +} + +/****************************************************************************************************************************************** +* : ADC_IntFULLDis() +* ˵: FIFOжϽֹ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntFULLDis(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx*4+3)); +} + +/****************************************************************************************************************************************** +* : ADC_IntFULLClr() +* ˵: FIFOжϱ־ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪõͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_IntFULLClr(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx*4+3)); +} + +/****************************************************************************************************************************************** +* : ADC_IntFULLStat() +* ˵: FIFOж״̬ +* : ADC_TypeDef * ADCx ָҪõADCȡֵADC +* uint32_t chn ҪѯͨЧֵADC_CH0ADC_CH1... ... ADC_CH7 +* : uint32_t 1 ͨת 0 ͨδת +* ע: +******************************************************************************************************************************************/ +uint32_t ADC_IntFULLStat(ADC_TypeDef * ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx*4+3))) ? 1 : 0; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_adc.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..56f93c66d8f5ccf30b993a65031d1836d2d73042 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_adc.h @@ -0,0 +1,79 @@ +#ifndef __SWM320_ADC_H__ +#define __SWM320_ADC_H__ + +typedef struct { + uint8_t clk_src; //ADCתʱԴADC_CLKSRC_HRCADC_CLKSRC_VCO_DIV16ADC_CLKSRC_VCO_DIV32ADC_CLKSRC_VCO_DIV32 + uint8_t clk_div; //ADCתʱӷƵȡֵ1--31 + uint8_t pga_ref; //PGA׼PGA_REF_INTERNALPGA_REF_EXTERNAL + uint8_t channels; //ADCתͨѡУADC_CH0ADC_CH1... ... ADC_CH7ϣλ㣩 + uint8_t samplAvg; //ȡƽADCתADCһͨתΣǵƽֵΪͨת + uint8_t trig_src; //ADCʽADC_TRIGSRC_SWADC_TRIGSRC_PWMADC_TRIGSRC_TIMR2ADC_TRIGSRC_TIMR3 + uint8_t Continue; //ģʽ£1 תģʽһֱתֱSTARTλ + // 0 תģʽתɺSTARTλԶֹͣת + uint8_t EOC_IEn; //EOCжʹܣÿͨãЧֵΪADC_CH0ADC_CH1... ... ADC_CH7ϣλ㣩 + uint8_t OVF_IEn; //OVFжʹܣÿͨãЧֵΪADC_CH0ADC_CH1... ... ADC_CH7ϣλ㣩 + uint8_t HFULL_IEn; //FIFOжʹܣÿͨãЧֵΪADC_CH0ADC_CH1... ... ADC_CH7ϣλ㣩 + uint8_t FULL_IEn; //FIFO жʹܣÿͨãЧֵΪADC_CH0ADC_CH1... ... ADC_CH7ϣλ㣩 +} ADC_InitStructure; + +#define ADC_CH0 0x01 +#define ADC_CH1 0x02 +#define ADC_CH2 0x04 +#define ADC_CH3 0x08 +#define ADC_CH4 0x10 +#define ADC_CH5 0x20 +#define ADC_CH6 0x40 +#define ADC_CH7 0x80 + +#define ADC_CLKSRC_HRC 1 +#define ADC_CLKSRC_VCO_DIV16 2 +#define ADC_CLKSRC_VCO_DIV32 3 +#define ADC_CLKSRC_VCO_DIV64 4 + +#define ADC_AVG_SAMPLE1 0 +#define ADC_AVG_SAMPLE2 1 //һת2ΣνƽֵΪת +#define ADC_AVG_SAMPLE4 3 +#define ADC_AVG_SAMPLE8 7 +#define ADC_AVG_SAMPLE16 15 + +#define ADC_TRIGSRC_SW 0 //ADC->START.GOд1ת +#define ADC_TRIGSRC_PWM 1 + +#define PGA_REF_INTERNAL 1 //PGA빲ģƽڲ·ADC_REFPADC_REFN +#define PGA_REF_EXTERNAL 0 //PGA빲ģƽⲿṩ(ADC_REFP + ADC_REFN) ƽֵͬ + + +void ADC_Init(ADC_TypeDef * ADCx, ADC_InitStructure * initStruct); //ADCģתʼ +void ADC_Open(ADC_TypeDef * ADCx); //ADCӲADCת +void ADC_Close(ADC_TypeDef * ADCx); //ADCرգ޷ӲADCת +void ADC_Start(ADC_TypeDef * ADCx); //ָADCʼģת +void ADC_Stop(ADC_TypeDef * ADCx); //رָADCֹͣģת + +uint32_t ADC_Read(ADC_TypeDef * ADCx, uint32_t chn); //ָͨȡת +uint32_t ADC_IsEOC(ADC_TypeDef * ADCx, uint32_t chn); //ָͨǷEnd Of Conversion + +void ADC_ChnSelect(ADC_TypeDef * ADCx, uint32_t chns); + + +void ADC_IntEOCEn(ADC_TypeDef * ADCx, uint32_t chn); //תжʹ +void ADC_IntEOCDis(ADC_TypeDef * ADCx, uint32_t chn); //תжϽֹ +void ADC_IntEOCClr(ADC_TypeDef * ADCx, uint32_t chn); //תжϱ־ +uint32_t ADC_IntEOCStat(ADC_TypeDef * ADCx, uint32_t chn); //תж״̬ + +void ADC_IntOVFEn(ADC_TypeDef * ADCx, uint32_t chn); //жʹ +void ADC_IntOVFDis(ADC_TypeDef * ADCx, uint32_t chn); //жϽֹ +void ADC_IntOVFClr(ADC_TypeDef * ADCx, uint32_t chn); //жϱ־ +uint32_t ADC_IntOVFStat(ADC_TypeDef * ADCx, uint32_t chn); //ж״̬ + +void ADC_IntHFULLEn(ADC_TypeDef * ADCx, uint32_t chn); //FIFOжʹ +void ADC_IntHFULLDis(ADC_TypeDef * ADCx, uint32_t chn); //FIFOжϽֹ +void ADC_IntHFULLClr(ADC_TypeDef * ADCx, uint32_t chn); //FIFOжϱ־ +uint32_t ADC_IntHFULLStat(ADC_TypeDef * ADCx, uint32_t chn);//FIFOж״̬ + +void ADC_IntFULLEn(ADC_TypeDef * ADCx, uint32_t chn); //FIFOжʹ +void ADC_IntFULLDis(ADC_TypeDef * ADCx, uint32_t chn); //FIFOжϽֹ +void ADC_IntFULLClr(ADC_TypeDef * ADCx, uint32_t chn); //FIFOжϱ־ +uint32_t ADC_IntFULLStat(ADC_TypeDef * ADCx, uint32_t chn); //FIFOж״̬ + + +#endif //__SWM320_ADC_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_can.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_can.c new file mode 100644 index 0000000000000000000000000000000000000000..c5c5f34a4583f3f7d211aef169e6ea19880d9af4 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_can.c @@ -0,0 +1,688 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_can.c +* ˵: SWM320ƬCANģ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_can.h" + + +/****************************************************************************************************************************************** +* : CAN_Init() +* ˵: CANӿڳʼ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* CAN_InitStructure * initStruct CANӿ趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void CAN_Init(CAN_TypeDef * CANx, CAN_InitStructure * initStruct) +{ + switch((uint32_t)CANx) + { + case ((uint32_t)CAN): + SYS->CLKEN |= (0x01 << SYS_CLKEN_CAN_Pos); + break; + } + + CAN_Close(CANx); //һЩؼĴֻCANرʱ + + CANx->CR &= ~(CAN_CR_LOM_Msk | CAN_CR_STM_Msk | CAN_CR_AFM_Msk); + CANx->CR |= (initStruct->Mode << CAN_CR_LOM_Pos) | + (initStruct->FilterMode << CAN_CR_AFM_Pos); + + CANx->FILTER.AMR[3] = initStruct->FilterMask32b & 0xFF; + CANx->FILTER.AMR[2] = (initStruct->FilterMask32b >> 8) & 0xFF; + CANx->FILTER.AMR[1] = (initStruct->FilterMask32b >> 16) & 0xFF; + CANx->FILTER.AMR[0] = (initStruct->FilterMask32b >> 24) & 0xFF; + + CANx->FILTER.ACR[3] = initStruct->FilterCheck32b & 0xFF; + CANx->FILTER.ACR[2] = (initStruct->FilterCheck32b >> 8) & 0xFF; + CANx->FILTER.ACR[1] = (initStruct->FilterCheck32b >> 16) & 0xFF; + CANx->FILTER.ACR[0] = (initStruct->FilterCheck32b >> 24) & 0xFF; + + CANx->BT1 = (0 << CAN_BT1_SAM_Pos) | + (initStruct->CAN_BS1 << CAN_BT1_TSEG1_Pos) | + (initStruct->CAN_BS2 << CAN_BT1_TSEG2_Pos); + + CANx->BT0 = (initStruct->CAN_SJW << CAN_BT0_SJW_Pos) | + ((SystemCoreClock/2/initStruct->Baudrate/(1 + (initStruct->CAN_BS1 + 1) + (initStruct->CAN_BS2 + 1)) - 1) << CAN_BT0_BRP_Pos); + + CANx->RXERR = 0; //ֻڸλģʽ + CANx->TXERR = 0; + + CANx->IE = (initStruct->RXNotEmptyIEn << CAN_IE_RXDA_Pos) | + (initStruct->RXOverflowIEn << CAN_IE_RXOV_Pos) | + (initStruct->ArbitrLostIEn << CAN_IE_ARBLOST_Pos) | + (initStruct->ErrPassiveIEn << CAN_IE_ERRPASS_Pos); + + switch((uint32_t)CANx) + { + case ((uint32_t)CAN): + if(initStruct->RXNotEmptyIEn | initStruct->RXOverflowIEn | initStruct->ArbitrLostIEn | initStruct->ErrPassiveIEn) + { + NVIC_EnableIRQ(CAN_IRQn); + } + else + { + NVIC_DisableIRQ(CAN_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : CAN_Open() +* ˵: CANӿڴ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_Open(CAN_TypeDef * CANx) +{ + CANx->CR &= ~(0x01 << CAN_CR_RST_Pos); //˳λģʽ빤ģʽ +} + +/****************************************************************************************************************************************** +* : CAN_Close() +* ˵: CANӿڹر +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_Close(CAN_TypeDef * CANx) +{ + CANx->CR |= (0x01 << CAN_CR_RST_Pos); //븴λģʽܷͺͽ +} + +/****************************************************************************************************************************************** +* : CAN_Transmit() +* ˵: CAN +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* uint32_t format CAN_FRAME_STD ׼֡ CAN_FRAME_EXT չ֡ +* uint32_t id ϢID +* uint8_t data[] Ҫ͵ +* uint32_t size Ҫ͵ݵĸ +* uint32_t once ֻһΣʹʧܣٲöʧͳNAKҲط +* : +* ע: +******************************************************************************************************************************************/ +void CAN_Transmit(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once) +{ + uint32_t i; + + if(format == CAN_FRAME_STD) + { + CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 3; + CANx->TXFRAME.DATA[1] = id << 5; + + for(i = 0; i < size; i++) + { + CANx->TXFRAME.DATA[i+2] = data[i]; + } + } + else //if(format == CAN_FRAME_EXT) + { + CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 21; + CANx->TXFRAME.DATA[1] = id >> 13; + CANx->TXFRAME.DATA[2] = id >> 5; + CANx->TXFRAME.DATA[3] = id << 3; + + for(i = 0; i < size; i++) + { + CANx->TXFRAME.DATA[i+4] = data[i]; + } + } + + if(CANx->CR & CAN_CR_STM_Msk) + { + CANx->CMD = (1 << CAN_CMD_SRR_Pos); + } + else + { + if(once == 0) + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos); + } + else + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos); + } + } +} + +/****************************************************************************************************************************************** +* : CAN_TransmitRequest() +* ˵: CANԶԶ̽ڵ㷢 +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* uint32_t format CAN_FRAME_STD ׼֡ CAN_FRAME_EXT չ֡ +* uint32_t id ϢID +* uint32_t once ֻһΣʹʧܣٲöʧͳNAKҲط +* : +* ע: +******************************************************************************************************************************************/ +void CAN_TransmitRequest(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint32_t once) +{ + if(format == CAN_FRAME_STD) + { + CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 3; + CANx->TXFRAME.DATA[1] = id << 5; + } + else //if(format == CAN_FRAME_EXT) + { + CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 21; + CANx->TXFRAME.DATA[1] = id >> 13; + CANx->TXFRAME.DATA[2] = id >> 5; + CANx->TXFRAME.DATA[3] = id << 3; + } + + if(once == 0) + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos); + } + else + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos); + } +} + +/****************************************************************************************************************************************** +* : CAN_Receive() +* ˵: CAN +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* CAN_RXMessage *msg յϢ洢ڴ˽ṹ +* : +* ע: +******************************************************************************************************************************************/ +void CAN_Receive(CAN_TypeDef * CANx, CAN_RXMessage *msg) +{ + uint32_t i; + msg->format = (CANx->RXFRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos; + + msg->remote = (CANx->RXFRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos; + msg->size = (CANx->RXFRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos; + + if(msg->format == CAN_FRAME_STD) + { + msg->id = (CANx->RXFRAME.DATA[0] << 3) | (CANx->RXFRAME.DATA[1] >> 5); + + for(i = 0; i < msg->size; i++) + { + msg->data[i] = CANx->RXFRAME.DATA[i+2]; + } + } + else //if(msg->format == CAN_FRAME_EXT) + { + msg->id = (CANx->RXFRAME.DATA[0] << 21) | (CANx->RXFRAME.DATA[1] << 13) | (CANx->RXFRAME.DATA[2] << 5) | (CANx->RXFRAME.DATA[3] >> 3); + + for(i = 0; i < msg->size; i++) + { + msg->data[i] = CANx->RXFRAME.DATA[i+4]; + } + } + + CANx->CMD = (1 << CAN_CMD_RRB_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_TXComplete() +* ˵: Ƿ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 Ѿ 0 δ +* ע: ͱAbortҲᴥɣᴥͳɹ +******************************************************************************************************************************************/ +uint32_t CAN_TXComplete(CAN_TypeDef * CANx) +{ + return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_TXSuccess() +* ˵: Ƿɹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 ͳɹ 0 ʧ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_TXSuccess(CAN_TypeDef * CANx) +{ + return (CANx->SR & CAN_SR_TXOK_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_AbortTransmit() +* ˵: ֹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: ڽеķ޷ִֹдʧܲط +******************************************************************************************************************************************/ +void CAN_AbortTransmit(CAN_TypeDef * CANx) +{ + CANx->CMD = (1 << CAN_CMD_ABTTX_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_TXBufferReady() +* ˵: TX BufferǷ׼ÿдϢ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 ׼ 0 δ׼ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_TXBufferReady(CAN_TypeDef * CANx) +{ + return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_RXDataAvailable() +* ˵: RX FIFOǷݿɶ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 ݿɶ 0 û +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_RXDataAvailable(CAN_TypeDef * CANx) +{ + return (CANx->SR & CAN_SR_RXDA_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_SetBaudrate() +* ˵: ò +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* uint32_t baudrate ʣλ +* uint32_t CAN_BS1 CAN_BS1_1tqCAN_BS1_2tq... ... CAN_BS1_16tq +* uint32_t CAN_BS2 CAN_BS2_1tqCAN_BS2_2tq... ... CAN_BS2_8tq +* uint32_t CAN_SJW CAN_SJW_1tqCAN_SJW_2tqCAN_SJW_3tqCAN_SJW_4tq +* : +* ע: ǰҪȵCAN_Close()رCANģ +******************************************************************************************************************************************/ +void CAN_SetBaudrate(CAN_TypeDef * CANx, uint32_t baudrate, uint32_t CAN_BS1, uint32_t CAN_BS2, uint32_t CAN_SJW) +{ + CANx->BT1 = (0 << CAN_BT1_SAM_Pos) | + (CAN_BS1 << CAN_BT1_TSEG1_Pos) | + (CAN_BS2 << CAN_BT1_TSEG2_Pos); + + CANx->BT0 = (CAN_SJW << CAN_BT0_SJW_Pos) | + ((SystemCoreClock/2/baudrate/(1 + (CAN_BS1 + 1) + (CAN_BS2 + 1)) - 1) << CAN_BT0_BRP_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_SetFilter32b() +* ˵: ý˲132λ˲ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* uint32_t check maskһ˽յMessageǷԼҪģcheck & (~mask) == ID & (~mask)Messageͨ +* uint32_t mask +* : +* ע: ǰҪȵCAN_Close()رCANģ +******************************************************************************************************************************************/ +void CAN_SetFilter32b(CAN_TypeDef * CANx, uint32_t check, uint32_t mask) +{ + CANx->CR &= ~CAN_CR_AFM_Msk; + CANx->CR |= (CAN_FILTER_32b << CAN_CR_AFM_Pos); + + CANx->FILTER.AMR[3] = mask & 0xFF; + CANx->FILTER.AMR[2] = (mask >> 8) & 0xFF; + CANx->FILTER.AMR[1] = (mask >> 16) & 0xFF; + CANx->FILTER.AMR[0] = (mask >> 24) & 0xFF; + + CANx->FILTER.ACR[3] = check & 0xFF; + CANx->FILTER.ACR[2] = (check >> 8) & 0xFF; + CANx->FILTER.ACR[1] = (check >> 16) & 0xFF; + CANx->FILTER.ACR[0] = (check >> 24) & 0xFF; +} + +/****************************************************************************************************************************************** +* : CAN_SetFilter16b() +* ˵: ý˲216λ˲ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* uint16_t check1 maskһ˽յMessageǷԼҪģcheck & (~mask) == ID & (~mask)Messageͨ +* uint16_t mask1 +* uint16_t check2 +* uint16_t mask2 +* : +* ע: ǰҪȵCAN_Close()رCANģ +******************************************************************************************************************************************/ +void CAN_SetFilter16b(CAN_TypeDef * CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2) +{ + CANx->CR &= ~CAN_CR_AFM_Msk; + CANx->CR |= (CAN_FILTER_16b << CAN_CR_AFM_Pos); + + CANx->FILTER.AMR[3] = mask1 & 0xFF; + CANx->FILTER.AMR[2] = (mask1 >> 8) & 0xFF; + CANx->FILTER.AMR[1] = mask2 & 0xFF; + CANx->FILTER.AMR[0] = (mask2 >> 8) & 0xFF; + + CANx->FILTER.ACR[3] = check1 & 0xFF; + CANx->FILTER.ACR[2] = (check1 >> 8) & 0xFF; + CANx->FILTER.ACR[1] = check2 & 0xFF; + CANx->FILTER.ACR[0] = (check2 >> 8) & 0xFF; +} + +/****************************************************************************************************************************************** +* : CAN_INTRXNotEmptyEn() +* ˵: RX FIFOʱǿգжʹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTRXNotEmptyEn(CAN_TypeDef * CANx) +{ + CANx->IE |= (1 << CAN_IE_RXDA_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTRXNotEmptyDis() +* ˵: RX FIFOʱǿգжϽֹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTRXNotEmptyDis(CAN_TypeDef * CANx) +{ + CANx->IE &= ~(1 << CAN_IE_RXDA_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTRXNotEmptyStat() +* ˵: RX FIFOǿжǷ񴥷 +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 Ѵ 0 δ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_INTRXNotEmptyStat(CAN_TypeDef * CANx) +{ + return (CANx->IF & CAN_IF_RXDA_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_INTTXBufEmptyEn() +* ˵: TX Bufferʱжʹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTTXBufEmptyEn(CAN_TypeDef * CANx) +{ + CANx->IE |= (1 << CAN_IE_TXBR_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTTXBufEmptyDis() +* ˵: TX BufferʱжϽֹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTTXBufEmptyDis(CAN_TypeDef * CANx) +{ + CANx->IE &= ~(1 << CAN_IE_TXBR_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTTXBufEmptyStat() +* ˵: TX BufferжǷ񴥷 +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 Ѵ 0 δ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_INTTXBufEmptyStat(CAN_TypeDef * CANx) +{ + return (CANx->IF & CAN_IF_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_INTErrWarningEn() +* ˵: TXERR/RXERRֵﵽError Warning Limitʱжʹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTErrWarningEn(CAN_TypeDef * CANx) +{ + CANx->IE |= (1 << CAN_IE_ERRWARN_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTErrWarningDis() +* ˵: TXERR/RXERRֵﵽError Warning LimitʱжϽֹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTErrWarningDis(CAN_TypeDef * CANx) +{ + CANx->IE &= ~(1 << CAN_IE_ERRWARN_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTErrWarningStat() +* ˵: TXERR/RXERRֵﵽError Warning LimitжǷ񴥷 +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 Ѵ 0 δ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_INTErrWarningStat(CAN_TypeDef * CANx) +{ + return (CANx->IF & CAN_IF_ERRWARN_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_INTRXOverflowEn() +* ˵: RX FIFO ʱжʹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTRXOverflowEn(CAN_TypeDef * CANx) +{ + CANx->IE |= (1 << CAN_IE_RXOV_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTRXOverflowDis() +* ˵: RX FIFO ʱжϽֹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTRXOverflowDis(CAN_TypeDef * CANx) +{ + CANx->IE &= ~(1 << CAN_IE_RXOV_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTRXOverflowStat() +* ˵: RX FIFO жǷ񴥷 +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 Ѵ 0 δ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_INTRXOverflowStat(CAN_TypeDef * CANx) +{ + return (CANx->IF & CAN_IF_RXOV_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_INTRXOverflowClear() +* ˵: RX FIFO ж +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTRXOverflowClear(CAN_TypeDef * CANx) +{ + CANx->CMD = (1 << CAN_CMD_CLROV_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTWakeupEn() +* ˵: ¼жʹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTWakeupEn(CAN_TypeDef * CANx) +{ + CANx->IE |= (1 << CAN_IE_WKUP_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTWakeupDis() +* ˵: ¼жϽֹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTWakeupDis(CAN_TypeDef * CANx) +{ + CANx->IE &= ~(1 << CAN_IE_WKUP_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTWakeupStat() +* ˵: ¼жǷ񴥷 +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 Ѵ 0 δ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_INTWakeupStat(CAN_TypeDef * CANx) +{ + return (CANx->IF & CAN_IF_WKUP_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_INTErrPassiveEn() +* ˵: TXERR/RXERRֵﵽ127ʱжʹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTErrPassiveEn(CAN_TypeDef * CANx) +{ + CANx->IE |= (1 << CAN_IE_ERRPASS_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTErrPassiveDis() +* ˵: TXERR/RXERRֵﵽ127ʱжϽֹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTErrPassiveDis(CAN_TypeDef * CANx) +{ + CANx->IE &= ~(1 << CAN_IE_ERRPASS_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTErrPassiveStat() +* ˵: TXERR/RXERRֵﵽ127жǷ񴥷 +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 Ѵ 0 δ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_INTErrPassiveStat(CAN_TypeDef * CANx) +{ + return (CANx->IF & CAN_IF_ERRPASS_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_INTArbitrLostEn() +* ˵: ٲʧжʹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTArbitrLostEn(CAN_TypeDef * CANx) +{ + CANx->IE |= (1 << CAN_IE_ARBLOST_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTArbitrLostDis() +* ˵: ٲʧжϽֹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTArbitrLostDis(CAN_TypeDef * CANx) +{ + CANx->IE &= ~(1 << CAN_IE_ARBLOST_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTArbitrLostStat() +* ˵: ٲʧжǷ񴥷 +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 Ѵ 0 δ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_INTArbitrLostStat(CAN_TypeDef * CANx) +{ + return (CANx->IF & CAN_IF_ARBLOST_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_INTBusErrorEn() +* ˵: ߴжʹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTBusErrorEn(CAN_TypeDef * CANx) +{ + CANx->IE |= (1 << CAN_IE_BUSERR_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTBusErrorDis() +* ˵: ߴжϽֹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTBusErrorDis(CAN_TypeDef * CANx) +{ + CANx->IE &= ~(1 << CAN_IE_BUSERR_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTBusErrorStat() +* ˵: ߴжǷ񴥷 +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN +* : uint32_t 1 Ѵ 0 δ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_INTBusErrorStat(CAN_TypeDef * CANx) +{ + return (CANx->IF & CAN_IF_BUSERR_Msk) ? 1 : 0; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_can.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_can.h new file mode 100644 index 0000000000000000000000000000000000000000..7b66ee4d5c4745f0f2571b1b44bbf69a80b98764 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_can.h @@ -0,0 +1,136 @@ +#ifndef __SWM320_CAN_H__ +#define __SWM320_CAN_H__ + +#define CAN_FRAME_STD 0 +#define CAN_FRAME_EXT 1 + +typedef struct { + uint8_t Mode; //CAN_MODE_NORMALCAN_MODE_LISTENCAN_MODE_SELFTEST + uint8_t CAN_BS1; //CAN_BS1_1tqCAN_BS1_2tq... ... CAN_BS1_16tq + uint8_t CAN_BS2; //CAN_BS2_1tqCAN_BS2_2tq... ... CAN_BS2_8tq + uint8_t CAN_SJW; //CAN_SJW_1tqCAN_SJW_2tqCAN_SJW_3tqCAN_SJW_4tq + uint32_t Baudrate; //ʣλʣȡֵ1--1000000 + uint8_t FilterMode; //CAN_FILTER_16bCAN_FILTER_32b + union { + uint32_t FilterMask32b; //FilterCheck & (~FilterMask) == ID & (~FilterMask)Messageͨ + struct { // 0 must match 1 don't care + uint16_t FilterMask16b1; + uint16_t FilterMask16b2; + }; + }; + union { + uint32_t FilterCheck32b; + struct { + uint16_t FilterCheck16b1; + uint16_t FilterCheck16b2; + }; + }; + uint8_t RXNotEmptyIEn; //FIFOǿգݿɶ + uint8_t RXOverflowIEn; //FIFOݶʧ + uint8_t ArbitrLostIEn; //ʧٲñɽշ + uint8_t ErrPassiveIEn; ///ʹֵﵽ127 +} CAN_InitStructure; + +#define CAN_MODE_NORMAL 0 //ģʽ +#define CAN_MODE_LISTEN 1 //ģʽ +#define CAN_MODE_SELFTEST 2 //Բģʽ + +#define CAN_BS1_1tq 0 +#define CAN_BS1_2tq 1 +#define CAN_BS1_3tq 2 +#define CAN_BS1_4tq 3 +#define CAN_BS1_5tq 4 +#define CAN_BS1_6tq 5 +#define CAN_BS1_7tq 6 +#define CAN_BS1_8tq 7 +#define CAN_BS1_9tq 8 +#define CAN_BS1_10tq 9 +#define CAN_BS1_11tq 10 +#define CAN_BS1_12tq 11 +#define CAN_BS1_13tq 12 +#define CAN_BS1_14tq 13 +#define CAN_BS1_15tq 14 +#define CAN_BS1_16tq 15 + +#define CAN_BS2_1tq 0 +#define CAN_BS2_2tq 1 +#define CAN_BS2_3tq 2 +#define CAN_BS2_4tq 3 +#define CAN_BS2_5tq 4 +#define CAN_BS2_6tq 5 +#define CAN_BS2_7tq 6 +#define CAN_BS2_8tq 7 + +#define CAN_SJW_1tq 0 +#define CAN_SJW_2tq 1 +#define CAN_SJW_3tq 2 +#define CAN_SJW_4tq 3 + +#define CAN_FILTER_16b 0 //16λ +#define CAN_FILTER_32b 1 //һ32λ + +typedef struct { + uint32_t id; //ϢID + uint8_t format; //֡ʽCAN_FRAME_STDCAN_FRAME_EXT + uint8_t remote; //ϢǷΪԶ֡ + uint8_t size; //յݸ + uint8_t data[8]; //յ +} CAN_RXMessage; + + +void CAN_Init(CAN_TypeDef * CANx, CAN_InitStructure * initStruct); +void CAN_Open(CAN_TypeDef * CANx); +void CAN_Close(CAN_TypeDef * CANx); + +void CAN_Transmit(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once); +void CAN_TransmitRequest(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint32_t once); +void CAN_Receive(CAN_TypeDef * CANx, CAN_RXMessage *msg); + +uint32_t CAN_TXComplete(CAN_TypeDef * CANx); +uint32_t CAN_TXSuccess(CAN_TypeDef * CANx); + +void CAN_AbortTransmit(CAN_TypeDef * CANx); + +uint32_t CAN_TXBufferReady(CAN_TypeDef * CANx); +uint32_t CAN_RXDataAvailable(CAN_TypeDef * CANx); + +void CAN_SetBaudrate(CAN_TypeDef * CANx, uint32_t baudrate, uint32_t CAN_BS1, uint32_t CAN_BS2, uint32_t CAN_SJW); + +void CAN_SetFilter32b(CAN_TypeDef * CANx, uint32_t check, uint32_t mask); +void CAN_SetFilter16b(CAN_TypeDef * CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2); + + +void CAN_INTRXNotEmptyEn(CAN_TypeDef * CANx); +void CAN_INTRXNotEmptyDis(CAN_TypeDef * CANx); +uint32_t CAN_INTRXNotEmptyStat(CAN_TypeDef * CANx); + +void CAN_INTTXBufEmptyEn(CAN_TypeDef * CANx); +void CAN_INTTXBufEmptyDis(CAN_TypeDef * CANx); +uint32_t CAN_INTTXBufEmptyStat(CAN_TypeDef * CANx); + +void CAN_INTErrWarningEn(CAN_TypeDef * CANx); +void CAN_INTErrWarningDis(CAN_TypeDef * CANx); +uint32_t CAN_INTErrWarningStat(CAN_TypeDef * CANx); + +void CAN_INTRXOverflowEn(CAN_TypeDef * CANx); +void CAN_INTRXOverflowDis(CAN_TypeDef * CANx); +uint32_t CAN_INTRXOverflowStat(CAN_TypeDef * CANx); +void CAN_INTRXOverflowClear(CAN_TypeDef * CANx); + +void CAN_INTWakeupEn(CAN_TypeDef * CANx); +void CAN_INTWakeupDis(CAN_TypeDef * CANx); +uint32_t CAN_INTWakeupStat(CAN_TypeDef * CANx); + +void CAN_INTErrPassiveEn(CAN_TypeDef * CANx); +void CAN_INTErrPassiveDis(CAN_TypeDef * CANx); +uint32_t CAN_INTErrPassiveStat(CAN_TypeDef * CANx); + +void CAN_INTArbitrLostEn(CAN_TypeDef * CANx); +void CAN_INTArbitrLostDis(CAN_TypeDef * CANx); +uint32_t CAN_INTArbitrLostStat(CAN_TypeDef * CANx); + +void CAN_INTBusErrorEn(CAN_TypeDef * CANx); +void CAN_INTBusErrorDis(CAN_TypeDef * CANx); +uint32_t CAN_INTBusErrorStat(CAN_TypeDef * CANx); + +#endif //__SWM320_CAN_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_crc.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..52634deebbdfc8dc50e0019a53b8ece7fb5e1085 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_crc.c @@ -0,0 +1,51 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_crc.c +* ˵: SWM320ƬCRCģ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_crc.h" + + +/****************************************************************************************************************************************** +* : CRC_Init() +* ˵: CRC ʼ +* : CRC_TypeDef * CRCx ָҪõCRCӿڣЧֵCRC +* uint32_t mode ģʽЧֵУCRC32_IN32CRC32_IN16CRC32_IN8CRC16_IN16CRC16_IN8 +* uint32_t out_not Ƿȡ +* uint32_t out_rev Ƿת +* uint32_t ini_val CRCʼֵ +* : +* ע: +******************************************************************************************************************************************/ +void CRC_Init(CRC_TypeDef * CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val) +{ + switch((uint32_t)CRCx) + { + case ((uint32_t)CRC): + SYS->CLKEN |= (0x01 << SYS_CLKEN_CRC_Pos); + break; + } + + CRCx->CR = (1 << CRC_CR_EN_Pos) | + (mode << CRC_CR_CRC16_Pos) | + (out_not << CRC_CR_ONOT_Pos) | + (out_rev << CRC_CR_OREV_Pos); + + CRCx->INIVAL = ini_val; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_crc.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..ce9f1f3731b2bde8f0c346237239636b6f35bf26 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_crc.h @@ -0,0 +1,39 @@ +#ifndef __SWM320_CRC_H__ +#define __SWM320_CRC_H__ + + +#define CRC32_IN32 0 //CRC32㷨32λ +#define CRC32_IN16 2 //CRC32㷨16λ +#define CRC32_IN8 4 //CRC32㷨 8λ +#define CRC16_IN16 3 //CRC16㷨16λ +#define CRC16_IN8 5 //CRC16㷨 8λ + + +void CRC_Init(CRC_TypeDef * CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val); + + +/****************************************************************************************************************************************** +* : CRC_Write() +* ˵: CRCд +* : uint32_t data Ҫд +* : +* ע: +******************************************************************************************************************************************/ +static __INLINE void CRC_Write(uint32_t data) +{ + CRC->DATAIN = data; +} + +/****************************************************************************************************************************************** +* : CRC_Result() +* ˵: ȡCRC +* : +* : uint32_t CRC +* ע: +******************************************************************************************************************************************/ +static __INLINE uint32_t CRC_Result(void) +{ + return CRC->RESULT; +} + +#endif //__SWM320_CRC_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_dma.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..78db4ee2dddda277d49c353f1811aa69debb84d3 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_dma.c @@ -0,0 +1,138 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_dma.c +* ˵: SWM320ƬDMA +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_dma.h" + +/****************************************************************************************************************************************** +* : DMA_CHM_Config() +* ˵: DMAͨãڴ洢䣨FlashRAM䣩 +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH2 +* uint32_t src_addr Դֶַ룬ַ2λ00 +* uint32_t src_addr_incr 0 ̶ַ 1 ַ +* uint32_t dst_addr Ŀĵֶַ룬ַ2λ00 +* uint32_t dst_addr_incr 0 ̶ַ 1 ַ +* uint32_t num_word Ҫ˵1024 +* uint32_t int_en жʹܣ1 ݰɺж 0 ݰɺ󲻲ж +* : +* ע: ΪԪֽ +******************************************************************************************************************************************/ +void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en) +{ + DMA->EN = 1; //ÿͨԼĿؿƣܿؿһֱ + + DMA_CH_Close(chn); //ǰȹرոͨ + + DMA->CH[chn].SRC = src_addr; + DMA->CH[chn].DST = dst_addr; + + DMA->CH[chn].CR = ((num_word*4-1) << DMA_CR_LEN_Pos) | + (0 << DMA_CR_AUTORE_Pos); + + DMA->CH[chn].AM = (src_addr_incr << DMA_AM_SRCAM_Pos) | + (dst_addr_incr << DMA_AM_DSTAM_Pos) | + (0 << DMA_AM_BURST_Pos); + + DMA->IF = (1 << chn); //жϱ־ + DMA->IE |= (1 << chn); + if(int_en) DMA->IM &= ~(1 << chn); + else DMA->IM |= (1 << chn); + + if(int_en) + { + NVIC_EnableIRQ(DMA_IRQn); + } + else + { + //ܵNVIC_DisalbeIRQ(DMA_IRQn)ΪͨʹDMAж + } +} + +/****************************************************************************************************************************************** +* : DMA_CH_Open() +* ˵: DMAͨ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH2 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_Open(uint32_t chn) +{ + DMA->CH[chn].CR |= (1 << DMA_CR_TXEN_Pos); +} + +/****************************************************************************************************************************************** +* : DMA_CH_Close() +* ˵: DMAͨر +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH2 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_Close(uint32_t chn) +{ + DMA->CH[chn].CR &= ~(1 << DMA_CR_TXEN_Pos); +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTEn() +* ˵: DMAжʹܣݰɺ󴥷ж +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH2 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_INTEn(uint32_t chn) +{ + DMA->IM &= ~(1 << chn); +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTDis() +* ˵: DMAжϽֹݰɺ󲻴ж +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH2 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_INTDis(uint32_t chn) +{ + DMA->IM |= (1 << chn); +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTClr() +* ˵: DMAжϱ־ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH2 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_INTClr(uint32_t chn) +{ + DMA->IF = (1 << chn); +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTStat() +* ˵: DMAж״̬ѯ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH2 +* : uint32_t 1 ݰ 0 ݰδ +* ע: +******************************************************************************************************************************************/ +uint32_t DMA_CH_INTStat(uint32_t chn) +{ + return (DMA->IF & (1 << chn)) ? 1 : 0; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_dma.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..817162cd65a1c5612c9bf2fd348e7e7756ec4801 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_dma.h @@ -0,0 +1,20 @@ +#ifndef __SWM320_DMA_H__ +#define __SWM320_DMA_H__ + + +#define DMA_CH0 0 +#define DMA_CH1 1 +#define DMA_CH2 2 + + +void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en); //DMAͨãڴ洢䣨FlashRAM䣩 +void DMA_CH_Open(uint32_t chn); //DMAͨ +void DMA_CH_Close(uint32_t chn); //DMAͨر + +void DMA_CH_INTEn(uint32_t chn); //DMAжʹܣݰɺ󴥷ж +void DMA_CH_INTDis(uint32_t chn); //DMAжϽֹݰɺ󲻴ж +void DMA_CH_INTClr(uint32_t chn); //DMAжϱ־ +uint32_t DMA_CH_INTStat(uint32_t chn); //DMAж״̬ѯ1 ݰ 0 ݰδ + + +#endif //__SWM320_DMA_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_exti.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_exti.c new file mode 100644 index 0000000000000000000000000000000000000000..8275b602d17ff5efab1f49de9ff08194344191f0 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_exti.c @@ -0,0 +1,131 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_exti.c +* ˵: SWM320ƬⲿжϹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_exti.h" + +/****************************************************************************************************************************************** +* : EXTI_Init() +* ˵: ָⲿжϳʼ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t mode ЧֵEXTI_FALL_EDGEEXTI_RISE_EDGEEXTI_BOTH_EDGEEXTI_LOW_LEVELEXTI_HIGH_LEVEL +* : +* ע: GPIOAGPIOBGPIOCGPIOMPIN0--7żԽNVICежϣGPIOA0_IRQnҲԽNVICжϣGPIOA_IRQn +* Բڴ˺еNVIC_EnableIRQ()ʹNVICжϣӶԸҪNVIC_EnableIRQ(GPIOA0_IRQn)NVIC_EnableIRQ(GPIOA_IRQn) +******************************************************************************************************************************************/ +void EXTI_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t mode) +{ + EXTI_Close(GPIOx, n); //ùؼĴǰȹر + + if(mode & 0x10) + { + GPIOx->INTLVLTRG |= (0x01 << n); //ƽ + + if(mode & 0x01) + GPIOx->INTRISEEN |= (0x01 << n); //ߵƽ + else + GPIOx->INTRISEEN &= ~(0x01 << n); //͵ƽ + } + else + { + GPIOx->INTLVLTRG &= ~(0x01 << n); //ش + + if(mode & 0x02) + { + GPIOx->INTBE |= (0x01 << n); //˫ش + } + else + { + GPIOx->INTBE &= ~(0x01 << n); //ش + + if(mode & 0x01) + GPIOx->INTRISEEN |= (0x01 << n); //ش + else + GPIOx->INTRISEEN &= ~(0x01 << n); //½ش + } + } + + GPIOx->INTCLR = (1 << n); //Ϊģʽÿܲж +} + +/****************************************************************************************************************************************** +* : EXTI_Open() +* ˵: ָⲿжϴ򿪣ʹܣ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: +******************************************************************************************************************************************/ +void EXTI_Open(GPIO_TypeDef * GPIOx, uint32_t n) +{ + GPIOx->INTEN |= (0x01 << n); +} + +/****************************************************************************************************************************************** +* : EXTI_Close() +* ˵: ָⲿжϹرգܣ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: +******************************************************************************************************************************************/ +void EXTI_Close(GPIO_TypeDef * GPIOx, uint32_t n) +{ + GPIOx->INTEN &= ~(0x01 << n); +} + +/****************************************************************************************************************************************** +* : EXTI_State() +* ˵: ָǷ񴥷ж +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : uint32_t 1 Ŵж 0 δж +* ע: +******************************************************************************************************************************************/ +uint32_t EXTI_State(GPIO_TypeDef * GPIOx, uint32_t n) +{ + return (GPIOx->INTSTAT >> n) & 0x01; +} + +/****************************************************************************************************************************************** +* : EXTI_RawState() +* ˵: ָǷ/жϴжϹرʱͨô˺ԲѯķʽǷ/жϴ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : uint32_t 1 /жϴ 0 δ/жϴ +* ע: +******************************************************************************************************************************************/ +uint32_t EXTI_RawState(GPIO_TypeDef * GPIOx, uint32_t n) +{ + return (GPIOx->INTRAWSTAT >> n) & 0x01; +} + +/****************************************************************************************************************************************** +* : EXTI_Clear() +* ˵: ָⲿжжϱ־ٴνжϣ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: ֻشжϵı־ƽжϵı־޷ֻŵƽжϴӲԶ +******************************************************************************************************************************************/ +void EXTI_Clear(GPIO_TypeDef * GPIOx, uint32_t n) +{ + GPIOx->INTCLR = (0x01 << n); +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_exti.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_exti.h new file mode 100644 index 0000000000000000000000000000000000000000..088cd9a6197131f6d697d70826feaac8be41d349 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_exti.h @@ -0,0 +1,20 @@ +#ifndef __SWM320_EXTI_H__ +#define __SWM320_EXTI_H__ + +void EXTI_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t mode); //ָⲿжϳʼ +void EXTI_Open(GPIO_TypeDef * GPIOx, uint32_t n); //ָⲿжϴ򿪣ʹܣ +void EXTI_Close(GPIO_TypeDef * GPIOx, uint32_t n); //ָⲿжϹرգܣ + +uint32_t EXTI_State(GPIO_TypeDef * GPIOx, uint32_t n); //ָǷ񴥷ж +uint32_t EXTI_RawState(GPIO_TypeDef * GPIOx, uint32_t n); //ָǷ/жϴжϹرʱͨô˺ԲѯķʽǷ/жϴ +void EXTI_Clear(GPIO_TypeDef * GPIOx, uint32_t n); //ָⲿжжϱ־ٴνжϣ + + +#define EXTI_FALL_EDGE 0x00 //½شж +#define EXTI_RISE_EDGE 0x01 //شж +#define EXTI_BOTH_EDGE 0x02 //˫شж +#define EXTI_LOW_LEVEL 0x10 //͵ƽж +#define EXTI_HIGH_LEVEL 0x11 //ߵƽж + + +#endif //__SWM320_EXTI_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_flash.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..dbd0eca4bfc4a6236ffb58e0abc46ef3ef98fa0d --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_flash.c @@ -0,0 +1,81 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_flash.c +* ˵: ʹоƬIAPܽƬFlashģEEPROMݣ󲻶ʧ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_flash.h" + + +IAP_Cache_Reset_t IAP_Cache_Reset = (IAP_Cache_Reset_t)0x11000601; +IAP_Flash_Param_t IAP_Flash_Param = (IAP_Flash_Param_t)0x11000681; +IAP_Flash_Erase_t IAP_Flash_Erase = (IAP_Flash_Erase_t)0x11000781; +IAP_Flash_Write_t IAP_Flash_Write = (IAP_Flash_Write_t)0x11000801; + + +/****************************************************************************************************************************************** +* : FLASH_Erase() +* ˵: ƬFlash +* : uint32_t addr ַСΪ4K Byte +* : +* ע: +******************************************************************************************************************************************/ +void FLASH_Erase(uint32_t addr) +{ + __disable_irq(); + + IAP_Flash_Erase(addr / 0x1000); + + IAP_Cache_Reset(); + + __enable_irq(); +} + +/****************************************************************************************************************************************** +* : FLASH_Write() +* ˵: ƬFlashд +* : uint32_t addr дַ +* uint32_t buff[] Ҫд +* uint32_t count ҪдݵĸΪλұ4д4 +* : +* ע: дݸ4д4 +******************************************************************************************************************************************/ +void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t count) +{ + __disable_irq(); + + IAP_Flash_Write(addr, (uint32_t)buff, count/4); + + IAP_Cache_Reset(); + + __enable_irq(); +} + +/****************************************************************************************************************************************** +* : Flash_Param_at_120MHz() +* ˵: Flashó120MHzƵʱIJ +* : +* : +* ע: +******************************************************************************************************************************************/ +void Flash_Param_at_120MHz(void) +{ + __disable_irq(); + + IAP_Flash_Param(0x48a, 0xabfc7a6e); + + __enable_irq(); +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_flash.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..113e2a2e0708715b92799bf5c2609b9c560c1e43 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_flash.h @@ -0,0 +1,23 @@ +#ifndef __SWM320_FLASH_H__ +#define __SWM320_FLASH_H__ + + +void FLASH_Erase(uint32_t addr); +void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t count); + +void Flash_Param_at_120MHz(void); + + + +typedef void (*IAP_Cache_Reset_t)(void); +typedef void (*IAP_Flash_Param_t)(uint32_t cfg0, uint32_t cfg1); +typedef void (*IAP_Flash_Erase_t)(uint32_t sector); +typedef void (*IAP_Flash_Write_t)(uint32_t flash_addr, uint32_t ram_addr, uint32_t count); + +extern IAP_Cache_Reset_t IAP_Cache_Reset; +extern IAP_Flash_Param_t IAP_Flash_Param; +extern IAP_Flash_Erase_t IAP_Flash_Erase; +extern IAP_Flash_Write_t IAP_Flash_Write; + + +#endif //__SWM320_FLASH_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..1d2aa3a2ab42db595c96af39d98bcad6928aa2f6 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c @@ -0,0 +1,378 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_gpio.c +* ˵: SWM320Ƭͨ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_gpio.h" + + +/****************************************************************************************************************************************** +* : GPIO_Init() +* ˵: ųʼŷ衢衢© +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t dir ŷ0 1 +* uint32_t pull_up 裬0 ر 1 +* uint32_t pull_down 裬0 ر 1 +* : +* ע: GPIOAGPIOCGPIOMGPIOPֻGPIOBGPIONֻ +******************************************************************************************************************************************/ +void GPIO_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down) +{ + switch((uint32_t)GPIOx) + { + case ((uint32_t)GPIOA): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOA_Pos); + + PORT_Init(PORTA, n, 0, 1); //PORTA.PINnΪGPIOܣ뿪 + if(dir == 1) + { + GPIOA->DIR |= (0x01 << n); + } + else + { + GPIOA->DIR &= ~(0x01 << n); + } + + if(pull_up == 1) + PORT->PORTA_PULLU |= (0x01 << n); + else + PORT->PORTA_PULLU &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOB): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOB_Pos); + + PORT_Init(PORTB, n, 0, 1); //PORTB.PINnΪGPIOܣ뿪 + if(dir == 1) + { + GPIOB->DIR |= (0x01 << n); + } + else + { + GPIOB->DIR &= ~(0x01 << n); + } + + if(pull_down == 1) + PORT->PORTB_PULLD |= (0x01 << n); + else + PORT->PORTB_PULLD &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOC): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOC_Pos); + + PORT_Init(PORTC, n, 0, 1); //PORTC.PINnΪGPIOܣ뿪 + if(dir == 1) + { + GPIOC->DIR |= (0x01 << n); + } + else + { + GPIOC->DIR &= ~(0x01 << n); + } + + if(pull_up == 1) + PORT->PORTC_PULLU |= (0x01 << n); + else + PORT->PORTC_PULLU &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOM): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOM_Pos); + + PORT_Init(PORTM, n, 0, 1); //PORTM.PINnΪGPIOܣ뿪 + if(dir == 1) + { + GPIOM->DIR |= (0x01 << n); + } + else + { + GPIOM->DIR &= ~(0x01 << n); + } + + if(pull_up == 1) + PORT->PORTM_PULLU |= (0x01 << n); + else + PORT->PORTM_PULLU &= ~(0x01 << n); + break; + + case ((uint32_t)GPION): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPION_Pos); + + PORT_Init(PORTN, n, 0, 1); //PORTN.PINnΪGPIOܣ뿪 + if(dir == 1) + { + GPION->DIR |= (0x01 << n); + } + else + { + GPION->DIR &= ~(0x01 << n); + } + + if(pull_down == 1) + PORT->PORTN_PULLD |= (0x01 << n); + else + PORT->PORTN_PULLD &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOP): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOP_Pos); + + PORT_Init(PORTP, n, 0, 1); //PORTP.PINnΪGPIOܣ뿪 + if(dir == 1) + { + GPIOP->DIR |= (0x01 << n); + } + else + { + GPIOP->DIR &= ~(0x01 << n); + } + + if(pull_up == 1) + PORT->PORTP_PULLU |= (0x01 << n); + else + PORT->PORTP_PULLU &= ~(0x01 << n); + break; + } +} + +/****************************************************************************************************************************************** +* : GPIO_SetBit() +* ˵: ָŵƽø +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_SetBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + GPIOx->DATA |= (0x01 << n); +} + +/****************************************************************************************************************************************** +* : GPIO_ClrBit() +* ˵: ָŵƽõ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_ClrBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + GPIOx->DATA &= ~(0x01 << n); +} + +/****************************************************************************************************************************************** +* : GPIO_InvBit() +* ˵: ָŵƽת +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_InvBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + GPIOx->DATA ^= (0x01 << n); +} + +/****************************************************************************************************************************************** +* : GPIO_GetBit() +* ˵: ȡָŵĵƽ״̬ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : ָŵĵƽ״̬ 0 ͵ƽ 1 ߵƽ +* ע: +******************************************************************************************************************************************/ +uint32_t GPIO_GetBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + return ((GPIOx->DATA >> n) & 0x01); +} + +/****************************************************************************************************************************************** +* : GPIO_SetBits() +* ˵: ָĴnʼwλŵĵƽø +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t w ָҪŵƽøߵŵĸ +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_SetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + GPIOx->DATA |= (bits << n); +} + +/****************************************************************************************************************************************** +* : GPIO_ClrBits() +* ˵: ָĴnʼwλŵĵƽõ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t w ָҪŵƽõ͵ŵĸ +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_ClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + GPIOx->DATA &= ~(bits << n); +} + +/****************************************************************************************************************************************** +* : GPIO_InvBits() +* ˵: ָĴnʼwλŵĵƽת +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t w ָҪŵƽתŵĸ +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_InvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + GPIOx->DATA ^= (bits << n); +} + +/****************************************************************************************************************************************** +* : GPIO_GetBits() +* ˵: ȡָĴnʼwλŵĵƽ״̬ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t w ָҪŵƽøߵŵĸ +* : ָĴnʼwλŵĵƽ״̬ 0 ͵ƽ 1 ߵƽ +* ֵĵ0λʾnĵƽ״ֵ̬ĵ1λʾn+1ĵƽ״̬... ...ֵĵwλʾn+wĵƽ״̬ +* ע: +******************************************************************************************************************************************/ +uint32_t GPIO_GetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + return ((GPIOx->DATA >> n) & bits); +} + +/****************************************************************************************************************************************** +* : GPIO_AtomicSetBit() +* ˵: ָŵƽøߣȷš--дԭԣжISRϣ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOD +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : +* ע: GPIOx16УЩѭвЩжISRвʱGPIOxű붼GPIO_Atomicͺ +******************************************************************************************************************************************/ +void GPIO_AtomicSetBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000)*32 + n*4)) = 1; +} + +/****************************************************************************************************************************************** +* : GPIO_AtomicClrBit() +* ˵: ָŵƽõͣȷš--дԭԣжISRϣ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOD +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : +* ע: GPIOx16УЩѭвЩжISRвʱGPIOxű붼GPIO_Atomicͺ +******************************************************************************************************************************************/ +void GPIO_AtomicClrBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000)*32 + n*4)) = 0; +} + +/****************************************************************************************************************************************** +* : GPIO_AtomicInvBit() +* ˵: ָŵƽתȷš--дԭԣжISRϣ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOD +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : +* ע: GPIOx16УЩѭвЩжISRвʱGPIOxű붼GPIO_Atomicͺ +******************************************************************************************************************************************/ +void GPIO_AtomicInvBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000)*32 + n*4)) = 1 - *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000)*32 + n*4)); +} + +/****************************************************************************************************************************************** +* : GPIO_AtomicSetBits() +* ˵: ָĴnʼwλŵĵƽøߣȷš--дԭԣжISRϣ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOD +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t w ָҪŵƽøߵŵĸ +* : +* ע: GPIOx16УЩѭвЩжISRвʱGPIOxű붼GPIO_Atomicͺ +******************************************************************************************************************************************/ +void GPIO_AtomicSetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + __disable_irq(); + GPIOx->DATA |= (bits << n); + __enable_irq(); +} + +/****************************************************************************************************************************************** +* : GPIO_AtomicClrBits() +* ˵: ָĴnʼwλŵĵƽõͣȷš--дԭԣжISRϣ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOD +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t w ָҪŵƽõ͵ŵĸ +* : +* ע: GPIOx16УЩѭвЩжISRвʱGPIOxű붼GPIO_Atomicͺ +******************************************************************************************************************************************/ +void GPIO_AtomicClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + __disable_irq(); + GPIOx->DATA &= ~(bits << n); + __enable_irq(); +} + +/****************************************************************************************************************************************** +* : GPIO_AtomicInvBits() +* ˵: ָĴnʼwλŵĵƽתȷš--дԭԣжISRϣ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOD +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t w ָҪŵƽתŵĸ +* : +* ע: GPIOx16УЩѭвЩжISRвʱGPIOxű붼GPIO_Atomicͺ +******************************************************************************************************************************************/ +void GPIO_AtomicInvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + __disable_irq(); + GPIOx->DATA ^= (bits << n); + __enable_irq(); +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..bcb59b0bee6f4ba4f42ec212cc7b2800b3eb1a44 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h @@ -0,0 +1,24 @@ +#ifndef __SWM320_GPIO_H__ +#define __SWM320_GPIO_H__ + + +void GPIO_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down); //ųʼŷ衢 + +void GPIO_SetBit(GPIO_TypeDef * GPIOx, uint32_t n); //ָŵƽø +void GPIO_ClrBit(GPIO_TypeDef * GPIOx, uint32_t n); //ָŵƽõ +void GPIO_InvBit(GPIO_TypeDef * GPIOx, uint32_t n); //ָŵƽת +uint32_t GPIO_GetBit(GPIO_TypeDef * GPIOx, uint32_t n); //ȡָŵĵƽ״̬ +void GPIO_SetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽø +void GPIO_ClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽõ +void GPIO_InvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽת +uint32_t GPIO_GetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //ȡָĴnʼwλŵĵƽ״̬ + +void GPIO_AtomicSetBit(GPIO_TypeDef * GPIOx, uint32_t n); +void GPIO_AtomicClrBit(GPIO_TypeDef * GPIOx, uint32_t n); +void GPIO_AtomicInvBit(GPIO_TypeDef * GPIOx, uint32_t n); +void GPIO_AtomicSetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); +void GPIO_AtomicClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); +void GPIO_AtomicInvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); + + +#endif //__SWM320_GPIO_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..04c414085f9cb6483d1436d0a0a1ab6f6a41d6c7 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c @@ -0,0 +1,215 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_i2c.c +* ˵: SWM320ƬI2Cнӿڹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIES AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIEE. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIES ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_i2c.h" + +/****************************************************************************************************************************************** +* : I2C_Init() +* ˵: I2Cʼ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* I2C_InitStructure * initStruct I2C趨ֵĽṹ +* : +* ע: ģֻܹģʽ +******************************************************************************************************************************************/ +void I2C_Init(I2C_TypeDef * I2Cx, I2C_InitStructure * initStruct) +{ + switch((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_I2C0_Pos); + break; + + case ((uint32_t)I2C1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_I2C1_Pos); + break; + } + + I2C_Close(I2Cx); //һЩؼĴֻI2Cرʱ + + if(initStruct->Master == 1) + { + I2Cx->CLKDIV = SystemCoreClock/5/initStruct->MstClk; + + I2Cx->MSTCMD = (I2Cx->MSTCMD & (~I2C_MSTCMD_IF_Msk)) | (1 << I2C_MSTCMD_IF_Pos); //ʹж֮ǰжϱ־ + I2Cx->CTRL &= ~I2C_CTRL_MSTIE_Msk; + I2Cx->CTRL |= (initStruct->MstIEn << I2C_CTRL_MSTIE_Pos); + + switch((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + if(initStruct->MstIEn) + { + NVIC_EnableIRQ(I2C0_IRQn); + } + else + { + NVIC_DisableIRQ(I2C0_IRQn); + } + break; + + case ((uint32_t)I2C1): + if(initStruct->MstIEn) + { + NVIC_EnableIRQ(I2C1_IRQn); + } + else + { + NVIC_DisableIRQ(I2C1_IRQn); + } + break; + } + } + else + { + I2Cx->SLVCR |= (1 << I2C_SLVCR_SLAVE_Pos); + + I2Cx->SLVCR &= ~(I2C_SLVCR_ADDR7b_Msk | I2C_SLVCR_ADDR_Msk); + I2Cx->SLVCR |= (1 << I2C_SLVCR_ACK_Pos) | + (initStruct->Addr7b << I2C_SLVCR_ADDR7b_Pos) | + (initStruct->SlvAddr << I2C_SLVCR_ADDR_Pos); + + I2Cx->SLVIF = I2C_SLVIF_RXEND_Msk | I2C_SLVIF_TXEND_Msk | I2C_SLVIF_STADET_Msk | I2C_SLVIF_STODET_Msk; //жϱ־ + I2Cx->SLVCR &= ~(I2C_SLVCR_IM_RXEND_Msk | I2C_SLVCR_IM_TXEND_Msk | I2C_SLVCR_IM_STADET_Msk | I2C_SLVCR_IM_STODET_Msk | + I2C_SLVCR_IM_RDREQ_Msk | I2C_SLVCR_IM_WRREQ_Msk); + I2Cx->SLVCR |= ((initStruct->SlvRxEndIEn ? 0 : 1) << I2C_SLVCR_IM_RXEND_Pos) | + ((initStruct->SlvTxEndIEn ? 0 : 1) << I2C_SLVCR_IM_TXEND_Pos) | + ((initStruct->SlvSTADetIEn ? 0 : 1) << I2C_SLVCR_IM_STADET_Pos) | + ((initStruct->SlvSTODetIEn ? 0 : 1) << I2C_SLVCR_IM_STODET_Pos) | + ((initStruct->SlvRdReqIEn ? 0 : 1) << I2C_SLVCR_IM_RDREQ_Pos) | + ((initStruct->SlvWrReqIEn ? 0 : 1) << I2C_SLVCR_IM_WRREQ_Pos); + + switch((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + if(initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn | + initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) + { + NVIC_EnableIRQ(I2C0_IRQn); + } + else + { + NVIC_DisableIRQ(I2C0_IRQn); + } + break; + + case ((uint32_t)I2C1): + if(initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn | + initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) + { + NVIC_EnableIRQ(I2C1_IRQn); + } + else + { + NVIC_DisableIRQ(I2C1_IRQn); + } + break; + } + } +} + +/****************************************************************************************************************************************** +* : I2C_Open() +* ˵: I2C򿪣շ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* : +* ע: +******************************************************************************************************************************************/ +void I2C_Open(I2C_TypeDef * I2Cx) +{ + I2Cx->CTRL |= (0x01 << I2C_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : I2C_Close() +* ˵: I2Cرգֹշ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* : +* ע: +******************************************************************************************************************************************/ +void I2C_Close(I2C_TypeDef * I2Cx) +{ + I2Cx->CTRL &= ~I2C_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* : I2C_Start() +* ˵: ʼźŲ豸ַ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* uint8_t addr 豸ַ +* : uint8_t 1 յACK 0 յNACK +* ע: +******************************************************************************************************************************************/ +uint8_t I2C_Start(I2C_TypeDef * I2Cx, uint8_t addr) +{ + I2Cx->MSTDAT = addr; + I2Cx->MSTCMD = (1 << I2C_MSTCMD_STA_Pos) | + (1 << I2C_MSTCMD_WR_Pos); //ʼλʹӻַ + while(I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) __NOP(); //ȴ + + return (I2Cx->MSTCMD & I2C_MSTCMD_RXACK_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : I2C_Stop() +* ˵: ֹͣź +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* : +* ע: +******************************************************************************************************************************************/ +void I2C_Stop(I2C_TypeDef * I2Cx) +{ + I2Cx->MSTCMD = (1 << I2C_MSTCMD_STO_Pos); + while(I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) __NOP(); //ȴ +} + +/****************************************************************************************************************************************** +* : I2C_Write() +* ˵: дһ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* uint8_t data Ҫд +* : uint8_t 1 յACK 0 յNACK +* ע: +******************************************************************************************************************************************/ +uint8_t I2C_Write(I2C_TypeDef * I2Cx, uint8_t data) +{ + I2Cx->MSTDAT = data; + I2Cx->MSTCMD = (1 << I2C_MSTCMD_WR_Pos); + while(I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) __NOP(); //ȴ + + return (I2Cx->MSTCMD & I2C_MSTCMD_RXACK_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : I2C_Read() +* ˵: ȡһ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* uint8_t ack 1 ACK 0 NACK +* : uint8_t ȡ +* ע: +******************************************************************************************************************************************/ +uint8_t I2C_Read(I2C_TypeDef * I2Cx, uint8_t ack) +{ + I2Cx->MSTCMD = (1 << I2C_MSTCMD_RD_Pos) | + ((ack ? 0 : 1) << I2C_MSTCMD_ACK_Pos); + while(I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) __NOP(); //ȴ + + return I2Cx->MSTDAT; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..fc52e9265ecd8b44cfe386a54777b07efec06f99 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h @@ -0,0 +1,31 @@ +#ifndef __SWM320_I2C_H__ +#define __SWM320_I2C_H__ + +typedef struct { + uint8_t Master; //1 ģʽ + uint8_t Addr7b; //1 7λַ 0 10λַ + + uint32_t MstClk; //ʱƵ + uint8_t MstIEn; //ģʽжʹ + + uint16_t SlvAddr; //ӻַ + uint8_t SlvRxEndIEn; //ӻжʹ + uint8_t SlvTxEndIEn; //ӻжʹ + uint8_t SlvSTADetIEn; //ӻ⵽ʼжʹ + uint8_t SlvSTODetIEn; //ӻ⵽ֹжʹ + uint8_t SlvRdReqIEn; //ӻյжʹ + uint8_t SlvWrReqIEn; //ӻյджʹ +} I2C_InitStructure; + + +void I2C_Init(I2C_TypeDef * I2Cx, I2C_InitStructure * initStruct); + +void I2C_Open(I2C_TypeDef * I2Cx); +void I2C_Close(I2C_TypeDef * I2Cx); + +uint8_t I2C_Start(I2C_TypeDef * I2Cx, uint8_t addr); +void I2C_Stop(I2C_TypeDef * I2Cx); +uint8_t I2C_Write(I2C_TypeDef * I2Cx, uint8_t data); +uint8_t I2C_Read(I2C_TypeDef * I2Cx, uint8_t ack); + +#endif //__SWM320_I2C_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c new file mode 100644 index 0000000000000000000000000000000000000000..5220cb80469583f15370991bb7ec4e73ddf1488d --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c @@ -0,0 +1,154 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_lcd.c +* ˵: SWM320ƬLCD +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_lcd.h" + +#include + +/****************************************************************************************************************************************** +* : LCD_Init() +* ˵: LCDʼ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* LCD_InitStructure * initStruct LCD趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void LCD_Init(LCD_TypeDef * LCDx, LCD_InitStructure * initStruct) +{ + switch((uint32_t)LCDx) + { + case ((uint32_t)LCD): + SYS->CLKEN |= (0x01 << SYS_CLKEN_LCD_Pos); + break; + } + + if(initStruct->Interface == LCD_INTERFACE_RGB) + { + LCDx->START = (0 << LCD_START_MPUEN_Pos); + + LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_HPIX_Pos) | + ((initStruct->VnPixel - 1) << LCD_CR0_VPIX_Pos) | + (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | + (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); + + LCDx->CR1 = ((initStruct->Hfp - 1) << LCD_CR1_HFP_Pos) | + ((initStruct->Hbp - 1) << LCD_CR1_HBP_Pos) | + ((initStruct->Vfp - 1) << LCD_CR1_VFP_Pos) | + ((initStruct->Vbp - 1) << LCD_CR1_VBP_Pos) | + (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | + (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); + } + else if(initStruct->Interface == LCD_INTERFACE_I80) + { + // + } + + LCDx->IE = 1; + LCDx->IF = 1; //־ + if(initStruct->IntEOTEn) LCD_INTEn(LCDx); + else LCD_INTDis(LCDx); + + switch((uint32_t)LCDx) + { + case ((uint32_t)LCD): + if(initStruct->IntEOTEn) + { + NVIC_EnableIRQ(LCD_IRQn); + } + else + { + NVIC_DisableIRQ(LCD_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : LCD_Start() +* ˵: һݴ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : +* ע: +******************************************************************************************************************************************/ +void LCD_Start(LCD_TypeDef * LCDx) +{ + LCDx->START |= (1 << LCD_START_GO_Pos) | (1 << LCD_START_BURST_Pos); +} + +/****************************************************************************************************************************************** +* : LCD_IsBusy() +* ˵: Ƿڽݴ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : uint32_t 1 ڴ 0 ݴ +* ע: +******************************************************************************************************************************************/ +uint32_t LCD_IsBusy(LCD_TypeDef * LCDx) +{ + return (LCDx->START & LCD_START_GO_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : LCD_INTEn() +* ˵: LCDжʹܣָȵݴʱж +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : +* ע: +******************************************************************************************************************************************/ +void LCD_INTEn(LCD_TypeDef * LCDx) +{ + LCDx->IM = 0; +} + +/****************************************************************************************************************************************** +* : LCD_INTDis() +* ˵: LCDжϽָֹȵݴʱж +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : +* ע: +******************************************************************************************************************************************/ +void LCD_INTDis(LCD_TypeDef * LCDx) +{ + LCDx->IM = 1; +} + +/****************************************************************************************************************************************** +* : LCD_INTClr() +* ˵: LCDжϱ־ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : +* ע: +******************************************************************************************************************************************/ +void LCD_INTClr(LCD_TypeDef * LCDx) +{ + LCDx->IF = 1; +} + +/****************************************************************************************************************************************** +* : LCD_INTStat() +* ˵: LCDж״̬ѯ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : uint32_t 1 ָȵݴ 0 δָȵݴ +* ע: +******************************************************************************************************************************************/ +uint32_t LCD_INTStat(LCD_TypeDef * LCDx) +{ + return (LCDx->IF & 0x01) ? 1 : 0; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..490af3162fc451e716a12867e30a5c1fc720932f --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h @@ -0,0 +1,80 @@ +#ifndef __SWM320_LCD_H__ +#define __SWM320_LCD_H__ + + +typedef struct { + uint8_t Interface; //LCDӿڣLCD_INTERFACE_RGBLCD_INTERFACE_I80LCD_INTERFACE_M68 + + /* RGBͬӿڲ */ + uint16_t HnPixel; //ˮƽظȡֵ1024 + uint16_t VnPixel; //ֱظȡֵ 768 + uint8_t Hfp; //horizonal front porchȡֵ32 + uint8_t Hbp; //horizonal back porch ȡֵ128 + uint8_t Vfp; //vertical front porch ȡֵ8 + uint8_t Vbp; //vertical back porch ȡֵ32 + uint8_t ClkDiv; //ϵͳʱӾClkDivƵDOCCLK0 2Ƶ 1 4Ƶ 2 6Ƶ ... ... 31 64Ƶ + uint8_t SamplEdge; //ĻDOTCLKĸزݣLCD_SAMPLEDGE_RISELCD_SAMPLEDGE_FALL + uint8_t ClkAlways; //1 һֱDOTCLK 0 ֻڴʱDOTCLK + uint8_t HsyncWidth; //HSYNC͵ƽٸDOTCLKȡֵLCD_HSYNC_1DOTCLKLCD_HSYNC_2DOTCLKLCD_HSYNC_3DOTCLKLCD_HSYNC_4DOTCLK + + uint8_t IntEOTEn; //End of Transterɣжʹ +} LCD_InitStructure; + + +#define LCD_INTERFACE_RGB 0 +#define LCD_INTERFACE_I80 1 +#define LCD_INTERFACE_M68 2 + +#define LCD_SAMPLEDGE_RISE 0 //ĻDOTCLKز +#define LCD_SAMPLEDGE_FALL 1 //ĻDOTCLK½ز + +#define LCD_HSYNC_1DOTCLK 0 //1DOTCLK +#define LCD_HSYNC_2DOTCLK 1 +#define LCD_HSYNC_3DOTCLK 2 +#define LCD_HSYNC_4DOTCLK 3 + +#define LCD_CLKDIV_2 0 +#define LCD_CLKDIV_4 1 +#define LCD_CLKDIV_6 2 +#define LCD_CLKDIV_8 3 +#define LCD_CLKDIV_10 4 +#define LCD_CLKDIV_12 5 +#define LCD_CLKDIV_14 6 +#define LCD_CLKDIV_16 7 +#define LCD_CLKDIV_18 8 +#define LCD_CLKDIV_20 9 +#define LCD_CLKDIV_22 10 +#define LCD_CLKDIV_24 11 +#define LCD_CLKDIV_26 12 +#define LCD_CLKDIV_28 13 +#define LCD_CLKDIV_30 14 +#define LCD_CLKDIV_32 15 +#define LCD_CLKDIV_34 16 +#define LCD_CLKDIV_36 17 +#define LCD_CLKDIV_38 18 +#define LCD_CLKDIV_40 19 +#define LCD_CLKDIV_42 20 +#define LCD_CLKDIV_44 21 +#define LCD_CLKDIV_46 22 +#define LCD_CLKDIV_48 23 +#define LCD_CLKDIV_50 24 +#define LCD_CLKDIV_52 25 +#define LCD_CLKDIV_54 26 +#define LCD_CLKDIV_56 27 +#define LCD_CLKDIV_58 28 +#define LCD_CLKDIV_60 29 +#define LCD_CLKDIV_62 30 +#define LCD_CLKDIV_64 31 + + +void LCD_Init(LCD_TypeDef * LCDx, LCD_InitStructure * initStruct); +void LCD_Start(LCD_TypeDef * LCDx); +uint32_t LCD_IsBusy(LCD_TypeDef * LCDx); + +void LCD_INTEn(LCD_TypeDef * LCDx); +void LCD_INTDis(LCD_TypeDef * LCDx); +void LCD_INTClr(LCD_TypeDef * LCDx); +uint32_t LCD_INTStat(LCD_TypeDef * LCDx); + + +#endif //__SWM320_LCD_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c new file mode 100644 index 0000000000000000000000000000000000000000..d811ea46e888d2854b07409e960f37235d719827 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c @@ -0,0 +1,172 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_norflash.c +* ˵: SWM320ƬNOR Flash +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_norflash.h" + + +/****************************************************************************************************************************************** +* : NORFL_Init() +* ˵: NOR Flashʼ +* : NORFL_InitStructure * initStruct NOR Flash趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void NORFL_Init(NORFL_InitStructure * initStruct) +{ + uint32_t i; + + // SRAMǰҪˢSDRAM + do { + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + while(SDRAMC->REFDONE == 0); + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); + + for(i = 0; i < 1000; i++) __NOP(); + SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); + } while(0); + + SYS->CLKEN |= (1 << SYS_CLKEN_NORFL_Pos); + + NORFLC->CR = ((initStruct->DataWidth == 8 ? 1 : 0) << NORFLC_CR_BYTEIF_Pos) | + (initStruct->WELowPulseTime << NORFLC_CR_WRTIME_Pos) | + (initStruct->OEPreValidTime << NORFLC_CR_RDTIME_Pos); + + NORFLC->IE = 3; + NORFLC->IF = 3; // жϱ־ + if(initStruct->OperFinishIEn) NORFLC->IM &= ~(1 << NORFLC_IM_FINISH_Pos); + else NORFLC->IM |= (1 << NORFLC_IM_FINISH_Pos); + if(initStruct->OperTimeoutIEn) NORFLC->IM &= ~(1 << NORFLC_IM_TIMEOUT_Pos); + else NORFLC->IM |= (1 << NORFLC_IM_TIMEOUT_Pos); +} + +/****************************************************************************************************************************************** +* : NORFL_ChipErase() +* ˵: NOR FlashƬ +* : +* : uint32_t 0 ɹ 1 ʱ +* ע: +******************************************************************************************************************************************/ +uint32_t NORFL_ChipErase(void) +{ + uint32_t res; + + NORFLC->CMD = (NORFL_CMD_CHIP_ERASE << NORFLC_CMD_CMD_Pos); + + while(((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + + if(NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; + else res = 1; + + NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; + + return res; +} + +/****************************************************************************************************************************************** +* : NORFL_SectorErase() +* ˵: NOR Flash +* : uint32_t addr Ҫʼַ +* : uint32_t 0 ɹ 1 ʱ +* ע: MX29LV128DB ǰ8Ϊ8K255Ϊ64K MX29LV128DT ǰ255Ϊ64K8Ϊ8K +******************************************************************************************************************************************/ +uint32_t NORFL_SectorErase(uint32_t addr) +{ + uint32_t res; + + NORFLC->ADDR = addr; + NORFLC->CMD = (NORFL_CMD_SECTOR_ERASE << NORFLC_CMD_CMD_Pos); + + while(((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + + if(NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; + else res = 1; + + NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; + + return res; +} + +/****************************************************************************************************************************************** +* : NORFL_Write() +* ˵: NOR Flashд +* : uint32_t addr Ҫдĵַ +* uint32_t data Ҫд +* : uint32_t 0 дɹ 1 д볬ʱ +* ע: ӲӣΪ16λʱд룻Ϊ8λʱֽд +******************************************************************************************************************************************/ +uint32_t NORFL_Write(uint32_t addr, uint32_t data) +{ + uint32_t res; + + NORFLC->ADDR = addr; + NORFLC->CMD = (NORFL_CMD_PROGRAM << NORFLC_CMD_CMD_Pos) | (data << NORFLC_CMD_DATA_Pos); + + while(((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + + if(NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; + else res = 1; + + NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; + + return res; +} + +/****************************************************************************************************************************************** +* : NORFL_Read() +* ˵: NOR Flash +* : uint32_t addr Ҫĵַ +* : uint32_t +* ע: ӲӣΪ16λʱֶΪ8λʱֽڶ +******************************************************************************************************************************************/ +uint32_t NORFL_Read(uint32_t addr) +{ + NORFLC->ADDR = addr; + NORFLC->CMD = (NORFL_CMD_READ << NORFLC_CMD_CMD_Pos); + + return (NORFLC->CMD & NORFLC_CMD_DATA_Msk); +} + +/****************************************************************************************************************************************** +* : NORFL_ReadID() +* ˵: NOR FlashID +* : uint32_t id_addr IDַ˲оƬصģÿоƬͬ +* : uint16_t ȡID +* ע: +******************************************************************************************************************************************/ +uint16_t NORFL_ReadID(uint32_t id_addr) +{ + uint16_t id; + + NORFLC->CMD = (NORFL_CMD_AUTO_SELECT << NORFLC_CMD_CMD_Pos); + + NORFLC->ADDR = id_addr; + NORFLC->CMD = (NORFL_CMD_READ << NORFLC_CMD_CMD_Pos); + + id = NORFLC->CMD & NORFLC_CMD_DATA_Msk; + + NORFLC->CMD = (NORFL_CMD_RESET << NORFLC_CMD_CMD_Pos); // ˳IDȡģʽ + + return id; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h new file mode 100644 index 0000000000000000000000000000000000000000..23f7e5f902f192cc4dce78e4854030cfc7e6042c --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h @@ -0,0 +1,38 @@ +#ifndef __SWM320_NORFLASH_H__ +#define __SWM320_NORFLASH_H__ + +typedef struct { + uint8_t DataWidth; // 816 + + uint8_t WELowPulseTime; // WE# pulse widthλΪϵͳʱڣֵΪ7 + uint8_t OEPreValidTime; // Valid data output after OE# lowλΪϵͳʱڣֵΪ15 + + uint8_t OperFinishIEn; // (д롢)жʹ + uint8_t OperTimeoutIEn; +} NORFL_InitStructure; + + + +void NORFL_Init(NORFL_InitStructure * initStruct); +uint32_t NORFL_ChipErase(void); +uint32_t NORFL_SectorErase(uint32_t addr); +uint32_t NORFL_Write(uint32_t addr, uint32_t data); +uint32_t NORFL_Read(uint32_t addr); +uint16_t NORFL_ReadID(uint32_t id_addr); + + +/* ǰ汾߶ֶֻ֧ +#define NORFL_Read8(addr) *((volatile uint8_t *)(NORFLM_BASE + addr)) +#define NORFL_Read16(addr) *((volatile uint16_t *)(NORFLM_BASE + addr)) */ +#define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr)) + + + +#define NORFL_CMD_READ 0 +#define NORFL_CMD_RESET 1 +#define NORFL_CMD_AUTO_SELECT 2 +#define NORFL_CMD_PROGRAM 3 +#define NORFL_CMD_CHIP_ERASE 4 +#define NORFL_CMD_SECTOR_ERASE 5 + +#endif // __SWM320_NORFLASH_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_port.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_port.c new file mode 100644 index 0000000000000000000000000000000000000000..af21c1ffebd27feaacbb24c4f0db5348d90288c7 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_port.c @@ -0,0 +1,221 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_port.c +* ˵: SWM320ƬĶ˿Źѡ⺯ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_port.h" + + +/****************************************************************************************************************************************** +* : PORT_Init() +* ˵: ˿Źѡ񣬿õĹܼ"SWM320_port.h"ļ +* : uint32_t PORTx ָPORT˿ڣЧֵPORTAPORTBPORTCPORTMPORTNPORTP +* uint32_t n ָPORTţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t func ָ˿Ҫ趨Ĺܣȡֵ"SWM320_port.h"ļ +* uint32_t digit_in_en ʹ +* : +* ע: űnΪżʱfuncȡֵֻFUNMUX0ͷģFUNMUX0_UART0_RXD +* űnΪʱfuncȡֵֻFUNMUX1ͷģFUNMUX1_UART0_TXD +******************************************************************************************************************************************/ +void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en) +{ + switch((uint32_t)PORTx) + { + case ((uint32_t)PORTA): + if(func > 99) + { + if(n < PIN6) + { + PORT->PORTA_MUX0 &= ~(0x1F << (n*5)); + PORT->PORTA_MUX0 |= (func-100) << (n*5); + } + else if(n < PIN12) + { + PORT->PORTA_MUX1 &= ~(0x1F << ((n-6)*5)); + PORT->PORTA_MUX1 |= (func-100) << ((n-6)*5); + } + } + + PORT->PORTA_SEL &= ~(0x03 << (n*2)); + PORT->PORTA_SEL |= (func > 99 ? 1 : func) << (n*2); + + PORT->PORTA_INEN &= ~(0x01 << n); + PORT->PORTA_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTB): + if(func > 99) + { + if(n < PIN6) + { + PORT->PORTB_MUX0 &= ~(0x1F << (n*5)); + PORT->PORTB_MUX0 |= (func-100) << (n*5); + } + else if(n < PIN12) + { + PORT->PORTB_MUX1 &= ~(0x1F << ((n-6)*5)); + PORT->PORTB_MUX1 |= (func-100) << ((n-6)*5); + } + } + + PORT->PORTB_SEL &= ~(0x03 << (n*2)); + PORT->PORTB_SEL |= (func > 99 ? 1 : func) << (n*2); + + PORT->PORTB_INEN &= ~(0x01 << n); + PORT->PORTB_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTC): + if(func > 99) + { + if(n < PIN6) + { + PORT->PORTC_MUX0 &= ~(0x1F << (n*5)); + PORT->PORTC_MUX0 |= (func-100) << (n*5); + } + else if(n < PIN12) + { + PORT->PORTC_MUX1 &= ~(0x1F << ((n-6)*5)); + PORT->PORTC_MUX1 |= (func-100) << ((n-6)*5); + } + } + + PORT->PORTC_SEL &= ~(0x03 << (n*2)); + PORT->PORTC_SEL |= (func > 99 ? 1 : func) << (n*2); + + PORT->PORTC_INEN &= ~(0x01 << n); + PORT->PORTC_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTM): + if(func > 99) + { + if(n < PIN6) + { + PORT->PORTM_MUX0 &= ~(0x1F << (n*5)); + PORT->PORTM_MUX0 |= (func-100) << (n*5); + } + else if(n < PIN12) + { + PORT->PORTM_MUX1 &= ~(0x1F << ((n-6)*5)); + PORT->PORTM_MUX1 |= (func-100) << ((n-6)*5); + } + else if(n < PIN18) + { + PORT->PORTM_MUX2 &= ~(0x1F << ((n-12)*5)); + PORT->PORTM_MUX2 |= (func-100) << ((n-12)*5); + } + else if(n < PIN24) + { + PORT->PORTM_MUX3 &= ~(0x1F << ((n-18)*5)); + PORT->PORTM_MUX3 |= (func-100) << ((n-18)*5); + } + } + + if(n < 16) + { + PORT->PORTM_SEL0 &= ~(0x03 << (n*2)); + PORT->PORTM_SEL0 |= (func > 99 ? 1 : func) << (n*2); + } + else + { + PORT->PORTM_SEL1 &= ~(0x03 << ((n-16)*2)); + PORT->PORTM_SEL1 |= (func > 99 ? 1 : func) << ((n-16)*2); + } + + PORT->PORTM_INEN &= ~(0x01 << n); + PORT->PORTM_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTN): + if(func > 99) + { + if(n < PIN6) + { + PORT->PORTN_MUX0 &= ~(0x1F << (n*5)); + PORT->PORTN_MUX0 |= (func-100) << (n*5); + } + else if(n < PIN12) + { + PORT->PORTN_MUX1 &= ~(0x1F << ((n-6)*5)); + PORT->PORTN_MUX1 |= (func-100) << ((n-6)*5); + } + else if(n < PIN18) + { + PORT->PORTN_MUX2 &= ~(0x1F << ((n-12)*5)); + PORT->PORTN_MUX2 |= (func-100) << ((n-12)*5); + } + } + + if(n < 16) + { + PORT->PORTN_SEL0 &= ~(0x03 << (n*2)); + PORT->PORTN_SEL0 |= (func > 99 ? 1 : func) << (n*2); + } + else + { + PORT->PORTN_SEL1 &= ~(0x03 << ((n-16)*2)); + PORT->PORTN_SEL1 |= (func > 99 ? 1 : func) << ((n-16)*2); + } + + PORT->PORTN_INEN &= ~(0x01 << n); + PORT->PORTN_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTP): + if(func > 99) + { + if(n < PIN6) + { + PORT->PORTP_MUX0 &= ~(0x1F << (n*5)); + PORT->PORTP_MUX0 |= (func-100) << (n*5); + } + else if(n < PIN12) + { + PORT->PORTP_MUX1 &= ~(0x1F << ((n-6)*5)); + PORT->PORTP_MUX1 |= (func-100) << ((n-6)*5); + } + else if(n < PIN18) + { + PORT->PORTP_MUX2 &= ~(0x1F << ((n-12)*5)); + PORT->PORTP_MUX2 |= (func-100) << ((n-12)*5); + } + else if(n < PIN24) + { + PORT->PORTP_MUX3 &= ~(0x1F << ((n-18)*5)); + PORT->PORTP_MUX3 |= (func-100) << ((n-18)*5); + } + } + + if(n < 16) + { + PORT->PORTP_SEL0 &= ~(0x03 << (n*2)); + PORT->PORTP_SEL0 |= (func > 99 ? 1 : func) << (n*2); + } + else + { + PORT->PORTP_SEL1 &= ~(0x03 << ((n-16)*2)); + PORT->PORTP_SEL1 |= (func > 99 ? 1 : func) << ((n-16)*2); + } + + PORT->PORTP_INEN &= ~(0x01 << n); + PORT->PORTP_INEN |= (digit_in_en << n); + break; + } +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_port.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_port.h new file mode 100644 index 0000000000000000000000000000000000000000..1e2f4f2244f02c49e4f3d9806f7d5297a599caeb --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_port.h @@ -0,0 +1,482 @@ +#ifndef __SWM320_PORT_H__ +#define __SWM320_PORT_H__ + +void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //˿Źѡȡֵ£ + +#define PORTA 0 +#define PORTB 1 +#define PORTC 2 +#define PORTM 3 +#define PORTN 4 +#define PORTP 5 + +#define PORTA_PIN0_GPIO 0 +#define PORTA_PIN0_FUNMUX 1 +#define PORTA_PIN0_SWCLK 2 + +#define PORTA_PIN1_GPIO 0 +#define PORTA_PIN1_FUNMUX 1 +#define PORTA_PIN1_SWDIO 2 + +#define PORTA_PIN2_GPIO 0 +#define PORTA_PIN2_FUNMUX 1 + +#define PORTA_PIN3_GPIO 0 +#define PORTA_PIN3_FUNMUX 1 + +#define PORTA_PIN4_GPIO 0 +#define PORTA_PIN4_FUNMUX 1 + +#define PORTA_PIN5_GPIO 0 +#define PORTA_PIN5_FUNMUX 1 + +#define PORTA_PIN6_GPIO 0 +#define PORTA_PIN6_FUNMUX 1 + +#define PORTA_PIN7_GPIO 0 +#define PORTA_PIN7_FUNMUX 1 + +#define PORTA_PIN8_GPIO 0 +#define PORTA_PIN8_FUNMUX 1 + +#define PORTA_PIN9_GPIO 0 +#define PORTA_PIN9_FUNMUX 1 +#define PORTA_PIN9_ADC0_IN7 3 + +#define PORTA_PIN10_GPIO 0 +#define PORTA_PIN10_FUNMUX 1 +#define PORTA_PIN10_ADC0_IN6 3 + +#define PORTA_PIN11_GPIO 0 +#define PORTA_PIN11_FUNMUX 1 +#define PORTA_PIN11_ADC0_IN5 3 + +#define PORTA_PIN12_GPIO 0 +#define PORTA_PIN12_ADC0_IN4 3 + + +#define PORTB_PIN0_GPIO 0 +#define PORTB_PIN0_FUNMUX 1 +#define PORTB_PIN0_SD_DETECT 2 + +#define PORTB_PIN1_GPIO 0 +#define PORTB_PIN1_FUNMUX 1 +#define PORTB_PIN1_SD_CLK 2 + +#define PORTB_PIN2_GPIO 0 +#define PORTB_PIN2_FUNMUX 1 +#define PORTB_PIN2_SD_CMD 2 + +#define PORTB_PIN3_GPIO 0 +#define PORTB_PIN3_FUNMUX 1 +#define PORTB_PIN3_SD_D0 2 + +#define PORTB_PIN4_GPIO 0 +#define PORTB_PIN4_FUNMUX 1 +#define PORTB_PIN4_SD_D1 2 + +#define PORTB_PIN5_GPIO 0 +#define PORTB_PIN5_FUNMUX 1 +#define PORTB_PIN5_SD_D2 2 + +#define PORTB_PIN6_GPIO 0 +#define PORTB_PIN6_FUNMUX 1 +#define PORTB_PIN6_SD_D3 2 + +#define PORTB_PIN7_GPIO 0 +#define PORTB_PIN7_FUNMUX 1 +#define PORTB_PIN7_SD_D4 2 + +#define PORTB_PIN8_GPIO 0 +#define PORTB_PIN8_FUNMUX 1 +#define PORTB_PIN8_SD_D5 2 + +#define PORTB_PIN9_GPIO 0 +#define PORTB_PIN9_FUNMUX 1 +#define PORTB_PIN9_SD_D6 2 + +#define PORTB_PIN10_GPIO 0 +#define PORTB_PIN10_FUNMUX 1 +#define PORTB_PIN10_SD_D7 2 + +#define PORTB_PIN11_GPIO 0 +#define PORTB_PIN11_FUNMUX 1 + +#define PORTB_PIN12_GPIO 0 + + +#define PORTC_PIN0_GPIO 0 +#define PORTC_PIN0_FUNMUX 1 + +#define PORTC_PIN1_GPIO 0 +#define PORTC_PIN1_FUNMUX 1 + +#define PORTC_PIN2_GPIO 0 +#define PORTC_PIN2_FUNMUX 1 + +#define PORTC_PIN3_GPIO 0 +#define PORTC_PIN3_FUNMUX 1 + +#define PORTC_PIN4_GPIO 0 +#define PORTC_PIN4_FUNMUX 1 +#define PORTC_PIN4_ADC1_IN3 3 + +#define PORTC_PIN5_GPIO 0 +#define PORTC_PIN5_FUNMUX 1 +#define PORTC_PIN5_ADC1_IN2 3 + +#define PORTC_PIN6_GPIO 0 +#define PORTC_PIN6_FUNMUX 1 +#define PORTC_PIN6_ADC1_IN1 3 + +#define PORTC_PIN7_GPIO 0 +#define PORTC_PIN7_FUNMUX 1 +#define PORTC_PIN7_ADC1_IN0 3 + + +#define PORTM_PIN0_GPIO 0 +#define PORTM_PIN0_FUNMUX 1 +#define PORTM_PIN0_NORFL_D15 2 + +#define PORTM_PIN1_GPIO 0 +#define PORTM_PIN1_FUNMUX 1 +#define PORTM_PIN1_NORFL_D14 2 + +#define PORTM_PIN2_GPIO 0 +#define PORTM_PIN2_FUNMUX 1 +#define PORTM_PIN2_NORFL_D13 2 + +#define PORTM_PIN3_GPIO 0 +#define PORTM_PIN3_FUNMUX 1 +#define PORTM_PIN3_NORFL_D12 2 + +#define PORTM_PIN4_GPIO 0 +#define PORTM_PIN4_FUNMUX 1 +#define PORTM_PIN4_NORFL_D11 2 + +#define PORTM_PIN5_GPIO 0 +#define PORTM_PIN5_FUNMUX 1 +#define PORTM_PIN5_NORFL_D10 2 + +#define PORTM_PIN6_GPIO 0 +#define PORTM_PIN6_FUNMUX 1 +#define PORTM_PIN6_NORFL_D9 2 + +#define PORTM_PIN7_GPIO 0 +#define PORTM_PIN7_FUNMUX 1 +#define PORTM_PIN7_NORFL_D8 2 + +#define PORTM_PIN8_GPIO 0 +#define PORTM_PIN8_FUNMUX 1 +#define PORTM_PIN8_NORFL_D7 2 + +#define PORTM_PIN9_GPIO 0 +#define PORTM_PIN9_FUNMUX 1 +#define PORTM_PIN9_NORFL_D6 2 + +#define PORTM_PIN10_GPIO 0 +#define PORTM_PIN10_FUNMUX 1 +#define PORTM_PIN10_NORFL_D5 2 + +#define PORTM_PIN11_GPIO 0 +#define PORTM_PIN11_FUNMUX 1 +#define PORTM_PIN11_NORFL_D4 2 + +#define PORTM_PIN12_GPIO 0 +#define PORTM_PIN12_FUNMUX 1 +#define PORTM_PIN12_NORFL_D3 2 + +#define PORTM_PIN13_GPIO 0 +#define PORTM_PIN13_FUNMUX 1 +#define PORTM_PIN13_NORFL_D2 2 + +#define PORTM_PIN14_GPIO 0 +#define PORTM_PIN14_FUNMUX 1 +#define PORTM_PIN14_NORFL_D1 2 + +#define PORTM_PIN15_GPIO 0 +#define PORTM_PIN15_FUNMUX 1 +#define PORTM_PIN15_NORFL_D0 2 + +#define PORTM_PIN16_GPIO 0 +#define PORTM_PIN16_FUNMUX 1 +#define PORTM_PIN16_NORFL_OEN 2 + +#define PORTM_PIN17_GPIO 0 +#define PORTM_PIN17_FUNMUX 1 +#define PORTM_PIN17_NORFL_WEN 2 + +#define PORTM_PIN18_GPIO 0 +#define PORTM_PIN18_FUNMUX 1 +#define PORTM_PIN18_NORFL_CSN 2 + +#define PORTM_PIN19_GPIO 0 +#define PORTM_PIN19_FUNMUX 1 +#define PORTM_PIN19_SDRAM_CSN 2 + +#define PORTM_PIN20_GPIO 0 +#define PORTM_PIN20_FUNMUX 1 +#define PORTM_PIN20_SRAM_CSN 2 + +#define PORTM_PIN21_GPIO 0 +#define PORTM_PIN21_FUNMUX 1 +#define PORTM_PIN21_SDRAM_CKE 2 + + +#define PORTN_PIN0_GPIO 0 +#define PORTN_PIN0_FUNMUX 1 +#define PORTN_PIN0_LCD_D0 2 +#define PORTN_PIN0_ADC1_IN4 3 + +#define PORTN_PIN1_GPIO 0 +#define PORTN_PIN1_FUNMUX 1 +#define PORTN_PIN1_LCD_D1 2 +#define PORTN_PIN1_ADC1_IN5 3 + +#define PORTN_PIN2_GPIO 0 +#define PORTN_PIN2_FUNMUX 1 +#define PORTN_PIN2_LCD_D2 2 +#define PORTN_PIN2_ADC1_IN6 3 + +#define PORTN_PIN3_GPIO 0 +#define PORTN_PIN3_FUNMUX 1 +#define PORTN_PIN3_LCD_D3 2 + +#define PORTN_PIN4_GPIO 0 +#define PORTN_PIN4_FUNMUX 1 +#define PORTN_PIN4_LCD_D4 2 + +#define PORTN_PIN5_GPIO 0 +#define PORTN_PIN5_FUNMUX 1 +#define PORTN_PIN5_LCD_D5 2 + +#define PORTN_PIN6_GPIO 0 +#define PORTN_PIN6_FUNMUX 1 +#define PORTN_PIN6_LCD_D6 2 + +#define PORTN_PIN7_GPIO 0 +#define PORTN_PIN7_FUNMUX 1 +#define PORTN_PIN7_LCD_D7 2 + +#define PORTN_PIN8_GPIO 0 +#define PORTN_PIN8_FUNMUX 1 +#define PORTN_PIN8_LCD_D8 2 + +#define PORTN_PIN9_GPIO 0 +#define PORTN_PIN9_FUNMUX 1 +#define PORTN_PIN9_LCD_D9 2 + +#define PORTN_PIN10_GPIO 0 +#define PORTN_PIN10_FUNMUX 1 +#define PORTN_PIN10_LCD_D10 2 + +#define PORTN_PIN11_GPIO 0 +#define PORTN_PIN11_FUNMUX 1 +#define PORTN_PIN11_LCD_D11 2 + +#define PORTN_PIN12_GPIO 0 +#define PORTN_PIN12_FUNMUX 1 +#define PORTN_PIN12_LCD_D12 2 + +#define PORTN_PIN13_GPIO 0 +#define PORTN_PIN13_FUNMUX 1 +#define PORTN_PIN13_LCD_D13 2 + +#define PORTN_PIN14_GPIO 0 +#define PORTN_PIN14_FUNMUX 1 +#define PORTN_PIN14_LCD_D14 2 + +#define PORTN_PIN15_GPIO 0 +#define PORTN_PIN15_FUNMUX 1 +#define PORTN_PIN15_LCD_D15 2 + +#define PORTN_PIN16_GPIO 0 +#define PORTN_PIN16_FUNMUX 1 +#define PORTN_PIN16_LCD_RD 2 +#define PORTN_PIN16_LCD_DOTCK 2 + +#define PORTN_PIN17_GPIO 0 +#define PORTN_PIN17_FUNMUX 1 +#define PORTN_PIN17_LCD_CS 2 +#define PORTN_PIN17_LCD_VSYNC 2 + +#define PORTN_PIN18_GPIO 0 +#define PORTN_PIN18_LCD_RS 2 +#define PORTN_PIN18_LCD_DATEN 2 //Data Enable + +#define PORTN_PIN19_GPIO 0 +#define PORTN_PIN19_LCD_WR 2 +#define PORTN_PIN19_LCD_HSYNC 2 + + +#define PORTP_PIN0_GPIO 0 +#define PORTP_PIN0_FUNMUX 1 +#define PORTP_PIN0_NORFL_A0 2 + +#define PORTP_PIN1_GPIO 0 +#define PORTP_PIN1_FUNMUX 1 +#define PORTP_PIN1_NORFL_A1 2 + +#define PORTP_PIN2_GPIO 0 +#define PORTP_PIN2_FUNMUX 1 +#define PORTP_PIN2_NORFL_A2 2 +#define PORTP_PIN2_SD_D7 3 + +#define PORTP_PIN3_GPIO 0 +#define PORTP_PIN3_FUNMUX 1 +#define PORTP_PIN3_NORFL_A3 2 +#define PORTP_PIN3_SD_D6 3 + +#define PORTP_PIN4_GPIO 0 +#define PORTP_PIN4_FUNMUX 1 +#define PORTP_PIN4_NORFL_A4 2 +#define PORTP_PIN4_SD_D5 3 + +#define PORTP_PIN5_GPIO 0 +#define PORTP_PIN5_FUNMUX 1 +#define PORTP_PIN5_NORFL_A5 2 +#define PORTP_PIN5_SD_D4 3 + +#define PORTP_PIN6_GPIO 0 +#define PORTP_PIN6_FUNMUX 1 +#define PORTP_PIN6_NORFL_A6 2 +#define PORTP_PIN6_SD_D3 3 + +#define PORTP_PIN7_GPIO 0 +#define PORTP_PIN7_FUNMUX 1 +#define PORTP_PIN7_NORFL_A7 2 +#define PORTP_PIN7_SD_D2 3 + +#define PORTP_PIN8_GPIO 0 +#define PORTP_PIN8_FUNMUX 1 +#define PORTP_PIN8_NORFL_A8 2 +#define PORTP_PIN8_SD_D1 3 + +#define PORTP_PIN9_GPIO 0 +#define PORTP_PIN9_FUNMUX 1 +#define PORTP_PIN9_NORFL_A9 2 +#define PORTP_PIN9_SD_D0 3 + +#define PORTP_PIN10_GPIO 0 +#define PORTP_PIN10_FUNMUX 1 +#define PORTP_PIN10_NORFL_A10 2 +#define PORTP_PIN10_SD_CMD 3 + +#define PORTP_PIN11_GPIO 0 +#define PORTP_PIN11_FUNMUX 1 +#define PORTP_PIN11_NORFL_A11 2 +#define PORTP_PIN11_SD_CLK 3 + +#define PORTP_PIN12_GPIO 0 +#define PORTP_PIN12_FUNMUX 1 +#define PORTP_PIN12_NORFL_A12 2 +#define PORTP_PIN12_SD_DETECT 3 + +#define PORTP_PIN13_GPIO 0 +#define PORTP_PIN13_FUNMUX 1 +#define PORTP_PIN13_NORFL_A13 2 +#define PORTP_PIN13_SDRAM_CLK 2 + +#define PORTP_PIN14_GPIO 0 +#define PORTP_PIN14_FUNMUX 1 +#define PORTP_PIN14_NORFL_A14 2 +#define PORTP_PIN14_SDRAM_CAS 2 + +#define PORTP_PIN15_GPIO 0 +#define PORTP_PIN15_FUNMUX 1 +#define PORTP_PIN15_NORFL_A15 2 +#define PORTP_PIN15_SDRAM_RAS 2 + +#define PORTP_PIN16_GPIO 0 +#define PORTP_PIN16_FUNMUX 1 +#define PORTP_PIN16_NORFL_A16 2 +#define PORTP_PIN16_SDRAM_LDQ 2 + +#define PORTP_PIN17_GPIO 0 +#define PORTP_PIN17_FUNMUX 1 +#define PORTP_PIN17_NORFL_A17 2 +#define PORTP_PIN17_SDRAM_UDQ 2 + +#define PORTP_PIN18_GPIO 0 +#define PORTP_PIN18_FUNMUX 1 +#define PORTP_PIN18_NORFL_A18 2 + +#define PORTP_PIN19_GPIO 0 +#define PORTP_PIN19_FUNMUX 1 +#define PORTP_PIN19_NORFL_A19 2 + +#define PORTP_PIN20_GPIO 0 +#define PORTP_PIN20_FUNMUX 1 +#define PORTP_PIN20_NORFL_A20 2 +#define PORTP_PIN20_SDRAM_BA0 2 + +#define PORTP_PIN21_GPIO 0 +#define PORTP_PIN21_FUNMUX 1 +#define PORTP_PIN21_NORFL_A21 2 +#define PORTP_PIN21_SDRAM_BA1 2 + +#define PORTP_PIN22_GPIO 0 +#define PORTP_PIN22_FUNMUX 1 +#define PORTP_PIN22_NORFL_A22 2 + +#define PORTP_PIN23_GPIO 0 +#define PORTP_PIN23_FUNMUX 1 +#define PORTP_PIN23_NORFL_A23 2 + + + +/* 궨ȡֵȫȷֵĻϡ100궨ֵӶ⺯ıд*/ +/* ЩֵżŵĹȡֵPIN0PIN2... */ +#define FUNMUX0_UART0_RXD 100 +#define FUNMUX0_UART1_RXD 101 +#define FUNMUX0_UART2_RXD 102 +#define FUNMUX0_UART3_RXD 103 +#define FUNMUX0_I2C0_SCL 105 +#define FUNMUX0_I2C1_SCL 106 +#define FUNMUX0_PWM0A_OUT 107 +#define FUNMUX0_PWM2A_OUT 108 +#define FUNMUX0_PWM4A_OUT 109 +#define FUNMUX0_PWM0B_OUT 110 +#define FUNMUX0_PWM2B_OUT 111 +#define FUNMUX0_PWM4B_OUT 112 +#define FUNMUX0_PWM_BREAK 113 +#define FUNMUX0_TIMR0_IN 114 +#define FUNMUX0_TIMR2_IN 115 +#define FUNMUX0_CAN_RX 116 +#define FUNMUX0_SPI0_SSEL 117 +#define FUNMUX0_SPI0_MOSI 118 +#define FUNMUX0_SPI1_SSEL 119 +#define FUNMUX0_SPI1_MOSI 120 +#define FUNMUX0_UART0_CTS 121 +#define FUNMUX0_UART1_CTS 122 +#define FUNMUX0_UART2_CTS 123 +#define FUNMUX0_UART3_CTS 124 + +/* ЩֵŵĹȡֵPIN1PIN3... */ +#define FUNMUX1_UART0_TXD 100 +#define FUNMUX1_UART1_TXD 101 +#define FUNMUX1_UART2_TXD 102 +#define FUNMUX1_UART3_TXD 103 +#define FUNMUX1_I2C0_SDA 105 +#define FUNMUX1_I2C1_SDA 106 +#define FUNMUX1_PWM1A_OUT 107 +#define FUNMUX1_PWM3A_OUT 108 +#define FUNMUX1_PWM5A_OUT 109 +#define FUNMUX1_PWM1B_OUT 110 +#define FUNMUX1_PWM3B_OUT 111 +#define FUNMUX1_PWM5B_OUT 112 +#define FUNMUX1_PULSE_IN 113 +#define FUNMUX1_TIMR1_IN 114 +#define FUNMUX1_TIMR3_IN 115 +#define FUNMUX1_CAN_TX 116 +#define FUNMUX1_SPI0_SCLK 117 +#define FUNMUX1_SPI0_MISO 118 +#define FUNMUX1_SPI1_SCLK 119 +#define FUNMUX1_SPI1_MISO 120 +#define FUNMUX1_UART0_RTS 121 +#define FUNMUX1_UART1_RTS 122 +#define FUNMUX1_UART2_RTS 123 +#define FUNMUX1_UART3_RTS 124 + + +#endif //__SWM320_PORT_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..e74334fc93a4e7dc879d2c6ce5cdca70f48bc088 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c @@ -0,0 +1,651 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_pwm.c +* ˵: SWM320ƬPWM +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_pwm.h" + + +/****************************************************************************************************************************************** +* : PWM_Init() +* ˵: PWMʼ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* PWM_InitStructure * initStruct PWM趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_Init(PWM_TypeDef * PWMx, PWM_InitStructure * initStruct) +{ + uint32_t bit_offset = 0; + + SYS->CLKEN |= (0x01 << SYS_CLKEN_PWM_Pos); + + SYS->CLKDIV &= ~SYS_CLKDIV_PWM_Msk; + SYS->CLKDIV |= (initStruct->clk_div << SYS_CLKDIV_PWM_Pos); + + PWM_Stop(PWMx, 1, 1); //һЩؼĴֻPWMֹͣʱ + + PWMx->MODE = initStruct->mode; + + PWMx->PERA = initStruct->cycleA; + PWMx->HIGHA = initStruct->hdutyA; + PWMx->DZA = initStruct->deadzoneA; + + PWMx->PERB = initStruct->cycleB; + PWMx->HIGHB = initStruct->hdutyB; + PWMx->DZB = initStruct->deadzoneB; + + PWMx->INIOUT &= ~(PWM_INIOUT_PWMA_Msk | PWM_INIOUT_PWMB_Msk); + PWMx->INIOUT |= (initStruct->initLevelA << PWM_INIOUT_PWMA_Pos) | + (initStruct->initLevelB << PWM_INIOUT_PWMB_Pos); + + PWMG->IM = 0x00000000; + + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + bit_offset = 0; + break; + + case((uint32_t)PWM1): + bit_offset = 2; + break; + + case((uint32_t)PWM2): + bit_offset = 4; + break; + + case((uint32_t)PWM3): + bit_offset = 6; + break; + + case((uint32_t)PWM4): + bit_offset = 8; + break; + + case((uint32_t)PWM5): + bit_offset = 10; + break; + } + + PWMG->IRS = ((0x01 << bit_offset) | (0x01 << (bit_offset+1)) | (0x01 << (bit_offset+12)) | (0x01 << (bit_offset+13))); //жϱ־ + PWMG->IE &= ~((0x01 << bit_offset) | (0x01 << (bit_offset+1)) | (0x01 << (bit_offset+12)) | (0x01 << (bit_offset+13))); + PWMG->IE |= (initStruct->NCycleAIEn << bit_offset) | (initStruct->NCycleBIEn << (bit_offset+1)) | + (initStruct->HEndAIEn << (bit_offset+12)) | (initStruct->HEndBIEn << (bit_offset+13)); + + if(initStruct->NCycleAIEn | initStruct->NCycleBIEn | initStruct->HEndAIEn | initStruct->HEndBIEn) + { + NVIC_EnableIRQ(PWM_IRQn); + } + else if((PWMG->IE & (~((0x01 << bit_offset) | (0x01 << (bit_offset+1)) | (0x01 << (bit_offset+12)) | (0x01 << (bit_offset+13))))) == 0) + { + NVIC_DisableIRQ(PWM_IRQn); + } +} + +/****************************************************************************************************************************************** +* : PWM_Start() +* ˵: PWMʼPWM +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chA 0 ͨA 1 ͨA +* uint32_t chB 0 ͨB 1 ͨB +* : +* ע: +******************************************************************************************************************************************/ +void PWM_Start(PWM_TypeDef * PWMx, uint32_t chA, uint32_t chB) +{ + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM0A_Pos) | (chB << PWMG_CHEN_PWM0B_Pos); + break; + + case((uint32_t)PWM1): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM1A_Pos) | (chB << PWMG_CHEN_PWM1B_Pos); + break; + + case((uint32_t)PWM2): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM2A_Pos) | (chB << PWMG_CHEN_PWM2B_Pos); + break; + + case((uint32_t)PWM3): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM3A_Pos) | (chB << PWMG_CHEN_PWM3B_Pos); + break; + + case((uint32_t)PWM4): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM4A_Pos) | (chB << PWMG_CHEN_PWM4B_Pos); + break; + + case((uint32_t)PWM5): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM5A_Pos) | (chB << PWMG_CHEN_PWM5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : PWM_Stop() +* ˵: رPWMֹͣPWM +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chA 0 ͨAر 1 ͨAر +* uint32_t chB 0 ͨBر 1 ͨBر +* : +* ע: +******************************************************************************************************************************************/ +void PWM_Stop(PWM_TypeDef * PWMx, uint32_t chA, uint32_t chB) +{ + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM0A_Pos) | (chB << PWMG_CHEN_PWM0B_Pos)); + break; + + case((uint32_t)PWM1): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM1A_Pos) | (chB << PWMG_CHEN_PWM1B_Pos)); + break; + + case((uint32_t)PWM2): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM2A_Pos) | (chB << PWMG_CHEN_PWM2B_Pos)); + break; + + case((uint32_t)PWM3): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM3A_Pos) | (chB << PWMG_CHEN_PWM3B_Pos)); + break; + + case((uint32_t)PWM4): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM4A_Pos) | (chB << PWMG_CHEN_PWM4B_Pos)); + break; + + case((uint32_t)PWM5): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM5A_Pos) | (chB << PWMG_CHEN_PWM5B_Pos)); + break; + } +} + +/****************************************************************************************************************************************** +* : PWM_SetCycle() +* ˵: +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* uint16_t cycle Ҫ趨ֵ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_SetCycle(PWM_TypeDef * PWMx, uint32_t chn, uint16_t cycle) +{ + if(chn == PWM_CH_A) + PWMx->PERA = cycle; + else if(chn == PWM_CH_B) + PWMx->PERB = cycle; +} + +/****************************************************************************************************************************************** +* : PWM_GetCycle() +* ˵: ȡ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪѯĸͨЧֵPWM_CH_APWM_CH_B +* : uint16_t ȡֵ +* ע: +******************************************************************************************************************************************/ +uint16_t PWM_GetCycle(PWM_TypeDef * PWMx, uint32_t chn) +{ + uint16_t cycle = 0; + + if(chn == PWM_CH_A) + cycle = PWMx->PERA; + else if(chn == PWM_CH_B) + cycle = PWMx->PERB; + + return cycle; +} + +/****************************************************************************************************************************************** +* : PWM_SetHDuty() +* ˵: øߵƽʱ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* uint16_t hduty Ҫ趨ĸߵƽʱ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_SetHDuty(PWM_TypeDef * PWMx, uint32_t chn, uint16_t hduty) +{ + if(chn == PWM_CH_A) + PWMx->HIGHA = hduty; + else if(chn == PWM_CH_B) + PWMx->HIGHB = hduty; +} + +/****************************************************************************************************************************************** +* : PWM_GetHDuty() +* ˵: ȡߵƽʱ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪѯĸͨЧֵPWM_CH_APWM_CH_B +* : uint16_t ȡĸߵƽʱ +* ע: +******************************************************************************************************************************************/ +uint16_t PWM_GetHDuty(PWM_TypeDef * PWMx, uint32_t chn) +{ + uint16_t hduty = 0; + + if(chn == PWM_CH_A) + hduty = PWMx->HIGHA; + else if(chn == PWM_CH_B) + hduty = PWMx->HIGHB; + + return hduty; +} + +/****************************************************************************************************************************************** +* : PWM_SetDeadzone() +* ˵: ʱ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* uint8_t deadzone Ҫ趨ʱ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_SetDeadzone(PWM_TypeDef * PWMx, uint32_t chn, uint8_t deadzone) +{ + if(chn == PWM_CH_A) + PWMx->DZA = deadzone; + else if(chn == PWM_CH_B) + PWMx->DZB = deadzone; +} + +/****************************************************************************************************************************************** +* : PWM_GetDeadzone() +* ˵: ȡʱ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪѯĸͨЧֵPWM_CH_APWM_CH_B +* : uint8_t ȡʱ +* ע: +******************************************************************************************************************************************/ +uint8_t PWM_GetDeadzone(PWM_TypeDef * PWMx, uint32_t chn) +{ + uint8_t deadzone = 0; + + if(chn == PWM_CH_A) + deadzone = PWMx->DZA; + else if(chn == PWM_CH_B) + deadzone = PWMx->DZB; + + return deadzone; +} + + +/****************************************************************************************************************************************** +* : PWM_IntNCycleEn() +* ˵: ڿʼжʹ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* : +* ע: +******************************************************************************************************************************************/ +void PWM_IntNCycleEn(PWM_TypeDef * PWMx, uint32_t chn) +{ + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_NEWP0A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_NEWP0B_Pos); + break; + + case((uint32_t)PWM1): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_NEWP1A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_NEWP1B_Pos); + break; + + case((uint32_t)PWM2): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_NEWP2A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_NEWP2B_Pos); + break; + + case((uint32_t)PWM3): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_NEWP3A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_NEWP3B_Pos); + break; + + case((uint32_t)PWM4): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_NEWP4A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_NEWP4B_Pos); + break; + + case((uint32_t)PWM5): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_NEWP5A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_NEWP5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : PWM_IntNCycleDis() +* ˵: ڿʼжϽ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* : +* ע: +******************************************************************************************************************************************/ +void PWM_IntNCycleDis(PWM_TypeDef * PWMx, uint32_t chn) +{ + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_NEWP0A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_NEWP0B_Pos); + break; + + case((uint32_t)PWM1): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_NEWP1A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_NEWP1B_Pos); + break; + + case((uint32_t)PWM2): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_NEWP2A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_NEWP2B_Pos); + break; + + case((uint32_t)PWM3): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_NEWP3A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_NEWP3B_Pos); + break; + + case((uint32_t)PWM4): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_NEWP4A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_NEWP4B_Pos); + break; + + case((uint32_t)PWM5): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_NEWP5A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_NEWP5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : PWM_IntNCycleClr() +* ˵: ڿʼжϱ־ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* : +* ע: +******************************************************************************************************************************************/ +void PWM_IntNCycleClr(PWM_TypeDef * PWMx, uint32_t chn) +{ + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_NEWP0A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_NEWP0B_Pos); + break; + + case((uint32_t)PWM1): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_NEWP1A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_NEWP1B_Pos); + break; + + case((uint32_t)PWM2): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_NEWP2A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_NEWP2B_Pos); + break; + + case((uint32_t)PWM3): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_NEWP3A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_NEWP3B_Pos); + break; + + case((uint32_t)PWM4): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_NEWP4A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_NEWP4B_Pos); + break; + + case((uint32_t)PWM5): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_NEWP5A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_NEWP5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : PWM_IntNCycleStat() +* ˵: ڿʼжǷ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* : uint32_t 1 ڿʼжѷ 0 ڿʼжδ +* ע: +******************************************************************************************************************************************/ +uint32_t PWM_IntNCycleStat(PWM_TypeDef * PWMx, uint32_t chn) +{ + uint32_t int_stat = 0; + + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_NEWP0A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_NEWP0B_Msk); + break; + + case((uint32_t)PWM1): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_NEWP1A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_NEWP1B_Msk); + break; + + case((uint32_t)PWM2): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_NEWP2A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_NEWP2B_Msk); + break; + + case((uint32_t)PWM3): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_NEWP3A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_NEWP3B_Msk); + break; + + case((uint32_t)PWM4): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_NEWP4A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_NEWP4B_Msk); + break; + + case((uint32_t)PWM5): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_NEWP5A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_NEWP5B_Msk); + break; + } + + return int_stat; +} + + +/****************************************************************************************************************************************** +* : PWM_IntHEndEn() +* ˵: ߵƽжʹ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* : +* ע: +******************************************************************************************************************************************/ +void PWM_IntHEndEn(PWM_TypeDef * PWMx, uint32_t chn) +{ + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_HEND0A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_HEND0B_Pos); + break; + + case((uint32_t)PWM1): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_HEND1A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_HEND1B_Pos); + break; + + case((uint32_t)PWM2): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_HEND2A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_HEND2B_Pos); + break; + + case((uint32_t)PWM3): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_HEND3A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_HEND3B_Pos); + break; + + case((uint32_t)PWM4): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_HEND4A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_HEND4B_Pos); + break; + + case((uint32_t)PWM5): + if(chn == PWM_CH_A) PWMG->IE |= (0x01 << PWMG_IE_HEND5A_Pos); + else PWMG->IE |= (0x01 << PWMG_IE_HEND5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : PWM_IntHEndDis() +* ˵: ߵƽжϽ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* : +* ע: +******************************************************************************************************************************************/ +void PWM_IntHEndDis(PWM_TypeDef * PWMx, uint32_t chn) +{ + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_HEND0A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_HEND0B_Pos); + break; + + case((uint32_t)PWM1): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_HEND1A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_HEND1B_Pos); + break; + + case((uint32_t)PWM2): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_HEND2A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_HEND2B_Pos); + break; + + case((uint32_t)PWM3): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_HEND3A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_HEND3B_Pos); + break; + + case((uint32_t)PWM4): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_HEND4A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_HEND4B_Pos); + break; + + case((uint32_t)PWM5): + if(chn == PWM_CH_A) PWMG->IE &= ~(0x01 << PWMG_IE_HEND5A_Pos); + else PWMG->IE &= ~(0x01 << PWMG_IE_HEND5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : PWM_IntHEndClr() +* ˵: ߵƽжϱ־ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* : +* ע: +******************************************************************************************************************************************/ +void PWM_IntHEndClr(PWM_TypeDef * PWMx, uint32_t chn) +{ + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_HEND0A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_HEND0B_Pos); + break; + + case((uint32_t)PWM1): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_HEND1A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_HEND1B_Pos); + break; + + case((uint32_t)PWM2): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_HEND2A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_HEND2B_Pos); + break; + + case((uint32_t)PWM3): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_HEND3A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_HEND3B_Pos); + break; + + case((uint32_t)PWM4): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_HEND4A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_HEND4B_Pos); + break; + + case((uint32_t)PWM5): + if(chn == PWM_CH_A) PWMG->IRS = (0x01 << PWMG_IRS_HEND5A_Pos); + else PWMG->IRS = (0x01 << PWMG_IRS_HEND5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : PWM_IntHEndStat() +* ˵: ߵƽжǷ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1PWM2PWM3PWM4PWM5 +* uint32_t chn ѡҪĸͨЧֵPWM_CH_APWM_CH_B +* : uint32_t 1 ߵƽжѷ 0 ߵƽжδ +* ע: +******************************************************************************************************************************************/ +uint32_t PWM_IntHEndStat(PWM_TypeDef * PWMx, uint32_t chn) +{ + uint32_t int_stat = 0; + + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_HEND0A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_HEND0B_Msk); + break; + + case((uint32_t)PWM1): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_HEND1A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_HEND1B_Msk); + break; + + case((uint32_t)PWM2): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_HEND2A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_HEND2B_Msk); + break; + + case((uint32_t)PWM3): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_HEND3A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_HEND3B_Msk); + break; + + case((uint32_t)PWM4): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_HEND4A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_HEND4B_Msk); + break; + + case((uint32_t)PWM5): + if(chn == PWM_CH_A) int_stat = (PWMG->IF & PWMG_IF_HEND5A_Msk); + else int_stat = (PWMG->IF & PWMG_IF_HEND5B_Msk); + break; + } + + return int_stat; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..4565a05a94e26f4fe77628c8eeba9bec6581e935 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h @@ -0,0 +1,58 @@ +#ifndef __SWM320_PWM_H__ +#define __SWM320_PWM_H__ + +typedef struct { + uint8_t clk_div; //PWM_CLKDIV_1PWM_CLKDIV_8 + + uint8_t mode; //PWM_MODE_INDEPPWM_MODE_COMPLPWM_MODE_INDEP_CALIGNPWM_MODE_COMPL_CALIGN + + uint16_t cycleA; //A· + uint16_t hdutyA; //A·ռձ + uint16_t deadzoneA; //A·ʱȡֵ0--1023 + uint8_t initLevelA; //A·ʼƽ0 ͵ƽ 1 ߵƽ + + uint16_t cycleB; //B· + uint16_t hdutyB; //B·ռձ + uint16_t deadzoneB; //B·ʱȡֵ0--1023 + uint8_t initLevelB; //B·ʼƽ0 ͵ƽ 1 ߵƽ + + uint8_t HEndAIEn; //A·ߵƽжʹ + uint8_t NCycleAIEn; //A·ڿʼжʹ + uint8_t HEndBIEn; //B·ߵƽжʹ + uint8_t NCycleBIEn; //B·ڿʼжʹ +} PWM_InitStructure; + +#define PWM_CLKDIV_1 0 +#define PWM_CLKDIV_8 1 + +#define PWM_MODE_INDEP 0 //A·B·Ϊ· +#define PWM_MODE_COMPL 1 //A·B·Ϊһ· +#define PWM_MODE_INDEP_CALIGN 3 //A·B·Ϊ·Ķ +#define PWM_MODE_COMPL_CALIGN 4 //A·B·Ϊһ·Ķ + +#define PWM_CH_A 0 +#define PWM_CH_B 1 + + +void PWM_Init(PWM_TypeDef * PWMx, PWM_InitStructure * initStruct); //PWMʼ +void PWM_Start(PWM_TypeDef * PWMx, uint32_t chA, uint32_t chB); //PWMʼPWM +void PWM_Stop(PWM_TypeDef * PWMx, uint32_t chA, uint32_t chB); //رPWMֹͣPWM + +void PWM_SetCycle(PWM_TypeDef * PWMx, uint32_t chn, uint16_t cycle); // +uint16_t PWM_GetCycle(PWM_TypeDef * PWMx, uint32_t chn); //ȡ +void PWM_SetHDuty(PWM_TypeDef * PWMx, uint32_t chn, uint16_t hduty); //øߵƽʱ +uint16_t PWM_GetHDuty(PWM_TypeDef * PWMx, uint32_t chn); //ȡߵƽʱ +void PWM_SetDeadzone(PWM_TypeDef * PWMx, uint32_t chn, uint8_t deadzone); //ʱ +uint8_t PWM_GetDeadzone(PWM_TypeDef * PWMx, uint32_t chn); //ȡʱ + +void PWM_IntNCycleEn(PWM_TypeDef * PWMx, uint32_t chn); //ڿʼжʹ +void PWM_IntNCycleDis(PWM_TypeDef * PWMx, uint32_t chn); //ڿʼжϽ +void PWM_IntNCycleClr(PWM_TypeDef * PWMx, uint32_t chn); //ڿʼжϱ־ +uint32_t PWM_IntNCycleStat(PWM_TypeDef * PWMx, uint32_t chn); //ڿʼжǷ +void PWM_IntHEndEn(PWM_TypeDef * PWMx, uint32_t chn); //ߵƽжʹ +void PWM_IntHEndDis(PWM_TypeDef * PWMx, uint32_t chn); //ߵƽжϽ +void PWM_IntHEndClr(PWM_TypeDef * PWMx, uint32_t chn); //ߵƽжϱ־ +uint32_t PWM_IntHEndStat(PWM_TypeDef * PWMx, uint32_t chn); //ߵƽжǷ + + +#endif //__SWM320_PWM_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..2ce0f390b735fc714765d3b73f5a79d7f531b906 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c @@ -0,0 +1,413 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_rtc.c +* ˵: SWM320ƬRTC +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_rtc.h" + + +static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date); +/****************************************************************************************************************************************** +* : RTC_Init() +* ˵: RTCʼ +* : RTC_TypeDef * RTCx ָҪõRTCЧֵRTC +* RTC_InitStructure * initStruct RTC趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void RTC_Init(RTC_TypeDef * RTCx, RTC_InitStructure * initStruct) +{ + SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); + + SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); //RTCʹ32KHz RCʱ + + SYS->CLKEN |= (1 << SYS_CLKEN_RTC_Pos) | + ((uint32_t)1 << SYS_CLKEN_ALIVE_Pos); + + RTC_Stop(RTCx); + + while(RTCx->CFGABLE == 0); + + RTCx->MINSEC = (initStruct->Second << RTC_MINSEC_SEC_Pos) | + (initStruct->Minute << RTC_MINSEC_MIN_Pos); + + RTCx->DATHUR = (initStruct->Hour << RTC_DATHUR_HOUR_Pos) | + (initStruct->Date << RTC_DATHUR_DATE_Pos); + + RTCx->MONDAY = (calcWeekDay(initStruct->Year, initStruct->Month, initStruct->Date) << RTC_MONDAY_DAY_Pos) | + (initStruct->Month << RTC_MONDAY_MON_Pos); + + RTCx->YEAR = initStruct->Year - 1901; + + RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos; + + RTCx->IF = 0x1F; + RTCx->IE = (initStruct->SecondIEn << RTC_IE_SEC_Pos) | + (initStruct->MinuteIEn << RTC_IE_MIN_Pos); + + if(initStruct->SecondIEn | initStruct->MinuteIEn) + { + NVIC_EnableIRQ(RTC_IRQn); + } + else + { + NVIC_DisableIRQ(RTC_IRQn); + } +} + +/****************************************************************************************************************************************** +* : RTC_Start() +* ˵: RTC +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_Start(RTC_TypeDef * RTCx) +{ + RTCx->EN = 1; +} + +/****************************************************************************************************************************************** +* : RTC_Stop() +* ˵: ֹͣRTC +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_Stop(RTC_TypeDef * RTCx) +{ + RTCx->EN = 0; +} + +/****************************************************************************************************************************************** +* : RTC_GetDateTime() +* ˵: ȡǰʱ +* : RTC_TypeDef * RTCx ָҪõRTCЧֵRTC +* RTC_DateTime * dateTime ȡʱ䡢ֵָָĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void RTC_GetDateTime(RTC_TypeDef * RTCx, RTC_DateTime * dateTime) +{ + dateTime->Year = RTCx->YEAR + 1901; + dateTime->Month = (RTCx->MONDAY & RTC_MONDAY_MON_Msk) >> RTC_MONDAY_MON_Pos; + dateTime->Date = (RTCx->DATHUR & RTC_DATHUR_DATE_Msk) >> RTC_DATHUR_DATE_Pos; + dateTime->Day = 1 << ((RTCx->MONDAY & RTC_MONDAY_DAY_Msk) >> RTC_MONDAY_DAY_Pos); + dateTime->Hour = (RTCx->DATHUR & RTC_DATHUR_HOUR_Msk) >> RTC_DATHUR_HOUR_Pos; + dateTime->Minute = (RTCx->MINSEC & RTC_MINSEC_MIN_Msk) >> RTC_MINSEC_MIN_Pos; + dateTime->Second = (RTCx->MINSEC & RTC_MINSEC_SEC_Msk) >> RTC_MINSEC_SEC_Pos; +} + +/****************************************************************************************************************************************** +* : RTC_AlarmSetup() +* ˵: RTC趨 +* : RTC_TypeDef * RTCx ָҪõRTCЧֵRTC +* RTC_AlarmStructure * alarmStruct RTC趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void RTC_AlarmSetup(RTC_TypeDef * RTCx, RTC_AlarmStructure * alarmStruct) +{ + while(RTCx->CFGABLE == 0); + + RTCx->MINSECAL = (alarmStruct->Second << RTC_MINSECAL_SEC_Pos) | + (alarmStruct->Minute << RTC_MINSECAL_MIN_Pos); + + RTCx->DAYHURAL = (alarmStruct->Hour << RTC_DAYHURAL_HOUR_Pos) | + (alarmStruct->Days << RTC_DAYHURAL_SUN_Pos); + + RTCx->LOAD = 1 << RTC_LOAD_ALARM_Pos; + while(RTCx->LOAD & RTC_LOAD_ALARM_Msk); + + RTCx->IF = (1 << RTC_IF_ALARM_Pos); + RTCx->IE &= ~RTC_IE_ALARM_Msk; + RTCx->IE |= (alarmStruct->AlarmIEn << RTC_IE_ALARM_Pos); + + if(alarmStruct->AlarmIEn) NVIC_EnableIRQ(RTC_IRQn); +} + +/****************************************************************************************************************************************** +* : calcWeekDay() +* ˵: ָꡢ¡ڼ +* : uint32_t year +* uint32_t month +* uint32_t date +* : uint32_t 0 1 һ ... ... 6 +* ע: +******************************************************************************************************************************************/ +static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) +{ + uint32_t i, cnt = 0; + const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + + for(i = 1; i < month; i++) cnt += daysOfMonth[i]; + + cnt += date; + + if((year%4 == 0) && ((year%100 != 0) || (year%400 == 0)) && (month >= 3)) cnt += 1; + + cnt += (year - 1901) * 365; + + for(i = 1901; i < year; i++) + { + if((i%4 == 0) && ((i%100 != 0) || (i%400 == 0))) cnt += 1; + } + + return (cnt+1) % 7; +} + +/****************************************************************************************************************************************** +* : RTC_IntSecondEn() +* ˵: жʹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntSecondEn(RTC_TypeDef * RTCx) +{ + RTCx->IE |= (1 << RTC_IE_SEC_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntSecondDis() +* ˵: жϽֹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntSecondDis(RTC_TypeDef * RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_SEC_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntSecondClr() +* ˵: жϱ־ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntSecondClr(RTC_TypeDef * RTCx) +{ + RTCx->IF = (1 << RTC_IF_SEC_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntSecondStat() +* ˵: ж״̬ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t RTC_IntSecondStat(RTC_TypeDef * RTCx) +{ + return (RTCx->IF & RTC_IF_SEC_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : RTC_IntMinuteEn() +* ˵: жʹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntMinuteEn(RTC_TypeDef * RTCx) +{ + RTCx->IE |= (1 << RTC_IE_MIN_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntMinuteDis() +* ˵: жϽֹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntMinuteDis(RTC_TypeDef * RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_MIN_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntMinuteClr() +* ˵: жϱ־ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntMinuteClr(RTC_TypeDef * RTCx) +{ + RTCx->IF = (1 << RTC_IF_MIN_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntMinuteStat() +* ˵: ж״̬ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t RTC_IntMinuteStat(RTC_TypeDef * RTCx) +{ + return (RTCx->IF & RTC_IF_MIN_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : RTC_IntHourEn() +* ˵: ʱжʹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntHourEn(RTC_TypeDef * RTCx) +{ + RTCx->IE |= (1 << RTC_IE_HOUR_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntHourDis() +* ˵: ʱжϽֹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntHourDis(RTC_TypeDef * RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_HOUR_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntHourClr() +* ˵: ʱжϱ־ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntHourClr(RTC_TypeDef * RTCx) +{ + RTCx->IF = (1 << RTC_IF_HOUR_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntHourStat() +* ˵: ʱж״̬ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : uint32_t 1 ʱжϷ 0 ʱжδ +* ע: +******************************************************************************************************************************************/ +uint32_t RTC_IntHourStat(RTC_TypeDef * RTCx) +{ + return (RTCx->IF & RTC_IF_HOUR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : RTC_IntDateEn() +* ˵: жʹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntDateEn(RTC_TypeDef * RTCx) +{ + RTCx->IE |= (1 << RTC_IE_DATE_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntDateDis() +* ˵: жϽֹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntDateDis(RTC_TypeDef * RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_DATE_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntDateClr() +* ˵: жϱ־ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntDateClr(RTC_TypeDef * RTCx) +{ + RTCx->IF = (1 << RTC_IF_DATE_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntDateStat() +* ˵: ж״̬ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t RTC_IntDateStat(RTC_TypeDef * RTCx) +{ + return (RTCx->IF & RTC_IF_DATE_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : RTC_IntAlarmEn() +* ˵: жʹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntAlarmEn(RTC_TypeDef * RTCx) +{ + RTCx->IE |= (1 << RTC_IE_ALARM_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntAlarmDis() +* ˵: жϽֹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntAlarmDis(RTC_TypeDef * RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_ALARM_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntAlarmClr() +* ˵: жϱ־ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntAlarmClr(RTC_TypeDef * RTCx) +{ + RTCx->IF = (1 << RTC_IF_ALARM_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntAlarmStat() +* ˵: ж״̬ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t RTC_IntAlarmStat(RTC_TypeDef * RTCx) +{ + return (RTCx->IF & RTC_IF_ALARM_Msk) ? 1 : 0; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..513f885cf6f76383e631bad692ffdede8e20360f --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h @@ -0,0 +1,73 @@ +#ifndef __SWM320_RTC_H__ +#define __SWM320_RTC_H__ + + +#define RTC_SUN 0x01 +#define RTC_MON 0x02 +#define RTC_TUE 0x04 +#define RTC_WED 0x08 +#define RTC_THU 0x10 +#define RTC_FRI 0x20 +#define RTC_SAT 0x40 + + +typedef struct { + uint16_t Year; + uint8_t Month; //ȡֵ1--12 + uint8_t Date; //ȡֵ1--31 + uint8_t Hour; //ȡֵ0--23 + uint8_t Minute; //ȡֵ0--59 + uint8_t Second; //ȡֵ0--59 + uint8_t SecondIEn; + uint8_t MinuteIEn; +} RTC_InitStructure; + +typedef struct { + uint8_t Days; //RTC_SUNRTC_MONRTC_TUERTC_WEDRTC_THURTC_FRIRTC_SAT + uint8_t Hour; + uint8_t Minute; + uint8_t Second; + uint8_t AlarmIEn; +} RTC_AlarmStructure; + +typedef struct { + uint16_t Year; + uint8_t Month; + uint8_t Date; + uint8_t Day; //RTC_SUNRTC_MONRTC_TUERTC_WEDRTC_THURTC_FRIRTC_SAT + uint8_t Hour; + uint8_t Minute; + uint8_t Second; +} RTC_DateTime; + +void RTC_Init(RTC_TypeDef * RTCx, RTC_InitStructure * initStruct); +void RTC_Start(RTC_TypeDef * RTCx); +void RTC_Stop(RTC_TypeDef * RTCx); + +void RTC_GetDateTime(RTC_TypeDef * RTCx, RTC_DateTime * dateTime); + +void RTC_AlarmSetup(RTC_TypeDef * RTCx, RTC_AlarmStructure * alarmStruct); + + +void RTC_IntSecondEn(RTC_TypeDef * RTCx); +void RTC_IntSecondDis(RTC_TypeDef * RTCx); +void RTC_IntSecondClr(RTC_TypeDef * RTCx); +uint32_t RTC_IntSecondStat(RTC_TypeDef * RTCx); +void RTC_IntMinuteEn(RTC_TypeDef * RTCx); +void RTC_IntMinuteDis(RTC_TypeDef * RTCx); +void RTC_IntMinuteClr(RTC_TypeDef * RTCx); +uint32_t RTC_IntMinuteStat(RTC_TypeDef * RTCx); +void RTC_IntHourEn(RTC_TypeDef * RTCx); +void RTC_IntHourDis(RTC_TypeDef * RTCx); +void RTC_IntHourClr(RTC_TypeDef * RTCx); +uint32_t RTC_IntHourStat(RTC_TypeDef * RTCx); +void RTC_IntDateEn(RTC_TypeDef * RTCx); +void RTC_IntDateDis(RTC_TypeDef * RTCx); +void RTC_IntDateClr(RTC_TypeDef * RTCx); +uint32_t RTC_IntDateStat(RTC_TypeDef * RTCx); +void RTC_IntAlarmEn(RTC_TypeDef * RTCx); +void RTC_IntAlarmDis(RTC_TypeDef * RTCx); +void RTC_IntAlarmClr(RTC_TypeDef * RTCx); +uint32_t RTC_IntAlarmStat(RTC_TypeDef * RTCx); + +#endif //__SWM320_RTC_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c new file mode 100644 index 0000000000000000000000000000000000000000..2cb8b9e3e8952f7e39b093ffa07f65e9dc12242d --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c @@ -0,0 +1,594 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_sdio.c +* ˵: SWM320ƬSDIOӿ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: Ϊͨԡԡԣֻ֧512ֽΪλĶд +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_sdio.h" + + +SD_CardInfo SD_cardInfo; + +/****************************************************************************************************************************************** +* : SDIO_Init() +* ˵: SDIOдSDʼʼɸ4ģʽд512ֽڴС +* : uint32_t freq SDIO_CLKʱƵ +* : uint32_t SD_RES_OK ɹ SD_RES_ERR ʧ SD_RES_TIMEOUT ʱ +* ע: +******************************************************************************************************************************************/ +uint32_t SDIO_Init(uint32_t freq) +{ + uint32_t res; + uint32_t resp, resps[4]; + + SYS->CLKDIV &= ~SYS_CLKDIV_SDIO_Msk; + if(SystemCoreClock > 80000000) //SDIOʱҪС52MHz + SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4 + else + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2 + + SYS->CLKEN |= (0x01 << SYS_CLKEN_SDIO_Pos); + + SDIO->CR2 = (1 << SDIO_CR2_RSTALL_Pos); + + SDIO->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | + (0 << SDIO_CR1_8BIT_Pos) | + (0 << SDIO_CR1_4BIT_Pos) | + (1 << SDIO_CR1_PWRON_Pos) | + (7 << SDIO_CR1_VOLT_Pos); + + SDIO->CR2 = (1 << SDIO_CR2_CLKEN_Pos) | + (1 << SDIO_CR2_SDCLKEN_Pos) | + (calcSDCLKDiv(100000) << SDIO_CR2_SDCLKDIV_Pos) | + (0xC << SDIO_CR2_TIMEOUT_Pos); // 2**25 SDIO_CLK + + while((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0); + + SDIO->IFE = 0xFFFFFFFF; + + + SDIO_SendCmd(SD_CMD_GO_IDLE_STATE, 0x00, SD_RESP_NO, 0); //CMD0: GO_IDLE_STATE + + res = SDIO_SendCmd(SD_CMD_SEND_IF_COND, 0x1AA, SD_RESP_32b, &resp); //CMD8: SEND_IF_COND, ⹤ѹǷ֧SD 2.0 + if(res != SD_RES_OK) + return res; + + if(resp == 0x1AA) SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; + else SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; + + do //ACMD41: SD_CMD_SD_APP_OP_COND + { + res = SDIO_SendCmd(SD_CMD_APP_CMD, 0x00, SD_RESP_32b, &resp); + if(res != SD_RES_OK) + return res; + + if(resp != 0x120) return SD_RES_ERR; //SDMMC + + if(SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0) + SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000|0x40000000, SD_RESP_32b, &resp); + else + SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000|0x00000000, SD_RESP_32b, &resp); + } while(((resp >> 31) & 0x01) == 0); //ϵûʱresp[31] == 0 + + if(((resp >> 30) & 0x01) == 1) SD_cardInfo.CardType = SDIO_HIGH_CAPACITY_SD_CARD; + + + SDIO_SendCmd(SD_CMD_ALL_SEND_CID, 0x00, SD_RESP_128b, resps); //CMD2: SD_CMD_ALL_SEND_CIDȡCID + + parseCID(resps); + + + SDIO_SendCmd(SD_CMD_SET_REL_ADDR, 0x00, SD_RESP_32b, &resp); //CMD3: SD_CMD_SET_REL_ADDRRCA + + SD_cardInfo.RCA = resp >> 16; + + + SDIO_SendCmd(SD_CMD_SEND_CSD, SD_cardInfo.RCA << 16, SD_RESP_128b, resps); //CMD9: SD_CMD_SEND_CSDȡCSD + + parseCSD(resps); + + if(SD_cardInfo.CardBlockSize < 0x200) return SD_RES_ERR; //ֻ֧512ֽΪλĶддλ벻С512 + + + SDIO->CR2 &= ~(SDIO_CR2_SDCLKEN_Msk | SDIO_CR2_SDCLKDIV_Msk); + SDIO->CR2 |= (1 << SDIO_CR2_SDCLKEN_Pos) | + (calcSDCLKDiv(freq) << SDIO_CR2_SDCLKDIV_Pos); //ʼɣSDCLKл + + + SDIO_SendCmd(SD_CMD_SEL_DESEL_CARD, SD_cardInfo.RCA << 16, SD_RESP_32b_busy, &resp); //CMD7: ѡпStandyģʽTransferģʽ + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + SDIO_SendCmd(SD_CMD_APP_CMD, SD_cardInfo.RCA << 16, SD_RESP_32b, &resp); + + SDIO_SendCmd(SD_CMD_APP_SD_SET_BUSWIDTH, SD_BUSWIDTH_4b, SD_RESP_32b, &resp); //л4λģʽ + + SDIO->CR1 |= (1 << SDIO_CR1_4BIT_Pos); + + + SDIO_SendCmd(SD_CMD_SET_BLOCKLEN, 512, SD_RESP_32b, &resp); //̶Сλ512ֽ + + SDIO->BLK = 512; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* : SDIO_BlockWrite() +* ˵: SDд +* : uint32_t block_addr SDַÿ512ֽ +* uint32_t buff[] Ҫд +* : uint32_t SD_RES_OK ɹ SD_RES_ERR ʧ SD_RES_TIMEOUT ʱ +* ע: +******************************************************************************************************************************************/ +uint32_t SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]) +{ + uint32_t res, i; + uint32_t addr, resp; + + if(SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; + else addr = block_addr * 512; + + res = SDIO_SendCmdWithData(SD_CMD_WRITE_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 0, 1); + if(res != SD_RES_OK) + return res; + + while((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0) __NOP(); + SDIO->IF = SDIO_IF_BUFWRRDY_Msk; + + for(i = 0; i < 512/4; i++) SDIO->DATA = buff[i]; + + while((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* : SDIO_MultiBlockWrite() +* ˵: SDд +* : uint32_t block_addr SDַÿ512ֽ +* uint16_t block_cnt ҪдĿ +* uint32_t buff[] Ҫд +* : uint32_t SD_RES_OK ɹ SD_RES_ERR ʧ SD_RES_TIMEOUT ʱ +* ע: +******************************************************************************************************************************************/ +uint32_t SDIO_MultiBlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) +{ + uint32_t res, i, j; + uint32_t addr, resp; + + if(SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; + else addr = block_addr * 512; + + res = SDIO_SendCmdWithData(SD_CMD_WRITE_MULT_BLOCK, addr, SD_RESP_32b, &resp, 0, block_cnt); + if(res != SD_RES_OK) + return res; + + for(i = 0; i < block_cnt; i++) + { + while((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0) __NOP(); + SDIO->IF = SDIO_IF_BUFWRRDY_Msk; + + for(j = 0; j < 512/4; j++) SDIO->DATA = buff[i*(512/4) + j]; + } + + while((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* : SDIO_DMABlockWrite() +* ˵: ͨDMASDд +* : uint32_t block_addr SDַÿ512ֽ +* uint16_t block_cnt ҪдĿ +* uint32_t buff[] Ҫд +* : uint32_t SD_RES_OK ɹ SD_RES_ERR ʧ SD_RES_TIMEOUT ʱ +* ע: +******************************************************************************************************************************************/ +uint32_t SDIO_DMABlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) +{ + uint32_t res; + uint32_t addr, resp; + + if(SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; + else addr = block_addr * 512; + + SDIO->DMA_MEM_ADDR = (uint32_t) buff; + + res = SDIO_SendCmdWithDataByDMA(SD_CMD_WRITE_MULT_BLOCK, addr, SD_RESP_32b, &resp, 0, block_cnt); + if(res != SD_RES_OK) + return res; + + while((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* : SDIO_BlockRead() +* ˵: SD +* : uint32_t block_addr SDַÿ512ֽ +* uint32_t buff[] +* : uint32_t SD_RES_OK ɹ SD_RES_ERR ʧ SD_RES_TIMEOUT ʱ +* ע: +******************************************************************************************************************************************/ +uint32_t SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]) +{ + uint32_t res, i; + uint32_t addr, resp; + + if(SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; + else addr = block_addr * 512; + + res = SDIO_SendCmdWithData(SD_CMD_READ_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 1); + if(res != SD_RES_OK) + return res; + + while((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0) __NOP(); + SDIO->IF = SDIO_IF_BUFRDRDY_Msk; + + for(i = 0; i < 512/4; i++) buff[i] = SDIO->DATA; + + while((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* : SDIO_MultiBlockRead() +* ˵: SD +* : uint32_t block_addr SDַÿ512ֽ +* uint16_t block_cnt ҪĿ +* uint32_t buff[] +* : uint32_t SD_RES_OK ɹ SD_RES_ERR ʧ SD_RES_TIMEOUT ʱ +* ע: +******************************************************************************************************************************************/ +uint32_t SDIO_MultiBlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) +{ + uint32_t res, i, j; + uint32_t addr, resp; + + if(SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; + else addr = block_addr * 512; + + res = SDIO_SendCmdWithData(SD_CMD_READ_MULT_BLOCK, addr, SD_RESP_32b, &resp, 1, block_cnt); + if(res != SD_RES_OK) + return res; + + for(i = 0; i < block_cnt; i++) + { + while((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0) __NOP(); + SDIO->IF = SDIO_IF_BUFRDRDY_Msk; + + for(j = 0; j < 512/4; j++) buff[i*(512/4) + j] = SDIO->DATA; + } + + while((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* : SDIO_DMABlockRead() +* ˵: ͨDMASD +* : uint32_t block_addr SDַÿ512ֽ +* uint16_t block_cnt ҪĿ +* uint32_t buff[] +* : uint32_t SD_RES_OK ɹ SD_RES_ERR ʧ SD_RES_TIMEOUT ʱ +* ע: +******************************************************************************************************************************************/ +uint32_t SDIO_DMABlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) +{ + uint32_t res; + uint32_t addr, resp; + + if(SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; + else addr = block_addr * 512; + + SDIO->DMA_MEM_ADDR = (uint32_t)buff; + + res = SDIO_SendCmdWithDataByDMA(SD_CMD_READ_MULT_BLOCK, addr, SD_RESP_32b, &resp, 1, block_cnt); + if(res != SD_RES_OK) + return res; + + while((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* : _SDIO_SendCmd() +* ˵: SDIOSD +* : uint32_t cmd +* uint32_t arg +* uint32_t _resp_type ӦͣȡֵSD_RESP_NOSD_RESP_32bSD_RESP_128bSD_RESP_32b_busy +* uint32_t *resp_data Ӧ +* uint32_t have_data Ƿݴ +* uint32_t data_read 1 SD 0 дSD +* uint16_t block_cnt д +* uint32_t use_dma 1 ʹDMA +* : uint32_t SD_RES_OK ɹ SD_RES_ERR ʧ SD_RES_TIMEOUT ʱ +* ע: +******************************************************************************************************************************************/ +uint32_t _SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t _resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read, uint16_t block_cnt, uint32_t use_dma) +{ + SDIO->BLK &= ~SDIO_BLK_COUNT_Msk; + SDIO->BLK |= (block_cnt << SDIO_BLK_COUNT_Pos); + + SDIO->ARG = arg; + SDIO->CMD = (cmd << SDIO_CMD_CMDINDX_Pos) | + (0 << SDIO_CMD_CMDTYPE_Pos) | + (0 << SDIO_CMD_IDXCHECK_Pos) | + (0 << SDIO_CMD_CRCCHECK_Pos) | + (_resp_type << SDIO_CMD_RESPTYPE_Pos) | + (have_data << SDIO_CMD_HAVEDATA_Pos) | + (data_read << SDIO_CMD_DIRREAD_Pos) | + ((block_cnt > 1) << SDIO_CMD_MULTBLK_Pos) | + ((block_cnt > 1) << SDIO_CMD_BLKCNTEN_Pos) | + ((block_cnt > 1) << SDIO_CMD_AUTOCMD12_Pos) | + (use_dma << SDIO_CMD_DMAEN_Pos); + + while((SDIO->IF & SDIO_IF_CMDDONE_Msk) == 0) + { + if(SDIO->IF & SDIO_IF_CMDTIMEOUT_Msk) + { + SDIO->IF = SDIO_IF_CMDTIMEOUT_Msk; + + return SD_RES_TIMEOUT; + } + else if(SDIO->IF & SDIO_IF_ERROR_Msk) + { + SDIO->IF = 0xFFFFFFFF; + + return SD_RES_ERR; + } + } + SDIO->IF = SDIO_IF_CMDDONE_Msk; + + if(_resp_type == SD_RESP_32b) + { + resp_data[0] = SDIO->RESP[0]; + } + else if(_resp_type == SD_RESP_128b) + { + //ĴнCID/CSD[127-8]δRESP3-0[119-0]λCRC + //ʱ˳򣬽CID/CSD[127-8]resp_data0-3[127-8]8λ0x00 + resp_data[0] = (SDIO->RESP[3] << 8) + ((SDIO->RESP[2] >> 24) & 0xFF); + resp_data[1] = (SDIO->RESP[2] << 8) + ((SDIO->RESP[1] >> 24) & 0xFF); + resp_data[2] = (SDIO->RESP[1] << 8) + ((SDIO->RESP[0] >> 24) & 0xFF); + resp_data[3] = (SDIO->RESP[0] << 8) + 0x00; + } + + return SD_RES_OK; +} + + +void parseCID(uint32_t CID_Tab[4]) +{ + uint8_t tmp = 0; + + /*!< Byte 0 */ + tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ManufacturerID = tmp; + + /*!< Byte 1 */ + tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.OEM_AppliID = tmp << 8; + + /*!< Byte 2 */ + tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8); + SD_cardInfo.SD_cid.OEM_AppliID |= tmp; + + /*!< Byte 3 */ + tmp = (uint8_t)(CID_Tab[0] & 0x000000FF); + SD_cardInfo.SD_cid.ProdName1 = tmp << 24; + + /*!< Byte 4 */ + tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ProdName1 |= tmp << 16; + + /*!< Byte 5 */ + tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.ProdName1 |= tmp << 8; + + /*!< Byte 6 */ + tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8); + SD_cardInfo.SD_cid.ProdName1 |= tmp; + + /*!< Byte 7 */ + tmp = (uint8_t)(CID_Tab[1] & 0x000000FF); + SD_cardInfo.SD_cid.ProdName2 = tmp; + + /*!< Byte 8 */ + tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ProdRev = tmp; + + /*!< Byte 9 */ + tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.ProdSN = tmp << 24; + + /*!< Byte 10 */ + tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8); + SD_cardInfo.SD_cid.ProdSN |= tmp << 16; + + /*!< Byte 11 */ + tmp = (uint8_t)(CID_Tab[2] & 0x000000FF); + SD_cardInfo.SD_cid.ProdSN |= tmp << 8; + + /*!< Byte 12 */ + tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ProdSN |= tmp; + + /*!< Byte 13 */ + tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; + SD_cardInfo.SD_cid.ManufactDate = (tmp & 0x0F) << 8; + + /*!< Byte 14 */ + tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8); + SD_cardInfo.SD_cid.ManufactDate |= tmp; +} + +void parseCSD(uint32_t CSD_Tab[4]) +{ + uint8_t tmp = 0; + + /*!< Byte 0 */ + tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.CSDStruct = (tmp & 0xC0) >> 6; + SD_cardInfo.SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2; + SD_cardInfo.SD_csd.Reserved1 = tmp & 0x03; + + /*!< Byte 1 */ + tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.TAAC = tmp; + + /*!< Byte 2 */ + tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.NSAC = tmp; + + /*!< Byte 3 */ + tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF); + SD_cardInfo.SD_csd.MaxBusClkFrec = tmp; + + /*!< Byte 4 */ + tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.CardComdClasses = tmp << 4; + + /*!< Byte 5 */ + tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4; + SD_cardInfo.SD_csd.RdBlockLen = tmp & 0x0F; + + /*!< Byte 6 */ + tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.PartBlockRead = (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6; + SD_cardInfo.SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5; + SD_cardInfo.SD_csd.DSRImpl = (tmp & 0x10) >> 4; + SD_cardInfo.SD_csd.Reserved2 = 0; /*!< Reserved */ + + if ((SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || + (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) + { + SD_cardInfo.SD_csd.DeviceSize = (tmp & 0x03) << 10; + + /*!< Byte 7 */ + tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); + SD_cardInfo.SD_csd.DeviceSize |= (tmp) << 2; + + /*!< Byte 8 */ + tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; + + SD_cardInfo.SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; + SD_cardInfo.SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); + + /*!< Byte 9 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; + SD_cardInfo.SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; + SD_cardInfo.SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; + /*!< Byte 10 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; + + SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1) ; + SD_cardInfo.CardCapacity *= (1 << (SD_cardInfo.SD_csd.DeviceSizeMul + 2)); + SD_cardInfo.CardBlockSize = 1 << (SD_cardInfo.SD_csd.RdBlockLen); + SD_cardInfo.CardCapacity *= SD_cardInfo.CardBlockSize; + } + else if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + /*!< Byte 7 */ + tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); + SD_cardInfo.SD_csd.DeviceSize = (tmp & 0x3F) << 16; + + /*!< Byte 8 */ + tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); + + SD_cardInfo.SD_csd.DeviceSize |= (tmp << 8); + + /*!< Byte 9 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); + + SD_cardInfo.SD_csd.DeviceSize |= (tmp); + + /*!< Byte 10 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); + + SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1) * 512 * 1024; + SD_cardInfo.CardBlockSize = 512; + } + + SD_cardInfo.SD_csd.EraseGrSize = (tmp & 0x40) >> 6; + SD_cardInfo.SD_csd.EraseGrMul = (tmp & 0x3F) << 1; + + /*!< Byte 11 */ + tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF); + SD_cardInfo.SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.WrProtectGrSize = (tmp & 0x7F); + + /*!< Byte 12 */ + tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.ManDeflECC = (tmp & 0x60) >> 5; + SD_cardInfo.SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; + SD_cardInfo.SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; + + /*!< Byte 13 */ + tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; + SD_cardInfo.SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; + SD_cardInfo.SD_csd.Reserved3 = 0; + SD_cardInfo.SD_csd.ContentProtectAppli = (tmp & 0x01); + + /*!< Byte 14 */ + tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.CopyFlag = (tmp & 0x40) >> 6; + SD_cardInfo.SD_csd.PermWrProtect = (tmp & 0x20) >> 5; + SD_cardInfo.SD_csd.TempWrProtect = (tmp & 0x10) >> 4; + SD_cardInfo.SD_csd.FileFormat = (tmp & 0x0C) >> 2; + SD_cardInfo.SD_csd.ECC = (tmp & 0x03); +} + +uint32_t calcSDCLKDiv(uint32_t freq) +{ + uint32_t prediv = ((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos); + uint32_t clkdiv = (SystemCoreClock / (1 << prediv)) / freq; + uint32_t regdiv = 0; + + if(clkdiv > 128) regdiv = 0x80; + else if(clkdiv > 64) regdiv = 0x40; + else if(clkdiv > 32) regdiv = 0x20; + else if(clkdiv > 16) regdiv = 0x10; + else if(clkdiv > 8) regdiv = 0x08; + else if(clkdiv > 4) regdiv = 0x04; + else if(clkdiv > 2) regdiv = 0x02; + else if(clkdiv > 1) regdiv = 0x01; + else regdiv = 0x00; + + return regdiv; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h new file mode 100644 index 0000000000000000000000000000000000000000..ece2711ce45e60383b5570b76f838a87ce4e39c7 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h @@ -0,0 +1,147 @@ +#ifndef __SWM320_SDIO_H__ +#define __SWM320_SDIO_H__ + + +#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) +#define SD_CMD_SEND_OP_COND ((uint8_t)1) +#define SD_CMD_ALL_SEND_CID ((uint8_t)2) +#define SD_CMD_SET_REL_ADDR ((uint8_t)3) +#define SD_CMD_SET_DSR ((uint8_t)4) +#define SD_CMD_HS_SWITCH ((uint8_t)6) +#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) +#define SD_CMD_SEND_IF_COND ((uint8_t)8) +#define SD_CMD_SEND_CSD ((uint8_t)9) +#define SD_CMD_SEND_CID ((uint8_t)10) +#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) +#define SD_CMD_SEND_STATUS ((uint8_t)13) +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) +#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) +#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) +#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) +#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) +#define SD_CMD_PROG_CID ((uint8_t)26) +#define SD_CMD_PROG_CSD ((uint8_t)27) +#define SD_CMD_APP_CMD ((uint8_t)55) + +/*Following commands are SD Card Specific commands. + SDIO_APP_CMD should be sent before sending these commands. */ +#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) +#define SD_CMD_SD_APP_STAUS ((uint8_t)13) +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) +#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) +#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) +#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) +#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) + + +#define SD_RESP_NO 0 //0 Ӧ +#define SD_RESP_32b 2 //2 32λӦ +#define SD_RESP_128b 1 //1 128λӦ +#define SD_RESP_32b_busy 3 //3 32λӦcheck Busy after response + +#define SD_BUSWIDTH_1b 0 +#define SD_BUSWIDTH_4b 2 + +#define SD_RES_OK 0 +#define SD_RES_ERR 1 +#define SD_RES_TIMEOUT 2 + + +typedef struct +{ + __IO uint8_t CSDStruct; // CSD structure + __IO uint8_t SysSpecVersion; // System specification version + __IO uint8_t Reserved1; // Reserved + __IO uint8_t TAAC; // Data read access-time 1 + __IO uint8_t NSAC; // Data read access-time 2 in CLK cycles + __IO uint8_t MaxBusClkFrec; // Max. bus clock frequency + __IO uint16_t CardComdClasses; //< Card command classes + __IO uint8_t RdBlockLen; // Max. read data block length + __IO uint8_t PartBlockRead; // Partial blocks for read allowed + __IO uint8_t WrBlockMisalign; // Write block misalignment + __IO uint8_t RdBlockMisalign; // Read block misalignment + __IO uint8_t DSRImpl; // DSR implemented + __IO uint8_t Reserved2; // Reserved + __IO uint32_t DeviceSize; // Device Size + __IO uint8_t MaxRdCurrentVDDMin; // Max. read current @ VDD min + __IO uint8_t MaxRdCurrentVDDMax; // Max. read current @ VDD max + __IO uint8_t MaxWrCurrentVDDMin; // Max. write current @ VDD min + __IO uint8_t MaxWrCurrentVDDMax; // Max. write current @ VDD max + __IO uint8_t DeviceSizeMul; // Device size multiplier + __IO uint8_t EraseGrSize; // Erase group size + __IO uint8_t EraseGrMul; // Erase group size multiplier + __IO uint8_t WrProtectGrSize; // Write protect group size + __IO uint8_t WrProtectGrEnable; // Write protect group enable + __IO uint8_t ManDeflECC; // Manufacturer default ECC + __IO uint8_t WrSpeedFact; // Write speed factor + __IO uint8_t MaxWrBlockLen; // Max. write data block length + __IO uint8_t WriteBlockPaPartial; // Partial blocks for write allowed + __IO uint8_t Reserved3; // Reserded + __IO uint8_t ContentProtectAppli; // Content protection application + __IO uint8_t FileFormatGrouop; // File format group + __IO uint8_t CopyFlag; // Copy flag (OTP) + __IO uint8_t PermWrProtect; // Permanent write protection + __IO uint8_t TempWrProtect; // Temporary write protection + __IO uint8_t FileFormat; // File Format + __IO uint8_t ECC; // ECC code +} SD_CSD; + +typedef struct +{ + __IO uint8_t ManufacturerID; // ManufacturerID + __IO uint16_t OEM_AppliID; // OEM/Application ID + __IO uint32_t ProdName1; // Product Name part1 + __IO uint8_t ProdName2; // Product Name part2 + __IO uint8_t ProdRev; // Product Revision + __IO uint32_t ProdSN; // Product Serial Number + __IO uint8_t Reserved1; // Reserved1 + __IO uint16_t ManufactDate; // Manufacturing Date +} SD_CID; + + +#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) +#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) +#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) +#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) +#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) +#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) +#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) +#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) + + +typedef struct +{ + SD_CSD SD_csd; + SD_CID SD_cid; + uint64_t CardCapacity; // Card Capacity + uint32_t CardBlockSize; // Card Block Size + uint16_t RCA; + uint8_t CardType; +} SD_CardInfo; + + +extern SD_CardInfo SD_cardInfo; + +uint32_t SDIO_Init(uint32_t freq); +uint32_t SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]); +uint32_t SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]); + +uint32_t SDIO_MultiBlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); +uint32_t SDIO_MultiBlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); + +uint32_t SDIO_DMABlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); +uint32_t SDIO_DMABlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); + +uint32_t _SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t _resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read, uint16_t block_cnt, uint32_t use_dma); + +#define SDIO_SendCmd(cmd, arg, _resp_type, resp_data) _SDIO_SendCmd(cmd, arg, _resp_type, resp_data, 0, 0, 0, 0) +#define SDIO_SendCmdWithData(cmd, arg, _resp_type, resp_data, data_read, block_cnt) _SDIO_SendCmd(cmd, arg, _resp_type, resp_data, 1, data_read, block_cnt, 0) +#define SDIO_SendCmdWithDataByDMA(cmd, arg, _resp_type, resp_data, data_read, block_cnt) _SDIO_SendCmd(cmd, arg, _resp_type, resp_data, 1, data_read, block_cnt, 1) + +void parseCID(uint32_t CID_Tab[4]); +void parseCSD(uint32_t CID_Tab[4]); + +uint32_t calcSDCLKDiv(uint32_t freq_sel); + +#endif //__SWM320_SDIO_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c new file mode 100644 index 0000000000000000000000000000000000000000..246f572eebf30e14ee5e53169415126a6ce07433 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c @@ -0,0 +1,103 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_sdram.c +* ˵: SWM320ƬSDRAM +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_sdram.h" + +/****************************************************************************************************************************************** +* : SDRAM_Init() +* ˵: SDRAMʼ +* : SDRAM_InitStructure * initStruct SDRAM 趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void SDRAM_Init(SDRAM_InitStructure * initStruct) +{ + uint32_t row_n; + + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + SYS->CLKDIV &= ~SYS_CLKDIV_SDRAM_Msk; + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDRAM_Pos); //2Ƶ + + SDRAMC->CR0 = (2 << SDRAMC_CR0_BURSTLEN_Pos) | //2 Burst LengthΪ4 + (initStruct->CASLatency << SDRAMC_CR0_CASDELAY_Pos); + + SDRAMC->CR1 = (initStruct->CellSize << SDRAMC_CR1_CELLSIZE_Pos) | + (initStruct->CellWidth << SDRAMC_CR1_CELL32BIT_Pos) | + (initStruct->CellBank << SDRAMC_CR1_BANK_Pos) | + (0 << SDRAMC_CR1_32BIT_Pos) | + (initStruct->TimeTMRD << SDRAMC_CR1_TMRD_Pos) | + (initStruct->TimeTRRD << SDRAMC_CR1_TRRD_Pos) | + (initStruct->TimeTRAS << SDRAMC_CR1_TRAS_Pos) | + (initStruct->TimeTRC << SDRAMC_CR1_TRC_Pos) | + (initStruct->TimeTRCD << SDRAMC_CR1_TRCD_Pos) | + (initStruct->TimeTRP << SDRAMC_CR1_TRP_Pos); + + SDRAMC->LATCH = 0x02; + + switch(initStruct->CellSize) + { + case SDRAM_CELLSIZE_16Mb: row_n = 11; break; + case SDRAM_CELLSIZE_64Mb: row_n = 12; break; + case SDRAM_CELLSIZE_128Mb: row_n = 12; break; + case SDRAM_CELLSIZE_256Mb: row_n = 13; break; + default: row_n = 13; break; + } + + SDRAMC->REFRESH = (1 << SDRAMC_REFRESH_EN_Pos) | + (((SystemCoreClock/2)/1000*64 / (1 << row_n)) << SDRAMC_REFRESH_RATE_Pos); + + while(SDRAMC->REFDONE == 0); +} + +/****************************************************************************************************************************************** +* : SDRAM_Enable() +* ˵: SDRAMʹܣʹܺɶдSDRAM +* : +* : +* ע: +******************************************************************************************************************************************/ +void SDRAM_Enable(void) +{ + uint32_t i; + + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + SDRAMC->REFRESH |= (1 << SDRAMC_REFRESH_EN_Pos); + + for(i = 0; i < 100; i++) __NOP(); +} + +/****************************************************************************************************************************************** +* : SDRAM_Disable() +* ˵: SDRAMܣܺSDRAM͹ģʽˢ£ɶд +* : +* : +* ע: +******************************************************************************************************************************************/ +void SDRAM_Disable(void) +{ + uint32_t i; + + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); + + for(i = 0; i < 100; i++) __NOP(); +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h new file mode 100644 index 0000000000000000000000000000000000000000..5659b3e330106f7c0e068d3de337c5b806e7ddee --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h @@ -0,0 +1,82 @@ +#ifndef __SWM320_SDRAM_H__ +#define __SWM320_SDRAM_H__ + +typedef struct { + uint8_t CellSize; // SDRAMSDRAM_CELLSIZE_16MbSDRAM_CELLSIZE_64MbSDRAM_CELLSIZE_128MbSDRAM_CELLSIZE_256Mb + uint8_t CellBank; // SDRAMмbankSDRAM_CELLBANK_2SDRAM_CELLBANK_4 + uint8_t CellWidth; // SDRAMλSDRAM_CELLWIDTH_16SDRAM_CELLWIDTH_32 + uint8_t CASLatency; // еַЧSDRAM_CASLATENCY_2SDRAM_CASLATENCY_3 + + uint8_t TimeTMRD; // MRS to New Command + uint8_t TimeTRRD; // Activate to activate on different banks + uint8_t TimeTRAS; // Self refresh timeСSelf-refresh + uint8_t TimeTRC; // Row cycle delayRefreshActivateʱҲRefreshʱ + uint8_t TimeTRCD; // Row to column delayеַеַʱҲActivateдʱ + uint8_t TimeTRP; // Row precharge delayPrechargeһʱ +} SDRAM_InitStructure; + +#define SDRAM_CELLSIZE_16Mb 3 +#define SDRAM_CELLSIZE_64Mb 0 +#define SDRAM_CELLSIZE_128Mb 1 +#define SDRAM_CELLSIZE_256Mb 2 + +#define SDRAM_CELLBANK_2 0 +#define SDRAM_CELLBANK_4 1 + +#define SDRAM_CELLWIDTH_16 0 +#define SDRAM_CELLWIDTH_32 1 + +#define SDRAM_CASLATENCY_2 2 +#define SDRAM_CASLATENCY_3 3 + +#define SDRAM_TMRD_3 3 +#define SDRAM_TMRD_4 4 +#define SDRAM_TMRD_5 5 +#define SDRAM_TMRD_6 6 +#define SDRAM_TMRD_7 7 + +#define SDRAM_TRRD_2 2 +#define SDRAM_TRRD_3 3 + +#define SDRAM_TRAS_2 2 +#define SDRAM_TRAS_3 3 +#define SDRAM_TRAS_4 4 +#define SDRAM_TRAS_5 5 +#define SDRAM_TRAS_6 6 +#define SDRAM_TRAS_7 7 + +#define SDRAM_TRC_2 2 +#define SDRAM_TRC_3 3 +#define SDRAM_TRC_4 4 +#define SDRAM_TRC_5 5 +#define SDRAM_TRC_6 6 +#define SDRAM_TRC_7 7 +#define SDRAM_TRC_8 8 +#define SDRAM_TRC_9 9 +#define SDRAM_TRC_10 10 +#define SDRAM_TRC_11 11 +#define SDRAM_TRC_12 12 +#define SDRAM_TRC_13 13 +#define SDRAM_TRC_14 14 +#define SDRAM_TRC_15 15 + +#define SDRAM_TRCD_3 3 +#define SDRAM_TRCD_4 4 +#define SDRAM_TRCD_5 5 +#define SDRAM_TRCD_6 6 +#define SDRAM_TRCD_7 7 + +#define SDRAM_TRP_3 3 +#define SDRAM_TRP_4 4 +#define SDRAM_TRP_5 5 +#define SDRAM_TRP_6 6 +#define SDRAM_TRP_7 7 + + + +void SDRAM_Init(SDRAM_InitStructure * initStruct); + +void SDRAM_Enable(void); +void SDRAM_Disable(void); + +#endif //__SWM320_SDRAM_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_spi.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..fb38187a3f18b7f218e8a5388c699b76b4b22353 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_spi.c @@ -0,0 +1,543 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_spi.c +* ˵: SWM320ƬSPI +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_spi.h" + + +/****************************************************************************************************************************************** +* : SPI_Init() +* ˵: SPIͬнӿڳʼ֡趨ʱ趨ٶ趨ж趨FIFO趨 +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* SPI_InitStructure * initStruct SPI趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Init(SPI_TypeDef * SPIx, SPI_InitStructure * initStruct) +{ + switch((uint32_t)SPIx) + { + case ((uint32_t)SPI0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); + break; + + case ((uint32_t)SPI1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); //SPI0ʹͬһλʱʹ + break; + } + + SPI_Close(SPIx); //һЩؼĴֻSPIرʱ + + SPIx->CTRL &= ~(SPI_CTRL_FFS_Msk | SPI_CTRL_CPHA_Msk | SPI_CTRL_CPOL_Msk | + SPI_CTRL_SIZE_Msk | SPI_CTRL_MSTR_Msk | SPI_CTRL_CLKDIV_Msk | SPI_CTRL_SSN_H_Msk); + SPIx->CTRL |= (initStruct->FrameFormat << SPI_CTRL_FFS_Pos) | + (initStruct->SampleEdge << SPI_CTRL_CPHA_Pos) | + (initStruct->IdleLevel << SPI_CTRL_CPOL_Pos) | + ((initStruct->WordSize-1) << SPI_CTRL_SIZE_Pos) | + (initStruct->Master << SPI_CTRL_MSTR_Pos) | + (initStruct->clkDiv << SPI_CTRL_CLKDIV_Pos) | + (0 << SPI_CTRL_SSN_H_Pos); + + SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); //жϱ־ + SPIx->IE &= ~(SPI_IE_RFHF_Msk | SPI_IE_TFHF_Msk | SPI_IE_FTC_Msk); + SPIx->IE |= (initStruct->RXHFullIEn << SPI_IE_RFHF_Pos) | + (initStruct->TXEmptyIEn << SPI_IE_TFHF_Pos) | + (initStruct->TXCompleteIEn << SPI_IE_FTC_Pos); + + switch((uint32_t)SPIx) + { + case ((uint32_t)SPI0): + if(initStruct->RXHFullIEn | initStruct->TXEmptyIEn | initStruct->TXCompleteIEn) + { + NVIC_EnableIRQ(SPI0_IRQn); + } + else + { + NVIC_DisableIRQ(SPI0_IRQn); + } + break; + + case ((uint32_t)SPI1): + if(initStruct->RXHFullIEn | initStruct->TXEmptyIEn | initStruct->TXCompleteIEn) + { + NVIC_EnableIRQ(SPI1_IRQn); + } + else + { + NVIC_DisableIRQ(SPI1_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : SPI_Open() +* ˵: SPI򿪣շ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Open(SPI_TypeDef * SPIx) +{ + SPIx->CTRL |= (0x01 << SPI_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_Close() +* ˵: SPIرգֹշ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Close(SPI_TypeDef * SPIx) +{ + SPIx->CTRL &= ~SPI_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* : SPI_Read() +* ˵: ȡһ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t ȡ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_Read(SPI_TypeDef * SPIx) +{ + return SPIx->DATA; +} + +/****************************************************************************************************************************************** +* : SPI_Write() +* ˵: дһ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* uint32_t Ҫд +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Write(SPI_TypeDef * SPIx, uint32_t data) +{ + SPIx->DATA = data; +} + +/****************************************************************************************************************************************** +* : SPI_WriteWithWait() +* ˵: дһݲȴȫͳȥ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1SPI1 +* uint32_t Ҫд +* : +* ע: +******************************************************************************************************************************************/ +void SPI_WriteWithWait(SPI_TypeDef * SPIx, uint32_t data) +{ + SPIx->STAT |= (1 << SPI_STAT_WTC_Pos); + + SPIx->DATA = data; + + while((SPIx->STAT & SPI_STAT_WTC_Msk) == 0); +} + +/****************************************************************************************************************************************** +* : SPI_ReadWrite() +* ˵: һݣط͹нյ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* uint32_t data Ҫ͵ +* : uint32_t յ +* ע: ͬһSPIģ飬˺ӦSPI_Write()ãΪSPI_Write()SPI_STAT_RFNE״̬ +******************************************************************************************************************************************/ +uint32_t SPI_ReadWrite(SPI_TypeDef * SPIx, uint32_t data) +{ + SPIx->DATA = data; + while(!(SPIx->STAT & SPI_STAT_RFNE_Msk)); + + return SPIx->DATA; +} + +/****************************************************************************************************************************************** +* : SPI_IsRXEmpty() +* ˵: FIFOǷգԼSPI_Read() +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_IsRXEmpty(SPI_TypeDef * SPIx) +{ + return (SPIx->STAT & SPI_STAT_RFNE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : SPI_IsTXFull() +* ˵: FIFOǷԼSPI_Write() +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFO +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_IsTXFull(SPI_TypeDef * SPIx) +{ + return (SPIx->STAT & SPI_STAT_TFNF_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : SPI_IsTXEmpty() +* ˵: FIFOǷ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_IsTXEmpty(SPI_TypeDef * SPIx) +{ + return (SPIx->STAT & SPI_STAT_TFE_Msk) ? 1 : 0; +} + + +/****************************************************************************************************************************************** +* : SPI_INTRXHalfFullEn() +* ˵: FIFOжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXHalfFullEn(SPI_TypeDef * SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_RFHF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXHalfFullDis() +* ˵: FIFOжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXHalfFullDis(SPI_TypeDef * SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_RFHF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXHalfFullClr() +* ˵: FIFOжϱ־ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXHalfFullClr(SPI_TypeDef * SPIx) +{ + SPIx->IF = (1 << SPI_IF_RFHF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXHalfFullStat() +* ˵: FIFOж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFOﵽ 0 FIFOδﵽ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef * SPIx) +{ + return (SPIx->IF & SPI_IF_RFHF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTRXFullEn() +* ˵: FIFOжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXFullEn(SPI_TypeDef * SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_RFF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXFullDis() +* ˵: FIFOжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXFullDis(SPI_TypeDef * SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_RFF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXFullClr() +* ˵: FIFOжϱ־ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXFullClr(SPI_TypeDef * SPIx) +{ + SPIx->IF = (1 << SPI_IF_RFF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXFullStat() +* ˵: FIFOж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFOδ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTRXFullStat(SPI_TypeDef * SPIx) +{ + return (SPIx->IF & SPI_IF_RFF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTRXOverflowEn() +* ˵: FIFOжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXOverflowEn(SPI_TypeDef * SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_RFOVF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXOverflowDis() +* ˵: FIFOжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXOverflowDis(SPI_TypeDef * SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_RFOVF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXOverflowClr() +* ˵: FIFOжϱ־ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXOverflowClr(SPI_TypeDef * SPIx) +{ + SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXOverflowStat() +* ˵: FIFOж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFOδ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTRXOverflowStat(SPI_TypeDef * SPIx) +{ + return (SPIx->IF & SPI_IF_RFOVF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTTXHalfFullEn() +* ˵: FIFOжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXHalfFullEn(SPI_TypeDef * SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_TFHF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXHalfFullDis() +* ˵: FIFOжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXHalfFullDis(SPI_TypeDef * SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_TFHF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXHalfFullClr() +* ˵: FIFOжϱ־ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXHalfFullClr(SPI_TypeDef * SPIx) +{ + SPIx->IF = (1 << SPI_IF_TFHF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXHalfFullStat() +* ˵: FIFOж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFOﵽ 0 FIFOδﵽ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef * SPIx) +{ + return (SPIx->IF & SPI_IF_TFHF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTTXEmptyEn() +* ˵: FIFOжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXEmptyEn(SPI_TypeDef * SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_TFE_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXEmptyDis() +* ˵: FIFOжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXEmptyDis(SPI_TypeDef * SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_TFE_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXEmptyClr() +* ˵: FIFOжϱ־ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXEmptyClr(SPI_TypeDef * SPIx) +{ + SPIx->IF = (1 << SPI_IF_TFE_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXEmptyStat() +* ˵: FIFOж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTTXEmptyStat(SPI_TypeDef * SPIx) +{ + return (SPIx->IF & SPI_IF_TFE_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTTXCompleteEn() +* ˵: FIFOҷλĴжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXCompleteEn(SPI_TypeDef * SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_FTC_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXCompleteDis() +* ˵: FIFOҷλĴжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXCompleteDis(SPI_TypeDef * SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_FTC_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXCompleteClr() +* ˵: FIFOҷλĴж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXCompleteClr(SPI_TypeDef * SPIx) +{ + SPIx->IF = (1 << SPI_IF_FTC_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXCompleteStat() +* ˵: FIFOҷλĴж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFOҷλĴ 0 FIFOλĴǿ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTTXCompleteStat(SPI_TypeDef * SPIx) +{ + return (SPIx->IF & SPI_IF_FTC_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTTXWordCompleteEn() +* ˵: FIFOַжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXWordCompleteEn(SPI_TypeDef * SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_WTC_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXWordCompleteDis() +* ˵: FIFOַжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXWordCompleteDis(SPI_TypeDef * SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_WTC_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXWordCompleteClr() +* ˵: FIFOַжϱ־ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXWordCompleteClr(SPI_TypeDef * SPIx) +{ + SPIx->IF = (1 << SPI_IF_WTC_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXWordCompleteStat() +* ˵: FIFOַж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 жѷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTTXWordCompleteStat(SPI_TypeDef * SPIx) +{ + return (SPIx->IF & SPI_IF_WTC_Msk) ? 1 : 0; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_spi.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..42c4d0cb707cdcfd5e0a00832b6fd074a80cb259 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_spi.h @@ -0,0 +1,83 @@ +#ifndef __SWM320_SPI_H__ +#define __SWM320_SPI_H__ + +typedef struct { + uint8_t FrameFormat; //֡ʽSPI_FORMAT_SPISPI_FORMAT_TI_SSI + uint8_t SampleEdge; //SPI֡ʽ£ѡݲأSPI_FIRST_EDGESPI_SECOND_EDGE + uint8_t IdleLevel; //SPI֡ʽ£ѡʱݴʱʱߵĵƽSPI_LOW_LEVELSPI_HIGH_LEVEL + uint8_t WordSize; //ֳ, Чֵ4-16 + uint8_t Master; //1 ģʽ 0 ӻģʽ + uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDivЧֵSPI_CLKDIV_4SPI_CLKDIV_8... ... SPI_CLKDIV_512 + + uint8_t RXHFullIEn; //FIFOжʹ + uint8_t TXEmptyIEn; //FIFO жʹ + uint8_t TXCompleteIEn; //FIFO ҷλĴжʹ +} SPI_InitStructure; + +#define SPI_FORMAT_SPI 0 //Motorola SPI ʽ +#define SPI_FORMAT_TI_SSI 1 //TI SSI ʽ + +#define SPI_FIRST_EDGE 0 //һʱؿʼ +#define SPI_SECOND_EDGE 1 //ڶʱؿʼ + +#define SPI_LOW_LEVEL 0 //ʱʱֵ߱͵ƽ +#define SPI_HIGH_LEVEL 1 //ʱʱָ߱ߵƽ + +#define SPI_CLKDIV_4 0 +#define SPI_CLKDIV_8 1 +#define SPI_CLKDIV_16 2 +#define SPI_CLKDIV_32 3 +#define SPI_CLKDIV_64 4 +#define SPI_CLKDIV_128 5 +#define SPI_CLKDIV_256 6 +#define SPI_CLKDIV_512 7 + + + +void SPI_Init(SPI_TypeDef * SPIx, SPI_InitStructure * initStruct); //SPIʼ +void SPI_Open(SPI_TypeDef * SPIx); //SPI򿪣շ +void SPI_Close(SPI_TypeDef * SPIx); //SPIرգֹշ + +uint32_t SPI_Read(SPI_TypeDef * SPIx); +void SPI_Write(SPI_TypeDef * SPIx, uint32_t data); +void SPI_WriteWithWait(SPI_TypeDef * SPIx, uint32_t data); +uint32_t SPI_ReadWrite(SPI_TypeDef * SPIx, uint32_t data); + +uint32_t SPI_IsRXEmpty(SPI_TypeDef * SPIx); //FIFOǷգԼSPI_Read() +uint32_t SPI_IsTXFull(SPI_TypeDef * SPIx); //FIFOǷԼSPI_Write() +uint32_t SPI_IsTXEmpty(SPI_TypeDef * SPIx); //FIFOǷ + + +void SPI_INTRXHalfFullEn(SPI_TypeDef * SPIx); +void SPI_INTRXHalfFullDis(SPI_TypeDef * SPIx); +void SPI_INTRXHalfFullClr(SPI_TypeDef * SPIx); +uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef * SPIx); +void SPI_INTRXFullEn(SPI_TypeDef * SPIx); +void SPI_INTRXFullDis(SPI_TypeDef * SPIx); +void SPI_INTRXFullClr(SPI_TypeDef * SPIx); +uint32_t SPI_INTRXFullStat(SPI_TypeDef * SPIx); +void SPI_INTRXOverflowEn(SPI_TypeDef * SPIx); +void SPI_INTRXOverflowDis(SPI_TypeDef * SPIx); +void SPI_INTRXOverflowClr(SPI_TypeDef * SPIx); +uint32_t SPI_INTRXOverflowStat(SPI_TypeDef * SPIx); + +void SPI_INTTXHalfFullEn(SPI_TypeDef * SPIx); +void SPI_INTTXHalfFullDis(SPI_TypeDef * SPIx); +void SPI_INTTXHalfFullClr(SPI_TypeDef * SPIx); +uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef * SPIx); +void SPI_INTTXEmptyEn(SPI_TypeDef * SPIx); +void SPI_INTTXEmptyDis(SPI_TypeDef * SPIx); +void SPI_INTTXEmptyClr(SPI_TypeDef * SPIx); +uint32_t SPI_INTTXEmptyStat(SPI_TypeDef * SPIx); +void SPI_INTTXCompleteEn(SPI_TypeDef * SPIx); +void SPI_INTTXCompleteDis(SPI_TypeDef * SPIx); +void SPI_INTTXCompleteClr(SPI_TypeDef * SPIx); +uint32_t SPI_INTTXCompleteStat(SPI_TypeDef * SPIx); + +void SPI_INTTXWordCompleteEn(SPI_TypeDef * SPIx); +void SPI_INTTXWordCompleteDis(SPI_TypeDef * SPIx); +void SPI_INTTXWordCompleteClr(SPI_TypeDef * SPIx); +uint32_t SPI_INTTXWordCompleteStat(SPI_TypeDef * SPIx); + + +#endif //__SWM320_SPI_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sram.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sram.c new file mode 100644 index 0000000000000000000000000000000000000000..d1f421aabaf969e68ab890a279d1fb7ee7411bea --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sram.c @@ -0,0 +1,53 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_sram.c +* ˵: SWM320ƬSRAM +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_sram.h" + + +/****************************************************************************************************************************************** +* : SRAM_Init() +* ˵: SRAMʼ +* : SRAM_InitStructure * initStruct SRAM 趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void SRAM_Init(SRAM_InitStructure * initStruct) +{ + uint32_t i; + + // SRAMǰҪˢSDRAM + do { + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + while(SDRAMC->REFDONE == 0); + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); + + for(i = 0; i < 1000; i++) __NOP(); + SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); + } while(0); + + SYS->CLKEN |= (1 << SYS_CLKEN_RAMC_Pos); + for(i = 0; i < 10; i++) __NOP(); + + SRAMC->CR = (initStruct->ClkDiv << SRAMC_CR_RWTIME_Pos) | + (initStruct->DataWidth << SRAMC_CR_BYTEIF_Pos) | + (0 << SRAMC_CR_HBLBDIS_Pos); // ʹֽڡַ +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sram.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sram.h new file mode 100644 index 0000000000000000000000000000000000000000..2ef71b24baae61b47e7e4ff5ac9fdfcb5d3ee36b --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sram.h @@ -0,0 +1,31 @@ +#ifndef __SWM320_SRAM_H__ +#define __SWM320_SRAM_H__ + +typedef struct { + uint8_t ClkDiv; //SRAM_CLKDIV_5...SRAM_CLKDIV_16SRAMоƬܵƵѡʷƵ + uint8_t DataWidth; //SRAM_DATAWIDTH_8SRAM_DATAWIDTH_16 +} SRAM_InitStructure; + + +#define SRAM_CLKDIV_4 3 +#define SRAM_CLKDIV_5 4 +#define SRAM_CLKDIV_6 5 +#define SRAM_CLKDIV_7 6 +#define SRAM_CLKDIV_8 7 +#define SRAM_CLKDIV_9 8 +#define SRAM_CLKDIV_10 9 +#define SRAM_CLKDIV_11 10 +#define SRAM_CLKDIV_12 11 +#define SRAM_CLKDIV_13 12 +#define SRAM_CLKDIV_14 13 +#define SRAM_CLKDIV_15 14 +#define SRAM_CLKDIV_16 15 + +#define SRAM_DATAWIDTH_8 1 +#define SRAM_DATAWIDTH_16 0 + + +void SRAM_Init(SRAM_InitStructure * initStruct); + + +#endif //__SWM320_SRAM_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_timr.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_timr.c new file mode 100644 index 0000000000000000000000000000000000000000..d4cbe03238c5230dcb03db850d92571a6eccc131 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_timr.c @@ -0,0 +1,436 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_timr.c +* ˵: SWM320Ƭļ/ʱ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_timr.h" + + +/****************************************************************************************************************************************** +* : TIMR_Init() +* ˵: TIMRʱ/ʼ +* : TIMR_TypeDef * TIMRx ָҪõĶʱЧֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* uint32_t mode TIMR_MODE_TIMER ʱģʽ TIMR_MODE_COUNTER ģʽ +* uint32_t period ʱ/ +* uint32_t int_en жʹ +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Init(TIMR_TypeDef * TIMRx, uint32_t mode, uint32_t period, uint32_t int_en) +{ + SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos); + + TIMR_Stop(TIMRx); //һЩؼĴֻڶʱֹͣʱ + + TIMRx->CTRL &= ~TIMR_CTRL_CLKSRC_Msk; + TIMRx->CTRL |= mode << TIMR_CTRL_CLKSRC_Pos; + + TIMRx->LDVAL = period; + + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IF = (1 << TIMRG_IF_TIMR0_Pos); //ʹжǰжϱ־ + TIMRG->IE &= ~TIMRG_IE_TIMR0_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR0_Pos); + + if(int_en) NVIC_EnableIRQ(TIMR0_IRQn); + break; + + case ((uint32_t)TIMR1): + TIMRG->IF = (1 << TIMRG_IF_TIMR1_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR1_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR1_Pos); + + if(int_en) NVIC_EnableIRQ(TIMR1_IRQn); + break; + + case ((uint32_t)TIMR2): + TIMRG->IF = (1 << TIMRG_IF_TIMR2_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR2_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR2_Pos); + + if(int_en) NVIC_EnableIRQ(TIMR2_IRQn); + break; + + case ((uint32_t)TIMR3): + TIMRG->IF = (1 << TIMRG_IF_TIMR3_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR3_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR3_Pos); + + if(int_en) NVIC_EnableIRQ(TIMR3_IRQn); + break; + + case ((uint32_t)TIMR4): + TIMRG->IF = (1 << TIMRG_IF_TIMR4_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR4_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR4_Pos); + + if(int_en) NVIC_EnableIRQ(TIMR4_IRQn); + break; + + case ((uint32_t)TIMR5): + TIMRG->IF = (1 << TIMRG_IF_TIMR5_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR5_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR5_Pos); + + if(int_en) NVIC_EnableIRQ(TIMR5_IRQn); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_Start() +* ˵: ʱӳʼֵʼʱ/ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Start(TIMR_TypeDef * TIMRx) +{ + TIMRx->CTRL |= TIMR_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* : TIMR_Stop() +* ˵: ֹͣʱ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Stop(TIMR_TypeDef * TIMRx) +{ + TIMRx->CTRL &= ~TIMR_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* : TIMR_Halt() +* ˵: ͣʱֲֵ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Halt(TIMR_TypeDef * TIMRx) +{ + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_Resume() +* ˵: ָʱͣ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Resume(TIMR_TypeDef * TIMRx) +{ + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_SetPeriod() +* ˵: öʱ/ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* uint32_t period ʱ/ +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_SetPeriod(TIMR_TypeDef * TIMRx, uint32_t period) +{ + TIMRx->LDVAL = period; +} + +/****************************************************************************************************************************************** +* : TIMR_GetPeriod() +* ˵: ȡʱ/ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : uint32_t ǰʱ/ +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_GetPeriod(TIMR_TypeDef * TIMRx) +{ + return TIMRx->LDVAL; +} + +/****************************************************************************************************************************************** +* : TIMR_GetCurValue() +* ˵: ȡǰֵ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : uint32_t ǰֵ +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_GetCurValue(TIMR_TypeDef * TIMRx) +{ + return TIMRx->CVAL; +} + +/****************************************************************************************************************************************** +* : TIMR_INTEn() +* ˵: ʹж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_INTEn(TIMR_TypeDef * TIMRx) +{ + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR0_Pos); + NVIC_EnableIRQ(TIMR0_IRQn); + break; + + case ((uint32_t)TIMR1): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR1_Pos); + NVIC_EnableIRQ(TIMR1_IRQn); + break; + + case ((uint32_t)TIMR2): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR2_Pos); + NVIC_EnableIRQ(TIMR2_IRQn); + break; + + case ((uint32_t)TIMR3): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR3_Pos); + NVIC_EnableIRQ(TIMR3_IRQn); + break; + + case ((uint32_t)TIMR4): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR4_Pos); + NVIC_EnableIRQ(TIMR4_IRQn); + break; + + case ((uint32_t)TIMR5): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR5_Pos); + NVIC_EnableIRQ(TIMR5_IRQn); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_INTDis() +* ˵: ж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_INTDis(TIMR_TypeDef * TIMRx) +{ + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_INTClr() +* ˵: жϱ־ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_INTClr(TIMR_TypeDef * TIMRx) +{ + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_INTStat() +* ˵: ȡж״̬ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : uint32_t 0 TIMRxδж 1 TIMRxж +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_INTStat(TIMR_TypeDef * TIMRx) +{ + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + return (TIMRG->IF & TIMRG_IF_TIMR0_Msk) ? 1 : 0; + + case ((uint32_t)TIMR1): + return (TIMRG->IF & TIMRG_IF_TIMR1_Msk) ? 1 : 0; + + case ((uint32_t)TIMR2): + return (TIMRG->IF & TIMRG_IF_TIMR2_Msk) ? 1 : 0; + + case ((uint32_t)TIMR3): + return (TIMRG->IF & TIMRG_IF_TIMR3_Msk) ? 1 : 0; + + case ((uint32_t)TIMR4): + return (TIMRG->IF & TIMRG_IF_TIMR4_Msk) ? 1 : 0; + + case ((uint32_t)TIMR5): + return (TIMRG->IF & TIMRG_IF_TIMR5_Msk) ? 1 : 0; + } + + return 0; +} + + +/****************************************************************************************************************************************** +* : Pulse_Init() +* ˵: ܳʼ +* : uint32_t pulse PULSE_LOW PULSE_HIGH +* uint32_t int_en Ƿʹж +* : +* ע: +******************************************************************************************************************************************/ +void Pulse_Init(uint32_t pulse, uint32_t int_en) +{ + SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos); + + TIMRG->PCTRL = (0 << TIMRG_PCTRL_CLKSRC_Pos) | // ϵͳʱΪʱԴ + (pulse << TIMRG_PCTRL_HIGH_Pos) | + (0 << TIMRG_PCTRL_EN_Pos); + + TIMRG->IE |= (1 << TIMRG_IE_PULSE_Pos); //ʹܲܲѯжϱ־ + + if(int_en) NVIC_EnableIRQ(PULSE_IRQn); +} + +/****************************************************************************************************************************************** +* : Pulse_Start() +* ˵: Զرղ +* : +* : +* ע: +******************************************************************************************************************************************/ +void Pulse_Start(void) +{ + TIMRG->PCTRL |= (1 << TIMRG_PCTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : Pulse_Done() +* ˵: Ƿ +* : +* : uint32_t 1 0 δ +* ע: +******************************************************************************************************************************************/ +uint32_t Pulse_Done(void) +{ + if(TIMRG->IF & TIMRG_IF_PULSE_Msk) + { + TIMRG->IF = TIMRG_IF_PULSE_Msk; // жϱ־ + + return 1; + } + else + { + return 0; + } +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_timr.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_timr.h new file mode 100644 index 0000000000000000000000000000000000000000..bd1aa2618d6a3b893be9994401bbd0fb4fba9670 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_timr.h @@ -0,0 +1,32 @@ +#ifndef __SWM320_TIMR_H__ +#define __SWM320_TIMR_H__ + +#define TIMR_MODE_TIMER 0 +#define TIMR_MODE_COUNTER 1 + +void TIMR_Init(TIMR_TypeDef * TIMRx, uint32_t mode, uint32_t period, uint32_t int_en); //ʱ/ʼ +void TIMR_Start(TIMR_TypeDef * TIMRx); //ʱӳʼֵʼʱ/ +void TIMR_Stop(TIMR_TypeDef * TIMRx); //ֹͣʱ +void TIMR_Halt(TIMR_TypeDef * TIMRx); //ͣʱֲֵ +void TIMR_Resume(TIMR_TypeDef * TIMRx); //ָʱͣ + +void TIMR_SetPeriod(TIMR_TypeDef * TIMRx, uint32_t period); //öʱ/ +uint32_t TIMR_GetPeriod(TIMR_TypeDef * TIMRx); //ȡʱ/ +uint32_t TIMR_GetCurValue(TIMR_TypeDef * TIMRx); //ȡǰֵ + +void TIMR_INTEn(TIMR_TypeDef * TIMRx); //ʹж +void TIMR_INTDis(TIMR_TypeDef * TIMRx); //ж +void TIMR_INTClr(TIMR_TypeDef * TIMRx); //жϱ־ +uint32_t TIMR_INTStat(TIMR_TypeDef * TIMRx); //ȡж״̬ + + + +#define PULSE_LOW 0 +#define PULSE_HIGH 1 + +void Pulse_Init(uint32_t pulse, uint32_t int_en); +void Pulse_Start(void); +uint32_t Pulse_Done(void); + + +#endif //__SWM320_TIMR_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_uart.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..6b3f046c75c246f70690a8694516370e2c6e4687 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_uart.c @@ -0,0 +1,553 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_uart.c +* ˵: SWM320ƬUARTڹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: ûбдLINصĺ +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_uart.h" + + +/****************************************************************************************************************************************** +* : UART_Init() +* ˵: UARTڳʼ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* UART_InitStructure * initStruct UART趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void UART_Init(UART_TypeDef * UARTx, UART_InitStructure * initStruct) +{ + switch((uint32_t)UARTx) + { + case ((uint32_t)UART0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART0_Pos); + break; + + case ((uint32_t)UART1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART1_Pos); + break; + + case ((uint32_t)UART2): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART2_Pos); + break; + + case ((uint32_t)UART3): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART3_Pos); + break; + } + + UART_Close(UARTx); //һЩؼĴֻڴڹرʱ + + UARTx->CTRL |= (0x01 << UART_CTRL_BAUDEN_Pos); + UARTx->BAUD &= ~UART_BAUD_BAUD_Msk; + UARTx->BAUD |= ((SystemCoreClock/16/initStruct->Baudrate - 1) << UART_BAUD_BAUD_Pos); + + UARTx->CTRL &= ~(UART_CTRL_DATA9b_Msk | UART_CTRL_PARITY_Msk | UART_CTRL_STOP2b_Msk); + UARTx->CTRL |= (initStruct->DataBits << UART_CTRL_DATA9b_Pos) | + (initStruct->Parity << UART_CTRL_PARITY_Pos) | + (initStruct->StopBits << UART_CTRL_STOP2b_Pos); + + /* SWM320У RXLVL >= RXTHR ʱжϣRXTHRΪ0Ļδյʱͻһֱжϣ + оƬУ RXLVL > RXTHR ʱжϣΪSWM320RXTHRΪ0⣬ͳһ⺯APIｫRXTHRֵһ + */ + switch((uint32_t)UARTx) // λ NVIC ĴֶĴ RXTHR ʱᵼһֱ ISR + { + case ((uint32_t)UART0): NVIC_DisableIRQ(UART0_IRQn); break; + case ((uint32_t)UART1): NVIC_DisableIRQ(UART1_IRQn); break; + case ((uint32_t)UART2): NVIC_DisableIRQ(UART2_IRQn); break; + case ((uint32_t)UART3): NVIC_DisableIRQ(UART3_IRQn); break; + } + UARTx->FIFO &= ~(UART_FIFO_RXTHR_Msk | UART_FIFO_TXTHR_Msk); + UARTx->FIFO |= ((initStruct->RXThreshold + 1) << UART_FIFO_RXTHR_Pos) | + (initStruct->TXThreshold << UART_FIFO_TXTHR_Pos); + + UARTx->CTRL &= ~UART_CTRL_TOTIME_Msk; + UARTx->CTRL |= (initStruct->TimeoutTime << UART_CTRL_TOTIME_Pos); + + UARTx->CTRL &= ~(UART_CTRL_RXIE_Msk | UART_CTRL_TXIE_Msk | UART_CTRL_TOIE_Msk); + UARTx->CTRL |= (initStruct->RXThresholdIEn << UART_CTRL_RXIE_Pos) | + (initStruct->TXThresholdIEn << UART_CTRL_TXIE_Pos) | + (initStruct->TimeoutIEn << UART_CTRL_TOIE_Pos); + + switch((uint32_t)UARTx) + { + case ((uint32_t)UART0): + if(initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART0_IRQn); + } + else + { + NVIC_DisableIRQ(UART0_IRQn); + } + break; + + case ((uint32_t)UART1): + if(initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART1_IRQn); + } + else + { + NVIC_DisableIRQ(UART1_IRQn); + } + break; + + case ((uint32_t)UART2): + if(initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART2_IRQn); + } + else + { + NVIC_DisableIRQ(UART2_IRQn); + } + break; + + case ((uint32_t)UART3): + if(initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART3_IRQn); + } + else + { + NVIC_DisableIRQ(UART3_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : UART_Open() +* ˵: UARTڴ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_Open(UART_TypeDef * UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : UART_Close() +* ˵: UARTڹر +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_Close(UART_TypeDef * UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : UART_WriteByte() +* ˵: һֽ +* : UART_TypeDef * UARTx ָҪõUARTڣȡֵUART0UART1UART2UART3UART4 +* uint32_t data Ҫ͵ֽ +* : +* ע: +******************************************************************************************************************************************/ +void UART_WriteByte(UART_TypeDef * UARTx, uint32_t data) +{ + UARTx->DATA = data; +} + +/****************************************************************************************************************************************** +* : UART_ReadByte() +* ˵: ȡһֽݣָǷValid +* : UART_TypeDef * UARTx ָҪõUARTڣȡֵUART0UART1UART2UART3UART4 +* uint32_t * data յ +* : uint32_t 0 ޴ UART_ERR_PARITY żУ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_ReadByte(UART_TypeDef * UARTx, uint32_t * data) +{ + uint32_t reg = UARTx->DATA; + + *data = (reg & UART_DATA_DATA_Msk); + + if(reg & UART_DATA_PAERR_Msk) return UART_ERR_PARITY; + + return 0; +} + +/****************************************************************************************************************************************** +* : UART_IsTXBusy() +* ˵: UARTǷڷ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 UARTڷ 0 ѷ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_IsTXBusy(UART_TypeDef * UARTx) +{ + return (UARTx->CTRL & UART_CTRL_TXIDLE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : UART_IsRXFIFOEmpty() +* ˵: FIFOǷΪգ˵ݿԶȡ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_IsRXFIFOEmpty(UART_TypeDef * UARTx) +{ + return (UARTx->CTRL & UART_CTRL_RXNE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : UART_IsTXFIFOFull() +* ˵: FIFOǷΪԼд +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 FIFO 0 FIFO +* ע: +******************************************************************************************************************************************/ +uint32_t UART_IsTXFIFOFull(UART_TypeDef * UARTx) +{ + return (UARTx->CTRL & UART_CTRL_TXFF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_SetBaudrate() +* ˵: ò +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t baudrate ҪõIJ +* : +* ע: ҪڴڹʱIJʣʹô˺ǰȵUART_Close()رմ +******************************************************************************************************************************************/ +void UART_SetBaudrate(UART_TypeDef * UARTx, uint32_t baudrate) +{ + UARTx->BAUD &= ~UART_BAUD_BAUD_Msk; + UARTx->BAUD |= ((SystemCoreClock/16/baudrate - 1) << UART_BAUD_BAUD_Pos); +} + +/****************************************************************************************************************************************** +* : UART_GetBaudrate() +* ˵: ѯ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t ǰ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_GetBaudrate(UART_TypeDef * UARTx) +{ + return SystemCoreClock/16/(((UARTx->BAUD & UART_BAUD_BAUD_Msk) >> UART_BAUD_BAUD_Pos) + 1); +} + +/****************************************************************************************************************************************** +* : UART_CTSConfig() +* ˵: UART CTS +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t enable 1 ʹCTS 0 ֹCTS +* uint32_t polarity 0 CTSΪͱʾԷ 1 CTSΪ߱ʾԷ +* : +* ע: +******************************************************************************************************************************************/ +void UART_CTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity) +{ + UARTx->CTSCR &= ~(UART_CTSCR_EN_Msk | UART_CTSCR_POL_Msk); + UARTx->CTSCR |= (enable << UART_CTSCR_EN_Pos) | + (polarity << UART_CTSCR_POL_Pos); +} + +/****************************************************************************************************************************************** +* : UART_CTSLineState() +* ˵: UART CTSߵǰ״̬ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 0 CTSߵǰΪ͵ƽ 1 CTSߵǰΪߵƽ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_CTSLineState(UART_TypeDef * UARTx) +{ + return (UARTx->CTSCR & UART_CTSCR_STAT_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_RTSConfig() +* ˵: UART RTS +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t enable 1 ʹRTS 0 ֹRTS +* uint32_t polarity 0 RTSͱʾԽ 1 RTS߱ʾԽ +* uint32_t threshold RTSصĴֵȡֵUART_RTS_1BYTEUART_RTS_2BYTEUART_RTS_4BYTEUART_RTS_6BYTE +* : +* ע: +******************************************************************************************************************************************/ +void UART_RTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold) +{ + UARTx->RTSCR &= ~(UART_RTSCR_EN_Msk | UART_RTSCR_POL_Msk | UART_RTSCR_THR_Msk); + UARTx->RTSCR |= (enable << UART_RTSCR_EN_Pos) | + (polarity << UART_RTSCR_POL_Pos) | + (threshold << UART_RTSCR_THR_Pos); +} + +/****************************************************************************************************************************************** +* : UART_RTSLineState() +* ˵: UART RTSߵǰ״̬ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 0 RTSߵǰΪ͵ƽ 1 RTSߵǰΪߵƽ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_RTSLineState(UART_TypeDef * UARTx) +{ + return (UARTx->RTSCR & UART_RTSCR_STAT_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_LINConfig() +* ˵: UART LIN +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t detectedIEn ⵽Breakжʹ +* uint32_t generatedIEn Breakжʹ +* : +* ע: +******************************************************************************************************************************************/ +void UART_LINConfig(UART_TypeDef * UARTx, uint32_t detectedIEn, uint32_t generatedIEn) +{ + UARTx->LINCR &= ~(UART_LINCR_BRKDETIE_Msk | UART_LINCR_GENBRKIE_Msk); + UARTx->LINCR |= (detectedIEn << UART_LINCR_BRKDETIE_Pos) | + (generatedIEn << UART_LINCR_GENBRKIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_LINGenerate() +* ˵: UART LIN/Break +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_LINGenerate(UART_TypeDef * UARTx) +{ + UARTx->LINCR |= (1 << UART_LINCR_GENBRK_Pos); +} + +/****************************************************************************************************************************************** +* : UART_LINIsDetected() +* ˵: UART LINǷ⵽Break +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 ⵽LIN Break 0 δ⵽LIN Break +* ע: +******************************************************************************************************************************************/ +uint32_t UART_LINIsDetected(UART_TypeDef * UARTx) +{ + return (UARTx->LINCR & UART_LINCR_BRKDETIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_LINIsGenerated() +* ˵: UART LIN BreakǷ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 LIN Break 0 LIN Breakδ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_LINIsGenerated(UART_TypeDef * UARTx) +{ + return (UARTx->LINCR & UART_LINCR_GENBRKIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_ABRStart() +* ˵: UART Զʼ⿪ʼ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t detectChar Զ⡢㲨ʵļַ +* 8λʱȡֵ0xFF0xFE0xF80x80ֱʾͷ뷢0xFF0xFE0xF80x80 +* 9λʱȡֵ0x1FF0x1FE0x1F80x180ֱʾͷ뷢0x1FF0x1FE0x1F80x180 +* : +* ע: ԶʼʱܿżУ +******************************************************************************************************************************************/ +void UART_ABRStart(UART_TypeDef * UARTx, uint32_t detectChar) +{ + uint32_t bits; + + if((detectChar == 0xFF) || (detectChar == 0x1FF)) bits = 0; + else if((detectChar == 0xFE) || (detectChar == 0x1FE)) bits = 1; + else if((detectChar == 0xF8) || (detectChar == 0x1F8)) bits = 2; + else if((detectChar == 0x80) || (detectChar == 0x180)) bits = 3; + else while(1); + + UARTx->BAUD &= ~(UART_BAUD_ABREN_Msk | UART_BAUD_ABRBIT_Msk); + UARTx->BAUD |= (1 << UART_BAUD_ABREN_Pos) | + (bits << UART_BAUD_ABRBIT_Pos); +} + +/****************************************************************************************************************************************** +* : UART_ABRIsDone() +* ˵: UART ԶǷ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 0 δ UART_ABR_RES_OK ɣҳɹ UART_ABR_RES_ERR ɣʧܡ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_ABRIsDone(UART_TypeDef * UARTx) +{ + if(UARTx->BAUD & UART_BAUD_ABREN_Msk) + { + return 0; + } + else if(UARTx->BAUD & UART_BAUD_ABRERR_Msk) + { + return UART_ABR_RES_ERR; + } + else + { + return UART_ABR_RES_OK; + } +} + +/****************************************************************************************************************************************** +* : UART_INTRXThresholdEn() +* ˵: RX FIFOݸ >= RXThresholdʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTRXThresholdEn(UART_TypeDef * UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_RXIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTRXThresholdDis() +* ˵: RX FIFOݸ >= RXThresholdʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTRXThresholdDis(UART_TypeDef * UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_RXIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTRXThresholdStat() +* ˵: ǷRX FIFOݸ >= RXThreshold +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 RX FIFOݸ >= RXThreshold 0 RX FIFOݸ < RXThreshold +* ע: RXIF = RXTHRF & RXIE +******************************************************************************************************************************************/ +uint32_t UART_INTRXThresholdStat(UART_TypeDef * UARTx) +{ + return (UARTx->BAUD & UART_BAUD_RXIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_INTTXThresholdEn() +* ˵: TX FIFOݸ <= TXThresholdʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTXThresholdEn(UART_TypeDef * UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_TXIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTXThresholdDis() +* ˵: TX FIFOݸ <= TXThresholdʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTXThresholdDis(UART_TypeDef * UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_TXIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTXThresholdStat() +* ˵: ǷTX FIFOݸ <= TXThreshold +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 TX FIFOݸ <= TXThreshold 0 TX FIFOݸ > TXThreshold +* ע: TXIF = TXTHRF & TXIE +******************************************************************************************************************************************/ +uint32_t UART_INTTXThresholdStat(UART_TypeDef * UARTx) +{ + return (UARTx->BAUD & UART_BAUD_TXIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_INTTimeoutEn() +* ˵: շʱʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTimeoutEn(UART_TypeDef * UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_TOIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTimeoutDis() +* ˵: շʱʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTimeoutDis(UART_TypeDef * UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_TOIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTimeoutStat() +* ˵: Ƿ˽ճʱ TimeoutTime/(Baudrate/10) ûRXϽյʱж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 ˽ճʱ 0 δճʱ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_INTTimeoutStat(UART_TypeDef * UARTx) +{ + return (UARTx->BAUD & UART_BAUD_TOIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_INTTXDoneEn() +* ˵: FIFOҷλĴжʹ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTXDoneEn(UART_TypeDef * UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_TXDOIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTXDoneDis() +* ˵: FIFOҷλĴжϽֹ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTXDoneDis(UART_TypeDef * UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_TXDOIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTXDoneStat() +* ˵: FIFOҷλĴж״̬ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 FIFOҷλĴ 0 FIFOλĴδ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_INTTXDoneStat(UART_TypeDef * UARTx) +{ + return (UARTx->BAUD & UART_BAUD_TXDOIF_Msk) ? 1 : 0; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_uart.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..1611744cb7a3116ceda08c0e28a614fb8cc13ced --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_uart.h @@ -0,0 +1,94 @@ +#ifndef __SWM320_UART_H__ +#define __SWM320_UART_H__ + +typedef struct { + uint32_t Baudrate; + + uint8_t DataBits; //λλȡֵUART_DATA_8BITUART_DATA_9BIT + + uint8_t Parity; //żУλȡֵUART_PARITY_NONEUART_PARITY_ODDUART_PARITY_EVENUART_PARITY_ONEUART_PARITY_ZERO + + uint8_t StopBits; //ֹͣλλȡֵUART_STOP_1BITUART_STOP_2BIT + + uint8_t RXThreshold; //ȡֵ0--7 + uint8_t RXThresholdIEn; //RX FIFOݸ > RXThresholdʱж + + uint8_t TXThreshold; //ȡֵ0--7 + uint8_t TXThresholdIEn; //TX FIFOݸ <= TXThresholdʱж + + uint8_t TimeoutTime; //ʱʱ = TimeoutTime/(Baudrate/10) + uint8_t TimeoutIEn; //ʱжϣRX FIFOǿգҳ TimeoutTime/(Baudrate/10) ûRXϽյʱж +} UART_InitStructure; + + +#define UART_DATA_8BIT 0 +#define UART_DATA_9BIT 1 + +#define UART_PARITY_NONE 0 +#define UART_PARITY_ODD 1 +#define UART_PARITY_EVEN 3 +#define UART_PARITY_ONE 5 +#define UART_PARITY_ZERO 7 + +#define UART_STOP_1BIT 0 +#define UART_STOP_2BIT 1 + +#define UART_RTS_1BYTE 0 +#define UART_RTS_2BYTE 1 +#define UART_RTS_4BYTE 2 +#define UART_RTS_6BYTE 3 + +#define UART_ABR_RES_OK 1 +#define UART_ABR_RES_ERR 2 + +#define UART_ERR_FRAME 1 +#define UART_ERR_PARITY 2 +#define UART_ERR_NOISE 3 + + +void UART_Init(UART_TypeDef * UARTx, UART_InitStructure * initStruct); //UARTڳʼ +void UART_Open(UART_TypeDef * UARTx); +void UART_Close(UART_TypeDef * UARTx); + +void UART_WriteByte(UART_TypeDef * UARTx, uint32_t data); //һֽ +uint32_t UART_ReadByte(UART_TypeDef * UARTx, uint32_t * data); //ȡһֽݣָǷValid + +uint32_t UART_IsTXBusy(UART_TypeDef * UARTx); +uint32_t UART_IsRXFIFOEmpty(UART_TypeDef * UARTx); //FIFOǷգԼUART_ReadByte() +uint32_t UART_IsTXFIFOFull(UART_TypeDef * UARTx); //FIFOǷԼUART_WriteByte() + + +void UART_SetBaudrate(UART_TypeDef * UARTx, uint32_t baudrate); //ò +uint32_t UART_GetBaudrate(UART_TypeDef * UARTx); //ȡǰʹõIJ + +void UART_CTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity); +uint32_t UART_CTSLineState(UART_TypeDef * UARTx); + +void UART_RTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold); +uint32_t UART_RTSLineState(UART_TypeDef * UARTx); + +void UART_LINConfig(UART_TypeDef * UARTx, uint32_t detectedIEn, uint32_t generatedIEn); +void UART_LINGenerate(UART_TypeDef * UARTx); +uint32_t UART_LINIsDetected(UART_TypeDef * UARTx); +uint32_t UART_LINIsGenerated(UART_TypeDef * UARTx); + +void UART_ABRStart(UART_TypeDef * UARTx, uint32_t detectChar); +uint32_t UART_ABRIsDone(UART_TypeDef * UARTx); + + +void UART_INTRXThresholdEn(UART_TypeDef * UARTx); +void UART_INTRXThresholdDis(UART_TypeDef * UARTx); +uint32_t UART_INTRXThresholdStat(UART_TypeDef * UARTx); +void UART_INTTXThresholdEn(UART_TypeDef * UARTx); +void UART_INTTXThresholdDis(UART_TypeDef * UARTx); +uint32_t UART_INTTXThresholdStat(UART_TypeDef * UARTx); +void UART_INTTimeoutEn(UART_TypeDef * UARTx); +void UART_INTTimeoutDis(UART_TypeDef * UARTx); +uint32_t UART_INTTimeoutStat(UART_TypeDef * UARTx); + +void UART_INTTXDoneEn(UART_TypeDef * UARTx); +void UART_INTTXDoneDis(UART_TypeDef * UARTx); +uint32_t UART_INTTXDoneStat(UART_TypeDef * UARTx); + + +#endif //__SWM320_UART_H__ diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..762e79b3ae30815d41a902abe1790cef01c995d5 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c @@ -0,0 +1,126 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_wdt.c +* ˵: SWM320ƬWDTŹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_wdt.h" + + +/****************************************************************************************************************************************** +* : WDT_Init() +* ˵: WDTŹʼ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* uint32_t peroid ȡֵ0--4294967295λΪƬϵͳʱ +* uint32_t mode WDT_MODE_RESET ʱλ WDT_MODE_INTERRUPT ʱж +* : +* ע: λʹʱжϲãΪڽʱоƬֱӸλˣ޷Ӧж +******************************************************************************************************************************************/ +void WDT_Init(WDT_TypeDef * WDTx, uint32_t peroid, uint32_t mode) +{ + SYS->CLKEN |= (0x01 << SYS_CLKEN_WDT_Pos); + + WDT_Stop(WDTx); //ǰȹر + + WDTx->LOAD = peroid; + + if(mode == WDT_MODE_RESET) + { + NVIC_DisableIRQ(WDT_IRQn); + + WDTx->CR |= (1 << WDT_CR_RSTEN_Pos); + } + else //mode == WDT_MODE_INTERRUPT + { + NVIC_EnableIRQ(WDT_IRQn); + + WDTx->CR &= ~(1 << WDT_CR_RSTEN_Pos); + } +} + +/****************************************************************************************************************************************** +* : WDT_Start() +* ˵: ָWDTʼʱ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_Start(WDT_TypeDef * WDTx) +{ + WDTx->CR |= (0x01 << WDT_CR_EN_Pos); +} + +/****************************************************************************************************************************************** +* : WDT_Stop() +* ˵: رָWDTֹͣʱ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_Stop(WDT_TypeDef * WDTx) +{ + WDTx->CR &= ~(0x01 << WDT_CR_EN_Pos); +} + +/****************************************************************************************************************************************** +* : WDT_Feed() +* ˵: ι´װֵʼʱ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_Feed(WDT_TypeDef * WDTx) +{ + WDTx->FEED = 0x55; +} + +/****************************************************************************************************************************************** +* : WDT_GetValue() +* ˵: ȡָŹʱĵǰʱֵ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : int32_t Źǰֵ +* ע: +******************************************************************************************************************************************/ +int32_t WDT_GetValue(WDT_TypeDef * WDTx) +{ + return WDTx->VALUE; +} + +/****************************************************************************************************************************************** +* : WDT_INTClr() +* ˵: жϱ־ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_INTClr(WDT_TypeDef * WDTx) +{ + WDTx->IF = 1; +} + +/****************************************************************************************************************************************** +* : WDT_INTStat() +* ˵: ж״̬ѯ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : int32_t 1 ж 0 δж +* ע: +******************************************************************************************************************************************/ +uint32_t WDT_INTStat(WDT_TypeDef * WDTx) +{ + return WDTx->IF; +} diff --git a/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..1d056ba2968da0fe0a1ad2fdc6e887350fdb4ba7 --- /dev/null +++ b/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h @@ -0,0 +1,19 @@ +#ifndef __SWM320_WDT_H__ +#define __SWM320_WDT_H__ + +#define WDT_MODE_RESET 0 +#define WDT_MODE_INTERRUPT 1 + +void WDT_Init(WDT_TypeDef * WDTx, uint32_t peroid, uint32_t mode); //WDTŹʼ +void WDT_Start(WDT_TypeDef * WDTx); //ָWDTʼʱ +void WDT_Stop(WDT_TypeDef * WDTx); //رָWDTֹͣʱ + +void WDT_Feed(WDT_TypeDef * WDTx); //ι´װֵʼʱ + +int32_t WDT_GetValue(WDT_TypeDef * WDTx); //ȡָŹʱĵǰʱֵ + + +void WDT_INTClr(WDT_TypeDef * WDTx); //жϱ־ +uint32_t WDT_INTStat(WDT_TypeDef * WDTx); //ж״̬ѯ + +#endif //__SWM320_WDT_H__ diff --git a/bsp/swm320/project.ewd b/bsp/swm320/project.ewd new file mode 100644 index 0000000000000000000000000000000000000000..e94c83ed06b9e53d88b513c0a40c0bc99c7bcb8b --- /dev/null +++ b/bsp/swm320/project.ewd @@ -0,0 +1,2834 @@ + + + 3 + + rt-thread + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\IARProbe\IarProbePlugin.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\IARProbe\IarProbePlugin.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/swm320/project.ewp b/bsp/swm320/project.ewp new file mode 100644 index 0000000000000000000000000000000000000000..517effb86bcce6afa14bb3f872711555954c435f --- /dev/null +++ b/bsp/swm320/project.ewp @@ -0,0 +1,2231 @@ + + 3 + + rtthread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ $PROJ_DIR$\applications\main.c + + + $PROJ_DIR$\applications\mnt.c + + + + Drivers + + $PROJ_DIR$\drivers\board.c + + + $PROJ_DIR$\drivers\drv_uart.c + + + + CPU + + $PROJ_DIR$\libcpu\port.c + + + + Libraries + + $PROJ_DIR$\Libraries\CMSIS\startup_xxx.s + + + + cpu + + $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m4\cpuport.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m4\context_iar.S + + + + DeviceDrivers + + $PROJ_DIR$\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\workqueue.c + + + + finsh + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\components\finsh\symbol.c + + + $PROJ_DIR$\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\components\finsh\msh_cmd.c + + + $PROJ_DIR$\..\..\components\finsh\msh_file.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_token.c + + + diff --git a/bsp/swm320/project.eww b/bsp/swm320/project.eww new file mode 100644 index 0000000000000000000000000000000000000000..faa93f37cdf824efd53c15b77e75dc1f03727d9a --- /dev/null +++ b/bsp/swm320/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/swm320/project.uvopt b/bsp/swm320/project.uvopt new file mode 100644 index 0000000000000000000000000000000000000000..068ac9af693377f268c716237453ba45287c9e52 --- /dev/null +++ b/bsp/swm320/project.uvopt @@ -0,0 +1,162 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/swm320/project.uvoptx b/bsp/swm320/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..37db9be0cd64026d80eec8deb847369e51ef120a --- /dev/null +++ b/bsp/swm320/project.uvoptx @@ -0,0 +1,1093 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0SWM320xE -FL080000 -FS00 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM) + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 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+ + + 8 + 65 + 1 + 0 + 0 + 0 + libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c + SWM320_sdram.c + 0 + 0 + + + 8 + 66 + 1 + 0 + 0 + 0 + libraries\SWM320_StdPeriph_Driver\SWM320_spi.c + SWM320_spi.c + 0 + 0 + + + 8 + 67 + 1 + 0 + 0 + 0 + libraries\SWM320_StdPeriph_Driver\SWM320_sram.c + SWM320_sram.c + 0 + 0 + + + 8 + 68 + 1 + 0 + 0 + 0 + libraries\SWM320_StdPeriph_Driver\SWM320_timr.c + SWM320_timr.c + 0 + 0 + + + 8 + 69 + 1 + 0 + 0 + 0 + libraries\SWM320_StdPeriph_Driver\SWM320_uart.c + SWM320_uart.c + 0 + 0 + + + 8 + 70 + 1 + 0 + 0 + 0 + libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c + SWM320_wdt.c + 0 + 0 + + + 8 + 71 + 2 + 0 + 0 + 0 + libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s + startup_SWM320.s + 0 + 0 + + + + diff --git a/bsp/swm320/project.uvproj b/bsp/swm320/project.uvproj new file mode 100644 index 0000000000000000000000000000000000000000..66eddd2602efd9d2c1948d91fa29e84ecac0e48b --- /dev/null +++ b/bsp/swm320/project.uvproj @@ -0,0 +1,786 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rtthread + 0x4 + ARM-ADS + + + STM32F407ZG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6105 + stm32f4xx.h + + + + + + + -DSTM32F40_41xxx + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 0 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + + + .;..\..\include;applications;drivers;libcpu;Libraries\CMSIS\CoreSupport;Libraries\CMSIS\DeviceSupport;Libraries\XXX_StdPeriph_Driver;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\src\clock.c + + + + + components.c + 1 + ..\..\src\components.c + + + + + cpu.c + 1 + ..\..\src\cpu.c + + + + + device.c + 1 + ..\..\src\device.c + + + + + idle.c + 1 + ..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + object.c + 1 + ..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\src\signal.c + + + + + thread.c + 1 + ..\..\src\thread.c + + + + + timer.c + 1 + ..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + mnt.c + 1 + applications\mnt.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + CPU + + + port.c + 1 + libcpu\port.c + + + + + Libraries + + + startup_xxx.s + 2 + Libraries\CMSIS\startup_xxx.s + + + + + cpu + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + + + symbol.c + 1 + ..\..\components\finsh\symbol.c + + + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + + + diff --git a/bsp/swm320/project.uvprojx b/bsp/swm320/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..f99301d47ff566984a3384b18898feb9596c6267 --- /dev/null +++ b/bsp/swm320/project.uvprojx @@ -0,0 +1,788 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + SWM320xE + Synwit + Synwit.SWM32_DFP.1.11.3 + http://www.synwit.com/pack + IRAM(0x20000000,0x20000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)) + 0 + $$Device:SWM320xE$CSL\SWM320\CMSIS\DeviceSupport\SWM320.h + + + + + + + + + + $$Device:SWM320xE$SVD\SWM320.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + applications;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;libraries\CMSIS\CoreSupport;libraries\CMSIS\DeviceSupport;libraries\SWM320_StdPeriph_Driver + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + Kernel + + + clock.c + 1 + ..\..\src\clock.c + + + components.c + 1 + ..\..\src\components.c + + + device.c + 1 + ..\..\src\device.c + + + idle.c + 1 + ..\..\src\idle.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + irq.c + 1 + ..\..\src\irq.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + memheap.c + 1 + ..\..\src\memheap.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + object.c + 1 + ..\..\src\object.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + thread.c + 1 + ..\..\src\thread.c + + + timer.c + 1 + ..\..\src\timer.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + + + Libraries + + + system_SWM320.c + 1 + libraries\CMSIS\DeviceSupport\system_SWM320.c + + + SWM320_adc.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_adc.c + + + SWM320_can.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_can.c + + + SWM320_crc.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_crc.c + + + SWM320_dma.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_dma.c + + + SWM320_exti.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_exti.c + + + SWM320_flash.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_flash.c + + + SWM320_gpio.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c + + + SWM320_i2c.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c + + + SWM320_lcd.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c + + + SWM320_norflash.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_norflash.c + + + SWM320_port.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_port.c + + + SWM320_pwm.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c + + + SWM320_rtc.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c + + + SWM320_sdio.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c + + + SWM320_sdram.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c + + + SWM320_spi.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_spi.c + + + SWM320_sram.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_sram.c + + + SWM320_timr.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_timr.c + + + SWM320_uart.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_uart.c + + + SWM320_wdt.c + 1 + libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c + + + startup_SWM320.s + 2 + libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s + + + + + + + + + + + + + + diff --git a/bsp/swm320/rtconfig.h b/bsp/swm320/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..91d579f1b0671d0284fbea6690541b99af73753e --- /dev/null +++ b/bsp/swm320/rtconfig.h @@ -0,0 +1,174 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40003 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* games: games run on RT-Thread console */ + + +/* Hardware Drivers Config */ + +#define SOC_SWM320 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_GPIO + +/* Onboard Peripheral Drivers */ + + +/* Offboard Peripheral Drivers */ + + +#endif diff --git a/bsp/swm320/rtconfig.py b/bsp/swm320/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..f90b4903920ae5411a3d1d9fa835958fa040e65f --- /dev/null +++ b/bsp/swm320/rtconfig.py @@ -0,0 +1,135 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# EXEC_PATH is the compiler execute path, for example, GCC, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + TARGET_EXT = 'elf' + DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -g -Wall' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + CXXFLAGS = CFLAGS + LFLAGS = ' --config "drivers/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' diff --git a/bsp/swm320/template.ewp b/bsp/swm320/template.ewp new file mode 100644 index 0000000000000000000000000000000000000000..7f8d4d422098cea3329f1b25ca0edcdc2d92a2a5 --- /dev/null +++ b/bsp/swm320/template.ewp @@ -0,0 +1,2031 @@ + + + 3 + + rtthread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/swm320/template.eww b/bsp/swm320/template.eww new file mode 100644 index 0000000000000000000000000000000000000000..c62178f07a5e15c70d24add2b6f369e079d7a335 --- /dev/null +++ b/bsp/swm320/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/swm320/template.uvopt b/bsp/swm320/template.uvopt new file mode 100644 index 0000000000000000000000000000000000000000..068ac9af693377f268c716237453ba45287c9e52 --- /dev/null +++ b/bsp/swm320/template.uvopt @@ -0,0 +1,162 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/swm320/template.uvoptx b/bsp/swm320/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..920c51f4437c21c0c6dfcf2c679f2cc26750275e --- /dev/null +++ b/bsp/swm320/template.uvoptx @@ -0,0 +1,185 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0SWM320xE -FL080000 -FS00 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM) + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/swm320/template.uvproj b/bsp/swm320/template.uvproj new file mode 100644 index 0000000000000000000000000000000000000000..3312f50fca3407abc03b8dd8063c24ac9945273d --- /dev/null +++ b/bsp/swm320/template.uvproj @@ -0,0 +1,407 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + + + STM32F407ZG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6105 + stm32f4xx.h + + + + + + + -DSTM32F40_41xxx + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 0 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + + diff --git a/bsp/swm320/template.uvprojx b/bsp/swm320/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..68f1afd63e35e5da5f4b554768ff19408264ae64 --- /dev/null +++ b/bsp/swm320/template.uvprojx @@ -0,0 +1,395 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + SWM320xE + Synwit + Synwit.SWM32_DFP.1.11.2 + http://www.synwit.com/pack + IRAM(0x20000000,0x20000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)) + 0 + $$Device:SWM320xE$CSL\SWM320\CMSIS\DeviceSupport\SWM320.h + + + + + + + + + + $$Device:SWM320xE$SVD\SWM320.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + +