From 7b332f6e765fd00086f76582f62a386c550901ff Mon Sep 17 00:00:00 2001 From: Charlotte Tan Date: Mon, 16 Oct 2017 07:09:32 -0700 Subject: [PATCH] Add/verilog courses #2151 (#2587) * Update Verilog courses Renamed `SystemVerilog` section to `Verilog / VHDL / SystemVerilog` because they are 3 different hardware description languages. Grouped them together so that all the Verilog resources can be found in one spot. Added new course as suggested in #2151 * Reorder Verilog courses by alphabetical order * Add new course suggested by @mramdas * Reorder Verilog courses --- free-courses-en.md | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/free-courses-en.md b/free-courses-en.md index b3be0a86..194a00e3 100644 --- a/free-courses-en.md +++ b/free-courses-en.md @@ -40,8 +40,8 @@ * [Scala](#scala) * [Software Engineering](#software-engineering) * [Swift](#swift) -* [SystemVerilog](#systemverilog) * [Theory](#theory) +* [Verilog / VHDL / SystemVerilog](#verilog--vhdl--systemverilog) * [Web Development](#web-development) @@ -337,18 +337,20 @@ * [Swiftris - Build an iOS Tetris app from scratch](https://www.bloc.io/swiftris-build-your-first-ios-game-with-swift) -### SystemVerilog - -* [SystemVerilog - Learn basics of SystemVerilog for Hardware Verification](https://verificationexcellence.teachable.com/p/learn-systemverilog) -* [SystemVerilog based UVM Methodology - Learn to build UVM based Testbenches in SystemVerilog](https://verificationexcellence.teachable.com/p/learn-ovm-uvm) - - ### Theory * [Automata Theory](https://lagunita.stanford.edu/courses/course-v1:ComputerScience+Automata+Fall2016/about) * [Udacity: Intro to Theoretical Computer Science](https://www.udacity.com/course/intro-to-theoretical-computer-science--cs313) +### Verilog / VHDL / SystemVerilog + +* [SOC Verification Using SystemVerilog](http://verificationexcellence.in/online-courses/soc-verification-using-systemverilog) +* [SystemVerilog - Learn basics of SystemVerilog for Hardware Verification](https://verificationexcellence.teachable.com/p/learn-systemverilog) +* [SystemVerilog based UVM Methodology - Learn to build UVM based Testbenches in SystemVerilog](https://verificationexcellence.teachable.com/p/learn-ovm-uvm) +* [Verilog Hardware Description Language - An Introductory Course](http://vol.verilog.com/VOL/main.htm) + + ### Web Development * [Discover Flask - Full Stack Web Development with Flask](https://github.com/realpython/discover-flask) -- GitLab