diff --git a/bsp/stm32_radio/application.c b/bsp/stm32_radio/application.c index d73feeb523424eb3846507f153ea6703ebe9d937..8f2544f5741b1208a2cb4cef2c3c18cace6e7c1a 100644 --- a/bsp/stm32_radio/application.c +++ b/bsp/stm32_radio/application.c @@ -113,8 +113,6 @@ int rt_application_init() { rt_thread_t init_thread; - rt_hw_lcd_init(); - #if (RT_THREAD_PRIORITY_MAX == 32) init_thread = rt_thread_create("init", rt_init_thread_entry, RT_NULL, diff --git a/bsp/stm32_radio/board.c b/bsp/stm32_radio/board.c index c53af4429c12dab414e090bd548f02297834b8a6..b2a2928b3c16aa204394136641cfc4f78aee70b6 100644 --- a/bsp/stm32_radio/board.c +++ b/bsp/stm32_radio/board.c @@ -118,6 +118,74 @@ static void all_device_reset(void) GPIO_Init(GPIOA,&GPIO_InitStructure); GPIO_ResetBits(GPIOA,GPIO_Pin_3); + /* FSMC GPIO configure */ + { + GPIO_InitTypeDef GPIO_InitStructure; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_GPIOF + | RCC_APB2Periph_GPIOG, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + + /* + FSMC_D0 ~ FSMC_D3 + PD14 FSMC_D0 PD15 FSMC_D1 PD0 FSMC_D2 PD1 FSMC_D3 + */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOD,&GPIO_InitStructure); + + /* + FSMC_D4 ~ FSMC_D12 + PE7 ~ PE15 FSMC_D4 ~ FSMC_D12 + */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 + | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOE,&GPIO_InitStructure); + + /* FSMC_D13 ~ FSMC_D15 PD8 ~ PD10 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10; + GPIO_Init(GPIOD,&GPIO_InitStructure); + + /* + FSMC_A0 ~ FSMC_A5 FSMC_A6 ~ FSMC_A9 + PF0 ~ PF5 PF12 ~ PF15 + */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 + | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOF,&GPIO_InitStructure); + + /* FSMC_A10 ~ FSMC_A15 PG0 ~ PG5 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5; + GPIO_Init(GPIOG,&GPIO_InitStructure); + + /* FSMC_A16 ~ FSMC_A18 PD11 ~ PD13 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; + GPIO_Init(GPIOD,&GPIO_InitStructure); + + /* RD-PD4 WR-PD5 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5; + GPIO_Init(GPIOD,&GPIO_InitStructure); + + /* NBL0-PE0 NBL1-PE1 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1; + GPIO_Init(GPIOE,&GPIO_InitStructure); + + /* NE1/NCE2 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_Init(GPIOD,&GPIO_InitStructure); + /* NE2 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_Init(GPIOG,&GPIO_InitStructure); + /* NE3 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_Init(GPIOG,&GPIO_InitStructure); + /* NE4 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_Init(GPIOG,&GPIO_InitStructure); + } + /* FSMC GPIO configure */ + GPIO_SetBits(GPIOE,GPIO_Pin_5); /* DM9000A */ GPIO_SetBits(GPIOF,GPIO_Pin_10); /* LCD */ GPIO_SetBits(GPIOA,GPIO_Pin_3); /* SPI_FLASH */ @@ -129,7 +197,7 @@ static void all_device_reset(void) extern void FSMC_SRAM_Init(void); void rt_hw_board_init() { - NAND_IDTypeDef NAND_ID; + //NAND_IDTypeDef NAND_ID; /* Configure the system clocks */ SystemInit(); @@ -147,11 +215,11 @@ void rt_hw_board_init() rt_kprintf("\r\n\r\nSystemInit......\r\n"); /* FSMC Initialization */ - FSMC_NAND_Init(); + //FSMC_NAND_Init(); /* NAND read ID command */ - FSMC_NAND_ReadID(&NAND_ID); - rt_kprintf("Read the NAND ID:%02X%02X%02X%02X",NAND_ID.Maker_ID,NAND_ID.Device_ID,NAND_ID.Third_ID,NAND_ID.Fourth_ID); + //FSMC_NAND_ReadID(&NAND_ID); + //rt_kprintf("Read the NAND ID:%02X%02X%02X%02X",NAND_ID.Maker_ID,NAND_ID.Device_ID,NAND_ID.Third_ID,NAND_ID.Fourth_ID); /* SRAM init */ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); @@ -214,7 +282,7 @@ void rt_hw_board_init() SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;/* 72M/64=1.125M */ + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;/* 72M/64=1.125M */ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; SPI_InitStructure.SPI_CRCPolynomial = 7; diff --git a/bsp/stm32_radio/fmt0371/fmt0371.c b/bsp/stm32_radio/fmt0371/fmt0371.c index 1cbed50e50e7aff1a77aec388e052669a9b02cb0..dea9e266146b5e03dfb0ac3f05e867f8ea6027b6 100644 --- a/bsp/stm32_radio/fmt0371/fmt0371.c +++ b/bsp/stm32_radio/fmt0371/fmt0371.c @@ -3,61 +3,61 @@ #define FSMC_GPIO_CONFIG -static void delay_ms(unsigned int dt) -{ - volatile unsigned int u; - for (u=0;uD3, NOE, NWE and NCE2 NAND pin configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 | - GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | - GPIO_Pin_7; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - - GPIO_Init(GPIOD, &GPIO_InitStructure); - -/* D4->D7 NAND pin configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10; - - GPIO_Init(GPIOE, &GPIO_InitStructure); - - -/* NWAIT NAND pin configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - - GPIO_Init(GPIOD, &GPIO_InitStructure); - -/* INT2 NAND pin configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - /*-- FSMC Configuration ------------------------------------------------------*/ - p.FSMC_SetupTime = 0x1; - p.FSMC_WaitSetupTime = 0x3; - p.FSMC_HoldSetupTime = 0x2; - p.FSMC_HiZSetupTime = 0x1; - - FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable; - FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable; - FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes; + FSMC_NANDInitTypeDef FSMC_NANDInitStructure; + FSMC_NAND_PCCARDTimingInitTypeDef p; + + /*-- FSMC Configuration ------------------------------------------------------*/ + p.FSMC_SetupTime = 0x1; + p.FSMC_WaitSetupTime = 0x3; + p.FSMC_HoldSetupTime = 0x2; + p.FSMC_HiZSetupTime = 0x1; + + FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable; + FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable; + FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes; // FSMC_NANDInitStructure.FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct; - FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00; - FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00; - FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p; - FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p; + FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00; + FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00; + FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p; + FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p; - FSMC_NANDInit(&FSMC_NANDInitStructure); + FSMC_NANDInit(&FSMC_NANDInitStructure); - /* FSMC NAND Bank Cmd Test */ - FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE); + /* FSMC NAND Bank Cmd Test */ + FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE); } /****************************************************************************** @@ -107,253 +76,253 @@ void FSMC_NAND_Init(void) *******************************************************************************/ void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID) { - u32 data = 0; + u32 data = 0; - /* Send Command to the command area */ - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = 0x90; - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; + /* Send Command to the command area */ + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = 0x90; + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; - /* Sequence to read ID from NAND flash */ - data = *(vu32 *)(Bank_NAND_ADDR | DATA_AREA); + /* Sequence to read ID from NAND flash */ + data = *(vu32 *)(Bank_NAND_ADDR | DATA_AREA); - NAND_ID->Maker_ID = ADDR_1st_CYCLE (data); - NAND_ID->Device_ID = ADDR_2nd_CYCLE (data); - NAND_ID->Third_ID = ADDR_3rd_CYCLE (data); - NAND_ID->Fourth_ID = ADDR_4th_CYCLE (data); + NAND_ID->Maker_ID = ADDR_1st_CYCLE (data); + NAND_ID->Device_ID = ADDR_2nd_CYCLE (data); + NAND_ID->Third_ID = ADDR_3rd_CYCLE (data); + NAND_ID->Fourth_ID = ADDR_4th_CYCLE (data); } /****************************************************************************** * Function Name : FSMC_NAND_WriteSmallPage * Description : This routine is for writing one or several 512 Bytes Page size. -* Input : - pBuffer: pointer on the Buffer containing data to be written +* Input : - pBuffer: pointer on the Buffer containing data to be written * - Address: First page address -* - NumPageToWrite: Number of page to write +* - NumPageToWrite: Number of page to write * Output : None * Return : New status of the NAND operation. This parameter can be: -* - NAND_TIMEOUT_ERROR: when the previous operation generate +* - NAND_TIMEOUT_ERROR: when the previous operation generate * a Timeout error -* - NAND_READY: when memory is ready for the next operation +* - NAND_READY: when memory is ready for the next operation * And the new status of the increment address operation. It can be: * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address *******************************************************************************/ u32 FSMC_NAND_WriteSmallPage(u8 *pBuffer, NAND_ADDRESS Address, u32 NumPageToWrite) { - u32 index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS; - u32 status = NAND_READY, size = 2048; + u32 index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS; + u32 status = NAND_READY, size = 2048; - while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY)) - { - /* Page write command and address */ - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A; - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0; + while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY)) + { + /* Page write command and address */ + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A; + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0; - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS); - /* Calculate the size */ - size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten); + /* Calculate the size */ + size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten); - /* Write data */ - for(; index < size; index++) - { - *(vu8 *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index]; - } - - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1; + /* Write data */ + for(; index < size; index++) + { + *(vu8 *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index]; + } - /* Check status for successful operation */ - status = FSMC_NAND_GetStatus(); - - if(status == NAND_READY) - { - numpagewritten++; + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1; - NumPageToWrite--; + /* Check status for successful operation */ + status = FSMC_NAND_GetStatus(); - /* Calculate Next small page Address */ - addressstatus = FSMC_NAND_AddressIncrement(&Address); - } - } - - return (status | addressstatus); + if(status == NAND_READY) + { + numpagewritten++; + + NumPageToWrite--; + + /* Calculate Next small page Address */ + addressstatus = FSMC_NAND_AddressIncrement(&Address); + } + } + + return (status | addressstatus); } /****************************************************************************** * Function Name : FSMC_NAND_ReadSmallPage -* Description : This routine is for sequential read from one or several +* Description : This routine is for sequential read from one or several * 512 Bytes Page size. -* Input : - pBuffer: pointer on the Buffer to fill +* Input : - pBuffer: pointer on the Buffer to fill * - Address: First page address * - NumPageToRead: Number of page to read * Output : None * Return : New status of the NAND operation. This parameter can be: -* - NAND_TIMEOUT_ERROR: when the previous operation generate +* - NAND_TIMEOUT_ERROR: when the previous operation generate * a Timeout error -* - NAND_READY: when memory is ready for the next operation +* - NAND_READY: when memory is ready for the next operation * And the new status of the increment address operation. It can be: * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address *******************************************************************************/ u32 FSMC_NAND_ReadSmallPage(u8 *pBuffer, NAND_ADDRESS Address, u32 NumPageToRead) { - u32 index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS; - u32 status = NAND_READY, size = 2048, i = 0; - - /* Calculate the size */ - size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread); - - while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS)) - { - /* Page Read command and page address */ - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A; - - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS); - - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1; - for(i = 0; i <= 10000; i++); - - /* Get Data into Buffer */ - for(; index < size; index++) + u32 index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS; + u32 status = NAND_READY, size = 2048, i = 0; + + /* Calculate the size */ + size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread); + + while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS)) { - pBuffer[index]= *(vu8 *)(Bank_NAND_ADDR | DATA_AREA); - } + /* Page Read command and page address */ + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A; + + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS); + + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1; + for(i = 0; i <= 10000; i++); + + /* Get Data into Buffer */ + for(; index < size; index++) + { + pBuffer[index]= *(vu8 *)(Bank_NAND_ADDR | DATA_AREA); + } + + numpageread++; + + NumPageToRead--; - numpageread++; - - NumPageToRead--; + /* Calculate page address */ + addressstatus = FSMC_NAND_AddressIncrement(&Address); + } - /* Calculate page address */ - addressstatus = FSMC_NAND_AddressIncrement(&Address); - } + status = FSMC_NAND_GetStatus(); - status = FSMC_NAND_GetStatus(); - - return (status | addressstatus); + return (status | addressstatus); } /****************************************************************************** * Function Name : FSMC_NAND_WriteSpareArea -* Description : This routine write the spare area information for the specified +* Description : This routine write the spare area information for the specified * pages addresses. -* Input : - pBuffer: pointer on the Buffer containing data to be written +* Input : - pBuffer: pointer on the Buffer containing data to be written * - Address: First page address * - NumSpareAreaTowrite: Number of Spare Area to write * Output : None * Return : New status of the NAND operation. This parameter can be: -* - NAND_TIMEOUT_ERROR: when the previous operation generate +* - NAND_TIMEOUT_ERROR: when the previous operation generate * a Timeout error -* - NAND_READY: when memory is ready for the next operation +* - NAND_READY: when memory is ready for the next operation * And the new status of the increment address operation. It can be: * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address *******************************************************************************/ u32 FSMC_NAND_WriteSpareArea(u8 *pBuffer, NAND_ADDRESS Address, u32 NumSpareAreaTowrite) { - u32 index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS; - u32 status = NAND_READY, size = 0x00; + u32 index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS; + u32 status = NAND_READY, size = 0x00; - while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY)) - { - /* Page write Spare area command and address */ - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C; - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0; - - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS); - /* Calculate the size */ - size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten); - - /* Write the data */ - for(; index < size; index++) + while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY)) { - *(vu8 *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index]; + /* Page write Spare area command and address */ + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C; + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0; + + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS); + /* Calculate the size */ + size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten); + + /* Write the data */ + for(; index < size; index++) + { + *(vu8 *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index]; + } + + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1; + + /* Check status for successful operation */ + status = FSMC_NAND_GetStatus(); + + if(status == NAND_READY) + { + numsparesreawritten++; + + NumSpareAreaTowrite--; + + /* Calculate Next page Address */ + addressstatus = FSMC_NAND_AddressIncrement(&Address); + } } - - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1; - /* Check status for successful operation */ - status = FSMC_NAND_GetStatus(); - - if(status == NAND_READY) - { - numsparesreawritten++; - - NumSpareAreaTowrite--; - - /* Calculate Next page Address */ - addressstatus = FSMC_NAND_AddressIncrement(&Address); - } - } - - return (status | addressstatus); + return (status | addressstatus); } /****************************************************************************** * Function Name : FSMC_NAND_ReadSpareArea * Description : This routine read the spare area information from the specified * pages addresses. -* Input : - pBuffer: pointer on the Buffer to fill +* Input : - pBuffer: pointer on the Buffer to fill * - Address: First page address * - NumSpareAreaToRead: Number of Spare Area to read * Output : None * Return : New status of the NAND operation. This parameter can be: -* - NAND_TIMEOUT_ERROR: when the previous operation generate +* - NAND_TIMEOUT_ERROR: when the previous operation generate * a Timeout error -* - NAND_READY: when memory is ready for the next operation +* - NAND_READY: when memory is ready for the next operation * And the new status of the increment address operation. It can be: * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address *******************************************************************************/ u32 FSMC_NAND_ReadSpareArea(u8 *pBuffer, NAND_ADDRESS Address, u32 NumSpareAreaToRead) { - u32 numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS; - u32 status = NAND_READY, size = 0x00; + u32 numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS; + u32 status = NAND_READY, size = 0x00; - while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS)) - { - /* Page Read command and page address */ - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C; + while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS)) + { + /* Page Read command and page address */ + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C; - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1; + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1; - /* Data Read */ - size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparearearead); - - /* Get Data into Buffer */ - for ( ;index < size; index++) - { - pBuffer[index] = *(vu8 *)(Bank_NAND_ADDR | DATA_AREA); - } - - numsparearearead++; - - NumSpareAreaToRead--; + /* Data Read */ + size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparearearead); + + /* Get Data into Buffer */ + for ( ; index < size; index++) + { + pBuffer[index] = *(vu8 *)(Bank_NAND_ADDR | DATA_AREA); + } + + numsparearearead++; + + NumSpareAreaToRead--; - /* Calculate page address */ - addressstatus = FSMC_NAND_AddressIncrement(&Address); - } + /* Calculate page address */ + addressstatus = FSMC_NAND_AddressIncrement(&Address); + } - status = FSMC_NAND_GetStatus(); + status = FSMC_NAND_GetStatus(); - return (status | addressstatus); + return (status | addressstatus); } /****************************************************************************** @@ -362,23 +331,23 @@ u32 FSMC_NAND_ReadSpareArea(u8 *pBuffer, NAND_ADDRESS Address, u32 NumSpareAreaT * Input : - Address: Any address into block to be erased * Output : None * Return : New status of the NAND operation. This parameter can be: -* - NAND_TIMEOUT_ERROR: when the previous operation generate +* - NAND_TIMEOUT_ERROR: when the previous operation generate * a Timeout error -* - NAND_READY: when memory is ready for the next operation +* - NAND_READY: when memory is ready for the next operation *******************************************************************************/ u32 FSMC_NAND_EraseBlock(NAND_ADDRESS Address) { - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0; + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0; - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS); - *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS); - - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1; + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS); + *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS); - return (FSMC_NAND_GetStatus()); + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1; + + return (FSMC_NAND_GetStatus()); } /****************************************************************************** @@ -390,9 +359,9 @@ u32 FSMC_NAND_EraseBlock(NAND_ADDRESS Address) *******************************************************************************/ u32 FSMC_NAND_Reset(void) { - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET; + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET; - return (NAND_READY); + return (NAND_READY); } /****************************************************************************** @@ -401,63 +370,63 @@ u32 FSMC_NAND_Reset(void) * Input : None * Output : None * Return : New status of the NAND operation. This parameter can be: -* - NAND_TIMEOUT_ERROR: when the previous operation generate +* - NAND_TIMEOUT_ERROR: when the previous operation generate * a Timeout error -* - NAND_READY: when memory is ready for the next operation +* - NAND_READY: when memory is ready for the next operation *******************************************************************************/ u32 FSMC_NAND_GetStatus(void) { - u32 timeout = 0x1000000, status = NAND_READY; + u32 timeout = 0x1000000, status = NAND_READY; - status = FSMC_NAND_ReadStatus(); + status = FSMC_NAND_ReadStatus(); - /* Wait for a NAND operation to complete or a TIMEOUT to occur */ - while ((status != NAND_READY) &&( timeout != 0x00)) - { - status = FSMC_NAND_ReadStatus(); - timeout --; - } + /* Wait for a NAND operation to complete or a TIMEOUT to occur */ + while ((status != NAND_READY) &&( timeout != 0x00)) + { + status = FSMC_NAND_ReadStatus(); + timeout --; + } - if(timeout == 0x00) - { - status = NAND_TIMEOUT_ERROR; - } + if(timeout == 0x00) + { + status = NAND_TIMEOUT_ERROR; + } - /* Return the operation status */ - return (status); + /* Return the operation status */ + return (status); } /****************************************************************************** * Function Name : FSMC_NAND_ReadStatus -* Description : Reads the NAND memory status using the Read status command +* Description : Reads the NAND memory status using the Read status command * Input : None * Output : None * Return : The status of the NAND memory. This parameter can be: * - NAND_BUSY: when memory is busy -* - NAND_READY: when memory is ready for the next operation -* - NAND_ERROR: when the previous operation gererates error +* - NAND_READY: when memory is ready for the next operation +* - NAND_ERROR: when the previous operation gererates error *******************************************************************************/ u32 FSMC_NAND_ReadStatus(void) { - u32 data = 0x00, status = NAND_BUSY; - - /* Read status operation ------------------------------------ */ - *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS; - data = *(vu8 *)(Bank_NAND_ADDR); - - if((data & NAND_ERROR) == NAND_ERROR) - { - status = NAND_ERROR; - } - else if((data & NAND_READY) == NAND_READY) - { - status = NAND_READY; - } - else - { - status = NAND_BUSY; - } - - return (status); + u32 data = 0x00, status = NAND_BUSY; + + /* Read status operation ------------------------------------ */ + *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS; + data = *(vu8 *)(Bank_NAND_ADDR); + + if((data & NAND_ERROR) == NAND_ERROR) + { + status = NAND_ERROR; + } + else if((data & NAND_READY) == NAND_READY) + { + status = NAND_READY; + } + else + { + status = NAND_BUSY; + } + + return (status); } /****************************************************************************** @@ -471,28 +440,28 @@ u32 FSMC_NAND_ReadStatus(void) *******************************************************************************/ u32 FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address) { - u32 status = NAND_VALID_ADDRESS; - - Address->Page++; - - if(Address->Page == NAND_BLOCK_SIZE) - { - Address->Page = 0; - Address->Block++; - - if(Address->Block == NAND_ZONE_SIZE) - { - Address->Block = 0; - Address->Zone++; + u32 status = NAND_VALID_ADDRESS; - if(Address->Zone == NAND_MAX_ZONE) - { - status = NAND_INVALID_ADDRESS; - } + Address->Page++; + + if(Address->Page == NAND_BLOCK_SIZE) + { + Address->Page = 0; + Address->Block++; + + if(Address->Block == NAND_ZONE_SIZE) + { + Address->Block = 0; + Address->Zone++; + + if(Address->Zone == NAND_MAX_ZONE) + { + status = NAND_INVALID_ADDRESS; + } + } } - } - - return (status); + + return (status); } /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/fsmc_sram.c b/bsp/stm32_radio/fsmc_sram.c index 43fcf3735f96d30b3d0be464bf4ab1186d059f85..538308d1bd5c0a14711705ef30691dd369ead459 100644 --- a/bsp/stm32_radio/fsmc_sram.c +++ b/bsp/stm32_radio/fsmc_sram.c @@ -34,83 +34,41 @@ *******************************************************************************/ void FSMC_SRAM_Init(void) { - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - FSMC_NORSRAMTimingInitTypeDef p; - GPIO_InitTypeDef GPIO_InitStructure; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE | - RCC_APB2Periph_GPIOF, ENABLE); - -/*-- GPIO Configuration ------------------------------------------------------*/ - /* SRAM Data lines configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | - GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /* SRAM Address lines configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | - GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOF, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | - GPIO_Pin_4 | GPIO_Pin_5; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* NOE and NWE configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* NE3 NE4 configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_12; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - /* NBL0, NBL1 configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1; - GPIO_Init(GPIOE, &GPIO_InitStructure); - -/*-- FSMC Configuration ------------------------------------------------------*/ - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 2; - p.FSMC_BusTurnAroundDuration = 0; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; - - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4; - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - /* Enable FSMC Bank1_SRAM Bank */ - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE); + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + FSMC_NORSRAMTimingInitTypeDef p; + + /*-- FSMC Configuration ------------------------------------------------------*/ + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 2; + p.FSMC_BusTurnAroundDuration = 0; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4; + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + /* Enable FSMC Bank1_SRAM Bank */ + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE); } /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/ili9325/ili9325.c b/bsp/stm32_radio/ili9325/ili9325.c index 9796ee01b1abca77d040d7f8ba806f8a816655d1..e3a2a3d5c53c33910fe84f34d291b3232e64d813 100644 --- a/bsp/stm32_radio/ili9325/ili9325.c +++ b/bsp/stm32_radio/ili9325/ili9325.c @@ -125,44 +125,6 @@ static u16 DeviceCode; -static void LCD_CtrlLinesConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | - RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG | - RCC_APB2Periph_AFIO, ENABLE); - - /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14), - PD.10(D15), PD.14(D0), PD.15(D1) as alternate - function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | - GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10), - PE.14(D11), PE.15(D12) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - GPIO_WriteBit(GPIOE, GPIO_Pin_6, Bit_SET); - /* Set PF.00(A0 (RS)) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2; - GPIO_Init(GPIOF, &GPIO_InitStructure); - - /* Set NE2(LCD/CS) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_Init(GPIOG, &GPIO_InitStructure); -} - /******************************************************************************* * Function Name : LCD_FSMCConfig * Description : Configures the Parallel interface (FSMC) for LCD(Parallel mode) @@ -213,17 +175,6 @@ static void LCD_FSMCConfig(void) FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); } - -static void LCD_X_Init(void) -{ - /* Configure the LCD Control pins --------------------------------------------*/ - LCD_CtrlLinesConfig(); - - /* Configure the FSMC Parallel interface -------------------------------------*/ - LCD_FSMCConfig(); -} - - /******************************************************************************* * Function Name : ili9325_WriteReg * Description : Writes to the selected LCD register. @@ -295,19 +246,7 @@ unsigned short ili9325_ReadGRAM(unsigned short x,unsigned short y) void ili9325_Initializtion(void) { volatile unsigned int i; - LCD_X_Init(); - - { - GPIO_InitTypeDef GPIO_InitStructure; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF,ENABLE); - - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_Init(GPIOF,&GPIO_InitStructure); - } - GPIO_SetBits(GPIOF, GPIO_Pin_10); + LCD_FSMCConfig(); DeviceCode = LCD_ReadReg(0x0000); if (DeviceCode==0x9325||DeviceCode==0x9328)