diff --git a/bsp/lpc176x/SConscript b/bsp/lpc176x/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..033c7e862161c300f773b092006bc06abc5f6729
--- /dev/null
+++ b/bsp/lpc176x/SConscript
@@ -0,0 +1,30 @@
+Import('env')
+Import('projects')
+Import('RTT_ROOT')
+Import('rtconfig')
+
+# group definitions
+group = {}
+group['name'] = 'Startup'
+group['CCFLAGS'] = ''
+group['CPPPATH'] = [RTT_ROOT + '/bsp/lpc176x', RTT_ROOT + '/bsp/lpc176x/CMSIS']
+group['CPPDEFINES'] = []
+group['LINKFLAGS'] = ''
+
+src_bsp = ['application.c', 'startup.c', 'board.c']
+src_drv = ['uart.c']
+src_cmsis = ['CMSIS/core_cm3.c', 'CMSIS/system_LPC17xx.c']
+
+group['src'] = File(src_bsp + src_drv + src_cmsis)
+
+# add group to project list
+projects.append(group)
+
+env.Append(CCFLAGS = group['CCFLAGS'])
+env.Append(CPPPATH = group['CPPPATH'])
+env.Append(CPPDEFINES = group['CPPDEFINES'])
+env.Append(LINKFLAGS = group['LINKFLAGS'])
+
+obj = env.Object(group['src'])
+
+Return('obj')
diff --git a/bsp/lpc176x/SConstruct b/bsp/lpc176x/SConstruct
new file mode 100644
index 0000000000000000000000000000000000000000..e3e8593216361389d70424398886053133cd7394
--- /dev/null
+++ b/bsp/lpc176x/SConstruct
@@ -0,0 +1,49 @@
+import os
+import sys
+import rtconfig
+
+RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+import mdk
+
+target = 'rtthread-lpc176x'
+projects = []
+
+AddOption('--target',
+ dest='target',
+ type='string',
+ help='set target project: mdk')
+
+if GetOption('target'):
+ SetOption('no_exec', 1)
+
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('env')
+Export('RTT_ROOT')
+Export('rtconfig')
+Export('projects')
+
+# kernel building script
+objs = SConscript(RTT_ROOT + '/src/SConscript', variant_dir='build/src', duplicate=0)
+# arch building script
+objs = objs + SConscript(RTT_ROOT + '/libcpu/SConscript', variant_dir='build/libcpu', duplicate=0)
+
+# component script
+Repository(RTT_ROOT)
+objs = objs + SConscript('components/SConscript')
+
+# board build script
+objs = objs + SConscript('SConscript', variant_dir='build/bsp', duplicate=0)
+
+TARGET = target + '.' + rtconfig.TARGET_EXT
+env.Program(TARGET, objs)
+env.AddPostAction(TARGET, rtconfig.POST_ACTION)
+
+if GetOption('target') == 'mdk':
+ mdk.MDKProject('project.uV2', projects)
diff --git a/bsp/lpc176x/lpc17rt-thread.uvopt b/bsp/lpc176x/lpc17rt-thread.uvopt
deleted file mode 100644
index 6f70eba25ad80e696ec069f19fe55bef7b63b632..0000000000000000000000000000000000000000
--- a/bsp/lpc176x/lpc17rt-thread.uvopt
+++ /dev/null
@@ -1,2162 +0,0 @@
-
-
-
- 1.0
-
- ### uVision Project, (C) Keil Software
-
-
- *.c
- *.s*; *.src; *.a*
- *.obj
- *.lib
- *.txt; *.h; *.inc
- *.plm
- *.cpp
-
-
-
- 0
- 0
-
-
-
- RT-Thread LPC1700
- 0x4
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-
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-
-
- 1
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- DATASHTS\PHILIPS\LPC17xx_UM.pdf
-
-
- 2
- Errata Sheet
- DATASHTS\PHILIPS\LPC1766_ES.pdf
-
-
-
- SARMCM3.DLL
- -MPU
- DARMP1.DLL
- -pLPC1766
- SARMCM3.DLL
- -MPU
- TARMP1.DLL
- -pLPC1766
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-
-
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-
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diff --git a/bsp/lpc176x/lpc17rt-thread.uvproj b/bsp/lpc176x/lpc17rt-thread.uvproj
deleted file mode 100644
index 5bd118f3f24da3c9195f93ecbad9fa18474905be..0000000000000000000000000000000000000000
--- a/bsp/lpc176x/lpc17rt-thread.uvproj
+++ /dev/null
@@ -1,628 +0,0 @@
-
-
-
- 1.0
-
- ### uVision Project, (C) Keil Software
-
-
-
- RT-Thread LPC1700
- 0x4
- ARM-ADS
-
-
- LPC1766
- NXP (founded by Philips)
- IRAM(0x10000000-0x10007FFF) IRAM2(0x2007C000-0x20083FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE("Cortex-M3")
-
- "STARTUP\NXP\LPC17xx\startup_LPC17xx.s" ("NXP LPC17xx Startup Code")
- UL2CM3(-O463 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL040000)
- 4629
- LPC17xx.H
-
-
-
-
-
-
-
-
-
- 0
-
-
-
- NXP\LPC17xx\
- NXP\LPC17xx\
-
- 0
- 0
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- 1
-
- .\obj\
- lpc17rt-thread
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- 1
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-
-
-
-
- SARMCM3.DLL
- -MPU
- DARMP1.DLL
- -pLPC1766
- SARMCM3.DLL
- -MPU
- TARMP1.DLL
- -pLPC1766
-
-
-
- 1
- 0
- 0
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- 16
-
-
- 1
- 1
- 1
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- 1
- 1
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-
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-
-
-
-
-
- BIN\UL2CM3.DLL
-
-
-
-
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- 4096
-
- BIN\UL2CM3.DLL
-
-
-
-
-
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- 1
- 1
- 1
- 1
- 1
- 1
- 1
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- "Cortex-M3"
-
- 0
- 0
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- 8
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-
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-
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-
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-
-
- 1
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- 0x40000
-
-
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-
-
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-
-
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- 0x8000
-
-
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- 0x8000
-
-
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- 0
- 0
-
-
-
-
- .;..\..\include;..\..\libcpu\arm\lpc17xx;.\Libraries\CMSIS\Core\CM3;.\Libraries\LPC17xx_StdPeriph_Drivers\include;..\..\finsh;..\..\filesystem\dfs\include;..\..\filesystem\dfs\;..\..\rtgui\include
-
-
-
- 1
- 0
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-
-
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- 0
- 0
- 1
- 0
- 0x00000000
- 0x10000000
-
-
-
-
-
-
-
-
-
-
-
- Startup
-
-
- board.h
- 5
- .\board.h
-
-
- rtconfig.h
- 5
- .\rtconfig.h
-
-
- board.c
- 1
- .\board.c
-
-
- startup.c
- 1
- .\startup.c
-
-
- uart.c
- 1
- .\uart.c
-
-
- application.c
- 1
- .\application.c
-
-
-
-
- CMSIS
-
-
- core_cm3.c
- 1
- .\CMSIS\core_cm3.c
-
-
- system_LPC17xx.c
- 1
- .\CMSIS\system_LPC17xx.c
-
-
-
-
- Kernel
-
-
- clock.c
- 1
- ..\..\src\clock.c
-
-
- device.c
- 1
- ..\..\src\device.c
-
-
- idle.c
- 1
- ..\..\src\idle.c
-
-
- ipc.c
- 1
- ..\..\src\ipc.c
-
-
- irq.c
- 1
- ..\..\src\irq.c
-
-
- kservice.c
- 1
- ..\..\src\kservice.c
-
-
- mem.c
- 1
- ..\..\src\mem.c
-
-
- mempool.c
- 1
- ..\..\src\mempool.c
-
-
- object.c
- 1
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-
-
- scheduler.c
- 1
- ..\..\src\scheduler.c
-
-
- slab.c
- 1
- ..\..\src\slab.c
-
-
- thread.c
- 1
- ..\..\src\thread.c
-
-
- timer.c
- 1
- ..\..\src\timer.c
-
-
-
-
- LPC1700
-
-
- cpu.c
- 1
- ..\..\libcpu\arm\lpc17xx\cpu.c
-
-
- fault.c
- 1
- ..\..\libcpu\arm\lpc17xx\fault.c
-
-
- interrupt.c
- 1
- ..\..\libcpu\arm\lpc17xx\interrupt.c
-
-
- stack.c
- 1
- ..\..\libcpu\arm\lpc17xx\stack.c
-
-
- context_rvds.S
- 2
- ..\..\libcpu\arm\lpc17xx\context_rvds.S
-
-
- fault_rvds.S
- 2
- ..\..\libcpu\arm\lpc17xx\fault_rvds.S
-
-
- start_rvds.S
- 2
- ..\..\libcpu\arm\lpc17xx\start_rvds.S
-
-
-
-
- finish
-
-
- cmd.c
- 1
- ..\..\finsh\cmd.c
-
-
- finsh_compiler.c
- 1
- ..\..\finsh\finsh_compiler.c
-
-
- finsh_error.c
- 1
- ..\..\finsh\finsh_error.c
-
-
- finsh_heap.c
- 1
- ..\..\finsh\finsh_heap.c
-
-
- finsh_init.c
- 1
- ..\..\finsh\finsh_init.c
-
-
- finsh_node.c
- 1
- ..\..\finsh\finsh_node.c
-
-
- finsh_ops.c
- 1
- ..\..\finsh\finsh_ops.c
-
-
- finsh_parser.c
- 1
- ..\..\finsh\finsh_parser.c
-
-
- finsh_token.c
- 1
- ..\..\finsh\finsh_token.c
-
-
- finsh_var.c
- 1
- ..\..\finsh\finsh_var.c
-
-
- finsh_vm.c
- 1
- ..\..\finsh\finsh_vm.c
-
-
- shell.c
- 1
- ..\..\finsh\shell.c
-
-
- symbol.c
- 1
- ..\..\finsh\symbol.c
-
-
-
-
- Filesystem
-
-
- LWIP
-
-
- RTGUI
-
-
-
-
-
-
diff --git a/bsp/lpc176x/lpc17xx_rom.sct b/bsp/lpc176x/lpc17xx_rom.sct
new file mode 100644
index 0000000000000000000000000000000000000000..5337368098579600ad016bd636bf4e48cf62b8e9
--- /dev/null
+++ b/bsp/lpc176x/lpc17xx_rom.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x10000000 0x00008000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/lpc176x/rtconfig.h b/bsp/lpc176x/rtconfig.h
index e050e66ad55a01b9bce6ae829a21904845136e42..e2500c6e5f8a4a62453066eea758dd1d6d31fb67 100644
--- a/bsp/lpc176x/rtconfig.h
+++ b/bsp/lpc176x/rtconfig.h
@@ -86,7 +86,8 @@
#define DFS_CACHE_MAX_NUM 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
-//#define RT_USING_LWIP
+/* #define RT_USING_LWIP */
+#define RT_LWIP_USING_RT_MEM
/* Enable ICMP protocol*/
#define RT_LWIP_ICMP
diff --git a/bsp/lpc176x/rtconfig.py b/bsp/lpc176x/rtconfig.py
new file mode 100644
index 0000000000000000000000000000000000000000..1f0f0cea1639dd53d6820716aaa5c729cbcd779e
--- /dev/null
+++ b/bsp/lpc176x/rtconfig.py
@@ -0,0 +1,131 @@
+import SCons.cpp
+
+# component options
+
+# make all component false
+RT_USING_FINSH = False
+RT_USING_DFS = False
+RT_USING_DFS_ELMFAT = False
+RT_USING_DFS_YAFFS2 = False
+RT_USING_LWIP = False
+RT_USING_WEBSERVER = False
+RT_USING_RTGUI = False
+
+# parse rtconfig.h to get used component
+PreProcessor = SCons.cpp.PreProcessor()
+f = file('rtconfig.h', 'r')
+contents = f.read()
+f.close()
+PreProcessor.process_contents(contents)
+rtconfig_ns = PreProcessor.cpp_namespace
+
+# finsh shell options
+if rtconfig_ns.has_key('RT_USING_FINSH'):
+ RT_USING_FINSH = True
+
+# device virtual filesystem options
+if rtconfig_ns.has_key('RT_USING_DFS'):
+ RT_USING_DFS = True
+
+ if rtconfig_ns.has_key('RT_USING_DFS_ELMFAT'):
+ RT_USING_DFS_ELMFAT = True
+ if rtconfig_ns.has_key('RT_USING_DFS_YAFFS2'):
+ RT_USING_DFS_YAFFS2 = True
+
+# lwip options
+if rtconfig_ns.has_key('RT_USING_LWIP'):
+ RT_USING_LWIP = True
+ if rtconfig_ns.has_key('RT_USING_WEBSERVER'):
+ RT_USING_WEBSERVER = True
+
+# rtgui options
+if rtconfig_ns.has_key('RT_USING_RTGUI'):
+ RT_USING_RTGUI = True
+
+# toolchains options
+ARCH='arm'
+CPU='lpc17xx'
+CROSS_TOOL='keil'
+
+if CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = 'D:/SourceryGCC/bin'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = 'E:/Keil'
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'axf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m3 -mthumb'
+ CFLAGS = DEVICE + ' -DRT_USING_MINILIBC'
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc17xx.map,-cref,-u,Reset_Handler -T lpc17xx_rom.ld'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ RT_USING_MINILIBC = True
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --device DARMSTM'
+ CFLAGS = DEVICE + ' --apcs=interwork'
+ AFLAGS = DEVICE
+ LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc17xx.map --scatter lpc17xx_rom.sct'
+
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+ LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+ EXEC_PATH += '/arm/bin40/'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ RT_USING_MINILIBC = False
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = ' --cpu DARMSTM --thumb'
+
+ CFLAGS = ''
+ AFLAGS = ''
+ LFLAGS = ' --config lpc17xx_flash.icf'
+
+ EXEC_PATH += '/arm/bin/'
+ RT_USING_MINILIBC = False
+ POST_ACTION = ''
diff --git a/bsp/lpc176x/template.Uv2 b/bsp/lpc176x/template.Uv2
new file mode 100644
index 0000000000000000000000000000000000000000..64223745ae7213a5d7a31a8cbaf9d9af8b1a7fe1
--- /dev/null
+++ b/bsp/lpc176x/template.Uv2
@@ -0,0 +1,98 @@
+### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+Target (RT-Thread LPC17xx), 0x0004 // Tools: 'ARM-ADS'
+
+
+
+
+Options 1,0,0 // Target 'RT-Thread LPC17xx'
+ Device (LPC1768)
+ Vendor (NXP (founded by Philips))
+ Cpu (IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x20007FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE("Cortex-M3"))
+ FlashUt ()
+ StupF ("STARTUP\NXP\startup_LPC17xx.s" ("NXP LPC17xx Startup Code"))
+ FlashDR (UL2CM3(-O463 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL040000))
+ DevID (4868)
+ Rgf (LPC17xx.H)
+ Mem ()
+ C ()
+ A ()
+ RL ()
+ OH ()
+ DBC_IFX ()
+ DBC_CMS ()
+ DBC_AMS ()
+ DBC_LMS ()
+ UseEnv=0
+ EnvBin ()
+ EnvInc ()
+ EnvLib ()
+ EnvReg (ÿNXP\)
+ OrgReg (ÿNXP\)
+ TgStat=16
+ OutDir (.\obj\)
+ OutName (project)
+ GenApp=1
+ GenLib=0
+ GenHex=0
+ Debug=1
+ Browse=1
+ LstDir (.\obj\)
+ HexSel=1
+ MG32K=0
+ TGMORE=0
+ RunUsr 0 0 <>
+ RunUsr 1 0 <>
+ BrunUsr 0 0 <>
+ BrunUsr 1 0 <>
+ CrunUsr 0 0 <>
+ CrunUsr 1 0 <>
+ SVCSID <>
+ GLFLAGS=1790
+ ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP ("Cortex-M3")
+ RVDEV ()
+ ADSTFLGA { 0,12,16,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSIRAM { 0,0,0,0,16,0,128,0,0 }
+ OCMADSIROM { 1,0,0,0,0,0,0,8,0 }
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,16,0,128,0,0,0,0,0,0,32,0,128,0,0 }
+ RV_STAVEC ()
+ ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCMISC ()
+ ADSCDEFN ()
+ ADSCUDEF ()
+ ADSCINCD ()
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSAMISC ()
+ ADSADEFN ()
+ ADSAUDEF ()
+ ADSAINCD ()
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ IncBld=1
+ AlwaysBuild=0
+ GenAsm=0
+ AsmAsm=0
+ PublicsOnly=0
+ StopCode=3
+ CustArgs ()
+ LibMods ()
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSLDTA (0x00000000)
+ ADSLDDA (0x10000000)
+ ADSLDSC ()
+ ADSLDIB ()
+ ADSLDIC ()
+ ADSLDMC ()
+ ADSLDIF ()
+ ADSLDDW ()
+ OPTDL (SARMCM3.DLL)(-MPU)(DARMP1.DLL)(-pLPC1768)(SARMCM3.DLL)(-MPU)(TARMP1.DLL)(-pLPC1768)
+ OPTDBG 48125,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
+ FLASH1 { 9,0,0,0,1,0,0,0,1,16,0,0,0,0,0,0,0,0,0,0 }
+ FLASH2 (BIN\UL2CM3.DLL)
+ FLASH3 ("" ())
+ FLASH4 ()
+EndOpt
+