From dcb0f280b491f5e0ff57373c7ec2936a1fba24e6 Mon Sep 17 00:00:00 2001 From: uestczyh222 Date: Tue, 12 Dec 2017 01:43:17 +0800 Subject: [PATCH] [BSP][fix and update]STM32F4xx-HAL fix an error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [1]修复了当选择含有CCMRAM的F4系列MCU时造成的heap初始化错误 --- bsp/stm32f4xx-HAL/.config | 19 +- bsp/stm32f4xx-HAL/Kconfig | 3 + bsp/stm32f4xx-HAL/SConstruct | 2 +- bsp/stm32f4xx-HAL/drivers/board.c | 109 ++++-- bsp/stm32f4xx-HAL/drivers/board.h | 22 +- bsp/stm32f4xx-HAL/drivers/drv_usart.c | 6 +- .../drivers/stm32f4xx_hal_conf.h | 5 +- bsp/stm32f4xx-HAL/project.uvoptx | 355 +++++++++--------- bsp/stm32f4xx-HAL/project.uvprojx | 114 +++--- bsp/stm32f4xx-HAL/rtconfig.h | 18 +- bsp/stm32f4xx-HAL/rtconfig.py | 4 +- bsp/stm32f4xx-HAL/stm32_rom.ld | 4 +- 12 files changed, 340 insertions(+), 321 deletions(-) diff --git a/bsp/stm32f4xx-HAL/.config b/bsp/stm32f4xx-HAL/.config index fec811876..09a901ddf 100644 --- a/bsp/stm32f4xx-HAL/.config +++ b/bsp/stm32f4xx-HAL/.config @@ -49,7 +49,7 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" # CONFIG_RT_USING_MODULE is not set # @@ -94,7 +94,7 @@ CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set @@ -136,6 +136,12 @@ CONFIG_RT_USING_RTC=y # # CONFIG_RT_USING_VBUS is not set +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + # # RT-Thread online packages # @@ -185,7 +191,7 @@ CONFIG_RT_USING_RTC=y # CONFIG_SOC_STM32F415RG is not set # CONFIG_SOC_STM32F415VG is not set # CONFIG_SOC_STM32F415ZG is not set -# CONFIG_SOC_STM32F407VG is not set +CONFIG_SOC_STM32F407VG=y # CONFIG_SOC_STM32F407VE is not set # CONFIG_SOC_STM32F407ZG is not set # CONFIG_SOC_STM32F407ZE is not set @@ -232,7 +238,7 @@ CONFIG_RT_USING_RTC=y # CONFIG_SOC_STM32F401CB is not set # CONFIG_SOC_STM32F401CC is not set # CONFIG_SOC_STM32F401RB is not set -CONFIG_SOC_STM32F401RC=y +# CONFIG_SOC_STM32F401RC is not set # CONFIG_SOC_STM32F401VB is not set # CONFIG_SOC_STM32F401VC is not set # CONFIG_SOC_STM32F401CD is not set @@ -311,6 +317,7 @@ CONFIG_SOC_STM32F401RC=y # CONFIG_SOC_STM32F423ZH is not set # CONFIG_RT_USING_HSI is not set CONFIG_RT_HSE_VALUE=8000000 -CONFIG_RT_USING_UART1=y -# CONFIG_RT_USING_UART2 is not set +CONFIG_RT_HSE_HCLK=168000000 +# CONFIG_RT_USING_UART1 is not set +CONFIG_RT_USING_UART2=y # CONFIG_RT_USING_UART6 is not set diff --git a/bsp/stm32f4xx-HAL/Kconfig b/bsp/stm32f4xx-HAL/Kconfig index 638f56d2b..61c4bfc9b 100644 --- a/bsp/stm32f4xx-HAL/Kconfig +++ b/bsp/stm32f4xx-HAL/Kconfig @@ -290,6 +290,9 @@ config RT_HSE_VALUE int "HSE Value" default 8000000 depends on !RT_USING_HSI +config RT_HSE_HCLK + int "System Clock Value" + default 84000000 config RT_USING_UART1 bool "Using UART1" default y diff --git a/bsp/stm32f4xx-HAL/SConstruct b/bsp/stm32f4xx-HAL/SConstruct index b4d12cc06..99c2876aa 100644 --- a/bsp/stm32f4xx-HAL/SConstruct +++ b/bsp/stm32f4xx-HAL/SConstruct @@ -15,7 +15,7 @@ except: print RTT_ROOT exit(-1) -TARGET = 'rtthread-stm32f411.' + rtconfig.TARGET_EXT +TARGET = 'rtthread-stm32f4xx.' + rtconfig.TARGET_EXT env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, diff --git a/bsp/stm32f4xx-HAL/drivers/board.c b/bsp/stm32f4xx-HAL/drivers/board.c index f6a10ba0a..4fb747e8f 100644 --- a/bsp/stm32f4xx-HAL/drivers/board.c +++ b/bsp/stm32f4xx-HAL/drivers/board.c @@ -23,55 +23,86 @@ static void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; +#ifdef RT_USING_RTC + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; +#endif /**Configure the main internal regulator output voltage */ - __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /**Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 4; - RCC_OscInitStruct.PLL.PLLN = 168; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; - RCC_OscInitStruct.PLL.PLLQ = 7; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - while(1) - {} - } + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; +#ifdef RT_USING_RTC + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; +#endif + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = (HSE_VALUE/1000000UL);//Get 1M clock + RCC_OscInitStruct.PLL.PLLN = (HCLK_VALUE/1000000UL)*2;//Get 2*HCLK_VALUE + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;//Get HCLK_VALUE + RCC_OscInitStruct.PLL.PLLQ = RCC_OscInitStruct.PLL.PLLN/48;//Get 48M Clock + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + while(1) + {} + } /**Initializes the CPU, AHB and APB busses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - { - while(1) - {} - } - - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - while(1) - {} - } + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + +#if (RT_HSE_HCLK <= 42000000UL) + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + while(1) + {} + } +#elif (RT_HSE_HCLK <= 84000000UL) + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + while(1) + {} + } +#elif (RT_HSE_HCLK <= 168000000UL) + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + while(1) + {} + } +#else + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV8; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + while(1) + {} + } +#endif +#ifdef RT_USING_RTC + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + while(1) + {} + } +#endif } /** * This is the timer interrupt service routine. diff --git a/bsp/stm32f4xx-HAL/drivers/board.h b/bsp/stm32f4xx-HAL/drivers/board.h index b639dfa88..789470934 100644 --- a/bsp/stm32f4xx-HAL/drivers/board.h +++ b/bsp/stm32f4xx-HAL/drivers/board.h @@ -177,13 +177,13 @@ defined(SOC_STM32F405VG)||\ defined(SOC_STM32F405ZG) //#define STM32F405xx -#define STM32_SRAM_SIZE 192-64 +#define STM32_SRAM_SIZE (192-64) #elif \ defined(SOC_STM32F415RG)||\ defined(SOC_STM32F415VG)||\ defined(SOC_STM32F415ZG) //#define STM32F415xx -#define STM32_SRAM_SIZE 192-64 +#define STM32_SRAM_SIZE (192-64) #elif \ defined(SOC_STM32F407VG)||\ defined(SOC_STM32F407VE)||\ @@ -192,7 +192,7 @@ defined(SOC_STM32F407IG)||\ defined(SOC_STM32F407IE) //#define STM32F407xx -#define STM32_SRAM_SIZE 192-64 +#define STM32_SRAM_SIZE (192-64) #elif \ defined(SOC_STM32F417VG)||\ defined(SOC_STM32F417VE)||\ @@ -201,7 +201,7 @@ defined(SOC_STM32F417IG)||\ defined(SOC_STM32F417IE) //#define STM32F417xx -#define STM32_SRAM_SIZE 192-64 +#define STM32_SRAM_SIZE (192-64) #elif \ defined(SOC_STM32F427VG)||\ defined(SOC_STM32F427VI)||\ @@ -210,7 +210,7 @@ defined(SOC_STM32F427IG)||\ defined(SOC_STM32F427II) //#define STM32F427xx -#define STM32_SRAM_SIZE 256-64 +#define STM32_SRAM_SIZE (256-64) #elif \ defined(SOC_STM32F437VG)||\ defined(SOC_STM32F437VI)||\ @@ -219,7 +219,7 @@ defined(SOC_STM32F437IG)||\ defined(SOC_STM32F437II) //#define STM32F437xx -#define STM32_SRAM_SIZE 256-64 +#define STM32_SRAM_SIZE (256-64) #elif \ defined(SOC_STM32F429VG)||\ defined(SOC_STM32F429VI)||\ @@ -232,7 +232,7 @@ defined(SOC_STM32F429IG)||\ defined(SOC_STM32F429II) //#define STM32F429xx -#define STM32_SRAM_SIZE 256-64 +#define STM32_SRAM_SIZE (256-64) #elif \ defined(SOC_STM32F439VG)||\ defined(SOC_STM32F439VI)||\ @@ -245,7 +245,7 @@ defined(SOC_STM32F439IG)||\ defined(SOC_STM32F439II) //#define STM32F439xx -#define STM32_SRAM_SIZE 256-64 +#define STM32_SRAM_SIZE (256-64) #elif \ defined(SOC_STM32F401CB)||\ defined(SOC_STM32F401CC)||\ @@ -313,7 +313,7 @@ defined(SOC_STM32F469BE)||\ defined(SOC_STM32F469NE) //#define STM32F469xx -#define STM32_SRAM_SIZE 384-64 +#define STM32_SRAM_SIZE (384-64) #elif \ defined(SOC_STM32F479AI)||\ defined(SOC_STM32F479II)||\ @@ -324,7 +324,7 @@ defined(SOC_STM32F479BG)||\ defined(SOC_STM32F479NG) //#define STM32F479xx -#define STM32_SRAM_SIZE 384-64 +#define STM32_SRAM_SIZE (384-64) #elif \ defined(SOC_STM32F412CEU)||\ defined(SOC_STM32F412CGU) @@ -385,7 +385,7 @@ extern int Image$$RW_IRAM1$$ZI$$Limit; extern int __bss_end; #define HEAP_BEGIN ((void *)&__bss_end) #endif -#define HEAP_END (0x20000000 + STM32_SRAM_SIZE*1024) +#define HEAP_END STM32_SRAM_END #endif extern void rt_hw_board_init(void); diff --git a/bsp/stm32f4xx-HAL/drivers/drv_usart.c b/bsp/stm32f4xx-HAL/drivers/drv_usart.c index dd239e357..2f45d5bb4 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_usart.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_usart.c @@ -260,7 +260,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { /* USART1 clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX @@ -276,7 +276,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX @@ -292,7 +292,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { /* USART6 clock enable */ __HAL_RCC_USART6_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); /**USART6 GPIO Configuration PC6 ------> USART6_TX PC7 ------> USART6_RX diff --git a/bsp/stm32f4xx-HAL/drivers/stm32f4xx_hal_conf.h b/bsp/stm32f4xx-HAL/drivers/stm32f4xx_hal_conf.h index 4c4b03096..e8646b0eb 100644 --- a/bsp/stm32f4xx-HAL/drivers/stm32f4xx_hal_conf.h +++ b/bsp/stm32f4xx-HAL/drivers/stm32f4xx_hal_conf.h @@ -103,8 +103,9 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (RT_USING_HSI) - #define HSE_VALUE ((unsigned int)RT_HSE_VALUE) + #define HSE_VALUE ((unsigned long)RT_HSE_VALUE) #endif + #define HCLK_VALUE ((unsigned long)RT_HSE_HCLK) #if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -158,7 +159,7 @@ * @brief This is the HAL system configuration section */ #define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY ((uint32_t)15U) /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U diff --git a/bsp/stm32f4xx-HAL/project.uvoptx b/bsp/stm32f4xx-HAL/project.uvoptx index 164e82c34..232a4a8e2 100644 --- a/bsp/stm32f4xx-HAL/project.uvoptx +++ b/bsp/stm32f4xx-HAL/project.uvoptx @@ -8,7 +8,7 @@ *.c *.s*; *.src; *.a* - *.obj; *.o + *.obj *.lib *.txt; *.h; *.inc *.plm @@ -101,7 +101,7 @@ 0 0 1 - 5 + 3 @@ -112,18 +112,23 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + Segger\JL2CM3.dll 0 - ST-LINKIII-KEIL_SWO - -U0664FF545449677267026033 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_256.FLM -FS08000000 -FL040000 -FP0($$Device:STM32F401RCTx$CMSIS\Flash\STM32F4xx_256.FLM) + JL2CM3 + -U775206746 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM) 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_256 -FL040000 -FS08000000 -FP0($$Device:STM32F401RCTx$CMSIS\Flash\STM32F4xx_256.FLM) + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + -U0664FF545449677267026033 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_256.FLM -FS08000000 -FL040000 -FP0($$Device:STM32F401RCTx$CMSIS\Flash\STM32F4xx_256.FLM) @@ -252,18 +257,6 @@ 0 0 - - 2 - 6 - 1 - 0 - 0 - 0 - drivers\drv_rtc.c - drv_rtc.c - 0 - 0 - @@ -274,7 +267,7 @@ 0 3 - 7 + 6 1 0 0 @@ -286,13 +279,13 @@ 3 - 8 + 7 2 0 0 0 - Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f401xc.s - startup_stm32f401xc.s + Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + startup_stm32f407xx.s 0 0 @@ -306,7 +299,7 @@ 0 4 - 9 + 8 1 0 0 @@ -318,7 +311,7 @@ 4 - 10 + 9 1 0 0 @@ -330,7 +323,7 @@ 4 - 11 + 10 1 0 0 @@ -342,7 +335,7 @@ 4 - 12 + 11 1 0 0 @@ -354,7 +347,7 @@ 4 - 13 + 12 1 0 0 @@ -366,7 +359,7 @@ 4 - 14 + 13 1 0 0 @@ -378,7 +371,7 @@ 4 - 15 + 14 1 0 0 @@ -390,7 +383,7 @@ 4 - 16 + 15 1 0 0 @@ -402,7 +395,7 @@ 4 - 17 + 16 1 0 0 @@ -414,7 +407,7 @@ 4 - 18 + 17 1 0 0 @@ -426,7 +419,7 @@ 4 - 19 + 18 1 0 0 @@ -438,7 +431,7 @@ 4 - 20 + 19 1 0 0 @@ -450,7 +443,7 @@ 4 - 21 + 20 1 0 0 @@ -462,7 +455,7 @@ 4 - 22 + 21 1 0 0 @@ -474,7 +467,7 @@ 4 - 23 + 22 1 0 0 @@ -486,7 +479,7 @@ 4 - 24 + 23 1 0 0 @@ -498,7 +491,7 @@ 4 - 25 + 24 1 0 0 @@ -510,7 +503,7 @@ 4 - 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53 + 52 1 0 0 @@ -846,7 +839,7 @@ 4 - 54 + 53 1 0 0 @@ -858,7 +851,7 @@ 4 - 55 + 54 1 0 0 @@ -870,7 +863,7 @@ 4 - 56 + 55 1 0 0 @@ -882,7 +875,7 @@ 4 - 57 + 56 1 0 0 @@ -894,7 +887,7 @@ 4 - 58 + 57 1 0 0 @@ -906,7 +899,7 @@ 4 - 59 + 58 1 0 0 @@ -918,7 +911,7 @@ 4 - 60 + 59 1 0 0 @@ -930,7 +923,7 @@ 4 - 61 + 60 1 0 0 @@ -942,7 +935,7 @@ 4 - 62 + 61 1 0 0 @@ -954,7 +947,7 @@ 4 - 63 + 62 1 0 0 @@ -966,7 +959,7 @@ 4 - 64 + 63 1 0 0 @@ -978,7 +971,7 @@ 4 - 65 + 64 1 0 0 @@ -990,7 +983,7 @@ 4 - 66 + 65 1 0 0 @@ -1002,7 +995,7 @@ 4 - 67 + 66 1 0 0 @@ -1014,7 +1007,7 @@ 4 - 68 + 67 1 0 0 @@ -1026,7 +1019,7 @@ 4 - 69 + 68 1 0 0 @@ -1038,7 +1031,7 @@ 4 - 70 + 69 1 0 0 @@ -1050,7 +1043,7 @@ 4 - 71 + 70 1 0 0 @@ -1062,7 +1055,7 @@ 4 - 72 + 71 1 0 0 @@ -1074,7 +1067,7 @@ 4 - 73 + 72 1 0 0 @@ -1086,7 +1079,7 @@ 4 - 74 + 73 1 0 0 @@ -1098,7 +1091,7 @@ 4 - 75 + 74 1 0 0 @@ -1110,7 +1103,7 @@ 4 - 76 + 75 1 0 0 @@ -1122,7 +1115,7 @@ 4 - 77 + 76 1 0 0 @@ -1134,7 +1127,7 @@ 4 - 78 + 77 1 0 0 @@ -1146,7 +1139,7 @@ 4 - 79 + 78 1 0 0 @@ -1158,7 +1151,7 @@ 4 - 80 + 79 1 0 0 @@ -1170,7 +1163,7 @@ 4 - 81 + 80 1 0 0 @@ -1182,7 +1175,7 @@ 4 - 82 + 81 1 0 0 @@ -1194,7 +1187,7 @@ 4 - 83 + 82 1 0 0 @@ -1206,7 +1199,7 @@ 4 - 84 + 83 1 0 0 @@ -1218,7 +1211,7 @@ 4 - 85 + 84 1 0 0 @@ -1230,7 +1223,7 @@ 4 - 86 + 85 1 0 0 @@ -1242,7 +1235,7 @@ 4 - 87 + 86 1 0 0 @@ -1254,7 +1247,7 @@ 4 - 88 + 87 1 0 0 @@ -1266,7 +1259,7 @@ 4 - 89 + 88 1 0 0 @@ -1278,7 +1271,7 @@ 4 - 90 + 89 1 0 0 @@ -1290,7 +1283,7 @@ 4 - 91 + 90 1 0 0 @@ -1302,7 +1295,7 @@ 4 - 92 + 91 1 0 0 @@ -1314,7 +1307,7 @@ 4 - 93 + 92 1 0 0 @@ -1334,180 +1327,180 @@ 0 5 - 94 + 93 1 0 0 0 - ..\..\src\clock.c + ..\rt-thread\src\clock.c clock.c 0 0 5 - 95 + 94 1 0 0 0 - ..\..\src\components.c + ..\rt-thread\src\components.c components.c 0 0 5 - 96 + 95 1 0 0 0 - ..\..\src\device.c + ..\rt-thread\src\device.c device.c 0 0 5 - 97 + 96 1 0 0 0 - ..\..\src\idle.c + ..\rt-thread\src\idle.c idle.c 0 0 5 - 98 + 97 1 0 0 0 - ..\..\src\ipc.c + ..\rt-thread\src\ipc.c ipc.c 0 0 5 - 99 + 98 1 0 0 0 - ..\..\src\irq.c + ..\rt-thread\src\irq.c irq.c 0 0 5 - 100 + 99 1 0 0 0 - ..\..\src\kservice.c + ..\rt-thread\src\kservice.c kservice.c 0 0 5 - 101 + 100 1 0 0 0 - ..\..\src\mem.c + ..\rt-thread\src\mem.c mem.c 0 0 5 - 102 + 101 1 0 0 0 - ..\..\src\memheap.c + ..\rt-thread\src\memheap.c memheap.c 0 0 5 - 103 + 102 1 0 0 0 - ..\..\src\mempool.c + ..\rt-thread\src\mempool.c mempool.c 0 0 5 - 104 + 103 1 0 0 0 - ..\..\src\object.c + ..\rt-thread\src\object.c object.c 0 0 5 - 105 + 104 1 0 0 0 - ..\..\src\scheduler.c + ..\rt-thread\src\scheduler.c scheduler.c 0 0 5 - 106 + 105 1 0 0 0 - ..\..\src\signal.c + ..\rt-thread\src\signal.c signal.c 0 0 5 - 107 + 106 1 0 0 0 - ..\..\src\thread.c + ..\rt-thread\src\thread.c thread.c 0 0 5 - 108 + 107 1 0 0 0 - ..\..\src\timer.c + ..\rt-thread\src\timer.c timer.c 0 0 @@ -1522,60 +1515,60 @@ 0 6 - 109 + 108 1 0 0 0 - ..\..\libcpu\arm\cortex-m4\cpuport.c + ..\rt-thread\libcpu\arm\cortex-m4\cpuport.c cpuport.c 0 0 6 - 110 + 109 2 0 0 0 - ..\..\libcpu\arm\cortex-m4\context_rvds.S + ..\rt-thread\libcpu\arm\cortex-m4\context_rvds.S context_rvds.S 0 0 6 - 111 + 110 1 0 0 0 - ..\..\libcpu\arm\common\backtrace.c + ..\rt-thread\libcpu\arm\common\backtrace.c backtrace.c 0 0 6 - 112 + 111 1 0 0 0 - ..\..\libcpu\arm\common\div0.c + ..\rt-thread\libcpu\arm\common\div0.c div0.c 0 0 6 - 113 + 112 1 0 0 0 - ..\..\libcpu\arm\common\showmem.c + ..\rt-thread\libcpu\arm\common\showmem.c showmem.c 0 0 @@ -1590,108 +1583,96 @@ 0 7 - 114 + 113 1 0 0 0 - ..\..\components\drivers\misc\pin.c + ..\rt-thread\components\drivers\misc\pin.c pin.c 0 0 7 - 115 - 1 - 0 - 0 - 0 - ..\..\components\drivers\rtc\rtc.c - rtc.c - 0 - 0 - - - 7 - 116 + 114 1 0 0 0 - ..\..\components\drivers\serial\serial.c + ..\rt-thread\components\drivers\serial\serial.c serial.c 0 0 7 - 117 + 115 1 0 0 0 - ..\..\components\drivers\src\completion.c + ..\rt-thread\components\drivers\src\completion.c completion.c 0 0 7 - 118 + 116 1 0 0 0 - ..\..\components\drivers\src\dataqueue.c + ..\rt-thread\components\drivers\src\dataqueue.c dataqueue.c 0 0 7 - 119 + 117 1 0 0 0 - ..\..\components\drivers\src\pipe.c + ..\rt-thread\components\drivers\src\pipe.c pipe.c 0 0 7 - 120 + 118 1 0 0 0 - ..\..\components\drivers\src\ringbuffer.c + ..\rt-thread\components\drivers\src\ringbuffer.c ringbuffer.c 0 0 7 - 121 + 119 1 0 0 0 - ..\..\components\drivers\src\waitqueue.c + ..\rt-thread\components\drivers\src\waitqueue.c waitqueue.c 0 0 7 - 122 + 120 1 0 0 0 - ..\..\components\drivers\src\workqueue.c + ..\rt-thread\components\drivers\src\workqueue.c workqueue.c 0 0 @@ -1706,72 +1687,72 @@ 0 8 - 123 + 121 1 0 0 0 - ..\..\components\finsh\shell.c + ..\rt-thread\components\finsh\shell.c shell.c 0 0 8 - 124 + 122 1 0 0 0 - ..\..\components\finsh\symbol.c + ..\rt-thread\components\finsh\symbol.c symbol.c 0 0 8 - 125 + 123 1 0 0 0 - ..\..\components\finsh\cmd.c + ..\rt-thread\components\finsh\cmd.c cmd.c 0 0 8 - 126 + 124 1 0 0 0 - ..\..\components\finsh\msh.c + ..\rt-thread\components\finsh\msh.c msh.c 0 0 8 - 127 + 125 1 0 0 0 - ..\..\components\finsh\msh_cmd.c + ..\rt-thread\components\finsh\msh_cmd.c msh_cmd.c 0 0 8 - 128 + 126 1 0 0 0 - ..\..\components\finsh\msh_file.c + ..\rt-thread\components\finsh\msh_file.c msh_file.c 0 0 diff --git a/bsp/stm32f4xx-HAL/project.uvprojx b/bsp/stm32f4xx-HAL/project.uvprojx index 20a5c0b50..dcb17df0c 100644 --- a/bsp/stm32f4xx-HAL/project.uvprojx +++ b/bsp/stm32f4xx-HAL/project.uvprojx @@ -14,16 +14,16 @@ 0 - STM32F401RCTx + STM32F407VGTx STMicroelectronics Keil.STM32F4xx_DFP.2.11.0 http://www.keil.com/pack - IRAM(0x20000000,0x10000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_256 -FS08000000 -FL040000 -FP0($$Device:STM32F401RCTx$CMSIS\Flash\STM32F4xx_256.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) 0 - $$Device:STM32F401RCTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + $$Device:STM32F407VGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h @@ -33,7 +33,7 @@ - $$Device:STM32F401RCTx$CMSIS\SVD\STM32F401x.svd + $$Device:STM32F407VGTx$CMSIS\SVD\STM32F40x.svd 0 0 @@ -138,7 +138,7 @@ 1 BIN\UL2CM3.DLL - "" () + @@ -184,7 +184,7 @@ 0 0 2 - 0 + 1 0 8 0 @@ -192,7 +192,7 @@ 0 0 3 - 3 + 4 0 0 0 @@ -244,12 +244,12 @@ 0 0x20000000 - 0x10000 + 0x20000 1 0x8000000 - 0x40000 + 0x100000 0 @@ -274,7 +274,7 @@ 1 0x8000000 - 0x40000 + 0x100000 1 @@ -299,12 +299,12 @@ 0 0x20000000 - 0x10000 + 0x20000 0 - 0x0 - 0x0 + 0x10000000 + 0x10000 @@ -334,9 +334,9 @@ 0 - USE_HAL_DRIVER, STM32F401xC + USE_HAL_DRIVER, STM32F407xx - applications;.;drivers;Libraries\CMSIS\Device\ST\STM32F4xx\Include;Libraries\CMSIS\Include;Libraries\STM32F4xx_HAL_Driver\Inc;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh + applications;.;drivers;Libraries\CMSIS\Device\ST\STM32F4xx\Include;Libraries\CMSIS\Include;Libraries\STM32F4xx_HAL_Driver\Inc;..\rt-thread\include;..\rt-thread\libcpu\arm\cortex-m4;..\rt-thread\libcpu\arm\common;..\rt-thread\components\drivers\include;..\rt-thread\components\drivers\include;..\rt-thread\components\drivers\include;..\rt-thread\components\finsh @@ -410,11 +410,6 @@ 1 drivers\drv_usart.c - - drv_rtc.c - 1 - drivers\drv_rtc.c - @@ -426,9 +421,9 @@ Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c - startup_stm32f401xc.s + startup_stm32f407xx.s 2 - Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f401xc.s + Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s @@ -868,77 +863,77 @@ clock.c 1 - ..\..\src\clock.c + ..\rt-thread\src\clock.c components.c 1 - ..\..\src\components.c + ..\rt-thread\src\components.c device.c 1 - ..\..\src\device.c + ..\rt-thread\src\device.c idle.c 1 - ..\..\src\idle.c + ..\rt-thread\src\idle.c ipc.c 1 - ..\..\src\ipc.c + ..\rt-thread\src\ipc.c irq.c 1 - ..\..\src\irq.c + ..\rt-thread\src\irq.c kservice.c 1 - ..\..\src\kservice.c + ..\rt-thread\src\kservice.c mem.c 1 - ..\..\src\mem.c + ..\rt-thread\src\mem.c memheap.c 1 - ..\..\src\memheap.c + ..\rt-thread\src\memheap.c mempool.c 1 - ..\..\src\mempool.c + ..\rt-thread\src\mempool.c object.c 1 - ..\..\src\object.c + ..\rt-thread\src\object.c scheduler.c 1 - ..\..\src\scheduler.c + ..\rt-thread\src\scheduler.c signal.c 1 - ..\..\src\signal.c + ..\rt-thread\src\signal.c thread.c 1 - ..\..\src\thread.c + ..\rt-thread\src\thread.c timer.c 1 - ..\..\src\timer.c + ..\rt-thread\src\timer.c @@ -948,27 +943,27 @@ cpuport.c 1 - ..\..\libcpu\arm\cortex-m4\cpuport.c + ..\rt-thread\libcpu\arm\cortex-m4\cpuport.c context_rvds.S 2 - ..\..\libcpu\arm\cortex-m4\context_rvds.S + ..\rt-thread\libcpu\arm\cortex-m4\context_rvds.S backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ..\rt-thread\libcpu\arm\common\backtrace.c div0.c 1 - ..\..\libcpu\arm\common\div0.c + ..\rt-thread\libcpu\arm\common\div0.c showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ..\rt-thread\libcpu\arm\common\showmem.c @@ -978,47 +973,42 @@ pin.c 1 - ..\..\components\drivers\misc\pin.c - - - rtc.c - 1 - ..\..\components\drivers\rtc\rtc.c + ..\rt-thread\components\drivers\misc\pin.c serial.c 1 - ..\..\components\drivers\serial\serial.c + ..\rt-thread\components\drivers\serial\serial.c completion.c 1 - ..\..\components\drivers\src\completion.c + ..\rt-thread\components\drivers\src\completion.c dataqueue.c 1 - ..\..\components\drivers\src\dataqueue.c + ..\rt-thread\components\drivers\src\dataqueue.c pipe.c 1 - ..\..\components\drivers\src\pipe.c + ..\rt-thread\components\drivers\src\pipe.c ringbuffer.c 1 - ..\..\components\drivers\src\ringbuffer.c + ..\rt-thread\components\drivers\src\ringbuffer.c waitqueue.c 1 - ..\..\components\drivers\src\waitqueue.c + ..\rt-thread\components\drivers\src\waitqueue.c workqueue.c 1 - ..\..\components\drivers\src\workqueue.c + ..\rt-thread\components\drivers\src\workqueue.c @@ -1028,32 +1018,32 @@ shell.c 1 - ..\..\components\finsh\shell.c + ..\rt-thread\components\finsh\shell.c symbol.c 1 - ..\..\components\finsh\symbol.c + ..\rt-thread\components\finsh\symbol.c cmd.c 1 - ..\..\components\finsh\cmd.c + ..\rt-thread\components\finsh\cmd.c msh.c 1 - ..\..\components\finsh\msh.c + ..\rt-thread\components\finsh\msh.c msh_cmd.c 1 - ..\..\components\finsh\msh_cmd.c + ..\rt-thread\components\finsh\msh_cmd.c msh_file.c 1 - ..\..\components\finsh\msh_file.c + ..\rt-thread\components\finsh\msh_file.c diff --git a/bsp/stm32f4xx-HAL/rtconfig.h b/bsp/stm32f4xx-HAL/rtconfig.h index 109f90a7c..ac95bd6b1 100644 --- a/bsp/stm32f4xx-HAL/rtconfig.h +++ b/bsp/stm32f4xx-HAL/rtconfig.h @@ -46,7 +46,7 @@ /* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_CONSOLE_DEVICE_NAME "uart2" /* RT_USING_MODULE is not set */ /* RT-Thread Components */ @@ -86,7 +86,7 @@ #define RT_USING_PIN /* RT_USING_MTD_NOR is not set */ /* RT_USING_MTD_NAND is not set */ -#define RT_USING_RTC +/* RT_USING_RTC is not set */ /* RT_USING_SDIO is not set */ /* RT_USING_SPI is not set */ /* RT_USING_WDT is not set */ @@ -120,6 +120,11 @@ /* RT_USING_VBUS is not set */ +/* Utilities */ + +/* RT_USING_LOGTRACE is not set */ +/* RT_USING_RYM is not set */ + /* RT-Thread online packages */ /* system packages */ @@ -159,7 +164,7 @@ /* SOC_STM32F415RG is not set */ /* SOC_STM32F415VG is not set */ /* SOC_STM32F415ZG is not set */ -/* SOC_STM32F407VG is not set */ +#define SOC_STM32F407VG /* SOC_STM32F407VE is not set */ /* SOC_STM32F407ZG is not set */ /* SOC_STM32F407ZE is not set */ @@ -206,7 +211,7 @@ /* SOC_STM32F401CB is not set */ /* SOC_STM32F401CC is not set */ /* SOC_STM32F401RB is not set */ -#define SOC_STM32F401RC +/* SOC_STM32F401RC is not set */ /* SOC_STM32F401VB is not set */ /* SOC_STM32F401VC is not set */ /* SOC_STM32F401CD is not set */ @@ -285,8 +290,9 @@ /* SOC_STM32F423ZH is not set */ /* RT_USING_HSI is not set */ #define RT_HSE_VALUE 8000000 -#define RT_USING_UART1 -/* RT_USING_UART2 is not set */ +#define RT_HSE_HCLK 168000000 +/* RT_USING_UART1 is not set */ +#define RT_USING_UART2 /* RT_USING_UART6 is not set */ #endif diff --git a/bsp/stm32f4xx-HAL/rtconfig.py b/bsp/stm32f4xx-HAL/rtconfig.py index 566ffeee5..39e739f83 100644 --- a/bsp/stm32f4xx-HAL/rtconfig.py +++ b/bsp/stm32f4xx-HAL/rtconfig.py @@ -5,7 +5,7 @@ import os # toolchains options ARCH='arm' CPU='cortex-m4' -CROSS_TOOL='keil' +CROSS_TOOL='gcc' if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') @@ -43,7 +43,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections' + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -std=c99 -Dgcc' # -D' + PART_TYPE AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld' diff --git a/bsp/stm32f4xx-HAL/stm32_rom.ld b/bsp/stm32f4xx-HAL/stm32_rom.ld index 5d4b55271..aa9c9b2af 100644 --- a/bsp/stm32f4xx-HAL/stm32_rom.ld +++ b/bsp/stm32f4xx-HAL/stm32_rom.ld @@ -6,8 +6,8 @@ /* Program Entry, set to mark it as "used" and avoid gc */ MEMORY { - CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 1024KB flash */ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 64k /* 128K sram */ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ } ENTRY(Reset_Handler) _system_stack_size = 0x200; -- GitLab