update jz47xx branch code.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@902 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/jz47xx/application.c

@@ -18,8 +18,33 @@
 /*@{*/
 #include <rtthread.h>
 
+#include <jz4755.h>
+#include <mipsregs.h>
+
+static struct rt_thread thread1;
+static rt_uint8_t thread1_stack[1024];
+
+void thread_entry(void* parameter)
+{
+	while (1)
+	{
+		rt_kprintf("IPR: 0x%08x, SR : 0x%08x, CAUSE: 0x%08x\n", INTC_IPR, read_c0_status(), read_c0_cause());
+
+		rt_thread_delay(100);
+	}
+}
+
 int rt_application_init()
 {
+	rt_err_t result;
+
+	result = rt_thread_init(&thread1, "t1",
+		thread_entry, RT_NULL,
+		&thread1_stack[0], sizeof(thread1_stack),
+		200, 10);
+	if (result == RT_EOK)
+		rt_thread_startup(&thread1);
+
 	return 0;
 }
 

bsp/jz47xx/board.c

@@ -17,6 +17,7 @@
 
 #include "board.h"
 #include "uart.h"
+#include <jz4755.h>
 
 /**
  * @addtogroup JZ47xx
@@ -28,13 +29,68 @@
  */
 void rt_hw_timer_handler()
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
-
+	/* increase a OS tick */
 	rt_tick_increase();
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+	/* clear flag */
+	TCU_TFCR = TCU_TFCR_OSTFLAG;
+}
+
+/**
+ * This function will initial OS timer
+ */
+void rt_hw_timer_init()
+{
+	rt_uint32_t val;
+
+	/* disable TCU clock */
+	CPM_CLKGR &= ~CPM_CLKGR_TCU;
+	TCU_TECR = TCU_TECR_OSTCL;
+
+	/* set */
+	OST_DR = RT_TICK_PER_SECOND * 0xcffff;
+	/* clear counter */
+	OST_CNT = 0;
+
+#if 0
+	switch (RTC_DIV)
+	{
+	case 1: 
+		val = OST_TCSR_PRESCALE1; 
+		break;
+	case 4: 
+		val = OST_TCSR_PRESCALE4; 
+		break;
+	case 16: 
+		val = OST_TCSR_PRESCALE16; 
+		break;
+	case 64: 
+		val = OST_TCSR_PRESCALE64; 
+		break;
+	case 256: 
+		val = OST_TCSR_PRESCALE256; 
+		break;
+	case 1024: 
+		val = OST_TCSR_PRESCALE1024; 
+		break;
+	default: 
+		val = OST_TCSR_PRESCALE4; 
+		break;
+	}
+#endif
+
+#ifdef RTC_SRC_EXTAL
+	OST_CSR = (val | OST_TCSR_EXT_EN);
+#else
+	OST_CSR = (val | OST_TCSR_PCLK_EN);
+#endif
+
+	TCU_TFCR = TCU_TFCR_OSTFLAG;
+	TCU_TMCR = TCU_TMCR_OSTMCL;
+	TCU_TESR = TCU_TESR_OSTST;
+
+	rt_hw_interrupt_install(IRQ_TCU0, rt_hw_timer_handler, RT_NULL);
+	rt_hw_interrupt_umask  (IRQ_TCU0);
 }
 
 /**
@@ -51,5 +107,8 @@ void rt_hw_board_init()
 	/* set console device */
 	rt_console_set_device("uart");
 #endif
+
+	/* init operating system timer */
+	rt_hw_timer_init();
 }
 /*@}*/

bsp/jz47xx/rtconfig.py

@@ -84,4 +84,4 @@ else:
 RT_USING_MINILIBC = True
 DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
 COPY_ACTION = 'copy rtthread.bin usbboot\n'
-POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + DUMP_ACTION + COPY_ACTION
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + COPY_ACTION

bsp/jz47xx/startup.c

@@ -14,6 +14,7 @@
 
 #include <rthw.h>
 #include <rtthread.h>
+#include <cache.h>
 
 #include "board.h"
 
@@ -27,22 +28,13 @@ extern unsigned char __bss_end;
 
 extern int rt_application_init(void);
 
-void dump_memory(rt_uint8_t* ptr, rt_size_t size)
-{
-	rt_size_t index;
-
-	for (index = 0; index < size; index ++)
-	{
-		rt_kprintf("%02x ", ptr[index] & 0xff);
-		if ((index + 1) % 16 == 0) rt_kprintf("\n");
-	}
-}
-
 /**
  * This function will startup RT-Thread RTOS.
  */
 void rtthread_startup(void)
 {
+	/* init cache */
+	rt_hw_cache_init();
 	/* init hardware interrupt */
 	rt_hw_interrupt_init();
 
@@ -50,8 +42,6 @@ void rtthread_startup(void)
 	rt_hw_board_init();
 	rt_show_version();
 
-	dump_memory((rt_uint8_t*)0x80000200, 32);
-
 	/* init tick */
 	rt_system_tick_init();
 

bsp/jz47xx/uart.c

 #include <rthw.h>
 #include <rtthread.h>
-#include <jz47xx.h>
+
+#include <jz4755.h>
 
 /**
  * @addtogroup Jz47xx

libcpu/mips/jz47xx/cache.c

+#include "jz47xx.h"
+#include "cache.h"
+
+#define CACHE_SIZE		16*1024
+#define CACHE_LINE_SIZE		32
+#define KSEG0			0x80000000
+
+
+#define K0_TO_K1()				\
+do {						\
+	unsigned long __k0_addr;		\
+						\
+	__asm__ __volatile__(			\
+	"la %0, 1f\n\t"				\
+	"or	%0, %0, %1\n\t"			\
+	"jr	%0\n\t"				\
+	"nop\n\t"				\
+	"1: nop\n"				\
+	: "=&r"(__k0_addr)			\
+	: "r" (0x20000000) );			\
+} while(0)
+
+#define K1_TO_K0()				\
+do {						\
+	unsigned long __k0_addr;		\
+	__asm__ __volatile__(			\
+	"nop;nop;nop;nop;nop;nop;nop\n\t"	\
+	"la %0, 1f\n\t"				\
+	"jr	%0\n\t"				\
+	"nop\n\t"				\
+	"1:	nop\n"				\
+	: "=&r" (__k0_addr));			\
+} while (0)
+
+#define INVALIDATE_BTB()			\
+do {						\
+	unsigned long tmp;			\
+	__asm__ __volatile__(			\
+	".set mips32\n\t"			\
+	"mfc0 %0, $16, 7\n\t"			\
+	"nop\n\t"				\
+	"ori %0, 2\n\t"				\
+	"mtc0 %0, $16, 7\n\t"			\
+	"nop\n\t"				\
+	".set mips2\n\t"			\
+	: "=&r" (tmp));				\
+} while (0)
+
+#define SYNC_WB() __asm__ __volatile__ ("sync")
+
+#define cache_op(op,addr)						\
+	__asm__ __volatile__(						\
+	"	.set	noreorder		\n"			\
+	"	.set	mips32\n\t		\n"			\
+	"	cache	%0, %1			\n"			\
+	"	.set	mips0			\n"			\
+	"	.set	reorder"					\
+	:										\
+	: "i" (op), "m" (*(unsigned char *)(addr)))
+
+void __icache_invalidate_all(void)
+{
+	unsigned int i;
+
+	K0_TO_K1();
+
+	asm volatile (".set noreorder\n"
+		      ".set mips32\n\t"
+		      "mtc0\t$0,$28\n\t"
+		      "mtc0\t$0,$29\n"
+		      ".set mips0\n"
+		      ".set reorder\n");
+	for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
+		cache_op(Index_Store_Tag_I, i);
+
+	K1_TO_K0();
+
+	INVALIDATE_BTB();
+}
+
+void __dcache_writeback_all(void)
+{
+	unsigned int i;
+	for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
+		cache_op(Index_Writeback_Inv_D, i);
+	SYNC_WB();
+}
+
+void rt_hw_cache_init(void)
+{
+	__dcache_writeback_all();
+	__icache_invalidate_all();
+}

libcpu/mips/jz47xx/cache.h

+#ifndef	__CACHE_H__
+#define	__CACHE_H__
+
+/*
+ * Cache Operations
+ */
+#define Index_Invalidate_I      0x00
+#define Index_Writeback_Inv_D   0x01
+#define Index_Invalidate_SI     0x02
+#define Index_Writeback_Inv_SD  0x03
+#define Index_Load_Tag_I		0x04
+#define Index_Load_Tag_D		0x05
+#define Index_Load_Tag_SI		0x06
+#define Index_Load_Tag_SD		0x07
+#define Index_Store_Tag_I		0x08
+#define Index_Store_Tag_D		0x09
+#define Index_Store_Tag_SI		0x0A
+#define Index_Store_Tag_SD		0x0B
+#define Create_Dirty_Excl_D		0x0d
+#define Create_Dirty_Excl_SD	0x0f
+#define Hit_Invalidate_I		0x10
+#define Hit_Invalidate_D		0x11
+#define Hit_Invalidate_SI		0x12
+#define Hit_Invalidate_SD		0x13
+#define Fill					0x14
+#define Hit_Writeback_Inv_D		0x15
+/* 0x16 is unused */
+#define Hit_Writeback_Inv_SD	0x17
+#define Hit_Writeback_I			0x18
+#define Hit_Writeback_D			0x19
+/* 0x1a is unused */
+#define Hit_Writeback_SD		0x1b
+/* 0x1c is unused */
+/* 0x1e is unused */
+#define Hit_Set_Virtual_SI		0x1e
+#define Hit_Set_Virtual_SD		0x1f
+
+void rt_hw_cache_init(void);
+
+#endif

libcpu/mips/jz47xx/context_gcc.S

@@ -3,6 +3,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
+ * 2010-09-11     bernard      port to Jz4755
  */
 #include "../common/mips.inc"
 #include "../common/stackframe.h"
@@ -79,6 +80,7 @@ _reswitch:
     jr      ra
     nop
 
+	.globl system_dump
 
 /*
  * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
@@ -97,13 +99,11 @@ mips_irq_handle:
     beqz    t0, spurious_interrupt
     nop
 
-    /* switch to kernel stack */
+	/* let k0 keep the current context sp */
     move    k0, sp 
+    /* switch to kernel stack */
     li      sp, SYSTEM_STACK
-    addiu   sp, sp, -4
-    sw      k0, 0(sp)
 
-1:
     jal     rt_interrupt_enter
     nop
     jal     rt_interrupt_dispatch
@@ -112,8 +112,6 @@ mips_irq_handle:
     nop
 
     /* switch sp back to thread's context */
-    lw      k0, 0(sp)
-    nop
     move    sp, k0
 
     /*
@@ -124,15 +122,17 @@ mips_irq_handle:
     lw      k1, 0(k0)
     beqz    k1, spurious_interrupt
     nop
+    sw      zero, 0(k0)                     /* clear flag */
+	nop
 
     /*
      * switch to the new thread
      */
-    sw      zero, 0(k0)                     /* clear flag */
     la      k0, rt_interrupt_from_thread
     lw      k1, 0(k0)
     nop
     sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
+
     la      k0, rt_interrupt_to_thread
     lw      k1, 0(k0)
     nop

libcpu/mips/jz47xx/cpu.c

@@ -10,9 +10,26 @@
  * Change Logs:
  * Date           Author       Notes
  * 2010-07-09     Bernard      first version
+ * 2010-09-11     Bernard      add CPU reset implementation
  */
 #include <rtthread.h>
+#include <jz4755.h>
 
+/* Watchdog definitions */
+#define	WDT_CLK_PRESCALE_CLK1			( 0x0 << 3)
+#define	WDT_CLK_PRESCALE_CLK4			( 0x1 << 3)
+#define	WDT_CLK_PRESCALE_CLK16			( 0x2 << 3)
+#define	WDT_CLK_PRESCALE_CLK64			( 0x3 << 3)
+#define	WDT_CLK_PRESCALE_CLK256			( 0x4 << 3)
+#define	WDT_CLK_PRESCALE_CLK1024		( 0x5 << 3)
+#define	WDT_CLK_PRESCALE_MASK			( 0x3F << 3)
+
+#define	WDT_CLK_EXTAL					( 0x1 << 2)
+#define	WDT_CLK_RTC						( 0x1 << 1)
+#define	WDT_CLK_PCLK					( 0x1 << 0)
+#define	WDT_CLK_MASK					( 7 )
+
+#define	WDT_ENABLE			( 1 << 0 )
 
 /**
  * @addtogroup Jz47xx
@@ -26,6 +43,14 @@
 void rt_hw_cpu_reset()
 {
 	/* open the watch-dog */
+	WDT_TCSR = WDT_CLK_EXTAL;
+	WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024;
+	WDT_TDR  = 0x03;
+	WDT_TCNT = 0x00;
+	WDT_TCER |= WDT_ENABLE;
+
+	rt_kprintf("reboot system...\n");
+	while (1);
 }
 
 /**

libcpu/mips/jz47xx/interrupt.c

@@ -88,17 +88,17 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha
 	}
 }
 
-static rt_uint32_t pending ;
 void rt_interrupt_dispatch(void *ptreg)
 {
     int i;
 	rt_isr_handler_t irq_func;
+	static rt_uint32_t pending = 0;
 
     /* the hardware interrupt */
 	pending |= INTC_IPR;
 	if (!pending) return;
 
-    for (i = 0; i < JZ47XX_MAX_INTR; i++)
+    for (i = JZ47XX_MAX_INTR; i > 0; --i)
     {
 		if ((pending & (1<<i)))
         {

libcpu/mips/jz47xx/jz4740.h

+#ifndef __JZ4740_H__
+#define __JZ4740_H__
+
+#include "jz47xx.h"
+
+#define	WDT_BASE	0xB0002000
+
+/* Watchdog */
+#define WDT_TDR		__REG16(WDT_BASE + 0x00)	/* Watchdog Timer Data Register */
+#define WDT_TCER	__REG8(WDT_BASE + 0x04)		/* Watchdog Counter Enable Register */
+#define WDT_TCNT	__REG16(WDT_BASE + 0x08)	/* Watchdog Timer Counter Register */
+#define WDT_TCSR	__REG16(WDT_BASE + 0x0C)	/* Watchdog Timer Control Register */
+
+/* Clock Gate Register Definitions */
+#define CPM_CLKGR_UART1   (1 << 15)
+#define CPM_CLKGR_UHC     (1 << 14)
+#define CPM_CLKGR_IPU     (1 << 13)
+#define CPM_CLKGR_DMAC    (1 << 12)
+#define CPM_CLKGR_UDC     (1 << 11)
+#define CPM_CLKGR_LCD     (1 << 10)
+#define CPM_CLKGR_CIM     (1 << 9)
+#define CPM_CLKGR_SADC    (1 << 8)
+#define CPM_CLKGR_MSC     (1 << 7)
+#define CPM_CLKGR_AIC1    (1 << 6)
+#define CPM_CLKGR_AIC2    (1 << 5)
+#define CPM_CLKGR_SSI     (1 << 4)
+#define CPM_CLKGR_I2C     (1 << 3)
+#define CPM_CLKGR_RTC     (1 << 2)
+#define CPM_CLKGR_TCU     (1 << 1)
+#define CPM_CLKGR_UART0   (1 << 0)
+
+/* Interrupt Definitions */
+#define IRQ_I2C		1
+#define IRQ_UHC		3
+#define IRQ_UART0	9
+#define IRQ_SADC	12
+#define IRQ_MSC		14
+#define IRQ_RTC		15
+#define IRQ_SSI		16
+#define IRQ_CIM		17
+#define IRQ_AIC		18
+#define IRQ_ETH		19
+#define IRQ_DMAC	20
+#define IRQ_TCU2	21
+#define IRQ_TCU1	22
+#define IRQ_TCU0	23
+#define IRQ_UDC		24
+#define IRQ_GPIO3	25
+#define IRQ_GPIO2	26
+#define IRQ_GPIO1	27
+#define IRQ_GPIO0	28
+#define IRQ_IPU		29
+#define IRQ_LCD		30
+
+#endif

libcpu/mips/jz47xx/jz4755.h

 #ifndef __JZ4755_H__
 #define __JZ4755_H__
 
+#include "jz47xx.h"
+
+#define	WDT_BASE	0xB0002000
+#define	OST_BASE	0xB00020e0
+
+/* Watchdog */
+#define WDT_TDR		__REG16(WDT_BASE + 0x00)	/* Watchdog Timer Data Register */
+#define WDT_TCER	__REG8(WDT_BASE + 0x04)		/* Watchdog Counter Enable Register */
+#define WDT_TCNT	__REG16(WDT_BASE + 0x08)	/* Watchdog Timer Counter Register */
+#define WDT_TCSR	__REG16(WDT_BASE + 0x0C)	/* Watchdog Timer Control Register */
+
+/* OS Timer */
+#define OST_DR		__REG32(OST_BASE + 0x00)	/* OS Timer Data Register */
+#define OST_CNT		__REG32(OST_BASE + 0x08)	/* OS Timer Counter Register */
+#define OST_CSR		__REG16(OST_BASE + 0x0C)	/* OS Timer Control Register */
+
+/* OST Register Definitions */
+#define OST_TCSR_EXT_EN		( 0x1 << 2)
+#define OST_TCSR_RTC_EN		( 0x1 << 1)
+#define OST_TCSR_PCLK_EN	( 0x1 << 0)
+
+/* Clock Gate Register Definitions */
+#define CPM_CLKGR_AUX_CPU      ( 1 << 24 )
+#define CPM_CLKGR_AHB1         ( 1 << 23 )
+#define CPM_CLKGR_IDCT         ( 1 << 22 )
+#define CPM_CLKGR_DB           ( 1 << 21 )
+#define CPM_CLKGR_ME           ( 1 << 20 )
+#define CPM_CLKGR_MC           ( 1 << 19 )
+#define CPM_CLKGR_TVE          ( 1 << 18 )
+#define CPM_CLKGR_TSSI         ( 1 << 17 )
+#define CPM_CLKGR_MSC1         ( 1 << 16 )
+#define CPM_CLKGR_UART2        ( 1 << 15 )
+#define CPM_CLKGR_UART1        ( 1 << 14 )
+#define CPM_CLKGR_IPU          ( 1 << 13 )
+#define CPM_CLKGR_DMAC         ( 1 << 12 )
+#define CPM_CLKGR_BCH          ( 1 << 11 )
+#define CPM_CLKGR_UDC          ( 1 << 10 )
+#define CPM_CLKGR_LCD          ( 1 << 9 )
+#define CPM_CLKGR_CIM          ( 1 << 8 )
+#define CPM_CLKGR_SADC         ( 1 << 7 )
+#define CPM_CLKGR_MSC0         ( 1 << 6 )
+#define CPM_CLKGR_AIC          ( 1 << 5 )
+#define CPM_CLKGR_SSI1         ( 1 << 4 )
+#define CPM_CLKGR_I2C          ( 1 << 3 )
+#define CPM_CLKGR_RTC          ( 1 << 2 )
+#define CPM_CLKGR_TCU          ( 1 << 1 )
+#define CPM_CLKGR_UART0        ( 1 << 0 )
+
+/* Interrupt Definitions */
+#define IRQ_ETH		0
+#define IRQ_SFT		4
+#define IRQ_I2C		5
+#define IRQ_RTC		6
+#define IRQ_UART2	7
+#define IRQ_UART1	8
+#define IRQ_UART0	9
+#define IRQ_AIC		10
+#define IRQ_GPIO5	11
+#define IRQ_GPIO4	12
+#define IRQ_GPIO3	13
+#define IRQ_GPIO2	14
+#define IRQ_GPIO1	15
+#define IRQ_GPIO0	16
+#define IRQ_BCH		17
+#define IRQ_SADC	18
+#define IRQ_CIM		19
+#define IRQ_TSSI	20
+#define IRQ_TCU2	21
+#define IRQ_TCU1	22
+#define IRQ_TCU0	23
+#define IRQ_MSC1	24
+#define IRQ_MSC0	25
+#define IRQ_SSI		26
+#define IRQ_UDC		27
+#define IRQ_DMA1	28		/* Used for DMA channel 4-7 */
+#define IRQ_DMA0	29		/* Used for DMA channel 0-3 */
+#define IRQ_IPU		30
+#define IRQ_LCD		31
+
 #endif

libcpu/mips/jz47xx/jz47xx.h

@@ -17,9 +17,8 @@
 
 #define	CPM_BASE	0xB0000000
 #define	INTC_BASE	0xB0001000
-#define	OST_BASE	0xB0002000
+#define TCU_BASE	0xB0002000
 #define	RTC_BASE	0xB0003000
-#define	WDT_BASE	0xB0004000
 #define	GPIO_BASE	0xB0010000
 #define	AIC_BASE	0xB0020000
 #define	MSC_BASE	0xB0021000
@@ -39,7 +38,209 @@
 #define	UPRT_BASE	0xB0061000
 #define KBC_BASE	0xB0062000
 
-/* uart offset */
+/* CPM Register */
+#define CPM_CPCCR			__REG32(CPM_BASE + 0x00)	/* Clock Control Register */
+#define CPM_LCR				__REG32(CPM_BASE + 0x04)	/* Low Power Control Register */
+#define CPM_RSR				__REG32(CPM_BASE + 0x08)	/* Reset Status Register */
+#define CPM_CPPCR			__REG32(CPM_BASE + 0x10)	/* PLL Control Register */
+#define CPM_CPPSR			__REG32(CPM_BASE + 0x14)	/* PLL Switch and Status Register */
+#define CPM_CLKGR			__REG32(CPM_BASE + 0x20)	/* Clock Gate Register */
+#define CPM_OPCR			__REG32(CPM_BASE + 0x24)	/* Osillator and Power Control Register */
+#define CPM_I2SCDR			__REG32(CPM_BASE + 0x60)	/* I2S Device Clock Divider Register */
+#define CPM_LPCDR			__REG32(CPM_BASE + 0x64)	/* LCD Pixel Clock Divider Register */
+#define CPM_MSCCDR			__REG32(CPM_BASE + 0x68)	/* MSC Clock Divider Register */
+#define CPM_SSICDR			__REG32(CPM_BASE + 0x74)	/* SSI Clock Divider Register */
+#define CPM_CIMCDR			__REG32(CPM_BASE + 0x7C)	/* CIM MCLK Clock Divider Register */
+
+/* Interrupt Controller Regester */
+#define INTC_ISR			__REG32(INTC_BASE + 0x00)
+#define INTC_IMR			__REG32(INTC_BASE + 0x04)
+#define INTC_IMSR			__REG32(INTC_BASE + 0x08)
+#define INTC_IMCR			__REG32(INTC_BASE + 0x0c)
+#define INTC_IPR			__REG32(INTC_BASE + 0x10)
+
+/* TCU Register */
+#define TCU_TSTR			__REG32(TCU_BASE + 0xF0)
+#define TCU_TSTSR			__REG32(TCU_BASE + 0xF4)
+#define TCU_TSTCR			__REG32(TCU_BASE + 0xF8)
+#define TCU_TSR				__REG32(TCU_BASE + 0x1C)
+#define TCU_TSSR			__REG32(TCU_BASE + 0x2C)
+#define TCU_TSCR			__REG32(TCU_BASE + 0x3C)
+#define TCU_TER				__REG32(TCU_BASE + 0x10)
+#define TCU_TESR			__REG32(TCU_BASE + 0x14)
+#define TCU_TECR			__REG32(TCU_BASE + 0x18)
+#define TCU_TFR				__REG32(TCU_BASE + 0x20)
+#define TCU_TFSR			__REG32(TCU_BASE + 0x24)
+#define TCU_TFCR			__REG32(TCU_BASE + 0x28)
+#define TCU_TMR				__REG32(TCU_BASE + 0x30)
+#define TCU_TMSR			__REG32(TCU_BASE + 0x34)
+#define TCU_TMCR			__REG32(TCU_BASE + 0x38)
+#define TCU_TDFR0_OFFSET	0x40
+#define TCU_TDFR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TDFR0_OFFSET)
+#define TCU_TDHR0_OFFSET	0x44
+#define TCU_TDHR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TDHR0_OFFSET)
+#define TCU_TCNT0_OFFSET	0x48
+#define TCU_TCNT(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TCNT0_OFFSET)
+#define TCU_TCSR0_OFFSET	0x4C
+#define TCU_TCSR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TCSR0_OFFSET)
+
+/* TCU Register Definitions */
+#define TCU_TCSR_PWM_SD         (1 << 9)
+#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
+#define TCU_TCSR_PWM_EN         (1 << 7)
+#define TCU_TCSR_PRESCALE_BIT   3
+#define TCU_TCSR_PRESCALE_MASK  (0x7 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE1      (0x0 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE4      (0x1 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE16     (0x2 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE64     (0x3 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE256    (0x4 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE1024   (0x5 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_EXT_EN         (1 << 2)
+#define TCU_TCSR_RTC_EN         (1 << 1)
+#define TCU_TCSR_PCK_EN         (1 << 0)
+
+#define TCU_TER_OSTEN   (1 << 15)
+#define TCU_TER_TCEN5   (1 << 5)
+#define TCU_TER_TCEN4   (1 << 4)
+#define TCU_TER_TCEN3   (1 << 3)
+#define TCU_TER_TCEN2   (1 << 2)
+#define TCU_TER_TCEN1   (1 << 1)
+#define TCU_TER_TCEN0   (1 << 0)
+
+#define TCU_TESR_OSTST  (1 << 15)
+#define TCU_TESR_TCST5  (1 << 5)
+#define TCU_TESR_TCST4  (1 << 4)
+#define TCU_TESR_TCST3  (1 << 3)
+#define TCU_TESR_TCST2  (1 << 2)
+#define TCU_TESR_TCST1  (1 << 1)
+#define TCU_TESR_TCST0  (1 << 0)
+
+#define TCU_TECR_OSTCL  (1 << 15)
+#define TCU_TECR_TCCL5  (1 << 5)
+#define TCU_TECR_TCCL4  (1 << 4)
+#define TCU_TECR_TCCL3  (1 << 3)
+#define TCU_TECR_TCCL2  (1 << 2)
+#define TCU_TECR_TCCL1  (1 << 1)
+#define TCU_TECR_TCCL0  (1 << 0)
+
+#define TCU_TFR_HFLAG5  (1 << 21)
+#define TCU_TFR_HFLAG4  (1 << 20)
+#define TCU_TFR_HFLAG3  (1 << 19)
+#define TCU_TFR_HFLAG2  (1 << 18)
+#define TCU_TFR_HFLAG1  (1 << 17)
+#define TCU_TFR_HFLAG0  (1 << 16)
+#define TCU_TFR_FFLAG5  (1 << 5)
+#define TCU_TFR_FFLAG4  (1 << 4)
+#define TCU_TFR_FFLAG3  (1 << 3)
+#define TCU_TFR_FFLAG2  (1 << 2)
+#define TCU_TFR_FFLAG1  (1 << 1)
+#define TCU_TFR_FFLAG0  (1 << 0)
+
+#define TCU_TFSR_HFLAG5 (1 << 21)
+#define TCU_TFSR_HFLAG4 (1 << 20)
+#define TCU_TFSR_HFLAG3 (1 << 19)
+#define TCU_TFSR_HFLAG2 (1 << 18)
+#define TCU_TFSR_HFLAG1 (1 << 17)
+#define TCU_TFSR_HFLAG0 (1 << 16)
+#define TCU_TFSR_OSTFLAG (1 << 15)
+#define TCU_TFSR_FFLAG5 (1 << 5)
+#define TCU_TFSR_FFLAG4 (1 << 4)
+#define TCU_TFSR_FFLAG3 (1 << 3)
+#define TCU_TFSR_FFLAG2 (1 << 2)
+#define TCU_TFSR_FFLAG1 (1 << 1)
+#define TCU_TFSR_FFLAG0 (1 << 0)
+
+#define TCU_TFCR_HFLAG5 (1 << 21)
+#define TCU_TFCR_HFLAG4 (1 << 20)
+#define TCU_TFCR_HFLAG3 (1 << 19)
+#define TCU_TFCR_HFLAG2 (1 << 18)
+#define TCU_TFCR_HFLAG1 (1 << 17)
+#define TCU_TFCR_HFLAG0 (1 << 16)
+#define TCU_TFCR_OSTFLAG (1 << 15)
+#define TCU_TFCR_FFLAG5 (1 << 5)
+#define TCU_TFCR_FFLAG4 (1 << 4)
+#define TCU_TFCR_FFLAG3 (1 << 3)
+#define TCU_TFCR_FFLAG2 (1 << 2)
+#define TCU_TFCR_FFLAG1 (1 << 1)
+#define TCU_TFCR_FFLAG0 (1 << 0)
+
+#define TCU_TMR_HMASK5  (1 << 21)
+#define TCU_TMR_HMASK4  (1 << 20)
+#define TCU_TMR_HMASK3  (1 << 19)
+#define TCU_TMR_HMASK2  (1 << 18)
+#define TCU_TMR_HMASK1  (1 << 17)
+#define TCU_TMR_HMASK0  (1 << 16)
+#define TCU_TMR_OSTMASK (1 << 15)
+#define TCU_TMR_FMASK5  (1 << 5)
+#define TCU_TMR_FMASK4  (1 << 4)
+#define TCU_TMR_FMASK3  (1 << 3)
+#define TCU_TMR_FMASK2  (1 << 2)
+#define TCU_TMR_FMASK1  (1 << 1)
+#define TCU_TMR_FMASK0  (1 << 0)
+
+#define TCU_TMSR_HMST5  (1 << 21)
+#define TCU_TMSR_HMST4  (1 << 20)
+#define TCU_TMSR_HMST3  (1 << 19)
+#define TCU_TMSR_HMST2  (1 << 18)
+#define TCU_TMSR_HMST1  (1 << 17)
+#define TCU_TMSR_HMST0  (1 << 16)
+#define TCU_TMSR_OSTMST (1 << 15)
+#define TCU_TMSR_FMST5  (1 << 5)
+#define TCU_TMSR_FMST4  (1 << 4)
+#define TCU_TMSR_FMST3  (1 << 3)
+#define TCU_TMSR_FMST2  (1 << 2)
+#define TCU_TMSR_FMST1  (1 << 1)
+#define TCU_TMSR_FMST0  (1 << 0)
+
+#define TCU_TMCR_HMCL5  (1 << 21)
+#define TCU_TMCR_HMCL4  (1 << 20)
+#define TCU_TMCR_HMCL3  (1 << 19)
+#define TCU_TMCR_HMCL2  (1 << 18)
+#define TCU_TMCR_HMCL1  (1 << 17)
+#define TCU_TMCR_HMCL0  (1 << 16)
+#define TCU_TMCR_OSTMCL (1 << 15)
+#define TCU_TMCR_FMCL5  (1 << 5)
+#define TCU_TMCR_FMCL4  (1 << 4)
+#define TCU_TMCR_FMCL3  (1 << 3)
+#define TCU_TMCR_FMCL2  (1 << 2)
+#define TCU_TMCR_FMCL1  (1 << 1)
+#define TCU_TMCR_FMCL0  (1 << 0)
+
+#define TCU_TSR_WDTS    (1 << 16)
+#define TCU_TSR_STOP5   (1 << 5)
+#define TCU_TSR_STOP4   (1 << 4)
+#define TCU_TSR_STOP3   (1 << 3)
+#define TCU_TSR_STOP2   (1 << 2)
+#define TCU_TSR_STOP1   (1 << 1)
+#define TCU_TSR_STOP0   (1 << 0)
+
+#define TCU_TSSR_WDTSS  (1 << 16)
+#define TCU_TSSR_STPS5  (1 << 5)
+#define TCU_TSSR_STPS4  (1 << 4)
+#define TCU_TSSR_STPS3  (1 << 3)
+#define TCU_TSSR_STPS2  (1 << 2)
+#define TCU_TSSR_STPS1  (1 << 1)
+#define TCU_TSSR_STPS0  (1 << 0)
+
+#define TCU_TSSR_WDTSC  (1 << 16)
+#define TCU_TSSR_STPC5  (1 << 5)
+#define TCU_TSSR_STPC4  (1 << 4)
+#define TCU_TSSR_STPC3  (1 << 3)
+#define TCU_TSSR_STPC2  (1 << 2)
+#define TCU_TSSR_STPC1  (1 << 1)
+#define TCU_TSSR_STPC0  (1 << 0)
+
+#define OST_TCSR_CNT_MD                  ( 1 << 15 )
+#define OST_TCSR_PWM_SHUT_ABRUPT         ( 1 << 9 )
+#define OST_TCSR_PRESCALE1               ( 0x0 << 3)
+#define OST_TCSR_PRESCALE4               ( 0x1 << 3)
+#define OST_TCSR_PRESCALE16              ( 0x2 << 3)
+#define OST_TCSR_PRESCALE64              ( 0x3 << 3)
+#define OST_TCSR_PRESCALE256             ( 0x4 << 3)
+#define OST_TCSR_PRESCALE1024            ( 0x5 << 3)
+
+/* Uart Register */
 #define UART_RDR(base)		__REG8((base) + 0x00)	/* R  8b H'xx */
 #define UART_TDR(base)		__REG8((base) + 0x00)	/* W  8b H'xx */
 #define UART_DLLR(base)		__REG8((base) + 0x00)	/* RW 8b H'00 */
@@ -55,42 +256,6 @@
 #define UART_MCR(base)		__REG8((base) + 0x10)	/* RW 8b H'00 */
 #define UART_SIRCR(base)	__REG8((base) + 0x20)	/* RW 8b H'00 */
 
-/* interrupt controller */
-#define INTC_ISR			__REG32(INTC_BASE + 0x00)
-#define INTC_IMR			__REG32(INTC_BASE + 0x04)
-#define INTC_IMSR			__REG32(INTC_BASE + 0x08)
-#define INTC_IMCR			__REG32(INTC_BASE + 0x0c)
-#define INTC_IPR			__REG32(INTC_BASE + 0x10)
-
-#define IRQ_I2C		1
-#define IRQ_PS2		2
-#define IRQ_UPRT	3
-#define IRQ_CORE	4
-#define IRQ_UART3	6
-#define IRQ_UART2	7
-#define IRQ_UART1	8
-#define IRQ_UART0	9
-#define IRQ_SCC1	10
-#define IRQ_SCC0	11
-#define IRQ_UDC		12
-#define IRQ_UHC		13
-#define IRQ_MSC		14
-#define IRQ_RTC		15
-#define IRQ_FIR		16
-#define IRQ_SSI		17
-#define IRQ_CIM		18
-#define IRQ_ETH		19
-#define IRQ_AIC		20
-#define IRQ_DMAC	21
-#define IRQ_OST2	22
-#define IRQ_OST1	23
-#define IRQ_OST0	24
-#define IRQ_GPIO3	25
-#define IRQ_GPIO2	26
-#define IRQ_GPIO1	27
-#define IRQ_GPIO0	28
-#define IRQ_LCD		30
-
 #define SYSTEM_STACK          0x80003fe8		/* the kernel system stack address */
 
 #endif