update radio code to v2.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@320 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/stm32_radio/board.c

@@ -153,6 +153,19 @@ void rt_hw_board_init()
     /* Configure the system clocks */
     RCC_Configuration();
 
+    /* DM9000A */
+    {
+        GPIO_InitTypeDef GPIO_InitStructure;
+
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE,ENABLE);
+
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_Init(GPIOE,&GPIO_InitStructure);
+        GPIO_SetBits(GPIOE,GPIO_Pin_5);
+    }
+
     /* NVIC Configuration */
     NVIC_Configuration();
 

bsp/stm32_radio/codec.c

+#include <rthw.h>
+#include <rtthread.h>
+#include "stm32f10x.h"
+
+/*
+ * WM8753 Driver
+ */
+
+/* WM8753 register definitions */
+#define WM8753_DAC		0x01
+#define WM8753_ADC		0x02
+#define WM8753_PCM		0x03
+#define WM8753_HIFI		0x04
+#define WM8753_IOCTL	0x05
+#define WM8753_SRATE1	0x06
+#define WM8753_SRATE2	0x07
+#define WM8753_LDAC		0x08
+#define WM8753_RDAC		0x09
+#define WM8753_BASS		0x0a
+#define WM8753_TREBLE	0x0b
+#define WM8753_ALC1		0x0c
+#define WM8753_ALC2		0x0d
+#define WM8753_ALC3		0x0e
+#define WM8753_NGATE	0x0f
+#define WM8753_LADC		0x10
+#define WM8753_RADC		0x11
+#define WM8753_ADCTL1	0x12
+#define WM8753_3D		0x13
+#define WM8753_PWR1		0x14
+#define WM8753_PWR2		0x15
+#define WM8753_PWR3		0x16
+#define WM8753_PWR4		0x17
+#define WM8753_ID		0x18
+#define WM8753_INTPOL	0x19
+#define WM8753_INTEN	0x1a
+#define WM8753_GPIO1	0x1b
+#define WM8753_GPIO2	0x1c
+#define WM8753_RESET	0x1f
+#define WM8753_RECMIX1	0x20
+#define WM8753_RECMIX2	0x21
+#define WM8753_LOUTM1	0x22
+#define WM8753_LOUTM2	0x23
+#define WM8753_ROUTM1	0x24
+#define WM8753_ROUTM2	0x25
+#define WM8753_MOUTM1	0x26
+#define WM8753_MOUTM2	0x27
+#define WM8753_LOUT1V	0x28
+#define WM8753_ROUT1V	0x29
+#define WM8753_LOUT2V	0x2a
+#define WM8753_ROUT2V	0x2b
+#define WM8753_MOUTV	0x2c
+#define WM8753_OUTCTL	0x2d
+#define WM8753_ADCIN	0x2e
+#define WM8753_INCTL1	0x2f
+#define WM8753_INCTL2	0x30
+#define WM8753_LINVOL	0x31
+#define WM8753_RINVOL	0x32
+#define WM8753_MICBIAS	0x33
+#define WM8753_CLOCK	0x34
+#define WM8753_PLL1CTL1	0x35
+#define WM8753_PLL1CTL2	0x36
+#define WM8753_PLL1CTL3	0x37
+#define WM8753_PLL1CTL4	0x38
+#define WM8753_PLL2CTL1	0x39
+#define WM8753_PLL2CTL2	0x3a
+#define WM8753_PLL2CTL3	0x3b
+#define WM8753_PLL2CTL4	0x3c
+#define WM8753_BIASCTL	0x3d
+#define WM8753_ADCTL2	0x3f
+
+/*
+SCLK  PA5  SPI1_SCK
+SDIN  PA6
+CSB   PC5
+*/
+#define wm_sclk_0  GPIO_ResetBits(GPIOA,GPIO_Pin_5)
+#define wm_sclk_1  GPIO_SetBits(GPIOA,GPIO_Pin_5)
+#define wm_sdin_0  GPIO_ResetBits(GPIOA,GPIO_Pin_7)
+#define wm_sdin_1  GPIO_SetBits(GPIOA,GPIO_Pin_7)
+#define wm_csb_0   GPIO_ResetBits(GPIOC,GPIO_Pin_5)
+#define wm_csb_1   GPIO_SetBits(GPIOC,GPIO_Pin_5)
+
+#define DATA_NODE_MAX 5
+/* data node for Tx Mode */
+struct wm8753_data_node
+{
+    rt_uint16_t *data_ptr;
+    rt_size_t  data_size;
+};
+
+struct wm8753_device
+{
+    /* inherit from rt_device */
+    struct rt_device parent;
+
+    /* pcm data list */
+    struct wm8753_data_node data_list[DATA_NODE_MAX];
+    rt_uint16_t read_index, put_index;
+
+    /* transmitted offset of current data node */
+    rt_size_t offset;
+};
+struct wm8753_device wm8753;
+
+static void NVIC_Configuration(void)
+{
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    /* SPI2 IRQ Channel configuration */
+    NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+
+    /* DMA1 IRQ Channel configuration */
+    NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel5_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+static void GPIO_Configuration(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure;
+    SPI_InitTypeDef SPI_InitStructure;
+
+#define SPI_MASTER                   SPI1
+#define SPI_MASTER_CLK               RCC_APB2Periph_SPI1
+#define SPI_MASTER_GPIO              GPIOA
+#define SPI_MASTER_GPIO_CLK          RCC_APB2Periph_GPIOA
+#define SPI_MASTER_PIN_SCK           GPIO_Pin_5
+#define SPI_MASTER_PIN_MISO          GPIO_Pin_6
+#define SPI_MASTER_PIN_MOSI          GPIO_Pin_7
+#define SPI_MASTER_IRQn              SPI1_IRQn
+
+    /* Disable the JTAG interface and enable the SWJ interface */
+    GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA |
+                           RCC_APB2Periph_AFIO, ENABLE);
+
+    /* Enable SPI_MASTER Periph clock */
+    RCC_APB2PeriphClockCmd(SPI_MASTER_CLK, ENABLE);
+
+    /* Configure SPI_MASTER pins: SCK, MISO and MOSI */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOC,&GPIO_InitStructure);
+
+    /* SPI_MASTER configuration ------------------------------------------------*/
+    SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx;
+    SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+    SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+    SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;/* 常态为低电平 */
+    SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; /* SPI_CPHA_1Edge 从第一个沿开始送数据: 上升沿
+                                                    SPI_CPHA_2Edge 从第二个沿开始送数据: 下降沿 */
+    SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+    SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256;
+    SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+    SPI_InitStructure.SPI_CRCPolynomial = 7;
+    SPI_Init(SPI1, &SPI_InitStructure);
+
+    /* Enable SPI_MASTER */
+    SPI_Cmd(SPI1, ENABLE);
+    SPI_CalculateCRC(SPI1, DISABLE);
+
+
+    /* Configure SPI2 pins: CK, WS and SD */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+#if 0
+    /*    MCO    configure */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOA,&GPIO_InitStructure);
+
+    RCC_MCOConfig(RCC_MCO_HSE);
+#endif
+}
+
+#define SPI2_DR_Address  0x4000380C
+static void DMA_Configuration(rt_uint32_t addr, rt_size_t size)
+{
+    DMA_InitTypeDef    DMA_InitStructure;
+
+    /* DMA1 Channel2 configuration ----------------------------------------------*/
+    DMA_Cmd(DMA1_Channel5, DISABLE);
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)SPI2_DR_Address;
+    DMA_InitStructure.DMA_MemoryBaseAddr = (u32)addr;
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    DMA_InitStructure.DMA_BufferSize = size;
+    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
+    DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
+    DMA_InitStructure.DMA_Priority = DMA_Priority_Low;
+    DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+    DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+    DMA_Init(DMA1_Channel5, &DMA_InitStructure);
+
+    /* Enable SPI2 DMA Tx request */
+    SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
+
+    DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);
+    DMA_Cmd(DMA1_Channel5, ENABLE);
+}
+
+static void I2S_Configuration(void)
+{
+    I2S_InitTypeDef I2S_InitStructure;
+
+    /* I2S peripheral configuration */
+    I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
+    I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
+    I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+    I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_44k;
+    I2S_InitStructure.I2S_CPOL = I2S_CPOL_High;// I2S_CPOL_Low
+
+    /* I2S2 Master Transmitter to I2S3 Slave Receiver communication -----------*/
+    /* I2S2 configuration */
+    I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;//I2S_Mode_MasterTx  I2S_Mode_SlaveTx
+    I2S_Init(SPI2, &I2S_InitStructure);
+}
+
+#if 1
+static void wm_delay(void)
+{
+    volatile unsigned int dl;
+    for(dl=0; dl<5000; dl++);
+}
+#endif
+
+void wm8753_send(rt_uint16_t s_data)
+{
+    /* Wait for SPI1 Tx buffer empty */
+    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
+
+    wm_csb_0;
+    /* Send SPI1 data */
+    SPI_I2S_SendData(SPI1, (s_data>>8)&0xFF );
+    /* Wait for SPI1 Tx buffer empty */
+    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
+    /* Send SPI1 data */
+    SPI_I2S_SendData(SPI1, s_data&0xFF);
+
+    wm_delay();
+    wm_csb_1;
+
+#if 0
+    u8 i;
+    wm_csb_0;
+    //wm_delay();
+    wm_sclk_0;
+    //wm_delay();
+    for (i=0;i<16;i++)
+    {
+        if (s_data & 0x8000)
+        {
+            wm_sdin_1;
+        }
+        else
+        {
+            wm_sdin_0;
+        }
+        //wm_delay();
+        wm_sclk_1;
+        s_data <<= 1;
+        //wm_delay();
+        wm_sclk_0;
+    }
+    //wm_delay();
+    wm_csb_1;
+#endif
+}
+
+static rt_err_t wm8753_init (rt_device_t dev)
+{
+    wm8753_send(0xF00F); // test
+    wm8753_send(0<<9 | 0xFF); // reset
+    //wm_delay();
+    //wm_delay();
+    //wm_delay();
+
+    /* POWER manager */
+    wm8753_send(1<<9 | (1<<8) | (0<<7) | (0<<6) | (0<<5) | (1<<4) | (1<<3) | (1<<2) | 2    );//电源设置
+    wm8753_send(2<<9 | (1<<8) | (1<<7) | (1<<5) | (1<<4) | (1<<3) | (1<<2) );                // 打开电源  耳机输出
+    wm8753_send(3<<9 | (0<<8) | (0<<7) | (1<<6) | (1<<5) | (1<<3) | (1<<2) | (1<<1) | 1 );   // 喇叭输出和DAC
+
+    /* IIS DAC test */
+    wm8753_send(4<<9 | (0<<7) | (2<<3) );//IIS 16BIT
+    // 12.288/3/8=512K
+    wm8753_send(6<<9  | (0<<5) | (3<<2)| 0);//0: slave 1: master  | (3<<5) | (3<<2)
+    wm8753_send(43<<9 | (1<<4) );//INVROUT2
+
+    /* 设置初始化音量 */
+    wm8753_send(52<<9 | (1<<8) | (1<<7) | 35 ); // LOUT1 0-57-63
+    wm8753_send(53<<9 | (1<<8) | (1<<7) | 35 ); // ROUT1 0-57-63
+    wm8753_send(54<<9 | (1<<8) | (1<<7) | 35 ); // LOUT2 0-57-63
+    wm8753_send(55<<9 | (1<<8) | (1<<7) | 35 ); // ROUT2 0-57-63
+
+    return RT_EOK;
+}
+
+#include <finsh.h>
+//0~57~63
+void vol(int v)
+{
+    wm8753_send(52<<9 | (0<<8) | (1<<7) | v ); // LOUT1 0-57-63
+    wm8753_send(53<<9 | (1<<8) | (1<<7) | v ); // ROUT1 0-57-63
+    wm8753_send(54<<9 | (0<<8) | (1<<7) | v ); // LOUT2 0-57-63
+    wm8753_send(55<<9 | (1<<8) | (1<<7) | v ); // ROUT2 0-57-63
+}
+FINSH_FUNCTION_EXPORT(vol, set volume)
+
+static rt_err_t wm8753_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    /* enable I2S */
+    I2S_Cmd(SPI2, ENABLE);
+
+    return RT_EOK;
+}
+
+static rt_err_t wm8753_close(rt_device_t dev)
+{
+    /* interrupt mode */
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* Disable the I2S2 */
+        I2S_Cmd(SPI2, DISABLE);
+    }
+
+    /* remove all data node */
+
+    return RT_EOK;
+}
+
+static rt_err_t wm8753_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    /* rate control */
+    return RT_EOK;
+}
+
+static rt_size_t wm8753_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+    struct wm8753_device* device;
+    struct wm8753_data_node* node;
+    rt_uint32_t level;
+    rt_uint16_t next_index;
+
+    device = (struct wm8753_device*)dev;
+    RT_ASSERT(device != RT_NULL);
+
+    next_index = device->put_index + 1;
+    if (next_index >= DATA_NODE_MAX) next_index = 0;
+
+    /* check data_list full */
+    if (next_index == device->read_index)
+    {
+        rt_set_errno(-RT_EFULL);
+        return 0;
+    }
+
+    level = rt_hw_interrupt_disable();
+    node = &device->data_list[device->put_index];
+    device->put_index = next_index;
+
+    // rt_kprintf("+\n");
+    /* set node attribute */
+    node->data_ptr = (rt_uint16_t*)buffer;
+    node->data_size = size >> 1; /* size is byte unit, convert to half word unit */
+
+    next_index = device->read_index + 1;
+    if (next_index >= DATA_NODE_MAX) next_index = 0;
+
+    /* check data list whether is empty */
+    if (next_index == device->put_index)
+    {
+        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            device->offset = 0;
+            /* enable I2S interrupt */
+            SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, ENABLE);
+        }
+        else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+        {
+            DMA_Configuration((rt_uint32_t)node->data_ptr, node->data_size);
+        }
+    }
+    rt_hw_interrupt_enable(level);
+
+    return size;
+}
+
+rt_err_t wm8753_hw_init(void)
+{
+    rt_device_t dev;
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+
+    NVIC_Configuration();
+    GPIO_Configuration();
+    I2S_Configuration();
+
+    dev = (rt_device_t)&wm8753;
+    dev->type			= RT_Device_Class_Unknown;
+    dev->rx_indicate 	= RT_NULL;
+    dev->tx_complete 	= RT_NULL;
+    dev->init 			= wm8753_init;
+    dev->open			= wm8753_open;
+    dev->close			= wm8753_close;
+    dev->read 			= RT_NULL;
+    dev->write 			= wm8753_write;
+    dev->control 		= wm8753_control;
+    dev->private		= RT_NULL;
+
+    /* set read_index and put index to 0 */
+    wm8753.read_index	= 0;
+    wm8753.put_index 	= 0;
+
+	wm_csb_1;
+
+#if 0
+    wm_sclk_0;
+    wm_sclk_1;
+    wm_sclk_0;
+
+    wm_sdin_0;
+    wm_sdin_1;
+    wm_sdin_0;
+
+    wm_csb_0;
+    wm_csb_1;
+#endif
+
+    /* register the device */
+    return rt_device_register(&wm8753.parent, "snd",
+                              RT_DEVICE_FLAG_WRONLY | RT_DEVICE_FLAG_DMA_TX);
+}
+
+void wm8753_isr()
+{
+    struct wm8753_data_node* node;
+    node = &wm8753.data_list[wm8753.read_index]; /* get current data node */
+
+    if (SPI_I2S_GetITStatus(SPI2, SPI_I2S_IT_TXE) == SET)
+    {
+        SPI_I2S_SendData(SPI2, node->data_ptr[wm8753.offset++]);
+    }
+
+    if (wm8753.offset == node->data_size)
+    {
+        /* move to next node */
+        rt_uint16_t next_index;
+
+        next_index = wm8753.read_index + 1;
+        if (next_index >= DATA_NODE_MAX) next_index = 0;
+
+        /* notify transmitted complete. */
+        if (wm8753.parent.tx_complete != RT_NULL)
+        {
+            wm8753.parent.tx_complete (&wm8753.parent, wm8753.data_list[wm8753.read_index].data_ptr);
+            rt_kprintf("-\n");
+        }
+
+        wm8753.offset = 0;
+        wm8753.read_index = next_index;
+        if (next_index == wm8753.put_index)
+        {
+            /* no data on the list, disable I2S interrupt */
+            SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
+
+            rt_kprintf("*\n");
+        }
+    }
+}
+
+void wm8753_dma_isr()
+{
+    /* switch to next buffer */
+    rt_uint16_t next_index;
+    void* data_ptr;
+
+    next_index = wm8753.read_index + 1;
+    if (next_index >= DATA_NODE_MAX) next_index = 0;
+
+    /* save current data pointer */
+    data_ptr = wm8753.data_list[wm8753.read_index].data_ptr;
+
+    wm8753.read_index = next_index;
+    if (next_index != wm8753.put_index)
+    {
+        /* enable next dma request */
+        DMA_Configuration((rt_uint32_t)wm8753.data_list[wm8753.read_index].data_ptr,
+                          wm8753.data_list[wm8753.read_index].data_size);
+    }
+    else
+    {
+        rt_kprintf("*\n");
+    }
+
+    /* notify transmitted complete. */
+    if (wm8753.parent.tx_complete != RT_NULL)
+    {
+        wm8753.parent.tx_complete (&wm8753.parent, data_ptr);
+        // rt_kprintf("-\n");
+    }
+}
+

bsp/stm32_radio/dm9000.c

@@ -18,8 +18,8 @@
 //--------------------------------------------------------
 
 #define DM9000_PHY          0x40    /* PHY address 0x01 */
-#define RST_1()             GPIO_SetBits(GPIOF,GPIO_Pin_6)
-#define RST_0()             GPIO_ResetBits(GPIOF,GPIO_Pin_6)
+#define RST_1()             GPIO_SetBits(GPIOE,GPIO_Pin_5)
+#define RST_0()             GPIO_ResetBits(GPIOE,GPIO_Pin_5)
 
 #define MAX_ADDR_LEN 6
 enum DM9000_PHY_mode
@@ -561,7 +561,7 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
 static void RCC_Configuration(void)
 {
     /* enable gpiob port clock */
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF | RCC_APB2Periph_AFIO, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE);
 }
 
 static void NVIC_Configuration(void)
@@ -569,7 +569,7 @@ static void NVIC_Configuration(void)
     NVIC_InitTypeDef NVIC_InitStructure;
 
     /* Enable the EXTI0 Interrupt */
-    NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannel = EXTI4_IRQn;
     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
@@ -581,32 +581,32 @@ static void GPIO_Configuration()
     GPIO_InitTypeDef GPIO_InitStructure;
     EXTI_InitTypeDef EXTI_InitStructure;
 
-    /* configure PF6 as eth RST */
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+    /* configure PE5 as eth RST */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-    GPIO_Init(GPIOF,&GPIO_InitStructure);
-    GPIO_ResetBits(GPIOF,GPIO_Pin_6);
-    RST_1();
+    GPIO_Init(GPIOE,&GPIO_InitStructure);
+    GPIO_SetBits(GPIOE,GPIO_Pin_5);
+    //RST_1();
 
-    /* configure PF7 as external interrupt */
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
+    /* configure PE4 as external interrupt */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
-    GPIO_Init(GPIOF, &GPIO_InitStructure);
+    GPIO_Init(GPIOE, &GPIO_InitStructure);
 
-    /* Connect DM9000 EXTI Line to GPIOF Pin 7 */
-    GPIO_EXTILineConfig(GPIO_PortSourceGPIOF, GPIO_PinSource7);
+    /* Connect DM9000 EXTI Line to GPIOE Pin 4 */
+    GPIO_EXTILineConfig(GPIO_PortSourceGPIOE, GPIO_PinSource4);
 
     /* Configure DM9000 EXTI Line to generate an interrupt on falling edge */
-    EXTI_InitStructure.EXTI_Line = EXTI_Line7;
+    EXTI_InitStructure.EXTI_Line = EXTI_Line4;
     EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
     EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
     EXTI_InitStructure.EXTI_LineCmd = ENABLE;
     EXTI_Init(&EXTI_InitStructure);
 
-    /* Clear the Key Button EXTI line pending bit */
-    EXTI_ClearITPendingBit(EXTI_Line7);
+    /* Clear DM9000A EXTI line pending bit */
+    EXTI_ClearITPendingBit(EXTI_Line4);
 }
 
 void rt_hw_dm9000_init()

bsp/stm32_radio/dm9000.h

@@ -12,8 +12,8 @@
 #define DM9000_inw(r) 		(*(volatile rt_uint16_t *)r)
 #define DM9000_outw(r, d) 	(*(volatile rt_uint16_t *)r = d)
 
-#define    RST_1()   GPIO_SetBits(GPIOF,GPIO_Pin_6)
-#define    RST_0()   GPIO_ResetBits(GPIOF,GPIO_Pin_6)
+#define    RST_1()   GPIO_SetBits(GPIOE,GPIO_Pin_5)
+#define    RST_0()   GPIO_ResetBits(GPIOE,GPIO_Pin_5)
 
 #define DM9000_ID		    0x90000A46  /* DM9000 ID */
 #define DM9000_PKT_MAX		1536	    /* Received packet max size */

bsp/stm32_radio/key.c

@@ -11,11 +11,11 @@ key_up      PA2
 key_right   PC2
 key_left    PC3
 */
-#define key_enter_GETVALUE()  GPIO_ReadInputDataBit(GPIOA,GPIO_Pin_0)
-#define key_down_GETVALUE()   GPIO_ReadInputDataBit(GPIOA,GPIO_Pin_1)
-#define key_up_GETVALUE()     GPIO_ReadInputDataBit(GPIOA,GPIO_Pin_2)
-#define key_right_GETVALUE()  GPIO_ReadInputDataBit(GPIOC,GPIO_Pin_2)
-#define key_left_GETVALUE()   GPIO_ReadInputDataBit(GPIOC,GPIO_Pin_3)
+#define key_enter_GETVALUE()  GPIO_ReadInputDataBit(GPIOF,GPIO_Pin_11)
+#define key_down_GETVALUE()   GPIO_ReadInputDataBit(GPIOG,GPIO_Pin_15)
+#define key_up_GETVALUE()     GPIO_ReadInputDataBit(GPIOG,GPIO_Pin_11)
+#define key_right_GETVALUE()  GPIO_ReadInputDataBit(GPIOG,GPIO_Pin_14)
+#define key_left_GETVALUE()   GPIO_ReadInputDataBit(GPIOG,GPIO_Pin_13)
 
 static void key_thread_entry(void *parameter)
 {
@@ -24,15 +24,21 @@ static void key_thread_entry(void *parameter)
     GPIO_InitTypeDef GPIO_InitStructure;
 
     /* init gpio configuration */
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC,ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE,ENABLE);
 
     GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_IPU;
     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-    GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2;
-    GPIO_Init(GPIOA,&GPIO_InitStructure);
+    GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_11 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+    GPIO_Init(GPIOG,&GPIO_InitStructure);
 
-    GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_2 | GPIO_Pin_3;
-    GPIO_Init(GPIOC,&GPIO_InitStructure);
+    GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_11;
+    GPIO_Init(GPIOF,&GPIO_InitStructure);
+
+    /* PE2 LED */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+    GPIO_Init(GPIOE,&GPIO_InitStructure);
+    GPIO_SetBits(GPIOE,GPIO_Pin_2);
 
     /* init keyboard event */
     RTGUI_EVENT_KBD_INIT(&kbd_event);

bsp/stm32_radio/project.Opt

@@ -11,7 +11,7 @@
  DaveTm { 0,0,0,0,0,0,0,0 }
 
 Target (RT-Thread STM32 Radio), 0x0004 // Tools: 'ARM-ADS'
-GRPOPT 1,(Startup),0,0,0
+GRPOPT 1,(Startup),1,0,0
 GRPOPT 2,(Kernel),0,0,0
 GRPOPT 3,(STM32),0,0,0
 GRPOPT 4,(StdPeriph_Driver),0,0,0
@@ -27,9 +27,9 @@ GRPOPT 12,(Mass_Storage),0,0,0
 OPTFFF 1,1,5,0,0,0,0,0,<.\rtconfig.h><rtconfig.h> 
 OPTFFF 1,2,5,0,0,0,0,0,<.\board.h><board.h> 
 OPTFFF 1,3,5,0,0,0,0,0,<.\stm32f10x_conf.h><stm32f10x_conf.h> 
-OPTFFF 1,4,1,100663296,0,0,0,0,<.\application.c><application.c> 
+OPTFFF 1,4,1,0,0,0,0,0,<.\application.c><application.c> 
 OPTFFF 1,5,1,0,0,0,0,0,<.\board.c><board.c> 
-OPTFFF 1,6,1,268435456,0,0,0,0,<.\startup.c><startup.c> 
+OPTFFF 1,6,1,352321536,0,0,0,0,<.\startup.c><startup.c> 
 OPTFFF 1,7,1,0,0,0,0,0,<.\stm32f10x_it.c><stm32f10x_it.c> 
 OPTFFF 1,8,1,0,0,0,0,0,<.\usart.c><usart.c> 
 OPTFFF 1,9,1,402653184,0,0,0,0,<.\sdcard.c><sdcard.c> 
@@ -39,7 +39,7 @@ OPTFFF 1,12,1,889192448,0,0,0,0,<.\fsmc_nand.c><fsmc_nand.c>
 OPTFFF 1,13,1,0,0,0,0,0,<.\fsmc_sram.c><fsmc_sram.c> 
 OPTFFF 1,14,1,0,0,0,0,0,<.\fmt0371\fmt0371.c><fmt0371.c> 
 OPTFFF 1,15,1,0,0,0,0,0,<.\http.c><http.c> 
-OPTFFF 1,16,1,402653184,0,0,0,0,<.\lcd.c><lcd.c> 
+OPTFFF 1,16,1,0,0,0,0,0,<.\lcd.c><lcd.c> 
 OPTFFF 1,17,1,16777216,0,0,0,0,<.\mp3.c><mp3.c> 
 OPTFFF 1,18,1,369098752,0,0,0,0,<.\wav.c><wav.c> 
 OPTFFF 1,19,1,0,0,0,0,0,<.\netbuffer.c><netbuffer.c> 
@@ -48,196 +48,195 @@ OPTFFF 1,21,1,0,0,0,0,0,<.\info.c><info.c>
 OPTFFF 1,22,1,0,0,0,0,0,<.\filelist.c><filelist.c> 
 OPTFFF 1,23,1,0,0,0,0,0,<.\device_info.c><device_info.c> 
 OPTFFF 1,24,1,0,0,0,0,0,<.\listview.c><listview.c> 
-OPTFFF 1,25,1,0,0,0,0,0,<.\wm8753.c><wm8753.c> 
-OPTFFF 1,26,1,0,0,0,0,0,<.\player_ui.c><player_ui.c> 
-OPTFFF 1,27,1,0,0,0,0,0,<.\player_bg.c><player_bg.c> 
-OPTFFF 1,28,1,0,0,0,0,0,<.\wm8978.c><wm8978.c> 
-OPTFFF 1,29,1,469762048,0,0,0,0,<.\play_list.c><play_list.c> 
-OPTFFF 1,30,1,0,0,0,0,0,<.\ili9325\ili9320.c><ili9320.c> 
-OPTFFF 2,31,1,0,0,0,0,0,<..\..\src\clock.c><clock.c> 
-OPTFFF 2,32,1,0,0,0,0,0,<..\..\src\idle.c><idle.c> 
-OPTFFF 2,33,1,0,0,0,0,0,<..\..\src\ipc.c><ipc.c> 
-OPTFFF 2,34,1,0,0,0,0,0,<..\..\src\mempool.c><mempool.c> 
-OPTFFF 2,35,1,0,0,0,0,0,<..\..\src\mem.c><mem.c> 
-OPTFFF 2,36,1,0,0,0,0,0,<..\..\src\object.c><object.c> 
-OPTFFF 2,37,1,0,0,0,0,0,<..\..\src\scheduler.c><scheduler.c> 
-OPTFFF 2,38,1,0,0,0,0,0,<..\..\src\thread.c><thread.c> 
-OPTFFF 2,39,1,0,0,0,0,0,<..\..\src\timer.c><timer.c> 
-OPTFFF 2,40,1,0,0,0,0,0,<..\..\src\irq.c><irq.c> 
-OPTFFF 2,41,1,0,0,0,0,0,<..\..\src\kservice.c><kservice.c> 
-OPTFFF 2,42,1,0,0,0,0,0,<..\..\src\device.c><device.c> 
-OPTFFF 2,43,1,0,0,0,0,0,<..\..\src\slab.c><slab.c> 
-OPTFFF 3,44,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\stack.c><stack.c> 
-OPTFFF 3,45,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\interrupt.c><interrupt.c> 
-OPTFFF 3,46,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\cpu.c><cpu.c> 
-OPTFFF 3,47,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\serial.c><serial.c> 
-OPTFFF 3,48,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\context_rvds.S><context_rvds.S> 
-OPTFFF 3,49,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\start_rvds.s><start_rvds.s> 
-OPTFFF 3,50,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\fault.c><fault.c> 
-OPTFFF 3,51,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\fault_rvds.S><fault_rvds.S> 
-OPTFFF 4,52,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c><misc.c> 
-OPTFFF 4,53,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c><stm32f10x_adc.c> 
-OPTFFF 4,54,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c><stm32f10x_bkp.c> 
-OPTFFF 4,55,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c><stm32f10x_can.c> 
-OPTFFF 4,56,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c><stm32f10x_crc.c> 
-OPTFFF 4,57,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c><stm32f10x_dac.c> 
-OPTFFF 4,58,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c><stm32f10x_dbgmcu.c> 
-OPTFFF 4,59,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c><stm32f10x_dma.c> 
-OPTFFF 4,60,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c><stm32f10x_exti.c> 
-OPTFFF 4,61,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c><stm32f10x_flash.c> 
-OPTFFF 4,62,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c><stm32f10x_fsmc.c> 
-OPTFFF 4,63,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c><stm32f10x_gpio.c> 
-OPTFFF 4,64,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c><stm32f10x_i2c.c> 
-OPTFFF 4,65,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c><stm32f10x_iwdg.c> 
-OPTFFF 4,66,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c><stm32f10x_pwr.c> 
-OPTFFF 4,67,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c><stm32f10x_rcc.c> 
-OPTFFF 4,68,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c><stm32f10x_rtc.c> 
-OPTFFF 4,69,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c><stm32f10x_sdio.c> 
-OPTFFF 4,70,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c><stm32f10x_spi.c> 
-OPTFFF 4,71,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c><stm32f10x_tim.c> 
-OPTFFF 4,72,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c><stm32f10x_usart.c> 
-OPTFFF 4,73,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c><stm32f10x_wwdg.c> 
-OPTFFF 5,74,1,0,0,0,0,0,<.\Libraries\STM32_USB-FS-Device_Driver\src\otgd_fs_cal.c><otgd_fs_cal.c> 
-OPTFFF 5,75,1,0,0,0,0,0,<.\Libraries\STM32_USB-FS-Device_Driver\src\otgd_fs_dev.c><otgd_fs_dev.c> 
-OPTFFF 5,76,1,0,0,0,0,0,<.\Libraries\STM32_USB-FS-Device_Driver\src\otgd_fs_int.c><otgd_fs_int.c> 
-OPTFFF 5,77,1,0,0,0,0,0,<.\Libraries\STM32_USB-FS-Device_Driver\src\otgd_fs_pcd.c><otgd_fs_pcd.c> 
-OPTFFF 5,78,1,0,0,0,0,0,<.\Libraries\STM32_USB-FS-Device_Driver\src\usb_core.c><usb_core.c> 
-OPTFFF 5,79,1,0,0,0,0,0,<.\Libraries\STM32_USB-FS-Device_Driver\src\usb_init.c><usb_init.c> 
-OPTFFF 5,80,1,0,0,0,0,0,<.\Libraries\STM32_USB-FS-Device_Driver\src\usb_int.c><usb_int.c> 
-OPTFFF 5,81,1,0,0,0,0,0,<.\Libraries\STM32_USB-FS-Device_Driver\src\usb_mem.c><usb_mem.c> 
-OPTFFF 5,82,1,0,0,0,0,0,<.\Libraries\STM32_USB-FS-Device_Driver\src\usb_regs.c><usb_regs.c> 
-OPTFFF 5,83,1,0,0,0,0,0,<.\Libraries\STM32_USB-FS-Device_Driver\src\usb_sil.c><usb_sil.c> 
-OPTFFF 6,84,1,0,0,0,0,0,<.\Libraries\CMSIS\Core\CM3\core_cm3.c><core_cm3.c> 
-OPTFFF 6,85,1,0,0,0,0,0,<.\Libraries\CMSIS\Core\CM3\system_stm32f10x.c><system_stm32f10x.c> 
-OPTFFF 7,86,1,0,0,0,0,0,<..\..\finsh\finsh_compiler.c><finsh_compiler.c> 
-OPTFFF 7,87,1,0,0,0,0,0,<..\..\finsh\finsh_error.c><finsh_error.c> 
-OPTFFF 7,88,1,0,0,0,0,0,<..\..\finsh\finsh_heap.c><finsh_heap.c> 
-OPTFFF 7,89,1,0,0,0,0,0,<..\..\finsh\finsh_init.c><finsh_init.c> 
-OPTFFF 7,90,1,0,0,0,0,0,<..\..\finsh\finsh_node.c><finsh_node.c> 
-OPTFFF 7,91,1,0,0,0,0,0,<..\..\finsh\finsh_ops.c><finsh_ops.c> 
-OPTFFF 7,92,1,0,0,0,0,0,<..\..\finsh\finsh_parser.c><finsh_parser.c> 
-OPTFFF 7,93,1,0,0,0,0,0,<..\..\finsh\finsh_token.c><finsh_token.c> 
-OPTFFF 7,94,1,0,0,0,0,0,<..\..\finsh\finsh_var.c><finsh_var.c> 
-OPTFFF 7,95,1,0,0,0,0,0,<..\..\finsh\finsh_vm.c><finsh_vm.c> 
-OPTFFF 7,96,1,0,0,0,0,0,<..\..\finsh\shell.c><shell.c> 
-OPTFFF 7,97,1,0,0,0,0,0,<..\..\finsh\symbol.c><symbol.c> 
-OPTFFF 7,98,1,0,0,0,0,0,<..\..\finsh\cmd.c><cmd.c> 
-OPTFFF 8,99,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_init.c><dfs_init.c> 
-OPTFFF 8,100,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_fs.c><dfs_fs.c> 
-OPTFFF 8,101,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_raw.c><dfs_raw.c> 
-OPTFFF 8,102,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_util.c><dfs_util.c> 
-OPTFFF 8,103,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_posix.c><dfs_posix.c> 
-OPTFFF 8,104,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c><dir.c> 
-OPTFFF 8,105,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c><fat.c> 
-OPTFFF 8,106,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c><file.c> 
-OPTFFF 8,107,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c><fs.c> 
-OPTFFF 8,108,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c><ls.c> 
-OPTFFF 8,109,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c><time.c> 
-OPTFFF 8,110,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c><ui.c> 
-OPTFFF 8,111,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c><plibc.c> 
-OPTFFF 8,112,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c><efs.c> 
-OPTFFF 8,113,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c><extract.c> 
-OPTFFF 8,114,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c><partition.c> 
-OPTFFF 8,115,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_cache.c><dfs_cache.c> 
-OPTFFF 9,116,1,0,0,0,0,0,<..\..\net\lwip\src\core\dhcp.c><dhcp.c> 
-OPTFFF 9,117,1,0,0,0,0,0,<..\..\net\lwip\src\core\dns.c><dns.c> 
-OPTFFF 9,118,1,0,0,0,0,0,<..\..\net\lwip\src\core\init.c><init.c> 
-OPTFFF 9,119,1,0,0,0,0,0,<..\..\net\lwip\src\core\memp.c><memp.c> 
-OPTFFF 9,120,1,0,0,0,0,0,<..\..\net\lwip\src\core\netif.c><netif.c> 
-OPTFFF 9,121,1,0,0,0,0,0,<..\..\net\lwip\src\core\pbuf.c><pbuf.c> 
-OPTFFF 9,122,1,0,0,0,0,0,<..\..\net\lwip\src\core\raw.c><raw.c> 
-OPTFFF 9,123,1,0,0,0,0,0,<..\..\net\lwip\src\core\stats.c><stats.c> 
-OPTFFF 9,124,1,0,0,0,0,0,<..\..\net\lwip\src\core\sys.c><sys.c> 
-OPTFFF 9,125,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp.c><tcp.c> 
-OPTFFF 9,126,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_in.c><tcp_in.c> 
-OPTFFF 9,127,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_out.c><tcp_out.c> 
-OPTFFF 9,128,1,0,0,0,0,0,<..\..\net\lwip\src\core\udp.c><udp.c> 
-OPTFFF 9,129,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\autoip.c><autoip.c> 
-OPTFFF 9,130,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\icmp.c><icmp.c> 
-OPTFFF 9,131,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\igmp.c><igmp.c> 
-OPTFFF 9,132,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet.c><inet.c> 
-OPTFFF 9,133,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c> 
-OPTFFF 9,134,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip.c><ip.c> 
-OPTFFF 9,135,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c> 
-OPTFFF 9,136,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c> 
-OPTFFF 9,137,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_in.c><msg_in.c> 
-OPTFFF 9,138,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_out.c><msg_out.c> 
-OPTFFF 9,139,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_lib.c><api_lib.c> 
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+OPTFFF 9,129,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\icmp.c><icmp.c> 
+OPTFFF 9,130,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\igmp.c><igmp.c> 
+OPTFFF 9,131,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet.c><inet.c> 
+OPTFFF 9,132,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c> 
+OPTFFF 9,133,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip.c><ip.c> 
+OPTFFF 9,134,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c> 
+OPTFFF 9,135,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c> 
+OPTFFF 9,136,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_in.c><msg_in.c> 
+OPTFFF 9,137,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_out.c><msg_out.c> 
+OPTFFF 9,138,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_lib.c><api_lib.c> 
+OPTFFF 9,139,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_msg.c><api_msg.c> 
+OPTFFF 9,140,1,0,0,0,0,0,<..\..\net\lwip\src\api\err.c><err.c> 
+OPTFFF 9,141,1,0,0,0,0,0,<..\..\net\lwip\src\api\netbuf.c><netbuf.c> 
+OPTFFF 9,142,1,0,0,0,0,0,<..\..\net\lwip\src\api\netdb.c><netdb.c> 
+OPTFFF 9,143,1,0,0,0,0,0,<..\..\net\lwip\src\api\netifapi.c><netifapi.c> 
+OPTFFF 9,144,1,0,0,0,0,0,<..\..\net\lwip\src\api\tcpip.c><tcpip.c> 
+OPTFFF 9,145,1,0,0,0,0,0,<..\..\net\lwip\src\netif\etharp.c><etharp.c> 
+OPTFFF 9,146,1,0,0,0,0,0,<..\..\net\lwip\src\netif\ethernetif.c><ethernetif.c> 
+OPTFFF 9,147,1,0,0,0,0,0,<..\..\net\lwip\src\netif\loopif.c><loopif.c> 
+OPTFFF 9,148,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch_init.c><sys_arch_init.c> 
+OPTFFF 9,149,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch.c><sys_arch.c> 
+OPTFFF 9,150,1,0,0,0,0,0,<..\..\net\lwip\src\api\sockets.c><sockets.c> 
+OPTFFF 10,151,1,0,0,0,0,0,<.\mp3\mp3dec.c><mp3dec.c> 
+OPTFFF 10,152,1,0,0,0,0,0,<.\mp3\mp3tabs.c><mp3tabs.c> 
+OPTFFF 10,153,1,0,0,0,0,0,<.\mp3\real\bitstream.c><bitstream.c> 
+OPTFFF 10,154,1,0,0,0,0,0,<.\mp3\real\buffers.c><buffers.c> 
+OPTFFF 10,155,1,0,0,0,0,0,<.\mp3\real\dct32.c><dct32.c> 
+OPTFFF 10,156,1,0,0,0,0,0,<.\mp3\real\dequant.c><dequant.c> 
+OPTFFF 10,157,1,0,0,0,0,0,<.\mp3\real\dqchan.c><dqchan.c> 
+OPTFFF 10,158,1,0,0,0,0,0,<.\mp3\real\huffman.c><huffman.c> 
+OPTFFF 10,159,1,0,0,0,0,0,<.\mp3\real\hufftabs.c><hufftabs.c> 
+OPTFFF 10,160,1,0,0,0,0,0,<.\mp3\real\imdct.c><imdct.c> 
+OPTFFF 10,161,1,0,0,0,0,0,<.\mp3\real\scalfact.c><scalfact.c> 
+OPTFFF 10,162,1,0,0,0,0,0,<.\mp3\real\stproc.c><stproc.c> 
+OPTFFF 10,163,1,0,0,0,0,0,<.\mp3\real\subband.c><subband.c> 
+OPTFFF 10,164,1,0,0,0,0,0,<.\mp3\real\trigtabs.c><trigtabs.c> 
+OPTFFF 10,165,2,0,0,0,0,0,<.\mp3\real\arm\asmpoly_thumb2.s><asmpoly_thumb2.s> 
+OPTFFF 10,166,2,0,0,0,0,0,<.\mp3\real\arm\asmmisc.s><asmmisc.s> 
+OPTFFF 11,167,1,0,0,0,0,0,<..\..\rtgui\common\rtgui_object.c><rtgui_object.c> 
+OPTFFF 11,168,1,0,0,0,0,0,<..\..\rtgui\common\rtgui_system.c><rtgui_system.c> 
+OPTFFF 11,169,1,0,0,0,0,0,<..\..\rtgui\common\rtgui_theme.c><rtgui_theme.c> 
+OPTFFF 11,170,1,0,0,0,0,0,<..\..\rtgui\common\asc12font.c><asc12font.c> 
+OPTFFF 11,171,1,0,0,0,0,0,<..\..\rtgui\common\asc16font.c><asc16font.c> 
+OPTFFF 11,172,1,0,0,0,0,0,<..\..\rtgui\common\color.c><color.c> 
+OPTFFF 11,173,1,0,0,0,0,0,<..\..\rtgui\common\dc.c><dc.c> 
+OPTFFF 11,174,1,0,0,0,0,0,<..\..\rtgui\common\dc_buffer.c><dc_buffer.c> 
+OPTFFF 11,175,1,0,0,0,0,0,<..\..\rtgui\common\dc_hw.c><dc_hw.c> 
+OPTFFF 11,176,1,0,0,0,0,0,<..\..\rtgui\common\filerw.c><filerw.c> 
+OPTFFF 11,177,1,402653184,0,0,0,0,<..\..\rtgui\common\font.c><font.c> 
+OPTFFF 11,178,1,0,0,0,0,0,<..\..\rtgui\common\image.c><image.c> 
+OPTFFF 11,179,1,0,0,0,0,0,<..\..\rtgui\common\image_xpm.c><image_xpm.c> 
+OPTFFF 11,180,1,0,0,0,0,0,<..\..\rtgui\common\image_hdc.c><image_hdc.c> 
+OPTFFF 11,181,1,0,0,0,0,0,<..\..\rtgui\common\region.c><region.c> 
+OPTFFF 11,182,1,0,0,0,0,0,<..\..\rtgui\server\server.c><server.c> 
+OPTFFF 11,183,1,0,0,0,0,0,<..\..\rtgui\server\driver.c><driver.c> 
+OPTFFF 11,184,1,0,0,0,0,0,<..\..\rtgui\server\panel.c><panel.c> 
+OPTFFF 11,185,1,0,0,0,0,0,<..\..\rtgui\widgets\widget.c><widget.c> 
+OPTFFF 11,186,1,0,0,0,0,0,<..\..\rtgui\widgets\window.c><window.c> 
+OPTFFF 11,187,1,0,0,0,0,0,<..\..\rtgui\widgets\workbench.c><workbench.c> 
+OPTFFF 11,188,1,0,0,0,0,0,<..\..\rtgui\widgets\view.c><view.c> 
+OPTFFF 11,189,1,0,0,0,0,0,<..\..\rtgui\widgets\box.c><box.c> 
+OPTFFF 11,190,1,0,0,0,0,0,<..\..\rtgui\widgets\button.c><button.c> 
+OPTFFF 11,191,1,0,0,0,0,0,<..\..\rtgui\widgets\container.c><container.c> 
+OPTFFF 11,192,1,0,0,0,0,0,<..\..\rtgui\widgets\iconbox.c><iconbox.c> 
+OPTFFF 11,193,1,0,0,0,0,0,<..\..\rtgui\widgets\label.c><label.c> 
+OPTFFF 11,194,1,0,0,0,0,0,<..\..\rtgui\widgets\textbox.c><textbox.c> 
+OPTFFF 11,195,1,0,0,0,0,0,<..\..\rtgui\widgets\title.c><title.c> 
+OPTFFF 11,196,1,0,0,0,0,0,<..\..\rtgui\widgets\toplevel.c><toplevel.c> 
+OPTFFF 11,197,1,0,0,0,0,0,<..\..\rtgui\server\mouse.c><mouse.c> 
+OPTFFF 11,198,1,0,0,0,0,0,<..\..\rtgui\server\topwin.c><topwin.c> 
+OPTFFF 11,199,1,0,0,0,0,0,<..\..\rtgui\common\font_hz_file.c><font_hz_file.c> 
+OPTFFF 11,200,1,0,0,0,0,0,<..\..\rtgui\common\hz16font.c><hz16font.c> 
+OPTFFF 11,201,1,0,0,0,0,0,<..\..\rtgui\common\hz12font.c><hz12font.c> 
+OPTFFF 12,202,1,0,0,0,0,0,<.\Libraries\Mass_Storage\src\hw_config.c><hw_config.c> 
+OPTFFF 12,203,1,0,0,0,0,0,<.\Libraries\Mass_Storage\src\mass_mal.c><mass_mal.c> 
+OPTFFF 12,204,1,419430400,0,0,0,0,<.\Libraries\Mass_Storage\src\memory.c><memory.c> 
+OPTFFF 12,205,1,0,0,0,0,0,<.\Libraries\Mass_Storage\src\usb_bot.c><usb_bot.c> 
+OPTFFF 12,206,1,100663296,0,0,0,0,<.\Libraries\Mass_Storage\src\scsi_data.c><scsi_data.c> 
+OPTFFF 12,207,1,0,0,0,0,0,<.\Libraries\Mass_Storage\src\usb_desc.c><usb_desc.c> 
+OPTFFF 12,208,1,0,0,0,0,0,<.\Libraries\Mass_Storage\src\usb_endp.c><usb_endp.c> 
+OPTFFF 12,209,1,0,0,0,0,0,<.\Libraries\Mass_Storage\src\usb_istr.c><usb_istr.c> 
+OPTFFF 12,210,1,0,0,0,0,0,<.\Libraries\Mass_Storage\src\usb_prop.c><usb_prop.c> 
+OPTFFF 12,211,1,0,0,0,0,0,<.\Libraries\Mass_Storage\src\usb_pwr.c><usb_pwr.c> 
+OPTFFF 12,212,1,0,0,0,0,0,<.\Libraries\Mass_Storage\src\usb_scsi.c><usb_scsi.c> 
+OPTFFF 12,213,1,16777216,0,0,0,0,<.\Libraries\Mass_Storage\src\usb_main.c><usb_main.c> 
 
 
 TARGOPT 1, (RT-Thread STM32 Radio)
@@ -256,14 +255,14 @@ TARGOPT 1, (RT-Thread STM32 Radio)
   OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=60,91,584,445,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(126=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0))
   OPTKEY 0,(ARMDBGFLAGS)(-T0)
   OPTKEY 0,(DLGUARM)((105=150,189,819,540,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0))
-  OPTKEY 0,(JL2CM3)(-U11111117 -O718 -S10 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TRE0 -FO27 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)
-  OPTBB 0,0,72,1,134329864,0,0,0,0,1,<application.c>()()
-  OPTBB 1,0,151,1,134324618,0,0,0,0,1,<application.c>()()
+  OPTKEY 0,(JL2CM3)(-U20090110 -O718 -S10 -C0 -JU1 -JI127.0.0.1 -JP0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO27 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)
+  OPTBB 0,0,41,1,134368182,0,0,0,0,1,<rtgui_system.c>()()
+  OPTBB 1,0,44,1,134356542,0,0,0,0,1,<font.c>()()
   OPTWA 0,1,(_mp)
   OPTWA 1,1,(tinfo,0x0A)
   OPTMM 1,8,(text)
   OPTMM 2,8,(mimeBuffer)
-  OPTDF 0x82
+  OPTDF 0x86
   OPTLE <>
   OPTLC <>
 EndOpt

bsp/stm32_radio/project.Uv2

@@ -40,12 +40,11 @@ File 1,1,<.\info.c><info.c>
 File 1,1,<.\filelist.c><filelist.c>
 File 1,1,<.\device_info.c><device_info.c>
 File 1,1,<.\listview.c><listview.c>
-File 1,1,<.\wm8753.c><wm8753.c>
 File 1,1,<.\player_ui.c><player_ui.c>
 File 1,1,<.\player_bg.c><player_bg.c>
-File 1,1,<.\wm8978.c><wm8978.c>
 File 1,1,<.\play_list.c><play_list.c>
 File 1,1,<.\ili9325\ili9320.c><ili9320.c>
+File 1,1,<.\codec.c><codec.c>
 File 2,1,<..\..\src\clock.c><clock.c>
 File 2,1,<..\..\src\idle.c><idle.c>
 File 2,1,<..\..\src\ipc.c><ipc.c>
@@ -286,7 +285,7 @@ Options 1,0,0  // Target 'RT-Thread STM32 Radio'
  OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
  OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,8,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 }
  RV_STAVEC ()
- ADSCCFLG { 17,34,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCCFLG { 5,32,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
  ADSCMISC ()
  ADSCDEFN (USE_STDPERIPH_DRIVER, STM32F10X_HD,)
  ADSCUDEF ()

bsp/stm32_radio/stm32f10x_it.c

@@ -275,6 +275,21 @@ void EXTI3_IRQHandler(void)
 *******************************************************************************/
 void EXTI4_IRQHandler(void)
 {
+#ifdef RT_USING_LWIP
+	extern void rt_dm9000_isr(void);
+
+	/* enter interrupt */
+	rt_interrupt_enter();
+
+	rt_dm9000_isr();
+
+	/* Clear the Key Button EXTI line pending bit */
+	EXTI_ClearITPendingBit(EXTI_Line4);
+
+	/* leave interrupt */
+	rt_interrupt_leave();
+	rt_hw_interrupt_thread_switch();
+#endif
 }
 
 /*******************************************************************************