diff --git a/CHANGELOG.md b/CHANGELOG.md
index 4b25b41618c1249b97c3c812157ee6a9b6c6107e..5f0135078b7b30537e432aa7284304cad602199e 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -6,6 +6,7 @@ Please mark all changes in change log and use the issue from GitHub
 
 ## Bug
 -   \#2487 Remove timeout when creating collection in dev test
+-   \#2532 Fix Milvus docker image report illegal instruction
 -   \#2551 Fix test_hybrid_db and test_rpc error
 -   \#2582 CreateHybridIndex.cpp compile error
 
diff --git a/core/src/index/thirdparty/faiss/utils/instruction_set.h b/core/src/index/thirdparty/faiss/utils/instruction_set.h
index a20141f7141a6c83ff7f71ca27a5a8c8f2624896..90ccc2c3689cf92ba823d28b18d94aa243eabc96 100644
--- a/core/src/index/thirdparty/faiss/utils/instruction_set.h
+++ b/core/src/index/thirdparty/faiss/utils/instruction_set.h
@@ -3,6 +3,7 @@
 
 #include <array>
 #include <bitset>
+#include <cpuid.h>
 #include <cstring>
 #include <iostream>
 #include <string>
@@ -10,58 +11,6 @@
 
 namespace faiss {
 
-#if defined(__i386__) && defined(__PIC__)
-
-/* %ebx may be the PIC register.  */
-#if __GNUC__ >= 3
-
-#define __cpuid(level, a, b, c, d)           \
-    __asm__(                                 \
-        "xchg{l}\t{%%}ebx, %1\n\t"           \
-        "cpuid\n\t"                          \
-        "xchg{l}\t{%%}ebx, %1\n\t"           \
-        : "=a"(a), "=r"(b), "=c"(c), "=d"(d) \
-        : "0"(level))
-
-#define __cpuid_count(level, count, a, b, c, d) \
-    __asm__(                                    \
-        "xchg{l}\t{%%}ebx, %1\n\t"              \
-        "cpuid\n\t"                             \
-        "xchg{l}\t{%%}ebx, %1\n\t"              \
-        : "=a"(a), "=r"(b), "=c"(c), "=d"(d)    \
-        : "0"(level), "2"(count))
-
-#else /* __GNUC__ >= 3 */
-
-/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
-   nor alternatives in i386 code.  */
-#define __cpuid(level, a, b, c, d)           \
-    __asm__(                                 \
-        "xchgl\t%%ebx, %1\n\t"               \
-        "cpuid\n\t"                          \
-        "xchgl\t%%ebx, %1\n\t"               \
-        : "=a"(a), "=r"(b), "=c"(c), "=d"(d) \
-        : "0"(level))
-
-#define __cpuid_count(level, count, a, b, c, d) \
-    __asm__(                                    \
-        "xchgl\t%%ebx, %1\n\t"                  \
-        "cpuid\n\t"                             \
-        "xchgl\t%%ebx, %1\n\t"                  \
-        : "=a"(a), "=r"(b), "=c"(c), "=d"(d)    \
-        : "0"(level), "2"(count))
-
-#endif /* __GNUC__ >= 3 */
-
-#else /* defined(__i386__) && defined(__PIC__) */
-
-#define __cpuid(level, a, b, c, d) __asm__("cpuid\n\t" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(level))
-
-#define __cpuid_count(level, count, a, b, c, d) \
-    __asm__("cpuid\n\t" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(level), "2"(count))
-
-#endif /* defined(__i386__) && defined(__PIC__) */
-
 class InstructionSet {
  public:
     static InstructionSet&