diff --git a/bsp/wch/risc-v/Libraries/Kconfig b/bsp/wch/risc-v/Libraries/Kconfig index 298f56a9aabb403459d7fe6c592a31678a80a560..6dad90ac06ee49b1026c99e4bcfb3ad065049f10 100644 --- a/bsp/wch/risc-v/Libraries/Kconfig +++ b/bsp/wch/risc-v/Libraries/Kconfig @@ -14,6 +14,7 @@ config SOC_RISCV_SERIES_CH32V2 config SOC_RISCV_SERIES_CH32V3 bool select ARCH_RISCV + select ARCH_RISCV_FPU select SOC_RISCV_FAMILY_CH32 config SOC_FAMILY_CH56X diff --git a/bsp/wch/risc-v/ch32v208v-r0/.config b/bsp/wch/risc-v/ch32v208w-r0/.config similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/.config rename to bsp/wch/risc-v/ch32v208w-r0/.config diff --git a/bsp/wch/risc-v/ch32v208v-r0/Kconfig b/bsp/wch/risc-v/ch32v208w-r0/Kconfig similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/Kconfig rename to bsp/wch/risc-v/ch32v208w-r0/Kconfig diff --git a/bsp/wch/risc-v/ch32v208v-r0/SConscript b/bsp/wch/risc-v/ch32v208w-r0/SConscript similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/SConscript rename to bsp/wch/risc-v/ch32v208w-r0/SConscript diff --git a/bsp/wch/risc-v/ch32v208v-r0/SConstruct b/bsp/wch/risc-v/ch32v208w-r0/SConstruct similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/SConstruct rename to bsp/wch/risc-v/ch32v208w-r0/SConstruct diff --git a/bsp/wch/risc-v/ch32v208v-r0/applications/SConscript b/bsp/wch/risc-v/ch32v208w-r0/applications/SConscript similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/applications/SConscript rename to bsp/wch/risc-v/ch32v208w-r0/applications/SConscript diff --git a/bsp/wch/risc-v/ch32v208v-r0/applications/main.c b/bsp/wch/risc-v/ch32v208w-r0/applications/main.c similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/applications/main.c rename to bsp/wch/risc-v/ch32v208w-r0/applications/main.c diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/Kconfig b/bsp/wch/risc-v/ch32v208w-r0/board/Kconfig similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/board/Kconfig rename to bsp/wch/risc-v/ch32v208w-r0/board/Kconfig diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/SConscript b/bsp/wch/risc-v/ch32v208w-r0/board/SConscript similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/board/SConscript rename to bsp/wch/risc-v/ch32v208w-r0/board/SConscript diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/board.c b/bsp/wch/risc-v/ch32v208w-r0/board/board.c similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/board/board.c rename to bsp/wch/risc-v/ch32v208w-r0/board/board.c diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/board.h b/bsp/wch/risc-v/ch32v208w-r0/board/board.h similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/board/board.h rename to bsp/wch/risc-v/ch32v208w-r0/board/board.h diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/linker_scripts/link.lds b/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/board/linker_scripts/link.lds rename to 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bsp/wch/risc-v/ch32v208v-r0/README_zh.md rename to bsp/wch/risc-v/ch32v208w-r0/readme.md diff --git a/bsp/wch/risc-v/ch32v208v-r0/rtconfig.h b/bsp/wch/risc-v/ch32v208w-r0/rtconfig.h similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/rtconfig.h rename to bsp/wch/risc-v/ch32v208w-r0/rtconfig.h diff --git a/bsp/wch/risc-v/ch32v208v-r0/rtconfig.py b/bsp/wch/risc-v/ch32v208w-r0/rtconfig.py similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/rtconfig.py rename to bsp/wch/risc-v/ch32v208w-r0/rtconfig.py diff --git a/libcpu/risc-v/ch32/context_gcc.S b/libcpu/risc-v/ch32/context_gcc.S index 3d6af1793461933f2771a49d0b463f3b4805a09c..5e6567a79fe6468c81a315c538cb5c843d499c66 100644 --- a/libcpu/risc-v/ch32/context_gcc.S +++ b/libcpu/risc-v/ch32/context_gcc.S @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2021-09-09 WCH the first version + * 2022-12-27 WangShun Merge WCH series mcu port files */ #include "cpuport.h" diff --git a/libcpu/risc-v/ch32/cpuport.c b/libcpu/risc-v/ch32/cpuport.c index e42bab949ef1bf8a79d33a56f9619a88ade80f34..c1c609c58d9ae43d9936fccc5bbe376cc151766e 100644 --- a/libcpu/risc-v/ch32/cpuport.c +++ b/libcpu/risc-v/ch32/cpuport.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2021-09-09 WCH the first version + * 2022-12-27 WangShun Merge WCH series mcu port files */ #include diff --git a/libcpu/risc-v/ch32/interrupt_gcc.S b/libcpu/risc-v/ch32/interrupt_gcc.S index 96c61ddd33a62c314a8ef1037815762d01ef2216..4d16a5b05498cb9bfddc4444d68f45dfd82f6a76 100644 --- a/libcpu/risc-v/ch32/interrupt_gcc.S +++ b/libcpu/risc-v/ch32/interrupt_gcc.S @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2021-09-09 WCH the first version + * 2022-12-27 WangShun Merge WCH series mcu port files */ #include "cpuport.h" diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S index e458268e1166df8e2659da480b0f050f639c287b..dbb5f8f4b5c2fb641447ebd5096cab614663e36f 100644 --- a/libcpu/risc-v/common/context_gcc.S +++ b/libcpu/risc-v/common/context_gcc.S @@ -8,6 +8,7 @@ * 2018/10/28 Bernard The unify RISC-V porting implementation * 2018/12/27 Jesven Add SMP support * 2020/11/20 BalanceTWK Add FPU support + * 2022/12/28 WangShun Add macro to distinguish whether FPU is supported */ #define __ASSEMBLY__ @@ -212,8 +213,11 @@ rt_hw_context_switch_exit: csrw mepc, a0 LOAD x1, 1 * REGBYTES(sp) - + #ifdef ARCH_RISCV_FPU li t0, 0x00007800 + #else + li t0, 0x00001800 + #endif csrw mstatus, t0 LOAD a0, 2 * REGBYTES(sp) csrs mstatus, a0