diff --git a/components/utilities/zmodem/crc.h b/components/utilities/zmodem/crc.h index df0c5dd41a70c600866c1b9409d5706870294744..fd11c1960a7215b84644c6870f08afaef56b4f21 100644 --- a/components/utilities/zmodem/crc.h +++ b/components/utilities/zmodem/crc.h @@ -1,129 +1,129 @@ -/* - * crc calculation stuff - */ - -/* crctab calculated by Mark G. Mendel, Network Systems Corporation */ -static unsigned short crctab[256] = { - 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, - 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, - 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, - 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, - 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, - 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, - 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, - 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, - 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, - 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, - 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, - 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, - 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, - 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, - 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, - 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, - 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, - 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, - 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, - 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, - 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, - 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, - 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, - 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, - 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, - 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, - 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, - 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, - 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, - 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, - 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, - 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 -}; - -/* - * updcrc macro derived from article Copyright (C) 1986 Stephen Satchell. - * NOTE: First srgument must be in range 0 to 255. - * Second argument is referenced twice. - * - * Programmers may incorporate any or all code into their programs, - * giving proper credit within the source. Publication of the - * source routines is permitted so long as proper credit is given - * to Stephen Satchell, Satchell Evaluations and Chuck Forsberg, - * Omen Technology. - */ - -#define updcrc16(cp, crc) ( crctab[((crc >> 8) & 255)] ^ (crc << 8) ^ cp) - -/* - * Copyright (C) 1986 Gary S. Brown. You may use this program, or - * code or tables extracted from it, as desired without restriction. - */ - -/* First, the polynomial itself and its table of feedback terms. The */ -/* polynomial is */ -/* X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 */ -/* Note that we take it "backwards" and put the highest-order term in */ -/* the lowest-order bit. The X^32 term is "implied"; the LSB is the */ -/* X^31 term, etc. The X^0 term (usually shown as "+1") results in */ -/* the MSB being 1. */ - -/* Note that the usual hardware shift register implementation, which */ -/* is what we're using (we're merely optimizing it by doing eight-bit */ -/* chunks at a time) shifts bits into the lowest-order term. In our */ -/* implementation, that means shifting towards the right. Why do we */ -/* do it this way? Because the calculated CRC must be transmitted in */ -/* order from highest-order term to lowest-order term. UARTs transmit */ -/* characters in order from LSB to MSB. By storing the CRC this way, */ -/* we hand it to the UART in the order low-byte to high-byte; the UART */ -/* sends each low-bit to hight-bit; and the result is transmission bit */ -/* by bit from highest- to lowest-order term without requiring any bit */ -/* shuffling on our part. Reception works similarly. */ - -/* The feedback terms table consists of 256, 32-bit entries. Notes: */ -/* */ -/* The table can be generated at runtime if desired; code to do so */ -/* is shown later. It might not be obvious, but the feedback */ -/* terms simply represent the results of eight shift/xor opera- */ -/* tions for all combinations of data and CRC register values. */ -/* */ -/* The values must be right-shifted by eight bits by the "updcrc" */ -/* logic; the shift must be unsigned (bring in zeroes). On some */ -/* hardware you could probably optimize the shift in assembler by */ -/* using byte-swap instructions. */ - -static unsigned long cr3tab[] = { /* CRC polynomial 0xedb88320 */ -0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, -0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, -0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, -0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, -0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, -0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, -0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, -0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, -0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, -0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, -0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, -0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, -0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, -0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, -0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, -0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, -0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, -0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, -0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, -0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, -0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, -0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, -0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, -0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, -0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, -0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, -0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, -0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, -0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, -0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, -0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, -0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d -}; - -#define updcrc32(b, c) (cr3tab[((int)c ^ b) & 0xff] ^ ((c >> 8) & 0x00FFFFFF)) - -/* End of crc.c */ +/* + * crc calculation stuff + */ + +/* crctab calculated by Mark G. Mendel, Network Systems Corporation */ +static unsigned short crctab[256] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; + +/* + * updcrc macro derived from article Copyright (C) 1986 Stephen Satchell. + * NOTE: First srgument must be in range 0 to 255. + * Second argument is referenced twice. + * + * Programmers may incorporate any or all code into their programs, + * giving proper credit within the source. Publication of the + * source routines is permitted so long as proper credit is given + * to Stephen Satchell, Satchell Evaluations and Chuck Forsberg, + * Omen Technology. + */ + +#define updcrc16(cp, crc) ( crctab[((crc >> 8) & 255)] ^ (crc << 8) ^ cp) + +/* + * Copyright (C) 1986 Gary S. Brown. You may use this program, or + * code or tables extracted from it, as desired without restriction. + */ + +/* First, the polynomial itself and its table of feedback terms. The */ +/* polynomial is */ +/* X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 */ +/* Note that we take it "backwards" and put the highest-order term in */ +/* the lowest-order bit. The X^32 term is "implied"; the LSB is the */ +/* X^31 term, etc. The X^0 term (usually shown as "+1") results in */ +/* the MSB being 1. */ + +/* Note that the usual hardware shift register implementation, which */ +/* is what we're using (we're merely optimizing it by doing eight-bit */ +/* chunks at a time) shifts bits into the lowest-order term. In our */ +/* implementation, that means shifting towards the right. Why do we */ +/* do it this way? Because the calculated CRC must be transmitted in */ +/* order from highest-order term to lowest-order term. UARTs transmit */ +/* characters in order from LSB to MSB. By storing the CRC this way, */ +/* we hand it to the UART in the order low-byte to high-byte; the UART */ +/* sends each low-bit to hight-bit; and the result is transmission bit */ +/* by bit from highest- to lowest-order term without requiring any bit */ +/* shuffling on our part. Reception works similarly. */ + +/* The feedback terms table consists of 256, 32-bit entries. Notes: */ +/* */ +/* The table can be generated at runtime if desired; code to do so */ +/* is shown later. It might not be obvious, but the feedback */ +/* terms simply represent the results of eight shift/xor opera- */ +/* tions for all combinations of data and CRC register values. */ +/* */ +/* The values must be right-shifted by eight bits by the "updcrc" */ +/* logic; the shift must be unsigned (bring in zeroes). On some */ +/* hardware you could probably optimize the shift in assembler by */ +/* using byte-swap instructions. */ + +static unsigned long cr3tab[] = { /* CRC polynomial 0xedb88320 */ +0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, +0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, +0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, +0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, +0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, +0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, +0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, +0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, +0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, +0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, +0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, +0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, +0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, +0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, +0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, +0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, +0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, +0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, +0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, +0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, +0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, +0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, +0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, +0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, +0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, +0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, +0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, +0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, +0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, +0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, +0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, +0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +#define updcrc32(b, c) (cr3tab[((int)c ^ b) & 0xff] ^ ((c >> 8) & 0x00FFFFFF)) + +/* End of crc.c */ diff --git a/components/utilities/zmodem/rz.c b/components/utilities/zmodem/rz.c index 23e952b23dd34f694abf2c8291fda6c4694eeadd..1324b5994b873409b845e4fb932e1526ec5e4615 100644 --- a/components/utilities/zmodem/rz.c +++ b/components/utilities/zmodem/rz.c @@ -1,401 +1,401 @@ /* - * File : rz.c - * the implemention of receiving files from the remote computers + * File : rz.c + * the implemention of receiving files from the remote computers * through the zmodem protocol. * Change Logs: * Date Author Notes * 2011-03-29 itspy * 2011-12-12 aozima fixed syntax error. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "zdef.h" - - -void zr_start(char *path); -static rt_err_t zrec_init(rt_uint8_t *rxbuf, struct zfile *zf); -static rt_err_t zrec_files(struct zfile *zf); -static rt_err_t zwrite_file(rt_uint8_t *buf, rt_uint16_t size, struct zfile *zf); -static rt_err_t zrec_file_data(rt_uint8_t *buf, struct zfile *zf);; -static rt_err_t zrec_file(rt_uint8_t *rxbuf, struct zfile *zf); -static rt_err_t zget_file_info(char *name, struct zfile *zf); -static rt_err_t zwrite_file(rt_uint8_t *buf, rt_uint16_t size, struct zfile *zf); -static void zrec_ack_bibi(void); - - -/* start zmodem receive proccess */ -void zr_start(char *path) -{ - struct zfile *zf; - rt_uint8_t n; - char ch,*p,*q; - rt_err_t res = -RT_ERROR; - - zf = rt_malloc(sizeof(struct zfile)); - if (zf == RT_NULL) - { - rt_kprintf("zf: out of memory\r\n"); - return; - } - memset(zf, 0, sizeof(struct zfile)); - zf->fname = path; - zf->fd = -1; - res = zrec_files(zf); - p = zf->fname; - for (;;) - { - q = strstr(p,"/"); - if (q == RT_NULL) break; - p = q+1; - } - if (res == RT_EOK) - { - rt_kprintf("\b\b\bfile: %s \r\n",p); - rt_kprintf("size: %ld bytes\r\n",zf->bytes_received); - rt_kprintf("receive completed.\r\n"); - close(zf->fd); - rt_free(zf->fname); - } - else - { - rt_kprintf("\b\b\bfile: %s \r\n",p); - rt_kprintf("size: 0 bytes\r\n"); - rt_kprintf("receive failed.\r\n"); - if (zf->fd >= 0) - { - close(zf->fd); - unlink(zf->fname); /* remove this file */ - rt_free(zf->fname); - } - } - rt_free(zf); - /* waiting,clear console buffer */ - rt_thread_delay(RT_TICK_PER_SECOND/2); - while(1) - { - n=rt_device_read(shell->device, 0, &ch, 1); - if (n == 0) break; - } - - return ; -} - -/* receiver init, wait for ack */ -static rt_err_t zrec_init(rt_uint8_t *rxbuf, struct zfile *zf) -{ - rt_uint8_t err_cnt = 0; - rt_err_t res = -RT_ERROR; - - for (;;) - { - zput_pos(0L); - tx_header[ZF0] = ZF0_CMD; - tx_header[ZF1] = ZF1_CMD; - tx_header[ZF2] = ZF2_CMD; - zsend_hex_header(ZRINIT, tx_header); -again: - res = zget_header(rx_header); - switch(res) - { - case ZFILE: - ZF0_CMD = rx_header[ZF0]; - ZF1_CMD = rx_header[ZF1]; - ZF2_CMD = rx_header[ZF2]; - ZF3_CMD = rx_header[ZF3]; - res = zget_data(rxbuf, RX_BUFFER_SIZE); - if (res == GOTCRCW) - { - if ((res =zget_file_info((char*)rxbuf,zf))!= RT_EOK) - { - zsend_hex_header(ZSKIP, tx_header); - return (res); - } - return RT_EOK;; - } - zsend_hex_header(ZNAK, tx_header); - goto again; - case ZSINIT: - if (zget_data((rt_uint8_t*)Attn, ZATTNLEN) == GOTCRCW) /* send zack */ - { - zsend_hex_header(ZACK, tx_header); - goto again; - } - zsend_hex_header(ZNAK, tx_header); /* send znak */ - goto again; - case ZRQINIT: - continue; - case ZEOF: - continue; - case ZCOMPL: - goto again; - case ZFIN: /* end file session */ - zrec_ack_bibi(); - return res; - default: - if (++err_cnt >1000) return -RT_ERROR; - continue; - } - } -} - -/* receive files */ -static rt_err_t zrec_files(struct zfile *zf) -{ - rt_uint8_t *rxbuf; - rt_err_t res = -RT_ERROR; - - zinit_parameter(); - rxbuf = rt_malloc(RX_BUFFER_SIZE*sizeof(rt_uint8_t)); - if (rxbuf == RT_NULL) - { - rt_kprintf("rxbuf: out of memory\r\n"); - return -RT_ERROR; - } - rt_kprintf("\r\nrz: ready...\r\n"); /* here ready to receive things */ - if ((res = zrec_init(rxbuf,zf))!= RT_EOK) - { - rt_kprintf("\b\b\breceive init failed\r\n"); - rt_free(rxbuf); - return -RT_ERROR; - } - res = zrec_file(rxbuf,zf); - if (res == ZFIN) - { - rt_free(rxbuf); - return RT_EOK; /* if finish session */ - } - else if (res == ZCAN) - { - rt_free(rxbuf); - return ZCAN; /* cancel by sender */ - } - else - { - zsend_can(); - rt_free(rxbuf); - return res; - } -} -/* receive file */ -static rt_err_t zrec_file(rt_uint8_t *rxbuf, struct zfile *zf) -{ - rt_err_t res = - RT_ERROR; - rt_uint16_t err_cnt = 0; - - do - { - zput_pos(zf->bytes_received); - zsend_hex_header(ZRPOS, tx_header); -again: - res = zget_header(rx_header); - switch (res) - { - case ZDATA: - zget_pos(Rxpos); - if (Rxpos != zf->bytes_received) - { - zsend_break(Attn); - continue; - } - err_cnt = 0; - res = zrec_file_data(rxbuf,zf); - if (res == -RT_ERROR) - { - zsend_break(Attn); - continue; - } - else if (res == GOTCAN) return res; - else goto again; - case ZRPOS: - zget_pos(Rxpos); - continue; - case ZEOF: - err_cnt = 0; - zget_pos(Rxpos); - if (Rxpos != zf->bytes_received || Rxpos != zf->bytes_total) - { - continue; - } - return (zrec_init(rxbuf,zf)); /* resend ZRINIT packet,ready to receive next file */ - case ZFIN: - zrec_ack_bibi(); - return ZCOMPL; - case ZCAN: -#ifdef ZDEBUG - rt_kprintf("error code: sender cancelled \r\n"); -#endif - zf->bytes_received = 0L; /* throw the received data */ - return res; - case ZSKIP: - return res; - case -RT_ERROR: - zsend_break(Attn); - continue; - case ZNAK: - case TIMEOUT: - default: - continue; - } - } while(++err_cnt < 100); - - return res; -} - -/* proccess file infomation */ -static rt_err_t zget_file_info(char *name, struct zfile *zf) -{ - char *p; - char *full_path,*ptr; - rt_uint16_t i,len; - rt_err_t res = -RT_ERROR; - struct statfs buf; - struct stat finfo; - - if (zf->fname == RT_NULL) /* extract file path */ - { - len = strlen(name)+2; - } - else - len = strlen(zf->fname)+strlen(name)+2; - full_path = rt_malloc(len); - if (full_path == RT_NULL) - { - zsend_can(); - rt_kprintf("\b\b\bfull_path: out of memory\n"); - rt_free(full_path); - return -RT_ERROR; - } - memset(full_path,0,len); - - for (i=0,ptr=zf->fname;ifd=open(full_path, DFS_O_DIRECTORY,0)) < 0) - { - zsend_can(); - rt_kprintf("\b\b\bcan not open file:%s\r\n",zf->fname+1); - close(zf->fd); - zf->fd = -1; - rt_free(full_path); - return res; - } - fstat(zf->fd, &finfo); - if ((finfo.st_mode&S_IFDIR) != S_IFDIR) - { - close(zf->fd); - zf->fd = -1; - return res; - } - close(zf->fd); - /* get fullpath && file attributes */ - strcat(full_path,name); - zf->fname = full_path; - p = strlen(name)+name+1; - sscanf((const char *)p, "%ld%lo%o", &zf->bytes_total,&zf->ctime,&zf->mode); -#if defined(RT_USING_DFS) && defined(DFS_USING_WORKDIR) - dfs_statfs(working_directory,&buf); - if (zf->bytes_total > (buf.f_blocks * buf.f_bfree)) - { - zsend_can(); - rt_kprintf("\b\b\bnot enough disk space\r\n"); - zf->fd = -1; - rt_free(full_path); - return -RT_ERROR; - } -#else - buf = buf; -#endif - zf->bytes_received = 0L; - if ((zf->fd = open(zf->fname,DFS_O_CREAT|DFS_O_WRONLY,0)) < 0) /* create or replace exist file */ - { - zsend_can(); - rt_kprintf("\b\b\bcan not create file:%s \r\n",zf->fname); - return -RT_ERROR; - } - - return RT_EOK; -} - -/* receive file data,continously, no ack */ -static rt_err_t zrec_file_data(rt_uint8_t *buf, struct zfile *zf) -{ - rt_err_t res = -RT_ERROR; - -more_data: - res = zget_data(buf,RX_BUFFER_SIZE); - switch(res) - { - case GOTCRCW: /* zack received */ - zwrite_file(buf,Rxcount,zf); - zf->bytes_received += Rxcount; - zput_pos(zf->bytes_received); - zsend_line(XON); - zsend_hex_header(ZACK, tx_header); - return RT_EOK; - case GOTCRCQ: - zwrite_file(buf,Rxcount,zf); - zf->bytes_received += Rxcount; - zput_pos(zf->bytes_received); - zsend_hex_header(ZACK, tx_header); - goto more_data; - case GOTCRCG: - zwrite_file(buf,Rxcount,zf); - zf->bytes_received += Rxcount; - goto more_data; - case GOTCRCE: - zwrite_file(buf,Rxcount,zf); - zf->bytes_received += Rxcount; - return RT_EOK; - case GOTCAN: -#ifdef ZDEBUG - rt_kprintf("error code : ZCAN \r\n"); -#endif - return res; - case TIMEOUT: - return res; - case -RT_ERROR: - zsend_break(Attn); - return res; - default: - return res; - } -} - -/* write file */ -static rt_err_t zwrite_file(rt_uint8_t *buf,rt_uint16_t size, struct zfile *zf) -{ - return (write(zf->fd,buf,size)); -} - -/* ack bibi */ -static void zrec_ack_bibi(void) -{ - rt_uint8_t i; - - zput_pos(0L); - for (i=0;i<3;i++) - { - zsend_hex_header(ZFIN, tx_header); - switch (zread_line(100)) - { - case 'O': - zread_line(1); - return; - case RCDO: - return; - case TIMEOUT: - default: - break; - } - } -} - -/* end of rz.c */ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "zdef.h" + + +void zr_start(char *path); +static rt_err_t zrec_init(rt_uint8_t *rxbuf, struct zfile *zf); +static rt_err_t zrec_files(struct zfile *zf); +static rt_err_t zwrite_file(rt_uint8_t *buf, rt_uint16_t size, struct zfile *zf); +static rt_err_t zrec_file_data(rt_uint8_t *buf, struct zfile *zf);; +static rt_err_t zrec_file(rt_uint8_t *rxbuf, struct zfile *zf); +static rt_err_t zget_file_info(char *name, struct zfile *zf); +static rt_err_t zwrite_file(rt_uint8_t *buf, rt_uint16_t size, struct zfile *zf); +static void zrec_ack_bibi(void); + + +/* start zmodem receive proccess */ +void zr_start(char *path) +{ + struct zfile *zf; + rt_uint8_t n; + char ch,*p,*q; + rt_err_t res = -RT_ERROR; + + zf = rt_malloc(sizeof(struct zfile)); + if (zf == RT_NULL) + { + rt_kprintf("zf: out of memory\r\n"); + return; + } + memset(zf, 0, sizeof(struct zfile)); + zf->fname = path; + zf->fd = -1; + res = zrec_files(zf); + p = zf->fname; + for (;;) + { + q = strstr(p,"/"); + if (q == RT_NULL) break; + p = q+1; + } + if (res == RT_EOK) + { + rt_kprintf("\b\b\bfile: %s \r\n",p); + rt_kprintf("size: %ld bytes\r\n",zf->bytes_received); + rt_kprintf("receive completed.\r\n"); + close(zf->fd); + rt_free(zf->fname); + } + else + { + rt_kprintf("\b\b\bfile: %s \r\n",p); + rt_kprintf("size: 0 bytes\r\n"); + rt_kprintf("receive failed.\r\n"); + if (zf->fd >= 0) + { + close(zf->fd); + unlink(zf->fname); /* remove this file */ + rt_free(zf->fname); + } + } + rt_free(zf); + /* waiting,clear console buffer */ + rt_thread_delay(RT_TICK_PER_SECOND/2); + while(1) + { + n=rt_device_read(shell->device, 0, &ch, 1); + if (n == 0) break; + } + + return ; +} + +/* receiver init, wait for ack */ +static rt_err_t zrec_init(rt_uint8_t *rxbuf, struct zfile *zf) +{ + rt_uint8_t err_cnt = 0; + rt_err_t res = -RT_ERROR; + + for (;;) + { + zput_pos(0L); + tx_header[ZF0] = ZF0_CMD; + tx_header[ZF1] = ZF1_CMD; + tx_header[ZF2] = ZF2_CMD; + zsend_hex_header(ZRINIT, tx_header); +again: + res = zget_header(rx_header); + switch(res) + { + case ZFILE: + ZF0_CMD = rx_header[ZF0]; + ZF1_CMD = rx_header[ZF1]; + ZF2_CMD = rx_header[ZF2]; + ZF3_CMD = rx_header[ZF3]; + res = zget_data(rxbuf, RX_BUFFER_SIZE); + if (res == GOTCRCW) + { + if ((res =zget_file_info((char*)rxbuf,zf))!= RT_EOK) + { + zsend_hex_header(ZSKIP, tx_header); + return (res); + } + return RT_EOK;; + } + zsend_hex_header(ZNAK, tx_header); + goto again; + case ZSINIT: + if (zget_data((rt_uint8_t*)Attn, ZATTNLEN) == GOTCRCW) /* send zack */ + { + zsend_hex_header(ZACK, tx_header); + goto again; + } + zsend_hex_header(ZNAK, tx_header); /* send znak */ + goto again; + case ZRQINIT: + continue; + case ZEOF: + continue; + case ZCOMPL: + goto again; + case ZFIN: /* end file session */ + zrec_ack_bibi(); + return res; + default: + if (++err_cnt >1000) return -RT_ERROR; + continue; + } + } +} + +/* receive files */ +static rt_err_t zrec_files(struct zfile *zf) +{ + rt_uint8_t *rxbuf; + rt_err_t res = -RT_ERROR; + + zinit_parameter(); + rxbuf = rt_malloc(RX_BUFFER_SIZE*sizeof(rt_uint8_t)); + if (rxbuf == RT_NULL) + { + rt_kprintf("rxbuf: out of memory\r\n"); + return -RT_ERROR; + } + rt_kprintf("\r\nrz: ready...\r\n"); /* here ready to receive things */ + if ((res = zrec_init(rxbuf,zf))!= RT_EOK) + { + rt_kprintf("\b\b\breceive init failed\r\n"); + rt_free(rxbuf); + return -RT_ERROR; + } + res = zrec_file(rxbuf,zf); + if (res == ZFIN) + { + rt_free(rxbuf); + return RT_EOK; /* if finish session */ + } + else if (res == ZCAN) + { + rt_free(rxbuf); + return ZCAN; /* cancel by sender */ + } + else + { + zsend_can(); + rt_free(rxbuf); + return res; + } +} +/* receive file */ +static rt_err_t zrec_file(rt_uint8_t *rxbuf, struct zfile *zf) +{ + rt_err_t res = - RT_ERROR; + rt_uint16_t err_cnt = 0; + + do + { + zput_pos(zf->bytes_received); + zsend_hex_header(ZRPOS, tx_header); +again: + res = zget_header(rx_header); + switch (res) + { + case ZDATA: + zget_pos(Rxpos); + if (Rxpos != zf->bytes_received) + { + zsend_break(Attn); + continue; + } + err_cnt = 0; + res = zrec_file_data(rxbuf,zf); + if (res == -RT_ERROR) + { + zsend_break(Attn); + continue; + } + else if (res == GOTCAN) return res; + else goto again; + case ZRPOS: + zget_pos(Rxpos); + continue; + case ZEOF: + err_cnt = 0; + zget_pos(Rxpos); + if (Rxpos != zf->bytes_received || Rxpos != zf->bytes_total) + { + continue; + } + return (zrec_init(rxbuf,zf)); /* resend ZRINIT packet,ready to receive next file */ + case ZFIN: + zrec_ack_bibi(); + return ZCOMPL; + case ZCAN: +#ifdef ZDEBUG + rt_kprintf("error code: sender cancelled \r\n"); +#endif + zf->bytes_received = 0L; /* throw the received data */ + return res; + case ZSKIP: + return res; + case -RT_ERROR: + zsend_break(Attn); + continue; + case ZNAK: + case TIMEOUT: + default: + continue; + } + } while(++err_cnt < 100); + + return res; +} + +/* proccess file infomation */ +static rt_err_t zget_file_info(char *name, struct zfile *zf) +{ + char *p; + char *full_path,*ptr; + rt_uint16_t i,len; + rt_err_t res = -RT_ERROR; + struct statfs buf; + struct stat finfo; + + if (zf->fname == RT_NULL) /* extract file path */ + { + len = strlen(name)+2; + } + else + len = strlen(zf->fname)+strlen(name)+2; + full_path = rt_malloc(len); + if (full_path == RT_NULL) + { + zsend_can(); + rt_kprintf("\b\b\bfull_path: out of memory\n"); + rt_free(full_path); + return -RT_ERROR; + } + memset(full_path,0,len); + + for (i=0,ptr=zf->fname;ifd=open(full_path, DFS_O_DIRECTORY,0)) < 0) + { + zsend_can(); + rt_kprintf("\b\b\bcan not open file:%s\r\n",zf->fname+1); + close(zf->fd); + zf->fd = -1; + rt_free(full_path); + return res; + } + fstat(zf->fd, &finfo); + if ((finfo.st_mode&S_IFDIR) != S_IFDIR) + { + close(zf->fd); + zf->fd = -1; + return res; + } + close(zf->fd); + /* get fullpath && file attributes */ + strcat(full_path,name); + zf->fname = full_path; + p = strlen(name)+name+1; + sscanf((const char *)p, "%ld%lo%o", &zf->bytes_total,&zf->ctime,&zf->mode); +#if defined(RT_USING_DFS) && defined(DFS_USING_WORKDIR) + dfs_statfs(working_directory,&buf); + if (zf->bytes_total > (buf.f_blocks * buf.f_bfree)) + { + zsend_can(); + rt_kprintf("\b\b\bnot enough disk space\r\n"); + zf->fd = -1; + rt_free(full_path); + return -RT_ERROR; + } +#else + buf = buf; +#endif + zf->bytes_received = 0L; + if ((zf->fd = open(zf->fname,DFS_O_CREAT|DFS_O_WRONLY,0)) < 0) /* create or replace exist file */ + { + zsend_can(); + rt_kprintf("\b\b\bcan not create file:%s \r\n",zf->fname); + return -RT_ERROR; + } + + return RT_EOK; +} + +/* receive file data,continously, no ack */ +static rt_err_t zrec_file_data(rt_uint8_t *buf, struct zfile *zf) +{ + rt_err_t res = -RT_ERROR; + +more_data: + res = zget_data(buf,RX_BUFFER_SIZE); + switch(res) + { + case GOTCRCW: /* zack received */ + zwrite_file(buf,Rxcount,zf); + zf->bytes_received += Rxcount; + zput_pos(zf->bytes_received); + zsend_line(XON); + zsend_hex_header(ZACK, tx_header); + return RT_EOK; + case GOTCRCQ: + zwrite_file(buf,Rxcount,zf); + zf->bytes_received += Rxcount; + zput_pos(zf->bytes_received); + zsend_hex_header(ZACK, tx_header); + goto more_data; + case GOTCRCG: + zwrite_file(buf,Rxcount,zf); + zf->bytes_received += Rxcount; + goto more_data; + case GOTCRCE: + zwrite_file(buf,Rxcount,zf); + zf->bytes_received += Rxcount; + return RT_EOK; + case GOTCAN: +#ifdef ZDEBUG + rt_kprintf("error code : ZCAN \r\n"); +#endif + return res; + case TIMEOUT: + return res; + case -RT_ERROR: + zsend_break(Attn); + return res; + default: + return res; + } +} + +/* write file */ +static rt_err_t zwrite_file(rt_uint8_t *buf,rt_uint16_t size, struct zfile *zf) +{ + return (write(zf->fd,buf,size)); +} + +/* ack bibi */ +static void zrec_ack_bibi(void) +{ + rt_uint8_t i; + + zput_pos(0L); + for (i=0;i<3;i++) + { + zsend_hex_header(ZFIN, tx_header); + switch (zread_line(100)) + { + case 'O': + zread_line(1); + return; + case RCDO: + return; + case TIMEOUT: + default: + break; + } + } +} + +/* end of rz.c */ diff --git a/components/utilities/zmodem/sz.c b/components/utilities/zmodem/sz.c index ad30c973612b5a885bbac1b378d663aaa55b5a98..0fde4165f6603fb3dc3bd82ffeede4085567f31c 100644 --- a/components/utilities/zmodem/sz.c +++ b/components/utilities/zmodem/sz.c @@ -1,321 +1,321 @@ /* - * File : sz.c - * the implemention of sending files to the remote computers + * File : sz.c + * the implemention of sending files to the remote computers * through the zmodem protocol. * Change Logs: * Date Author Notes * 2011-03-29 itspy - */ - -#include -#include -#include -#include -#include -#include -#include -#include "zdef.h" - - -static rt_uint8_t TX_BUFFER[TX_BUFFER_SIZE]; /* sender buffer */ -static rt_uint8_t file_cnt = 0; /* count of number of files opened */ -static rt_uint8_t Rxflags = 0; /* rx parameter flags */ -static rt_uint8_t ZF2_OP; /* file transfer option */ - -void zs_start(char *path); -static void zsend_init(void); -static rt_err_t zsend_files(struct zfile *zf); -static rt_err_t zsend_file(struct zfile *zf, rt_uint8_t *buf, rt_uint16_t len); -static rt_err_t zsend_file_data(struct zfile *zf); -static rt_uint16_t zfill_buffer(struct zfile *zf, rt_uint8_t *buf, rt_uint16_t size); -static rt_err_t zget_sync(void); -static void zsay_bibi(void); - - - - -/* start zmodem send process */ -void zs_start(char *path) -{ - struct zfile *zf; - rt_err_t res = RT_ERROR; - char *p,*q; - zf = rt_malloc(sizeof(struct zfile)); - if (zf == RT_NULL) - { - rt_kprintf("zf: out of memory\r\n"); - return; - } - rt_kprintf("\r\nsz: ready...\r\n"); /* here ready to send things */ - memset(zf, 0, sizeof(struct zfile)); - zf->fname = path; - zf->fd = -1; - res = zsend_files(zf); - p = zf->fname; - for (;;) - { - q = strstr(p,"/"); - if (q == RT_NULL) break; - p = q+1; - } - if (res == RT_EOK) - { - rt_kprintf("\r\nfile: %s \r\nsize: %ld bytes\r\nsend completed.\r\n", - p,zf->bytes_received); - } - else - { - rt_kprintf("\r\nfile: %s \r\nsize: 0 bytes\r\nsend failed.\r\n",p); - } - rt_free(zf); - - return; -} - -/* init the parameters */ -static void zsend_init(void) -{ - rt_err_t res = -RT_ERROR; - - zinit_parameter(); - for(;;) /* wait ZPAD */ - { - res = zread_line(800); - if (res == ZPAD) break; - } - for (;;) - { - res = zget_header(rx_header); - if (res == ZRINIT) break; - } - if ((rx_header[ZF1] & ZRQNVH)) - { - zput_pos(0x80L); /* Show we can var header */ - zsend_hex_header(ZRQINIT, tx_header); - } - Rxflags = rx_header[ZF0] & 0377; - if (Rxflags & CANFC32) Txfcs32 = 1; /* used 32bits CRC check */ - - if (ZF2_OP == ZTRLE && (Rxflags & CANRLE)) /* for RLE packet */ - Txfcs32 = 2; - else - ZF2_OP = 0; - /* send SINIT cmd */ - return; -} - -/* send files */ -static rt_err_t zsend_files(struct zfile *zf) -{ - char *p,*q; - char *str = "/"; - struct stat finfo; - rt_err_t res = -RT_ERROR; - - if (zf->fname == RT_NULL) - { - rt_kprintf("\r\nerror: no file to be send.\r\n"); - return res; - } - if ((zf->fd=open(zf->fname, DFS_O_RDONLY,0)) <0) - { - rt_kprintf("\r\ncan not open file:%s\r\n",zf->fname+1); - return res; - } - - zf->file_end = 0; - ++file_cnt; - /* extract file name */ - p = zf->fname; - for (;;) - { - q = strstr(p,str); - if (q == RT_NULL) break; - p = q+1; - } - q = (char*)TX_BUFFER; - for (;;) - { - *q++ = *p++; - if (*p == 0) break; - } - *q++ = 0; - p=q; - while (q < (char*)(TX_BUFFER + 1024)) - *q++ = 0; - /* get file attributes */ - fstat(zf->fd,&finfo); - Left_sizes += finfo.st_size; - rt_sprintf(p, "%lu %lo %o 3 %d %ld", (long)finfo.st_size, finfo.st_mtime, - finfo.st_mode, file_cnt, Left_sizes); - Left_sizes -= finfo.st_size; - TX_BUFFER[127] = (finfo.st_size + 127) >>7; - TX_BUFFER[126] = (finfo.st_size + 127) >>15; - - zsend_init(); - /* start sending files */ - res = zsend_file(zf,TX_BUFFER, (p-(char*)TX_BUFFER)+strlen(p)+1); - zsay_bibi(); - close(zf->fd); - - return res; -} - -/* send file name and related info */ -static rt_err_t zsend_file(struct zfile *zf, rt_uint8_t *buf, rt_uint16_t len) -{ - rt_uint8_t cnt; - rt_err_t res = -RT_ERROR; - - for (cnt=0;cnt<5;cnt++) - { - tx_header[ZF0] = ZF0_CMD; /* file conversion option */ - tx_header[ZF1] = ZF1_CMD; /* file management option */ - tx_header[ZF2] = (ZF3_CMD|ZF2_OP); /* file transfer option */ - tx_header[ZF3] = ZF3_CMD; - zsend_bin_header(ZFILE, tx_header); - zsend_bin_data(buf, len, ZCRCW); -loop: - res = zget_header(rx_header); - switch (res) - { - case ZRINIT: - while ((res = zread_line(50)) > 0) - { - if (res == ZPAD) - { - goto loop; - } - } - break; - case ZCAN: - case TIMEOUT: - case ZABORT: - case ZFIN: - break; - case -RT_ERROR: - case ZNAK: - break; - case ZCRC: /* no CRC request */ - goto loop; - case ZFERR: - case ZSKIP: - break; - case ZRPOS: /* here we want */ - zget_pos(Rxpos); - Txpos = Rxpos; - return(zsend_file_data(zf)); - default: - break; - } - } - - return res; -} - -/* send the file data */ -static rt_err_t zsend_file_data(struct zfile *zf) -{ - rt_int16_t cnt; - rt_uint8_t cmd; - rt_err_t res = -RT_ERROR; - /* send ZDATA packet, start to send data */ -start_send: - zput_pos(Txpos); - zsend_bin_header(ZDATA, tx_header); - do - { - cnt = zfill_buffer(zf,TX_BUFFER,RX_BUFFER_SIZE); - if (cnt < RX_BUFFER_SIZE ) - cmd = ZCRCE; - else - cmd = ZCRCG; - zsend_bin_data(TX_BUFFER, cnt, cmd); - zf->bytes_received= Txpos += cnt; - if (cmd == ZCRCW) - goto get_syn1; - } while (cnt == RX_BUFFER_SIZE); - for (;;) /* get ack and check if send finish */ - { - zput_pos(Txpos); - zsend_bin_header(ZEOF, tx_header); -get_syn1: - res = zget_sync(); - switch (res) - { - case ZACK: - goto get_syn1; - case ZNAK: - continue; - case ZRPOS: /* resend here */ - lseek(zf->fd,Txpos,0); - goto start_send; - case ZRINIT: /* send finish,then begin to send next file */ - return RT_EOK; - case ZSKIP: - case -RT_ERROR: - return res; - default: - return res; - } - } -} - -/* fill file data to buffer*/ -static rt_uint16_t zfill_buffer(struct zfile *zf, rt_uint8_t *buf, rt_uint16_t size) -{ - return (read(zf->fd,buf,size)); -} - -/* wait sync(ack) from the receiver */ -static rt_err_t zget_sync(void) -{ - rt_err_t res = -RT_ERROR; - - for (;;) - { - res = zget_header(rx_header); - switch (res) - { - case ZCAN: - case ZABORT: - case ZFIN: - case TIMEOUT: - return -RT_ERROR; - case ZRPOS: /* get pos, need to resend */ - zget_pos(Rxpos); - Txpos = Rxpos; - return res; - case ZACK: - return res; - case ZRINIT: /* get ZRINIT indicate that the prev file send completed */ - return res; - case ZSKIP: - return res; - case -RT_ERROR: - default: - zsend_bin_header(ZNAK, tx_header); - continue; - } - } -} - -/* say "bibi" to the receiver */ -static void zsay_bibi(void) -{ - for (;;) - { - zput_pos(0L); /* reninit position of next file*/ - zsend_hex_header(ZFIN, tx_header); /* send finished session cmd */ - switch (zget_header(rx_header)) - { - case ZFIN: - zsend_line('O'); - zsend_line('O'); - case ZCAN: - case TIMEOUT: - return; - } - } -} -/* end of sz.c */ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "zdef.h" + + +static rt_uint8_t TX_BUFFER[TX_BUFFER_SIZE]; /* sender buffer */ +static rt_uint8_t file_cnt = 0; /* count of number of files opened */ +static rt_uint8_t Rxflags = 0; /* rx parameter flags */ +static rt_uint8_t ZF2_OP; /* file transfer option */ + +void zs_start(char *path); +static void zsend_init(void); +static rt_err_t zsend_files(struct zfile *zf); +static rt_err_t zsend_file(struct zfile *zf, rt_uint8_t *buf, rt_uint16_t len); +static rt_err_t zsend_file_data(struct zfile *zf); +static rt_uint16_t zfill_buffer(struct zfile *zf, rt_uint8_t *buf, rt_uint16_t size); +static rt_err_t zget_sync(void); +static void zsay_bibi(void); + + + + +/* start zmodem send process */ +void zs_start(char *path) +{ + struct zfile *zf; + rt_err_t res = RT_ERROR; + char *p,*q; + zf = rt_malloc(sizeof(struct zfile)); + if (zf == RT_NULL) + { + rt_kprintf("zf: out of memory\r\n"); + return; + } + rt_kprintf("\r\nsz: ready...\r\n"); /* here ready to send things */ + memset(zf, 0, sizeof(struct zfile)); + zf->fname = path; + zf->fd = -1; + res = zsend_files(zf); + p = zf->fname; + for (;;) + { + q = strstr(p,"/"); + if (q == RT_NULL) break; + p = q+1; + } + if (res == RT_EOK) + { + rt_kprintf("\r\nfile: %s \r\nsize: %ld bytes\r\nsend completed.\r\n", + p,zf->bytes_received); + } + else + { + rt_kprintf("\r\nfile: %s \r\nsize: 0 bytes\r\nsend failed.\r\n",p); + } + rt_free(zf); + + return; +} + +/* init the parameters */ +static void zsend_init(void) +{ + rt_err_t res = -RT_ERROR; + + zinit_parameter(); + for(;;) /* wait ZPAD */ + { + res = zread_line(800); + if (res == ZPAD) break; + } + for (;;) + { + res = zget_header(rx_header); + if (res == ZRINIT) break; + } + if ((rx_header[ZF1] & ZRQNVH)) + { + zput_pos(0x80L); /* Show we can var header */ + zsend_hex_header(ZRQINIT, tx_header); + } + Rxflags = rx_header[ZF0] & 0377; + if (Rxflags & CANFC32) Txfcs32 = 1; /* used 32bits CRC check */ + + if (ZF2_OP == ZTRLE && (Rxflags & CANRLE)) /* for RLE packet */ + Txfcs32 = 2; + else + ZF2_OP = 0; + /* send SINIT cmd */ + return; +} + +/* send files */ +static rt_err_t zsend_files(struct zfile *zf) +{ + char *p,*q; + char *str = "/"; + struct stat finfo; + rt_err_t res = -RT_ERROR; + + if (zf->fname == RT_NULL) + { + rt_kprintf("\r\nerror: no file to be send.\r\n"); + return res; + } + if ((zf->fd=open(zf->fname, DFS_O_RDONLY,0)) <0) + { + rt_kprintf("\r\ncan not open file:%s\r\n",zf->fname+1); + return res; + } + + zf->file_end = 0; + ++file_cnt; + /* extract file name */ + p = zf->fname; + for (;;) + { + q = strstr(p,str); + if (q == RT_NULL) break; + p = q+1; + } + q = (char*)TX_BUFFER; + for (;;) + { + *q++ = *p++; + if (*p == 0) break; + } + *q++ = 0; + p=q; + while (q < (char*)(TX_BUFFER + 1024)) + *q++ = 0; + /* get file attributes */ + fstat(zf->fd,&finfo); + Left_sizes += finfo.st_size; + rt_sprintf(p, "%lu %lo %o 3 %d %ld", (long)finfo.st_size, finfo.st_mtime, + finfo.st_mode, file_cnt, Left_sizes); + Left_sizes -= finfo.st_size; + TX_BUFFER[127] = (finfo.st_size + 127) >>7; + TX_BUFFER[126] = (finfo.st_size + 127) >>15; + + zsend_init(); + /* start sending files */ + res = zsend_file(zf,TX_BUFFER, (p-(char*)TX_BUFFER)+strlen(p)+1); + zsay_bibi(); + close(zf->fd); + + return res; +} + +/* send file name and related info */ +static rt_err_t zsend_file(struct zfile *zf, rt_uint8_t *buf, rt_uint16_t len) +{ + rt_uint8_t cnt; + rt_err_t res = -RT_ERROR; + + for (cnt=0;cnt<5;cnt++) + { + tx_header[ZF0] = ZF0_CMD; /* file conversion option */ + tx_header[ZF1] = ZF1_CMD; /* file management option */ + tx_header[ZF2] = (ZF3_CMD|ZF2_OP); /* file transfer option */ + tx_header[ZF3] = ZF3_CMD; + zsend_bin_header(ZFILE, tx_header); + zsend_bin_data(buf, len, ZCRCW); +loop: + res = zget_header(rx_header); + switch (res) + { + case ZRINIT: + while ((res = zread_line(50)) > 0) + { + if (res == ZPAD) + { + goto loop; + } + } + break; + case ZCAN: + case TIMEOUT: + case ZABORT: + case ZFIN: + break; + case -RT_ERROR: + case ZNAK: + break; + case ZCRC: /* no CRC request */ + goto loop; + case ZFERR: + case ZSKIP: + break; + case ZRPOS: /* here we want */ + zget_pos(Rxpos); + Txpos = Rxpos; + return(zsend_file_data(zf)); + default: + break; + } + } + + return res; +} + +/* send the file data */ +static rt_err_t zsend_file_data(struct zfile *zf) +{ + rt_int16_t cnt; + rt_uint8_t cmd; + rt_err_t res = -RT_ERROR; + /* send ZDATA packet, start to send data */ +start_send: + zput_pos(Txpos); + zsend_bin_header(ZDATA, tx_header); + do + { + cnt = zfill_buffer(zf,TX_BUFFER,RX_BUFFER_SIZE); + if (cnt < RX_BUFFER_SIZE ) + cmd = ZCRCE; + else + cmd = ZCRCG; + zsend_bin_data(TX_BUFFER, cnt, cmd); + zf->bytes_received= Txpos += cnt; + if (cmd == ZCRCW) + goto get_syn1; + } while (cnt == RX_BUFFER_SIZE); + for (;;) /* get ack and check if send finish */ + { + zput_pos(Txpos); + zsend_bin_header(ZEOF, tx_header); +get_syn1: + res = zget_sync(); + switch (res) + { + case ZACK: + goto get_syn1; + case ZNAK: + continue; + case ZRPOS: /* resend here */ + lseek(zf->fd,Txpos,0); + goto start_send; + case ZRINIT: /* send finish,then begin to send next file */ + return RT_EOK; + case ZSKIP: + case -RT_ERROR: + return res; + default: + return res; + } + } +} + +/* fill file data to buffer*/ +static rt_uint16_t zfill_buffer(struct zfile *zf, rt_uint8_t *buf, rt_uint16_t size) +{ + return (read(zf->fd,buf,size)); +} + +/* wait sync(ack) from the receiver */ +static rt_err_t zget_sync(void) +{ + rt_err_t res = -RT_ERROR; + + for (;;) + { + res = zget_header(rx_header); + switch (res) + { + case ZCAN: + case ZABORT: + case ZFIN: + case TIMEOUT: + return -RT_ERROR; + case ZRPOS: /* get pos, need to resend */ + zget_pos(Rxpos); + Txpos = Rxpos; + return res; + case ZACK: + return res; + case ZRINIT: /* get ZRINIT indicate that the prev file send completed */ + return res; + case ZSKIP: + return res; + case -RT_ERROR: + default: + zsend_bin_header(ZNAK, tx_header); + continue; + } + } +} + +/* say "bibi" to the receiver */ +static void zsay_bibi(void) +{ + for (;;) + { + zput_pos(0L); /* reninit position of next file*/ + zsend_hex_header(ZFIN, tx_header); /* send finished session cmd */ + switch (zget_header(rx_header)) + { + case ZFIN: + zsend_line('O'); + zsend_line('O'); + case ZCAN: + case TIMEOUT: + return; + } + } +} +/* end of sz.c */ diff --git a/components/utilities/zmodem/zcore.c b/components/utilities/zmodem/zcore.c index cd52e2b245f873dbad71bef7e463f20aed2e82e6..02ffbba830bd656a9cf7e449af1f5f755e9fae0d 100644 --- a/components/utilities/zmodem/zcore.c +++ b/components/utilities/zmodem/zcore.c @@ -1,27 +1,27 @@ /* - * File : rz.c + * File : rz.c * the core functions of implementing zmodem protocol * Change Logs: * Date Author Notes * 2011-03-29 itspy - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "zdef.h" + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "zdef.h" char ZF0_CMD; /* file conversion request */ char ZF1_CMD; /* file management request */ -char ZF2_CMD; /* file transport request */ +char ZF2_CMD; /* file transport request */ char ZF3_CMD; rt_uint8_t Rxframeind; /* ZBIN ZBIN32, or ZHEX type of frame */ -rt_uint16_t Rxcount; /* received count*/ +rt_uint16_t Rxcount; /* received count*/ char header_type; /* header type */ rt_uint8_t rx_header[4]; /* received header */ rt_uint8_t tx_header[4]; /* transmitted header */ @@ -29,116 +29,116 @@ rt_uint32_t Rxpos; /* received file position */ rt_uint32_t Txpos; /* transmitted file position */ rt_uint8_t Txfcs32; /* TURE means send binary frames with 32 bit FCS */ rt_uint8_t TxCRC; /* controls 32 bit CRC being sent */ -rt_uint8_t RxCRC; /* indicates/controls 32 bit CRC being received */ +rt_uint8_t RxCRC; /* indicates/controls 32 bit CRC being received */ /* 0 == CRC16, 1 == CRC32, 2 == CRC32 + RLE */ -char Attn[ZATTNLEN+1]; /* attention string rx sends to tx on err */ - -void zinit_parameter(void); -void zsend_bin_header(rt_uint8_t type, rt_uint8_t *hdr); -void zsend_hex_header(rt_uint8_t type, rt_uint8_t *hdr); -void zsend_bin_data(rt_uint8_t *buf, rt_int16_t len, rt_uint8_t frameend); -static rt_int16_t zrec_data16(rt_uint8_t *buf, rt_uint16_t len); -static rt_int16_t zrec_data32(rt_uint8_t *buf, rt_int16_t len); -static rt_int16_t zrec_data32r(rt_uint8_t *buf, rt_int16_t len); -rt_int16_t zget_data(rt_uint8_t *buf, rt_uint16_t len); -rt_int16_t zget_header(rt_uint8_t *hdr); -static rt_int16_t zget_bin_header(rt_uint8_t *hdr); -static rt_int16_t zget_bin_fcs(rt_uint8_t *hdr); -rt_int16_t zget_hex_header(rt_uint8_t *hdr); -static void zsend_ascii(rt_uint8_t c); -void zsend_zdle_char(rt_uint16_t ch); -static rt_int16_t zget_hex(void); -rt_int16_t zread_byte(void); -rt_int16_t zxor_read(void); -void zput_pos(rt_uint32_t pos); -void zget_pos(rt_uint32_t pos); - - - - -void zinit_parameter(void) -{ - rt_uint8_t i; - - ZF0_CMD = CANFC32|CANFDX|CANOVIO; /* not chose CANFC32,CANRLE,although it have been supported */ - ZF1_CMD = 0; /* fix header length,not support CANVHDR */ - ZF2_CMD = 0; - ZF3_CMD = 0; - Rxframeind =0; - header_type = 0; - Rxcount = 0; - for (i=0;i<4;i++) rx_header[i] = tx_header[i] = 0; - Rxpos = Txpos = 0; - RxCRC = 0; - Txfcs32 = 0; - - return ; -} - +char Attn[ZATTNLEN+1]; /* attention string rx sends to tx on err */ + +void zinit_parameter(void); +void zsend_bin_header(rt_uint8_t type, rt_uint8_t *hdr); +void zsend_hex_header(rt_uint8_t type, rt_uint8_t *hdr); +void zsend_bin_data(rt_uint8_t *buf, rt_int16_t len, rt_uint8_t frameend); +static rt_int16_t zrec_data16(rt_uint8_t *buf, rt_uint16_t len); +static rt_int16_t zrec_data32(rt_uint8_t *buf, rt_int16_t len); +static rt_int16_t zrec_data32r(rt_uint8_t *buf, rt_int16_t len); +rt_int16_t zget_data(rt_uint8_t *buf, rt_uint16_t len); +rt_int16_t zget_header(rt_uint8_t *hdr); +static rt_int16_t zget_bin_header(rt_uint8_t *hdr); +static rt_int16_t zget_bin_fcs(rt_uint8_t *hdr); +rt_int16_t zget_hex_header(rt_uint8_t *hdr); +static void zsend_ascii(rt_uint8_t c); +void zsend_zdle_char(rt_uint16_t ch); +static rt_int16_t zget_hex(void); +rt_int16_t zread_byte(void); +rt_int16_t zxor_read(void); +void zput_pos(rt_uint32_t pos); +void zget_pos(rt_uint32_t pos); + + + + +void zinit_parameter(void) +{ + rt_uint8_t i; + + ZF0_CMD = CANFC32|CANFDX|CANOVIO; /* not chose CANFC32,CANRLE,although it have been supported */ + ZF1_CMD = 0; /* fix header length,not support CANVHDR */ + ZF2_CMD = 0; + ZF3_CMD = 0; + Rxframeind =0; + header_type = 0; + Rxcount = 0; + for (i=0;i<4;i++) rx_header[i] = tx_header[i] = 0; + Rxpos = Txpos = 0; + RxCRC = 0; + Txfcs32 = 0; + + return ; +} + /* send binary header */ void zsend_bin_header(rt_uint8_t type, rt_uint8_t *hdr) { rt_uint8_t i; - rt_uint32_t crc; + rt_uint32_t crc; - zsend_byte(ZPAD); + zsend_byte(ZPAD); zsend_byte(ZDLE); - TxCRC = Txfcs32; - if (TxCRC == 0) + TxCRC = Txfcs32; + if (TxCRC == 0) { - zsend_byte(ZBIN); - zsend_zdle_char(type); - /* add 16bits crc */ - crc = 0L; - crc = updcrc16(type, 0); - for (i=0;i<4;i++) - { - zsend_zdle_char(*hdr); - crc = updcrc16((0377 & *hdr++),crc); - } + zsend_byte(ZBIN); + zsend_zdle_char(type); + /* add 16bits crc */ + crc = 0L; + crc = updcrc16(type, 0); + for (i=0;i<4;i++) + { + zsend_zdle_char(*hdr); + crc = updcrc16((0377 & *hdr++),crc); + } crc = updcrc16(0,updcrc16(0,crc)); zsend_zdle_char(((int)(crc>>8))); - zsend_zdle_char(crc); - } - else if(TxCRC == 1) - { - zsend_byte(ZBIN32); - zsend_zdle_char(type); - /* add 32bits crc */ - crc = 0xffffffffL; - crc = updcrc32(type, crc); - for (i=0;i<4;i++) - { - zsend_zdle_char(*hdr); - crc = updcrc32((0377 & *hdr++), crc); - } + zsend_zdle_char(crc); + } + else if(TxCRC == 1) + { + zsend_byte(ZBIN32); + zsend_zdle_char(type); + /* add 32bits crc */ + crc = 0xffffffffL; + crc = updcrc32(type, crc); + for (i=0;i<4;i++) + { + zsend_zdle_char(*hdr); + crc = updcrc32((0377 & *hdr++), crc); + } crc = ~crc; - for (i=0; i<4;i++) + for (i=0; i<4;i++) { zsend_zdle_char(crc); crc >>= 8; - } - } - else if (TxCRC == 2) - { - zsend_byte(ZBINR32); - zsend_zdle_char(type); - /* add 32bits crc */ - crc = 0xffffffffL; - crc = updcrc32(type, crc); - for (i=0;i<4;i++) - { - zsend_zdle_char(*hdr); - crc = updcrc32((0377 & *hdr++), crc); - } + } + } + else if (TxCRC == 2) + { + zsend_byte(ZBINR32); + zsend_zdle_char(type); + /* add 32bits crc */ + crc = 0xffffffffL; + crc = updcrc32(type, crc); + for (i=0;i<4;i++) + { + zsend_zdle_char(*hdr); + crc = updcrc32((0377 & *hdr++), crc); + } crc = ~crc; - for (i=0; i<4;i++) + for (i=0; i<4;i++) { zsend_zdle_char(crc); crc >>= 8; - } - } - + } + } + return; } @@ -146,53 +146,53 @@ void zsend_bin_header(rt_uint8_t type, rt_uint8_t *hdr) void zsend_hex_header(rt_uint8_t type, rt_uint8_t *hdr) { rt_uint8_t i; - rt_uint16_t crc; + rt_uint16_t crc; zsend_line(ZPAD); zsend_line(ZPAD); zsend_line(ZDLE); zsend_line(ZHEX); zsend_ascii(type); crc = updcrc16(type, 0); - for (i=0; i<4; i++) + for (i=0; i<4; i++) { - zsend_ascii(*hdr); + zsend_ascii(*hdr); crc = updcrc16((0377 & *hdr++), crc); } crc = updcrc16(0,updcrc16(0,crc)); - zsend_ascii(crc>>8); + zsend_ascii(crc>>8); zsend_ascii(crc); /* send display control cmd */ zsend_line(015); zsend_line(0212); if (type != ZFIN && type != ZACK) - zsend_line(021); - TxCRC = 0; /* clear tx crc type */ - + zsend_line(021); + TxCRC = 0; /* clear tx crc type */ + return; } /* send binary data,with frameend */ void zsend_bin_data(rt_uint8_t *buf, rt_int16_t len, rt_uint8_t frameend) -{ +{ rt_int16_t i,c,tmp; - rt_uint32_t crc; + rt_uint32_t crc; - if (TxCRC == 0) /* send binary data with 16bits crc check */ - { + if (TxCRC == 0) /* send binary data with 16bits crc check */ + { crc = 0x0L; - for (i=0;i>8); - zsend_zdle_char(crc); - } - else if (TxCRC == 1) /* send binary data with 32 bits crc check */ - { + zsend_zdle_char(crc>>8); + zsend_zdle_char(crc); + } + else if (TxCRC == 1) /* send binary data with 32 bits crc check */ + { crc = 0xffffffffL; - for (i=0;i>= 8; - } - } - else if (TxCRC == 2) /* send binary data with 32bits crc check,RLE encode */ - { - crc = 0xffffffffL; + } + } + else if (TxCRC == 2) /* send binary data with 32bits crc check,RLE encode */ + { + crc = 0xffffffffL; tmp = *buf++ & 0377; - for (i = 0; --len >= 0; ++buf) + for (i = 0; --len >= 0; ++buf) { - if ((c = *buf & 0377) == tmp && i < 126 && len>0) + if ((c = *buf & 0377) == tmp && i < 126 && len>0) { ++i; continue; } - if (i==0) + if (i==0) { zsend_zdle_char(tmp); crc = updcrc32(tmp, crc); - if (tmp == ZRESC) + if (tmp == ZRESC) { zsend_zdle_char(0100); crc = updcrc32(0100, crc); } - tmp = c; - } - else if (i == 1) - { - if (tmp != ZRESC) + tmp = c; + } + else if (i == 1) + { + if (tmp != ZRESC) { zsend_zdle_char(tmp); zsend_zdle_char(tmp); crc = updcrc32(tmp, crc); crc = updcrc32(tmp, crc); i = 0; tmp = c; - } - - } - else - { + } + + } + else + { zsend_zdle_char(ZRESC); crc = updcrc32(ZRESC, crc); - if (tmp == 040 && i < 34) + if (tmp == 040 && i < 34) { i += 036; - zsend_zdle_char(i); + zsend_zdle_char(i); crc = updcrc32(i, crc); } - else + else { i += 0101; zsend_zdle_char(i); crc = updcrc32(i, crc); zsend_zdle_char(tmp); crc = updcrc32(tmp, crc); } - i = 0; tmp = c; + i = 0; tmp = c; } } zsend_byte(ZDLE); zsend_byte(frameend); crc = updcrc32(frameend, crc); crc = ~crc; - for (i=0;i<4;i++) + for (i=0;i<4;i++) { - zsend_zdle_char(crc); + zsend_zdle_char(crc); crc >>= 8; - } + } } if (frameend == ZCRCW) - zsend_byte(XON); - + zsend_byte(XON); + return; -} - -/* receive data,with 16bits CRC check */ -static rt_int16_t zrec_data16(rt_uint8_t *buf, rt_uint16_t len) -{ +} + +/* receive data,with 16bits CRC check */ +static rt_int16_t zrec_data16(rt_uint8_t *buf, rt_uint16_t len) +{ rt_int16_t c,crc_cnt; - rt_uint16_t crc; - rt_err_t res = -RT_ERROR; - rt_uint8_t *p,flag = 0; - - p = buf; - crc_cnt = 0; crc = 0L; + rt_uint16_t crc; + rt_err_t res = -RT_ERROR; + rt_uint8_t *p,flag = 0; + + p = buf; + crc_cnt = 0; crc = 0L; Rxcount = 0; - while(buf <= p+len) - { - if ((res = zread_byte()) & ~0377) - { - if (res == GOTCRCE || res == GOTCRCG || - res == GOTCRCQ || res == GOTCRCW) - { - c = res; + while(buf <= p+len) + { + if ((res = zread_byte()) & ~0377) + { + if (res == GOTCRCE || res == GOTCRCG || + res == GOTCRCQ || res == GOTCRCW) + { + c = res; c = res; - crc = updcrc16(res&0377, crc); - flag = 1; - continue; - } - else if (res == GOTCAN) return ZCAN; - else if (res == TIMEOUT) return TIMEOUT; - else return res; - - } - else - { - if (flag) - { - crc = updcrc16(res, crc); - crc_cnt++; - if (crc_cnt < 2) continue; - if ((crc & 0xffff)) - { + crc = updcrc16(res&0377, crc); + flag = 1; + continue; + } + else if (res == GOTCAN) return ZCAN; + else if (res == TIMEOUT) return TIMEOUT; + else return res; + + } + else + { + if (flag) + { + crc = updcrc16(res, crc); + crc_cnt++; + if (crc_cnt < 2) continue; + if ((crc & 0xffff)) + { #ifdef ZDEBUG - rt_kprintf("error code: CRC16 error \r\n"); + rt_kprintf("error code: CRC16 error \r\n"); #endif - return -RT_ERROR; - } - return c; - } - else - { - *buf++ = res; - Rxcount++; - crc = updcrc16(res, crc); - } + return -RT_ERROR; + } + return c; + } + else + { + *buf++ = res; + Rxcount++; + crc = updcrc16(res, crc); + } } - } - - return -RT_ERROR; -} + } + + return -RT_ERROR; +} /* receive data,with 32bits CRC check */ static rt_int16_t zrec_data32(rt_uint8_t *buf, rt_int16_t len) { rt_int16_t c,crc_cnt; rt_uint32_t crc; - rt_err_t res = -RT_ERROR; - rt_uint8_t *p,flag = 0; + rt_err_t res = -RT_ERROR; + rt_uint8_t *p,flag = 0; - crc_cnt = 0; crc = 0xffffffffL; + crc_cnt = 0; crc = 0xffffffffL; Rxcount = 0; - while (buf <= p+len) - { - if ((res = zread_byte()) & ~0377) - { - if (res == GOTCRCE || res == GOTCRCG || - res == GOTCRCQ || res == GOTCRCW) - { + while (buf <= p+len) + { + if ((res = zread_byte()) & ~0377) + { + if (res == GOTCRCE || res == GOTCRCG || + res == GOTCRCQ || res == GOTCRCW) + { c = res; - crc = updcrc32(res&0377, crc); - flag = 1; - continue; - } - else if (res == GOTCAN) return ZCAN; - else if (res == TIMEOUT) return TIMEOUT; - else return res; - - } - else - { - if (flag) - { - crc = updcrc32(res, crc); - crc_cnt++; - if (crc_cnt < 4) continue; - if ((crc & 0xDEBB20E3)) - { + crc = updcrc32(res&0377, crc); + flag = 1; + continue; + } + else if (res == GOTCAN) return ZCAN; + else if (res == TIMEOUT) return TIMEOUT; + else return res; + + } + else + { + if (flag) + { + crc = updcrc32(res, crc); + crc_cnt++; + if (crc_cnt < 4) continue; + if ((crc & 0xDEBB20E3)) + { #ifdef ZDEBUG - rt_kprintf("error code: CRC32 error \r\n"); + rt_kprintf("error code: CRC32 error \r\n"); #endif - return -RT_ERROR; - } - return c; - } - else - { - *buf++ = res; - Rxcount++; - crc = updcrc32(res, crc); - } + return -RT_ERROR; + } + return c; + } + else + { + *buf++ = res; + Rxcount++; + crc = updcrc32(res, crc); + } } - } + } return -RT_ERROR; -} +} /* receive data,with RLE encoded,32bits CRC check */ static rt_int16_t zrec_data32r(rt_uint8_t *buf, rt_int16_t len) { rt_int16_t c,crc_cnt; rt_uint32_t crc; - rt_err_t res = -RT_ERROR; - rt_uint8_t *p,flag = 0; + rt_err_t res = -RT_ERROR; + rt_uint8_t *p,flag = 0; - crc_cnt = 0; crc = 0xffffffffL; - Rxcount = 0; + crc_cnt = 0; crc = 0xffffffffL; + Rxcount = 0; p = buf; - while (buf <= p+len) + while (buf <= p+len) { - if ((res = zread_byte()) & ~0377) - { - if (res == GOTCRCE || res == GOTCRCG || - res == GOTCRCQ || res == GOTCRCW) - { + if ((res = zread_byte()) & ~0377) + { + if (res == GOTCRCE || res == GOTCRCG || + res == GOTCRCQ || res == GOTCRCW) + { c = res; - crc = updcrc32(res&0377, crc); - flag = 1; - continue; - } - else if (res == GOTCAN) return ZCAN; - else if (res == TIMEOUT) return TIMEOUT; - else return res; - - } - else - { - if (flag) - { - crc = updcrc32(res, crc); - crc_cnt++; - if (crc_cnt < 4) continue; - if ((crc & 0xDEBB20E3)) - { + crc = updcrc32(res&0377, crc); + flag = 1; + continue; + } + else if (res == GOTCAN) return ZCAN; + else if (res == TIMEOUT) return TIMEOUT; + else return res; + + } + else + { + if (flag) + { + crc = updcrc32(res, crc); + crc_cnt++; + if (crc_cnt < 4) continue; + if ((crc & 0xDEBB20E3)) + { #ifdef ZDEBUG - rt_kprintf("error code: CRC32 error \r\n"); + rt_kprintf("error code: CRC32 error \r\n"); #endif - return -RT_ERROR; - } - return c; - } - else - { + return -RT_ERROR; + } + return c; + } + else + { crc = updcrc32(res, crc); - switch (c) + switch (c) { case 0: - if (res == ZRESC) + if (res == ZRESC) { c = -1; continue; } - *buf++ = res; - Rxcount++; + *buf++ = res; + Rxcount++; continue; case -1: - if (res >= 040 && res < 0100) + if (res >= 040 && res < 0100) { - c = res - 035; res = 040; + c = res - 035; res = 040; goto spaces; } - if (res == 0100) + if (res == 0100) { c = 0; - *buf++ = ZRESC; - Rxcount++; + *buf++ = ZRESC; + Rxcount++; continue; } c = res; continue; @@ -459,14 +459,14 @@ static rt_int16_t zrec_data32r(rt_uint8_t *buf, rt_int16_t len) spaces: if ((buf + c) > p+len) goto end; - while ( --res >= 0) + while ( --res >= 0) { - *buf++ = res; - Rxcount++; + *buf++ = res; + Rxcount++; } c = 0; continue; - } - } + } + } } // if -else } @@ -475,105 +475,105 @@ end: } rt_int16_t zget_data(rt_uint8_t *buf, rt_uint16_t len) { - rt_int16_t res = -RT_ERROR; - - if (RxCRC == 0) - { - res = zrec_data16(buf,len); - } - else if (RxCRC == 1) - { - res = zrec_data32(buf, len); - } - else if (RxCRC == 2) - { - res = zrec_data32r(buf, len); - } - + rt_int16_t res = -RT_ERROR; + + if (RxCRC == 0) + { + res = zrec_data16(buf,len); + } + else if (RxCRC == 1) + { + res = zrec_data32(buf, len); + } + else if (RxCRC == 2) + { + res = zrec_data32r(buf, len); + } + return res; } /* get type and cmd of header, fix lenght */ rt_int16_t zget_header(rt_uint8_t *hdr) { - rt_int16_t c,prev_char; + rt_int16_t c,prev_char; rt_uint32_t bit; - rt_uint16_t get_can,step_out; + rt_uint16_t get_can,step_out; bit = get_device_baud(); /* get console baud rate */ Rxframeind = header_type = 0; - step_out = 0; - prev_char = 0xff; - for (;;) - { - c = zread_line(100); - switch(c) - { - case 021: - case 0221: - if (prev_char == CAN) break; - if (prev_char == ZCRCW) goto start_again; - break; - case RCDO: - goto end; - case TIMEOUT: - if (prev_char == CAN) break; - if (prev_char == ZCRCW) - { - c = -RT_ERROR; goto end; - } - goto end; - case ZCRCW: - if (prev_char == CAN) goto start_again; - break; - case CAN: -get_can: - if (++get_can > 5) - { - c = ZCAN; goto end; - } - break; - case ZPAD: - if (prev_char == CAN) break; - if (prev_char == ZCRCW) goto start_again; - step_out = 1; - break; - default: - if (prev_char == CAN) break; - if (prev_char == ZCRCW) goto start_again; -start_again: - if (--bit == 0) - { - c = GCOUNT; goto end; - } - get_can = 0; - break; - } - prev_char = c; - if (step_out) break; /* exit loop */ - } - step_out = get_can = 0; - for (;;) - { - c = zxor_read(); - switch(c) - { - case ZPAD: - break; - case RCDO: - case TIMEOUT: - goto end; - case ZDLE: - step_out = 1; - break; - default: - goto start_again; - } - if (step_out) break; + step_out = 0; + prev_char = 0xff; + for (;;) + { + c = zread_line(100); + switch(c) + { + case 021: + case 0221: + if (prev_char == CAN) break; + if (prev_char == ZCRCW) goto start_again; + break; + case RCDO: + goto end; + case TIMEOUT: + if (prev_char == CAN) break; + if (prev_char == ZCRCW) + { + c = -RT_ERROR; goto end; + } + goto end; + case ZCRCW: + if (prev_char == CAN) goto start_again; + break; + case CAN: +get_can: + if (++get_can > 5) + { + c = ZCAN; goto end; + } + break; + case ZPAD: + if (prev_char == CAN) break; + if (prev_char == ZCRCW) goto start_again; + step_out = 1; + break; + default: + if (prev_char == CAN) break; + if (prev_char == ZCRCW) goto start_again; +start_again: + if (--bit == 0) + { + c = GCOUNT; goto end; + } + get_can = 0; + break; + } + prev_char = c; + if (step_out) break; /* exit loop */ + } + step_out = get_can = 0; + for (;;) + { + c = zxor_read(); + switch(c) + { + case ZPAD: + break; + case RCDO: + case TIMEOUT: + goto end; + case ZDLE: + step_out = 1; + break; + default: + goto start_again; + } + if (step_out) break; } Rxframeind = c = zxor_read(); - switch (c) - { + switch (c) + { case ZBIN32: RxCRC = 1; c = zget_bin_fcs(hdr); break; case ZBINR32: @@ -583,7 +583,7 @@ start_again: case ZHEX: RxCRC = 0; c = zget_hex_header(hdr); break; case CAN: - goto get_can; + goto get_can; case RCDO: case TIMEOUT: goto end; @@ -605,7 +605,7 @@ static rt_int16_t zget_bin_header(rt_uint8_t *hdr) header_type = res; crc = updcrc16(res, 0); - for (i=0;i<4;i++) + for (i=0;i<4;i++) { if ((res = zread_byte()) & ~0377) return res; @@ -618,11 +618,11 @@ static rt_int16_t zget_bin_header(rt_uint8_t *hdr) if ((res = zread_byte()) & ~0377) return res; crc = updcrc16(res, crc); - if (crc & 0xFFFF) + if (crc & 0xFFFF) { rt_kprintf("CRC error\n"); return -RT_ERROR; - } + } return header_type; } @@ -636,10 +636,10 @@ static rt_int16_t zget_bin_fcs(rt_uint8_t *hdr) if ((res = zread_byte()) & ~0377) return res; header_type = res; - crc = 0xFFFFFFFFL; + crc = 0xFFFFFFFFL; crc = updcrc32(res, crc); - for (i=0;i<4;i++) /* 4headers */ + for (i=0;i<4;i++) /* 4headers */ { if ((res = zread_byte()) & ~0377) return res; @@ -647,20 +647,20 @@ static rt_int16_t zget_bin_fcs(rt_uint8_t *hdr) *hdr++ = res; } - for (i=0;i<4;i++) /* 4bytes crc */ + for (i=0;i<4;i++) /* 4bytes crc */ { if ((res = zread_byte()) & ~0377) return res; crc = updcrc32(res, crc); } - if (crc != 0xDEBB20E3) - { + if (crc != 0xDEBB20E3) + { #ifdef ZDEBUG - rt_kprintf("CRC error\n"); + rt_kprintf("CRC error\n"); #endif return -RT_ERROR; - } + } return header_type; } @@ -670,14 +670,14 @@ static rt_int16_t zget_bin_fcs(rt_uint8_t *hdr) rt_int16_t zget_hex_header(rt_uint8_t *hdr) { rt_int16_t res,i; - rt_uint16_t crc; + rt_uint16_t crc; if ((res = zget_hex()) < 0) return res; header_type = res; crc = updcrc16(res, 0); - for (i=0;i<4;i++) + for (i=0;i<4;i++) { if ((res = zget_hex()) < 0) return res; @@ -690,11 +690,11 @@ rt_int16_t zget_hex_header(rt_uint8_t *hdr) if ((res = zget_hex()) < 0) return res; crc = updcrc16(res, crc); - if (crc & 0xFFFF) - { + if (crc & 0xFFFF) + { #ifdef ZDEBUG - rt_kprintf("error code : CRC error\r\n"); -#endif + rt_kprintf("error code : CRC error\r\n"); +#endif return -RT_ERROR; } res = zread_line(100); @@ -702,7 +702,7 @@ rt_int16_t zget_hex_header(rt_uint8_t *hdr) return res; res = zread_line(100); if (res < 0) - return res; + return res; return header_type; } @@ -710,11 +710,11 @@ rt_int16_t zget_hex_header(rt_uint8_t *hdr) /* convert to ascii */ static void zsend_ascii(rt_uint8_t c) { - const char hex[] = "0123456789abcdef"; + const char hex[] = "0123456789abcdef"; zsend_line(hex[(c&0xF0)>>4]); - zsend_line(hex[(c)&0xF]); - + zsend_line(hex[(c)&0xF]); + return; } @@ -722,26 +722,26 @@ static void zsend_ascii(rt_uint8_t c) * aend character c with ZMODEM escape sequence encoding. */ void zsend_zdle_char(rt_uint16_t ch) -{ - rt_uint16_t res; - +{ + rt_uint16_t res; + res = ch & 0377; - switch (res) + switch (res) { case 0377: zsend_byte(res); break; case ZDLE: - zsend_byte(ZDLE); - res ^= 0100; + zsend_byte(ZDLE); + res ^= 0100; zsend_byte(res); break; - case 021: + case 021: case 023: - case 0221: + case 0221: case 0223: - zsend_byte(ZDLE); - res ^= 0100; + zsend_byte(ZDLE); + res ^= 0100; zsend_byte(res); break; default: @@ -752,7 +752,7 @@ void zsend_zdle_char(rt_uint16_t ch) /* decode two lower case hex digits into an 8 bit byte value */ static rt_int16_t zget_hex(void) { - rt_int16_t res,n; + rt_int16_t res,n; if ((res = zxor_read()) < 0) return res; @@ -768,7 +768,7 @@ static rt_int16_t zget_hex(void) res -= ('a' - ':'); if (res & ~0x0f) return -RT_ERROR; - res += (n<<4); + res += (n<<4); return res; } @@ -786,7 +786,7 @@ again: /* Quick check for non control characters */ if ((res = zread_line(100)) & 0140) return res; - switch (res) + switch (res) { case ZDLE: break; @@ -807,7 +807,7 @@ again2: return res; if (res == CAN && (res = zread_line(100)) < 0) return res; - switch (res) + switch (res) { case CAN: return GOTCAN; @@ -829,7 +829,7 @@ again2: if ((res & 0140) == 0100) return (res ^ 0100); break; - } + } return -RT_ERROR; } @@ -842,7 +842,7 @@ rt_int16_t zxor_read(void) { rt_int16_t res; - for (;;) + for (;;) { if ((res = zread_line(100)) < 0) return res; @@ -852,11 +852,11 @@ rt_int16_t zxor_read(void) continue; case '\r': case '\n': - case ZDLE: + case ZDLE: default: return res; } - } + } } @@ -866,8 +866,8 @@ void zput_pos(rt_uint32_t pos) tx_header[ZP0] = pos; tx_header[ZP1] = pos>>8; tx_header[ZP2] = pos>>16; - tx_header[ZP3] = pos>>24; - + tx_header[ZP3] = pos>>24; + return; } @@ -877,9 +877,9 @@ void zget_pos(rt_uint32_t pos) Rxpos = (rx_header[ZP3] & 0377); Rxpos = (Rxpos << 8) | (rx_header[ZP2] & 0377); Rxpos = (Rxpos << 8) | (rx_header[ZP1] & 0377); - Rxpos = (Rxpos << 8) | (rx_header[ZP0] & 0377); - + Rxpos = (Rxpos << 8) | (rx_header[ZP0] & 0377); + return; -} +} -/* end of zcore.c */ +/* end of zcore.c */ diff --git a/components/utilities/zmodem/zdef.h b/components/utilities/zmodem/zdef.h index 14df3412ad89738ccaab39b871d794d2e99db18e..3568bdfd963148ffc1b02707410b8ce2a1e5df30 100644 --- a/components/utilities/zmodem/zdef.h +++ b/components/utilities/zmodem/zdef.h @@ -1,7 +1,7 @@ -#ifndef __ZDEF_H__ -#define __ZDEF_H__ - -#include +#ifndef __ZDEF_H__ +#define __ZDEF_H__ + +#include #include "crc.h" #define ZPAD '*' /* 052 padding character begins frames */ #define ZDLE 030 /* ctrl-X ZMODEM escape - `ala BISYNC DLE */ @@ -121,7 +121,7 @@ extern char Attn[ZATTNLEN+1]; /* Attention string rx sends to tx on err */ /* globals used by ZMODEM functions */ extern rt_uint8_t Rxframeind; /* ZBIN ZBIN32, or ZHEX type of frame */ -extern char header_type; /* type of header received */ +extern char header_type; /* type of header received */ extern rt_uint8_t rx_header[4]; /* received header */ extern rt_uint8_t tx_header[4]; /* transmitted header */ extern rt_uint8_t Txfcs32; /* TRUE means send binary frames with 32 bit FCS */ @@ -129,18 +129,18 @@ extern rt_uint16_t Rxcount; /* count of data bytes received */ extern rt_uint16_t Rxtimeout; /* tenths of seconds to wait for something */ extern rt_uint32_t Rxpos; /* received file position */ extern rt_uint32_t Txpos; /* transmitted file position */ -extern rt_uint8_t Txfcs32; /* TURE means send binary frames with 32 bit FCS */ - +extern rt_uint8_t Txfcs32; /* TURE means send binary frames with 32 bit FCS */ + /* ward Christensen / CP/M parameters - Don't change these! */ #define ENQ 005 #define CAN ('X'&037) #define XOFF ('s'&037) #define XON ('q'&037) #define SOH 1 -#define STX 2 -#define ETX 3 -#define SYN 026 -#define ESC 033 +#define STX 2 +#define ETX 3 +#define SYN 026 +#define ESC 033 #define WANTG 0107 /* send G not NAK to get nonstop batch xmsn */ #define EOT 4 #define ACK 6 @@ -154,64 +154,64 @@ extern rt_uint8_t Txfcs32; /* TURE means send binary frames with 32 bit #define RETRYMAX 5 #define WCEOT (-10) - - - - -#define BITRATE 115200 -#define TX_BUFFER_SIZE 1024 -#define RX_BUFFER_SIZE 1024 /* sender or receiver's max buffer size */ + + + + +#define BITRATE 115200 +#define TX_BUFFER_SIZE 1024 +#define RX_BUFFER_SIZE 1024 /* sender or receiver's max buffer size */ extern char ZF0_CMD; /* local ZMODEM file conversion request */ -extern char ZF1_CMD; /* local ZMODEM file management request */ -extern char ZF2_CMD; /* local ZMODEM file management request */ -extern char ZF3_CMD; /* local ZMODEM file management request */ -extern rt_uint32_t Baudrate ; -extern rt_uint32_t Left_bytes; -extern rt_uint32_t Left_sizes; - - -struct zmodemf -{ - struct rt_semaphore zsem; - rt_device_t device; -}; -extern struct zmodemf zmodem; - -struct zfile -{ - char *fname; +extern char ZF1_CMD; /* local ZMODEM file management request */ +extern char ZF2_CMD; /* local ZMODEM file management request */ +extern char ZF3_CMD; /* local ZMODEM file management request */ +extern rt_uint32_t Baudrate ; +extern rt_uint32_t Left_bytes; +extern rt_uint32_t Left_sizes; + + +struct zmodemf +{ + struct rt_semaphore zsem; + rt_device_t device; +}; +extern struct zmodemf zmodem; + +struct zfile +{ + char *fname; rt_int32_t fd; - rt_uint32_t ctime; + rt_uint32_t ctime; rt_uint32_t mode; rt_uint32_t bytes_total; rt_uint32_t bytes_sent; rt_uint32_t bytes_received; - rt_uint32_t file_end; - -}; -extern struct finsh_shell* shell; - -#define ZDEBUG 0 -/* sz.c */ -extern void zs_start(char *path); -/* rz.c */ -extern void zr_start(char *path); - -/* zcore.c */ -extern void zinit_parameter(void); -extern rt_int16_t zget_header(rt_uint8_t *hdr); -extern void zsend_bin_header(rt_uint8_t type, rt_uint8_t *hdr); -extern void zsend_hex_header(rt_uint8_t type, rt_uint8_t *hdr); -extern rt_int16_t zget_data(rt_uint8_t *buf, rt_uint16_t len); -extern void zsend_bin_data(rt_uint8_t *buf, rt_int16_t len, rt_uint8_t frameend); -extern void zput_pos(rt_uint32_t pos); -extern void zget_pos(rt_uint32_t pos); -/* zdevice.c */ -extern rt_uint32_t get_device_baud(void); -extern void zsend_byte(rt_uint16_t c); -extern void zsend_line(rt_uint16_t c); -extern rt_int16_t zread_line(rt_uint16_t timeout); -extern void zsend_break(char *cmd); + rt_uint32_t file_end; + +}; +extern struct finsh_shell* shell; + +#define ZDEBUG 0 +/* sz.c */ +extern void zs_start(char *path); +/* rz.c */ +extern void zr_start(char *path); + +/* zcore.c */ +extern void zinit_parameter(void); +extern rt_int16_t zget_header(rt_uint8_t *hdr); +extern void zsend_bin_header(rt_uint8_t type, rt_uint8_t *hdr); +extern void zsend_hex_header(rt_uint8_t type, rt_uint8_t *hdr); +extern rt_int16_t zget_data(rt_uint8_t *buf, rt_uint16_t len); +extern void zsend_bin_data(rt_uint8_t *buf, rt_int16_t len, rt_uint8_t frameend); +extern void zput_pos(rt_uint32_t pos); +extern void zget_pos(rt_uint32_t pos); +/* zdevice.c */ +extern rt_uint32_t get_device_baud(void); +extern void zsend_byte(rt_uint16_t c); +extern void zsend_line(rt_uint16_t c); +extern rt_int16_t zread_line(rt_uint16_t timeout); +extern void zsend_break(char *cmd); extern void zsend_can(void); - + #endif /* __ZDEF_H__ */ diff --git a/components/utilities/zmodem/zdevice.c b/components/utilities/zmodem/zdevice.c index 6bf57d3b9c9ef93e781f058d099764b4f6ef3222..1562cc5f5c651b2cd60572fca7e236fa96108a79 100644 --- a/components/utilities/zmodem/zdevice.c +++ b/components/utilities/zmodem/zdevice.c @@ -1,79 +1,79 @@ /* - * File : zdevice.c + * File : zdevice.c * the implemention of zmodem protocol. * Change Logs: * Date Author Notes * 2011-03-29 itspy - */ - -#include -#include -#include -#include -#include -#include -#include -#include "zdef.h" + */ + +#include +#include +#include +#include +#include +#include +#include +#include "zdef.h" -rt_uint32_t Line_left = 0; /* left number of data in the read line buffer*/ -rt_uint32_t Left_sizes = 0; /* left file sizes */ +rt_uint32_t Line_left = 0; /* left number of data in the read line buffer*/ +rt_uint32_t Left_sizes = 0; /* left file sizes */ rt_uint32_t Baudrate = BITRATE; /* console baudrate */ - - - -rt_uint32_t get_device_baud(void) -{ - return(Baudrate); -} - -rt_uint32_t get_sys_time(void) -{ - return(0L); -} - -void zsend_byte(rt_uint16_t ch) -{ - rt_device_write(zmodem.device, 0, &ch,1); - - return; -} - -void zsend_line(rt_uint16_t c) -{ - rt_uint16_t ch; - - ch = (c & 0377); - rt_device_write(zmodem.device, 0, &ch, 1); - - return; -} + + + +rt_uint32_t get_device_baud(void) +{ + return(Baudrate); +} + +rt_uint32_t get_sys_time(void) +{ + return(0L); +} + +void zsend_byte(rt_uint16_t ch) +{ + rt_device_write(zmodem.device, 0, &ch,1); + + return; +} + +void zsend_line(rt_uint16_t c) +{ + rt_uint16_t ch; + + ch = (c & 0377); + rt_device_write(zmodem.device, 0, &ch, 1); + + return; +} rt_int16_t zread_line(rt_uint16_t timeout) { - char *str; - static char buf[10]; - - if (Line_left > 0) - { - Line_left -= 1; - return (*str++ & 0377); - } - Line_left = 0; - timeout/=5; - while (1) - { - Line_left = rt_device_read(shell->device, 0, buf, 1); - if (Line_left) - { - Line_left = Line_left; - str = buf; - break; - } - } - if (Line_left < 1) return TIMEOUT; - Line_left -=1; - + char *str; + static char buf[10]; + + if (Line_left > 0) + { + Line_left -= 1; + return (*str++ & 0377); + } + Line_left = 0; + timeout/=5; + while (1) + { + Line_left = rt_device_read(shell->device, 0, buf, 1); + if (Line_left) + { + Line_left = Line_left; + str = buf; + break; + } + } + if (Line_left < 1) return TIMEOUT; + Line_left -=1; + return (*str++ & 0377); } @@ -82,33 +82,33 @@ rt_int16_t zread_line(rt_uint16_t timeout) * and \335 (break signal) */ void zsend_break(char *cmd) -{ +{ - while (*cmd++) + while (*cmd++) { - switch (*cmd) + switch (*cmd) { - case '\336': + case '\336': continue; - case '\335': - rt_thread_delay(RT_TICK_PER_SECOND); + case '\335': + rt_thread_delay(RT_TICK_PER_SECOND); continue; default: - zsend_line(*cmd); + zsend_line(*cmd); break; } } -} +} /* send cancel string to get the other end to shut up */ void zsend_can(void) { - static char cmd[] = {24,24,24,24,24,24,24,24,24,24,0}; + static char cmd[] = {24,24,24,24,24,24,24,24,24,24,0}; - zsend_break(cmd); + zsend_break(cmd); rt_kprintf("\x0d"); - Line_left=0; /* clear Line_left */ - + Line_left=0; /* clear Line_left */ + return; -} +} /* end of zdevice.c */ diff --git a/components/utilities/zmodem/zstart.c b/components/utilities/zmodem/zstart.c index f8e19d7e9218cff56136366f489e87b021103983..e5a36ca7abe1fca6c5f1fc8766cbe6696270cfa7 100644 --- a/components/utilities/zmodem/zstart.c +++ b/components/utilities/zmodem/zstart.c @@ -1,120 +1,120 @@ /* - * File : zstart.c + * File : zstart.c * the implemention of zmodem protocol. * Change Logs: * Date Author Notes * 2011-03-29 itspy - */ - -#include -#include -#include -#include -#include -#include "zdef.h" - - - -struct zmodemf zmodem; - -rt_err_t zmodem_rx_ind(rt_device_t dev, rt_size_t size) -{ - /* release semaphore */ - rt_sem_release(&zmodem.zsem); - - return RT_EOK; -} - -void finsh_rz(void *parameter) -{ - char *path; - rt_err_t (*rx_indicate)(rt_device_t dev, rt_size_t size); - rt_uint8_t flag; - - flag = RT_DEVICE_FLAG_STREAM; - zmodem.device->flag &=(~flag); - rt_sem_init(&(zmodem.zsem), "zsem", 0, 0); - path = rt_thread_self()->parameter; - /* save old rx_indicate */ - rx_indicate = zmodem.device->rx_indicate; - /* set new rx_indicate */ - rt_device_set_rx_indicate(zmodem.device, RT_NULL); - /* start receive remote files */ - zr_start(path); - zmodem.device->flag |=flag; - /* recovery old rx_indicate */ - rt_device_set_rx_indicate(zmodem.device, rx_indicate); - /* finsh>> */ - rt_kprintf(FINSH_PROMPT); -} -void finsh_sz(void *parameter) -{ - char *path; - rt_err_t (*rx_indicate)(rt_device_t dev, rt_size_t size); - rt_uint8_t flag; - - flag = RT_DEVICE_FLAG_STREAM; - zmodem.device->flag &=(~flag); - rt_sem_init(&(zmodem.zsem), "zsem", 0, 0); - path = rt_thread_self()->parameter; - /* save old rx_indicate */ - rx_indicate = zmodem.device->rx_indicate; - /* set new rx_indicate */ - rt_device_set_rx_indicate(zmodem.device, zmodem_rx_ind); - zs_start(path); - zmodem.device->flag |=flag; - /* recovery old rx_indicate */ - rt_device_set_rx_indicate(zmodem.device, rx_indicate); - /* finsh>> */ - rt_kprintf(FINSH_PROMPT); -} - -#ifdef RT_USING_FINSH -#include -#include - -static void rz(char *para) -{ - rt_thread_t init_thread; - rt_device_t device; - const char* device_name = finsh_get_device(); - - device = rt_device_find(device_name); - if( device == RT_NULL ) - { - rt_kprintf("%s not find\r\n",device_name); - } - zmodem.device = device; - init_thread = rt_thread_create("rz", - finsh_rz, - (void*)para, - 2048, - rt_thread_self()->current_priority+1, - 20); - - if (init_thread != RT_NULL) rt_thread_startup(init_thread); -} -FINSH_FUNCTION_EXPORT(rz, receive files by zmodem protocol) -static void sz(char *para) -{ - rt_thread_t init_thread; - rt_device_t device; - const char* device_name = finsh_get_device(); - - device = rt_device_find(device_name); - if( device == RT_NULL ) - { - rt_kprintf("%s not find\r\n",device_name); - } - zmodem.device = device; - init_thread = rt_thread_create("sz", - finsh_sz, - (void*)para, - 2048, - rt_thread_self()->current_priority+1, - 20); - - if (init_thread != RT_NULL) rt_thread_startup(init_thread); -} -FINSH_FUNCTION_EXPORT(sz, send files by zmodem protocol) -#endif + */ + +#include +#include +#include +#include +#include +#include "zdef.h" + + + +struct zmodemf zmodem; + +rt_err_t zmodem_rx_ind(rt_device_t dev, rt_size_t size) +{ + /* release semaphore */ + rt_sem_release(&zmodem.zsem); + + return RT_EOK; +} + +void finsh_rz(void *parameter) +{ + char *path; + rt_err_t (*rx_indicate)(rt_device_t dev, rt_size_t size); + rt_uint8_t flag; + + flag = RT_DEVICE_FLAG_STREAM; + zmodem.device->flag &=(~flag); + rt_sem_init(&(zmodem.zsem), "zsem", 0, 0); + path = rt_thread_self()->parameter; + /* save old rx_indicate */ + rx_indicate = zmodem.device->rx_indicate; + /* set new rx_indicate */ + rt_device_set_rx_indicate(zmodem.device, RT_NULL); + /* start receive remote files */ + zr_start(path); + zmodem.device->flag |=flag; + /* recovery old rx_indicate */ + rt_device_set_rx_indicate(zmodem.device, rx_indicate); + /* finsh>> */ + rt_kprintf(FINSH_PROMPT); +} +void finsh_sz(void *parameter) +{ + char *path; + rt_err_t (*rx_indicate)(rt_device_t dev, rt_size_t size); + rt_uint8_t flag; + + flag = RT_DEVICE_FLAG_STREAM; + zmodem.device->flag &=(~flag); + rt_sem_init(&(zmodem.zsem), "zsem", 0, 0); + path = rt_thread_self()->parameter; + /* save old rx_indicate */ + rx_indicate = zmodem.device->rx_indicate; + /* set new rx_indicate */ + rt_device_set_rx_indicate(zmodem.device, zmodem_rx_ind); + zs_start(path); + zmodem.device->flag |=flag; + /* recovery old rx_indicate */ + rt_device_set_rx_indicate(zmodem.device, rx_indicate); + /* finsh>> */ + rt_kprintf(FINSH_PROMPT); +} + +#ifdef RT_USING_FINSH +#include +#include + +static void rz(char *para) +{ + rt_thread_t init_thread; + rt_device_t device; + const char* device_name = finsh_get_device(); + + device = rt_device_find(device_name); + if( device == RT_NULL ) + { + rt_kprintf("%s not find\r\n",device_name); + } + zmodem.device = device; + init_thread = rt_thread_create("rz", + finsh_rz, + (void*)para, + 2048, + rt_thread_self()->current_priority+1, + 20); + + if (init_thread != RT_NULL) rt_thread_startup(init_thread); +} +FINSH_FUNCTION_EXPORT(rz, receive files by zmodem protocol) +static void sz(char *para) +{ + rt_thread_t init_thread; + rt_device_t device; + const char* device_name = finsh_get_device(); + + device = rt_device_find(device_name); + if( device == RT_NULL ) + { + rt_kprintf("%s not find\r\n",device_name); + } + zmodem.device = device; + init_thread = rt_thread_create("sz", + finsh_sz, + (void*)para, + 2048, + rt_thread_self()->current_priority+1, + 20); + + if (init_thread != RT_NULL) rt_thread_startup(init_thread); +} +FINSH_FUNCTION_EXPORT(sz, send files by zmodem protocol) +#endif diff --git a/documentation/coding_style_en.txt b/documentation/coding_style_en.txt index 926b6b551881777af946669970dd21d1486f1a85..e5dad024045a5ba40cf516bd5eadc4254667ca08 100644 --- a/documentation/coding_style_en.txt +++ b/documentation/coding_style_en.txt @@ -1,231 +1,231 @@ - RT-Thread Coding Style - -This is an developing instruction for RT-Thread developers. As an open source -software, RT-Thread is done by the cooperation of different people. This -document is a guide for RT-Thread developers and please obey it if you are. -RT-Thread users could also get to know some conventions in the code through it -and thus easier to understand the implementations of RT-Thread. - - -1. Directory Naming - -In normal conditions, please name directories in lower-case. Directories should -have descriptive names. For example, the port of a chip should be composed of -the name of the chip and the category of the chip. Directories under components/ -should stand for what the component does. - - -2. File Naming - -In normal conditions, please name files in lower-case. If the file is -referencing other places, it can have the original name. To avoid naming -collision, do not use general names or the names that are frequently used. - - -3. Header Files - -To avoid include the same header file for multiple times, you need to define a -symbol like this: - - #ifndef __FILE_H__ - #define __FILE_H__ - /* header file content */ - #endif - -The symbol should begin and end with "__" to avoid naming collision. The words -of the file name should be connected by "_". - - -4. Header File Comments - -In every header file, there should be copyright information and Change Log -record like this: - - /* - * File : rtthread.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE. - * - * Change Logs: - * Date Author Notes - * 2006-03-18 Bernard the first version - * 2006-04-26 Bernard add semaphore APIs - * … - */ - - -5. Structure Defines - -Please name structures in lower-case and connect words with "_". For example: - - struct rt_list_node - { - struct rt_list_node *next; - struct rt_list_node *prev; - }; - -Braces should have their own lines and the members should be defines with -indent. - -The names of type defines such like structure types should be the structure name -plus "_t". For example: - - typedef struct rt_list_node rt_list_t; - - -In order to be easily referenced, the types of objects in kernel is pointer. For -example: - - typedef struct rt_timer* rt_timer_t; - - -6. Micros - -In RT-Thread, please use upper-case names for micro definitions. Words are -connected by "_". Like: - - #define RT_TRUE 1 - - -7. Function Naming and Declaration - -Please name functions in lower-case and separate words with "_". API provided to -upper application should be declared in header files. If the function don't have -parameters, it should be declared as void: - - rt_thread_t rt_thread_self(void); - - -8. Commenting - -Please use English to comment. There shouldn't be too much comments and the -comments should describe what does the code do. And it should describe how the -complicated algorithm works. Comments to statements should be placed before them -or right of them. Anther places are illegal. - - -9. Indent - -Please use TAB or 4 spaces to indent. It's preferred to use 4 spaces. If no -other special meanings, the indent should begin right after "{": - - if (condition) - { - /* others */ - } - -The only one exception is switch. In switch-case statements, "case" should be -aligned with "switch": - - switch (value) - { - case value1: - break; - } - -"case" is aligned with "switch", the following code block should be indented. - - -10. Braces and Spaces - -For ease of reading, it is advised that braces should occupy the whole line -instead of following other statements. Like: - - if (condition) - { - /* others */ - } - -When matching braces have their own lines, the reader would identify the code -blocks easily. - -There should be a space before parentheses when it's not a function call. For -example: - - if (x <= y) - { - /* others */ - } - - for (index = 0; index < MAX_NUMBER; index ++) - { - /* others */ - } - -In expressions, there should be a space between most binary and ternary -operators and the strings. No spaces around(inside) parentheses, like: - - if ( x <= y ) - { - /* other */ - } - -This is a bad practice. - - -11. trace, log Informations - -In RT-Thread, rt_kprintf is a commonly used logging routine. In RT-Thread -rt_kprintf is implemented as a polling, non-interrupting string output. It is -suitable in "instant" situations such as interrupt context. The polling method -would have influence to the timing sequence of the log output. - -It is not recommended to use rt_kprintf frequently. Unless you are aware of that -it's not a big deal to run slower. - -Logging should be off by default and can be turned on by a switch(e.g. a -variable or a micro). When logging, it should be easy to understand and easy to -determine where the problem is. - - -12. Functions - -Functions in kernel should be K.I.S.S. If the function is too long, you should -split it into smaller ones and make each of them simplified and easy to -understand. - - -13. Objects - -The kernel of RT-Thread uses object-oriented tech in C. The naming convention -is: structure names are the object names, object names + verb phrases are the -method names of objects: - - struct rt_timer - { - struct rt_object parent; - /* other fields */ - }; - typedef struct rt_timer* rt_timer_t; - -The definition of structure rt_timer stands for the object definition of timer -object. - - rt_timer_t rt_timer_create(const char* name, - void (*timeout)(void* parameter), void* parameter, - rt_tick_t time, rt_uint8_t flag); - rt_err_t rt_timer_delete(rt_timer_t timer); - rt_err_t rt_timer_start(rt_timer_t timer); - rt_err_t rt_timer_stop(rt_timer_t timer); - -rt_timer + verb phrase stands for the method that could be used on timer object. - -When creating a new object, think twice on memory allocations: whether a static -object could be created or it could only created dynamically on heap. - -14. Use astyle to format the code automatically -parameters: --style=allman - --indent=spaces=4 - --pad-oper - --pad-header - --unpad-paren - --suffix=none - --align-pointer=name - --lineend=linux - --convert-tabs - --verbose - + RT-Thread Coding Style + +This is an developing instruction for RT-Thread developers. As an open source +software, RT-Thread is done by the cooperation of different people. This +document is a guide for RT-Thread developers and please obey it if you are. +RT-Thread users could also get to know some conventions in the code through it +and thus easier to understand the implementations of RT-Thread. + + +1. Directory Naming + +In normal conditions, please name directories in lower-case. Directories should +have descriptive names. For example, the port of a chip should be composed of +the name of the chip and the category of the chip. Directories under components/ +should stand for what the component does. + + +2. File Naming + +In normal conditions, please name files in lower-case. If the file is +referencing other places, it can have the original name. To avoid naming +collision, do not use general names or the names that are frequently used. + + +3. Header Files + +To avoid include the same header file for multiple times, you need to define a +symbol like this: + + #ifndef __FILE_H__ + #define __FILE_H__ + /* header file content */ + #endif + +The symbol should begin and end with "__" to avoid naming collision. The words +of the file name should be connected by "_". + + +4. Header File Comments + +In every header file, there should be copyright information and Change Log +record like this: + + /* + * File : rtthread.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE. + * + * Change Logs: + * Date Author Notes + * 2006-03-18 Bernard the first version + * 2006-04-26 Bernard add semaphore APIs + * … + */ + + +5. Structure Defines + +Please name structures in lower-case and connect words with "_". For example: + + struct rt_list_node + { + struct rt_list_node *next; + struct rt_list_node *prev; + }; + +Braces should have their own lines and the members should be defines with +indent. + +The names of type defines such like structure types should be the structure name +plus "_t". For example: + + typedef struct rt_list_node rt_list_t; + + +In order to be easily referenced, the types of objects in kernel is pointer. For +example: + + typedef struct rt_timer* rt_timer_t; + + +6. Micros + +In RT-Thread, please use upper-case names for micro definitions. Words are +connected by "_". Like: + + #define RT_TRUE 1 + + +7. Function Naming and Declaration + +Please name functions in lower-case and separate words with "_". API provided to +upper application should be declared in header files. If the function don't have +parameters, it should be declared as void: + + rt_thread_t rt_thread_self(void); + + +8. Commenting + +Please use English to comment. There shouldn't be too much comments and the +comments should describe what does the code do. And it should describe how the +complicated algorithm works. Comments to statements should be placed before them +or right of them. Anther places are illegal. + + +9. Indent + +Please use TAB or 4 spaces to indent. It's preferred to use 4 spaces. If no +other special meanings, the indent should begin right after "{": + + if (condition) + { + /* others */ + } + +The only one exception is switch. In switch-case statements, "case" should be +aligned with "switch": + + switch (value) + { + case value1: + break; + } + +"case" is aligned with "switch", the following code block should be indented. + + +10. Braces and Spaces + +For ease of reading, it is advised that braces should occupy the whole line +instead of following other statements. Like: + + if (condition) + { + /* others */ + } + +When matching braces have their own lines, the reader would identify the code +blocks easily. + +There should be a space before parentheses when it's not a function call. For +example: + + if (x <= y) + { + /* others */ + } + + for (index = 0; index < MAX_NUMBER; index ++) + { + /* others */ + } + +In expressions, there should be a space between most binary and ternary +operators and the strings. No spaces around(inside) parentheses, like: + + if ( x <= y ) + { + /* other */ + } + +This is a bad practice. + + +11. trace, log Informations + +In RT-Thread, rt_kprintf is a commonly used logging routine. In RT-Thread +rt_kprintf is implemented as a polling, non-interrupting string output. It is +suitable in "instant" situations such as interrupt context. The polling method +would have influence to the timing sequence of the log output. + +It is not recommended to use rt_kprintf frequently. Unless you are aware of that +it's not a big deal to run slower. + +Logging should be off by default and can be turned on by a switch(e.g. a +variable or a micro). When logging, it should be easy to understand and easy to +determine where the problem is. + + +12. Functions + +Functions in kernel should be K.I.S.S. If the function is too long, you should +split it into smaller ones and make each of them simplified and easy to +understand. + + +13. Objects + +The kernel of RT-Thread uses object-oriented tech in C. The naming convention +is: structure names are the object names, object names + verb phrases are the +method names of objects: + + struct rt_timer + { + struct rt_object parent; + /* other fields */ + }; + typedef struct rt_timer* rt_timer_t; + +The definition of structure rt_timer stands for the object definition of timer +object. + + rt_timer_t rt_timer_create(const char* name, + void (*timeout)(void* parameter), void* parameter, + rt_tick_t time, rt_uint8_t flag); + rt_err_t rt_timer_delete(rt_timer_t timer); + rt_err_t rt_timer_start(rt_timer_t timer); + rt_err_t rt_timer_stop(rt_timer_t timer); + +rt_timer + verb phrase stands for the method that could be used on timer object. + +When creating a new object, think twice on memory allocations: whether a static +object could be created or it could only created dynamically on heap. + +14. Use astyle to format the code automatically +parameters: --style=allman + --indent=spaces=4 + --pad-oper + --pad-header + --unpad-paren + --suffix=none + --align-pointer=name + --lineend=linux + --convert-tabs + --verbose + diff --git a/documentation/doxygen/basicdef.h b/documentation/doxygen/basicdef.h index ad766b4ebd9b04021c37bfb860da11460485122e..4479840843ca2d6a6060015b993e875c7dd4c54f 100644 --- a/documentation/doxygen/basicdef.h +++ b/documentation/doxygen/basicdef.h @@ -1,14 +1,14 @@ -/* - * This file is only used for doxygen document generation. - */ - -/** - * @defgroup BasicDef Basic Definitions - * - * @brief Basic data type in RT-Thread RTOS. - * - * These are the basic definitions which used in RT-Thread RTOS. In general, - * RT-Thread kernel uses its own definition of the basic data types, such as - * rt_uint32_t, rt_uint8_t, etc., which does not depend on the compiler or - * architecture. - */ +/* + * This file is only used for doxygen document generation. + */ + +/** + * @defgroup BasicDef Basic Definitions + * + * @brief Basic data type in RT-Thread RTOS. + * + * These are the basic definitions which used in RT-Thread RTOS. In general, + * RT-Thread kernel uses its own definition of the basic data types, such as + * rt_uint32_t, rt_uint8_t, etc., which does not depend on the compiler or + * architecture. + */ diff --git a/documentation/doxygen/filesystem.h b/documentation/doxygen/filesystem.h index 2cb4d6066ba11b462ad9597dd6e7dc924a1e74fe..f5a1834e25783c5a4358727b1027512c9baad9eb 100644 --- a/documentation/doxygen/filesystem.h +++ b/documentation/doxygen/filesystem.h @@ -1,44 +1,44 @@ -/* - * This file is only used for doxygen document generation. - */ - -/** - * @defgroup DFS Device Virtual File System - * - * @brief DFS is a virtual file system in RT-Thread RTOS. - * - * The DFS (Device Virtual File System) is a vfs file system of RT-Thread RTOS, - * which is focused on embedded device. VFS is an abstraction layer on top of a - * more concrete file system. The purpose of a VFS is to allow client applications - * to access different types of concrete file systems in a uniform way. - * - * @image html dfs.png "Figure 4: Device Virtual File System Architecture" - * - * The DFS specifies an interface between the kernel and a concrete file system. - * Therefore, it is easy to add support for new file system types to the kernel - * simply by fulfilling the interface. - */ - -/** - * @addtogroup DFS - */ -/*@{*/ - -/** - * @defgroup Fd File Descriptor - * - */ - -/** - * @defgroup FsApi File System API - */ - -/** - * @defgroup FileApi File API - */ - -/** - * @defgroup FsPosixApi File POSIX API - */ - -/*@}*/ +/* + * This file is only used for doxygen document generation. + */ + +/** + * @defgroup DFS Device Virtual File System + * + * @brief DFS is a virtual file system in RT-Thread RTOS. + * + * The DFS (Device Virtual File System) is a vfs file system of RT-Thread RTOS, + * which is focused on embedded device. VFS is an abstraction layer on top of a + * more concrete file system. The purpose of a VFS is to allow client applications + * to access different types of concrete file systems in a uniform way. + * + * @image html dfs.png "Figure 4: Device Virtual File System Architecture" + * + * The DFS specifies an interface between the kernel and a concrete file system. + * Therefore, it is easy to add support for new file system types to the kernel + * simply by fulfilling the interface. + */ + +/** + * @addtogroup DFS + */ +/*@{*/ + +/** + * @defgroup Fd File Descriptor + * + */ + +/** + * @defgroup FsApi File System API + */ + +/** + * @defgroup FileApi File API + */ + +/** + * @defgroup FsPosixApi File POSIX API + */ + +/*@}*/ diff --git a/documentation/doxygen/finsh.h b/documentation/doxygen/finsh.h index fd13c43379e2b72b8d73654b7beca46f82242fc8..e443b8c28fcfcf37069f9ae293db9aa7670ec155 100644 --- a/documentation/doxygen/finsh.h +++ b/documentation/doxygen/finsh.h @@ -1,19 +1,19 @@ -/* - * This file is only used for doxygen document generation. - */ - -/** - * @defgroup finsh finsh shell - * - * @brief finsh shell is a user command shell in RT-Thread RTOS. - * - * finsh shell is a user command shell in RT-Thread RTOS, which is a shell can - * accept C-expression like syntax in command. From finsh shell, user can access - * system area, such as memory, variables and function by input C-expression in - * command. - * - * @image html finsh.png "Figure 3: finsh shell architecture" - * There is a shell thread, which named as "tshell", in the finsh shell, it read - * user command from console device, and then invokes system function or access - * system variable to output result (by rt_kprintf). - */ +/* + * This file is only used for doxygen document generation. + */ + +/** + * @defgroup finsh finsh shell + * + * @brief finsh shell is a user command shell in RT-Thread RTOS. + * + * finsh shell is a user command shell in RT-Thread RTOS, which is a shell can + * accept C-expression like syntax in command. From finsh shell, user can access + * system area, such as memory, variables and function by input C-expression in + * command. + * + * @image html finsh.png "Figure 3: finsh shell architecture" + * There is a shell thread, which named as "tshell", in the finsh shell, it read + * user command from console device, and then invokes system function or access + * system variable to output result (by rt_kprintf). + */ diff --git a/documentation/doxygen/hardware.h b/documentation/doxygen/hardware.h index f46aed3e4b7673d62610dca9160e903fab0cae67..dd50f3abe83571ac599fdf0a12b531ec1d2ed75c 100644 --- a/documentation/doxygen/hardware.h +++ b/documentation/doxygen/hardware.h @@ -1,85 +1,85 @@ -/* - * This file is only used for doxygen document generation. - */ - -/** - * @defgroup bsp Hardware Related Package - * - * @brief Hardware Related Package includes board support package(BSP) and CSP(Chip - * Support Package). - * - * Board Support Package(BSP) is the hardware related wrapper, for example, peripherals - * in board, the pinmux setting etc. In RT-Thread RTOS, the bsp is placed under bsp - * directory. - * - * Chip Support Package (CSP) is a software set that contains chip specific software. - * A CSP usually includes operating system porting and peripheral device drivers inside - * chip. In RT-Thread RTOS, the csp is placed under libcpu directory. - */ - -/** - * @addtogroup bsp - */ -/*@{*/ - -/** - * This function will return current system interrupt status and disable system - * interrupt. - * - * @return the current system interrupt status - */ -rt_base_t rt_hw_interrupt_disable(void); - -/** - * This function will set the specified interrupt status, which shall saved by - * rt_hw_intterrupt_disable function. If the saved interrupt status is interrupt - * opened, this function will open system interrupt status. - */ -void rt_hw_interrupt_enable(rt_base_t level); - -/** - * This function initializes interrupt. - */ -void rt_hw_interrupt_init(void); - -/** - * This function masks the specified interrupt. - * - * @param vector the interrupt number to be masked. - * - * @note not all of platform provide this function. - */ -void rt_hw_interrupt_mask(int vector); - -/** - * This function umasks the specified interrupt. - * - * @param vector the interrupt number to be unmasked. - * - * @note not all of platform provide this function. - */ -void rt_hw_interrupt_umask(int vector); - -/** - * This function will install specified interrupt handler. - * - * @param vector the interrupt number to be installed. - * @param new_handler the new interrupt handler. - * @param old_handler the old interrupt handler. This parameter can be RT_NULL. - * - * @note not all of platform provide this function. - */ -void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, - rt_isr_handler_t *old_handler); - -/** - * This function will reset whole platform. - */ -void rt_hw_cpu_reset(void); - -/** - * This function will halt whole platform. - */ -void rt_hw_cpu_shutdown(void); - -/*@}*/ +/* + * This file is only used for doxygen document generation. + */ + +/** + * @defgroup bsp Hardware Related Package + * + * @brief Hardware Related Package includes board support package(BSP) and CSP(Chip + * Support Package). + * + * Board Support Package(BSP) is the hardware related wrapper, for example, peripherals + * in board, the pinmux setting etc. In RT-Thread RTOS, the bsp is placed under bsp + * directory. + * + * Chip Support Package (CSP) is a software set that contains chip specific software. + * A CSP usually includes operating system porting and peripheral device drivers inside + * chip. In RT-Thread RTOS, the csp is placed under libcpu directory. + */ + +/** + * @addtogroup bsp + */ +/*@{*/ + +/** + * This function will return current system interrupt status and disable system + * interrupt. + * + * @return the current system interrupt status + */ +rt_base_t rt_hw_interrupt_disable(void); + +/** + * This function will set the specified interrupt status, which shall saved by + * rt_hw_intterrupt_disable function. If the saved interrupt status is interrupt + * opened, this function will open system interrupt status. + */ +void rt_hw_interrupt_enable(rt_base_t level); + +/** + * This function initializes interrupt. + */ +void rt_hw_interrupt_init(void); + +/** + * This function masks the specified interrupt. + * + * @param vector the interrupt number to be masked. + * + * @note not all of platform provide this function. + */ +void rt_hw_interrupt_mask(int vector); + +/** + * This function umasks the specified interrupt. + * + * @param vector the interrupt number to be unmasked. + * + * @note not all of platform provide this function. + */ +void rt_hw_interrupt_umask(int vector); + +/** + * This function will install specified interrupt handler. + * + * @param vector the interrupt number to be installed. + * @param new_handler the new interrupt handler. + * @param old_handler the old interrupt handler. This parameter can be RT_NULL. + * + * @note not all of platform provide this function. + */ +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, + rt_isr_handler_t *old_handler); + +/** + * This function will reset whole platform. + */ +void rt_hw_cpu_reset(void); + +/** + * This function will halt whole platform. + */ +void rt_hw_cpu_shutdown(void); + +/*@}*/ diff --git a/documentation/doxygen/kernel.h b/documentation/doxygen/kernel.h index 6270af6dba4fe18b55d469b46ea4d2a3cfb7110b..b54144780b1bfb581947ac0678c5aa2eed385dee 100644 --- a/documentation/doxygen/kernel.h +++ b/documentation/doxygen/kernel.h @@ -1,138 +1,138 @@ -/* - * This file is only used for doxygen document generation. - */ - -/** - * @defgroup Kernel RT-Thread Kernel API - * - * The Kernel APIs are the core APIs of RT-Thread, which supports the following - * features: - * - Multi-thread management - * - Synchronization mechanisms - * - Inter-thread communication - * - Memory management - * - Asynchronous timer - */ - +/* + * This file is only used for doxygen document generation. + */ + +/** + * @defgroup Kernel RT-Thread Kernel API + * + * The Kernel APIs are the core APIs of RT-Thread, which supports the following + * features: + * - Multi-thread management + * - Synchronization mechanisms + * - Inter-thread communication + * - Memory management + * - Asynchronous timer + */ + /** * @addtogroup Kernel - */ + */ /*@{*/ - -/** - * @defgroup Thread Thread Management - * @brief the thread management - * - * RT-Thread operating system supports multitask systems, which are based on thread - * scheduling. - * - The scheduling is a full preemptive priority-based scheduling algorithm. - * - 8/32/256 priority levels are supported, in which 0 is the highest and 7/31/255 the lowest. - * The 7/31/255th priority is used for idle thread. - * - Threads running at same priority level are supported. The shared time-slice - * round-robin scheduling is used for this case. - * - The time of scheduler to choose the next highest ready thread is determinant. - * - There are four status in thread management - * -# Initialization - * -# Running/Ready - * -# Blocked - * -# Closed - * - The number of threads in the system is unlimited, only related with RAM. - */ - -/** - * @defgroup Clock Clock and Timer Management - * * @brief clock and system timer management - * - * RT-Thread uses clock tick to implement shared time-slice scheduling. - * - * The timing sensitivity of thread is implemented by timers. The timer can be set as - * one-shot or periodic timeout. - */ - -/** - * @defgroup KernelObject Kernel Object Management - * @brief kernel object management - * - * The Kernel object system can access and manage all of the kernel objects. - * - * Kernel objects include most of the facilities in the kernel: - * - thread - * - semaphore and mutex - * - event/fast event, mailbox, messagequeue - * - memory pool - * - timer - * @image html Kernel_Object.png "Figure 2: Kernel Object" - * @image rtf Kernel_Object.png "Figure 2: Kernel Object" - * - * Kernel objects can be static objects, whose memory is allocated in compiling. - * It can be dynamic objects as well, whose memory is allocated from system heaps - * in runtime. - */ - -/** - * @defgroup IPC Inter-Thread Communication - * @brief inter-thread communication - * - * RT-Thread operating system supports the traditional semaphore and mutex. - * - Mutex objects use inherited priority to prevent priority reversion. - * - The semaphore release action is safe for interrupt service routine. - * - * Moreover, the blocked queue for thread to obtain semaphore or mutex can be sorted - * by priority or FIFO. There are two flags to indicate this mechanism. - * - RT_IPC_FLAG_FIFO - * when the resource is available, thread pended on this resource at first would get - * the resource. - * - RT_IPC_FLAG_PRIO - * when the resource is available, thread pended on this resource who had the most high - * priority would get the resource. - * - * RT-Thread operating systems supports event/fast event, mail box and message queue. - * - The event mechanism is used to awake a thead by setting one or more corresponding - * bit of a binary number when an event ocurs. - * - The fast event supports event thread queue. Once a one bit event occurs, the corresponding - * blocked thread can be found out timing accurately, then will be waked up. - * - In mailbox, the mail length is fixed to 4 byte, which is more effective than message queue. - * - The send action for communication facilities is also safe for interrupt service routine. - */ - -/** - * @defgroup MM Memory Management - * @brief memory management for memory pool and heap memory - * - * RT-Thread operating system supports two types memory management: - * - Static memory pool management - * - Dynamic memory heap management. - * - * The time to allocate a memory block from the memory pool is determinant. When - * the memory pool is empty, the allocated thread can be blocked (or immediately return, - * or waiting for sometime to return, which are determined by a timeout parameter). - * When other thread releases memory blocks to this memory pool, the blocked thread is - * wake up. - * - * There are two methods in dynamic memory heap management, one is used for small memory, - * such as less than 1MB. Another is a SLAB like memory management, which is suitable - * for large memory system. All of them has no real-time character. - */ - -/** - * @defgroup Device Device System - * @brief device I/O subsystem - * - * The Device System is designed as simple and minimum layer to help communication between - * applications and drivers. - * - * The Device System provide five interfaces to driver: - * - open, open a device - * - close, close a device - * - read, read some data from a device - * - write, write some data to a device - * - control, send some control command to a device - */ - -/** - * @defgroup Hook Runtime Trace and Record - * @brief the hook function set in runtime - * + +/** + * @defgroup Thread Thread Management + * @brief the thread management + * + * RT-Thread operating system supports multitask systems, which are based on thread + * scheduling. + * - The scheduling is a full preemptive priority-based scheduling algorithm. + * - 8/32/256 priority levels are supported, in which 0 is the highest and 7/31/255 the lowest. + * The 7/31/255th priority is used for idle thread. + * - Threads running at same priority level are supported. The shared time-slice + * round-robin scheduling is used for this case. + * - The time of scheduler to choose the next highest ready thread is determinant. + * - There are four status in thread management + * -# Initialization + * -# Running/Ready + * -# Blocked + * -# Closed + * - The number of threads in the system is unlimited, only related with RAM. + */ + +/** + * @defgroup Clock Clock and Timer Management + * * @brief clock and system timer management + * + * RT-Thread uses clock tick to implement shared time-slice scheduling. + * + * The timing sensitivity of thread is implemented by timers. The timer can be set as + * one-shot or periodic timeout. + */ + +/** + * @defgroup KernelObject Kernel Object Management + * @brief kernel object management + * + * The Kernel object system can access and manage all of the kernel objects. + * + * Kernel objects include most of the facilities in the kernel: + * - thread + * - semaphore and mutex + * - event/fast event, mailbox, messagequeue + * - memory pool + * - timer + * @image html Kernel_Object.png "Figure 2: Kernel Object" + * @image rtf Kernel_Object.png "Figure 2: Kernel Object" + * + * Kernel objects can be static objects, whose memory is allocated in compiling. + * It can be dynamic objects as well, whose memory is allocated from system heaps + * in runtime. + */ + +/** + * @defgroup IPC Inter-Thread Communication + * @brief inter-thread communication + * + * RT-Thread operating system supports the traditional semaphore and mutex. + * - Mutex objects use inherited priority to prevent priority reversion. + * - The semaphore release action is safe for interrupt service routine. + * + * Moreover, the blocked queue for thread to obtain semaphore or mutex can be sorted + * by priority or FIFO. There are two flags to indicate this mechanism. + * - RT_IPC_FLAG_FIFO + * when the resource is available, thread pended on this resource at first would get + * the resource. + * - RT_IPC_FLAG_PRIO + * when the resource is available, thread pended on this resource who had the most high + * priority would get the resource. + * + * RT-Thread operating systems supports event/fast event, mail box and message queue. + * - The event mechanism is used to awake a thead by setting one or more corresponding + * bit of a binary number when an event ocurs. + * - The fast event supports event thread queue. Once a one bit event occurs, the corresponding + * blocked thread can be found out timing accurately, then will be waked up. + * - In mailbox, the mail length is fixed to 4 byte, which is more effective than message queue. + * - The send action for communication facilities is also safe for interrupt service routine. + */ + +/** + * @defgroup MM Memory Management + * @brief memory management for memory pool and heap memory + * + * RT-Thread operating system supports two types memory management: + * - Static memory pool management + * - Dynamic memory heap management. + * + * The time to allocate a memory block from the memory pool is determinant. When + * the memory pool is empty, the allocated thread can be blocked (or immediately return, + * or waiting for sometime to return, which are determined by a timeout parameter). + * When other thread releases memory blocks to this memory pool, the blocked thread is + * wake up. + * + * There are two methods in dynamic memory heap management, one is used for small memory, + * such as less than 1MB. Another is a SLAB like memory management, which is suitable + * for large memory system. All of them has no real-time character. + */ + +/** + * @defgroup Device Device System + * @brief device I/O subsystem + * + * The Device System is designed as simple and minimum layer to help communication between + * applications and drivers. + * + * The Device System provide five interfaces to driver: + * - open, open a device + * - close, close a device + * - read, read some data from a device + * - write, write some data to a device + * - control, send some control command to a device + */ + +/** + * @defgroup Hook Runtime Trace and Record + * @brief the hook function set in runtime + * * In order to trace and record RT-Thread activity in runtime, a hook mechanism * is introduced. * @@ -141,20 +141,20 @@ * - object hook, invoked at object created, deleted, taken and put etc. * - scheduler hook, invoked at thread switch and idle thread loop. * - memory hook, invoked when allocate or free memory block. - * - timer hook, invoked when timer is timeout. - */ - -/** - * @defgroup KernelService Other useful kernel service - * @brief other useful service in the kernel - */ - -/** - * @defgroup Error Error Code - * @brief error code - * - * The error code is defined to identify which kind of error occurs. When some - * bad things happen, the current thread's errno will be set. see @ref _rt_errno - */ - -/*@}*/ + * - timer hook, invoked when timer is timeout. + */ + +/** + * @defgroup KernelService Other useful kernel service + * @brief other useful service in the kernel + */ + +/** + * @defgroup Error Error Code + * @brief error code + * + * The error code is defined to identify which kind of error occurs. When some + * bad things happen, the current thread's errno will be set. see @ref _rt_errno + */ + +/*@}*/ diff --git a/documentation/doxygen/mainpage.h b/documentation/doxygen/mainpage.h index 6347a34b3c9ea687d4c56ac3db65fbb963df5cec..a9d932da6473e66b6f5cf95da492adce0a091c0d 100644 --- a/documentation/doxygen/mainpage.h +++ b/documentation/doxygen/mainpage.h @@ -1,49 +1,49 @@ -/* - * This file is only used for doxygen document generation. - */ - -/** - * @mainpage Introduction - * @author RT-Thread Development Team - * @version 1.1.0 - * - * RT-Thread RTOS is an open source embedded real-time operating system and is - * designed specifically for small memory footprint platforms. The real-time and - * embedded characters are the most significant advantages of RT-Thread. - * - * - Real-Time Character - * - * RT-Thread has a real-time operating system kernel, with fully preempted - * multi-thread scheduler, inter-thread communication with timing sensitivity - * and transparent interrupt handling. - * - * - Embedded Character - * - * RT-Thread is suitable for embedded systems for small footprint characters. - * The kernel is implemented as a simple C library. The simplest application - * costs less than 1 Kbytes RAM on the ARM Cortex-M platform. - * - * @section kernel_arch RT-Thread Architecture - * - * RT-Thread system architecture is like: - * @image html System_Arch.png "Figure 1: RT-Thread Architecture" - * - * @section kernel_service Kernel API - * - * The Kernel APIs are the core APIs of RT-Thread, which supports the following - * features: - * - Multi-thread management and scheduler - * - Synchronization mechanisms, semaphore, recursive mutex and event set - * - Inter-thread communication, mailbox and message queue - * - Memory management, memory pool and dynamic heap memory management - * - Asynchronous timer - * - * For more details, please refer to @ref Kernel - * - * @section system_init System Initialization - * - * Once RT-Thread operating system starts up, the facility in system must be initialized - * firstly. - * - * For more details, please refer to @ref SystemInit - */ +/* + * This file is only used for doxygen document generation. + */ + +/** + * @mainpage Introduction + * @author RT-Thread Development Team + * @version 1.1.0 + * + * RT-Thread RTOS is an open source embedded real-time operating system and is + * designed specifically for small memory footprint platforms. The real-time and + * embedded characters are the most significant advantages of RT-Thread. + * + * - Real-Time Character + * + * RT-Thread has a real-time operating system kernel, with fully preempted + * multi-thread scheduler, inter-thread communication with timing sensitivity + * and transparent interrupt handling. + * + * - Embedded Character + * + * RT-Thread is suitable for embedded systems for small footprint characters. + * The kernel is implemented as a simple C library. The simplest application + * costs less than 1 Kbytes RAM on the ARM Cortex-M platform. + * + * @section kernel_arch RT-Thread Architecture + * + * RT-Thread system architecture is like: + * @image html System_Arch.png "Figure 1: RT-Thread Architecture" + * + * @section kernel_service Kernel API + * + * The Kernel APIs are the core APIs of RT-Thread, which supports the following + * features: + * - Multi-thread management and scheduler + * - Synchronization mechanisms, semaphore, recursive mutex and event set + * - Inter-thread communication, mailbox and message queue + * - Memory management, memory pool and dynamic heap memory management + * - Asynchronous timer + * + * For more details, please refer to @ref Kernel + * + * @section system_init System Initialization + * + * Once RT-Thread operating system starts up, the facility in system must be initialized + * firstly. + * + * For more details, please refer to @ref SystemInit + */ diff --git a/documentation/doxygen/module.h b/documentation/doxygen/module.h index 1b7ff4db9028e89c0310e385f88d9cdf85b28a38..5fc78169859f1ef88528b00fc66954763a0d17dd 100644 --- a/documentation/doxygen/module.h +++ b/documentation/doxygen/module.h @@ -1,14 +1,14 @@ -/* - * This file is only used for doxygen document generation. - */ - -/** - * @defgroup Module Application Module - * - * @brief Application Module is a feature let user to execute application in RT-Thread RTOS. - * - * Application Module is implemented as dynamic object loader, but it can handle - * the dependences relationship between application and dynamic library, moreover, - * it also can handle the kernel object destroy and memory release issue when application - * (abnormally) exit. - */ +/* + * This file is only used for doxygen document generation. + */ + +/** + * @defgroup Module Application Module + * + * @brief Application Module is a feature let user to execute application in RT-Thread RTOS. + * + * Application Module is implemented as dynamic object loader, but it can handle + * the dependences relationship between application and dynamic library, moreover, + * it also can handle the kernel object destroy and memory release issue when application + * (abnormally) exit. + */ diff --git a/documentation/doxygen/systeminit.h b/documentation/doxygen/systeminit.h index 8508958c1dbda07679bf35f079e55a4c62f11443..d62aca59bbf097497d5175338474be92b974f2e4 100644 --- a/documentation/doxygen/systeminit.h +++ b/documentation/doxygen/systeminit.h @@ -1,79 +1,79 @@ -/* - * This file is only used for doxygen document generation. - */ - -/** - * @defgroup SystemInit System Initialization - * - * @brief System initialization procedure. - * - * When RT-Thread operating system starts up, the basic operating system facility - * initialization routines must be invoked. - * - * The suggested initialization sequence is: - * - * - initialize device hardware - * rt_hw_board_init(); - * - * User can put the low level hardware initialization in this function, such as - * DDR memory setting, pinmux setting, console device setting etc. - * - * - show version - * rt_show_version(); - * - * - initialize system tick - * rt_system_tick_init(); - * - * - initialize kernel object [deprecated] - * rt_system_object_init(); - * - * - initialize timer system - * rt_system_timer_init(); - * - * - initialize system heap memory - * rt_system_heap_init(__bss_end, __end_of_memory); - * - * - initialize module system - * rt_system_module_init(); - * - * - initialize scheduler system - * rt_system_scheduler_init(); - * - * - initialize application - * rt_application_init(); - * - * - initialize system timer thread - * rt_system_timer_thread_init(); - * - * - initialize idle thread - * rt_thread_idle_init(); - * - * - start scheduler - * rt_system_scheduler_start(); - */ - -/** - * @ingroup SystemInit - * - * This function will initialize user application. - * - * This function will be invoked when system initialization and system scheduler - * has not started. User can allocate memory, create thread, semaphore etc. However, - * user shall not suspend 'current' thread. - */ -void rt_application_init() -{ -} - -/** - * @ingroup SystemInit - * - * This function will initialize system heap memory. - * - * @param begin_addr the beginning address of system heap memory. - * @param end_addr the end address of system heap memory. - * - */ -void rt_system_heap_init(void* begin_addr, void* end_addr) -{ -} +/* + * This file is only used for doxygen document generation. + */ + +/** + * @defgroup SystemInit System Initialization + * + * @brief System initialization procedure. + * + * When RT-Thread operating system starts up, the basic operating system facility + * initialization routines must be invoked. + * + * The suggested initialization sequence is: + * + * - initialize device hardware + * rt_hw_board_init(); + * + * User can put the low level hardware initialization in this function, such as + * DDR memory setting, pinmux setting, console device setting etc. + * + * - show version + * rt_show_version(); + * + * - initialize system tick + * rt_system_tick_init(); + * + * - initialize kernel object [deprecated] + * rt_system_object_init(); + * + * - initialize timer system + * rt_system_timer_init(); + * + * - initialize system heap memory + * rt_system_heap_init(__bss_end, __end_of_memory); + * + * - initialize module system + * rt_system_module_init(); + * + * - initialize scheduler system + * rt_system_scheduler_init(); + * + * - initialize application + * rt_application_init(); + * + * - initialize system timer thread + * rt_system_timer_thread_init(); + * + * - initialize idle thread + * rt_thread_idle_init(); + * + * - start scheduler + * rt_system_scheduler_start(); + */ + +/** + * @ingroup SystemInit + * + * This function will initialize user application. + * + * This function will be invoked when system initialization and system scheduler + * has not started. User can allocate memory, create thread, semaphore etc. However, + * user shall not suspend 'current' thread. + */ +void rt_application_init() +{ +} + +/** + * @ingroup SystemInit + * + * This function will initialize system heap memory. + * + * @param begin_addr the beginning address of system heap memory. + * @param end_addr the end address of system heap memory. + * + */ +void rt_system_heap_init(void* begin_addr, void* end_addr) +{ +} diff --git a/examples/file/listdir.c b/examples/file/listdir.c index 991351fc6cb7f004d0c03f053bdc48eef3f86774..cf91bc77d4b4daffa941dbdc0405afd3580dfd4d 100644 --- a/examples/file/listdir.c +++ b/examples/file/listdir.c @@ -1,56 +1,56 @@ -/* - * File : listdir.c - * This file is part of RT-TestCase in RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-02-10 Bernard first version - */ -#include -#include - -static char fullpath[256]; -void list_dir(const char* path) -{ - DIR *dir; - - dir = opendir(path); - if (dir != RT_NULL) - { - struct dirent* dirent; - struct stat s; - - do - { - dirent = readdir(dir); - if (dirent == RT_NULL) break; - rt_memset(&s, 0, sizeof(struct stat)); - - /* build full path for each file */ - rt_sprintf(fullpath, "%s/%s", path, dirent->d_name); - - stat(fullpath, &s); - if ( s.st_mode & DFS_S_IFDIR ) - { - rt_kprintf("%s\t\t\n", dirent->d_name); - } - else - { - rt_kprintf("%s\t\t%lu\n", dirent->d_name, s.st_size); - } - } while (dirent != RT_NULL); - - closedir(dir); - } - else rt_kprintf("open %s directory failed\n", path); -} - -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT(list_dir, list directory); -#endif +/* + * File : listdir.c + * This file is part of RT-TestCase in RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-02-10 Bernard first version + */ +#include +#include + +static char fullpath[256]; +void list_dir(const char* path) +{ + DIR *dir; + + dir = opendir(path); + if (dir != RT_NULL) + { + struct dirent* dirent; + struct stat s; + + do + { + dirent = readdir(dir); + if (dirent == RT_NULL) break; + rt_memset(&s, 0, sizeof(struct stat)); + + /* build full path for each file */ + rt_sprintf(fullpath, "%s/%s", path, dirent->d_name); + + stat(fullpath, &s); + if ( s.st_mode & DFS_S_IFDIR ) + { + rt_kprintf("%s\t\t\n", dirent->d_name); + } + else + { + rt_kprintf("%s\t\t%lu\n", dirent->d_name, s.st_size); + } + } while (dirent != RT_NULL); + + closedir(dir); + } + else rt_kprintf("open %s directory failed\n", path); +} + +#ifdef RT_USING_FINSH +#include +FINSH_FUNCTION_EXPORT(list_dir, list directory); +#endif diff --git a/examples/file/readspeed.c b/examples/file/readspeed.c index d83fdcb20fe28acdf52fa20a8a87f0adfa574985..52f15b627b76a31322caee942c87e295aea635e2 100644 --- a/examples/file/readspeed.c +++ b/examples/file/readspeed.c @@ -1,64 +1,64 @@ -/* - * File : readspeed.c - * This file is part of RT-TestCase in RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-02-10 Bernard first version - */ - -#include -#include - -void readspeed(const char* filename, int block_size) -{ - int fd; - char *buff_ptr; - rt_size_t total_length; - rt_tick_t tick; - - fd = open(filename, 0, O_RDONLY); - if (fd < 0) - { - rt_kprintf("open file:%s failed\n", filename); - return; - } - - buff_ptr = rt_malloc(block_size); - if (buff_ptr == RT_NULL) - { - rt_kprintf("no memory\n"); - close(fd); - - return; - } - - tick = rt_tick_get(); - total_length = 0; - while (1) - { - int length; - length = read(fd, buff_ptr, block_size); - - if (length <= 0) break; - total_length += length; - } - tick = rt_tick_get() - tick; - - /* close file and release memory */ - close(fd); - rt_free(buff_ptr); - - /* calculate read speed */ - rt_kprintf("File read speed: %d byte/s\n", total_length /tick * RT_TICK_PER_SECOND); -} - -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT(readspeed, perform file read test); -#endif +/* + * File : readspeed.c + * This file is part of RT-TestCase in RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-02-10 Bernard first version + */ + +#include +#include + +void readspeed(const char* filename, int block_size) +{ + int fd; + char *buff_ptr; + rt_size_t total_length; + rt_tick_t tick; + + fd = open(filename, 0, O_RDONLY); + if (fd < 0) + { + rt_kprintf("open file:%s failed\n", filename); + return; + } + + buff_ptr = rt_malloc(block_size); + if (buff_ptr == RT_NULL) + { + rt_kprintf("no memory\n"); + close(fd); + + return; + } + + tick = rt_tick_get(); + total_length = 0; + while (1) + { + int length; + length = read(fd, buff_ptr, block_size); + + if (length <= 0) break; + total_length += length; + } + tick = rt_tick_get() - tick; + + /* close file and release memory */ + close(fd); + rt_free(buff_ptr); + + /* calculate read speed */ + rt_kprintf("File read speed: %d byte/s\n", total_length /tick * RT_TICK_PER_SECOND); +} + +#ifdef RT_USING_FINSH +#include +FINSH_FUNCTION_EXPORT(readspeed, perform file read test); +#endif diff --git a/examples/file/readwrite.c b/examples/file/readwrite.c index 17d173c3536fa2a283d3484aaa532b8692d8867f..6f25249c6186792b2b1ea0fa28d96a69b4300410 100644 --- a/examples/file/readwrite.c +++ b/examples/file/readwrite.c @@ -1,123 +1,123 @@ -/* - * 代ç æ¸…å•ï¼šæ–‡ä»¶è¯»å†™ä¾‹å­ - * - * 这个例å­æ¼”示了如何读写一个文件，特别是写的时候应该如何æ“作。 - */ - -#include -#include /* 当需è¦ä½¿ç”¨æ–‡ä»¶æ“作时，需è¦åŒ…å«è¿™ä¸ªå¤´æ–‡ä»¶ */ - -#define TEST_FN "/test.dat" - -/* 测试用的数æ®å’Œç¼“冲 */ -static char test_data[120], buffer[120]; - -/* 文件读写测试 */ -void readwrite(const char* filename) -{ - int fd; - int index, length; - - /* åªå†™ & 创建 打开 */ - fd = open(TEST_FN, O_WRONLY | O_CREAT | O_TRUNC, 0); - if (fd < 0) - { - rt_kprintf("open file for write failed\n"); - return; - } - - /* å‡†å¤‡å†™å…¥æ•°æ® */ - for (index = 0; index < sizeof(test_data); index ++) - { - test_data[index] = index + 27; - } - - /* å†™å…¥æ•°æ® */ - length = write(fd, test_data, sizeof(test_data)); - if (length != sizeof(test_data)) - { - rt_kprintf("write data failed\n"); - close(fd); - return; - } - - /* 关闭文件 */ - close(fd); - - /* åªå†™å¹¶åœ¨æœ«å°¾æ·»åŠ æ‰“å¼€ */ - fd = open(TEST_FN, O_WRONLY | O_CREAT | O_APPEND, 0); - if (fd < 0) - { - rt_kprintf("open file for append write failed\n"); - return; - } - - length = write(fd, test_data, sizeof(test_data)); - if (length != sizeof(test_data)) - { - rt_kprintf("append write data failed\n"); - close(fd); - return; - } - /* 关闭文件 */ - close(fd); - - /* åªè¯»æ‰“开进行数æ®æ ¡éªŒ */ - fd = open(TEST_FN, O_RDONLY, 0); - if (fd < 0) - { - rt_kprintf("check: open file for read failed\n"); - return; - } - - /* 读å–æ•°æ®(应该为第一次写入的数æ®) */ - length = read(fd, buffer, sizeof(buffer)); - if (length != sizeof(buffer)) - { - rt_kprintf("check: read file failed\n"); - close(fd); - return; - } - - /* 检查数æ®æ˜¯å¦æ­£ç¡® */ - for (index = 0; index < sizeof(test_data); index ++) - { - if (test_data[index] != buffer[index]) - { - rt_kprintf("check: check data failed at %d\n", index); - close(fd); - return; - } - } - - /* 读å–æ•°æ®(应该为第二次写入的数æ®) */ - length = read(fd, buffer, sizeof(buffer)); - if (length != sizeof(buffer)) - { - rt_kprintf("check: read file failed\n"); - close(fd); - return; - } - - /* 检查数æ®æ˜¯å¦æ­£ç¡® */ - for (index = 0; index < sizeof(test_data); index ++) - { - if (test_data[index] != buffer[index]) - { - rt_kprintf("check: check data failed at %d\n", index); - close(fd); - return; - } - } - - /* 检查数æ®å®Œæ¯•ï¼Œå…³é—­æ–‡ä»¶ */ - close(fd); - /* 打å°ç»“æžœ */ - rt_kprintf("read/write done.\n"); -} - -#ifdef RT_USING_FINSH -#include -/* 输出函数到finsh shell命令行中 */ -FINSH_FUNCTION_EXPORT(readwrite, perform file read and write test); -#endif +/* + * 代ç æ¸…å•ï¼šæ–‡ä»¶è¯»å†™ä¾‹å­ + * + * 这个例å­æ¼”示了如何读写一个文件，特别是写的时候应该如何æ“作。 + */ + +#include +#include /* 当需è¦ä½¿ç”¨æ–‡ä»¶æ“作时，需è¦åŒ…å«è¿™ä¸ªå¤´æ–‡ä»¶ */ + +#define TEST_FN "/test.dat" + +/* 测试用的数æ®å’Œç¼“冲 */ +static char test_data[120], buffer[120]; + +/* 文件读写测试 */ +void readwrite(const char* filename) +{ + int fd; + int index, length; + + /* åªå†™ & 创建 打开 */ + fd = open(TEST_FN, O_WRONLY | O_CREAT | O_TRUNC, 0); + if (fd < 0) + { + rt_kprintf("open file for write failed\n"); + return; + } + + /* å‡†å¤‡å†™å…¥æ•°æ® */ + for (index = 0; index < sizeof(test_data); index ++) + { + test_data[index] = index + 27; + } + + /* å†™å…¥æ•°æ® */ + length = write(fd, test_data, sizeof(test_data)); + if (length != sizeof(test_data)) + { + rt_kprintf("write data failed\n"); + close(fd); + return; + } + + /* 关闭文件 */ + close(fd); + + /* åªå†™å¹¶åœ¨æœ«å°¾æ·»åŠ æ‰“å¼€ */ + fd = open(TEST_FN, O_WRONLY | O_CREAT | O_APPEND, 0); + if (fd < 0) + { + rt_kprintf("open file for append write failed\n"); + return; + } + + length = write(fd, test_data, sizeof(test_data)); + if (length != sizeof(test_data)) + { + rt_kprintf("append write data failed\n"); + close(fd); + return; + } + /* 关闭文件 */ + close(fd); + + /* åªè¯»æ‰“开进行数æ®æ ¡éªŒ */ + fd = open(TEST_FN, O_RDONLY, 0); + if (fd < 0) + { + rt_kprintf("check: open file for read failed\n"); + return; + } + + /* 读å–æ•°æ®(应该为第一次写入的数æ®) */ + length = read(fd, buffer, sizeof(buffer)); + if (length != sizeof(buffer)) + { + rt_kprintf("check: read file failed\n"); + close(fd); + return; + } + + /* 检查数æ®æ˜¯å¦æ­£ç¡® */ + for (index = 0; index < sizeof(test_data); index ++) + { + if (test_data[index] != buffer[index]) + { + rt_kprintf("check: check data failed at %d\n", index); + close(fd); + return; + } + } + + /* 读å–æ•°æ®(应该为第二次写入的数æ®) */ + length = read(fd, buffer, sizeof(buffer)); + if (length != sizeof(buffer)) + { + rt_kprintf("check: read file failed\n"); + close(fd); + return; + } + + /* 检查数æ®æ˜¯å¦æ­£ç¡® */ + for (index = 0; index < sizeof(test_data); index ++) + { + if (test_data[index] != buffer[index]) + { + rt_kprintf("check: check data failed at %d\n", index); + close(fd); + return; + } + } + + /* 检查数æ®å®Œæ¯•ï¼Œå…³é—­æ–‡ä»¶ */ + close(fd); + /* 打å°ç»“æžœ */ + rt_kprintf("read/write done.\n"); +} + +#ifdef RT_USING_FINSH +#include +/* 输出函数到finsh shell命令行中 */ +FINSH_FUNCTION_EXPORT(readwrite, perform file read and write test); +#endif diff --git a/examples/file/seekdir.c b/examples/file/seekdir.c index 831023f8ebb5abaa986e9d5111516fc3408939bb..1cf8b5fd78020259c0c4e5c2bea111e7849f5024 100644 --- a/examples/file/seekdir.c +++ b/examples/file/seekdir.c @@ -1,50 +1,50 @@ -/* - * File : seekdir.c - * This file is part of RT-TestCase in RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-06-02 Bernard first version - */ -#include - -void seekdir_test(void) -{ - DIR * dirp; - long save3 = 0; - long cur; - int i = 0; - struct dirent *dp; - - dirp = opendir ("/"); - save3 = telldir(dirp); - for (dp = readdir(dirp); dp != RT_NULL; dp = readdir(dirp)) - { - rt_kprintf("direntry: %s\n", dp->d_name); - - /* ±£´æµÚÈý¸öĿ¼ÏîµÄĿ¼ָÕë */ - if (i++ == 3) - { - save3 = telldir(dirp); - } - } - - /* »Øµ½¸Õ²Å±£´æµÄµÚÈý¸öĿ¼ÏîµÄĿ¼ָÕë */ - seekdir (dirp, save3); - rt_kprintf("seek dientry to: %d\n", save3); - for (dp = readdir(dirp); dp != RT_NULL; dp = readdir(dirp)) - { - rt_kprintf("direntry: %s\n", dp->d_name); - } - - /* ¹Ø±ÕĿ¼ */ - closedir (dirp); -} - -#include -FINSH_FUNCTION_EXPORT(seekdir_test, perform directory seek test); +/* + * File : seekdir.c + * This file is part of RT-TestCase in RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-06-02 Bernard first version + */ +#include + +void seekdir_test(void) +{ + DIR * dirp; + long save3 = 0; + long cur; + int i = 0; + struct dirent *dp; + + dirp = opendir ("/"); + save3 = telldir(dirp); + for (dp = readdir(dirp); dp != RT_NULL; dp = readdir(dirp)) + { + rt_kprintf("direntry: %s\n", dp->d_name); + + /* ±£´æµÚÈý¸öĿ¼ÏîµÄĿ¼ָÕë */ + if (i++ == 3) + { + save3 = telldir(dirp); + } + } + + /* »Øµ½¸Õ²Å±£´æµÄµÚÈý¸öĿ¼ÏîµÄĿ¼ָÕë */ + seekdir (dirp, save3); + rt_kprintf("seek dientry to: %d\n", save3); + for (dp = readdir(dirp); dp != RT_NULL; dp = readdir(dirp)) + { + rt_kprintf("direntry: %s\n", dp->d_name); + } + + /* ¹Ø±ÕĿ¼ */ + closedir (dirp); +} + +#include +FINSH_FUNCTION_EXPORT(seekdir_test, perform directory seek test); diff --git a/examples/file/writespeed.c b/examples/file/writespeed.c index 5fa2f44452f5e0873f607c8c40f6d6973b323059..ab6946888fde2da187297709d5a33165a056252a 100644 --- a/examples/file/writespeed.c +++ b/examples/file/writespeed.c @@ -1,72 +1,72 @@ -/* - * File : writespeed.c - * This file is part of RT-TestCase in RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-02-10 Bernard first version - */ -#include -#include - -void writespeed(const char* filename, int total_length, int block_size) -{ - int fd, index, length; - char *buff_ptr; - rt_tick_t tick; - - fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0); - if (fd < 0) - { - rt_kprintf("open file:%s failed\n", filename); - return; - } - - buff_ptr = rt_malloc(block_size); - if (buff_ptr == RT_NULL) - { - rt_kprintf("no memory\n"); - close(fd); - - return; - } - - /* prepare write data */ - for (index = 0; index < block_size; index++) - { - buff_ptr[index] = index; - } - index = 0; - - /* get the beginning tick */ - tick = rt_tick_get(); - while (index < total_length / block_size) - { - length = write(fd, buff_ptr, block_size); - if (length != block_size) - { - rt_kprintf("write failed\n"); - break; - } - - index ++; - } - tick = rt_tick_get() - tick; - - /* close file and release memory */ - close(fd); - rt_free(buff_ptr); - - /* calculate write speed */ - rt_kprintf("File write speed: %d byte/s\n", total_length / tick * RT_TICK_PER_SECOND); -} - -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT(writespeed, perform file write test); -#endif +/* + * File : writespeed.c + * This file is part of RT-TestCase in RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-02-10 Bernard first version + */ +#include +#include + +void writespeed(const char* filename, int total_length, int block_size) +{ + int fd, index, length; + char *buff_ptr; + rt_tick_t tick; + + fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0); + if (fd < 0) + { + rt_kprintf("open file:%s failed\n", filename); + return; + } + + buff_ptr = rt_malloc(block_size); + if (buff_ptr == RT_NULL) + { + rt_kprintf("no memory\n"); + close(fd); + + return; + } + + /* prepare write data */ + for (index = 0; index < block_size; index++) + { + buff_ptr[index] = index; + } + index = 0; + + /* get the beginning tick */ + tick = rt_tick_get(); + while (index < total_length / block_size) + { + length = write(fd, buff_ptr, block_size); + if (length != block_size) + { + rt_kprintf("write failed\n"); + break; + } + + index ++; + } + tick = rt_tick_get() - tick; + + /* close file and release memory */ + close(fd); + rt_free(buff_ptr); + + /* calculate write speed */ + rt_kprintf("File write speed: %d byte/s\n", total_length / tick * RT_TICK_PER_SECOND); +} + +#ifdef RT_USING_FINSH +#include +FINSH_FUNCTION_EXPORT(writespeed, perform file write test); +#endif diff --git a/examples/kernel/SConscript b/examples/kernel/SConscript index 361008515770dc7a43cab5d88c9f665cf41aaa7b..bfbc80b54a18df195feea98bdbe97624383e905d 100644 --- a/examples/kernel/SConscript +++ b/examples/kernel/SConscript @@ -1,39 +1,39 @@ -from building import * - -src = Split(""" -tc_comm.c -thread_static.c -thread_dynamic.c -thread_priority.c -thread_same_priority.c -thread_static_simple.c -thread_dynamic_simple.c -thread_delete.c -thread_detach.c -thread_yield.c -thread_suspend.c -thread_resume.c -semaphore_static.c -semaphore_dynamic.c -semaphore_priority.c -semaphore_buffer_worker.c -semaphore_producer_consumer.c -mutex_simple.c -event_simple.c -mbox_simple.c -mbox_send_wait.c -messageq_simple.c -timer_static.c -timer_dynamic.c -timer_stop_self.c -timer_control.c -timer_timeout.c -heap_malloc.c -heap_realloc.c -memp_simple.c -tc_sample.c -""") - -group = DefineGroup('examples', src, depend = ['RT_USING_TC']) - -Return('group') +from building import * + +src = Split(""" +tc_comm.c +thread_static.c +thread_dynamic.c +thread_priority.c +thread_same_priority.c +thread_static_simple.c +thread_dynamic_simple.c +thread_delete.c +thread_detach.c +thread_yield.c +thread_suspend.c +thread_resume.c +semaphore_static.c +semaphore_dynamic.c +semaphore_priority.c +semaphore_buffer_worker.c +semaphore_producer_consumer.c +mutex_simple.c +event_simple.c +mbox_simple.c +mbox_send_wait.c +messageq_simple.c +timer_static.c +timer_dynamic.c +timer_stop_self.c +timer_control.c +timer_timeout.c +heap_malloc.c +heap_realloc.c +memp_simple.c +tc_sample.c +""") + +group = DefineGroup('examples', src, depend = ['RT_USING_TC']) + +Return('group') diff --git a/examples/kernel/heap_malloc.c b/examples/kernel/heap_malloc.c index 236a982fdfeecc71fbde8ee87a97d50a84c6a2d4..0a6b46cc951fc369c52ba1c33b90ef1b5b3ff348 100644 --- a/examples/kernel/heap_malloc.c +++ b/examples/kernel/heap_malloc.c @@ -1,72 +1,72 @@ -#include -#include "tc_comm.h" - -/* - * This is an example for heap malloc - */ - -static rt_bool_t mem_check(rt_uint8_t *ptr, rt_uint8_t value, rt_uint32_t len) -{ - while (len) - { - if (*ptr != value) return RT_FALSE; - - ptr ++; - len --; - } - - return RT_TRUE; -} - -static void heap_malloc_init() -{ - rt_uint8_t *ptr1, *ptr2, *ptr3, *ptr4, *ptr5; - - ptr1 = rt_malloc(1); - ptr2 = rt_malloc(13); - ptr3 = rt_malloc(31); - ptr4 = rt_malloc(127); - ptr5 = rt_malloc(0); - - memset(ptr1, 1, 1); - memset(ptr2, 2, 13); - memset(ptr3, 3, 31); - memset(ptr4, 4, 127); - - if (mem_check(ptr1, 1, 1) != RT_FALSE) goto _failed; - if (mem_check(ptr2, 2, 13) != RT_FALSE) goto _failed; - if (mem_check(ptr3, 3, 31) != RT_FALSE) goto _failed; - if (mem_check(ptr4, 4, 127) != RT_FALSE) goto _failed; - - rt_free(ptr4); - rt_free(ptr3); - rt_free(ptr3); - rt_free(ptr1); - - if (ptr5 != RT_NULL) - { - rt_free(ptr5); - } - - tc_done(TC_STAT_PASSED); - -_failed: - tc_done(TC_STAT_FAILED); -} - -#ifdef RT_USING_TC -int _tc_heap_malloc() -{ - heap_malloc_init(); - - return 0; -} -FINSH_FUNCTION_EXPORT(_tc_heap_malloc, a heap malloc test); -#else -int rt_application_init() -{ - heap_malloc_init(); - - return 0; -} -#endif +#include +#include "tc_comm.h" + +/* + * This is an example for heap malloc + */ + +static rt_bool_t mem_check(rt_uint8_t *ptr, rt_uint8_t value, rt_uint32_t len) +{ + while (len) + { + if (*ptr != value) return RT_FALSE; + + ptr ++; + len --; + } + + return RT_TRUE; +} + +static void heap_malloc_init() +{ + rt_uint8_t *ptr1, *ptr2, *ptr3, *ptr4, *ptr5; + + ptr1 = rt_malloc(1); + ptr2 = rt_malloc(13); + ptr3 = rt_malloc(31); + ptr4 = rt_malloc(127); + ptr5 = rt_malloc(0); + + memset(ptr1, 1, 1); + memset(ptr2, 2, 13); + memset(ptr3, 3, 31); + memset(ptr4, 4, 127); + + if (mem_check(ptr1, 1, 1) != RT_FALSE) goto _failed; + if (mem_check(ptr2, 2, 13) != RT_FALSE) goto _failed; + if (mem_check(ptr3, 3, 31) != RT_FALSE) goto _failed; + if (mem_check(ptr4, 4, 127) != RT_FALSE) goto _failed; + + rt_free(ptr4); + rt_free(ptr3); + rt_free(ptr3); + rt_free(ptr1); + + if (ptr5 != RT_NULL) + { + rt_free(ptr5); + } + + tc_done(TC_STAT_PASSED); + +_failed: + tc_done(TC_STAT_FAILED); +} + +#ifdef RT_USING_TC +int _tc_heap_malloc() +{ + heap_malloc_init(); + + return 0; +} +FINSH_FUNCTION_EXPORT(_tc_heap_malloc, a heap malloc test); +#else +int rt_application_init() +{ + heap_malloc_init(); + + return 0; +} +#endif diff --git a/examples/kernel/heap_realloc.c b/examples/kernel/heap_realloc.c index 5fa96c7f304162448b38cc2bd62d932a7a8e8f4d..a4974d5bf3468cb75c2ba2fbb62b9c5aba58a2a0 100644 --- a/examples/kernel/heap_realloc.c +++ b/examples/kernel/heap_realloc.c @@ -1,83 +1,83 @@ -#include -#include "tc_comm.h" - -/* - * This is an example for heap malloc - */ - -static rt_bool_t mem_check(rt_uint8_t *ptr, rt_uint8_t value, rt_uint32_t len) -{ - while (len) - { - if (*ptr != value) return RT_FALSE; - - ptr ++; - len --; - } - - return RT_TRUE; -} - -static void heap_realloc_init() -{ - rt_uint8_t *ptr1, *ptr2, *ptr3, *ptr4, *ptr5; - - ptr1 = rt_malloc(1); - ptr2 = rt_malloc(13); - ptr3 = rt_malloc(31); - ptr4 = rt_malloc(127); - ptr5 = rt_malloc(0); - - memset(ptr1, 1, 1); - memset(ptr2, 2, 13); - memset(ptr3, 3, 31); - memset(ptr4, 4, 127); - - if (mem_check(ptr1, 1, 1) != RT_FALSE) goto _failed; - if (mem_check(ptr2, 2, 13) != RT_FALSE) goto _failed; - if (mem_check(ptr3, 3, 31) != RT_FALSE) goto _failed; - if (mem_check(ptr4, 4, 127) != RT_FALSE) goto _failed; - - ptr1 = rt_realloc(ptr1, 13); - ptr2 = rt_realloc(ptr2, 31); - ptr3 = rt_realloc(ptr3, 127); - ptr4 = rt_realloc(ptr4, 1); - ptr5 = rt_realloc(ptr5, 0); - - if (mem_check(ptr1, 1, 1) != RT_FALSE) goto _failed; - if (mem_check(ptr2, 2, 13) != RT_FALSE) goto _failed; - if (mem_check(ptr3, 3, 31) != RT_FALSE) goto _failed; - if (mem_check(ptr4, 4, 1) != RT_FALSE) goto _failed; - - rt_free(ptr4); - rt_free(ptr3); - rt_free(ptr3); - rt_free(ptr1); - - if (ptr5 != RT_NULL) - { - rt_free(ptr5); - } - - tc_done(TC_STAT_PASSED); - -_failed: - tc_done(TC_STAT_FAILED); -} - -#ifdef RT_USING_TC -int _tc_heap_realloc() -{ - heap_realloc_init(); - - return 0; -} -FINSH_FUNCTION_EXPORT(_tc_heap_realloc, a heap re-malloc test); -#else -int rt_application_init() -{ - heap_realloc_init(); - - return 0; -} -#endif +#include +#include "tc_comm.h" + +/* + * This is an example for heap malloc + */ + +static rt_bool_t mem_check(rt_uint8_t *ptr, rt_uint8_t value, rt_uint32_t len) +{ + while (len) + { + if (*ptr != value) return RT_FALSE; + + ptr ++; + len --; + } + + return RT_TRUE; +} + +static void heap_realloc_init() +{ + rt_uint8_t *ptr1, *ptr2, *ptr3, *ptr4, *ptr5; + + ptr1 = rt_malloc(1); + ptr2 = rt_malloc(13); + ptr3 = rt_malloc(31); + ptr4 = rt_malloc(127); + ptr5 = rt_malloc(0); + + memset(ptr1, 1, 1); + memset(ptr2, 2, 13); + memset(ptr3, 3, 31); + memset(ptr4, 4, 127); + + if (mem_check(ptr1, 1, 1) != RT_FALSE) goto _failed; + if (mem_check(ptr2, 2, 13) != RT_FALSE) goto _failed; + if (mem_check(ptr3, 3, 31) != RT_FALSE) goto _failed; + if (mem_check(ptr4, 4, 127) != RT_FALSE) goto _failed; + + ptr1 = rt_realloc(ptr1, 13); + ptr2 = rt_realloc(ptr2, 31); + ptr3 = rt_realloc(ptr3, 127); + ptr4 = rt_realloc(ptr4, 1); + ptr5 = rt_realloc(ptr5, 0); + + if (mem_check(ptr1, 1, 1) != RT_FALSE) goto _failed; + if (mem_check(ptr2, 2, 13) != RT_FALSE) goto _failed; + if (mem_check(ptr3, 3, 31) != RT_FALSE) goto _failed; + if (mem_check(ptr4, 4, 1) != RT_FALSE) goto _failed; + + rt_free(ptr4); + rt_free(ptr3); + rt_free(ptr3); + rt_free(ptr1); + + if (ptr5 != RT_NULL) + { + rt_free(ptr5); + } + + tc_done(TC_STAT_PASSED); + +_failed: + tc_done(TC_STAT_FAILED); +} + +#ifdef RT_USING_TC +int _tc_heap_realloc() +{ + heap_realloc_init(); + + return 0; +} +FINSH_FUNCTION_EXPORT(_tc_heap_realloc, a heap re-malloc test); +#else +int rt_application_init() +{ + heap_realloc_init(); + + return 0; +} +#endif diff --git a/examples/kernel/mutex_simple.c b/examples/kernel/mutex_simple.c index c098018da0f367211fbd0d4b234107c567818d4d..8545ddc660be52d93b25d305d92a05b02ac00251 100644 --- a/examples/kernel/mutex_simple.c +++ b/examples/kernel/mutex_simple.c @@ -1,163 +1,163 @@ -/* - * 程åºæ¸…å•ï¼š - */ -#include -#include "tc_comm.h" - -/* 指å‘线程控制å—的指针 */ -static rt_thread_t tid1 = RT_NULL; -static rt_thread_t tid2 = RT_NULL; -static rt_thread_t tid3 = RT_NULL; -static rt_mutex_t mutex = RT_NULL; - -/* 线程1å…¥å£ */ -static void thread1_entry(void* parameter) -{ - /* 先让低优先级线程è¿è¡Œ */ - rt_thread_delay(10); - - /* 此时thread3æŒæœ‰mutex，并且thread2等待æŒæœ‰mutex */ - - /* 检查thread2与thread3的优先级情况 */ - if (tid2->current_priority != tid3->current_priority) - { - /* 优先级ä¸ç›¸åŒï¼Œæµ‹è¯•å¤±è´¥ */ - tc_stat(TC_STAT_END | TC_STAT_FAILED); - return; - } -} - -/* 线程2å…¥å£ */ -static void thread2_entry(void* parameter) -{ - rt_err_t result; - - /* 先让低优先级线程è¿è¡Œ */ - rt_thread_delay(5); - - while (1) - { - /* - * 试图æŒæœ‰äº’æ–¥é”，此时thread3æŒæœ‰ï¼Œåº”把thread3的优先级æå‡åˆ°thread2ç›¸åŒ - * 的优先级 - */ - result = rt_mutex_take(mutex, RT_WAITING_FOREVER); - - if (result == RT_EOK) - { - /* é‡Šæ”¾äº’æ–¥é” */ - rt_mutex_release(mutex); - } - } -} - -/* 线程3å…¥å£ */ -static void thread3_entry(void* parameter) -{ - rt_tick_t tick; - rt_err_t result; - - while (1) - { - result = rt_mutex_take(mutex, RT_WAITING_FOREVER); - result = rt_mutex_take(mutex, RT_WAITING_FOREVER); - if (result != RT_EOK) - { - tc_stat(TC_STAT_END | TC_STAT_FAILED); - } - - /* åšä¸€ä¸ªé•¿æ—¶é—´çš„循环，总共50个OS Tick */ - tick = rt_tick_get(); - while (rt_tick_get() - tick < 50) ; - - rt_mutex_release(mutex); - rt_mutex_release(mutex); - } -} - -int mutex_simple_init() -{ - /* åˆ›å»ºäº’æ–¥é” */ - mutex = rt_mutex_create("mutex", RT_IPC_FLAG_FIFO); - if (mutex == RT_NULL) - { - tc_stat(TC_STAT_END | TC_STAT_FAILED); - return 0; - } - - /* 创建线程1 */ - tid1 = rt_thread_create("t1", - thread1_entry, RT_NULL, /* 线程入å£æ˜¯thread1_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); - if (tid1 != RT_NULL) - rt_thread_startup(tid1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* 创建线程2 */ - tid2 = rt_thread_create("t2", - thread2_entry, RT_NULL, /* 线程入å£æ˜¯thread2_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid2 != RT_NULL) - rt_thread_startup(tid2); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* 创建线程3 */ - tid3 = rt_thread_create("t3", - thread3_entry, RT_NULL, /* 线程入å£æ˜¯thread3_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY + 1, THREAD_TIMESLICE); - if (tid3 != RT_NULL) - rt_thread_startup(tid3); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除线程 */ - if (tid1 != RT_NULL && tid1->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid1); - if (tid2 != RT_NULL && tid2->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid2); - if (tid3 != RT_NULL && tid3->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid3); - - if (mutex != RT_NULL) - { - rt_mutex_delete(mutex); - } - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_mutex_simple() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - mutex_simple_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_mutex_simple, sime mutex example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - mutex_simple_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼š + */ +#include +#include "tc_comm.h" + +/* 指å‘线程控制å—的指针 */ +static rt_thread_t tid1 = RT_NULL; +static rt_thread_t tid2 = RT_NULL; +static rt_thread_t tid3 = RT_NULL; +static rt_mutex_t mutex = RT_NULL; + +/* 线程1å…¥å£ */ +static void thread1_entry(void* parameter) +{ + /* 先让低优先级线程è¿è¡Œ */ + rt_thread_delay(10); + + /* 此时thread3æŒæœ‰mutex，并且thread2等待æŒæœ‰mutex */ + + /* 检查thread2与thread3的优先级情况 */ + if (tid2->current_priority != tid3->current_priority) + { + /* 优先级ä¸ç›¸åŒï¼Œæµ‹è¯•å¤±è´¥ */ + tc_stat(TC_STAT_END | TC_STAT_FAILED); + return; + } +} + +/* 线程2å…¥å£ */ +static void thread2_entry(void* parameter) +{ + rt_err_t result; + + /* 先让低优先级线程è¿è¡Œ */ + rt_thread_delay(5); + + while (1) + { + /* + * 试图æŒæœ‰äº’æ–¥é”，此时thread3æŒæœ‰ï¼Œåº”把thread3的优先级æå‡åˆ°thread2ç›¸åŒ + * 的优先级 + */ + result = rt_mutex_take(mutex, RT_WAITING_FOREVER); + + if (result == RT_EOK) + { + /* é‡Šæ”¾äº’æ–¥é” */ + rt_mutex_release(mutex); + } + } +} + +/* 线程3å…¥å£ */ +static void thread3_entry(void* parameter) +{ + rt_tick_t tick; + rt_err_t result; + + while (1) + { + result = rt_mutex_take(mutex, RT_WAITING_FOREVER); + result = rt_mutex_take(mutex, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + tc_stat(TC_STAT_END | TC_STAT_FAILED); + } + + /* åšä¸€ä¸ªé•¿æ—¶é—´çš„循环，总共50个OS Tick */ + tick = rt_tick_get(); + while (rt_tick_get() - tick < 50) ; + + rt_mutex_release(mutex); + rt_mutex_release(mutex); + } +} + +int mutex_simple_init() +{ + /* åˆ›å»ºäº’æ–¥é” */ + mutex = rt_mutex_create("mutex", RT_IPC_FLAG_FIFO); + if (mutex == RT_NULL) + { + tc_stat(TC_STAT_END | TC_STAT_FAILED); + return 0; + } + + /* 创建线程1 */ + tid1 = rt_thread_create("t1", + thread1_entry, RT_NULL, /* 线程入å£æ˜¯thread1_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); + if (tid1 != RT_NULL) + rt_thread_startup(tid1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* 创建线程2 */ + tid2 = rt_thread_create("t2", + thread2_entry, RT_NULL, /* 线程入å£æ˜¯thread2_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid2 != RT_NULL) + rt_thread_startup(tid2); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* 创建线程3 */ + tid3 = rt_thread_create("t3", + thread3_entry, RT_NULL, /* 线程入å£æ˜¯thread3_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY + 1, THREAD_TIMESLICE); + if (tid3 != RT_NULL) + rt_thread_startup(tid3); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除线程 */ + if (tid1 != RT_NULL && tid1->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid1); + if (tid2 != RT_NULL && tid2->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid2); + if (tid3 != RT_NULL && tid3->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid3); + + if (mutex != RT_NULL) + { + rt_mutex_delete(mutex); + } + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_mutex_simple() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + mutex_simple_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_mutex_simple, sime mutex example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + mutex_simple_init(); + + return 0; +} +#endif diff --git a/examples/kernel/semaphore_buffer_worker.c b/examples/kernel/semaphore_buffer_worker.c index af5722547ae440894431794e7c4916f84052e6a4..6e5920dd6fbcf90e4ab4f19c8ce037ef29de62ac 100644 --- a/examples/kernel/semaphore_buffer_worker.c +++ b/examples/kernel/semaphore_buffer_worker.c @@ -1,267 +1,267 @@ -/* - * 程åºæ¸…å•ï¼šä¿¡å·é‡å®žçŽ°ç”Ÿäº§è€…消费者间的互斥 - * - * 在这个程åºä¸­ï¼Œä¼šåˆ›å»ºä¸¤ä¸ªçº¿ç¨‹ï¼Œä¸€ä¸ªæ˜¯ç”Ÿæˆè€…线程worker一个是消费者线程thread - * - * 在数æ®ä¿¡æ¯ç”Ÿäº§ã€æ¶ˆè´¹çš„过程中，worker负责把数æ®å°†å†™å…¥åˆ°çŽ¯å½¢buffer中，而thread - * 则从环形buffer中读出。 - */ -#include -#include "tc_comm.h" - -/* 一个环形buffer的实现 */ -struct rb -{ - rt_uint16_t read_index, write_index; - rt_uint8_t *buffer_ptr; - rt_uint16_t buffer_size; -}; - -/* 指å‘ä¿¡å·é‡æŽ§åˆ¶å—的指针 */ -static rt_sem_t sem = RT_NULL; -/* 指å‘线程控制å—的指针 */ -static rt_thread_t tid = RT_NULL, worker = RT_NULL; - -/* 环形buffer的内存å—（用数组体现出æ¥ï¼‰ */ -#define BUFFER_SIZE 256 -#define BUFFER_ITEM 32 -static rt_uint8_t working_buffer[BUFFER_SIZE]; -struct rb working_rb; - -/* åˆå§‹åŒ–环形buffer，size指的是buffer的大å°ã€‚注：这里并没对数æ®åœ°å€å¯¹é½åšå¤„ç† */ -static void rb_init(struct rb* rb, rt_uint8_t *pool, rt_uint16_t size) -{ - RT_ASSERT(rb != RT_NULL); - - /* 对读写指针清零*/ - rb->read_index = rb->write_index = 0; - - /* 设置环形buffer的内存数æ®å— */ - rb->buffer_ptr = pool; - rb->buffer_size = size; -} - -/* å‘环形bufferä¸­å†™å…¥æ•°æ® */ -static rt_bool_t rb_put(struct rb* rb, const rt_uint8_t *ptr, rt_uint16_t length) -{ - rt_size_t size; - - /* 判断是å¦æœ‰è¶³å¤Ÿçš„剩余空间 */ - if (rb->read_index > rb->write_index) - size = rb->read_index - rb->write_index; - else - size = rb->buffer_size - rb->write_index + rb->read_index; - - /* 没有多余的空间 */ - if (size < length) return RT_FALSE; - - if (rb->read_index > rb->write_index) - { - /* read_index - write_index å³ä¸ºæ€»çš„空余空间 */ - memcpy(&rb->buffer_ptr[rb->write_index], ptr, length); - rb->write_index += length; - } - else - { - if (rb->buffer_size - rb->write_index > length) - { - /* write_index åŽé¢å‰©ä½™çš„空间有足够的长度 */ - memcpy(&rb->buffer_ptr[rb->write_index], ptr, length); - rb->write_index += length; - } - else - { - /* - * write_index åŽé¢å‰©ä½™çš„空间ä¸å­˜åœ¨è¶³å¤Ÿçš„长度，需è¦æŠŠéƒ¨åˆ†æ•°æ®å¤åˆ¶åˆ° - * å‰é¢çš„剩余空间中 - */ - memcpy(&rb->buffer_ptr[rb->write_index], ptr, - rb->buffer_size - rb->write_index); - memcpy(&rb->buffer_ptr[0], &ptr[rb->buffer_size - rb->write_index], - length - (rb->buffer_size - rb->write_index)); - rb->write_index = length - (rb->buffer_size - rb->write_index); - } - } - - return RT_TRUE; -} - -/* 从环形bufferä¸­è¯»å‡ºæ•°æ® */ -static rt_bool_t rb_get(struct rb* rb, rt_uint8_t *ptr, rt_uint16_t length) -{ - rt_size_t size; - - /* 判断是å¦æœ‰è¶³å¤Ÿçš„æ•°æ® */ - if (rb->read_index > rb->write_index) - size = rb->buffer_size - rb->read_index + rb->write_index; - else - size = rb->write_index - rb->read_index; - - /* æ²¡æœ‰è¶³å¤Ÿçš„æ•°æ® */ - if (size < length) return RT_FALSE; - - if (rb->read_index > rb->write_index) - { - if (rb->buffer_size - rb->read_index > length) - { - /* read_indexçš„æ•°æ®è¶³å¤Ÿå¤šï¼Œç›´æŽ¥å¤åˆ¶ */ - memcpy(ptr, &rb->buffer_ptr[rb->read_index], length); - rb->read_index += length; - } - else - { - /* read_indexçš„æ•°æ®ä¸å¤Ÿï¼Œéœ€è¦åˆ†æ®µå¤åˆ¶ */ - memcpy(ptr, &rb->buffer_ptr[rb->read_index], - rb->buffer_size - rb->read_index); - memcpy(&ptr[rb->buffer_size - rb->read_index], &rb->buffer_ptr[0], - length - rb->buffer_size + rb->read_index); - rb->read_index = length - rb->buffer_size + rb->read_index; - } - } - else - { - /* - * read_indexè¦æ¯”write_indexå°ï¼Œæ€»çš„æ•°æ®é‡å¤Ÿï¼ˆå‰é¢å·²ç»æœ‰æ€»æ•°æ®é‡çš„判 - * 断），直接å¤åˆ¶å‡ºæ•°æ®ã€‚ - */ - memcpy(ptr, &rb->buffer_ptr[rb->read_index], length); - rb->read_index += length; - } - - return RT_TRUE; -} - -/* ç”Ÿäº§è€…çº¿ç¨‹å…¥å£ */ -static void thread_entry(void* parameter) -{ - rt_bool_t result; - rt_uint8_t data_buffer[BUFFER_ITEM + 1]; - - while (1) - { - /* æŒæœ‰ä¿¡å·é‡ */ - rt_sem_take(sem, RT_WAITING_FOREVER); - /* 从环bufferä¸­èŽ·å¾—æ•°æ® */ - result = rb_get(&working_rb, &data_buffer[0], BUFFER_ITEM); - /* 释放信å·é‡ */ - rt_sem_release(sem); - data_buffer[BUFFER_ITEM] = '\0'; - - if (result == RT_TRUE) - { - /* 获å–æ•°æ®æˆåŠŸï¼Œæ‰“å°æ•°æ® */ - rt_kprintf("%s\n", data_buffer); - } - - /* åšä¸€ä¸ª5 OS Tick的休眠 */ - rt_thread_delay(5); - } -} - -/* workerçº¿ç¨‹å…¥å£ */ -static void worker_entry(void* parameter) -{ - rt_bool_t result; - rt_uint32_t index, setchar; - rt_uint8_t data_buffer[BUFFER_ITEM]; - - setchar = 0x21; - while (1) - { - /* æž„é€ æ•°æ® */ - for(index = 0; index < BUFFER_ITEM; index++) - { - data_buffer[index] = setchar; - if (++setchar == 0x7f) - setchar = 0x21; - } - - /* æŒæœ‰ä¿¡å·é‡ */ - rt_sem_take(sem, RT_WAITING_FOREVER); - /* 把数æ®æ”¾åˆ°çŽ¯å½¢buffer中 */ - result = rb_put(&working_rb, &data_buffer[0], BUFFER_ITEM); - /* 释放信å·é‡ */ - rt_sem_release(sem); - - /* 放入æˆåŠŸï¼Œåšä¸€ä¸ª10 OS Tick的休眠 */ - rt_thread_delay(10); - } -} - -int semaphore_buffer_worker_init() -{ - /* åˆå§‹åŒ–ring buffer */ - rb_init(&working_rb, working_buffer, BUFFER_SIZE); - - /* 创建信å·é‡ */ - sem = rt_sem_create("sem", 1, RT_IPC_FLAG_FIFO); - if (sem == RT_NULL) - { - tc_stat(TC_STAT_END | TC_STAT_FAILED); - return 0; - } - - /* 创建线程1 */ - tid = rt_thread_create("thread", - thread_entry, RT_NULL, /* 线程入å£æ˜¯thread_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid != RT_NULL) - rt_thread_startup(tid); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* 创建线程2 */ - worker = rt_thread_create("worker", - worker_entry, RT_NULL, /* 线程入å£æ˜¯worker_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (worker != RT_NULL) - rt_thread_startup(worker); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除信å·é‡ */ - if (sem != RT_NULL) - rt_sem_delete(sem); - - /* 删除线程 */ - if (tid != RT_NULL && tid->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid); - if (worker != RT_NULL && worker->stat != RT_THREAD_CLOSE) - rt_thread_delete(worker); - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_semaphore_buffer_worker() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - semaphore_buffer_worker_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_semaphore_buffer_worker, a buffer worker with semaphore example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - semaphore_buffer_worker_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šä¿¡å·é‡å®žçŽ°ç”Ÿäº§è€…消费者间的互斥 + * + * 在这个程åºä¸­ï¼Œä¼šåˆ›å»ºä¸¤ä¸ªçº¿ç¨‹ï¼Œä¸€ä¸ªæ˜¯ç”Ÿæˆè€…线程worker一个是消费者线程thread + * + * 在数æ®ä¿¡æ¯ç”Ÿäº§ã€æ¶ˆè´¹çš„过程中，worker负责把数æ®å°†å†™å…¥åˆ°çŽ¯å½¢buffer中，而thread + * 则从环形buffer中读出。 + */ +#include +#include "tc_comm.h" + +/* 一个环形buffer的实现 */ +struct rb +{ + rt_uint16_t read_index, write_index; + rt_uint8_t *buffer_ptr; + rt_uint16_t buffer_size; +}; + +/* 指å‘ä¿¡å·é‡æŽ§åˆ¶å—的指针 */ +static rt_sem_t sem = RT_NULL; +/* 指å‘线程控制å—的指针 */ +static rt_thread_t tid = RT_NULL, worker = RT_NULL; + +/* 环形buffer的内存å—（用数组体现出æ¥ï¼‰ */ +#define BUFFER_SIZE 256 +#define BUFFER_ITEM 32 +static rt_uint8_t working_buffer[BUFFER_SIZE]; +struct rb working_rb; + +/* åˆå§‹åŒ–环形buffer，size指的是buffer的大å°ã€‚注：这里并没对数æ®åœ°å€å¯¹é½åšå¤„ç† */ +static void rb_init(struct rb* rb, rt_uint8_t *pool, rt_uint16_t size) +{ + RT_ASSERT(rb != RT_NULL); + + /* 对读写指针清零*/ + rb->read_index = rb->write_index = 0; + + /* 设置环形buffer的内存数æ®å— */ + rb->buffer_ptr = pool; + rb->buffer_size = size; +} + +/* å‘环形bufferä¸­å†™å…¥æ•°æ® */ +static rt_bool_t rb_put(struct rb* rb, const rt_uint8_t *ptr, rt_uint16_t length) +{ + rt_size_t size; + + /* 判断是å¦æœ‰è¶³å¤Ÿçš„剩余空间 */ + if (rb->read_index > rb->write_index) + size = rb->read_index - rb->write_index; + else + size = rb->buffer_size - rb->write_index + rb->read_index; + + /* 没有多余的空间 */ + if (size < length) return RT_FALSE; + + if (rb->read_index > rb->write_index) + { + /* read_index - write_index å³ä¸ºæ€»çš„空余空间 */ + memcpy(&rb->buffer_ptr[rb->write_index], ptr, length); + rb->write_index += length; + } + else + { + if (rb->buffer_size - rb->write_index > length) + { + /* write_index åŽé¢å‰©ä½™çš„空间有足够的长度 */ + memcpy(&rb->buffer_ptr[rb->write_index], ptr, length); + rb->write_index += length; + } + else + { + /* + * write_index åŽé¢å‰©ä½™çš„空间ä¸å­˜åœ¨è¶³å¤Ÿçš„长度，需è¦æŠŠéƒ¨åˆ†æ•°æ®å¤åˆ¶åˆ° + * å‰é¢çš„剩余空间中 + */ + memcpy(&rb->buffer_ptr[rb->write_index], ptr, + rb->buffer_size - rb->write_index); + memcpy(&rb->buffer_ptr[0], &ptr[rb->buffer_size - rb->write_index], + length - (rb->buffer_size - rb->write_index)); + rb->write_index = length - (rb->buffer_size - rb->write_index); + } + } + + return RT_TRUE; +} + +/* 从环形bufferä¸­è¯»å‡ºæ•°æ® */ +static rt_bool_t rb_get(struct rb* rb, rt_uint8_t *ptr, rt_uint16_t length) +{ + rt_size_t size; + + /* 判断是å¦æœ‰è¶³å¤Ÿçš„æ•°æ® */ + if (rb->read_index > rb->write_index) + size = rb->buffer_size - rb->read_index + rb->write_index; + else + size = rb->write_index - rb->read_index; + + /* æ²¡æœ‰è¶³å¤Ÿçš„æ•°æ® */ + if (size < length) return RT_FALSE; + + if (rb->read_index > rb->write_index) + { + if (rb->buffer_size - rb->read_index > length) + { + /* read_indexçš„æ•°æ®è¶³å¤Ÿå¤šï¼Œç›´æŽ¥å¤åˆ¶ */ + memcpy(ptr, &rb->buffer_ptr[rb->read_index], length); + rb->read_index += length; + } + else + { + /* read_indexçš„æ•°æ®ä¸å¤Ÿï¼Œéœ€è¦åˆ†æ®µå¤åˆ¶ */ + memcpy(ptr, &rb->buffer_ptr[rb->read_index], + rb->buffer_size - rb->read_index); + memcpy(&ptr[rb->buffer_size - rb->read_index], &rb->buffer_ptr[0], + length - rb->buffer_size + rb->read_index); + rb->read_index = length - rb->buffer_size + rb->read_index; + } + } + else + { + /* + * read_indexè¦æ¯”write_indexå°ï¼Œæ€»çš„æ•°æ®é‡å¤Ÿï¼ˆå‰é¢å·²ç»æœ‰æ€»æ•°æ®é‡çš„判 + * 断），直接å¤åˆ¶å‡ºæ•°æ®ã€‚ + */ + memcpy(ptr, &rb->buffer_ptr[rb->read_index], length); + rb->read_index += length; + } + + return RT_TRUE; +} + +/* ç”Ÿäº§è€…çº¿ç¨‹å…¥å£ */ +static void thread_entry(void* parameter) +{ + rt_bool_t result; + rt_uint8_t data_buffer[BUFFER_ITEM + 1]; + + while (1) + { + /* æŒæœ‰ä¿¡å·é‡ */ + rt_sem_take(sem, RT_WAITING_FOREVER); + /* 从环bufferä¸­èŽ·å¾—æ•°æ® */ + result = rb_get(&working_rb, &data_buffer[0], BUFFER_ITEM); + /* 释放信å·é‡ */ + rt_sem_release(sem); + data_buffer[BUFFER_ITEM] = '\0'; + + if (result == RT_TRUE) + { + /* 获å–æ•°æ®æˆåŠŸï¼Œæ‰“å°æ•°æ® */ + rt_kprintf("%s\n", data_buffer); + } + + /* åšä¸€ä¸ª5 OS Tick的休眠 */ + rt_thread_delay(5); + } +} + +/* workerçº¿ç¨‹å…¥å£ */ +static void worker_entry(void* parameter) +{ + rt_bool_t result; + rt_uint32_t index, setchar; + rt_uint8_t data_buffer[BUFFER_ITEM]; + + setchar = 0x21; + while (1) + { + /* æž„é€ æ•°æ® */ + for(index = 0; index < BUFFER_ITEM; index++) + { + data_buffer[index] = setchar; + if (++setchar == 0x7f) + setchar = 0x21; + } + + /* æŒæœ‰ä¿¡å·é‡ */ + rt_sem_take(sem, RT_WAITING_FOREVER); + /* 把数æ®æ”¾åˆ°çŽ¯å½¢buffer中 */ + result = rb_put(&working_rb, &data_buffer[0], BUFFER_ITEM); + /* 释放信å·é‡ */ + rt_sem_release(sem); + + /* 放入æˆåŠŸï¼Œåšä¸€ä¸ª10 OS Tick的休眠 */ + rt_thread_delay(10); + } +} + +int semaphore_buffer_worker_init() +{ + /* åˆå§‹åŒ–ring buffer */ + rb_init(&working_rb, working_buffer, BUFFER_SIZE); + + /* 创建信å·é‡ */ + sem = rt_sem_create("sem", 1, RT_IPC_FLAG_FIFO); + if (sem == RT_NULL) + { + tc_stat(TC_STAT_END | TC_STAT_FAILED); + return 0; + } + + /* 创建线程1 */ + tid = rt_thread_create("thread", + thread_entry, RT_NULL, /* 线程入å£æ˜¯thread_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid != RT_NULL) + rt_thread_startup(tid); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* 创建线程2 */ + worker = rt_thread_create("worker", + worker_entry, RT_NULL, /* 线程入å£æ˜¯worker_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (worker != RT_NULL) + rt_thread_startup(worker); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除信å·é‡ */ + if (sem != RT_NULL) + rt_sem_delete(sem); + + /* 删除线程 */ + if (tid != RT_NULL && tid->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid); + if (worker != RT_NULL && worker->stat != RT_THREAD_CLOSE) + rt_thread_delete(worker); + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_semaphore_buffer_worker() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + semaphore_buffer_worker_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_semaphore_buffer_worker, a buffer worker with semaphore example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + semaphore_buffer_worker_init(); + + return 0; +} +#endif diff --git a/examples/kernel/semaphore_dynamic.c b/examples/kernel/semaphore_dynamic.c index bea4060e381af8db79479f2030109c36ac443293..7f2c2ffd42e785f41f3f311e07a6e65e7f347dcf 100644 --- a/examples/kernel/semaphore_dynamic.c +++ b/examples/kernel/semaphore_dynamic.c @@ -1,128 +1,128 @@ -/* - * 程åºæ¸…å•ï¼šåŠ¨æ€ä¿¡å·é‡ - * - * 这个例å­ä¸­å°†åˆ›å»ºä¸€ä¸ªåŠ¨æ€ä¿¡å·é‡ï¼ˆåˆå§‹å€¼ä¸º0 ）åŠä¸€ä¸ªåŠ¨æ€çº¿ç¨‹ï¼Œåœ¨è¿™ä¸ªåŠ¨æ€çº¿ç¨‹ä¸­ - * 将试图采用超时方å¼åŽ»æŒæœ‰ä¿¡å·é‡ï¼Œåº”该超时返回。然åŽè¿™ä¸ªçº¿ç¨‹é‡Šæ”¾ä¸€æ¬¡ä¿¡å·é‡ï¼Œå¹¶ - * 在åŽé¢ç»§ç»­é‡‡ç”¨æ°¸ä¹…等待方å¼åŽ»æŒæœ‰ä¿¡å·é‡ï¼Œ æˆåŠŸèŽ·å¾—ä¿¡å·é‡åŽè¿”回。 - */ -#include -#include "tc_comm.h" - -/* 指å‘线程控制å—的指针 */ -static rt_thread_t tid = RT_NULL; -/* 指å‘ä¿¡å·é‡çš„指针 */ -static rt_sem_t sem = RT_NULL; -/* çº¿ç¨‹å…¥å£ */ -static void thread_entry(void* parameter) -{ - rt_err_t result; - rt_tick_t tick; - - /* 获得当å‰çš„OS Tick */ - tick = rt_tick_get(); - - /* 试图æŒæœ‰ä¸€ä¸ªä¿¡å·é‡ï¼Œå¦‚æžœ10个OS Tickä¾ç„¶æ²¡æ‹¿åˆ°ï¼Œåˆ™è¶…时返回 */ - result = rt_sem_take(sem, 10); - if (result == -RT_ETIMEOUT) - { - /* 判断是å¦åˆšå¥½è¿‡åŽ»10个OS Tick */ - if (rt_tick_get() - tick != 10) - { - /* 如果失败，则测试失败 */ - tc_done(TC_STAT_FAILED); - rt_sem_delete(sem); - return; - } - rt_kprintf("take semaphore timeout\n"); - } - else - { - /* 因为并没释放信å·é‡ï¼Œåº”该是超时返回，å¦åˆ™æµ‹è¯•å¤±è´¥ */ - tc_done(TC_STAT_FAILED); - rt_sem_delete(sem); - return; - } - - /* 释放一次信å·é‡ */ - rt_sem_release(sem); - - /* 继续æŒæœ‰ä¿¡å·é‡ï¼Œå¹¶æ°¸è¿œç­‰å¾…直到æŒæœ‰åˆ°ä¿¡å·é‡ */ - result = rt_sem_take(sem, RT_WAITING_FOREVER); - if (result != RT_EOK) - { - /* 返回ä¸æ­£ç¡®ï¼Œæµ‹è¯•å¤±è´¥ */ - tc_done(TC_STAT_FAILED); - rt_sem_delete(sem); - return; - } - - /* 测试æˆåŠŸ */ - tc_done(TC_STAT_PASSED); - /* 删除信å·é‡ */ - rt_sem_delete(sem); -} - -int semaphore_dynamic_init() -{ - /* 创建一个信å·é‡ï¼Œåˆå§‹å€¼æ˜¯0 */ - sem = rt_sem_create("sem", 0, RT_IPC_FLAG_FIFO); - if (sem == RT_NULL) - { - tc_stat(TC_STAT_END | TC_STAT_FAILED); - return 0; - } - - /* 创建线程 */ - tid = rt_thread_create("thread", - thread_entry, RT_NULL, /* 线程入å£æ˜¯thread_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid != RT_NULL) - rt_thread_startup(tid); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除线程 */ - if (tid != RT_NULL && tid->stat != RT_THREAD_CLOSE) - { - rt_thread_delete(tid); - - /* 删除信å·é‡ */ - rt_sem_delete(sem); - } - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_semaphore_dynamic() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - semaphore_dynamic_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_semaphore_dynamic, a dynamic semaphore example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - semaphore_dynamic_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šåŠ¨æ€ä¿¡å·é‡ + * + * 这个例å­ä¸­å°†åˆ›å»ºä¸€ä¸ªåŠ¨æ€ä¿¡å·é‡ï¼ˆåˆå§‹å€¼ä¸º0 ）åŠä¸€ä¸ªåŠ¨æ€çº¿ç¨‹ï¼Œåœ¨è¿™ä¸ªåŠ¨æ€çº¿ç¨‹ä¸­ + * 将试图采用超时方å¼åŽ»æŒæœ‰ä¿¡å·é‡ï¼Œåº”该超时返回。然åŽè¿™ä¸ªçº¿ç¨‹é‡Šæ”¾ä¸€æ¬¡ä¿¡å·é‡ï¼Œå¹¶ + * 在åŽé¢ç»§ç»­é‡‡ç”¨æ°¸ä¹…等待方å¼åŽ»æŒæœ‰ä¿¡å·é‡ï¼Œ æˆåŠŸèŽ·å¾—ä¿¡å·é‡åŽè¿”回。 + */ +#include +#include "tc_comm.h" + +/* 指å‘线程控制å—的指针 */ +static rt_thread_t tid = RT_NULL; +/* 指å‘ä¿¡å·é‡çš„指针 */ +static rt_sem_t sem = RT_NULL; +/* çº¿ç¨‹å…¥å£ */ +static void thread_entry(void* parameter) +{ + rt_err_t result; + rt_tick_t tick; + + /* 获得当å‰çš„OS Tick */ + tick = rt_tick_get(); + + /* 试图æŒæœ‰ä¸€ä¸ªä¿¡å·é‡ï¼Œå¦‚æžœ10个OS Tickä¾ç„¶æ²¡æ‹¿åˆ°ï¼Œåˆ™è¶…时返回 */ + result = rt_sem_take(sem, 10); + if (result == -RT_ETIMEOUT) + { + /* 判断是å¦åˆšå¥½è¿‡åŽ»10个OS Tick */ + if (rt_tick_get() - tick != 10) + { + /* 如果失败，则测试失败 */ + tc_done(TC_STAT_FAILED); + rt_sem_delete(sem); + return; + } + rt_kprintf("take semaphore timeout\n"); + } + else + { + /* 因为并没释放信å·é‡ï¼Œåº”该是超时返回，å¦åˆ™æµ‹è¯•å¤±è´¥ */ + tc_done(TC_STAT_FAILED); + rt_sem_delete(sem); + return; + } + + /* 释放一次信å·é‡ */ + rt_sem_release(sem); + + /* 继续æŒæœ‰ä¿¡å·é‡ï¼Œå¹¶æ°¸è¿œç­‰å¾…直到æŒæœ‰åˆ°ä¿¡å·é‡ */ + result = rt_sem_take(sem, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + /* 返回ä¸æ­£ç¡®ï¼Œæµ‹è¯•å¤±è´¥ */ + tc_done(TC_STAT_FAILED); + rt_sem_delete(sem); + return; + } + + /* 测试æˆåŠŸ */ + tc_done(TC_STAT_PASSED); + /* 删除信å·é‡ */ + rt_sem_delete(sem); +} + +int semaphore_dynamic_init() +{ + /* 创建一个信å·é‡ï¼Œåˆå§‹å€¼æ˜¯0 */ + sem = rt_sem_create("sem", 0, RT_IPC_FLAG_FIFO); + if (sem == RT_NULL) + { + tc_stat(TC_STAT_END | TC_STAT_FAILED); + return 0; + } + + /* 创建线程 */ + tid = rt_thread_create("thread", + thread_entry, RT_NULL, /* 线程入å£æ˜¯thread_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid != RT_NULL) + rt_thread_startup(tid); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除线程 */ + if (tid != RT_NULL && tid->stat != RT_THREAD_CLOSE) + { + rt_thread_delete(tid); + + /* 删除信å·é‡ */ + rt_sem_delete(sem); + } + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_semaphore_dynamic() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + semaphore_dynamic_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_semaphore_dynamic, a dynamic semaphore example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + semaphore_dynamic_init(); + + return 0; +} +#endif diff --git a/examples/kernel/semaphore_priority.c b/examples/kernel/semaphore_priority.c index 4ee8d889e3924bf6dc5e8cec7e704cf4499bec1b..c106a25d5e010d55624acbcbc5a8f42f996ae0fb 100644 --- a/examples/kernel/semaphore_priority.c +++ b/examples/kernel/semaphore_priority.c @@ -1,128 +1,128 @@ -#include -#include "tc_comm.h" - -static rt_sem_t sem; -static rt_uint8_t t1_count, t2_count; -static rt_thread_t t1, t2, worker; -static void thread1_entry(void* parameter) -{ - rt_err_t result; - - while (1) - { - result = rt_sem_take(sem, RT_WAITING_FOREVER); - if (result != RT_EOK) - { - tc_done(TC_STAT_FAILED); - return; - } - - t1_count ++; - rt_kprintf("thread1: got semaphore, count: %d\n", t1_count); - } -} - -static void thread2_entry(void* parameter) -{ - rt_err_t result; - - while (1) - { - result = rt_sem_take(sem, RT_WAITING_FOREVER); - if (result != RT_EOK) - { - tc_done(TC_STAT_FAILED); - return; - } - - t2_count ++; - rt_kprintf("thread2: got semaphore, count: %d\n", t2_count); - } -} - -static void worker_thread_entry(void* parameter) -{ - rt_thread_delay(10); - - while (1) - { - rt_sem_release(sem); - rt_thread_delay(5); - } -} - -int semaphore_priority_init() -{ - sem = rt_sem_create("sem", 0, RT_IPC_FLAG_PRIO); - if (sem == RT_NULL) - { - tc_stat(TC_STAT_END | TC_STAT_FAILED); - return 0; - } - - t1_count = t2_count = 0; - - t1 = rt_thread_create("t1", - thread1_entry, RT_NULL, - THREAD_STACK_SIZE, THREAD_PRIORITY + 1, THREAD_TIMESLICE); - if (t1 != RT_NULL) - rt_thread_startup(t1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - t2 = rt_thread_create("t2", - thread2_entry, RT_NULL, - THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); - if (t2 != RT_NULL) - rt_thread_startup(t2); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - worker = rt_thread_create("worker", - worker_thread_entry, RT_NULL, - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (worker != RT_NULL) - rt_thread_startup(worker); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* lock scheduler */ - rt_enter_critical(); - - /* delete t1, t2 and worker thread */ - rt_thread_delete(t1); - rt_thread_delete(t2); - rt_thread_delete(worker); - - if (t1_count > t2_count) - tc_done(TC_STAT_FAILED); - else - tc_done(TC_STAT_PASSED); - - /* unlock scheduler */ - rt_exit_critical(); -} - -int _tc_semaphore_priority() -{ - /* set tc cleanup */ - tc_cleanup(_tc_cleanup); - semaphore_priority_init(); - - return 50; -} -FINSH_FUNCTION_EXPORT(_tc_semaphore_priority, a priority semaphore test); -#else -int rt_application_init() -{ - semaphore_priority_init(); - - return 0; -} -#endif +#include +#include "tc_comm.h" + +static rt_sem_t sem; +static rt_uint8_t t1_count, t2_count; +static rt_thread_t t1, t2, worker; +static void thread1_entry(void* parameter) +{ + rt_err_t result; + + while (1) + { + result = rt_sem_take(sem, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + tc_done(TC_STAT_FAILED); + return; + } + + t1_count ++; + rt_kprintf("thread1: got semaphore, count: %d\n", t1_count); + } +} + +static void thread2_entry(void* parameter) +{ + rt_err_t result; + + while (1) + { + result = rt_sem_take(sem, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + tc_done(TC_STAT_FAILED); + return; + } + + t2_count ++; + rt_kprintf("thread2: got semaphore, count: %d\n", t2_count); + } +} + +static void worker_thread_entry(void* parameter) +{ + rt_thread_delay(10); + + while (1) + { + rt_sem_release(sem); + rt_thread_delay(5); + } +} + +int semaphore_priority_init() +{ + sem = rt_sem_create("sem", 0, RT_IPC_FLAG_PRIO); + if (sem == RT_NULL) + { + tc_stat(TC_STAT_END | TC_STAT_FAILED); + return 0; + } + + t1_count = t2_count = 0; + + t1 = rt_thread_create("t1", + thread1_entry, RT_NULL, + THREAD_STACK_SIZE, THREAD_PRIORITY + 1, THREAD_TIMESLICE); + if (t1 != RT_NULL) + rt_thread_startup(t1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + t2 = rt_thread_create("t2", + thread2_entry, RT_NULL, + THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); + if (t2 != RT_NULL) + rt_thread_startup(t2); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + worker = rt_thread_create("worker", + worker_thread_entry, RT_NULL, + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (worker != RT_NULL) + rt_thread_startup(worker); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* lock scheduler */ + rt_enter_critical(); + + /* delete t1, t2 and worker thread */ + rt_thread_delete(t1); + rt_thread_delete(t2); + rt_thread_delete(worker); + + if (t1_count > t2_count) + tc_done(TC_STAT_FAILED); + else + tc_done(TC_STAT_PASSED); + + /* unlock scheduler */ + rt_exit_critical(); +} + +int _tc_semaphore_priority() +{ + /* set tc cleanup */ + tc_cleanup(_tc_cleanup); + semaphore_priority_init(); + + return 50; +} +FINSH_FUNCTION_EXPORT(_tc_semaphore_priority, a priority semaphore test); +#else +int rt_application_init() +{ + semaphore_priority_init(); + + return 0; +} +#endif diff --git a/examples/kernel/semaphore_producer_consumer.c b/examples/kernel/semaphore_producer_consumer.c index f85acc3b70bccb61fbc22c3713e6bb6d7905a8e1..ec0bf2234c93b846c81892aa2cb31922d0c1cee7 100644 --- a/examples/kernel/semaphore_producer_consumer.c +++ b/examples/kernel/semaphore_producer_consumer.c @@ -1,154 +1,154 @@ -/* - * 程åºæ¸…å•ï¼šç”Ÿäº§è€…æ¶ˆè´¹è€…ä¾‹å­ - * - * 这个例å­ä¸­å°†åˆ›å»ºä¸¤ä¸ªçº¿ç¨‹ç”¨äºŽå®žçŽ°ç”Ÿäº§è€…消费者问题 - */ -#include -#include "tc_comm.h" - -/* 定义最大5个元素能够被产生 */ -#define MAXSEM 5 - -/* 用于放置生产的整数数组 */ -rt_uint32_t array[MAXSEM]; -/* 指å‘生产者ã€æ¶ˆè´¹è€…在array数组中的读写ä½ç½® */ -static rt_uint32_t set, get; - -/* 指å‘线程控制å—的指针 */ -static rt_thread_t producer_tid = RT_NULL; -static rt_thread_t consumer_tid = RT_NULL; - -struct rt_semaphore sem_lock; -struct rt_semaphore sem_empty, sem_full; - -/* 生æˆè€…çº¿ç¨‹å…¥å£ */ -void producer_thread_entry(void* parameter) -{ - int cnt = 0; - - /* è¿è¡Œ100次 */ - while( cnt < 100) - { - /* 获å–ä¸€ä¸ªç©ºä½ */ - rt_sem_take(&sem_empty, RT_WAITING_FOREVER); - - /* 修改arrayå†…å®¹ï¼Œä¸Šé” */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - array[set%MAXSEM] = cnt + 1; - rt_kprintf("the producer generates a number: %d\n", array[set%MAXSEM]); - set++; - rt_sem_release(&sem_lock); - - /* å‘å¸ƒä¸€ä¸ªæ»¡ä½ */ - rt_sem_release(&sem_full); - cnt++; - - /* æš‚åœä¸€æ®µæ—¶é—´ */ - rt_thread_delay(50); - } - - rt_kprintf("the producer exit!\n"); -} - -/* æ¶ˆè´¹è€…çº¿ç¨‹å…¥å£ */ -void consumer_thread_entry(void* parameter) -{ - rt_uint32_t no; - rt_uint32_t sum; - - /* 第n个线程，由入å£å‚æ•°ä¼ è¿›æ¥ */ - no = (rt_uint32_t)parameter; - - while(1) - { - /* 获å–ä¸€ä¸ªæ»¡ä½ */ - rt_sem_take(&sem_full, RT_WAITING_FOREVER); - - /* 临界区，上é”进行æ“作 */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - sum += array[get%MAXSEM]; - rt_kprintf("the consumer[%d] get a number: %d\n", no, array[get%MAXSEM] ); - get++; - rt_sem_release(&sem_lock); - - /* é‡Šæ”¾ä¸€ä¸ªç©ºä½ */ - rt_sem_release(&sem_empty); - - /* 生产者生产到100个数目，åœæ­¢ï¼Œæ¶ˆè´¹è€…线程相应åœæ­¢ */ - if (get == 100) break; - - /* æš‚åœä¸€å°ä¼šæ—¶é—´ */ - rt_thread_delay(10); - } - - rt_kprintf("the consumer[%d] sum is %d \n ", no, sum); - rt_kprintf("the consumer[%d] exit!\n"); -} - -int semaphore_producer_consumer_init() -{ - /* åˆå§‹åŒ–3个信å·é‡ */ - rt_sem_init(&sem_lock , "lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&sem_empty, "empty", MAXSEM, RT_IPC_FLAG_FIFO); - rt_sem_init(&sem_full , "full", 0, RT_IPC_FLAG_FIFO); - - /* 创建线程1 */ - producer_tid = rt_thread_create("producer", - producer_thread_entry, RT_NULL, /* 线程入å£æ˜¯producer_thread_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); - if (producer_tid != RT_NULL) - rt_thread_startup(producer_tid); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* 创建线程2 */ - consumer_tid = rt_thread_create("consumer", - consumer_thread_entry, RT_NULL, /* 线程入å£æ˜¯consumer_thread_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY + 1, THREAD_TIMESLICE); - if (consumer_tid != RT_NULL) - rt_thread_startup(consumer_tid); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除线程 */ - if (producer_tid != RT_NULL && producer_tid->stat != RT_THREAD_CLOSE) - rt_thread_delete(producer_tid); - if (consumer_tid != RT_NULL && consumer_tid->stat != RT_THREAD_CLOSE) - rt_thread_delete(consumer_tid); - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_semaphore_producer_consumer() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - semaphore_producer_consumer_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_semaphore_producer_consumer, producer and consumer example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - semaphore_producer_consumer_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šç”Ÿäº§è€…æ¶ˆè´¹è€…ä¾‹å­ + * + * 这个例å­ä¸­å°†åˆ›å»ºä¸¤ä¸ªçº¿ç¨‹ç”¨äºŽå®žçŽ°ç”Ÿäº§è€…消费者问题 + */ +#include +#include "tc_comm.h" + +/* 定义最大5个元素能够被产生 */ +#define MAXSEM 5 + +/* 用于放置生产的整数数组 */ +rt_uint32_t array[MAXSEM]; +/* 指å‘生产者ã€æ¶ˆè´¹è€…在array数组中的读写ä½ç½® */ +static rt_uint32_t set, get; + +/* 指å‘线程控制å—的指针 */ +static rt_thread_t producer_tid = RT_NULL; +static rt_thread_t consumer_tid = RT_NULL; + +struct rt_semaphore sem_lock; +struct rt_semaphore sem_empty, sem_full; + +/* 生æˆè€…çº¿ç¨‹å…¥å£ */ +void producer_thread_entry(void* parameter) +{ + int cnt = 0; + + /* è¿è¡Œ100次 */ + while( cnt < 100) + { + /* 获å–ä¸€ä¸ªç©ºä½ */ + rt_sem_take(&sem_empty, RT_WAITING_FOREVER); + + /* 修改arrayå†…å®¹ï¼Œä¸Šé” */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + array[set%MAXSEM] = cnt + 1; + rt_kprintf("the producer generates a number: %d\n", array[set%MAXSEM]); + set++; + rt_sem_release(&sem_lock); + + /* å‘å¸ƒä¸€ä¸ªæ»¡ä½ */ + rt_sem_release(&sem_full); + cnt++; + + /* æš‚åœä¸€æ®µæ—¶é—´ */ + rt_thread_delay(50); + } + + rt_kprintf("the producer exit!\n"); +} + +/* æ¶ˆè´¹è€…çº¿ç¨‹å…¥å£ */ +void consumer_thread_entry(void* parameter) +{ + rt_uint32_t no; + rt_uint32_t sum; + + /* 第n个线程，由入å£å‚æ•°ä¼ è¿›æ¥ */ + no = (rt_uint32_t)parameter; + + while(1) + { + /* 获å–ä¸€ä¸ªæ»¡ä½ */ + rt_sem_take(&sem_full, RT_WAITING_FOREVER); + + /* 临界区，上é”进行æ“作 */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + sum += array[get%MAXSEM]; + rt_kprintf("the consumer[%d] get a number: %d\n", no, array[get%MAXSEM] ); + get++; + rt_sem_release(&sem_lock); + + /* é‡Šæ”¾ä¸€ä¸ªç©ºä½ */ + rt_sem_release(&sem_empty); + + /* 生产者生产到100个数目，åœæ­¢ï¼Œæ¶ˆè´¹è€…线程相应åœæ­¢ */ + if (get == 100) break; + + /* æš‚åœä¸€å°ä¼šæ—¶é—´ */ + rt_thread_delay(10); + } + + rt_kprintf("the consumer[%d] sum is %d \n ", no, sum); + rt_kprintf("the consumer[%d] exit!\n"); +} + +int semaphore_producer_consumer_init() +{ + /* åˆå§‹åŒ–3个信å·é‡ */ + rt_sem_init(&sem_lock , "lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_empty, "empty", MAXSEM, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_full , "full", 0, RT_IPC_FLAG_FIFO); + + /* 创建线程1 */ + producer_tid = rt_thread_create("producer", + producer_thread_entry, RT_NULL, /* 线程入å£æ˜¯producer_thread_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); + if (producer_tid != RT_NULL) + rt_thread_startup(producer_tid); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* 创建线程2 */ + consumer_tid = rt_thread_create("consumer", + consumer_thread_entry, RT_NULL, /* 线程入å£æ˜¯consumer_thread_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY + 1, THREAD_TIMESLICE); + if (consumer_tid != RT_NULL) + rt_thread_startup(consumer_tid); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除线程 */ + if (producer_tid != RT_NULL && producer_tid->stat != RT_THREAD_CLOSE) + rt_thread_delete(producer_tid); + if (consumer_tid != RT_NULL && consumer_tid->stat != RT_THREAD_CLOSE) + rt_thread_delete(consumer_tid); + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_semaphore_producer_consumer() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + semaphore_producer_consumer_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_semaphore_producer_consumer, producer and consumer example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + semaphore_producer_consumer_init(); + + return 0; +} +#endif diff --git a/examples/kernel/semaphore_static.c b/examples/kernel/semaphore_static.c index 717ff25c57445baf5afd977de26a3e55fb53becf..167b5e905573d2f3bbbbfb1cddd1b95f94ca11cb 100644 --- a/examples/kernel/semaphore_static.c +++ b/examples/kernel/semaphore_static.c @@ -1,132 +1,132 @@ -/* - * 程åºæ¸…å•ï¼šé™æ€ä¿¡å·é‡ - * - * 这个例å­ä¸­å°†åˆ›å»ºä¸€ä¸ªé™æ€ä¿¡å·é‡ï¼ˆåˆå§‹å€¼ä¸º0 ）åŠä¸€ä¸ªé™æ€çº¿ç¨‹ï¼Œåœ¨è¿™ä¸ªé™æ€çº¿ç¨‹ä¸­ - * 将试图采用超时方å¼åŽ»æŒæœ‰ä¿¡å·é‡ï¼Œåº”该超时返回。然åŽè¿™ä¸ªçº¿ç¨‹é‡Šæ”¾ä¸€æ¬¡ä¿¡å·é‡ï¼Œå¹¶ - * 在åŽé¢ç»§ç»­é‡‡ç”¨æ°¸ä¹…等待方å¼åŽ»æŒæœ‰ä¿¡å·é‡ï¼Œ æˆåŠŸèŽ·å¾—ä¿¡å·é‡åŽè¿”回。 - */ -#include -#include "tc_comm.h" - -/* 线程控制å—åŠæ ˆ */ -static struct rt_thread thread; -static rt_uint8_t thread_stack[THREAD_STACK_SIZE]; -/* ä¿¡å·é‡æŽ§åˆ¶å— */ -static struct rt_semaphore sem; - -/* çº¿ç¨‹å…¥å£ */ -static void thread_entry(void* parameter) -{ - rt_err_t result; - rt_tick_t tick; - - /* 获得当å‰çš„OS Tick */ - tick = rt_tick_get(); - - /* 试图æŒæœ‰ä¿¡å·é‡ï¼Œæœ€å¤§ç­‰å¾…10个OS TickåŽè¿”回 */ - result = rt_sem_take(&sem, 10); - if (result == -RT_ETIMEOUT) - { - /* 超时åŽåˆ¤æ–­æ˜¯å¦åˆšå¥½æ˜¯10个OS Tick */ - if (rt_tick_get() - tick != 10) - { - tc_done(TC_STAT_FAILED); - rt_sem_detach(&sem); - return; - } - rt_kprintf("take semaphore timeout\n"); - } - else - { - /* 因为没有其他地方是å¦ä¿¡å·é‡ï¼Œæ‰€ä»¥ä¸åº”该æˆåŠŸæŒæœ‰ä¿¡å·é‡ï¼Œå¦åˆ™æµ‹è¯•å¤±è´¥ */ - tc_done(TC_STAT_FAILED); - rt_sem_detach(&sem); - return; - } - - /* 释放一次信å·é‡ */ - rt_sem_release(&sem); - - /* 永久等待方å¼æŒæœ‰ä¿¡å·é‡ */ - result = rt_sem_take(&sem, RT_WAITING_FOREVER); - if (result != RT_EOK) - { - /* ä¸æˆåŠŸåˆ™æµ‹è¯•å¤±è´¥ */ - tc_done(TC_STAT_FAILED); - rt_sem_detach(&sem); - return; - } - - /* 测试通过 */ - tc_done(TC_STAT_PASSED); - /* 脱离信å·é‡å¯¹è±¡ */ - rt_sem_detach(&sem); -} - -int semaphore_static_init() -{ - rt_err_t result; - - /* åˆå§‹åŒ–ä¿¡å·é‡ï¼Œåˆå§‹å€¼æ˜¯0 */ - result = rt_sem_init(&sem, "sem", 0, RT_IPC_FLAG_FIFO); - if (result != RT_EOK) - { - tc_stat(TC_STAT_END | TC_STAT_FAILED); - return 0; - } - - /* åˆå§‹åŒ–线程1 */ - result = rt_thread_init(&thread, "thread", /* 线程å：thread */ - thread_entry, RT_NULL, /* 线程的入å£æ˜¯thread_entry，入å£å‚数是RT_NULL*/ - &thread_stack[0], sizeof(thread_stack), /* 线程栈是thread_stack */ - THREAD_PRIORITY, 10); - if (result == RT_EOK) /* 如果返回正确，å¯åŠ¨çº¿ç¨‹1 */ - rt_thread_startup(&thread); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 执行线程脱离 */ - if (thread.stat != RT_THREAD_CLOSE) - { - rt_thread_detach(&thread); - - /* 执行信å·é‡å¯¹è±¡è„±ç¦» */ - rt_sem_detach(&sem); - } - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_semaphore_static() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - semaphore_static_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_semaphore_static, a static semaphore example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - thread_static_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šé™æ€ä¿¡å·é‡ + * + * 这个例å­ä¸­å°†åˆ›å»ºä¸€ä¸ªé™æ€ä¿¡å·é‡ï¼ˆåˆå§‹å€¼ä¸º0 ）åŠä¸€ä¸ªé™æ€çº¿ç¨‹ï¼Œåœ¨è¿™ä¸ªé™æ€çº¿ç¨‹ä¸­ + * 将试图采用超时方å¼åŽ»æŒæœ‰ä¿¡å·é‡ï¼Œåº”该超时返回。然åŽè¿™ä¸ªçº¿ç¨‹é‡Šæ”¾ä¸€æ¬¡ä¿¡å·é‡ï¼Œå¹¶ + * 在åŽé¢ç»§ç»­é‡‡ç”¨æ°¸ä¹…等待方å¼åŽ»æŒæœ‰ä¿¡å·é‡ï¼Œ æˆåŠŸèŽ·å¾—ä¿¡å·é‡åŽè¿”回。 + */ +#include +#include "tc_comm.h" + +/* 线程控制å—åŠæ ˆ */ +static struct rt_thread thread; +static rt_uint8_t thread_stack[THREAD_STACK_SIZE]; +/* ä¿¡å·é‡æŽ§åˆ¶å— */ +static struct rt_semaphore sem; + +/* çº¿ç¨‹å…¥å£ */ +static void thread_entry(void* parameter) +{ + rt_err_t result; + rt_tick_t tick; + + /* 获得当å‰çš„OS Tick */ + tick = rt_tick_get(); + + /* 试图æŒæœ‰ä¿¡å·é‡ï¼Œæœ€å¤§ç­‰å¾…10个OS TickåŽè¿”回 */ + result = rt_sem_take(&sem, 10); + if (result == -RT_ETIMEOUT) + { + /* 超时åŽåˆ¤æ–­æ˜¯å¦åˆšå¥½æ˜¯10个OS Tick */ + if (rt_tick_get() - tick != 10) + { + tc_done(TC_STAT_FAILED); + rt_sem_detach(&sem); + return; + } + rt_kprintf("take semaphore timeout\n"); + } + else + { + /* 因为没有其他地方是å¦ä¿¡å·é‡ï¼Œæ‰€ä»¥ä¸åº”该æˆåŠŸæŒæœ‰ä¿¡å·é‡ï¼Œå¦åˆ™æµ‹è¯•å¤±è´¥ */ + tc_done(TC_STAT_FAILED); + rt_sem_detach(&sem); + return; + } + + /* 释放一次信å·é‡ */ + rt_sem_release(&sem); + + /* 永久等待方å¼æŒæœ‰ä¿¡å·é‡ */ + result = rt_sem_take(&sem, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + /* ä¸æˆåŠŸåˆ™æµ‹è¯•å¤±è´¥ */ + tc_done(TC_STAT_FAILED); + rt_sem_detach(&sem); + return; + } + + /* 测试通过 */ + tc_done(TC_STAT_PASSED); + /* 脱离信å·é‡å¯¹è±¡ */ + rt_sem_detach(&sem); +} + +int semaphore_static_init() +{ + rt_err_t result; + + /* åˆå§‹åŒ–ä¿¡å·é‡ï¼Œåˆå§‹å€¼æ˜¯0 */ + result = rt_sem_init(&sem, "sem", 0, RT_IPC_FLAG_FIFO); + if (result != RT_EOK) + { + tc_stat(TC_STAT_END | TC_STAT_FAILED); + return 0; + } + + /* åˆå§‹åŒ–线程1 */ + result = rt_thread_init(&thread, "thread", /* 线程å：thread */ + thread_entry, RT_NULL, /* 线程的入å£æ˜¯thread_entry，入å£å‚数是RT_NULL*/ + &thread_stack[0], sizeof(thread_stack), /* 线程栈是thread_stack */ + THREAD_PRIORITY, 10); + if (result == RT_EOK) /* 如果返回正确，å¯åŠ¨çº¿ç¨‹1 */ + rt_thread_startup(&thread); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 执行线程脱离 */ + if (thread.stat != RT_THREAD_CLOSE) + { + rt_thread_detach(&thread); + + /* 执行信å·é‡å¯¹è±¡è„±ç¦» */ + rt_sem_detach(&sem); + } + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_semaphore_static() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + semaphore_static_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_semaphore_static, a static semaphore example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + thread_static_init(); + + return 0; +} +#endif diff --git a/examples/kernel/tc_comm.c b/examples/kernel/tc_comm.c index 1ec48f53984b03ce20bb2904f4110edef1138874..60d843171fb12fe57371f4df2d1848d7bfab5bfc 100644 --- a/examples/kernel/tc_comm.c +++ b/examples/kernel/tc_comm.c @@ -1,176 +1,176 @@ -#include "tc_comm.h" -#ifdef RT_USING_FINSH -#include -#endif - -#ifdef RT_USING_TC -#define TC_PRIORITY 25 -#define TC_STACK_SIZE 0x400 - -static rt_uint8_t _tc_stat; -static struct rt_semaphore _tc_sem; -static struct rt_thread _tc_thread; -static rt_uint8_t _tc_stack[TC_STACK_SIZE]; -static char _tc_prefix[64]; -static const char* _tc_current; -static void (*_tc_cleanup)(void) = RT_NULL; - -static rt_uint32_t _tc_scale = 1; -FINSH_VAR_EXPORT(_tc_scale, finsh_type_int, the testcase timer timeout scale) - -void tc_thread_entry(void* parameter) -{ - struct finsh_syscall* index; - - /* create tc semaphore */ - rt_sem_init(&_tc_sem, "tc", 0, RT_IPC_FLAG_FIFO); - - while (_tc_stat & TC_STAT_RUNNING) - { - for (index = _syscall_table_begin; index < _syscall_table_end; FINSH_NEXT_SYSCALL(index)) - { - /* search testcase */ - if (rt_strstr(index->name, _tc_prefix) == index->name) - { - long tick; - - _tc_current = index->name + 4; - rt_kprintf("Run TestCase: %s\n", _tc_current); - _tc_stat = TC_STAT_PASSED | TC_STAT_RUNNING; - tick = index->func(); - if (tick > 0) - { - rt_sem_take(&_tc_sem, tick * _tc_scale); - - if (_tc_cleanup != RT_NULL) - { - /* perform testcase cleanup */ - _tc_cleanup(); - _tc_cleanup = RT_NULL; - } - - rt_sem_trytake(&_tc_sem);/* by nl1031 */ - - if (_tc_stat & TC_STAT_FAILED) - rt_kprintf("TestCase[%s] failed\n", _tc_current); - else - rt_kprintf("TestCase[%s] passed\n", _tc_current); - } - else - { - if (_tc_cleanup != RT_NULL) - { - /* perform testcase cleanup */ - _tc_cleanup(); - _tc_cleanup = RT_NULL; - } - } - } - } - } - - rt_kprintf("RT-Thread TestCase Running Done!\n"); - /* detach tc semaphore */ - rt_sem_detach(&_tc_sem); -} - -void tc_stop() -{ - _tc_stat &= ~TC_STAT_RUNNING; - - rt_thread_delay(RT_TICK_PER_SECOND/2); - if (_tc_thread.stat != RT_THREAD_INIT) - { - /* lock scheduler */ - rt_enter_critical(); - - /* detach old tc thread */ - rt_thread_detach(&_tc_thread); - rt_sem_detach(&_tc_sem); - - /* unlock scheduler */ - rt_exit_critical(); - } - rt_thread_delay(RT_TICK_PER_SECOND/2); -} -FINSH_FUNCTION_EXPORT(tc_stop, stop testcase thread); - -void tc_done(rt_uint8_t stat) -{ - _tc_stat |= stat; - _tc_stat &= ~TC_STAT_RUNNING; - - /* release semaphore */ - rt_sem_release(&_tc_sem); -} - -void tc_stat(rt_uint8_t stat) -{ - if (stat & TC_STAT_FAILED) - { - rt_kprintf("TestCases[%s] failed\n", _tc_current); - } - _tc_stat |= stat; -} - -void tc_cleanup(void (*cleanup)()) -{ - _tc_cleanup = cleanup; -} - -void tc_start(const char* tc_prefix) -{ - rt_err_t result; - - /* tesecase prefix is null */ - if (tc_prefix == RT_NULL) - { - rt_kprintf("TestCase Usage: tc_start(prefix)\n\n"); - rt_kprintf("list_tc() can list all testcases.\n"); - return ; - } - - /* init tc thread */ - if (_tc_stat & TC_STAT_RUNNING) - { - /* stop old tc thread */ - tc_stop(); - } - - rt_memset(_tc_prefix, 0, sizeof(_tc_prefix)); - rt_snprintf(_tc_prefix, sizeof(_tc_prefix), "_tc_%s", tc_prefix); - - result = rt_thread_init(&_tc_thread, "tc", - tc_thread_entry, RT_NULL, - &_tc_stack[0], sizeof(_tc_stack), - TC_PRIORITY - 3, 5); - - /* set tc stat */ - _tc_stat = TC_STAT_RUNNING | TC_STAT_FAILED; - - if (result == RT_EOK) - rt_thread_startup(&_tc_thread); -} -FINSH_FUNCTION_EXPORT(tc_start, start testcase with testcase prefix or name); - -void list_tc() -{ - struct finsh_syscall* index; - - rt_kprintf("TestCases List:\n"); - for (index = _syscall_table_begin; index < _syscall_table_end; FINSH_NEXT_SYSCALL(index)) - { - /* search testcase */ - if (rt_strstr(index->name, "_tc_") == index->name) - { -#ifdef FINSH_USING_DESCRIPTION - rt_kprintf("%-16s -- %s\n", index->name + 4, index->desc); -#else - rt_kprintf("%s\n", index->name + 4); -#endif - } - } -} -FINSH_FUNCTION_EXPORT(list_tc, list all testcases); -#endif - +#include "tc_comm.h" +#ifdef RT_USING_FINSH +#include +#endif + +#ifdef RT_USING_TC +#define TC_PRIORITY 25 +#define TC_STACK_SIZE 0x400 + +static rt_uint8_t _tc_stat; +static struct rt_semaphore _tc_sem; +static struct rt_thread _tc_thread; +static rt_uint8_t _tc_stack[TC_STACK_SIZE]; +static char _tc_prefix[64]; +static const char* _tc_current; +static void (*_tc_cleanup)(void) = RT_NULL; + +static rt_uint32_t _tc_scale = 1; +FINSH_VAR_EXPORT(_tc_scale, finsh_type_int, the testcase timer timeout scale) + +void tc_thread_entry(void* parameter) +{ + struct finsh_syscall* index; + + /* create tc semaphore */ + rt_sem_init(&_tc_sem, "tc", 0, RT_IPC_FLAG_FIFO); + + while (_tc_stat & TC_STAT_RUNNING) + { + for (index = _syscall_table_begin; index < _syscall_table_end; FINSH_NEXT_SYSCALL(index)) + { + /* search testcase */ + if (rt_strstr(index->name, _tc_prefix) == index->name) + { + long tick; + + _tc_current = index->name + 4; + rt_kprintf("Run TestCase: %s\n", _tc_current); + _tc_stat = TC_STAT_PASSED | TC_STAT_RUNNING; + tick = index->func(); + if (tick > 0) + { + rt_sem_take(&_tc_sem, tick * _tc_scale); + + if (_tc_cleanup != RT_NULL) + { + /* perform testcase cleanup */ + _tc_cleanup(); + _tc_cleanup = RT_NULL; + } + + rt_sem_trytake(&_tc_sem);/* by nl1031 */ + + if (_tc_stat & TC_STAT_FAILED) + rt_kprintf("TestCase[%s] failed\n", _tc_current); + else + rt_kprintf("TestCase[%s] passed\n", _tc_current); + } + else + { + if (_tc_cleanup != RT_NULL) + { + /* perform testcase cleanup */ + _tc_cleanup(); + _tc_cleanup = RT_NULL; + } + } + } + } + } + + rt_kprintf("RT-Thread TestCase Running Done!\n"); + /* detach tc semaphore */ + rt_sem_detach(&_tc_sem); +} + +void tc_stop() +{ + _tc_stat &= ~TC_STAT_RUNNING; + + rt_thread_delay(RT_TICK_PER_SECOND/2); + if (_tc_thread.stat != RT_THREAD_INIT) + { + /* lock scheduler */ + rt_enter_critical(); + + /* detach old tc thread */ + rt_thread_detach(&_tc_thread); + rt_sem_detach(&_tc_sem); + + /* unlock scheduler */ + rt_exit_critical(); + } + rt_thread_delay(RT_TICK_PER_SECOND/2); +} +FINSH_FUNCTION_EXPORT(tc_stop, stop testcase thread); + +void tc_done(rt_uint8_t stat) +{ + _tc_stat |= stat; + _tc_stat &= ~TC_STAT_RUNNING; + + /* release semaphore */ + rt_sem_release(&_tc_sem); +} + +void tc_stat(rt_uint8_t stat) +{ + if (stat & TC_STAT_FAILED) + { + rt_kprintf("TestCases[%s] failed\n", _tc_current); + } + _tc_stat |= stat; +} + +void tc_cleanup(void (*cleanup)()) +{ + _tc_cleanup = cleanup; +} + +void tc_start(const char* tc_prefix) +{ + rt_err_t result; + + /* tesecase prefix is null */ + if (tc_prefix == RT_NULL) + { + rt_kprintf("TestCase Usage: tc_start(prefix)\n\n"); + rt_kprintf("list_tc() can list all testcases.\n"); + return ; + } + + /* init tc thread */ + if (_tc_stat & TC_STAT_RUNNING) + { + /* stop old tc thread */ + tc_stop(); + } + + rt_memset(_tc_prefix, 0, sizeof(_tc_prefix)); + rt_snprintf(_tc_prefix, sizeof(_tc_prefix), "_tc_%s", tc_prefix); + + result = rt_thread_init(&_tc_thread, "tc", + tc_thread_entry, RT_NULL, + &_tc_stack[0], sizeof(_tc_stack), + TC_PRIORITY - 3, 5); + + /* set tc stat */ + _tc_stat = TC_STAT_RUNNING | TC_STAT_FAILED; + + if (result == RT_EOK) + rt_thread_startup(&_tc_thread); +} +FINSH_FUNCTION_EXPORT(tc_start, start testcase with testcase prefix or name); + +void list_tc() +{ + struct finsh_syscall* index; + + rt_kprintf("TestCases List:\n"); + for (index = _syscall_table_begin; index < _syscall_table_end; FINSH_NEXT_SYSCALL(index)) + { + /* search testcase */ + if (rt_strstr(index->name, "_tc_") == index->name) + { +#ifdef FINSH_USING_DESCRIPTION + rt_kprintf("%-16s -- %s\n", index->name + 4, index->desc); +#else + rt_kprintf("%s\n", index->name + 4); +#endif + } + } +} +FINSH_FUNCTION_EXPORT(list_tc, list all testcases); +#endif + diff --git a/examples/kernel/tc_comm.h b/examples/kernel/tc_comm.h index 9333b96815fd6b0f175a26f38afa5f9671c53b83..714609768463c73d9f1a162da8a6131963cbaa60 100644 --- a/examples/kernel/tc_comm.h +++ b/examples/kernel/tc_comm.h @@ -1,43 +1,43 @@ -#ifndef __TC_COMM_H__ -#define __TC_COMM_H__ - -/* - * RT-Thread TestCase - * - */ -#include -#ifdef RT_USING_FINSH -#include -#endif - -#if RT_THREAD_PRIORITY_MAX == 8 -#define THREAD_PRIORITY 6 -#elif RT_THREAD_PRIORITY_MAX == 32 -#define THREAD_PRIORITY 25 -#elif RT_THREAD_PRIORITY_MAX == 256 -#define THREAD_PRIORITY 200 -#endif -#define THREAD_STACK_SIZE 512 -#define THREAD_TIMESLICE 5 - -#define TC_STAT_END 0x00 -#define TC_STAT_RUNNING 0x01 -#define TC_STAT_FAILED 0x10 -#define TC_STAT_PASSED 0x00 - -#ifdef RT_USING_TC -void tc_start(const char* tc_prefix); -void tc_stop(void); -void tc_done(rt_uint8_t state); -void tc_stat(rt_uint8_t state); -void tc_cleanup(void (*cleanup)(void)); -#else -#define tc_start(x) -#define tc_stop() -#define tc_done(s) -#define tc_stat(s) -#define tc_cleanup(c) -#endif - -#endif - +#ifndef __TC_COMM_H__ +#define __TC_COMM_H__ + +/* + * RT-Thread TestCase + * + */ +#include +#ifdef RT_USING_FINSH +#include +#endif + +#if RT_THREAD_PRIORITY_MAX == 8 +#define THREAD_PRIORITY 6 +#elif RT_THREAD_PRIORITY_MAX == 32 +#define THREAD_PRIORITY 25 +#elif RT_THREAD_PRIORITY_MAX == 256 +#define THREAD_PRIORITY 200 +#endif +#define THREAD_STACK_SIZE 512 +#define THREAD_TIMESLICE 5 + +#define TC_STAT_END 0x00 +#define TC_STAT_RUNNING 0x01 +#define TC_STAT_FAILED 0x10 +#define TC_STAT_PASSED 0x00 + +#ifdef RT_USING_TC +void tc_start(const char* tc_prefix); +void tc_stop(void); +void tc_done(rt_uint8_t state); +void tc_stat(rt_uint8_t state); +void tc_cleanup(void (*cleanup)(void)); +#else +#define tc_start(x) +#define tc_stop() +#define tc_done(s) +#define tc_stat(s) +#define tc_cleanup(c) +#endif + +#endif + diff --git a/examples/kernel/thread_delay.c b/examples/kernel/thread_delay.c index 28b579487a6d9c5561551aedf3dfc12421be9d03..23d25d6d5c46c85c4b72480b7d11c20ba67aae09 100644 --- a/examples/kernel/thread_delay.c +++ b/examples/kernel/thread_delay.c @@ -1,70 +1,70 @@ -#include -#include "tc_comm.h" - -/* - * This is an example for delay thread - */ -static struct rt_thread thread; -static char thread_stack[THREAD_STACK_SIZE]; -static void thread_entry(void* parameter) -{ - rt_tick_t tick; - rt_kprintf("thread inited ok\n"); - - rt_kprintf("thread delay 10 tick\n"); - tick = rt_tick_get(); - rt_thread_delay(10); - if (rt_tick_get() - tick > 10) - { - tc_done(TC_STAT_FAILED); - return; - } - - rt_kprintf("thread delay 15 tick\n"); - tick = rt_tick_get(); - rt_thread_delay(15); - if (rt_tick_get() - tick > 15) - { - tc_done(TC_STAT_FAILED); - return; - } - - rt_kprintf("thread exit\n"); - - tc_done(TC_STAT_PASSED); -} - -rt_err_t thread_delay_init() -{ - rt_err_t result; - - result = rt_thread_init(&thread, - "test", - thread_entry, RT_NULL, - &thread_stack[0], sizeof(thread_stack), - THREAD_PRIORITY, 10); - - if (result == RT_EOK) - rt_thread_startup(&thread); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return result; -} - -#ifdef RT_USING_TC -int _tc_thread_delay() -{ - thread_delay_init(); - - return 30; -} -FINSH_FUNCTION_EXPORT(_tc_thread_delay, a thread delay test); -#else -int rt_application_init() -{ - thread_delay_init(); - - return 0; -} -#endif +#include +#include "tc_comm.h" + +/* + * This is an example for delay thread + */ +static struct rt_thread thread; +static char thread_stack[THREAD_STACK_SIZE]; +static void thread_entry(void* parameter) +{ + rt_tick_t tick; + rt_kprintf("thread inited ok\n"); + + rt_kprintf("thread delay 10 tick\n"); + tick = rt_tick_get(); + rt_thread_delay(10); + if (rt_tick_get() - tick > 10) + { + tc_done(TC_STAT_FAILED); + return; + } + + rt_kprintf("thread delay 15 tick\n"); + tick = rt_tick_get(); + rt_thread_delay(15); + if (rt_tick_get() - tick > 15) + { + tc_done(TC_STAT_FAILED); + return; + } + + rt_kprintf("thread exit\n"); + + tc_done(TC_STAT_PASSED); +} + +rt_err_t thread_delay_init() +{ + rt_err_t result; + + result = rt_thread_init(&thread, + "test", + thread_entry, RT_NULL, + &thread_stack[0], sizeof(thread_stack), + THREAD_PRIORITY, 10); + + if (result == RT_EOK) + rt_thread_startup(&thread); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return result; +} + +#ifdef RT_USING_TC +int _tc_thread_delay() +{ + thread_delay_init(); + + return 30; +} +FINSH_FUNCTION_EXPORT(_tc_thread_delay, a thread delay test); +#else +int rt_application_init() +{ + thread_delay_init(); + + return 0; +} +#endif diff --git a/examples/kernel/thread_delete.c b/examples/kernel/thread_delete.c index 4c8336ca5d3f0fd5b9316e0b20e9cb4ea5b88a5a..6bae53994e9171cc3ff3b0d4740c43c195942dd8 100644 --- a/examples/kernel/thread_delete.c +++ b/examples/kernel/thread_delete.c @@ -1,144 +1,144 @@ -/* - * 程åºæ¸…å•ï¼šåˆ é™¤çº¿ç¨‹ - * - * 这个例å­ä¼šåˆ›å»ºä¸¤ä¸ªçº¿ç¨‹ï¼Œåœ¨ä¸€ä¸ªçº¿ç¨‹ä¸­åˆ é™¤å¦å¤–一个线程。 - */ -#include -#include "tc_comm.h" - -/* - * 线程删除(rt_thread_delete)函数仅适åˆäºŽåŠ¨æ€çº¿ç¨‹ï¼Œä¸ºäº†åœ¨ä¸€ä¸ªçº¿ç¨‹ - * 中访问å¦ä¸€ä¸ªçº¿ç¨‹çš„控制å—，所以把线程å—指针声明æˆå…¨å±€ç±»åž‹ä»¥ä¾›å…¨ - * 局访问 - */ -static rt_thread_t tid1 = RT_NULL, tid2 = RT_NULL; -/* 线程1çš„å…¥å£å‡½æ•° */ -static void thread1_entry(void* parameter) -{ - rt_uint32_t count = 0; - - while (1) - { - /* 线程1采用低优先级è¿è¡Œï¼Œä¸€ç›´æ‰“å°è®¡æ•°å€¼ */ - // rt_kprintf("thread count: %d\n", count ++); - count ++; - } -} -static void thread1_cleanup(struct rt_thread *tid) -{ - if (tid != tid1) - { - tc_stat(TC_STAT_END | TC_STAT_FAILED); - return ; - } - rt_kprintf("thread1 end\n"); - tid1 = RT_NULL; -} - -/* 线程2çš„å…¥å£å‡½æ•° */ -static void thread2_entry(void* parameter) -{ - /* 线程2拥有较高的优先级，以抢å çº¿ç¨‹1而获得执行 */ - - /* 线程2å¯åŠ¨åŽå…ˆç¡çœ 10个OS Tick */ - rt_thread_delay(10); - - /* - * 线程2唤醒åŽç›´æŽ¥åˆ é™¤çº¿ç¨‹1，删除线程1åŽï¼Œçº¿ç¨‹1自动脱离就绪线程 - * 队列 - */ - rt_thread_delete(tid1); - - /* - * 线程2继续休眠10个OS Tick然åŽé€€å‡ºï¼Œçº¿ç¨‹2休眠åŽåº”切æ¢åˆ°idle线程 - * idle线程将执行真正的线程1控制å—和线程栈的删除 - */ - rt_thread_delay(10); -} - -static void thread2_cleanup(struct rt_thread *tid) -{ - /* - * 线程2è¿è¡Œç»“æŸåŽä¹Ÿå°†è‡ªåŠ¨è¢«åˆ é™¤(线程控制å—和线程栈在idle线 - * 程中释放) - */ - - if (tid != tid2) - { - tc_stat(TC_STAT_END | TC_STAT_FAILED); - return ; - } - rt_kprintf("thread2 end\n"); - tid2 = RT_NULL; - tc_done(TC_STAT_PASSED); -} - -/* 线程删除示例的åˆå§‹åŒ– */ -int thread_delete_init() -{ - /* 创建线程1 */ - tid1 = rt_thread_create("t1", /* 线程1çš„å称是t1 */ - thread1_entry, RT_NULL, /* å…¥å£æ˜¯thread1_entry，å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid1 != RT_NULL) /* 如果获得线程控制å—，å¯åŠ¨è¿™ä¸ªçº¿ç¨‹ */ - { - tid1->cleanup = thread1_cleanup; - rt_thread_startup(tid1); - } - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* 创建线程1 */ - tid2 = rt_thread_create("t2", /* 线程1çš„å称是t2 */ - thread2_entry, RT_NULL, /* å…¥å£æ˜¯thread2_entry，å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); - if (tid2 != RT_NULL) /* 如果获得线程控制å—，å¯åŠ¨è¿™ä¸ªçº¿ç¨‹ */ - { - tid2->cleanup = thread2_cleanup; - rt_thread_startup(tid2); - } - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* lock scheduler */ - rt_enter_critical(); - - /* delete thread */ - if (tid1 != RT_NULL) - { - rt_kprintf("tid1 is bad\n"); - tc_stat(TC_STAT_FAILED); - } - if (tid2 != RT_NULL) - { - rt_kprintf("tid2 is bad\n"); - tc_stat(TC_STAT_FAILED); - } - - /* unlock scheduler */ - rt_exit_critical(); -} - -int _tc_thread_delete() -{ - /* set tc cleanup */ - tc_cleanup(_tc_cleanup); - thread_delete_init(); - - return 27; -} -FINSH_FUNCTION_EXPORT(_tc_thread_delete, a thread delete example); -#else -int rt_application_init() -{ - thread_delete_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šåˆ é™¤çº¿ç¨‹ + * + * 这个例å­ä¼šåˆ›å»ºä¸¤ä¸ªçº¿ç¨‹ï¼Œåœ¨ä¸€ä¸ªçº¿ç¨‹ä¸­åˆ é™¤å¦å¤–一个线程。 + */ +#include +#include "tc_comm.h" + +/* + * 线程删除(rt_thread_delete)函数仅适åˆäºŽåŠ¨æ€çº¿ç¨‹ï¼Œä¸ºäº†åœ¨ä¸€ä¸ªçº¿ç¨‹ + * 中访问å¦ä¸€ä¸ªçº¿ç¨‹çš„控制å—，所以把线程å—指针声明æˆå…¨å±€ç±»åž‹ä»¥ä¾›å…¨ + * 局访问 + */ +static rt_thread_t tid1 = RT_NULL, tid2 = RT_NULL; +/* 线程1çš„å…¥å£å‡½æ•° */ +static void thread1_entry(void* parameter) +{ + rt_uint32_t count = 0; + + while (1) + { + /* 线程1采用低优先级è¿è¡Œï¼Œä¸€ç›´æ‰“å°è®¡æ•°å€¼ */ + // rt_kprintf("thread count: %d\n", count ++); + count ++; + } +} +static void thread1_cleanup(struct rt_thread *tid) +{ + if (tid != tid1) + { + tc_stat(TC_STAT_END | TC_STAT_FAILED); + return ; + } + rt_kprintf("thread1 end\n"); + tid1 = RT_NULL; +} + +/* 线程2çš„å…¥å£å‡½æ•° */ +static void thread2_entry(void* parameter) +{ + /* 线程2拥有较高的优先级，以抢å çº¿ç¨‹1而获得执行 */ + + /* 线程2å¯åŠ¨åŽå…ˆç¡çœ 10个OS Tick */ + rt_thread_delay(10); + + /* + * 线程2唤醒åŽç›´æŽ¥åˆ é™¤çº¿ç¨‹1，删除线程1åŽï¼Œçº¿ç¨‹1自动脱离就绪线程 + * 队列 + */ + rt_thread_delete(tid1); + + /* + * 线程2继续休眠10个OS Tick然åŽé€€å‡ºï¼Œçº¿ç¨‹2休眠åŽåº”切æ¢åˆ°idle线程 + * idle线程将执行真正的线程1控制å—和线程栈的删除 + */ + rt_thread_delay(10); +} + +static void thread2_cleanup(struct rt_thread *tid) +{ + /* + * 线程2è¿è¡Œç»“æŸåŽä¹Ÿå°†è‡ªåŠ¨è¢«åˆ é™¤(线程控制å—和线程栈在idle线 + * 程中释放) + */ + + if (tid != tid2) + { + tc_stat(TC_STAT_END | TC_STAT_FAILED); + return ; + } + rt_kprintf("thread2 end\n"); + tid2 = RT_NULL; + tc_done(TC_STAT_PASSED); +} + +/* 线程删除示例的åˆå§‹åŒ– */ +int thread_delete_init() +{ + /* 创建线程1 */ + tid1 = rt_thread_create("t1", /* 线程1çš„å称是t1 */ + thread1_entry, RT_NULL, /* å…¥å£æ˜¯thread1_entry，å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid1 != RT_NULL) /* 如果获得线程控制å—，å¯åŠ¨è¿™ä¸ªçº¿ç¨‹ */ + { + tid1->cleanup = thread1_cleanup; + rt_thread_startup(tid1); + } + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* 创建线程1 */ + tid2 = rt_thread_create("t2", /* 线程1çš„å称是t2 */ + thread2_entry, RT_NULL, /* å…¥å£æ˜¯thread2_entry，å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); + if (tid2 != RT_NULL) /* 如果获得线程控制å—，å¯åŠ¨è¿™ä¸ªçº¿ç¨‹ */ + { + tid2->cleanup = thread2_cleanup; + rt_thread_startup(tid2); + } + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* lock scheduler */ + rt_enter_critical(); + + /* delete thread */ + if (tid1 != RT_NULL) + { + rt_kprintf("tid1 is bad\n"); + tc_stat(TC_STAT_FAILED); + } + if (tid2 != RT_NULL) + { + rt_kprintf("tid2 is bad\n"); + tc_stat(TC_STAT_FAILED); + } + + /* unlock scheduler */ + rt_exit_critical(); +} + +int _tc_thread_delete() +{ + /* set tc cleanup */ + tc_cleanup(_tc_cleanup); + thread_delete_init(); + + return 27; +} +FINSH_FUNCTION_EXPORT(_tc_thread_delete, a thread delete example); +#else +int rt_application_init() +{ + thread_delete_init(); + + return 0; +} +#endif diff --git a/examples/kernel/thread_detach.c b/examples/kernel/thread_detach.c index 84c85977fb1928f67b38af377b92cef98e34a868..af1824ae30d45f6482166779f5975e3362a5bc3a 100644 --- a/examples/kernel/thread_detach.c +++ b/examples/kernel/thread_detach.c @@ -1,118 +1,118 @@ -/* - * 程åºæ¸…å•ï¼šçº¿ç¨‹è„±ç¦» - * - * 这个例å­ä¼šåˆ›å»ºä¸¤ä¸ªçº¿ç¨‹ï¼Œåœ¨å…¶ä¸­ä¸€ä¸ªçº¿ç¨‹ä¸­æ‰§è¡Œå¯¹å¦ä¸€ä¸ªçº¿ç¨‹çš„脱离。 - */ -#include -#include "tc_comm.h" - -/* 线程1æŽ§åˆ¶å— */ -static struct rt_thread thread1; -/* 线程1æ ˆ */ -static rt_uint8_t thread1_stack[THREAD_STACK_SIZE]; -/* 线程2æŽ§åˆ¶å— */ -static struct rt_thread thread2; -/* 线程2æ ˆ */ -static rt_uint8_t thread2_stack[THREAD_STACK_SIZE]; - -/* 线程1å…¥å£ */ -static void thread1_entry(void* parameter) -{ - rt_uint32_t count = 0; - - while (1) - { - /* 线程1采用低优先级è¿è¡Œï¼Œä¸€ç›´æ‰“å°è®¡æ•°å€¼ */ - rt_kprintf("thread count: %d\n", count ++); - } -} - -/* 线程2å…¥å£ */ -static void thread2_entry(void* parameter) -{ - /* 线程2拥有较高的优先级，以抢å çº¿ç¨‹1而获得执行 */ - - /* 线程2å¯åŠ¨åŽå…ˆç¡çœ 10个OS Tick */ - rt_thread_delay(10); - - /* - * 线程2唤醒åŽç›´æŽ¥æ‰§è¡Œçº¿ç¨‹1脱离，线程1将从就绪线程队列中删除 - */ - rt_thread_detach(&thread1); - - /* - * 线程2继续休眠10个OS Tick然åŽé€€å‡º - */ - rt_thread_delay(10); - - /* - * 线程2è¿è¡Œç»“æŸåŽä¹Ÿå°†è‡ªåŠ¨è¢«ä»Žå°±ç»ªé˜Ÿåˆ—中删除，并脱离线程队列 - */ -} - -int thread_detach_init() -{ - rt_err_t result; - - /* åˆå§‹åŒ–线程1 */ - result = rt_thread_init(&thread1, "t1", /* 线程å：t1 */ - thread1_entry, RT_NULL, /* 线程的入å£æ˜¯thread1_entry，入å£å‚数是RT_NULL*/ - &thread1_stack[0], sizeof(thread1_stack), /* 线程栈是thread1_stack */ - THREAD_PRIORITY, 10); - if (result == RT_EOK) /* 如果返回正确，å¯åŠ¨çº¿ç¨‹1 */ - rt_thread_startup(&thread1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* åˆå§‹åŒ–线程2 */ - result = rt_thread_init(&thread2, "t2", /* 线程å：t2 */ - thread2_entry, RT_NULL, /* 线程的入å£æ˜¯thread2_entry，入å£å‚数是RT_NULL*/ - &thread2_stack[0], sizeof(thread2_stack), /* 线程栈是thread2_stack */ - THREAD_PRIORITY - 1, 10); - if (result == RT_EOK) /* 如果返回正确，å¯åŠ¨çº¿ç¨‹2 */ - rt_thread_startup(&thread2); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 执行线程脱离 */ - if (thread1.stat != RT_THREAD_CLOSE) - rt_thread_detach(&thread1); - if (thread2.stat != RT_THREAD_CLOSE) - rt_thread_detach(&thread2); - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_thread_detach() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - thread_detach_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 25; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_thread_detach, a static thread example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - thread_detach_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šçº¿ç¨‹è„±ç¦» + * + * 这个例å­ä¼šåˆ›å»ºä¸¤ä¸ªçº¿ç¨‹ï¼Œåœ¨å…¶ä¸­ä¸€ä¸ªçº¿ç¨‹ä¸­æ‰§è¡Œå¯¹å¦ä¸€ä¸ªçº¿ç¨‹çš„脱离。 + */ +#include +#include "tc_comm.h" + +/* 线程1æŽ§åˆ¶å— */ +static struct rt_thread thread1; +/* 线程1æ ˆ */ +static rt_uint8_t thread1_stack[THREAD_STACK_SIZE]; +/* 线程2æŽ§åˆ¶å— */ +static struct rt_thread thread2; +/* 线程2æ ˆ */ +static rt_uint8_t thread2_stack[THREAD_STACK_SIZE]; + +/* 线程1å…¥å£ */ +static void thread1_entry(void* parameter) +{ + rt_uint32_t count = 0; + + while (1) + { + /* 线程1采用低优先级è¿è¡Œï¼Œä¸€ç›´æ‰“å°è®¡æ•°å€¼ */ + rt_kprintf("thread count: %d\n", count ++); + } +} + +/* 线程2å…¥å£ */ +static void thread2_entry(void* parameter) +{ + /* 线程2拥有较高的优先级，以抢å çº¿ç¨‹1而获得执行 */ + + /* 线程2å¯åŠ¨åŽå…ˆç¡çœ 10个OS Tick */ + rt_thread_delay(10); + + /* + * 线程2唤醒åŽç›´æŽ¥æ‰§è¡Œçº¿ç¨‹1脱离，线程1将从就绪线程队列中删除 + */ + rt_thread_detach(&thread1); + + /* + * 线程2继续休眠10个OS Tick然åŽé€€å‡º + */ + rt_thread_delay(10); + + /* + * 线程2è¿è¡Œç»“æŸåŽä¹Ÿå°†è‡ªåŠ¨è¢«ä»Žå°±ç»ªé˜Ÿåˆ—中删除，并脱离线程队列 + */ +} + +int thread_detach_init() +{ + rt_err_t result; + + /* åˆå§‹åŒ–线程1 */ + result = rt_thread_init(&thread1, "t1", /* 线程å：t1 */ + thread1_entry, RT_NULL, /* 线程的入å£æ˜¯thread1_entry，入å£å‚数是RT_NULL*/ + &thread1_stack[0], sizeof(thread1_stack), /* 线程栈是thread1_stack */ + THREAD_PRIORITY, 10); + if (result == RT_EOK) /* 如果返回正确，å¯åŠ¨çº¿ç¨‹1 */ + rt_thread_startup(&thread1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* åˆå§‹åŒ–线程2 */ + result = rt_thread_init(&thread2, "t2", /* 线程å：t2 */ + thread2_entry, RT_NULL, /* 线程的入å£æ˜¯thread2_entry，入å£å‚数是RT_NULL*/ + &thread2_stack[0], sizeof(thread2_stack), /* 线程栈是thread2_stack */ + THREAD_PRIORITY - 1, 10); + if (result == RT_EOK) /* 如果返回正确，å¯åŠ¨çº¿ç¨‹2 */ + rt_thread_startup(&thread2); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 执行线程脱离 */ + if (thread1.stat != RT_THREAD_CLOSE) + rt_thread_detach(&thread1); + if (thread2.stat != RT_THREAD_CLOSE) + rt_thread_detach(&thread2); + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_thread_detach() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + thread_detach_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 25; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_thread_detach, a static thread example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + thread_detach_init(); + + return 0; +} +#endif diff --git a/examples/kernel/thread_dynamic.c b/examples/kernel/thread_dynamic.c index 9d1218be5d8308163603997a4097c6c9bf698771..960a40de9d4b543241b54c2180350a9a696fc286 100644 --- a/examples/kernel/thread_dynamic.c +++ b/examples/kernel/thread_dynamic.c @@ -1,44 +1,44 @@ -#include -#include "tc_comm.h" - -static void thread_entry(void* parameter) -{ - rt_kprintf("thread dynamicly created ok\n"); - rt_thread_delay(10); - rt_kprintf("thread exit\n"); - - tc_done(TC_STAT_PASSED); -} - -int thread_dynamic_init() -{ - rt_thread_t tid; - - tid = rt_thread_create("test", - thread_entry, RT_NULL, - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid != RT_NULL) - rt_thread_startup(tid); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -int _tc_thread_dynamic() -{ - thread_dynamic_init(); - - return 20; -} -FINSH_FUNCTION_EXPORT(_tc_thread_dynamic, a dynamic thread test); -#else -int rt_application_init() -{ - thread_dynamic_init(); - - return 0; -} -#endif - +#include +#include "tc_comm.h" + +static void thread_entry(void* parameter) +{ + rt_kprintf("thread dynamicly created ok\n"); + rt_thread_delay(10); + rt_kprintf("thread exit\n"); + + tc_done(TC_STAT_PASSED); +} + +int thread_dynamic_init() +{ + rt_thread_t tid; + + tid = rt_thread_create("test", + thread_entry, RT_NULL, + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid != RT_NULL) + rt_thread_startup(tid); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +int _tc_thread_dynamic() +{ + thread_dynamic_init(); + + return 20; +} +FINSH_FUNCTION_EXPORT(_tc_thread_dynamic, a dynamic thread test); +#else +int rt_application_init() +{ + thread_dynamic_init(); + + return 0; +} +#endif + diff --git a/examples/kernel/thread_dynamic_simple.c b/examples/kernel/thread_dynamic_simple.c index c8a4b905aadcf60c8b2d87288a9112fea3db075d..9d7612bddc06dfd383364bd3a3e9ff82b6dbe42f 100644 --- a/examples/kernel/thread_dynamic_simple.c +++ b/examples/kernel/thread_dynamic_simple.c @@ -1,89 +1,89 @@ -/* - * 程åºæ¸…å•ï¼šåŠ¨æ€çº¿ç¨‹ - * - * 这个程åºä¼šåˆå§‹åŒ–2个动æ€çº¿ç¨‹ï¼Œå®ƒä»¬æ‹¥æœ‰å…±åŒçš„å…¥å£å‡½æ•°ï¼Œä½†å‚æ•°ä¸ç›¸åŒ - */ -#include -#include "tc_comm.h" - -/* 指å‘线程控制å—的指针 */ -static rt_thread_t tid1 = RT_NULL; -static rt_thread_t tid2 = RT_NULL; -/* çº¿ç¨‹å…¥å£ */ -static void thread_entry(void* parameter) -{ - rt_uint32_t count = 0; - rt_uint32_t no = (rt_uint32_t) parameter; /* 获得正确的入å£å‚æ•° */ - - while (1) - { - /* 打å°çº¿ç¨‹è®¡æ•°å€¼è¾“出 */ - rt_kprintf("thread%d count: %d\n", no, count ++); - - /* 休眠10个OS Tick */ - rt_thread_delay(10); - } -} - -int thread_dynamic_simple_init() -{ - /* 创建线程1 */ - tid1 = rt_thread_create("t1", - thread_entry, (void*)1, /* 线程入å£æ˜¯thread_entry, å…¥å£å‚数是1 */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid1 != RT_NULL) - rt_thread_startup(tid1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* 创建线程2 */ - tid2 = rt_thread_create("t2", - thread_entry, (void*)2, /* 线程入å£æ˜¯thread_entry, å…¥å£å‚数是2 */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid2 != RT_NULL) - rt_thread_startup(tid2); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除线程 */ - if (tid1 != RT_NULL && tid1->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid1); - if (tid2 != RT_NULL && tid2->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid2); - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_thread_dynamic_simple() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - thread_dynamic_simple_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_thread_dynamic_simple, a dynamic thread example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - thread_dynamic_simple_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šåŠ¨æ€çº¿ç¨‹ + * + * 这个程åºä¼šåˆå§‹åŒ–2个动æ€çº¿ç¨‹ï¼Œå®ƒä»¬æ‹¥æœ‰å…±åŒçš„å…¥å£å‡½æ•°ï¼Œä½†å‚æ•°ä¸ç›¸åŒ + */ +#include +#include "tc_comm.h" + +/* 指å‘线程控制å—的指针 */ +static rt_thread_t tid1 = RT_NULL; +static rt_thread_t tid2 = RT_NULL; +/* çº¿ç¨‹å…¥å£ */ +static void thread_entry(void* parameter) +{ + rt_uint32_t count = 0; + rt_uint32_t no = (rt_uint32_t) parameter; /* 获得正确的入å£å‚æ•° */ + + while (1) + { + /* 打å°çº¿ç¨‹è®¡æ•°å€¼è¾“出 */ + rt_kprintf("thread%d count: %d\n", no, count ++); + + /* 休眠10个OS Tick */ + rt_thread_delay(10); + } +} + +int thread_dynamic_simple_init() +{ + /* 创建线程1 */ + tid1 = rt_thread_create("t1", + thread_entry, (void*)1, /* 线程入å£æ˜¯thread_entry, å…¥å£å‚数是1 */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid1 != RT_NULL) + rt_thread_startup(tid1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* 创建线程2 */ + tid2 = rt_thread_create("t2", + thread_entry, (void*)2, /* 线程入å£æ˜¯thread_entry, å…¥å£å‚数是2 */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid2 != RT_NULL) + rt_thread_startup(tid2); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除线程 */ + if (tid1 != RT_NULL && tid1->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid1); + if (tid2 != RT_NULL && tid2->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid2); + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_thread_dynamic_simple() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + thread_dynamic_simple_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_thread_dynamic_simple, a dynamic thread example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + thread_dynamic_simple_init(); + + return 0; +} +#endif diff --git a/examples/kernel/thread_priority.c b/examples/kernel/thread_priority.c index 6d0692e4dc4afeb73465c8f65222f8834d1bfec4..1d6fb4a80ebc2e2e178b8d3ffc706bab67011527 100644 --- a/examples/kernel/thread_priority.c +++ b/examples/kernel/thread_priority.c @@ -1,105 +1,105 @@ -#include -#include "tc_comm.h" - -struct rt_thread thread1; -struct rt_thread thread2; -static char thread1_stack[THREAD_STACK_SIZE]; -static char thread2_stack[THREAD_STACK_SIZE]; -static rt_uint32_t count = 0; - -/* - * the priority of thread1 > the priority of thread2 - */ -static void thread1_entry(void* parameter) -{ - while (1) - { - count ++; - rt_kprintf("count = %d\n", count); - - rt_thread_delay(10); - } -} - -static void thread2_entry(void* parameter) -{ - rt_tick_t tick; - - tick = rt_tick_get(); - while (1) - { - if (rt_tick_get() - tick >= 50) - { - if (count == 0) - tc_done(TC_STAT_FAILED); - else - tc_done(TC_STAT_PASSED); - - break; - } - } -} - -int thread_priority_init() -{ - rt_err_t result; - - result = rt_thread_init(&thread1, - "t1", - thread1_entry, RT_NULL, - &thread1_stack[0], sizeof(thread1_stack), - THREAD_PRIORITY - 1, THREAD_TIMESLICE); - - if (result == RT_EOK) - rt_thread_startup(&thread1); - else - tc_stat(TC_STAT_FAILED); - - rt_thread_init(&thread2, - "t2", - thread2_entry, RT_NULL, - &thread2_stack[0], sizeof(thread2_stack), - THREAD_PRIORITY + 1, THREAD_TIMESLICE); - - if (result == RT_EOK) - rt_thread_startup(&thread2); - else - tc_stat(TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* lock scheduler */ - rt_enter_critical(); - - if (thread1.stat != RT_THREAD_CLOSE) - rt_thread_detach(&thread1); - if (thread2.stat != RT_THREAD_CLOSE) - rt_thread_detach(&thread2); - - /* unlock scheduler */ - rt_exit_critical(); -} -int _tc_thread_priority() -{ - count = 0; - - /* set tc cleanup */ - tc_cleanup(_tc_cleanup); - thread_priority_init(); - - return RT_TICK_PER_SECOND; -} -FINSH_FUNCTION_EXPORT(_tc_thread_priority, a priority thread test); -#else -int rt_application_init() -{ - thread_priority_init(); - - return 0; -} -#endif - +#include +#include "tc_comm.h" + +struct rt_thread thread1; +struct rt_thread thread2; +static char thread1_stack[THREAD_STACK_SIZE]; +static char thread2_stack[THREAD_STACK_SIZE]; +static rt_uint32_t count = 0; + +/* + * the priority of thread1 > the priority of thread2 + */ +static void thread1_entry(void* parameter) +{ + while (1) + { + count ++; + rt_kprintf("count = %d\n", count); + + rt_thread_delay(10); + } +} + +static void thread2_entry(void* parameter) +{ + rt_tick_t tick; + + tick = rt_tick_get(); + while (1) + { + if (rt_tick_get() - tick >= 50) + { + if (count == 0) + tc_done(TC_STAT_FAILED); + else + tc_done(TC_STAT_PASSED); + + break; + } + } +} + +int thread_priority_init() +{ + rt_err_t result; + + result = rt_thread_init(&thread1, + "t1", + thread1_entry, RT_NULL, + &thread1_stack[0], sizeof(thread1_stack), + THREAD_PRIORITY - 1, THREAD_TIMESLICE); + + if (result == RT_EOK) + rt_thread_startup(&thread1); + else + tc_stat(TC_STAT_FAILED); + + rt_thread_init(&thread2, + "t2", + thread2_entry, RT_NULL, + &thread2_stack[0], sizeof(thread2_stack), + THREAD_PRIORITY + 1, THREAD_TIMESLICE); + + if (result == RT_EOK) + rt_thread_startup(&thread2); + else + tc_stat(TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* lock scheduler */ + rt_enter_critical(); + + if (thread1.stat != RT_THREAD_CLOSE) + rt_thread_detach(&thread1); + if (thread2.stat != RT_THREAD_CLOSE) + rt_thread_detach(&thread2); + + /* unlock scheduler */ + rt_exit_critical(); +} +int _tc_thread_priority() +{ + count = 0; + + /* set tc cleanup */ + tc_cleanup(_tc_cleanup); + thread_priority_init(); + + return RT_TICK_PER_SECOND; +} +FINSH_FUNCTION_EXPORT(_tc_thread_priority, a priority thread test); +#else +int rt_application_init() +{ + thread_priority_init(); + + return 0; +} +#endif + diff --git a/examples/kernel/thread_resume.c b/examples/kernel/thread_resume.c index e0ed6fa5f79527b659a5bee968d0c23464314848..ac8b6cb4896fa8601db03412ec8af7c2ecbfd914 100644 --- a/examples/kernel/thread_resume.c +++ b/examples/kernel/thread_resume.c @@ -1,123 +1,123 @@ -/* - * 程åºæ¸…å•ï¼šå”¤é†’线程 - * - * 这个例å­ä¸­å°†åˆ›å»ºä¸¤ä¸ªåŠ¨æ€çº¿ç¨‹ï¼Œä½Žä¼˜å…ˆçº§çº¿ç¨‹å°†æŒ‚èµ·è‡ªèº«ï¼Œç„¶åŽ - * 高优先级线程将在一定时刻åŽå”¤é†’低优先级线程。 - */ -#include -#include "tc_comm.h" - -/* 指å‘线程控制å—的指针 */ -static rt_thread_t tid1 = RT_NULL; -static rt_thread_t tid2 = RT_NULL; -/* 线程1å…¥å£ */ -static void thread1_entry(void* parameter) -{ - /* 低优先级线程1开始è¿è¡Œ */ - rt_kprintf("thread1 startup%d\n"); - - /* 挂起自身 */ - rt_kprintf("suspend thread self\n"); - rt_thread_suspend(tid1); - /* 主动执行线程调度 */ - rt_schedule(); - - /* 当线程1被唤醒时 */ - rt_kprintf("thread1 resumed\n"); -} -static void thread_cleanup(rt_thread_t tid) -{ - if (tid == tid1) - { - tid1 = RT_NULL; - } - if (tid == tid2) - { - tid = RT_NULL; - } -} - -/* 线程2å…¥å£ */ -static void thread2_entry(void* parameter) -{ - /* 延时10个OS Tick */ - rt_thread_delay(10); - - /* 唤醒线程1 */ - rt_thread_resume(tid1); - rt_kprintf("thread2: to resume thread1\n"); - - /* 延时10个OS Tick */ - rt_thread_delay(10); - - /* 线程2自动退出 */ -} - -int thread_resume_init() -{ - /* 创建线程1 */ - tid1 = rt_thread_create("thread", - thread1_entry, RT_NULL, /* 线程入å£æ˜¯thread1_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid1 != RT_NULL) - { - tid1->cleanup = thread_cleanup; - rt_thread_startup(tid1); - } - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* 创建线程2 */ - tid2 = rt_thread_create("thread", - thread2_entry, RT_NULL, /* 线程入å£æ˜¯thread2_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); - if (tid2 != RT_NULL) - { - tid2->cleanup = thread_cleanup; - rt_thread_startup(tid2); - } - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除线程 */ - if (tid1 != RT_NULL && tid1->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid1); - if (tid2 != RT_NULL && tid2->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid2); - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_thread_resume() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - thread_resume_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 25; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_thread_resume, a thread resume example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - thread_resume_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šå”¤é†’线程 + * + * 这个例å­ä¸­å°†åˆ›å»ºä¸¤ä¸ªåŠ¨æ€çº¿ç¨‹ï¼Œä½Žä¼˜å…ˆçº§çº¿ç¨‹å°†æŒ‚èµ·è‡ªèº«ï¼Œç„¶åŽ + * 高优先级线程将在一定时刻åŽå”¤é†’低优先级线程。 + */ +#include +#include "tc_comm.h" + +/* 指å‘线程控制å—的指针 */ +static rt_thread_t tid1 = RT_NULL; +static rt_thread_t tid2 = RT_NULL; +/* 线程1å…¥å£ */ +static void thread1_entry(void* parameter) +{ + /* 低优先级线程1开始è¿è¡Œ */ + rt_kprintf("thread1 startup%d\n"); + + /* 挂起自身 */ + rt_kprintf("suspend thread self\n"); + rt_thread_suspend(tid1); + /* 主动执行线程调度 */ + rt_schedule(); + + /* 当线程1被唤醒时 */ + rt_kprintf("thread1 resumed\n"); +} +static void thread_cleanup(rt_thread_t tid) +{ + if (tid == tid1) + { + tid1 = RT_NULL; + } + if (tid == tid2) + { + tid = RT_NULL; + } +} + +/* 线程2å…¥å£ */ +static void thread2_entry(void* parameter) +{ + /* 延时10个OS Tick */ + rt_thread_delay(10); + + /* 唤醒线程1 */ + rt_thread_resume(tid1); + rt_kprintf("thread2: to resume thread1\n"); + + /* 延时10个OS Tick */ + rt_thread_delay(10); + + /* 线程2自动退出 */ +} + +int thread_resume_init() +{ + /* 创建线程1 */ + tid1 = rt_thread_create("thread", + thread1_entry, RT_NULL, /* 线程入å£æ˜¯thread1_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid1 != RT_NULL) + { + tid1->cleanup = thread_cleanup; + rt_thread_startup(tid1); + } + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* 创建线程2 */ + tid2 = rt_thread_create("thread", + thread2_entry, RT_NULL, /* 线程入å£æ˜¯thread2_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); + if (tid2 != RT_NULL) + { + tid2->cleanup = thread_cleanup; + rt_thread_startup(tid2); + } + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除线程 */ + if (tid1 != RT_NULL && tid1->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid1); + if (tid2 != RT_NULL && tid2->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid2); + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_thread_resume() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + thread_resume_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 25; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_thread_resume, a thread resume example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + thread_resume_init(); + + return 0; +} +#endif diff --git a/examples/kernel/thread_same_priority.c b/examples/kernel/thread_same_priority.c index 228990ba1a519606822597253b0d214af34c9394..5e0fb8111641853ba505d2b515ec6f814e6505b3 100644 --- a/examples/kernel/thread_same_priority.c +++ b/examples/kernel/thread_same_priority.c @@ -1,96 +1,96 @@ -#include -#include "tc_comm.h" - -static struct rt_thread thread1; -static struct rt_thread thread2; -static char thread1_stack[THREAD_STACK_SIZE]; -static char thread2_stack[THREAD_STACK_SIZE]; - -volatile static rt_uint32_t t1_count = 0; -volatile static rt_uint32_t t2_count = 0; -static void thread1_entry(void* parameter) -{ - while (1) - { - t1_count ++; - } -} - -static void thread2_entry(void* parameter) -{ - while (1) - { - t2_count ++; - } -} - -rt_err_t thread_same_priority_init() -{ - rt_err_t result; - - result = rt_thread_init(&thread1, - "t1", - thread1_entry, RT_NULL, - &thread1_stack[0], sizeof(thread1_stack), - THREAD_PRIORITY, 10); - if (result == RT_EOK) - rt_thread_startup(&thread1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - result = rt_thread_init(&thread2, - "t2", - thread2_entry, RT_NULL, - &thread2_stack[0], sizeof(thread2_stack), - THREAD_PRIORITY, 5); - if (result == RT_EOK) - rt_thread_startup(&thread2); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return result; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* lock scheduler */ - rt_enter_critical(); - - if (thread1.stat != RT_THREAD_CLOSE) - rt_thread_detach(&thread1); - if (thread2.stat != RT_THREAD_CLOSE) - rt_thread_detach(&thread2); - - /* unlock scheduler */ - rt_exit_critical(); - - rt_kprintf("t1_count=%d t2_count=%d\n",t1_count,t2_count); - - if (t1_count / t2_count != 2) - tc_stat(TC_STAT_END | TC_STAT_FAILED); - else - tc_done(TC_STAT_PASSED); -} - -int _tc_thread_same_priority() -{ - t1_count = 0; - t2_count = 0; - - /* set tc cleanup */ - tc_cleanup(_tc_cleanup); - - thread_same_priority_init(); - - return 100; -} -FINSH_FUNCTION_EXPORT(_tc_thread_same_priority, a same priority thread test); -#else -int rt_application_init() -{ - thread_same_priority_init(); - - return 0; -} -#endif +#include +#include "tc_comm.h" + +static struct rt_thread thread1; +static struct rt_thread thread2; +static char thread1_stack[THREAD_STACK_SIZE]; +static char thread2_stack[THREAD_STACK_SIZE]; + +volatile static rt_uint32_t t1_count = 0; +volatile static rt_uint32_t t2_count = 0; +static void thread1_entry(void* parameter) +{ + while (1) + { + t1_count ++; + } +} + +static void thread2_entry(void* parameter) +{ + while (1) + { + t2_count ++; + } +} + +rt_err_t thread_same_priority_init() +{ + rt_err_t result; + + result = rt_thread_init(&thread1, + "t1", + thread1_entry, RT_NULL, + &thread1_stack[0], sizeof(thread1_stack), + THREAD_PRIORITY, 10); + if (result == RT_EOK) + rt_thread_startup(&thread1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + result = rt_thread_init(&thread2, + "t2", + thread2_entry, RT_NULL, + &thread2_stack[0], sizeof(thread2_stack), + THREAD_PRIORITY, 5); + if (result == RT_EOK) + rt_thread_startup(&thread2); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return result; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* lock scheduler */ + rt_enter_critical(); + + if (thread1.stat != RT_THREAD_CLOSE) + rt_thread_detach(&thread1); + if (thread2.stat != RT_THREAD_CLOSE) + rt_thread_detach(&thread2); + + /* unlock scheduler */ + rt_exit_critical(); + + rt_kprintf("t1_count=%d t2_count=%d\n",t1_count,t2_count); + + if (t1_count / t2_count != 2) + tc_stat(TC_STAT_END | TC_STAT_FAILED); + else + tc_done(TC_STAT_PASSED); +} + +int _tc_thread_same_priority() +{ + t1_count = 0; + t2_count = 0; + + /* set tc cleanup */ + tc_cleanup(_tc_cleanup); + + thread_same_priority_init(); + + return 100; +} +FINSH_FUNCTION_EXPORT(_tc_thread_same_priority, a same priority thread test); +#else +int rt_application_init() +{ + thread_same_priority_init(); + + return 0; +} +#endif diff --git a/examples/kernel/thread_static.c b/examples/kernel/thread_static.c index 9a8c158c8663af0500d515368a5aadb23b07cacd..4547304b5815242c9c192a29b4023ad9e192735d 100644 --- a/examples/kernel/thread_static.c +++ b/examples/kernel/thread_static.c @@ -1,52 +1,52 @@ -#include -#include "tc_comm.h" - -/* - * This is an example for static thread - */ -static struct rt_thread thread; -static char thread_stack[THREAD_STACK_SIZE]; -static void thread_entry(void* parameter) -{ - rt_kprintf("thread staticly inited ok\n"); - rt_thread_delay(10); - rt_kprintf("thread exit\n"); - - tc_done(TC_STAT_PASSED); -} - -rt_err_t thread_static_init() -{ - rt_err_t result; - - result = rt_thread_init(&thread, - "test", - thread_entry, RT_NULL, - &thread_stack[0], sizeof(thread_stack), - THREAD_PRIORITY, 10); - - if (result == RT_EOK) - rt_thread_startup(&thread); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return result; -} - -#ifdef RT_USING_TC -int _tc_thread_static() -{ - thread_static_init(); - - return 20; -} -FINSH_FUNCTION_EXPORT(_tc_thread_static, a static thread test); -#else -int rt_application_init() -{ - thread_static_init(); - - return 0; -} -#endif - +#include +#include "tc_comm.h" + +/* + * This is an example for static thread + */ +static struct rt_thread thread; +static char thread_stack[THREAD_STACK_SIZE]; +static void thread_entry(void* parameter) +{ + rt_kprintf("thread staticly inited ok\n"); + rt_thread_delay(10); + rt_kprintf("thread exit\n"); + + tc_done(TC_STAT_PASSED); +} + +rt_err_t thread_static_init() +{ + rt_err_t result; + + result = rt_thread_init(&thread, + "test", + thread_entry, RT_NULL, + &thread_stack[0], sizeof(thread_stack), + THREAD_PRIORITY, 10); + + if (result == RT_EOK) + rt_thread_startup(&thread); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return result; +} + +#ifdef RT_USING_TC +int _tc_thread_static() +{ + thread_static_init(); + + return 20; +} +FINSH_FUNCTION_EXPORT(_tc_thread_static, a static thread test); +#else +int rt_application_init() +{ + thread_static_init(); + + return 0; +} +#endif + diff --git a/examples/kernel/thread_static_simple.c b/examples/kernel/thread_static_simple.c index 61005fd23b7b749da5a0845f775ae62f71ee5bd7..3ab8ffda012ce24a023dafce3b3c55ed3be8cdf3 100644 --- a/examples/kernel/thread_static_simple.c +++ b/examples/kernel/thread_static_simple.c @@ -1,99 +1,99 @@ -/* - * 程åºæ¸…å•ï¼šé™æ€çº¿ç¨‹ - * - * 这个程åºä¼šåˆå§‹åŒ–2个é™æ€çº¿ç¨‹ï¼Œå®ƒä»¬æ‹¥æœ‰å…±åŒçš„å…¥å£å‡½æ•°ï¼Œä½†å‚æ•°ä¸ç›¸åŒ - */ -#include -#include "tc_comm.h" - -/* 线程1æŽ§åˆ¶å— */ -static struct rt_thread thread1; -/* 线程1æ ˆ */ -static rt_uint8_t thread1_stack[THREAD_STACK_SIZE]; -/* 线程2æŽ§åˆ¶å— */ -static struct rt_thread thread2; -/* 线程2æ ˆ */ -static rt_uint8_t thread2_stack[THREAD_STACK_SIZE]; - -/* çº¿ç¨‹å…¥å£ */ -static void thread_entry(void* parameter) -{ - rt_uint32_t count = 0; - rt_uint32_t no = (rt_uint32_t) parameter; /* 获得正确的入å£å‚æ•° */ - - while (1) - { - /* 打å°çº¿ç¨‹è®¡æ•°å€¼è¾“出 */ - rt_kprintf("thread%d count: %d\n", no, count ++); - - /* 休眠10个OS Tick */ - rt_thread_delay(10); - } -} - -int thread_static_simple_init() -{ - rt_err_t result; - - /* åˆå§‹åŒ–线程1 */ - result = rt_thread_init(&thread1, "t1", /* 线程å：t1 */ - thread_entry, (void*)1, /* 线程的入å£æ˜¯thread_entry，入å£å‚数是1 */ - &thread1_stack[0], sizeof(thread1_stack), /* 线程栈是thread1_stack */ - THREAD_PRIORITY, 10); - if (result == RT_EOK) /* 如果返回正确，å¯åŠ¨çº¿ç¨‹1 */ - rt_thread_startup(&thread1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* åˆå§‹åŒ–线程2 */ - result = rt_thread_init(&thread2, "t2", /* 线程å：t2 */ - thread_entry, RT_NULL, /* 线程的入å£æ˜¯thread_entry，入å£å‚数是2 */ - &thread2_stack[0], sizeof(thread2_stack), /* 线程栈是thread2_stack */ - THREAD_PRIORITY + 1, 10); - if (result == RT_EOK) /* 如果返回正确，å¯åŠ¨çº¿ç¨‹2 */ - rt_thread_startup(&thread2); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 执行线程脱离 */ - if (thread1.stat != RT_THREAD_CLOSE) - rt_thread_detach(&thread1); - if (thread2.stat != RT_THREAD_CLOSE) - rt_thread_detach(&thread2); - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_thread_static_simple() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - thread_static_simple_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_thread_static_simple, a static thread example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - thread_static_simple_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šé™æ€çº¿ç¨‹ + * + * 这个程åºä¼šåˆå§‹åŒ–2个é™æ€çº¿ç¨‹ï¼Œå®ƒä»¬æ‹¥æœ‰å…±åŒçš„å…¥å£å‡½æ•°ï¼Œä½†å‚æ•°ä¸ç›¸åŒ + */ +#include +#include "tc_comm.h" + +/* 线程1æŽ§åˆ¶å— */ +static struct rt_thread thread1; +/* 线程1æ ˆ */ +static rt_uint8_t thread1_stack[THREAD_STACK_SIZE]; +/* 线程2æŽ§åˆ¶å— */ +static struct rt_thread thread2; +/* 线程2æ ˆ */ +static rt_uint8_t thread2_stack[THREAD_STACK_SIZE]; + +/* çº¿ç¨‹å…¥å£ */ +static void thread_entry(void* parameter) +{ + rt_uint32_t count = 0; + rt_uint32_t no = (rt_uint32_t) parameter; /* 获得正确的入å£å‚æ•° */ + + while (1) + { + /* 打å°çº¿ç¨‹è®¡æ•°å€¼è¾“出 */ + rt_kprintf("thread%d count: %d\n", no, count ++); + + /* 休眠10个OS Tick */ + rt_thread_delay(10); + } +} + +int thread_static_simple_init() +{ + rt_err_t result; + + /* åˆå§‹åŒ–线程1 */ + result = rt_thread_init(&thread1, "t1", /* 线程å：t1 */ + thread_entry, (void*)1, /* 线程的入å£æ˜¯thread_entry，入å£å‚数是1 */ + &thread1_stack[0], sizeof(thread1_stack), /* 线程栈是thread1_stack */ + THREAD_PRIORITY, 10); + if (result == RT_EOK) /* 如果返回正确，å¯åŠ¨çº¿ç¨‹1 */ + rt_thread_startup(&thread1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* åˆå§‹åŒ–线程2 */ + result = rt_thread_init(&thread2, "t2", /* 线程å：t2 */ + thread_entry, RT_NULL, /* 线程的入å£æ˜¯thread_entry，入å£å‚数是2 */ + &thread2_stack[0], sizeof(thread2_stack), /* 线程栈是thread2_stack */ + THREAD_PRIORITY + 1, 10); + if (result == RT_EOK) /* 如果返回正确，å¯åŠ¨çº¿ç¨‹2 */ + rt_thread_startup(&thread2); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 执行线程脱离 */ + if (thread1.stat != RT_THREAD_CLOSE) + rt_thread_detach(&thread1); + if (thread2.stat != RT_THREAD_CLOSE) + rt_thread_detach(&thread2); + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_thread_static_simple() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + thread_static_simple_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_thread_static_simple, a static thread example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + thread_static_simple_init(); + + return 0; +} +#endif diff --git a/examples/kernel/thread_suspend.c b/examples/kernel/thread_suspend.c index b38cb8fdfbd75672bb5cb20bff3494dfdd1f3e96..7c019573b1242ccb6f59130eb578b4f089e695b3 100644 --- a/examples/kernel/thread_suspend.c +++ b/examples/kernel/thread_suspend.c @@ -1,101 +1,101 @@ -/* - * 程åºæ¸…å•ï¼šæŒ‚起线程 - * - * 这个例å­ä¸­å°†åˆ›å»ºä¸¤ä¸ªåŠ¨æ€çº¿ç¨‹ï¼Œé«˜ä¼˜å…ˆçº§çº¿ç¨‹å°†åœ¨ä¸€å®šæ—¶åˆ»åŽæŒ‚起低优先级线程。 - */ -#include -#include "tc_comm.h" - -/* 指å‘线程控制å—的指针 */ -static rt_thread_t tid1 = RT_NULL; -static rt_thread_t tid2 = RT_NULL; -/* 线程1å…¥å£ */ -static void thread1_entry(void* parameter) -{ - rt_uint32_t count = 0; - - while (1) - { - /* 线程1采用低优先级è¿è¡Œï¼Œä¸€ç›´æ‰“å°è®¡æ•°å€¼ */ - rt_kprintf("thread count: %d\n", count ++); - } -} - -/* 线程2å…¥å£ */ -static void thread2_entry(void* parameter) -{ - /* 延时10个OS Tick */ - rt_thread_delay(10); - - /* 挂起线程1 */ - rt_thread_suspend(tid1); - - /* 延时10个OS Tick */ - rt_thread_delay(10); - - /* 线程2自动退出 */ - tid2 = RT_NULL; -} - -int thread_suspend_init() -{ - /* 创建线程1 */ - tid1 = rt_thread_create("thread", - thread1_entry, RT_NULL, /* 线程入å£æ˜¯thread1_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid1 != RT_NULL) - rt_thread_startup(tid1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* 创建线程2 */ - tid2 = rt_thread_create("thread", - thread2_entry, RT_NULL, /* 线程入å£æ˜¯thread2_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); - if (tid2 != RT_NULL) - rt_thread_startup(tid2); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除线程 */ - if (tid1 != RT_NULL && tid1->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid1); - if (tid2 != RT_NULL && tid2->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid2); - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_thread_suspend() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - thread_suspend_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_thread_suspend, a thread suspend example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - thread_suspend_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šæŒ‚起线程 + * + * 这个例å­ä¸­å°†åˆ›å»ºä¸¤ä¸ªåŠ¨æ€çº¿ç¨‹ï¼Œé«˜ä¼˜å…ˆçº§çº¿ç¨‹å°†åœ¨ä¸€å®šæ—¶åˆ»åŽæŒ‚起低优先级线程。 + */ +#include +#include "tc_comm.h" + +/* 指å‘线程控制å—的指针 */ +static rt_thread_t tid1 = RT_NULL; +static rt_thread_t tid2 = RT_NULL; +/* 线程1å…¥å£ */ +static void thread1_entry(void* parameter) +{ + rt_uint32_t count = 0; + + while (1) + { + /* 线程1采用低优先级è¿è¡Œï¼Œä¸€ç›´æ‰“å°è®¡æ•°å€¼ */ + rt_kprintf("thread count: %d\n", count ++); + } +} + +/* 线程2å…¥å£ */ +static void thread2_entry(void* parameter) +{ + /* 延时10个OS Tick */ + rt_thread_delay(10); + + /* 挂起线程1 */ + rt_thread_suspend(tid1); + + /* 延时10个OS Tick */ + rt_thread_delay(10); + + /* 线程2自动退出 */ + tid2 = RT_NULL; +} + +int thread_suspend_init() +{ + /* 创建线程1 */ + tid1 = rt_thread_create("thread", + thread1_entry, RT_NULL, /* 线程入å£æ˜¯thread1_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid1 != RT_NULL) + rt_thread_startup(tid1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* 创建线程2 */ + tid2 = rt_thread_create("thread", + thread2_entry, RT_NULL, /* 线程入å£æ˜¯thread2_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY - 1, THREAD_TIMESLICE); + if (tid2 != RT_NULL) + rt_thread_startup(tid2); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除线程 */ + if (tid1 != RT_NULL && tid1->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid1); + if (tid2 != RT_NULL && tid2->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid2); + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_thread_suspend() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + thread_suspend_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_thread_suspend, a thread suspend example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + thread_suspend_init(); + + return 0; +} +#endif diff --git a/examples/kernel/thread_yield.c b/examples/kernel/thread_yield.c index 71244589b84750065b74126d3b5e88dec7c76989..de2c3a53acdb9d78db2c612f67c1985e4858526d 100644 --- a/examples/kernel/thread_yield.c +++ b/examples/kernel/thread_yield.c @@ -1,101 +1,101 @@ -/* - * 程åºæ¸…å•ï¼š - */ -#include -#include "tc_comm.h" - -/* 指å‘线程控制å—的指针 */ -static rt_thread_t tid1 = RT_NULL; -static rt_thread_t tid2 = RT_NULL; -/* 线程1å…¥å£ */ -static void thread1_entry(void* parameter) -{ - rt_uint32_t count = 0; - - while (1) - { - /* 打å°çº¿ç¨‹1的输出 */ - rt_kprintf("thread1: count = %d\n", count ++); - - /* 执行yieldåŽåº”该切æ¢åˆ°thread2执行 */ - rt_thread_yield(); - } -} - -/* 线程2å…¥å£ */ -static void thread2_entry(void* parameter) -{ - rt_uint32_t count = 0; - - while (1) - { - /* 打å°çº¿ç¨‹2的输出 */ - rt_kprintf("thread2: count = %d\n", count ++); - - /* 执行yieldåŽåº”该切æ¢åˆ°thread1执行 */ - rt_thread_yield(); - } -} - -int thread_yield_init() -{ - /* 创建线程1 */ - tid1 = rt_thread_create("thread", - thread1_entry, RT_NULL, /* 线程入å£æ˜¯thread1_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid1 != RT_NULL) - rt_thread_startup(tid1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* 创建线程2 */ - tid2 = rt_thread_create("thread", - thread2_entry, RT_NULL, /* 线程入å£æ˜¯thread2_entry, å…¥å£å‚数是RT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid2 != RT_NULL) - rt_thread_startup(tid2); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除线程 */ - if (tid1 != RT_NULL && tid1->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid1); - if (tid2 != RT_NULL && tid2->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid2); - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_thread_yield() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - thread_yield_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 30; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_thread_yield, a thread yield example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - thread_yield_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼š + */ +#include +#include "tc_comm.h" + +/* 指å‘线程控制å—的指针 */ +static rt_thread_t tid1 = RT_NULL; +static rt_thread_t tid2 = RT_NULL; +/* 线程1å…¥å£ */ +static void thread1_entry(void* parameter) +{ + rt_uint32_t count = 0; + + while (1) + { + /* 打å°çº¿ç¨‹1的输出 */ + rt_kprintf("thread1: count = %d\n", count ++); + + /* 执行yieldåŽåº”该切æ¢åˆ°thread2执行 */ + rt_thread_yield(); + } +} + +/* 线程2å…¥å£ */ +static void thread2_entry(void* parameter) +{ + rt_uint32_t count = 0; + + while (1) + { + /* 打å°çº¿ç¨‹2的输出 */ + rt_kprintf("thread2: count = %d\n", count ++); + + /* 执行yieldåŽåº”该切æ¢åˆ°thread1执行 */ + rt_thread_yield(); + } +} + +int thread_yield_init() +{ + /* 创建线程1 */ + tid1 = rt_thread_create("thread", + thread1_entry, RT_NULL, /* 线程入å£æ˜¯thread1_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid1 != RT_NULL) + rt_thread_startup(tid1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* 创建线程2 */ + tid2 = rt_thread_create("thread", + thread2_entry, RT_NULL, /* 线程入å£æ˜¯thread2_entry, å…¥å£å‚数是RT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid2 != RT_NULL) + rt_thread_startup(tid2); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除线程 */ + if (tid1 != RT_NULL && tid1->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid1); + if (tid2 != RT_NULL && tid2->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid2); + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_thread_yield() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + thread_yield_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 30; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_thread_yield, a thread yield example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + thread_yield_init(); + + return 0; +} +#endif diff --git a/examples/kernel/timer_control.c b/examples/kernel/timer_control.c index f04521a752e0e8aef5a79e81501a01c6be76dd69..f685f140eb663e245910159882b2aa968797ab2e 100644 --- a/examples/kernel/timer_control.c +++ b/examples/kernel/timer_control.c @@ -1,84 +1,84 @@ -/* - * 程åºæ¸…å•ï¼šåŠ¨æ€å®šæ—¶å™¨ä¾‹ç¨‹ - * - * 这个例程会创建1个动æ€å‘¨æœŸåž‹å®šæ—¶å™¨å¯¹è±¡ï¼Œç„¶åŽæŽ§åˆ¶å®ƒè¿›è¡Œå®šæ—¶æ—¶é—´é•¿åº¦çš„更改。 - */ -#include -#include "tc_comm.h" - -/* å®šæ—¶å™¨çš„æŽ§åˆ¶å— */ -static rt_timer_t timer1; -static rt_uint8_t count; - -/* 定时器超时函数 */ -static void timeout1(void* parameter) -{ - rt_tick_t timeout = 50; - - rt_kprintf("periodic timer is timeout\n"); - - count ++; - /* åœæ­¢å®šæ—¶å™¨è‡ªèº« */ - if (count >= 8) - { - /* 控制定时器然åŽæ›´æ”¹è¶…时时间长度 */ - rt_timer_control(timer1, RT_TIMER_CTRL_SET_TIME, (void *)&timeout); - count = 0; - } -} - -void timer_control_init() -{ - /* 创建定时器1 */ - timer1 = rt_timer_create("timer1", /* 定时器å字是 timer1 */ - timeout1, /* 超时时回调的处ç†å‡½æ•° */ - RT_NULL, /* 超时函数的入å£å‚æ•° */ - 10, /* 定时长度，以OS Tick为å•ä½ï¼Œå³10个OS Tick */ - RT_TIMER_FLAG_PERIODIC); /* 周期性定时器 */ - /* å¯åŠ¨å®šæ—¶å™¨ */ - if (timer1 != RT_NULL) - rt_timer_start(timer1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除定时器对象 */ - rt_timer_delete(timer1); - timer1 = RT_NULL; - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_timer_control() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - - /* 执行定时器例程 */ - count = 0; - timer_control_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_timer_control, a timer control example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - timer_control_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šåŠ¨æ€å®šæ—¶å™¨ä¾‹ç¨‹ + * + * 这个例程会创建1个动æ€å‘¨æœŸåž‹å®šæ—¶å™¨å¯¹è±¡ï¼Œç„¶åŽæŽ§åˆ¶å®ƒè¿›è¡Œå®šæ—¶æ—¶é—´é•¿åº¦çš„更改。 + */ +#include +#include "tc_comm.h" + +/* å®šæ—¶å™¨çš„æŽ§åˆ¶å— */ +static rt_timer_t timer1; +static rt_uint8_t count; + +/* 定时器超时函数 */ +static void timeout1(void* parameter) +{ + rt_tick_t timeout = 50; + + rt_kprintf("periodic timer is timeout\n"); + + count ++; + /* åœæ­¢å®šæ—¶å™¨è‡ªèº« */ + if (count >= 8) + { + /* 控制定时器然åŽæ›´æ”¹è¶…时时间长度 */ + rt_timer_control(timer1, RT_TIMER_CTRL_SET_TIME, (void *)&timeout); + count = 0; + } +} + +void timer_control_init() +{ + /* 创建定时器1 */ + timer1 = rt_timer_create("timer1", /* 定时器å字是 timer1 */ + timeout1, /* 超时时回调的处ç†å‡½æ•° */ + RT_NULL, /* 超时函数的入å£å‚æ•° */ + 10, /* 定时长度，以OS Tick为å•ä½ï¼Œå³10个OS Tick */ + RT_TIMER_FLAG_PERIODIC); /* 周期性定时器 */ + /* å¯åŠ¨å®šæ—¶å™¨ */ + if (timer1 != RT_NULL) + rt_timer_start(timer1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除定时器对象 */ + rt_timer_delete(timer1); + timer1 = RT_NULL; + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_timer_control() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + + /* 执行定时器例程 */ + count = 0; + timer_control_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_timer_control, a timer control example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + timer_control_init(); + + return 0; +} +#endif diff --git a/examples/kernel/timer_dynamic.c b/examples/kernel/timer_dynamic.c index b28a4c9056a50e11cdaa7bb31e02e77d85cde94e..49262b8193cf1b75443cf98ec610dcde9d055d42 100644 --- a/examples/kernel/timer_dynamic.c +++ b/examples/kernel/timer_dynamic.c @@ -1,91 +1,91 @@ -/* - * 程åºæ¸…å•ï¼šåŠ¨æ€å®šæ—¶å™¨ä¾‹ç¨‹ - * - * 这个例程会创建两个动æ€å®šæ—¶å™¨å¯¹è±¡ï¼Œä¸€ä¸ªæ˜¯å•æ¬¡å®šæ—¶ï¼Œä¸€ä¸ªæ˜¯å‘¨æœŸæ€§çš„定时 - */ -#include -#include "tc_comm.h" - -/* å®šæ—¶å™¨çš„æŽ§åˆ¶å— */ -static rt_timer_t timer1; -static rt_timer_t timer2; - -/* 定时器1超时函数 */ -static void timeout1(void* parameter) -{ - rt_kprintf("periodic timer is timeout\n"); -} - -/* 定时器2超时函数 */ -static void timeout2(void* parameter) -{ - rt_kprintf("one shot timer is timeout\n"); -} - -void timer_create_init() -{ - /* 创建定时器1 */ - timer1 = rt_timer_create("timer1", /* 定时器å字是 timer1 */ - timeout1, /* 超时时回调的处ç†å‡½æ•° */ - RT_NULL, /* 超时函数的入å£å‚æ•° */ - 10, /* 定时长度，以OS Tick为å•ä½ï¼Œå³10个OS Tick */ - RT_TIMER_FLAG_PERIODIC); /* 周期性定时器 */ - /* å¯åŠ¨å®šæ—¶å™¨ */ - if (timer1 != RT_NULL) - rt_timer_start(timer1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - /* 创建定时器2 */ - timer2 = rt_timer_create("timer2", /* 定时器å字是 timer2 */ - timeout2, /* 超时时回调的处ç†å‡½æ•° */ - RT_NULL, /* 超时函数的入å£å‚æ•° */ - 30, /* 定时长度为30个OS Tick */ - RT_TIMER_FLAG_ONE_SHOT); /* å•æ¬¡å®šæ—¶å™¨ */ - - /* å¯åŠ¨å®šæ—¶å™¨ */ - if (timer2 != RT_NULL) - rt_timer_start(timer2); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除定时器对象 */ - rt_timer_delete(timer1); - rt_timer_delete(timer2); - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_timer_create() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - - /* 执行定时器例程 */ - timer_create_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_timer_create, a dynamic timer example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - timer_create_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šåŠ¨æ€å®šæ—¶å™¨ä¾‹ç¨‹ + * + * 这个例程会创建两个动æ€å®šæ—¶å™¨å¯¹è±¡ï¼Œä¸€ä¸ªæ˜¯å•æ¬¡å®šæ—¶ï¼Œä¸€ä¸ªæ˜¯å‘¨æœŸæ€§çš„定时 + */ +#include +#include "tc_comm.h" + +/* å®šæ—¶å™¨çš„æŽ§åˆ¶å— */ +static rt_timer_t timer1; +static rt_timer_t timer2; + +/* 定时器1超时函数 */ +static void timeout1(void* parameter) +{ + rt_kprintf("periodic timer is timeout\n"); +} + +/* 定时器2超时函数 */ +static void timeout2(void* parameter) +{ + rt_kprintf("one shot timer is timeout\n"); +} + +void timer_create_init() +{ + /* 创建定时器1 */ + timer1 = rt_timer_create("timer1", /* 定时器å字是 timer1 */ + timeout1, /* 超时时回调的处ç†å‡½æ•° */ + RT_NULL, /* 超时函数的入å£å‚æ•° */ + 10, /* 定时长度，以OS Tick为å•ä½ï¼Œå³10个OS Tick */ + RT_TIMER_FLAG_PERIODIC); /* 周期性定时器 */ + /* å¯åŠ¨å®šæ—¶å™¨ */ + if (timer1 != RT_NULL) + rt_timer_start(timer1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + /* 创建定时器2 */ + timer2 = rt_timer_create("timer2", /* 定时器å字是 timer2 */ + timeout2, /* 超时时回调的处ç†å‡½æ•° */ + RT_NULL, /* 超时函数的入å£å‚æ•° */ + 30, /* 定时长度为30个OS Tick */ + RT_TIMER_FLAG_ONE_SHOT); /* å•æ¬¡å®šæ—¶å™¨ */ + + /* å¯åŠ¨å®šæ—¶å™¨ */ + if (timer2 != RT_NULL) + rt_timer_start(timer2); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除定时器对象 */ + rt_timer_delete(timer1); + rt_timer_delete(timer2); + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_timer_create() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + + /* 执行定时器例程 */ + timer_create_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_timer_create, a dynamic timer example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + timer_create_init(); + + return 0; +} +#endif diff --git a/examples/kernel/timer_stop_self.c b/examples/kernel/timer_stop_self.c index 8a19637e521d85aa52847c556e91a566ef6eb0ac..6d1e287e54a81207ec88b775a327f3bb39e00fbc 100644 --- a/examples/kernel/timer_stop_self.c +++ b/examples/kernel/timer_stop_self.c @@ -1,82 +1,82 @@ -/* - * 程åºæ¸…å•ï¼šåŠ¨æ€å®šæ—¶å™¨ä¾‹ç¨‹ - * - * 这个例程会创建1个动æ€å‘¨æœŸåž‹å®šæ—¶å™¨å¯¹è±¡ - */ -#include -#include "tc_comm.h" - -/* å®šæ—¶å™¨çš„æŽ§åˆ¶å— */ -static rt_timer_t timer1; -static rt_uint8_t count; - -/* 定时器超时函数 */ -static void timeout1(void* parameter) -{ - rt_kprintf("periodic timer is timeout\n"); - - count ++; - /* åœæ­¢å®šæ—¶å™¨è‡ªèº« */ - if (count >= 8) - { - /* åœæ­¢å®šæ—¶å™¨ */ - rt_timer_stop(timer1); - count = 0; - } -} - -void timer_stop_self_init() -{ - /* 创建定时器1 */ - timer1 = rt_timer_create("timer1", /* 定时器å字是 timer1 */ - timeout1, /* 超时时回调的处ç†å‡½æ•° */ - RT_NULL, /* 超时函数的入å£å‚æ•° */ - 10, /* 定时长度，以OS Tick为å•ä½ï¼Œå³10个OS Tick */ - RT_TIMER_FLAG_PERIODIC); /* 周期性定时器 */ - /* å¯åŠ¨å®šæ—¶å™¨ */ - if (timer1 != RT_NULL) - rt_timer_start(timer1); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ - rt_enter_critical(); - - /* 删除定时器对象 */ - rt_timer_delete(timer1); - timer1 = RT_NULL; - - /* è°ƒåº¦å™¨è§£é” */ - rt_exit_critical(); - - /* 设置TestCaseçŠ¶æ€ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_timer_stop_self() -{ - /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ - tc_cleanup(_tc_cleanup); - - /* 执行定时器例程 */ - count = 0; - timer_stop_self_init(); - - /* 返回TestCaseè¿è¡Œçš„最长时间 */ - return 100; -} -/* 输出函数命令到finsh shell中 */ -FINSH_FUNCTION_EXPORT(_tc_timer_stop_self, a dynamic timer example); -#else -/* ç”¨æˆ·åº”ç”¨å…¥å£ */ -int rt_application_init() -{ - timer_stop_self_init(); - - return 0; -} -#endif +/* + * 程åºæ¸…å•ï¼šåŠ¨æ€å®šæ—¶å™¨ä¾‹ç¨‹ + * + * 这个例程会创建1个动æ€å‘¨æœŸåž‹å®šæ—¶å™¨å¯¹è±¡ + */ +#include +#include "tc_comm.h" + +/* å®šæ—¶å™¨çš„æŽ§åˆ¶å— */ +static rt_timer_t timer1; +static rt_uint8_t count; + +/* 定时器超时函数 */ +static void timeout1(void* parameter) +{ + rt_kprintf("periodic timer is timeout\n"); + + count ++; + /* åœæ­¢å®šæ—¶å™¨è‡ªèº« */ + if (count >= 8) + { + /* åœæ­¢å®šæ—¶å™¨ */ + rt_timer_stop(timer1); + count = 0; + } +} + +void timer_stop_self_init() +{ + /* 创建定时器1 */ + timer1 = rt_timer_create("timer1", /* 定时器å字是 timer1 */ + timeout1, /* 超时时回调的处ç†å‡½æ•° */ + RT_NULL, /* 超时函数的入å£å‚æ•° */ + 10, /* 定时长度，以OS Tick为å•ä½ï¼Œå³10个OS Tick */ + RT_TIMER_FLAG_PERIODIC); /* 周期性定时器 */ + /* å¯åŠ¨å®šæ—¶å™¨ */ + if (timer1 != RT_NULL) + rt_timer_start(timer1); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* 调度器上é”，上é”åŽï¼Œå°†ä¸å†åˆ‡æ¢åˆ°å…¶ä»–线程，仅å“应中断 */ + rt_enter_critical(); + + /* 删除定时器对象 */ + rt_timer_delete(timer1); + timer1 = RT_NULL; + + /* è°ƒåº¦å™¨è§£é” */ + rt_exit_critical(); + + /* 设置TestCaseçŠ¶æ€ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_timer_stop_self() +{ + /* 设置TestCase清ç†å›žè°ƒå‡½æ•° */ + tc_cleanup(_tc_cleanup); + + /* 执行定时器例程 */ + count = 0; + timer_stop_self_init(); + + /* 返回TestCaseè¿è¡Œçš„最长时间 */ + return 100; +} +/* 输出函数命令到finsh shell中 */ +FINSH_FUNCTION_EXPORT(_tc_timer_stop_self, a dynamic timer example); +#else +/* ç”¨æˆ·åº”ç”¨å…¥å£ */ +int rt_application_init() +{ + timer_stop_self_init(); + + return 0; +} +#endif diff --git a/examples/kernel/timer_timeout.c b/examples/kernel/timer_timeout.c index d82754e5575dc49b007adf787043d26e77ed4afa..80241e53f21d0fcfdb6259cb3678a54bfcf9bcd4 100644 --- a/examples/kernel/timer_timeout.c +++ b/examples/kernel/timer_timeout.c @@ -1,122 +1,122 @@ -/* - * ³ÌÐòÇåµ¥£ºÏûÏ¢¶ÓÁÐÀý³Ì - * - * Õâ¸ö³ÌÐò»á´´½¨3¸ö¶¯Ì¬Ị̈߳¬Ò»¸öÏ̻߳á´ÓÏûÏ¢¶ÓÁÐÖÐÊÕÈ¡ÏûÏ¢£»Ò»¸öÏ̻߳ᶨʱ¸øÏû - * Ï¢¶ÓÁз¢ËÍÏûÏ¢£»Ò»¸öÏ̻߳ᶨʱ¸øÏûÏ¢¶ÓÁз¢Ëͽô¼±ÏûÏ¢¡£ - */ -#include -#include "tc_comm.h" - -/* Ö¸ÏòÏ߳̿ØÖÆ¿éµÄÖ¸Õë */ -static rt_thread_t tid = RT_NULL; - -/* ÏûÏ¢¶ÓÁпØÖÆ¿é */ -static struct rt_messagequeue mq; -/* ÏûÏ¢¶ÓÁÐÖÐÓõ½µÄ·ÅÖÃÏûÏ¢µÄÄÚ´æ³Ø */ -static char msg_pool[2048]; - -/* ¶¨Ê±Æ÷µÄ¿ØÖÆ¿é */ -static struct rt_timer timer; -static rt_uint16_t no = 0; -static void timer_timeout(void* parameter) -{ - char buf[32]; - rt_uint32_t length; - - length = rt_snprintf(buf, sizeof(buf), "message %d", no++); - rt_mq_send(&mq, &buf[0], length); -} - -/* Ïß³ÌÈë¿Úº¯Êý */ -static void thread_entry(void* parameter) -{ - char buf[64]; - rt_err_t result; - - /* ³õʼ»¯¶¨Ê±Æ÷ */ - rt_timer_init(&timer, "timer", /* ¶¨Ê±Æ÷Ãû×ÖÊÇ timer1 */ - timer_timeout, /* ³¬Ê±Ê±»Øµ÷µÄ´¦Àíº¯Êý */ - RT_NULL, /* ³¬Ê±º¯ÊýµÄÈë¿Ú²ÎÊý */ - 1, /* ¶¨Ê±³¤¶È£¬ÒÔOS TickΪµ¥Î»£¬¼´1¸öOS Tick */ - RT_TIMER_FLAG_PERIODIC); /* ÖÜÆÚÐÔ¶¨Ê±Æ÷ */ - - while (1) - { - rt_memset(&buf[0], 0, sizeof(buf)); - - /* ´ÓÏûÏ¢¶ÓÁÐÖнÓÊÕÏûÏ¢ */ - result = rt_mq_recv(&mq, &buf[0], sizeof(buf), 1); - if (result == RT_EOK) - { - rt_kprintf("recv msg: %s\n", buf); - } - else if (result == -RT_ETIMEOUT) - { - rt_kprintf("recv msg timeout\n"); - } - } -} - -int timer_timeout_init() -{ - /* ³õʼ»¯ÏûÏ¢¶ÓÁÐ */ - rt_mq_init(&mq, "mqt", - &msg_pool[0], /* ÄÚ´æ³ØÖ¸Ïòmsg_pool */ - 128 - sizeof(void*), /* ÿ¸öÏûÏ¢µÄ´óСÊÇ 128 - void* */ - sizeof(msg_pool), /* ÄÚ´æ³ØµÄ´óСÊÇmsg_poolµÄ´óС */ - RT_IPC_FLAG_FIFO); /* Èç¹ûÓжà¸öÏ̵߳ȴý£¬°´ÕÕÏÈÀ´Ïȵõ½µÄ·½·¨·ÖÅäÏûÏ¢ */ - - /* ´´½¨Ïß³Ì */ - tid = rt_thread_create("t", - thread_entry, RT_NULL, /* Ïß³ÌÈë¿ÚÊÇthread_entry, Èë¿Ú²ÎÊýÊÇRT_NULL */ - THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); - if (tid != RT_NULL) - rt_thread_startup(tid); - else - tc_stat(TC_STAT_END | TC_STAT_FAILED); - - return 0; -} - -#ifdef RT_USING_TC -static void _tc_cleanup() -{ - /* µ÷¶ÈÆ÷ÉÏËø£¬ÉÏËøºó£¬½«²»ÔÙÇл»µ½ÆäËûỊ̈߳¬½öÏìÓ¦ÖÐ¶Ï */ - rt_enter_critical(); - - /* ɾ³ýÏß³Ì */ - if (tid != RT_NULL && tid->stat != RT_THREAD_CLOSE) - rt_thread_delete(tid); - - /* Ö´ÐÐÏûÏ¢¶ÓÁжÔÏóÍÑÀë */ - rt_mq_detach(&mq); - /* Ö´Ðж¨Ê±Æ÷ÍÑÀë */ - rt_timer_detach(&timer); - - /* µ÷¶ÈÆ÷½âËø */ - rt_exit_critical(); - - /* ÉèÖÃTestCase״̬ */ - tc_done(TC_STAT_PASSED); -} - -int _tc_timer_timeout() -{ - /* ÉèÖÃTestCaseÇåÀí»Øµ÷º¯Êý */ - tc_cleanup(_tc_cleanup); - timer_timeout_init(); - - /* ·µ»ØTestCaseÔËÐеÄ×ʱ¼ä */ - return 100; -} -/* Êä³öº¯ÊýÃüÁîµ½finsh shellÖÐ */ -FINSH_FUNCTION_EXPORT(_tc_timer_timeout, a thread timer testcase); -#else -/* Óû§Ó¦ÓÃÈë¿Ú */ -int rt_application_init() -{ - timer_timeout_init(); - - return 0; -} -#endif +/* + * ³ÌÐòÇåµ¥£ºÏûÏ¢¶ÓÁÐÀý³Ì + * + * Õâ¸ö³ÌÐò»á´´½¨3¸ö¶¯Ì¬Ị̈߳¬Ò»¸öÏ̻߳á´ÓÏûÏ¢¶ÓÁÐÖÐÊÕÈ¡ÏûÏ¢£»Ò»¸öÏ̻߳ᶨʱ¸øÏû + * Ï¢¶ÓÁз¢ËÍÏûÏ¢£»Ò»¸öÏ̻߳ᶨʱ¸øÏûÏ¢¶ÓÁз¢Ëͽô¼±ÏûÏ¢¡£ + */ +#include +#include "tc_comm.h" + +/* Ö¸ÏòÏ߳̿ØÖÆ¿éµÄÖ¸Õë */ +static rt_thread_t tid = RT_NULL; + +/* ÏûÏ¢¶ÓÁпØÖÆ¿é */ +static struct rt_messagequeue mq; +/* ÏûÏ¢¶ÓÁÐÖÐÓõ½µÄ·ÅÖÃÏûÏ¢µÄÄÚ´æ³Ø */ +static char msg_pool[2048]; + +/* ¶¨Ê±Æ÷µÄ¿ØÖÆ¿é */ +static struct rt_timer timer; +static rt_uint16_t no = 0; +static void timer_timeout(void* parameter) +{ + char buf[32]; + rt_uint32_t length; + + length = rt_snprintf(buf, sizeof(buf), "message %d", no++); + rt_mq_send(&mq, &buf[0], length); +} + +/* Ïß³ÌÈë¿Úº¯Êý */ +static void thread_entry(void* parameter) +{ + char buf[64]; + rt_err_t result; + + /* ³õʼ»¯¶¨Ê±Æ÷ */ + rt_timer_init(&timer, "timer", /* ¶¨Ê±Æ÷Ãû×ÖÊÇ timer1 */ + timer_timeout, /* ³¬Ê±Ê±»Øµ÷µÄ´¦Àíº¯Êý */ + RT_NULL, /* ³¬Ê±º¯ÊýµÄÈë¿Ú²ÎÊý */ + 1, /* ¶¨Ê±³¤¶È£¬ÒÔOS TickΪµ¥Î»£¬¼´1¸öOS Tick */ + RT_TIMER_FLAG_PERIODIC); /* ÖÜÆÚÐÔ¶¨Ê±Æ÷ */ + + while (1) + { + rt_memset(&buf[0], 0, sizeof(buf)); + + /* ´ÓÏûÏ¢¶ÓÁÐÖнÓÊÕÏûÏ¢ */ + result = rt_mq_recv(&mq, &buf[0], sizeof(buf), 1); + if (result == RT_EOK) + { + rt_kprintf("recv msg: %s\n", buf); + } + else if (result == -RT_ETIMEOUT) + { + rt_kprintf("recv msg timeout\n"); + } + } +} + +int timer_timeout_init() +{ + /* ³õʼ»¯ÏûÏ¢¶ÓÁÐ */ + rt_mq_init(&mq, "mqt", + &msg_pool[0], /* ÄÚ´æ³ØÖ¸Ïòmsg_pool */ + 128 - sizeof(void*), /* ÿ¸öÏûÏ¢µÄ´óСÊÇ 128 - void* */ + sizeof(msg_pool), /* ÄÚ´æ³ØµÄ´óСÊÇmsg_poolµÄ´óС */ + RT_IPC_FLAG_FIFO); /* Èç¹ûÓжà¸öÏ̵߳ȴý£¬°´ÕÕÏÈÀ´Ïȵõ½µÄ·½·¨·ÖÅäÏûÏ¢ */ + + /* ´´½¨Ïß³Ì */ + tid = rt_thread_create("t", + thread_entry, RT_NULL, /* Ïß³ÌÈë¿ÚÊÇthread_entry, Èë¿Ú²ÎÊýÊÇRT_NULL */ + THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE); + if (tid != RT_NULL) + rt_thread_startup(tid); + else + tc_stat(TC_STAT_END | TC_STAT_FAILED); + + return 0; +} + +#ifdef RT_USING_TC +static void _tc_cleanup() +{ + /* µ÷¶ÈÆ÷ÉÏËø£¬ÉÏËøºó£¬½«²»ÔÙÇл»µ½ÆäËûỊ̈߳¬½öÏìÓ¦ÖÐ¶Ï */ + rt_enter_critical(); + + /* ɾ³ýÏß³Ì */ + if (tid != RT_NULL && tid->stat != RT_THREAD_CLOSE) + rt_thread_delete(tid); + + /* Ö´ÐÐÏûÏ¢¶ÓÁжÔÏóÍÑÀë */ + rt_mq_detach(&mq); + /* Ö´Ðж¨Ê±Æ÷ÍÑÀë */ + rt_timer_detach(&timer); + + /* µ÷¶ÈÆ÷½âËø */ + rt_exit_critical(); + + /* ÉèÖÃTestCase״̬ */ + tc_done(TC_STAT_PASSED); +} + +int _tc_timer_timeout() +{ + /* ÉèÖÃTestCaseÇåÀí»Øµ÷º¯Êý */ + tc_cleanup(_tc_cleanup); + timer_timeout_init(); + + /* ·µ»ØTestCaseÔËÐеÄ×ʱ¼ä */ + return 100; +} +/* Êä³öº¯ÊýÃüÁîµ½finsh shellÖÐ */ +FINSH_FUNCTION_EXPORT(_tc_timer_timeout, a thread timer testcase); +#else +/* Óû§Ó¦ÓÃÈë¿Ú */ +int rt_application_init() +{ + timer_timeout_init(); + + return 0; +} +#endif diff --git a/examples/libc/SConscript b/examples/libc/SConscript index 60a48fd3765ebcca513a8a1c7beca262fdd59157..7801049c0745d74d3b8e5526cb33ca638cafa5a7 100644 --- a/examples/libc/SConscript +++ b/examples/libc/SConscript @@ -1,6 +1,6 @@ -from building import * - -src = Glob('*.c') -group = DefineGroup('libc_test', src, depend = ['RT_USING_NEWLIB', 'RT_USING_PTHREADS']) - -Return('group') +from building import * + +src = Glob('*.c') +group = DefineGroup('libc_test', src, depend = ['RT_USING_NEWLIB', 'RT_USING_PTHREADS']) + +Return('group') diff --git a/examples/libc/dirent.c b/examples/libc/dirent.c index a763ecb0227eb93bdf312d3aa10447d1aa4d9643..75604f6067b8c00c98e317bba10239f59510e514 100644 --- a/examples/libc/dirent.c +++ b/examples/libc/dirent.c @@ -1,56 +1,56 @@ -/* - * dirent.c - * - * Created on: 2010-11-17 - * Author: bernard - */ -#include -#include -#include - -#include -int libc_dirent() -{ - DIR * dirp; - long int save3 = 0; - long int cur; - int i = 0; - int result = 0; - struct dirent *dp; - - dirp = opendir("/"); - for (dp = readdir(dirp); dp != NULL; dp = readdir(dirp)) - { - /* save position 3 (after fourth entry) */ - if (i++ == 3) - save3 = telldir(dirp); - - printf("%s\n", dp->d_name); - - /* stop at 400 (just to make sure dirp->__offset and dirp->__size are - scrambled */ - if (i == 400) - break; - } - - printf("going back past 4-th entry...\n"); - - /* go back to saved entry */ - seekdir(dirp, save3); - - /* Check whether telldir equals to save3 now. */ - cur = telldir(dirp); - if (cur != save3) - { - printf("seekdir (d, %ld); telldir (d) == %ld\n", save3, cur); - result = 1; - } - - /* print remaining files (3-last) */ - for (dp = readdir(dirp); dp != NULL; dp = readdir(dirp)) - printf("%s\n", dp->d_name); - - closedir(dirp); - return result; -} -FINSH_FUNCTION_EXPORT(libc_dirent, dirent test for libc); +/* + * dirent.c + * + * Created on: 2010-11-17 + * Author: bernard + */ +#include +#include +#include + +#include +int libc_dirent() +{ + DIR * dirp; + long int save3 = 0; + long int cur; + int i = 0; + int result = 0; + struct dirent *dp; + + dirp = opendir("/"); + for (dp = readdir(dirp); dp != NULL; dp = readdir(dirp)) + { + /* save position 3 (after fourth entry) */ + if (i++ == 3) + save3 = telldir(dirp); + + printf("%s\n", dp->d_name); + + /* stop at 400 (just to make sure dirp->__offset and dirp->__size are + scrambled */ + if (i == 400) + break; + } + + printf("going back past 4-th entry...\n"); + + /* go back to saved entry */ + seekdir(dirp, save3); + + /* Check whether telldir equals to save3 now. */ + cur = telldir(dirp); + if (cur != save3) + { + printf("seekdir (d, %ld); telldir (d) == %ld\n", save3, cur); + result = 1; + } + + /* print remaining files (3-last) */ + for (dp = readdir(dirp); dp != NULL; dp = readdir(dirp)) + printf("%s\n", dp->d_name); + + closedir(dirp); + return result; +} +FINSH_FUNCTION_EXPORT(libc_dirent, dirent test for libc); diff --git a/examples/libc/env.c b/examples/libc/env.c index 56f906774f52939b3032f7a19d0d21ba573735cd..ca67ac2e2a2c0ab4e02a501a304817c42273a449 100644 --- a/examples/libc/env.c +++ b/examples/libc/env.c @@ -1,18 +1,18 @@ -/* - * env.c - * - * Created on: 2010-11-17 - * Author: bernard - */ -#include -#include -#include - -int libc_env() -{ - printf("PATH=%s\n", getenv("PATH")); - putenv("foo=bar"); - printf("foo=%s\n", getenv("foo")); - return 0; -} -FINSH_FUNCTION_EXPORT(libc_env, get/set_env test); +/* + * env.c + * + * Created on: 2010-11-17 + * Author: bernard + */ +#include +#include +#include + +int libc_env() +{ + printf("PATH=%s\n", getenv("PATH")); + putenv("foo=bar"); + printf("foo=%s\n", getenv("foo")); + return 0; +} +FINSH_FUNCTION_EXPORT(libc_env, get/set_env test); diff --git a/examples/libc/file.c b/examples/libc/file.c index 94aa206ce97633c57d90cf996317115d660d84b5..f366e047029a714fcc3b747a0c9e6dc84917adf4 100644 --- a/examples/libc/file.c +++ b/examples/libc/file.c @@ -1,516 +1,516 @@ -/* - * fstat.c - * - * Created on: 2010-11-17 - * Author: bernard - */ -#include -#include -#include -#include -#include -#include - -const char* text = "this is a test string\n"; -void libc_fstat() -{ - int fd; - struct stat s; - - fd = open("/tmp/tt.txt", O_WRONLY | O_CREAT, 0); - if (fd < 0) - { - printf("open failed\n"); - return; - } - - write(fd, text, strlen(text) + 1); - printf("begin: %d\n", lseek(fd, 0, SEEK_SET)); - printf("end: %d\n", lseek(fd, 0, SEEK_END)); - - printf("fstat result: %d\n", fstat(fd, &s)); - close(fd); -} -FINSH_FUNCTION_EXPORT(libc_fstat, fstat test for libc); - -void libc_lseek() -{ - int fd; - - fd = open("/tmp/tt.txt", O_WRONLY | O_CREAT, 0); - if (fd < 0) - { - printf("open failed\n"); - return; - } - - write(fd, text, strlen(text) + 1); - printf("begin: %d\n", lseek(fd, 0, SEEK_SET)); - printf("end: %d\n", lseek(fd, 0, SEEK_END)); - close(fd); -} -FINSH_FUNCTION_EXPORT(libc_lseek, lseek test for libc); - -void sleep(int tick) -{ - rt_thread_sleep(tick); -} - -int libc_fseek(void) -{ - const char *tmpdir; - char *fname; - int fd; - FILE *fp; - const char outstr[] = "hello world!\n"; - char strbuf[sizeof outstr]; - char buf[200]; - struct stat st1; - struct stat st2; - int result = 0; - - tmpdir = getenv("TMPDIR"); - if (tmpdir == NULL || tmpdir[0] == '\0') - tmpdir = "/tmp"; - - asprintf(&fname, "%s/tst-fseek.XXXXXX", tmpdir); - if (fname == NULL) - { - fprintf(stderr, "cannot generate name for temporary file: %s\n", - strerror(errno)); - return 1; - } - - /* Create a temporary file. */ - fd = mkstemp(fname); - if (fd == -1) - { - fprintf(stderr, "cannot open temporary file: %s\n", strerror(errno)); - return 1; - } - - fp = fdopen(fd, "w+"); - if (fp == NULL) - { - fprintf(stderr, "cannot get FILE for temporary file: %s\n", strerror( - errno)); - return 1; - } - setbuffer(fp, strbuf, sizeof(outstr) - 1); - - if (fwrite(outstr, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: write error\n", __LINE__); - result = 1; - goto out; - } - - /* The EOF flag must be reset. */ - if (fgetc(fp) != EOF) - { - printf("%d: managed to read at end of file\n", __LINE__); - result = 1; - } - else if (!feof(fp)) - { - printf("%d: EOF flag not set\n", __LINE__); - result = 1; - } - if (fseek(fp, 0, SEEK_CUR) != 0) - { - printf("%d: fseek(fp, 0, SEEK_CUR) failed\n", __LINE__); - result = 1; - } - else if (feof(fp)) - { - printf("%d: fseek() didn't reset EOF flag\n", __LINE__); - result = 1; - } - - /* Do the same for fseeko(). */ - if (fgetc(fp) != EOF) - { - printf("%d: managed to read at end of file\n", __LINE__); - result = 1; - } - else if (!feof(fp)) - { - printf("%d: EOF flag not set\n", __LINE__); - result = 1; - } - if (fseeko(fp, 0, SEEK_CUR) != 0) - { - printf("%d: fseek(fp, 0, SEEK_CUR) failed\n", __LINE__); - result = 1; - } - else if (feof(fp)) - { - printf("%d: fseek() didn't reset EOF flag\n", __LINE__); - result = 1; - } - - /* Go back to the beginning of the file: absolute. */ - if (fseek(fp, 0, SEEK_SET) != 0) - { - printf("%d: fseek(fp, 0, SEEK_SET) failed\n", __LINE__); - result = 1; - } - else if (fflush(fp) != 0) - { - printf("%d: fflush() failed\n", __LINE__); - result = 1; - } - else if (lseek(fd, 0, SEEK_CUR) != 0) - { - int pos = lseek(fd, 0, SEEK_CUR); - printf("%d: lseek() returned different position, pos %d\n", __LINE__, - pos); - result = 1; - } - else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: fread() failed\n", __LINE__); - result = 1; - } - else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) - { - printf("%d: content after fseek(,,SEEK_SET) wrong\n", __LINE__); - result = 1; - } - - /* Now with fseeko. */ - if (fseeko(fp, 0, SEEK_SET) != 0) - { - printf("%d: fseeko(fp, 0, SEEK_SET) failed\n", __LINE__); - result = 1; - } - else if (fflush(fp) != 0) - { - printf("%d: fflush() failed\n", __LINE__); - result = 1; - } - else if (lseek(fd, 0, SEEK_CUR) != 0) - { - printf("%d: lseek() returned different position\n", __LINE__); - result = 1; - } - else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: fread() failed\n", __LINE__); - result = 1; - } - else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) - { - printf("%d: content after fseeko(,,SEEK_SET) wrong\n", __LINE__); - result = 1; - } - - /* Go back to the beginning of the file: relative. */ - if (fseek(fp, -((int) sizeof(outstr) - 1), SEEK_CUR) != 0) - { - printf("%d: fseek(fp, 0, SEEK_SET) failed\n", __LINE__); - result = 1; - } - else if (fflush(fp) != 0) - { - printf("%d: fflush() failed\n", __LINE__); - result = 1; - } - else if (lseek(fd, 0, SEEK_CUR) != 0) - { - printf("%d: lseek() returned different position\n", __LINE__); - result = 1; - } - else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: fread() failed\n", __LINE__); - result = 1; - } - else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) - { - printf("%d: content after fseek(,,SEEK_SET) wrong\n", __LINE__); - result = 1; - } - - /* Now with fseeko. */ - if (fseeko(fp, -((int) sizeof(outstr) - 1), SEEK_CUR) != 0) - { - printf("%d: fseeko(fp, 0, SEEK_SET) failed\n", __LINE__); - result = 1; - } - else if (fflush(fp) != 0) - { - printf("%d: fflush() failed\n", __LINE__); - result = 1; - } - else if (lseek(fd, 0, SEEK_CUR) != 0) - { - printf("%d: lseek() returned different position\n", __LINE__); - result = 1; - } - else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: fread() failed\n", __LINE__); - result = 1; - } - else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) - { - printf("%d: content after fseeko(,,SEEK_SET) wrong\n", __LINE__); - result = 1; - } - - /* Go back to the beginning of the file: from the end. */ - if (fseek(fp, -((int) sizeof(outstr) - 1), SEEK_END) != 0) - { - printf("%d: fseek(fp, 0, SEEK_SET) failed\n", __LINE__); - result = 1; - } - else if (fflush(fp) != 0) - { - printf("%d: fflush() failed\n", __LINE__); - result = 1; - } - else if (lseek(fd, 0, SEEK_CUR) != 0) - { - printf("%d: lseek() returned different position\n", __LINE__); - result = 1; - } - else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: fread() failed\n", __LINE__); - result = 1; - } - else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) - { - printf("%d: content after fseek(,,SEEK_SET) wrong\n", __LINE__); - result = 1; - } - - /* Now with fseeko. */ - if (fseeko(fp, -((int) sizeof(outstr) - 1), SEEK_END) != 0) - { - printf("%d: fseeko(fp, 0, SEEK_SET) failed\n", __LINE__); - result = 1; - } - else if (fflush(fp) != 0) - { - printf("%d: fflush() failed\n", __LINE__); - result = 1; - } - else if (lseek(fd, 0, SEEK_CUR) != 0) - { - printf("%d: lseek() returned different position\n", __LINE__); - result = 1; - } - else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: fread() failed\n", __LINE__); - result = 1; - } - else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) - { - printf("%d: content after fseeko(,,SEEK_SET) wrong\n", __LINE__); - result = 1; - } - - if (fwrite(outstr, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: write error 2\n", __LINE__); - result = 1; - goto out; - } - - if (fwrite(outstr, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: write error 3\n", __LINE__); - result = 1; - goto out; - } - - if (fwrite(outstr, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: write error 4\n", __LINE__); - result = 1; - goto out; - } - - if (fwrite(outstr, sizeof(outstr) - 1, 1, fp) != 1) - { - printf("%d: write error 5\n", __LINE__); - result = 1; - goto out; - } - - if (fputc('1', fp) == EOF || fputc('2', fp) == EOF) - { - printf("%d: cannot add characters at the end\n", __LINE__); - result = 1; - goto out; - } - - /* Check the access time. */ - if (fstat(fd, &st1) < 0) - { - printf("%d: fstat64() before fseeko() failed\n\n", __LINE__); - result = 1; - } - else - { - sleep(1); - - if (fseek(fp, -(2 + 2 * (sizeof(outstr) - 1)), SEEK_CUR) != 0) - { - printf("%d: fseek() after write characters failed\n", __LINE__); - result = 1; - goto out; - } - else - { - - time_t t; - /* Make sure the timestamp actually can be different. */ - sleep(1); - t = time(NULL); - - if (fstat(fd, &st2) < 0) - { - printf("%d: fstat64() after fseeko() failed\n\n", __LINE__); - result = 1; - } - if (st1.st_ctime >= t) - { - printf("%d: st_ctime not updated\n", __LINE__); - result = 1; - } - if (st1.st_mtime >= t) - { - printf("%d: st_mtime not updated\n", __LINE__); - result = 1; - } - if (st1.st_ctime >= st2.st_ctime) - { - printf("%d: st_ctime not changed\n", __LINE__); - result = 1; - } - if (st1.st_mtime >= st2.st_mtime) - { - printf("%d: st_mtime not changed\n", __LINE__); - result = 1; - } - } - } - - if (fread(buf, 1, 2 + 2 * (sizeof(outstr) - 1), fp) != 2 + 2 - * (sizeof(outstr) - 1)) - { - printf("%d: reading 2 records plus bits failed\n", __LINE__); - result = 1; - } - else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0 || memcmp( - &buf[sizeof(outstr) - 1], outstr, sizeof(outstr) - 1) != 0 || buf[2 - * (sizeof(outstr) - 1)] != '1' || buf[2 * (sizeof(outstr) - 1) + 1] - != '2') - { - printf("%d: reading records failed\n", __LINE__); - result = 1; - } - else if (ungetc('9', fp) == EOF) - { - printf("%d: ungetc() failed\n", __LINE__); - result = 1; - } - else if (fseek(fp, -(2 + 2 * (sizeof(outstr) - 1)), SEEK_END) != 0) - { - printf("%d: fseek after ungetc failed\n", __LINE__); - result = 1; - } - else if (fread(buf, 1, 2 + 2 * (sizeof(outstr) - 1), fp) != 2 + 2 - * (sizeof(outstr) - 1)) - { - printf("%d: reading 2 records plus bits failed\n", __LINE__); - result = 1; - } - else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0 || memcmp( - &buf[sizeof(outstr) - 1], outstr, sizeof(outstr) - 1) != 0 || buf[2 - * (sizeof(outstr) - 1)] != '1') - { - printf("%d: reading records for the second time failed\n", __LINE__); - result = 1; - } - else if (buf[2 * (sizeof(outstr) - 1) + 1] == '9') - { - printf("%d: unget character not ignored\n", __LINE__); - result = 1; - } - else if (buf[2 * (sizeof(outstr) - 1) + 1] != '2') - { - printf("%d: unget somehow changed character\n", __LINE__); - result = 1; - } - - fclose(fp); - - fp = fopen(fname, "r"); - if (fp == NULL) - { - printf("%d: fopen() failed\n\n", __LINE__); - result = 1; - } - else if (fstat(fileno(fp), &st1) < 0) - { - printf("%d: fstat64() before fseeko() failed\n\n", __LINE__); - result = 1; - } - else if (fseeko(fp, 0, SEEK_END) != 0) - { - printf("%d: fseeko(fp, 0, SEEK_END) failed\n", __LINE__); - result = 1; - } - else if (ftello(fp) != st1.st_size) - { - printf("%d: fstat64 st_size %zd ftello %zd\n", __LINE__, - (size_t) st1.st_size, (size_t) ftello(fp)); - result = 1; - } - else - printf("%d: SEEK_END works\n", __LINE__); - if (fp != NULL) - fclose(fp); - - fp = fopen(fname, "r"); - if (fp == NULL) - { - printf("%d: fopen() failed\n\n", __LINE__); - result = 1; - } - else if (fstat(fileno(fp), &st1) < 0) - { - printf("%d: fstat64() before fgetc() failed\n\n", __LINE__); - result = 1; - } - else if (fgetc(fp) == EOF) - { - printf("%d: fgetc() before fseeko() failed\n\n", __LINE__); - result = 1; - } - else if (fseeko(fp, 0, SEEK_END) != 0) - { - printf("%d: fseeko(fp, 0, SEEK_END) failed\n", __LINE__); - result = 1; - } - else if (ftello(fp) != st1.st_size) - { - printf("%d: fstat64 st_size %zd ftello %zd\n", __LINE__, - (size_t) st1.st_size, (size_t) ftello(fp)); - result = 1; - } - else - printf("%d: SEEK_END works\n", __LINE__); - if (fp != NULL) - fclose(fp); - - out: unlink(fname); - - return result; -} -FINSH_FUNCTION_EXPORT(libc_fseek, lseek test for libc); +/* + * fstat.c + * + * Created on: 2010-11-17 + * Author: bernard + */ +#include +#include +#include +#include +#include +#include + +const char* text = "this is a test string\n"; +void libc_fstat() +{ + int fd; + struct stat s; + + fd = open("/tmp/tt.txt", O_WRONLY | O_CREAT, 0); + if (fd < 0) + { + printf("open failed\n"); + return; + } + + write(fd, text, strlen(text) + 1); + printf("begin: %d\n", lseek(fd, 0, SEEK_SET)); + printf("end: %d\n", lseek(fd, 0, SEEK_END)); + + printf("fstat result: %d\n", fstat(fd, &s)); + close(fd); +} +FINSH_FUNCTION_EXPORT(libc_fstat, fstat test for libc); + +void libc_lseek() +{ + int fd; + + fd = open("/tmp/tt.txt", O_WRONLY | O_CREAT, 0); + if (fd < 0) + { + printf("open failed\n"); + return; + } + + write(fd, text, strlen(text) + 1); + printf("begin: %d\n", lseek(fd, 0, SEEK_SET)); + printf("end: %d\n", lseek(fd, 0, SEEK_END)); + close(fd); +} +FINSH_FUNCTION_EXPORT(libc_lseek, lseek test for libc); + +void sleep(int tick) +{ + rt_thread_sleep(tick); +} + +int libc_fseek(void) +{ + const char *tmpdir; + char *fname; + int fd; + FILE *fp; + const char outstr[] = "hello world!\n"; + char strbuf[sizeof outstr]; + char buf[200]; + struct stat st1; + struct stat st2; + int result = 0; + + tmpdir = getenv("TMPDIR"); + if (tmpdir == NULL || tmpdir[0] == '\0') + tmpdir = "/tmp"; + + asprintf(&fname, "%s/tst-fseek.XXXXXX", tmpdir); + if (fname == NULL) + { + fprintf(stderr, "cannot generate name for temporary file: %s\n", + strerror(errno)); + return 1; + } + + /* Create a temporary file. */ + fd = mkstemp(fname); + if (fd == -1) + { + fprintf(stderr, "cannot open temporary file: %s\n", strerror(errno)); + return 1; + } + + fp = fdopen(fd, "w+"); + if (fp == NULL) + { + fprintf(stderr, "cannot get FILE for temporary file: %s\n", strerror( + errno)); + return 1; + } + setbuffer(fp, strbuf, sizeof(outstr) - 1); + + if (fwrite(outstr, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: write error\n", __LINE__); + result = 1; + goto out; + } + + /* The EOF flag must be reset. */ + if (fgetc(fp) != EOF) + { + printf("%d: managed to read at end of file\n", __LINE__); + result = 1; + } + else if (!feof(fp)) + { + printf("%d: EOF flag not set\n", __LINE__); + result = 1; + } + if (fseek(fp, 0, SEEK_CUR) != 0) + { + printf("%d: fseek(fp, 0, SEEK_CUR) failed\n", __LINE__); + result = 1; + } + else if (feof(fp)) + { + printf("%d: fseek() didn't reset EOF flag\n", __LINE__); + result = 1; + } + + /* Do the same for fseeko(). */ + if (fgetc(fp) != EOF) + { + printf("%d: managed to read at end of file\n", __LINE__); + result = 1; + } + else if (!feof(fp)) + { + printf("%d: EOF flag not set\n", __LINE__); + result = 1; + } + if (fseeko(fp, 0, SEEK_CUR) != 0) + { + printf("%d: fseek(fp, 0, SEEK_CUR) failed\n", __LINE__); + result = 1; + } + else if (feof(fp)) + { + printf("%d: fseek() didn't reset EOF flag\n", __LINE__); + result = 1; + } + + /* Go back to the beginning of the file: absolute. */ + if (fseek(fp, 0, SEEK_SET) != 0) + { + printf("%d: fseek(fp, 0, SEEK_SET) failed\n", __LINE__); + result = 1; + } + else if (fflush(fp) != 0) + { + printf("%d: fflush() failed\n", __LINE__); + result = 1; + } + else if (lseek(fd, 0, SEEK_CUR) != 0) + { + int pos = lseek(fd, 0, SEEK_CUR); + printf("%d: lseek() returned different position, pos %d\n", __LINE__, + pos); + result = 1; + } + else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: fread() failed\n", __LINE__); + result = 1; + } + else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) + { + printf("%d: content after fseek(,,SEEK_SET) wrong\n", __LINE__); + result = 1; + } + + /* Now with fseeko. */ + if (fseeko(fp, 0, SEEK_SET) != 0) + { + printf("%d: fseeko(fp, 0, SEEK_SET) failed\n", __LINE__); + result = 1; + } + else if (fflush(fp) != 0) + { + printf("%d: fflush() failed\n", __LINE__); + result = 1; + } + else if (lseek(fd, 0, SEEK_CUR) != 0) + { + printf("%d: lseek() returned different position\n", __LINE__); + result = 1; + } + else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: fread() failed\n", __LINE__); + result = 1; + } + else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) + { + printf("%d: content after fseeko(,,SEEK_SET) wrong\n", __LINE__); + result = 1; + } + + /* Go back to the beginning of the file: relative. */ + if (fseek(fp, -((int) sizeof(outstr) - 1), SEEK_CUR) != 0) + { + printf("%d: fseek(fp, 0, SEEK_SET) failed\n", __LINE__); + result = 1; + } + else if (fflush(fp) != 0) + { + printf("%d: fflush() failed\n", __LINE__); + result = 1; + } + else if (lseek(fd, 0, SEEK_CUR) != 0) + { + printf("%d: lseek() returned different position\n", __LINE__); + result = 1; + } + else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: fread() failed\n", __LINE__); + result = 1; + } + else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) + { + printf("%d: content after fseek(,,SEEK_SET) wrong\n", __LINE__); + result = 1; + } + + /* Now with fseeko. */ + if (fseeko(fp, -((int) sizeof(outstr) - 1), SEEK_CUR) != 0) + { + printf("%d: fseeko(fp, 0, SEEK_SET) failed\n", __LINE__); + result = 1; + } + else if (fflush(fp) != 0) + { + printf("%d: fflush() failed\n", __LINE__); + result = 1; + } + else if (lseek(fd, 0, SEEK_CUR) != 0) + { + printf("%d: lseek() returned different position\n", __LINE__); + result = 1; + } + else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: fread() failed\n", __LINE__); + result = 1; + } + else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) + { + printf("%d: content after fseeko(,,SEEK_SET) wrong\n", __LINE__); + result = 1; + } + + /* Go back to the beginning of the file: from the end. */ + if (fseek(fp, -((int) sizeof(outstr) - 1), SEEK_END) != 0) + { + printf("%d: fseek(fp, 0, SEEK_SET) failed\n", __LINE__); + result = 1; + } + else if (fflush(fp) != 0) + { + printf("%d: fflush() failed\n", __LINE__); + result = 1; + } + else if (lseek(fd, 0, SEEK_CUR) != 0) + { + printf("%d: lseek() returned different position\n", __LINE__); + result = 1; + } + else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: fread() failed\n", __LINE__); + result = 1; + } + else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) + { + printf("%d: content after fseek(,,SEEK_SET) wrong\n", __LINE__); + result = 1; + } + + /* Now with fseeko. */ + if (fseeko(fp, -((int) sizeof(outstr) - 1), SEEK_END) != 0) + { + printf("%d: fseeko(fp, 0, SEEK_SET) failed\n", __LINE__); + result = 1; + } + else if (fflush(fp) != 0) + { + printf("%d: fflush() failed\n", __LINE__); + result = 1; + } + else if (lseek(fd, 0, SEEK_CUR) != 0) + { + printf("%d: lseek() returned different position\n", __LINE__); + result = 1; + } + else if (fread(buf, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: fread() failed\n", __LINE__); + result = 1; + } + else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0) + { + printf("%d: content after fseeko(,,SEEK_SET) wrong\n", __LINE__); + result = 1; + } + + if (fwrite(outstr, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: write error 2\n", __LINE__); + result = 1; + goto out; + } + + if (fwrite(outstr, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: write error 3\n", __LINE__); + result = 1; + goto out; + } + + if (fwrite(outstr, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: write error 4\n", __LINE__); + result = 1; + goto out; + } + + if (fwrite(outstr, sizeof(outstr) - 1, 1, fp) != 1) + { + printf("%d: write error 5\n", __LINE__); + result = 1; + goto out; + } + + if (fputc('1', fp) == EOF || fputc('2', fp) == EOF) + { + printf("%d: cannot add characters at the end\n", __LINE__); + result = 1; + goto out; + } + + /* Check the access time. */ + if (fstat(fd, &st1) < 0) + { + printf("%d: fstat64() before fseeko() failed\n\n", __LINE__); + result = 1; + } + else + { + sleep(1); + + if (fseek(fp, -(2 + 2 * (sizeof(outstr) - 1)), SEEK_CUR) != 0) + { + printf("%d: fseek() after write characters failed\n", __LINE__); + result = 1; + goto out; + } + else + { + + time_t t; + /* Make sure the timestamp actually can be different. */ + sleep(1); + t = time(NULL); + + if (fstat(fd, &st2) < 0) + { + printf("%d: fstat64() after fseeko() failed\n\n", __LINE__); + result = 1; + } + if (st1.st_ctime >= t) + { + printf("%d: st_ctime not updated\n", __LINE__); + result = 1; + } + if (st1.st_mtime >= t) + { + printf("%d: st_mtime not updated\n", __LINE__); + result = 1; + } + if (st1.st_ctime >= st2.st_ctime) + { + printf("%d: st_ctime not changed\n", __LINE__); + result = 1; + } + if (st1.st_mtime >= st2.st_mtime) + { + printf("%d: st_mtime not changed\n", __LINE__); + result = 1; + } + } + } + + if (fread(buf, 1, 2 + 2 * (sizeof(outstr) - 1), fp) != 2 + 2 + * (sizeof(outstr) - 1)) + { + printf("%d: reading 2 records plus bits failed\n", __LINE__); + result = 1; + } + else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0 || memcmp( + &buf[sizeof(outstr) - 1], outstr, sizeof(outstr) - 1) != 0 || buf[2 + * (sizeof(outstr) - 1)] != '1' || buf[2 * (sizeof(outstr) - 1) + 1] + != '2') + { + printf("%d: reading records failed\n", __LINE__); + result = 1; + } + else if (ungetc('9', fp) == EOF) + { + printf("%d: ungetc() failed\n", __LINE__); + result = 1; + } + else if (fseek(fp, -(2 + 2 * (sizeof(outstr) - 1)), SEEK_END) != 0) + { + printf("%d: fseek after ungetc failed\n", __LINE__); + result = 1; + } + else if (fread(buf, 1, 2 + 2 * (sizeof(outstr) - 1), fp) != 2 + 2 + * (sizeof(outstr) - 1)) + { + printf("%d: reading 2 records plus bits failed\n", __LINE__); + result = 1; + } + else if (memcmp(buf, outstr, sizeof(outstr) - 1) != 0 || memcmp( + &buf[sizeof(outstr) - 1], outstr, sizeof(outstr) - 1) != 0 || buf[2 + * (sizeof(outstr) - 1)] != '1') + { + printf("%d: reading records for the second time failed\n", __LINE__); + result = 1; + } + else if (buf[2 * (sizeof(outstr) - 1) + 1] == '9') + { + printf("%d: unget character not ignored\n", __LINE__); + result = 1; + } + else if (buf[2 * (sizeof(outstr) - 1) + 1] != '2') + { + printf("%d: unget somehow changed character\n", __LINE__); + result = 1; + } + + fclose(fp); + + fp = fopen(fname, "r"); + if (fp == NULL) + { + printf("%d: fopen() failed\n\n", __LINE__); + result = 1; + } + else if (fstat(fileno(fp), &st1) < 0) + { + printf("%d: fstat64() before fseeko() failed\n\n", __LINE__); + result = 1; + } + else if (fseeko(fp, 0, SEEK_END) != 0) + { + printf("%d: fseeko(fp, 0, SEEK_END) failed\n", __LINE__); + result = 1; + } + else if (ftello(fp) != st1.st_size) + { + printf("%d: fstat64 st_size %zd ftello %zd\n", __LINE__, + (size_t) st1.st_size, (size_t) ftello(fp)); + result = 1; + } + else + printf("%d: SEEK_END works\n", __LINE__); + if (fp != NULL) + fclose(fp); + + fp = fopen(fname, "r"); + if (fp == NULL) + { + printf("%d: fopen() failed\n\n", __LINE__); + result = 1; + } + else if (fstat(fileno(fp), &st1) < 0) + { + printf("%d: fstat64() before fgetc() failed\n\n", __LINE__); + result = 1; + } + else if (fgetc(fp) == EOF) + { + printf("%d: fgetc() before fseeko() failed\n\n", __LINE__); + result = 1; + } + else if (fseeko(fp, 0, SEEK_END) != 0) + { + printf("%d: fseeko(fp, 0, SEEK_END) failed\n", __LINE__); + result = 1; + } + else if (ftello(fp) != st1.st_size) + { + printf("%d: fstat64 st_size %zd ftello %zd\n", __LINE__, + (size_t) st1.st_size, (size_t) ftello(fp)); + result = 1; + } + else + printf("%d: SEEK_END works\n", __LINE__); + if (fp != NULL) + fclose(fp); + + out: unlink(fname); + + return result; +} +FINSH_FUNCTION_EXPORT(libc_fseek, lseek test for libc); diff --git a/examples/libc/memory.c b/examples/libc/memory.c index 81b566f6468b3c4585d8b1071ad33ce4b3a82bd7..ee524fa43de08cea70179aeeb0c4a8fc964fa2a5 100644 --- a/examples/libc/memory.c +++ b/examples/libc/memory.c @@ -1,56 +1,56 @@ -/* - * memory.c - * - * Created on: 2010-11-17 - * Author: bernard - */ -#include -#include -#include -#include - -static int errors = 0; -static void merror(const char *msg) -{ - ++errors; - printf("Error: %s\n", msg); -} - -int libc_mem(void) -{ - void *p; - int save; - - errno = 0; - - p = malloc(-1); - save = errno; - - if (p != NULL) - merror("malloc (-1) succeeded."); - - if (p == NULL && save != ENOMEM) - merror("errno is not set correctly"); - - p = malloc(10); - if (p == NULL) - merror("malloc (10) failed."); - - /* realloc (p, 0) == free (p). */ - p = realloc(p, 0); - if (p != NULL) - merror("realloc (p, 0) failed."); - - p = malloc(0); - if (p == NULL) - { - printf("malloc(0) returns NULL\n"); - } - - p = realloc(p, 0); - if (p != NULL) - merror("realloc (p, 0) failed."); - - return errors != 0; -} -FINSH_FUNCTION_EXPORT(libc_mem, memory test for libc); +/* + * memory.c + * + * Created on: 2010-11-17 + * Author: bernard + */ +#include +#include +#include +#include + +static int errors = 0; +static void merror(const char *msg) +{ + ++errors; + printf("Error: %s\n", msg); +} + +int libc_mem(void) +{ + void *p; + int save; + + errno = 0; + + p = malloc(-1); + save = errno; + + if (p != NULL) + merror("malloc (-1) succeeded."); + + if (p == NULL && save != ENOMEM) + merror("errno is not set correctly"); + + p = malloc(10); + if (p == NULL) + merror("malloc (10) failed."); + + /* realloc (p, 0) == free (p). */ + p = realloc(p, 0); + if (p != NULL) + merror("realloc (p, 0) failed."); + + p = malloc(0); + if (p == NULL) + { + printf("malloc(0) returns NULL\n"); + } + + p = realloc(p, 0); + if (p != NULL) + merror("realloc (p, 0) failed."); + + return errors != 0; +} +FINSH_FUNCTION_EXPORT(libc_mem, memory test for libc); diff --git a/examples/libc/mq.c b/examples/libc/mq.c index 6f9b1c6e59618c41db81292958331369df0b4322..3163e27975945b97353716099e109456726bf369 100644 --- a/examples/libc/mq.c +++ b/examples/libc/mq.c @@ -1,119 +1,119 @@ -#include -#include -#include -#include -#include -#include - -#define MQ_NAME_1 "testmsg1" -#define MQ_NAME_2 "testmsg2" -#define MSG_SIZE 128 -#define MAX_MSG 3 - -const char *s_msg_ptr[] = {"msg test 1", "msg test 2", "msg test 3"}; -char r_msg_ptr_1[MAX_MSG][MSG_SIZE]; -char r_msg_ptr_2[MAX_MSG][MSG_SIZE]; -pthread_t send1, send2, rev1, rev2; - -int * send_1(void * mq) -{ - int i; - mqd_t mq1 = *(mqd_t *)mq; - - printf("Enter into send_1 \n"); - for (i = 0; i < MAX_MSG; i++ ) { - if ( -1 == mq_send(mq1, s_msg_ptr[i], MSG_SIZE, i)) { - perror("mq_send doesn't return success \n"); - pthread_exit((void *)1); - } - printf("[%d] send '%s' in thread send_1. \n", i+1, s_msg_ptr[i]); - } - pthread_exit((void *)0); - -} - -int * send_2(void * mq) -{ - int i; - mqd_t mq2 = *(mqd_t *)mq; - - printf("Enter into send_2 \n"); - for (i = 0; i < MAX_MSG; i++ ) { - if ( -1 == mq_send(mq2, s_msg_ptr[i], MSG_SIZE, i)) { - perror("mq_send doesn't return success \n"); - pthread_exit((void *)1); - } - printf("[%d] send '%s' in thread send_2. \n", i+1, s_msg_ptr[i]); - } - pthread_exit((void *)0); -} - -int * receive_1(void * mq) -{ - int i; - mqd_t mq1 = *(mqd_t *)mq; - - printf("Enter into receive_1 \n"); - for (i = 0; i< MAX_MSG; i++) { - if ( -1 == mq_receive(mq1, r_msg_ptr_1[i], MSG_SIZE, NULL) ) { - perror("mq_receive doesn't return success \n"); - pthread_exit((void *)1); - } - printf("[%d] receive '%s' in thread receive_1. \n", i+1, r_msg_ptr_1[i]); - } - pthread_exit((void *)0); -} -int * receive_2(void * mq) -{ - int i; - mqd_t mq2 = *(mqd_t *)mq; - - printf("Enter into receive_2 \n"); - for (i = 0; i< MAX_MSG; i++) { - if ( -1 == mq_receive(mq2, r_msg_ptr_2[i], MSG_SIZE, NULL) ) { - perror("mq_receive doesn't return success \n"); - pthread_exit((void *)1); - } - printf("[%d] receive '%s' in thread receive_2. \n", i+1, r_msg_ptr_2[i]); - } - pthread_exit((void *)0); -} - -int libc_mq() -{ - mqd_t mq1 = 0, mq2 = 0; - struct mq_attr mqstat; - int oflag = O_CREAT|O_RDWR; - - memset(&mqstat, 0, sizeof(mqstat)); - mqstat.mq_maxmsg = MAX_MSG; - mqstat.mq_msgsize = MSG_SIZE; - mqstat.mq_flags = 0; - - if( ((mqd_t) -1) == (mq1 = mq_open(MQ_NAME_1,oflag,0777, &mqstat)) ) { - printf("mq_open doesn't return success \n"); - return -1; - } - if( ((mqd_t) -1) == (mq2 = mq_open(MQ_NAME_2,oflag,0777, &mqstat)) ) { - printf("mq_open doesn't return success \n"); - return -1; - } - pthread_create(&send1, NULL, (void *)send_1, (void *)&mq1); - pthread_create(&send2, NULL, (void *)send_2, (void *)&mq2); - pthread_create(&rev1, NULL, (void *)receive_1, (void *)&mq1); - pthread_create(&rev2, NULL, (void *)receive_2, (void *)&mq2); - pthread_join(send1, NULL); - pthread_join(send2, NULL); - pthread_join(rev1, NULL); - pthread_join(rev2, NULL); - - mq_close(mq1); - mq_close(mq2); - mq_unlink(MQ_NAME_1); - mq_unlink(MQ_NAME_2); - - printf("PASSED\n"); - return 0; -} -#include -FINSH_FUNCTION_EXPORT(libc_mq, posix mqueue test); +#include +#include +#include +#include +#include +#include + +#define MQ_NAME_1 "testmsg1" +#define MQ_NAME_2 "testmsg2" +#define MSG_SIZE 128 +#define MAX_MSG 3 + +const char *s_msg_ptr[] = {"msg test 1", "msg test 2", "msg test 3"}; +char r_msg_ptr_1[MAX_MSG][MSG_SIZE]; +char r_msg_ptr_2[MAX_MSG][MSG_SIZE]; +pthread_t send1, send2, rev1, rev2; + +int * send_1(void * mq) +{ + int i; + mqd_t mq1 = *(mqd_t *)mq; + + printf("Enter into send_1 \n"); + for (i = 0; i < MAX_MSG; i++ ) { + if ( -1 == mq_send(mq1, s_msg_ptr[i], MSG_SIZE, i)) { + perror("mq_send doesn't return success \n"); + pthread_exit((void *)1); + } + printf("[%d] send '%s' in thread send_1. \n", i+1, s_msg_ptr[i]); + } + pthread_exit((void *)0); + +} + +int * send_2(void * mq) +{ + int i; + mqd_t mq2 = *(mqd_t *)mq; + + printf("Enter into send_2 \n"); + for (i = 0; i < MAX_MSG; i++ ) { + if ( -1 == mq_send(mq2, s_msg_ptr[i], MSG_SIZE, i)) { + perror("mq_send doesn't return success \n"); + pthread_exit((void *)1); + } + printf("[%d] send '%s' in thread send_2. \n", i+1, s_msg_ptr[i]); + } + pthread_exit((void *)0); +} + +int * receive_1(void * mq) +{ + int i; + mqd_t mq1 = *(mqd_t *)mq; + + printf("Enter into receive_1 \n"); + for (i = 0; i< MAX_MSG; i++) { + if ( -1 == mq_receive(mq1, r_msg_ptr_1[i], MSG_SIZE, NULL) ) { + perror("mq_receive doesn't return success \n"); + pthread_exit((void *)1); + } + printf("[%d] receive '%s' in thread receive_1. \n", i+1, r_msg_ptr_1[i]); + } + pthread_exit((void *)0); +} +int * receive_2(void * mq) +{ + int i; + mqd_t mq2 = *(mqd_t *)mq; + + printf("Enter into receive_2 \n"); + for (i = 0; i< MAX_MSG; i++) { + if ( -1 == mq_receive(mq2, r_msg_ptr_2[i], MSG_SIZE, NULL) ) { + perror("mq_receive doesn't return success \n"); + pthread_exit((void *)1); + } + printf("[%d] receive '%s' in thread receive_2. \n", i+1, r_msg_ptr_2[i]); + } + pthread_exit((void *)0); +} + +int libc_mq() +{ + mqd_t mq1 = 0, mq2 = 0; + struct mq_attr mqstat; + int oflag = O_CREAT|O_RDWR; + + memset(&mqstat, 0, sizeof(mqstat)); + mqstat.mq_maxmsg = MAX_MSG; + mqstat.mq_msgsize = MSG_SIZE; + mqstat.mq_flags = 0; + + if( ((mqd_t) -1) == (mq1 = mq_open(MQ_NAME_1,oflag,0777, &mqstat)) ) { + printf("mq_open doesn't return success \n"); + return -1; + } + if( ((mqd_t) -1) == (mq2 = mq_open(MQ_NAME_2,oflag,0777, &mqstat)) ) { + printf("mq_open doesn't return success \n"); + return -1; + } + pthread_create(&send1, NULL, (void *)send_1, (void *)&mq1); + pthread_create(&send2, NULL, (void *)send_2, (void *)&mq2); + pthread_create(&rev1, NULL, (void *)receive_1, (void *)&mq1); + pthread_create(&rev2, NULL, (void *)receive_2, (void *)&mq2); + pthread_join(send1, NULL); + pthread_join(send2, NULL); + pthread_join(rev1, NULL); + pthread_join(rev2, NULL); + + mq_close(mq1); + mq_close(mq2); + mq_unlink(MQ_NAME_1); + mq_unlink(MQ_NAME_2); + + printf("PASSED\n"); + return 0; +} +#include +FINSH_FUNCTION_EXPORT(libc_mq, posix mqueue test); diff --git a/examples/libc/printf.c b/examples/libc/printf.c index 12435731b70a31bf6d13f87826b8559a99e48ef2..2d2d8a7763adb6721391f3f5e5e0c1b350589fe0 100644 --- a/examples/libc/printf.c +++ b/examples/libc/printf.c @@ -1,200 +1,200 @@ -#include -#include -#include - -#include - -char * format[] = { - "%", - "%0.", - "%.0", - "%+0.", - "%+.0", - "%.5", - "%+.5", - "%2.5", - "%22.5", - "%022.5", - "%#022.5", - "%-#022.5", - "%+#022.5", - "%-22.5", - "%+22.5", - "%--22.5", - "%++22.5", - "%+-22.5", - "%-+22.5", - "%-#022.5", - "%-#22.5", - "%-2.22", - "%+2.22", - "%-#02.22", - "%-#2.22", - "%-1.5", - "%1.5", - "%-#01.5", - "%-#1.5", - "%-#.5", - "%-#1.", - "%-#.", - NULL -}; - - -static void -intchk (const char *fmt) -{ - (void) printf("%15s :, \"", fmt); - (void) printf(fmt, 0); - (void) printf("\", \""); - (void) printf(fmt, 123); - (void) printf("\", \""); - (void) printf(fmt, -18); - (void) printf("\"\n"); -} - -static void -fltchk (const char *fmt) -{ - (void) printf("%15s :, \"", fmt); - (void) printf(fmt, 0.0); - (void) printf("\", \""); - (void) printf(fmt, 123.0001); - (void) printf("\", \""); - (void) printf(fmt, -18.0002301); - (void) printf("\"\n"); -} - - -int printf_test() -{ - char buf[256]; - int i; - - printf("%s\n\n", "# vim:syntax=off:"); - - /* integers */ - for(i=0;format[i];i++) { - strcpy(buf, format[i]); - strcat(buf, "d"); - intchk(buf); - } - - /* floats */ - for(i=0;format[i];i++) { - strcpy(buf, format[i]); - strcat(buf, "f"); - fltchk(buf); - } - /* hexa */ - for(i=0;format[i];i++) { - strcpy(buf, format[i]); - strcat(buf, "x"); - intchk(buf); - } - - printf("#%.4x %4x#\n", 4, 88); - printf("#%4x#\n",4); - printf("#%#22.8x#\n",1234567); - - printf("#%+2i#\n",18); - printf("#%i#\n",18); - printf("#%llu#\n",4294967297ULL); - printf("#%#x#\n",44444); - printf("#%-8i#\n",33); - printf("#%i#\n",18); - printf("#%d#\n",18); - printf("#%u#\n",18); - printf("#%lu#\n",18); - printf("#%li#\n",18); - printf("#%-+#06d#\n", -123); - printf("#%-+#6d#\n", -123); - printf("#%+#06d#\n", -123); - printf("#%06d#\n", -123); - printf("#%+15s#\n","ABCDEF"); - /* from ncurses make_keys */ - printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 16, 16, "KEY_A1", "key_a1"); - printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 16, 2, "KEY_A1", "key_a1"); - printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 2, 16, "KEY_A1", "key_a1"); - printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 16, 0, "KEY_A1", "key_a1"); - printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 0, 16, "KEY_A1", "key_a1"); - printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 0, 0, "KEY_A1", "key_a1"); - printf("{ %4d, %*.*s },\t/* %s */\n", 139, 16, 16, "KEY_A1", "key_a1"); - printf("{ %4d, %*.*s },\t/* %s */\n", 139, 16, 2, "KEY_A1", "key_a1"); - printf("{ %4d, %*.*s },\t/* %s */\n", 139, 2, 16, "KEY_A1", "key_a1"); - printf("{ %4d, %*.*s },\t/* %s */\n", 139, 16, 0, "KEY_A1", "key_a1"); - printf("{ %4d, %*.*s },\t/* %s */\n", 139, 0, 16, "KEY_A1", "key_a1"); - printf("{ %4d, %*.*s },\t/* %s */\n", 139, 0, 0, "KEY_A1", "key_a1"); - printf("%*.*f\n", 0, 16, 0.0); - printf("%*.*f\n", 16, 16, 0.0); - printf("%*.*f\n", 2, 2, -0.0); - printf("%*.*f\n", 20, 0, -123.123); - printf("%*.*f\n", 10, 0, +123.123); - - - i = printf("\"%s\"\n","A"); - printf("%i\n", i); - /* from glibc's tst-printf.c */ - - { - char buf[20]; - char buf2[512]; - int i; - - printf ("snprintf (\"%%30s\", \"foo\") == %d, \"%.*s\"\n", - snprintf (buf, sizeof (buf), "%30s", "foo"), (int) sizeof (buf), - buf); - memset(buf2,0,sizeof(buf)); - i=snprintf(buf2, 256, "%.9999u", 10); - printf("%i %i\n",i,strlen(buf2)); - - printf ("snprintf (\"%%.999999u\", 10) == %d\n", - snprintf(buf2, sizeof(buf2), "%.999999u", 10)); - } - return 0; -} - -void libc_printf() -{ - printf("stdout test!!\n"); - fprintf(stdout, "fprintf test!!\n"); - fprintf(stderr, "fprintf test!!\n"); - puts("puts test!!\n"); - - putc('1', stderr); - putc('2', stderr); - putc('\n', stderr); - - printf_test(); -} -FINSH_FUNCTION_EXPORT(libc_printf, printf test in libc); - - -void libc_dprintf() -{ - int fd; - - fd = open("/dev/console", O_WRONLY, 0); - if (fd >0) - { - dprintf(fd, "fd:%d printf test!!\n", fd); - close(fd); - } -} -FINSH_FUNCTION_EXPORT(libc_dprintf, dprintf test); - - -void libc_fdopen() -{ - int fd; - FILE* fp; - - fd = open("/dev/console", O_WRONLY, 0); - if (fd >0) - { - fp = fdopen(fd, "w"); - fprintf(fp, "fdopen test, fd %d!!\n", fileno(fp)); - fclose(fp); - } -} -FINSH_FUNCTION_EXPORT(libc_fdopen, fdopen test); +#include +#include +#include + +#include + +char * format[] = { + "%", + "%0.", + "%.0", + "%+0.", + "%+.0", + "%.5", + "%+.5", + "%2.5", + "%22.5", + "%022.5", + "%#022.5", + "%-#022.5", + "%+#022.5", + "%-22.5", + "%+22.5", + "%--22.5", + "%++22.5", + "%+-22.5", + "%-+22.5", + "%-#022.5", + "%-#22.5", + "%-2.22", + "%+2.22", + "%-#02.22", + "%-#2.22", + "%-1.5", + "%1.5", + "%-#01.5", + "%-#1.5", + "%-#.5", + "%-#1.", + "%-#.", + NULL +}; + + +static void +intchk (const char *fmt) +{ + (void) printf("%15s :, \"", fmt); + (void) printf(fmt, 0); + (void) printf("\", \""); + (void) printf(fmt, 123); + (void) printf("\", \""); + (void) printf(fmt, -18); + (void) printf("\"\n"); +} + +static void +fltchk (const char *fmt) +{ + (void) printf("%15s :, \"", fmt); + (void) printf(fmt, 0.0); + (void) printf("\", \""); + (void) printf(fmt, 123.0001); + (void) printf("\", \""); + (void) printf(fmt, -18.0002301); + (void) printf("\"\n"); +} + + +int printf_test() +{ + char buf[256]; + int i; + + printf("%s\n\n", "# vim:syntax=off:"); + + /* integers */ + for(i=0;format[i];i++) { + strcpy(buf, format[i]); + strcat(buf, "d"); + intchk(buf); + } + + /* floats */ + for(i=0;format[i];i++) { + strcpy(buf, format[i]); + strcat(buf, "f"); + fltchk(buf); + } + /* hexa */ + for(i=0;format[i];i++) { + strcpy(buf, format[i]); + strcat(buf, "x"); + intchk(buf); + } + + printf("#%.4x %4x#\n", 4, 88); + printf("#%4x#\n",4); + printf("#%#22.8x#\n",1234567); + + printf("#%+2i#\n",18); + printf("#%i#\n",18); + printf("#%llu#\n",4294967297ULL); + printf("#%#x#\n",44444); + printf("#%-8i#\n",33); + printf("#%i#\n",18); + printf("#%d#\n",18); + printf("#%u#\n",18); + printf("#%lu#\n",18); + printf("#%li#\n",18); + printf("#%-+#06d#\n", -123); + printf("#%-+#6d#\n", -123); + printf("#%+#06d#\n", -123); + printf("#%06d#\n", -123); + printf("#%+15s#\n","ABCDEF"); + /* from ncurses make_keys */ + printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 16, 16, "KEY_A1", "key_a1"); + printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 16, 2, "KEY_A1", "key_a1"); + printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 2, 16, "KEY_A1", "key_a1"); + printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 16, 0, "KEY_A1", "key_a1"); + printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 0, 16, "KEY_A1", "key_a1"); + printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 0, 0, "KEY_A1", "key_a1"); + printf("{ %4d, %*.*s },\t/* %s */\n", 139, 16, 16, "KEY_A1", "key_a1"); + printf("{ %4d, %*.*s },\t/* %s */\n", 139, 16, 2, "KEY_A1", "key_a1"); + printf("{ %4d, %*.*s },\t/* %s */\n", 139, 2, 16, "KEY_A1", "key_a1"); + printf("{ %4d, %*.*s },\t/* %s */\n", 139, 16, 0, "KEY_A1", "key_a1"); + printf("{ %4d, %*.*s },\t/* %s */\n", 139, 0, 16, "KEY_A1", "key_a1"); + printf("{ %4d, %*.*s },\t/* %s */\n", 139, 0, 0, "KEY_A1", "key_a1"); + printf("%*.*f\n", 0, 16, 0.0); + printf("%*.*f\n", 16, 16, 0.0); + printf("%*.*f\n", 2, 2, -0.0); + printf("%*.*f\n", 20, 0, -123.123); + printf("%*.*f\n", 10, 0, +123.123); + + + i = printf("\"%s\"\n","A"); + printf("%i\n", i); + /* from glibc's tst-printf.c */ + + { + char buf[20]; + char buf2[512]; + int i; + + printf ("snprintf (\"%%30s\", \"foo\") == %d, \"%.*s\"\n", + snprintf (buf, sizeof (buf), "%30s", "foo"), (int) sizeof (buf), + buf); + memset(buf2,0,sizeof(buf)); + i=snprintf(buf2, 256, "%.9999u", 10); + printf("%i %i\n",i,strlen(buf2)); + + printf ("snprintf (\"%%.999999u\", 10) == %d\n", + snprintf(buf2, sizeof(buf2), "%.999999u", 10)); + } + return 0; +} + +void libc_printf() +{ + printf("stdout test!!\n"); + fprintf(stdout, "fprintf test!!\n"); + fprintf(stderr, "fprintf test!!\n"); + puts("puts test!!\n"); + + putc('1', stderr); + putc('2', stderr); + putc('\n', stderr); + + printf_test(); +} +FINSH_FUNCTION_EXPORT(libc_printf, printf test in libc); + + +void libc_dprintf() +{ + int fd; + + fd = open("/dev/console", O_WRONLY, 0); + if (fd >0) + { + dprintf(fd, "fd:%d printf test!!\n", fd); + close(fd); + } +} +FINSH_FUNCTION_EXPORT(libc_dprintf, dprintf test); + + +void libc_fdopen() +{ + int fd; + FILE* fp; + + fd = open("/dev/console", O_WRONLY, 0); + if (fd >0) + { + fp = fdopen(fd, "w"); + fprintf(fp, "fdopen test, fd %d!!\n", fileno(fp)); + fclose(fp); + } +} +FINSH_FUNCTION_EXPORT(libc_fdopen, fdopen test); diff --git a/examples/libc/rand.c b/examples/libc/rand.c index ca74353adcb8f121d4ccb65547a6efb6b8dccdae..8f52ad28bb3e6523687335d37c368be554751987 100644 --- a/examples/libc/rand.c +++ b/examples/libc/rand.c @@ -1,43 +1,43 @@ -/* - * rand.c - * - * Created on: 2010-11-17 - * Author: bernard - */ -#include -#include -#include - -int libc_rand(void) -{ - int i1, i2; - int j1, j2; - - /* The C standard says that "If rand is called before any calls to - srand have been made, the same sequence shall be generated as - when srand is first called with a seed value of 1." */ - i1 = rand(); - i2 = rand(); - srand(1); - j1 = rand(); - j2 = rand(); - if (i1 < 0 || i2 < 0 || j1 < 0 || j2 < 0) - { - puts("Test FAILED!"); - } - if (j1 == i1 && j2 == i2) - { - puts("Test succeeded."); - return 0; - } - else - { - if (j1 != i1) - printf("%d != %d\n", j1, i1); - if (j2 != i2) - printf("%d != %d\n", j2, i2); - puts("Test FAILED!"); - return 1; - } -} -FINSH_FUNCTION_EXPORT(libc_rand, rand test for libc); +/* + * rand.c + * + * Created on: 2010-11-17 + * Author: bernard + */ +#include +#include +#include + +int libc_rand(void) +{ + int i1, i2; + int j1, j2; + + /* The C standard says that "If rand is called before any calls to + srand have been made, the same sequence shall be generated as + when srand is first called with a seed value of 1." */ + i1 = rand(); + i2 = rand(); + srand(1); + j1 = rand(); + j2 = rand(); + if (i1 < 0 || i2 < 0 || j1 < 0 || j2 < 0) + { + puts("Test FAILED!"); + } + if (j1 == i1 && j2 == i2) + { + puts("Test succeeded."); + return 0; + } + else + { + if (j1 != i1) + printf("%d != %d\n", j1, i1); + if (j2 != i2) + printf("%d != %d\n", j2, i2); + puts("Test FAILED!"); + return 1; + } +} +FINSH_FUNCTION_EXPORT(libc_rand, rand test for libc); diff --git a/examples/libc/sem.c b/examples/libc/sem.c index 9686119059908ce972d6c67142f2dab3bc8dfdc0..d081d246e93eee93c39ce1205239909dbc326589 100644 --- a/examples/libc/sem.c +++ b/examples/libc/sem.c @@ -1,65 +1,65 @@ -#include -#include -#include - -static sem_t sema; -static void* other_thread() -{ - printf("other_thread here!\n"); - - sleep(1); - - while (1) - { - printf("other_thread: sem_post...\n"); - if(sem_post(&sema) == -1) - printf("sem_post failed\n"); - sleep(1); - } - - printf("other_thread dies!\n"); - pthread_exit(0); -} - -static void test_thread(void* parameter) -{ - pthread_t tid; - - printf("main thread here!\n"); - printf("sleep 5 seconds..."); - sleep(5); - printf("done\n"); - - sem_init(&sema, 0, 0); - - /* create the "other" thread */ - if(pthread_create(&tid, 0, &other_thread, 0)!=0) - /* error */ - printf("pthread_create OtherThread failed.\n"); - else - printf("created OtherThread=%x\n", tid); - - /* let the other thread run */ - while (1) - { - printf("Main: sem_wait...\n"); - if(sem_wait(&sema) == -1) - printf("sem_wait failed\n"); - printf("Main back.\n\n"); - } - - pthread_exit(0); -} -#include -void libc_sem() -{ - rt_thread_t tid; - - tid = rt_thread_create("semtest", test_thread, RT_NULL, - 2048, 20, 5); - if (tid != RT_NULL) - { - rt_thread_startup(tid); - } -} -FINSH_FUNCTION_EXPORT(libc_sem, posix semaphore test); +#include +#include +#include + +static sem_t sema; +static void* other_thread() +{ + printf("other_thread here!\n"); + + sleep(1); + + while (1) + { + printf("other_thread: sem_post...\n"); + if(sem_post(&sema) == -1) + printf("sem_post failed\n"); + sleep(1); + } + + printf("other_thread dies!\n"); + pthread_exit(0); +} + +static void test_thread(void* parameter) +{ + pthread_t tid; + + printf("main thread here!\n"); + printf("sleep 5 seconds..."); + sleep(5); + printf("done\n"); + + sem_init(&sema, 0, 0); + + /* create the "other" thread */ + if(pthread_create(&tid, 0, &other_thread, 0)!=0) + /* error */ + printf("pthread_create OtherThread failed.\n"); + else + printf("created OtherThread=%x\n", tid); + + /* let the other thread run */ + while (1) + { + printf("Main: sem_wait...\n"); + if(sem_wait(&sema) == -1) + printf("sem_wait failed\n"); + printf("Main back.\n\n"); + } + + pthread_exit(0); +} +#include +void libc_sem() +{ + rt_thread_t tid; + + tid = rt_thread_create("semtest", test_thread, RT_NULL, + 2048, 20, 5); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } +} +FINSH_FUNCTION_EXPORT(libc_sem, posix semaphore test); diff --git a/examples/libc/time.c b/examples/libc/time.c index cbe5773ec0127ebf9578e834eb4ffe72fcc7e77a..fa6dee74c8b892db113cd581e618b668cac4685c 100644 --- a/examples/libc/time.c +++ b/examples/libc/time.c @@ -1,24 +1,24 @@ -/* - * time.c - * - * Created on: 2010-11-17 - * Author: bernard - */ - -#include -#include -#include - -int speed() -{ - int i; - time_t t; - - printf("%d\n", time(0)); - for (i = 0; i < 10000000; ++i) - t = time(0); - - printf("%d\n", time(0)); - return 0; -} -FINSH_FUNCTION_EXPORT(speed, speed test); +/* + * time.c + * + * Created on: 2010-11-17 + * Author: bernard + */ + +#include +#include +#include + +int speed() +{ + int i; + time_t t; + + printf("%d\n", time(0)); + for (i = 0; i < 10000000; ++i) + t = time(0); + + printf("%d\n", time(0)); + return 0; +} +FINSH_FUNCTION_EXPORT(speed, speed test); diff --git a/examples/module/README b/examples/module/README index d5990192cecf0f4c51fbb1520e60ac437af74eba..b862667bf2d9d08090fa1effa2a9e9d119a3deb0 100644 --- a/examples/module/README +++ b/examples/module/README @@ -1,4 +1,4 @@ -example: -1.edit rtconfig.py to config toolchain and bsp -2.scons --app=basicapp -3.copy basicapp/build/$bsp/basicapp.so to filesystem +example: +1.edit rtconfig.py to config toolchain and bsp +2.scons --app=basicapp +3.copy basicapp/build/$bsp/basicapp.so to filesystem diff --git a/examples/module/SConstruct b/examples/module/SConstruct index 47bff46f1cb4326078a7db64960a6865f6ed869f..d11d1b6128a4bd588ca8d8ded0c8b48b6e19a9a1 100644 --- a/examples/module/SConstruct +++ b/examples/module/SConstruct @@ -1,73 +1,73 @@ -import os -import sys -import SCons.cpp -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -Export('RTT_ROOT') - -# add target option -AddOption('--app', - dest='app', - nargs=1, type='string', - action='store', - metavar='DIR', - help='installation prefix') - -# add target option -AddOption('--type', - dest='type', - nargs=1, type='string', - action='store', - metavar='DIR', - help='installation prefix') - -app = GetOption('app') - -if GetOption('type') == 'ext': - linkflags = rtconfig.LFLAGS + ' -e 0' -else: - linkflags = rtconfig.LFLAGS + ' -e main' - -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = linkflags, - CPPPATH = [ - RTT_ROOT + '/include', - RTT_ROOT + '/bsp/' + rtconfig.BSP, - RTT_ROOT + '/components/finsh', - RTT_ROOT + '/components/rtgui/include', - RTT_ROOT + '/components/rgtui/common', - RTT_ROOT + '/components/rtgui/server', - RTT_ROOT + '/components/rtgui/widgets', - RTT_ROOT + '/components/libdl', - RTT_ROOT + '/components/external/ftk/ftk/src/os/rt-thread', - RTT_ROOT + '/components/external/ftk/ftk/src/demos', - RTT_ROOT + '/components/external/ftk/ftk/apps/common', - RTT_ROOT + '/components/external/ftk/ftk/src', - RTT_ROOT + '/components/dfs', - RTT_ROOT + '/components/dfs/include', - RTT_ROOT + '/components/libc/newlib', - RTT_ROOT + '/components/external/cairo/cairo-1.10.2/src', - RTT_ROOT + '/components/external/cairo/' - ]) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -PrepareModuleBuilding(env, RTT_ROOT) - -dir = app + '/build/' + rtconfig.BSP -objs = SConscript(app + '/Sconscript', variant_dir=dir, duplicate=0) -TARGET = dir + '/' + app + '.' + rtconfig.TARGET_EXT - -# build program -env.Program(TARGET, objs) +import os +import sys +import SCons.cpp +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +Export('RTT_ROOT') + +# add target option +AddOption('--app', + dest='app', + nargs=1, type='string', + action='store', + metavar='DIR', + help='installation prefix') + +# add target option +AddOption('--type', + dest='type', + nargs=1, type='string', + action='store', + metavar='DIR', + help='installation prefix') + +app = GetOption('app') + +if GetOption('type') == 'ext': + linkflags = rtconfig.LFLAGS + ' -e 0' +else: + linkflags = rtconfig.LFLAGS + ' -e main' + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = linkflags, + CPPPATH = [ + RTT_ROOT + '/include', + RTT_ROOT + '/bsp/' + rtconfig.BSP, + RTT_ROOT + '/components/finsh', + RTT_ROOT + '/components/rtgui/include', + RTT_ROOT + '/components/rgtui/common', + RTT_ROOT + '/components/rtgui/server', + RTT_ROOT + '/components/rtgui/widgets', + RTT_ROOT + '/components/libdl', + RTT_ROOT + '/components/external/ftk/ftk/src/os/rt-thread', + RTT_ROOT + '/components/external/ftk/ftk/src/demos', + RTT_ROOT + '/components/external/ftk/ftk/apps/common', + RTT_ROOT + '/components/external/ftk/ftk/src', + RTT_ROOT + '/components/dfs', + RTT_ROOT + '/components/dfs/include', + RTT_ROOT + '/components/libc/newlib', + RTT_ROOT + '/components/external/cairo/cairo-1.10.2/src', + RTT_ROOT + '/components/external/cairo/' + ]) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +PrepareModuleBuilding(env, RTT_ROOT) + +dir = app + '/build/' + rtconfig.BSP +objs = SConscript(app + '/Sconscript', variant_dir=dir, duplicate=0) +TARGET = dir + '/' + app + '.' + rtconfig.TARGET_EXT + +# build program +env.Program(TARGET, objs) diff --git a/examples/module/basicapp/Sconscript b/examples/module/basicapp/Sconscript index 690ae8c7dd36865e0bca50fec41afe159c46db84..d8dd99964e17081bd6d07dfd91a6dc240e2446ee 100644 --- a/examples/module/basicapp/Sconscript +++ b/examples/module/basicapp/Sconscript @@ -1,7 +1,7 @@ -import rtconfig -Import('RTT_ROOT') -from building import * - -src = Glob('*.c') -group = DefineGroup('', src, depend = ['']) +import rtconfig +Import('RTT_ROOT') +from building import * + +src = Glob('*.c') +group = DefineGroup('', src, depend = ['']) Return('group') \ No newline at end of file diff --git a/examples/module/extapp/Sconscript b/examples/module/extapp/Sconscript index 690ae8c7dd36865e0bca50fec41afe159c46db84..d8dd99964e17081bd6d07dfd91a6dc240e2446ee 100644 --- a/examples/module/extapp/Sconscript +++ b/examples/module/extapp/Sconscript @@ -1,7 +1,7 @@ -import rtconfig -Import('RTT_ROOT') -from building import * - -src = Glob('*.c') -group = DefineGroup('', src, depend = ['']) +import rtconfig +Import('RTT_ROOT') +from building import * + +src = Glob('*.c') +group = DefineGroup('', src, depend = ['']) Return('group') \ No newline at end of file diff --git a/examples/module/rtconfig.py b/examples/module/rtconfig.py index 00163c4e853094b034d552e73d091101f362957b..70ecf91e1fb6e1934cea59bbd6e981ff202929ad 100644 --- a/examples/module/rtconfig.py +++ b/examples/module/rtconfig.py @@ -1,23 +1,23 @@ -# bsp name -BSP = 'mini2440' - -# toolchains -EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' -PREFIX = 'arm-none-eabi-' -CC = PREFIX + 'gcc' -CXX = PREFIX + 'g++' -AS = PREFIX + 'gcc' -AR = PREFIX + 'ar' -LINK = PREFIX + 'gcc' -TARGET_EXT = 'so' -SIZE = PREFIX + 'size' -OBJDUMP = PREFIX + 'objdump' -OBJCPY = PREFIX + 'objcopy' - -DEVICE = ' -mcpu=arm920t' -CFLAGS = DEVICE + ' -O0 -fPIC -DFTK_AS_PLUGIN -DRT_THREAD ' -AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' -LFLAGS = DEVICE + ' -Wl,-z,max-page-size=0x4 -shared -fPIC -nostdlib -s' - -CPATH = '' -LPATH = '' +# bsp name +BSP = 'mini2440' + +# toolchains +EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +PREFIX = 'arm-none-eabi-' +CC = PREFIX + 'gcc' +CXX = PREFIX + 'g++' +AS = PREFIX + 'gcc' +AR = PREFIX + 'ar' +LINK = PREFIX + 'gcc' +TARGET_EXT = 'so' +SIZE = PREFIX + 'size' +OBJDUMP = PREFIX + 'objdump' +OBJCPY = PREFIX + 'objcopy' + +DEVICE = ' -mcpu=arm920t' +CFLAGS = DEVICE + ' -O0 -fPIC -DFTK_AS_PLUGIN -DRT_THREAD ' +AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' +LFLAGS = DEVICE + ' -Wl,-z,max-page-size=0x4 -shared -fPIC -nostdlib -s' + +CPATH = '' +LPATH = '' diff --git a/examples/module/rtconfig_lm3s.py b/examples/module/rtconfig_lm3s.py index 0f81c67a48f51a60b3f096b84ce969dec168970e..a0d350c5b118cf3cc51c2ddbdae49598280eee57 100644 --- a/examples/module/rtconfig_lm3s.py +++ b/examples/module/rtconfig_lm3s.py @@ -1,23 +1,23 @@ -# bsp name -BSP = 'lm3s8962' - -# toolchains -EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' -PREFIX = 'arm-none-eabi-' -CC = PREFIX + 'gcc' -CXX = PREFIX + 'g++' -AS = PREFIX + 'gcc' -AR = PREFIX + 'ar' -LINK = PREFIX + 'gcc' -TARGET_EXT = 'so' -SIZE = PREFIX + 'size' -OBJDUMP = PREFIX + 'objdump' -OBJCPY = PREFIX + 'objcopy' - -DEVICE = ' -mcpu=cortex-m3' -CFLAGS = DEVICE + ' -mthumb -mlong-calls -Dsourcerygxx -O0 -fPIC' -AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' -LFLAGS = DEVICE + ' -mthumb -Wl,-z,max-page-size=0x4 -shared -fPIC -e main -nostdlib' - -CPATH = '' -LPATH = '' +# bsp name +BSP = 'lm3s8962' + +# toolchains +EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +PREFIX = 'arm-none-eabi-' +CC = PREFIX + 'gcc' +CXX = PREFIX + 'g++' +AS = PREFIX + 'gcc' +AR = PREFIX + 'ar' +LINK = PREFIX + 'gcc' +TARGET_EXT = 'so' +SIZE = PREFIX + 'size' +OBJDUMP = PREFIX + 'objdump' +OBJCPY = PREFIX + 'objcopy' + +DEVICE = ' -mcpu=cortex-m3' +CFLAGS = DEVICE + ' -mthumb -mlong-calls -Dsourcerygxx -O0 -fPIC' +AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' +LFLAGS = DEVICE + ' -mthumb -Wl,-z,max-page-size=0x4 -shared -fPIC -e main -nostdlib' + +CPATH = '' +LPATH = '' diff --git a/examples/module/tetris/Sconscript b/examples/module/tetris/Sconscript index 690ae8c7dd36865e0bca50fec41afe159c46db84..d8dd99964e17081bd6d07dfd91a6dc240e2446ee 100644 --- a/examples/module/tetris/Sconscript +++ b/examples/module/tetris/Sconscript @@ -1,7 +1,7 @@ -import rtconfig -Import('RTT_ROOT') -from building import * - -src = Glob('*.c') -group = DefineGroup('', src, depend = ['']) +import rtconfig +Import('RTT_ROOT') +from building import * + +src = Glob('*.c') +group = DefineGroup('', src, depend = ['']) Return('group') \ No newline at end of file diff --git a/examples/module/tetris/tetris.h b/examples/module/tetris/tetris.h index b5ef13785f93ccfa9f75ac380adda0a5eb5005c2..5be429cf726b7c6c2eaf3b8a28037935b4e1bc53 100644 --- a/examples/module/tetris/tetris.h +++ b/examples/module/tetris/tetris.h @@ -1,61 +1,61 @@ -/* - * File : tetris_modal.c - * This file is part of RTGUI in RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-08-14 Yi.Qiu first version - */ - - #include - - struct rt_tetris; - typedef struct rt_tetris rt_tetris_t; - - struct rt_tetris_view; - typedef struct rt_tetris_view rt_tetris_view_t; - - typedef rt_err_t (*on_update)(rt_tetris_view_t* thiz, rt_tetris_t* tetris); - - struct rt_tetris_view - { - rt_uint32_t width; - rt_uint32_t height; - - on_update update; - on_update update_next_brick; - on_update update_level; - on_update update_score_and_lines; - void *private; - }; - - rt_tetris_t* rt_tetris_create(rt_uint32_t width, rt_uint32_t height); - rt_err_t rt_tetris_destory(rt_tetris_t* thiz); - rt_err_t rt_tetris_start(rt_tetris_t* thiz); - rt_err_t rt_tetris_pause(rt_tetris_t* thiz); - rt_uint32_t rt_tetris_width(rt_tetris_t* thiz); - rt_uint32_t* rt_tetris_next_brick(rt_tetris_t* thiz); - rt_uint32_t rt_tetris_level(rt_tetris_t* thiz); - rt_uint32_t rt_tetris_lines(rt_tetris_t* thiz); - rt_uint32_t rt_tetris_score(rt_tetris_t* thiz); - rt_uint32_t rt_tetris_height(rt_tetris_t* thiz); - rt_bool_t rt_tetris_status(rt_tetris_t* thiz); - rt_err_t rt_tetris_down(rt_tetris_t* thiz); - rt_err_t rt_tetris_left(rt_tetris_t* thiz); - rt_err_t rt_tetris_right(rt_tetris_t* thiz); - rt_err_t rt_tetris_drop(rt_tetris_t* thiz); - rt_err_t rt_tetris_rotate(rt_tetris_t* thiz, rt_bool_t direction); - rt_err_t rt_tetris_add_view(rt_tetris_t* thiz, rt_tetris_view_t* view); - rt_err_t rt_tetris_delete_view(rt_tetris_t* thiz, rt_tetris_view_t* view); - rt_err_t rt_tetris_check_collision(rt_tetris_t* thiz, rt_uint32_t block); - - rt_tetris_view_t* rt_tetris_view_create(void* private); - rt_err_t rt_tetris_view_destroy(rt_tetris_view_t* thiz); - -void tetris_ui_entry(void* parameter); - +/* + * File : tetris_modal.c + * This file is part of RTGUI in RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-08-14 Yi.Qiu first version + */ + + #include + + struct rt_tetris; + typedef struct rt_tetris rt_tetris_t; + + struct rt_tetris_view; + typedef struct rt_tetris_view rt_tetris_view_t; + + typedef rt_err_t (*on_update)(rt_tetris_view_t* thiz, rt_tetris_t* tetris); + + struct rt_tetris_view + { + rt_uint32_t width; + rt_uint32_t height; + + on_update update; + on_update update_next_brick; + on_update update_level; + on_update update_score_and_lines; + void *private; + }; + + rt_tetris_t* rt_tetris_create(rt_uint32_t width, rt_uint32_t height); + rt_err_t rt_tetris_destory(rt_tetris_t* thiz); + rt_err_t rt_tetris_start(rt_tetris_t* thiz); + rt_err_t rt_tetris_pause(rt_tetris_t* thiz); + rt_uint32_t rt_tetris_width(rt_tetris_t* thiz); + rt_uint32_t* rt_tetris_next_brick(rt_tetris_t* thiz); + rt_uint32_t rt_tetris_level(rt_tetris_t* thiz); + rt_uint32_t rt_tetris_lines(rt_tetris_t* thiz); + rt_uint32_t rt_tetris_score(rt_tetris_t* thiz); + rt_uint32_t rt_tetris_height(rt_tetris_t* thiz); + rt_bool_t rt_tetris_status(rt_tetris_t* thiz); + rt_err_t rt_tetris_down(rt_tetris_t* thiz); + rt_err_t rt_tetris_left(rt_tetris_t* thiz); + rt_err_t rt_tetris_right(rt_tetris_t* thiz); + rt_err_t rt_tetris_drop(rt_tetris_t* thiz); + rt_err_t rt_tetris_rotate(rt_tetris_t* thiz, rt_bool_t direction); + rt_err_t rt_tetris_add_view(rt_tetris_t* thiz, rt_tetris_view_t* view); + rt_err_t rt_tetris_delete_view(rt_tetris_t* thiz, rt_tetris_view_t* view); + rt_err_t rt_tetris_check_collision(rt_tetris_t* thiz, rt_uint32_t block); + + rt_tetris_view_t* rt_tetris_view_create(void* private); + rt_err_t rt_tetris_view_destroy(rt_tetris_view_t* thiz); + +void tetris_ui_entry(void* parameter); + diff --git a/examples/module/tetris/tetris_modal.c b/examples/module/tetris/tetris_modal.c index 01b5850e96cab016f2e8fe655be91729b9bbae1b..d4532ed78dc8b38796f09754fc9debab17a7616f 100644 --- a/examples/module/tetris/tetris_modal.c +++ b/examples/module/tetris/tetris_modal.c @@ -1,730 +1,730 @@ -/* - * File : tetris_modal.c - * This file is part of RTGUI in RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-08-14 Yi.Qiu first version - */ - -#include -#include -#include "tetris.h" - -struct rt_tetris -{ - rt_uint32_t width; /* the width of the tetris */ - rt_uint32_t height; /* the height of the tetris */ - rt_uint16_t* panel; /* the panel of the tetris */ - rt_uint32_t* brick; /* the current brick of the tetris */ - rt_uint32_t* next_brick; /* the next brick of the tetris */ - rt_tetris_view_t* view; /* the view on which the tetris show */ - rt_uint32_t level; /* game level */ - rt_uint32_t lines; /* released lines count */ - rt_uint32_t score; /* total scores statistic */ - rt_bool_t status; /* game status, pause or runing */ -}; - -static const rt_uint32_t g_brick[][4] = -{ - {23,7,8,22}, - {23,7,8,24}, - {24,7,8,25}, - {8,7,9,23}, - {8,7,9,24}, - {8,7,9,25}, - {7,6,8,9}, -}; - -static rt_err_t rt_tetris_append_brick(rt_tetris_t* thiz, rt_uint32_t brick[]); -static rt_err_t rt_tetris_delete_brick(rt_tetris_t* thiz, rt_uint32_t brick[]); -static rt_err_t rt_tetris_release_lines(rt_tetris_t* thiz, rt_uint32_t brick[]); -static rt_err_t rt_tetris_is_reach_top(rt_tetris_t* thiz, rt_uint32_t brick[]); -static rt_err_t rt_tetris_update_brick(rt_tetris_t* thiz); - -/** - * this function create a tetris instance - * - * @param width the width of tetris. - * @param height the height of tetris. - * - * @return the tetris instance - */ -rt_tetris_t* rt_tetris_create(rt_uint32_t width, rt_uint32_t height) -{ - int index; - - rt_tetris_t* thiz = (rt_tetris_t*)rt_malloc(sizeof(rt_tetris_t)); - RT_ASSERT(thiz != RT_NULL); - - thiz->height = height; - thiz->width = width; - thiz->panel = rt_malloc(thiz->height * sizeof(rt_uint32_t)); - rt_memset(thiz->panel, 0, thiz->height * sizeof(rt_uint32_t)); - - thiz->brick = (rt_uint32_t*)rt_malloc(4 * sizeof(rt_uint32_t)); - index = (int)(7.0 * rand()/(RAND_MAX + 1.0)); - rt_memcpy(thiz->brick, g_brick[index], 4 * sizeof(rt_uint32_t)); - - thiz->next_brick= (rt_uint32_t*)rt_malloc(4 * sizeof(rt_uint32_t)); - index = (int)(7.0 * rand()/(RAND_MAX + 1.0)); - rt_memcpy(thiz->next_brick, g_brick[index], 4 * sizeof(rt_uint32_t)); - - thiz->view = RT_NULL; - thiz->level = 0; - thiz->lines = 0; - thiz->score = 0; - thiz->status = RT_FALSE; - - return thiz; -} - -/** - * this function destory a tetris instance - * - * @param thiz the tetris instance. - * - * @return RT_EOK - */ -rt_err_t rt_tetris_destory(rt_tetris_t* thiz) -{ - RT_ASSERT(thiz->panel && thiz->brick && thiz->next_brick); - - rt_free(thiz->panel); - rt_free(thiz->brick); - rt_free(thiz->next_brick); - rt_free(thiz); - - return RT_EOK; -} - -/** - * this function start tetris game - * - * @param thiz the tetris instance. - * - * @return RT_EOK - */ -rt_err_t rt_tetris_start(rt_tetris_t* thiz) -{ - RT_ASSERT(thiz != RT_NULL); - - /* update next brick on view */ - thiz->view->update_next_brick(thiz->view, thiz); - - /* update level */ - thiz->view->update_level(thiz->view, thiz); - - /* update lines and score */ - thiz->view->update_score_and_lines(thiz->view, thiz); - - thiz->status = RT_TRUE; - - return RT_EOK; -} - -/** - * this function pause tetris game - * - * @param thiz the tetris instance. - * - * @return RT_EOK - */ -rt_err_t rt_tetris_pause(rt_tetris_t* thiz) -{ - RT_ASSERT(thiz != RT_NULL); - - thiz->status = RT_FALSE; - - return RT_EOK; -} - -/** - * this function get width of a tetris instance - * - * @param thiz the tetris instance. - * - * @return the width of the tetris instance - */ -rt_uint32_t rt_tetris_width(rt_tetris_t* thiz) -{ - RT_ASSERT(thiz != RT_NULL); - - return thiz->width; -} - -/** - * this function get next brick of a tetris instance - * - * @param thiz the tetris instance. - * - * @return the next brick of the tetris instance - */ -rt_uint32_t* rt_tetris_next_brick(rt_tetris_t* thiz) -{ - RT_ASSERT(thiz != RT_NULL); - - return thiz->next_brick; -} - -/** - * this function get level of the tetris instance - * - * @param thiz the tetris instance. - * - * @return the level of the tetris instance - */ -rt_uint32_t rt_tetris_level(rt_tetris_t* thiz) -{ - RT_ASSERT(thiz != RT_NULL); - - return thiz->level; -} - -/** - * this function get released lines of the tetris instance - * - * @param thiz the tetris instance. - * - * @return the released lines of the tetris instance - */ -rt_uint32_t rt_tetris_lines(rt_tetris_t* thiz) -{ - RT_ASSERT(thiz != RT_NULL); - - return thiz->lines; -} - -/** - * this function get score of the tetris instance - * - * @param thiz the tetris instance. - * - * @return the score of the tetris instance - */ -rt_uint32_t rt_tetris_score(rt_tetris_t* thiz) -{ - RT_ASSERT(thiz != RT_NULL); - - return thiz->score; -} - -/** - * this function get height of a tetris instance - * - * @param thiz the tetris instance. - * - * @return the height of the tetris instance - */ -rt_uint32_t rt_tetris_height(rt_tetris_t* thiz) -{ - RT_ASSERT(thiz != RT_NULL); - - return thiz->height; -} - -/** - * this function get status of a tetris instance - * - * @param thiz the tetris instance. - * - * @return the status of the tetris instance - */ -rt_bool_t rt_tetris_status(rt_tetris_t* thiz) -{ - RT_ASSERT(thiz != RT_NULL); - - return thiz->status; -} - -/** - * this function makes current brick move down - * - * @param thiz the tetris instance. - * - * @return RT_EOK on success, -RT_ERROR on fail - */ -rt_err_t rt_tetris_down(rt_tetris_t* thiz) -{ - int i; - - RT_ASSERT(thiz != RT_NULL); - - if(thiz->status == RT_FALSE) return -RT_ERROR; - - /* delete the brick from tetris panel */ - rt_tetris_delete_brick(thiz, thiz->brick); - - for(i=0; i<4; i++) - { - /* check collision and bottom*/ - if((thiz->brick[i] >= thiz->width * (thiz->height - 1)) - || rt_tetris_check_collision(thiz, thiz->brick[i] + thiz->width) == RT_EOK) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - - if(rt_tetris_is_reach_top(thiz, thiz->brick) == RT_EOK) - { - rt_memset(thiz->panel, 0xff, thiz->height * sizeof(rt_uint32_t)); - - /* update view */ - thiz->view->update(thiz->view, thiz); - - /* game over */ - return -RT_ETIMEOUT; - } - - if(rt_tetris_release_lines(thiz, thiz->brick) == RT_EOK) - { - /* update view */ - thiz->view->update(thiz->view, thiz); - } - - rt_tetris_update_brick(thiz); - return -RT_ERROR; - } - } - - for(i=0; i<4; i++) - { - /* increase one line */ - thiz->brick[i] += thiz->width; - } - - /* append the brick to tetris panel */ - rt_tetris_append_brick(thiz, thiz->brick); - - /* update view */ - thiz->view->update(thiz->view, thiz); - - return RT_EOK; -} - -/** - * this function makes current brick move left - * - * @param thiz the tetris instance. - * - * @return RT_EOK on success, -RT_ERROR on fail - */ -rt_err_t rt_tetris_left(rt_tetris_t* thiz) -{ - int i; - RT_ASSERT(thiz != RT_NULL); - - if(thiz->status == RT_FALSE) return -RT_ERROR; - - /* delete the brick from tetris panel */ - rt_tetris_delete_brick(thiz, thiz->brick); - - for(i=0; i<4; i++) - { - /* check left board */ - if((thiz->brick[i] % thiz->width) == 0) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - return -RT_ERROR; - } - - if(rt_tetris_check_collision(thiz, thiz->brick[i] - 1) == RT_EOK) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - return -RT_ERROR; - } - } - - for(i=0; i<4; i++) - { - /* move one step to left */ - thiz->brick[i] --;; - } - - /* append the brick to tetris panel */ - rt_tetris_append_brick(thiz, thiz->brick); - - /* update view */ - thiz->view->update(thiz->view, thiz); - - return RT_EOK; -} - -/** - * this function makes current brick move right - * - * @param thiz the tetris instance. - * - * @return RT_EOK on success, -RT_ERROR on fail - */ -rt_err_t rt_tetris_right(rt_tetris_t* thiz) -{ - int i; - RT_ASSERT(thiz != RT_NULL); - - if(thiz->status == RT_FALSE) return -RT_ERROR; - - /* delete the brick from tetris panel */ - rt_tetris_delete_brick(thiz, thiz->brick); - - for(i=0; i<4; i++) - { - /* check left board */ - if(((thiz->brick[i] + 1) % thiz->width) == 0) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - return -RT_ERROR; - } - - /* check collision */ - if(rt_tetris_check_collision(thiz, thiz->brick[i] + 1) == RT_EOK) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - return -RT_ERROR; - } - } - - for(i=0; i<4; i++) - { - /* move one step to right */ - thiz->brick[i] ++;; - } - - /* append the brick to tetris panel */ - rt_tetris_append_brick(thiz, thiz->brick); - - /* update view */ - thiz->view->update(thiz->view, thiz); - - return RT_EOK; -} - -/** - * this function makes current brick drop quickly - * - * @param thiz the tetris instance. - * - * @return RT_EOK on success, -RT_ERROR on fail - */ -rt_err_t rt_tetris_drop(rt_tetris_t* thiz) -{ - rt_err_t ret; - RT_ASSERT(thiz != RT_NULL); - - if(thiz->status == RT_FALSE) return -RT_ETIMEOUT; - - /* move down until blocked */ - while((ret = rt_tetris_down(thiz)) == RT_EOK); - - return ret; -} - -/** - * this function makes current brick do rotation - * - * @param thiz the tetris instance. - * - * @return RT_EOK on success, -RT_ERROR on fail - */ -rt_err_t rt_tetris_rotate(rt_tetris_t* thiz, rt_bool_t direction) -{ - int i; - rt_uint32_t tmp[4]; - RT_ASSERT(thiz != RT_NULL); - - if(thiz->status == RT_FALSE) return -RT_ERROR; - - rt_tetris_delete_brick(thiz, thiz->brick); - - tmp[0] = thiz->brick[0]; - for(i=1; i<4; i++) - { - int diff = thiz->brick[0] - thiz->brick[i]; - if(diff == 1) - { - tmp[i] = thiz->brick[0] - thiz->width; - } - else if(diff == -1) - { - tmp[i] = thiz->brick[0] + thiz->width; - } - else if(diff == 2) - { - tmp[i] = thiz->brick[0] - 2 * thiz->width; - } - else if(diff == -2) - { - tmp[i] = thiz->brick[0] + 2 * thiz->width; - } - else if(diff == thiz->width - 1) - { - tmp[i] = thiz->brick[0] + thiz->width + 1; - } - else if(diff == 1 - thiz->width) - { - tmp[i] = thiz->brick[0] - thiz->width - 1; - } - else if(diff == thiz->width) - { - if((thiz->brick[0] + 1) % thiz->width == 0) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - return -RT_ERROR; - } - else tmp[i] = thiz->brick[0] + 1; - } - else if(diff == -1 * (thiz->width)) - { - if(thiz->brick[0] % thiz->width == 0) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - return -RT_ERROR; - } - else tmp[i] = thiz->brick[0] - 1; - } - else if(diff == thiz->width + 1) - { - tmp[i] = thiz->brick[0] - thiz->width + 1; - } - else if(diff == -1 - thiz->width) - { - tmp[i] = thiz->brick[0] + thiz->width - 1; - } - else if(diff == 2 * thiz->width) - { - if((thiz->brick[0] % thiz->width) >= (thiz->width - 2)) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - return -RT_ERROR; - } - else tmp[i] = thiz->brick[0] + 2; - } - else if(diff == -2 * thiz->width) - { - if((thiz->brick[0] % thiz->width) < 2) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - return -RT_ERROR; - } - else tmp[i] = thiz->brick[0] - 2; - } - - if(tmp[i] > (thiz->height) * thiz->width) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - return -RT_ERROR; - } - - if(rt_tetris_check_collision(thiz, tmp[i]) == RT_EOK) - { - /* restore the deleted brick */ - rt_tetris_append_brick(thiz, thiz->brick); - return -RT_ERROR; - } - } - - /* do roration */ - for(i=0; i<4; i++) - { - thiz->brick[i] = tmp[i]; - } - - /* append the brick to tetris panel */ - rt_tetris_append_brick(thiz, thiz->brick); - - /* update view */ - thiz->view->update(thiz->view, thiz); - - return RT_EOK; -} - -/** - * this function add a view to the tetris - * - * @param thiz the tetris instance. - * @param view the view instance. - * - * @return RT_EOK on success, -RT_ERROR on fail - */ -rt_err_t rt_tetris_add_view(rt_tetris_t* thiz, rt_tetris_view_t* view) -{ - RT_ASSERT(thiz != RT_NULL); - - /* Only suppurt single view now */ - thiz->view = view; - - return RT_EOK; -} - -/** - * this function delete a view from the tetris - * - * @param thiz the tetris instance. - * @param view the view instance. - * - * @return RT_EOK on success, -RT_ERROR on fail - */ - -rt_err_t rt_tetris_delete_view(rt_tetris_t* thiz, rt_tetris_view_t* view) -{ - RT_ASSERT(thiz != RT_NULL); - - thiz->view = RT_NULL; - - return RT_EOK; -} - -/** - * this function used to check collision - * - * @param thiz the tetris instance. - * @param block the block to be checked. - * - * @return RT_EOK on collision, -RT_ERROR on not collision - */ -rt_err_t rt_tetris_check_collision(rt_tetris_t* thiz, rt_uint32_t block) -{ - RT_ASSERT(thiz != RT_NULL); - RT_ASSERT(block < thiz->height * thiz->width); - - if((thiz->panel[block/thiz->width] & (1 << (block % thiz->width))) - == (1 << (block % thiz->width))) - { - return RT_EOK; - } - else - { - return -RT_ERROR; - } -} - -static rt_err_t rt_tetris_update_brick(rt_tetris_t* thiz) -{ - int index; - - RT_ASSERT(thiz != RT_NULL); - - index = (int)(7.0 * rand()/(RAND_MAX + 1.0)); - - rt_memcpy(thiz->brick, thiz->next_brick, 4 * sizeof(rt_uint32_t)); - rt_memcpy(thiz->next_brick, g_brick[index], 4 * sizeof(rt_uint32_t)); - - /* update next brick on view */ - thiz->view->update_next_brick(thiz->view, thiz); - - return RT_EOK; -} - -static rt_err_t rt_tetris_append_brick(rt_tetris_t* thiz, rt_uint32_t brick[]) -{ - int i; - - RT_ASSERT(thiz != RT_NULL); - RT_ASSERT(brick != RT_NULL); - - for(i=0; i<4; i++) - { - int y = brick[i]/thiz->width; - int x = brick[i]%thiz->width; - - thiz->panel[y] |= (1<width; - int x = brick[i]%thiz->width; - - thiz->panel[y] &= ~(1<width == 0) - return RT_EOK; - } - - return -RT_ERROR; -} - -static rt_err_t rt_tetris_release_lines(rt_tetris_t* thiz, rt_uint32_t brick[]) -{ - int i, j, check_line = 0; - rt_bool_t line_released = -RT_ERROR; - - RT_ASSERT(thiz != RT_NULL); - RT_ASSERT(brick != RT_NULL); - - for(i=0; i<4; i++) - { - /* choose a line */ - check_line = brick[i]/thiz->width; - if((thiz->panel[check_line]) == ((1 << thiz->width) - 1)) - { - for(j=check_line; j>0; j--) - { - thiz->panel[j] = thiz->panel[j-1]; - } - - /* clear the first line */ - thiz->panel[0] = 0; - - for(j=i+1; j<4; j++) - { - if(brick[j] < brick[i]) - { - brick[j] += thiz->width; - } - } - - thiz->lines++; - thiz->score += 100; - line_released = RT_EOK; - } - } - - if(line_released == RT_EOK) - { - /* update view */ - thiz->view->update_score_and_lines(thiz->view, thiz); - return RT_EOK; - } - else - { - return -RT_ERROR; - } -} - +/* + * File : tetris_modal.c + * This file is part of RTGUI in RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-08-14 Yi.Qiu first version + */ + +#include +#include +#include "tetris.h" + +struct rt_tetris +{ + rt_uint32_t width; /* the width of the tetris */ + rt_uint32_t height; /* the height of the tetris */ + rt_uint16_t* panel; /* the panel of the tetris */ + rt_uint32_t* brick; /* the current brick of the tetris */ + rt_uint32_t* next_brick; /* the next brick of the tetris */ + rt_tetris_view_t* view; /* the view on which the tetris show */ + rt_uint32_t level; /* game level */ + rt_uint32_t lines; /* released lines count */ + rt_uint32_t score; /* total scores statistic */ + rt_bool_t status; /* game status, pause or runing */ +}; + +static const rt_uint32_t g_brick[][4] = +{ + {23,7,8,22}, + {23,7,8,24}, + {24,7,8,25}, + {8,7,9,23}, + {8,7,9,24}, + {8,7,9,25}, + {7,6,8,9}, +}; + +static rt_err_t rt_tetris_append_brick(rt_tetris_t* thiz, rt_uint32_t brick[]); +static rt_err_t rt_tetris_delete_brick(rt_tetris_t* thiz, rt_uint32_t brick[]); +static rt_err_t rt_tetris_release_lines(rt_tetris_t* thiz, rt_uint32_t brick[]); +static rt_err_t rt_tetris_is_reach_top(rt_tetris_t* thiz, rt_uint32_t brick[]); +static rt_err_t rt_tetris_update_brick(rt_tetris_t* thiz); + +/** + * this function create a tetris instance + * + * @param width the width of tetris. + * @param height the height of tetris. + * + * @return the tetris instance + */ +rt_tetris_t* rt_tetris_create(rt_uint32_t width, rt_uint32_t height) +{ + int index; + + rt_tetris_t* thiz = (rt_tetris_t*)rt_malloc(sizeof(rt_tetris_t)); + RT_ASSERT(thiz != RT_NULL); + + thiz->height = height; + thiz->width = width; + thiz->panel = rt_malloc(thiz->height * sizeof(rt_uint32_t)); + rt_memset(thiz->panel, 0, thiz->height * sizeof(rt_uint32_t)); + + thiz->brick = (rt_uint32_t*)rt_malloc(4 * sizeof(rt_uint32_t)); + index = (int)(7.0 * rand()/(RAND_MAX + 1.0)); + rt_memcpy(thiz->brick, g_brick[index], 4 * sizeof(rt_uint32_t)); + + thiz->next_brick= (rt_uint32_t*)rt_malloc(4 * sizeof(rt_uint32_t)); + index = (int)(7.0 * rand()/(RAND_MAX + 1.0)); + rt_memcpy(thiz->next_brick, g_brick[index], 4 * sizeof(rt_uint32_t)); + + thiz->view = RT_NULL; + thiz->level = 0; + thiz->lines = 0; + thiz->score = 0; + thiz->status = RT_FALSE; + + return thiz; +} + +/** + * this function destory a tetris instance + * + * @param thiz the tetris instance. + * + * @return RT_EOK + */ +rt_err_t rt_tetris_destory(rt_tetris_t* thiz) +{ + RT_ASSERT(thiz->panel && thiz->brick && thiz->next_brick); + + rt_free(thiz->panel); + rt_free(thiz->brick); + rt_free(thiz->next_brick); + rt_free(thiz); + + return RT_EOK; +} + +/** + * this function start tetris game + * + * @param thiz the tetris instance. + * + * @return RT_EOK + */ +rt_err_t rt_tetris_start(rt_tetris_t* thiz) +{ + RT_ASSERT(thiz != RT_NULL); + + /* update next brick on view */ + thiz->view->update_next_brick(thiz->view, thiz); + + /* update level */ + thiz->view->update_level(thiz->view, thiz); + + /* update lines and score */ + thiz->view->update_score_and_lines(thiz->view, thiz); + + thiz->status = RT_TRUE; + + return RT_EOK; +} + +/** + * this function pause tetris game + * + * @param thiz the tetris instance. + * + * @return RT_EOK + */ +rt_err_t rt_tetris_pause(rt_tetris_t* thiz) +{ + RT_ASSERT(thiz != RT_NULL); + + thiz->status = RT_FALSE; + + return RT_EOK; +} + +/** + * this function get width of a tetris instance + * + * @param thiz the tetris instance. + * + * @return the width of the tetris instance + */ +rt_uint32_t rt_tetris_width(rt_tetris_t* thiz) +{ + RT_ASSERT(thiz != RT_NULL); + + return thiz->width; +} + +/** + * this function get next brick of a tetris instance + * + * @param thiz the tetris instance. + * + * @return the next brick of the tetris instance + */ +rt_uint32_t* rt_tetris_next_brick(rt_tetris_t* thiz) +{ + RT_ASSERT(thiz != RT_NULL); + + return thiz->next_brick; +} + +/** + * this function get level of the tetris instance + * + * @param thiz the tetris instance. + * + * @return the level of the tetris instance + */ +rt_uint32_t rt_tetris_level(rt_tetris_t* thiz) +{ + RT_ASSERT(thiz != RT_NULL); + + return thiz->level; +} + +/** + * this function get released lines of the tetris instance + * + * @param thiz the tetris instance. + * + * @return the released lines of the tetris instance + */ +rt_uint32_t rt_tetris_lines(rt_tetris_t* thiz) +{ + RT_ASSERT(thiz != RT_NULL); + + return thiz->lines; +} + +/** + * this function get score of the tetris instance + * + * @param thiz the tetris instance. + * + * @return the score of the tetris instance + */ +rt_uint32_t rt_tetris_score(rt_tetris_t* thiz) +{ + RT_ASSERT(thiz != RT_NULL); + + return thiz->score; +} + +/** + * this function get height of a tetris instance + * + * @param thiz the tetris instance. + * + * @return the height of the tetris instance + */ +rt_uint32_t rt_tetris_height(rt_tetris_t* thiz) +{ + RT_ASSERT(thiz != RT_NULL); + + return thiz->height; +} + +/** + * this function get status of a tetris instance + * + * @param thiz the tetris instance. + * + * @return the status of the tetris instance + */ +rt_bool_t rt_tetris_status(rt_tetris_t* thiz) +{ + RT_ASSERT(thiz != RT_NULL); + + return thiz->status; +} + +/** + * this function makes current brick move down + * + * @param thiz the tetris instance. + * + * @return RT_EOK on success, -RT_ERROR on fail + */ +rt_err_t rt_tetris_down(rt_tetris_t* thiz) +{ + int i; + + RT_ASSERT(thiz != RT_NULL); + + if(thiz->status == RT_FALSE) return -RT_ERROR; + + /* delete the brick from tetris panel */ + rt_tetris_delete_brick(thiz, thiz->brick); + + for(i=0; i<4; i++) + { + /* check collision and bottom*/ + if((thiz->brick[i] >= thiz->width * (thiz->height - 1)) + || rt_tetris_check_collision(thiz, thiz->brick[i] + thiz->width) == RT_EOK) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + + if(rt_tetris_is_reach_top(thiz, thiz->brick) == RT_EOK) + { + rt_memset(thiz->panel, 0xff, thiz->height * sizeof(rt_uint32_t)); + + /* update view */ + thiz->view->update(thiz->view, thiz); + + /* game over */ + return -RT_ETIMEOUT; + } + + if(rt_tetris_release_lines(thiz, thiz->brick) == RT_EOK) + { + /* update view */ + thiz->view->update(thiz->view, thiz); + } + + rt_tetris_update_brick(thiz); + return -RT_ERROR; + } + } + + for(i=0; i<4; i++) + { + /* increase one line */ + thiz->brick[i] += thiz->width; + } + + /* append the brick to tetris panel */ + rt_tetris_append_brick(thiz, thiz->brick); + + /* update view */ + thiz->view->update(thiz->view, thiz); + + return RT_EOK; +} + +/** + * this function makes current brick move left + * + * @param thiz the tetris instance. + * + * @return RT_EOK on success, -RT_ERROR on fail + */ +rt_err_t rt_tetris_left(rt_tetris_t* thiz) +{ + int i; + RT_ASSERT(thiz != RT_NULL); + + if(thiz->status == RT_FALSE) return -RT_ERROR; + + /* delete the brick from tetris panel */ + rt_tetris_delete_brick(thiz, thiz->brick); + + for(i=0; i<4; i++) + { + /* check left board */ + if((thiz->brick[i] % thiz->width) == 0) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + return -RT_ERROR; + } + + if(rt_tetris_check_collision(thiz, thiz->brick[i] - 1) == RT_EOK) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + return -RT_ERROR; + } + } + + for(i=0; i<4; i++) + { + /* move one step to left */ + thiz->brick[i] --;; + } + + /* append the brick to tetris panel */ + rt_tetris_append_brick(thiz, thiz->brick); + + /* update view */ + thiz->view->update(thiz->view, thiz); + + return RT_EOK; +} + +/** + * this function makes current brick move right + * + * @param thiz the tetris instance. + * + * @return RT_EOK on success, -RT_ERROR on fail + */ +rt_err_t rt_tetris_right(rt_tetris_t* thiz) +{ + int i; + RT_ASSERT(thiz != RT_NULL); + + if(thiz->status == RT_FALSE) return -RT_ERROR; + + /* delete the brick from tetris panel */ + rt_tetris_delete_brick(thiz, thiz->brick); + + for(i=0; i<4; i++) + { + /* check left board */ + if(((thiz->brick[i] + 1) % thiz->width) == 0) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + return -RT_ERROR; + } + + /* check collision */ + if(rt_tetris_check_collision(thiz, thiz->brick[i] + 1) == RT_EOK) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + return -RT_ERROR; + } + } + + for(i=0; i<4; i++) + { + /* move one step to right */ + thiz->brick[i] ++;; + } + + /* append the brick to tetris panel */ + rt_tetris_append_brick(thiz, thiz->brick); + + /* update view */ + thiz->view->update(thiz->view, thiz); + + return RT_EOK; +} + +/** + * this function makes current brick drop quickly + * + * @param thiz the tetris instance. + * + * @return RT_EOK on success, -RT_ERROR on fail + */ +rt_err_t rt_tetris_drop(rt_tetris_t* thiz) +{ + rt_err_t ret; + RT_ASSERT(thiz != RT_NULL); + + if(thiz->status == RT_FALSE) return -RT_ETIMEOUT; + + /* move down until blocked */ + while((ret = rt_tetris_down(thiz)) == RT_EOK); + + return ret; +} + +/** + * this function makes current brick do rotation + * + * @param thiz the tetris instance. + * + * @return RT_EOK on success, -RT_ERROR on fail + */ +rt_err_t rt_tetris_rotate(rt_tetris_t* thiz, rt_bool_t direction) +{ + int i; + rt_uint32_t tmp[4]; + RT_ASSERT(thiz != RT_NULL); + + if(thiz->status == RT_FALSE) return -RT_ERROR; + + rt_tetris_delete_brick(thiz, thiz->brick); + + tmp[0] = thiz->brick[0]; + for(i=1; i<4; i++) + { + int diff = thiz->brick[0] - thiz->brick[i]; + if(diff == 1) + { + tmp[i] = thiz->brick[0] - thiz->width; + } + else if(diff == -1) + { + tmp[i] = thiz->brick[0] + thiz->width; + } + else if(diff == 2) + { + tmp[i] = thiz->brick[0] - 2 * thiz->width; + } + else if(diff == -2) + { + tmp[i] = thiz->brick[0] + 2 * thiz->width; + } + else if(diff == thiz->width - 1) + { + tmp[i] = thiz->brick[0] + thiz->width + 1; + } + else if(diff == 1 - thiz->width) + { + tmp[i] = thiz->brick[0] - thiz->width - 1; + } + else if(diff == thiz->width) + { + if((thiz->brick[0] + 1) % thiz->width == 0) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + return -RT_ERROR; + } + else tmp[i] = thiz->brick[0] + 1; + } + else if(diff == -1 * (thiz->width)) + { + if(thiz->brick[0] % thiz->width == 0) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + return -RT_ERROR; + } + else tmp[i] = thiz->brick[0] - 1; + } + else if(diff == thiz->width + 1) + { + tmp[i] = thiz->brick[0] - thiz->width + 1; + } + else if(diff == -1 - thiz->width) + { + tmp[i] = thiz->brick[0] + thiz->width - 1; + } + else if(diff == 2 * thiz->width) + { + if((thiz->brick[0] % thiz->width) >= (thiz->width - 2)) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + return -RT_ERROR; + } + else tmp[i] = thiz->brick[0] + 2; + } + else if(diff == -2 * thiz->width) + { + if((thiz->brick[0] % thiz->width) < 2) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + return -RT_ERROR; + } + else tmp[i] = thiz->brick[0] - 2; + } + + if(tmp[i] > (thiz->height) * thiz->width) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + return -RT_ERROR; + } + + if(rt_tetris_check_collision(thiz, tmp[i]) == RT_EOK) + { + /* restore the deleted brick */ + rt_tetris_append_brick(thiz, thiz->brick); + return -RT_ERROR; + } + } + + /* do roration */ + for(i=0; i<4; i++) + { + thiz->brick[i] = tmp[i]; + } + + /* append the brick to tetris panel */ + rt_tetris_append_brick(thiz, thiz->brick); + + /* update view */ + thiz->view->update(thiz->view, thiz); + + return RT_EOK; +} + +/** + * this function add a view to the tetris + * + * @param thiz the tetris instance. + * @param view the view instance. + * + * @return RT_EOK on success, -RT_ERROR on fail + */ +rt_err_t rt_tetris_add_view(rt_tetris_t* thiz, rt_tetris_view_t* view) +{ + RT_ASSERT(thiz != RT_NULL); + + /* Only suppurt single view now */ + thiz->view = view; + + return RT_EOK; +} + +/** + * this function delete a view from the tetris + * + * @param thiz the tetris instance. + * @param view the view instance. + * + * @return RT_EOK on success, -RT_ERROR on fail + */ + +rt_err_t rt_tetris_delete_view(rt_tetris_t* thiz, rt_tetris_view_t* view) +{ + RT_ASSERT(thiz != RT_NULL); + + thiz->view = RT_NULL; + + return RT_EOK; +} + +/** + * this function used to check collision + * + * @param thiz the tetris instance. + * @param block the block to be checked. + * + * @return RT_EOK on collision, -RT_ERROR on not collision + */ +rt_err_t rt_tetris_check_collision(rt_tetris_t* thiz, rt_uint32_t block) +{ + RT_ASSERT(thiz != RT_NULL); + RT_ASSERT(block < thiz->height * thiz->width); + + if((thiz->panel[block/thiz->width] & (1 << (block % thiz->width))) + == (1 << (block % thiz->width))) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + +static rt_err_t rt_tetris_update_brick(rt_tetris_t* thiz) +{ + int index; + + RT_ASSERT(thiz != RT_NULL); + + index = (int)(7.0 * rand()/(RAND_MAX + 1.0)); + + rt_memcpy(thiz->brick, thiz->next_brick, 4 * sizeof(rt_uint32_t)); + rt_memcpy(thiz->next_brick, g_brick[index], 4 * sizeof(rt_uint32_t)); + + /* update next brick on view */ + thiz->view->update_next_brick(thiz->view, thiz); + + return RT_EOK; +} + +static rt_err_t rt_tetris_append_brick(rt_tetris_t* thiz, rt_uint32_t brick[]) +{ + int i; + + RT_ASSERT(thiz != RT_NULL); + RT_ASSERT(brick != RT_NULL); + + for(i=0; i<4; i++) + { + int y = brick[i]/thiz->width; + int x = brick[i]%thiz->width; + + thiz->panel[y] |= (1<width; + int x = brick[i]%thiz->width; + + thiz->panel[y] &= ~(1<width == 0) + return RT_EOK; + } + + return -RT_ERROR; +} + +static rt_err_t rt_tetris_release_lines(rt_tetris_t* thiz, rt_uint32_t brick[]) +{ + int i, j, check_line = 0; + rt_bool_t line_released = -RT_ERROR; + + RT_ASSERT(thiz != RT_NULL); + RT_ASSERT(brick != RT_NULL); + + for(i=0; i<4; i++) + { + /* choose a line */ + check_line = brick[i]/thiz->width; + if((thiz->panel[check_line]) == ((1 << thiz->width) - 1)) + { + for(j=check_line; j>0; j--) + { + thiz->panel[j] = thiz->panel[j-1]; + } + + /* clear the first line */ + thiz->panel[0] = 0; + + for(j=i+1; j<4; j++) + { + if(brick[j] < brick[i]) + { + brick[j] += thiz->width; + } + } + + thiz->lines++; + thiz->score += 100; + line_released = RT_EOK; + } + } + + if(line_released == RT_EOK) + { + /* update view */ + thiz->view->update_score_and_lines(thiz->view, thiz); + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + diff --git a/examples/module/tetris/tetris_ui.c b/examples/module/tetris/tetris_ui.c index 86bb7f3b3ae7018f47cd2fa9c539e0eaf1069c5b..f5b64ab9fa301d28b057722ac88c1d0c059cc219 100644 --- a/examples/module/tetris/tetris_ui.c +++ b/examples/module/tetris/tetris_ui.c @@ -1,239 +1,239 @@ -/* - * File : tetris_ui.c - * This file is part of RTGUI in RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-08-14 Yi.Qiu first version - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "tetris.h" - -struct app_info -{ - rtgui_workbench_t* workbench; - rtgui_view_t* game_view; - rtgui_list_view_t* function_view; - - rt_tetris_t * tetris; - rt_tetris_view_t* tetris_view; - rtgui_timer_t* _timer; -}; -typedef struct app_info app_info; -static app_info g_app_info; - -static void _game_over(void) -{ - rtgui_timer_destory(g_app_info._timer); - rt_tetris_destory(g_app_info.tetris); - rt_tetris_view_destroy(g_app_info.tetris_view); - rt_kprintf("GAME OVER\n"); - - rtgui_view_show(g_app_info.function_view, RT_FALSE); -} - -static rt_bool_t game_view_event_handler(struct rtgui_widget* widget, struct rtgui_event* event) -{ - if (event->type == RTGUI_EVENT_PAINT) - { - struct rtgui_dc* dc; - rtgui_rect_t rect; - - /* draw child */ - rtgui_view_event_handler(widget, event); - - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) return -RT_ERROR; - rect.x1 = 96; - rect.y1 = 0; - rect.x2 = 128; - rect.y2 = 16; - rtgui_dc_draw_text(dc, "next", &rect); - rect.y1 += 30; - rect.y2 = rect.y1 + 16; - rtgui_dc_draw_text(dc, "level", &rect); - rect.y1 += 22; - rect.y2 = rect.y1 + 16; - rtgui_dc_draw_text(dc, "lines", &rect); - rect.y1 += 22; - rect.y2 = rect.y1 + 16; - rtgui_dc_draw_text(dc, "score", &rect); - rtgui_dc_end_drawing(dc); - - /* start tetris game, removed later */ - rt_tetris_start(g_app_info.tetris); - return RT_FALSE; - } - else if ((event->type == RTGUI_EVENT_KBD)) - { - struct rtgui_event_kbd* ekbd = (struct rtgui_event_kbd*)event; - - if (ekbd->type == RTGUI_KEYDOWN) - { - if (ekbd->key == RTGUIK_RIGHT) - { - rt_tetris_right(g_app_info.tetris); - } - else if (ekbd->key == RTGUIK_LEFT) - { - rt_tetris_left(g_app_info.tetris); - } - else if (ekbd->key == RTGUIK_UP) - { - rt_tetris_rotate(g_app_info.tetris, RT_EOK); - } - else if (ekbd->key == RTGUIK_DOWN) - { - if( rt_tetris_drop(g_app_info.tetris) == -RT_ETIMEOUT - && rt_tetris_status(g_app_info.tetris) != RT_FALSE) - { - _game_over(); - } - } - } - } - - return rtgui_view_event_handler(widget, event); -} - -static void _timer_timeout(rtgui_timer_t* timer, void* parameter) -{ - if( rt_tetris_down(g_app_info.tetris) == -RT_ETIMEOUT) - { - _game_over(); - } -} - -static rt_bool_t workbench_event_handler(rtgui_widget_t *widget, rtgui_event_t *event) -{ - if (event->type == RTGUI_EVENT_KBD) - { - struct rtgui_event_kbd* ekbd = (struct rtgui_event_kbd*)event; - if (((ekbd->type == RTGUI_KEYUP) && ekbd->key == RTGUIK_HOME) - && !RTGUI_WORKBENCH_IS_MODAL_MODE(g_app_info.workbench)) - { - /* active home view */ - if (g_app_info.workbench->current_view != g_app_info.game_view) - { - rtgui_view_show(g_app_info.game_view, RT_FALSE); - return RT_TRUE; - } - } - } - - return rtgui_workbench_event_handler(widget, event); -} - -static void listitem_action_return(void) -{ - rtgui_view_destroy(g_app_info.game_view); - rtgui_list_view_destroy(g_app_info.function_view); - rtgui_workbench_close(g_app_info.workbench); -} - -static void listitem_action_start(void) -{ - /* create tetris modal instance */ - g_app_info.tetris = rt_tetris_create(16, 17); - - /* create tetris view instance */ - g_app_info.tetris_view = rt_tetris_view_create(RTGUI_WIDGET(g_app_info.game_view)); - - /* register tetris view to tetris modal */ - rt_tetris_add_view(g_app_info.tetris, g_app_info.tetris_view); - - /* create timer */ - g_app_info._timer = rtgui_timer_create(40, RT_TIMER_FLAG_PERIODIC, _timer_timeout, RT_NULL); - - /* this view can be focused */ - RTGUI_WIDGET(g_app_info.game_view)->flag |= RTGUI_WIDGET_FLAG_FOCUSABLE; - - /* set widget focus */ - rtgui_widget_focus(RTGUI_WIDGET(g_app_info.game_view)); - RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(g_app_info.game_view)) = RTGUI_RGB(0xff, 0xff, 0xff); - - rtgui_view_show(g_app_info.game_view, RT_FALSE); - rtgui_timer_start(g_app_info._timer); -} - -static void listitem_action_continue(void) -{ - -} - -static void listitem_action_adjust(void) -{ - -} - -static void listitem_action_description(void) -{ - -} - -static const struct rtgui_list_item function_list[] = -{ - {"ÐÂÓÎÏ·", RT_NULL, listitem_action_start, RT_NULL}, - {"¼ÌÐø", RT_NULL, listitem_action_continue, RT_NULL}, - {"µÈ¼¶", RT_NULL, listitem_action_adjust, RT_NULL}, - {"ÓÎϷ˵Ã÷", RT_NULL, listitem_action_description, RT_NULL}, - {"Í˳öÓÎÏ·", RT_NULL, listitem_action_return, RT_NULL}, -}; - -void main(void) -{ - rt_mq_t mq; - rtgui_rect_t rect; - - mq = rt_mq_create("tetris_ui", 256, 4, RT_IPC_FLAG_FIFO); - rtgui_thread_register(rt_thread_self(), mq); - - g_app_info.workbench = rtgui_workbench_create("main", "tetris"); - if (g_app_info.workbench == RT_NULL) - { - rt_kprintf("can't find panel 'main'\n"); - rt_mq_delete(mq); - - return; - } - rtgui_widget_set_event_handler(RTGUI_WIDGET(g_app_info.workbench), workbench_event_handler); - - /* add function view */ - rtgui_widget_get_rect(RTGUI_WIDGET(g_app_info.workbench), &rect); - - g_app_info.function_view = rtgui_list_view_create(function_list, - sizeof(function_list) / sizeof(struct rtgui_list_item), - &rect, - RTGUI_LIST_VIEW_LIST); - - rtgui_workbench_add_view(g_app_info.workbench, RTGUI_VIEW(g_app_info.function_view)); - - /* add home view */ - g_app_info.game_view = rtgui_view_create("game"); - - rtgui_widget_set_event_handler(RTGUI_WIDGET(g_app_info.game_view), game_view_event_handler); - rtgui_workbench_add_view(g_app_info.workbench, g_app_info.game_view); - - rtgui_view_show(RTGUI_VIEW(g_app_info.function_view), RT_FALSE); - - rtgui_workbench_event_loop(g_app_info.workbench); - rtgui_workbench_destroy(g_app_info.workbench); - - rtgui_thread_deregister(rt_thread_self()); - rt_mq_delete(mq); -} - +/* + * File : tetris_ui.c + * This file is part of RTGUI in RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-08-14 Yi.Qiu first version + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tetris.h" + +struct app_info +{ + rtgui_workbench_t* workbench; + rtgui_view_t* game_view; + rtgui_list_view_t* function_view; + + rt_tetris_t * tetris; + rt_tetris_view_t* tetris_view; + rtgui_timer_t* _timer; +}; +typedef struct app_info app_info; +static app_info g_app_info; + +static void _game_over(void) +{ + rtgui_timer_destory(g_app_info._timer); + rt_tetris_destory(g_app_info.tetris); + rt_tetris_view_destroy(g_app_info.tetris_view); + rt_kprintf("GAME OVER\n"); + + rtgui_view_show(g_app_info.function_view, RT_FALSE); +} + +static rt_bool_t game_view_event_handler(struct rtgui_widget* widget, struct rtgui_event* event) +{ + if (event->type == RTGUI_EVENT_PAINT) + { + struct rtgui_dc* dc; + rtgui_rect_t rect; + + /* draw child */ + rtgui_view_event_handler(widget, event); + + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) return -RT_ERROR; + rect.x1 = 96; + rect.y1 = 0; + rect.x2 = 128; + rect.y2 = 16; + rtgui_dc_draw_text(dc, "next", &rect); + rect.y1 += 30; + rect.y2 = rect.y1 + 16; + rtgui_dc_draw_text(dc, "level", &rect); + rect.y1 += 22; + rect.y2 = rect.y1 + 16; + rtgui_dc_draw_text(dc, "lines", &rect); + rect.y1 += 22; + rect.y2 = rect.y1 + 16; + rtgui_dc_draw_text(dc, "score", &rect); + rtgui_dc_end_drawing(dc); + + /* start tetris game, removed later */ + rt_tetris_start(g_app_info.tetris); + return RT_FALSE; + } + else if ((event->type == RTGUI_EVENT_KBD)) + { + struct rtgui_event_kbd* ekbd = (struct rtgui_event_kbd*)event; + + if (ekbd->type == RTGUI_KEYDOWN) + { + if (ekbd->key == RTGUIK_RIGHT) + { + rt_tetris_right(g_app_info.tetris); + } + else if (ekbd->key == RTGUIK_LEFT) + { + rt_tetris_left(g_app_info.tetris); + } + else if (ekbd->key == RTGUIK_UP) + { + rt_tetris_rotate(g_app_info.tetris, RT_EOK); + } + else if (ekbd->key == RTGUIK_DOWN) + { + if( rt_tetris_drop(g_app_info.tetris) == -RT_ETIMEOUT + && rt_tetris_status(g_app_info.tetris) != RT_FALSE) + { + _game_over(); + } + } + } + } + + return rtgui_view_event_handler(widget, event); +} + +static void _timer_timeout(rtgui_timer_t* timer, void* parameter) +{ + if( rt_tetris_down(g_app_info.tetris) == -RT_ETIMEOUT) + { + _game_over(); + } +} + +static rt_bool_t workbench_event_handler(rtgui_widget_t *widget, rtgui_event_t *event) +{ + if (event->type == RTGUI_EVENT_KBD) + { + struct rtgui_event_kbd* ekbd = (struct rtgui_event_kbd*)event; + if (((ekbd->type == RTGUI_KEYUP) && ekbd->key == RTGUIK_HOME) + && !RTGUI_WORKBENCH_IS_MODAL_MODE(g_app_info.workbench)) + { + /* active home view */ + if (g_app_info.workbench->current_view != g_app_info.game_view) + { + rtgui_view_show(g_app_info.game_view, RT_FALSE); + return RT_TRUE; + } + } + } + + return rtgui_workbench_event_handler(widget, event); +} + +static void listitem_action_return(void) +{ + rtgui_view_destroy(g_app_info.game_view); + rtgui_list_view_destroy(g_app_info.function_view); + rtgui_workbench_close(g_app_info.workbench); +} + +static void listitem_action_start(void) +{ + /* create tetris modal instance */ + g_app_info.tetris = rt_tetris_create(16, 17); + + /* create tetris view instance */ + g_app_info.tetris_view = rt_tetris_view_create(RTGUI_WIDGET(g_app_info.game_view)); + + /* register tetris view to tetris modal */ + rt_tetris_add_view(g_app_info.tetris, g_app_info.tetris_view); + + /* create timer */ + g_app_info._timer = rtgui_timer_create(40, RT_TIMER_FLAG_PERIODIC, _timer_timeout, RT_NULL); + + /* this view can be focused */ + RTGUI_WIDGET(g_app_info.game_view)->flag |= RTGUI_WIDGET_FLAG_FOCUSABLE; + + /* set widget focus */ + rtgui_widget_focus(RTGUI_WIDGET(g_app_info.game_view)); + RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(g_app_info.game_view)) = RTGUI_RGB(0xff, 0xff, 0xff); + + rtgui_view_show(g_app_info.game_view, RT_FALSE); + rtgui_timer_start(g_app_info._timer); +} + +static void listitem_action_continue(void) +{ + +} + +static void listitem_action_adjust(void) +{ + +} + +static void listitem_action_description(void) +{ + +} + +static const struct rtgui_list_item function_list[] = +{ + {"ÐÂÓÎÏ·", RT_NULL, listitem_action_start, RT_NULL}, + {"¼ÌÐø", RT_NULL, listitem_action_continue, RT_NULL}, + {"µÈ¼¶", RT_NULL, listitem_action_adjust, RT_NULL}, + {"ÓÎϷ˵Ã÷", RT_NULL, listitem_action_description, RT_NULL}, + {"Í˳öÓÎÏ·", RT_NULL, listitem_action_return, RT_NULL}, +}; + +void main(void) +{ + rt_mq_t mq; + rtgui_rect_t rect; + + mq = rt_mq_create("tetris_ui", 256, 4, RT_IPC_FLAG_FIFO); + rtgui_thread_register(rt_thread_self(), mq); + + g_app_info.workbench = rtgui_workbench_create("main", "tetris"); + if (g_app_info.workbench == RT_NULL) + { + rt_kprintf("can't find panel 'main'\n"); + rt_mq_delete(mq); + + return; + } + rtgui_widget_set_event_handler(RTGUI_WIDGET(g_app_info.workbench), workbench_event_handler); + + /* add function view */ + rtgui_widget_get_rect(RTGUI_WIDGET(g_app_info.workbench), &rect); + + g_app_info.function_view = rtgui_list_view_create(function_list, + sizeof(function_list) / sizeof(struct rtgui_list_item), + &rect, + RTGUI_LIST_VIEW_LIST); + + rtgui_workbench_add_view(g_app_info.workbench, RTGUI_VIEW(g_app_info.function_view)); + + /* add home view */ + g_app_info.game_view = rtgui_view_create("game"); + + rtgui_widget_set_event_handler(RTGUI_WIDGET(g_app_info.game_view), game_view_event_handler); + rtgui_workbench_add_view(g_app_info.workbench, g_app_info.game_view); + + rtgui_view_show(RTGUI_VIEW(g_app_info.function_view), RT_FALSE); + + rtgui_workbench_event_loop(g_app_info.workbench); + rtgui_workbench_destroy(g_app_info.workbench); + + rtgui_thread_deregister(rt_thread_self()); + rt_mq_delete(mq); +} + diff --git a/examples/module/tetris/tetris_view.c b/examples/module/tetris/tetris_view.c index dcb0cb312a4f4c46d690751684cb3c93a4cb9e78..722a4d315cc87a754b51c8c9b30f69073c9ee277 100644 --- a/examples/module/tetris/tetris_view.c +++ b/examples/module/tetris/tetris_view.c @@ -1,218 +1,218 @@ -/* - * File : tetris_view.c - * This file is part of RTGUI in RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-08-14 Yi.Qiu first version - */ - -#include -#include -#include -#include -#include -#include "tetris.h" - -static rt_err_t _rt_tetris_view_update(rt_tetris_view_t* thiz, rt_tetris_t* tetris); -static rt_err_t _rt_tetris_view_update_next_brick(rt_tetris_view_t* thiz, rt_tetris_t* tetris); -static rt_err_t _rt_tetris_view_update_level(rt_tetris_view_t* thiz, rt_tetris_t* tetris); -static rt_err_t _rt_tetris_view_update_score_and_lines(rt_tetris_view_t* thiz, rt_tetris_t* tetris); - -rt_tetris_view_t* rt_tetris_view_create(void* private) -{ - rt_tetris_view_t* thiz; - - RT_ASSERT(private != RT_NULL) - - thiz = (rt_tetris_view_t*)rt_malloc(sizeof(rt_tetris_view_t)); - thiz->width = 96; - thiz->height = 96; - - thiz->update = _rt_tetris_view_update; - thiz->update_next_brick = _rt_tetris_view_update_next_brick; - thiz->update_level = _rt_tetris_view_update_level; - thiz->update_score_and_lines = _rt_tetris_view_update_score_and_lines; - thiz->private = private; - - return thiz; -} - -rt_err_t rt_tetris_view_destroy(rt_tetris_view_t* thiz) -{ - RT_ASSERT(thiz != RT_NULL); - - rt_free(thiz); - - return RT_EOK; -} - -static rt_err_t _rt_tetris_view_update_next_brick(rt_tetris_view_t* thiz, rt_tetris_t* tetris) -{ - struct rtgui_dc* dc; - struct rtgui_rect rect; - rt_uint32_t width; - rt_uint32_t ppb, i; - rtgui_widget_t* widget; - rt_uint32_t* next_brick; - - RT_ASSERT(thiz != RT_NULL); - RT_ASSERT(tetris != RT_NULL); - - next_brick = rt_tetris_next_brick(tetris); - widget = (rtgui_widget_t*)thiz->private; - width = rt_tetris_width(tetris); - /* pixel per block */ - ppb = thiz->width / width; - - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) return -RT_ERROR; - - rect.x1 = 100; - rect.x2 = rect.x1 + 4 * ppb; - rect.y1 = 16; - rect.y2 = rect.y1 + 2 * ppb; - - RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0xff, 0xff); - rtgui_dc_fill_rect(dc, &rect); - - for(i=0; i<4; i++) - { - rt_uint32_t y = next_brick[i] / width; - rt_uint32_t x = next_brick[i] % width; - - rect.x1 = 100 + ppb * (x - 6); - rect.x2 = rect.x1 + ppb - 1; - rect.y1 = 16 + ppb * y ; - rect.y2 = rect.y1 + ppb - 1; - - RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0x00, 0x00); - rtgui_dc_fill_rect(dc, &rect); - } - - rtgui_dc_end_drawing(dc); - - return RT_EOK; -} - -static rt_err_t _rt_tetris_view_update_level(rt_tetris_view_t* thiz, rt_tetris_t* tetris) -{ - struct rtgui_dc* dc; - struct rtgui_rect rect; - rtgui_widget_t* widget; - char text[4]; - - RT_ASSERT(thiz != RT_NULL); - RT_ASSERT(tetris != RT_NULL); - - widget = (rtgui_widget_t*)thiz->private; - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) return -RT_ERROR; - - rect.x1 = 96; - rect.y1 = 42; - rect.x2 = 128; - rect.y2 = rect.y1 + 10; - RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0xff, 0xff); - rtgui_dc_fill_rect(dc, &rect); - rt_sprintf(text, "%d", rt_tetris_level(tetris)); - RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0x00, 0x00); - rtgui_dc_draw_text(dc, text, &rect); - - /* Redraw panel */ - rtgui_dc_end_drawing(dc); - - return RT_EOK; -} - -static rt_err_t _rt_tetris_view_update_score_and_lines(rt_tetris_view_t* thiz, rt_tetris_t* tetris) -{ - struct rtgui_dc* dc; - struct rtgui_rect rect; - rtgui_widget_t* widget; - char text[4]; - - RT_ASSERT(thiz != RT_NULL); - RT_ASSERT(tetris != RT_NULL); - - widget = (rtgui_widget_t*)thiz->private; - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) return -RT_ERROR; - - rect.x1 = 96; - rect.y1 = 64; - rect.x2 = 128; - rect.y2 = rect.y1 + 10; - RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0xff, 0xff); - rtgui_dc_fill_rect(dc, &rect); - rt_sprintf(text, "%d", rt_tetris_lines(tetris)); - RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0x00, 0x00); - rtgui_dc_draw_text(dc, text, &rect); - - rect.y1 += 22; - rect.y2 = rect.y1 + 10; - RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0xff, 0xff); - rtgui_dc_fill_rect(dc, &rect); - rt_sprintf(text, "%d", rt_tetris_score(tetris)); - RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0x00, 0x00); - rtgui_dc_draw_text(dc, text, &rect); - - /* Redraw panel */ - rtgui_dc_end_drawing(dc); - - return RT_EOK; -} - -static rt_err_t _rt_tetris_view_update(rt_tetris_view_t* thiz, rt_tetris_t* tetris) -{ - struct rtgui_dc* dc; - struct rtgui_rect rect; - rt_uint32_t width, height; - rt_uint32_t j,k, ppb; - rtgui_widget_t* widget; - - RT_ASSERT(thiz != RT_NULL); - RT_ASSERT(tetris != RT_NULL); - - widget = (rtgui_widget_t*)thiz->private; - width = rt_tetris_width(tetris); - height = rt_tetris_height(tetris); - ppb = thiz->width / width; - - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) return -RT_ERROR; - - /* Redraw panel */ - for(j=0; j +#include +#include +#include +#include +#include "tetris.h" + +static rt_err_t _rt_tetris_view_update(rt_tetris_view_t* thiz, rt_tetris_t* tetris); +static rt_err_t _rt_tetris_view_update_next_brick(rt_tetris_view_t* thiz, rt_tetris_t* tetris); +static rt_err_t _rt_tetris_view_update_level(rt_tetris_view_t* thiz, rt_tetris_t* tetris); +static rt_err_t _rt_tetris_view_update_score_and_lines(rt_tetris_view_t* thiz, rt_tetris_t* tetris); + +rt_tetris_view_t* rt_tetris_view_create(void* private) +{ + rt_tetris_view_t* thiz; + + RT_ASSERT(private != RT_NULL) + + thiz = (rt_tetris_view_t*)rt_malloc(sizeof(rt_tetris_view_t)); + thiz->width = 96; + thiz->height = 96; + + thiz->update = _rt_tetris_view_update; + thiz->update_next_brick = _rt_tetris_view_update_next_brick; + thiz->update_level = _rt_tetris_view_update_level; + thiz->update_score_and_lines = _rt_tetris_view_update_score_and_lines; + thiz->private = private; + + return thiz; +} + +rt_err_t rt_tetris_view_destroy(rt_tetris_view_t* thiz) +{ + RT_ASSERT(thiz != RT_NULL); + + rt_free(thiz); + + return RT_EOK; +} + +static rt_err_t _rt_tetris_view_update_next_brick(rt_tetris_view_t* thiz, rt_tetris_t* tetris) +{ + struct rtgui_dc* dc; + struct rtgui_rect rect; + rt_uint32_t width; + rt_uint32_t ppb, i; + rtgui_widget_t* widget; + rt_uint32_t* next_brick; + + RT_ASSERT(thiz != RT_NULL); + RT_ASSERT(tetris != RT_NULL); + + next_brick = rt_tetris_next_brick(tetris); + widget = (rtgui_widget_t*)thiz->private; + width = rt_tetris_width(tetris); + /* pixel per block */ + ppb = thiz->width / width; + + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) return -RT_ERROR; + + rect.x1 = 100; + rect.x2 = rect.x1 + 4 * ppb; + rect.y1 = 16; + rect.y2 = rect.y1 + 2 * ppb; + + RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0xff, 0xff); + rtgui_dc_fill_rect(dc, &rect); + + for(i=0; i<4; i++) + { + rt_uint32_t y = next_brick[i] / width; + rt_uint32_t x = next_brick[i] % width; + + rect.x1 = 100 + ppb * (x - 6); + rect.x2 = rect.x1 + ppb - 1; + rect.y1 = 16 + ppb * y ; + rect.y2 = rect.y1 + ppb - 1; + + RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0x00, 0x00); + rtgui_dc_fill_rect(dc, &rect); + } + + rtgui_dc_end_drawing(dc); + + return RT_EOK; +} + +static rt_err_t _rt_tetris_view_update_level(rt_tetris_view_t* thiz, rt_tetris_t* tetris) +{ + struct rtgui_dc* dc; + struct rtgui_rect rect; + rtgui_widget_t* widget; + char text[4]; + + RT_ASSERT(thiz != RT_NULL); + RT_ASSERT(tetris != RT_NULL); + + widget = (rtgui_widget_t*)thiz->private; + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) return -RT_ERROR; + + rect.x1 = 96; + rect.y1 = 42; + rect.x2 = 128; + rect.y2 = rect.y1 + 10; + RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0xff, 0xff); + rtgui_dc_fill_rect(dc, &rect); + rt_sprintf(text, "%d", rt_tetris_level(tetris)); + RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0x00, 0x00); + rtgui_dc_draw_text(dc, text, &rect); + + /* Redraw panel */ + rtgui_dc_end_drawing(dc); + + return RT_EOK; +} + +static rt_err_t _rt_tetris_view_update_score_and_lines(rt_tetris_view_t* thiz, rt_tetris_t* tetris) +{ + struct rtgui_dc* dc; + struct rtgui_rect rect; + rtgui_widget_t* widget; + char text[4]; + + RT_ASSERT(thiz != RT_NULL); + RT_ASSERT(tetris != RT_NULL); + + widget = (rtgui_widget_t*)thiz->private; + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) return -RT_ERROR; + + rect.x1 = 96; + rect.y1 = 64; + rect.x2 = 128; + rect.y2 = rect.y1 + 10; + RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0xff, 0xff); + rtgui_dc_fill_rect(dc, &rect); + rt_sprintf(text, "%d", rt_tetris_lines(tetris)); + RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0x00, 0x00); + rtgui_dc_draw_text(dc, text, &rect); + + rect.y1 += 22; + rect.y2 = rect.y1 + 10; + RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0xff, 0xff); + rtgui_dc_fill_rect(dc, &rect); + rt_sprintf(text, "%d", rt_tetris_score(tetris)); + RTGUI_DC_BC(dc) = RTGUI_RGB(0xff, 0x00, 0x00); + rtgui_dc_draw_text(dc, text, &rect); + + /* Redraw panel */ + rtgui_dc_end_drawing(dc); + + return RT_EOK; +} + +static rt_err_t _rt_tetris_view_update(rt_tetris_view_t* thiz, rt_tetris_t* tetris) +{ + struct rtgui_dc* dc; + struct rtgui_rect rect; + rt_uint32_t width, height; + rt_uint32_t j,k, ppb; + rtgui_widget_t* widget; + + RT_ASSERT(thiz != RT_NULL); + RT_ASSERT(tetris != RT_NULL); + + widget = (rtgui_widget_t*)thiz->private; + width = rt_tetris_width(tetris); + height = rt_tetris_height(tetris); + ppb = thiz->width / width; + + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) return -RT_ERROR; + + /* Redraw panel */ + for(j=0; j -#include /* 为了解æžä¸»æœºå，需è¦åŒ…å«netdb.h头文件 */ -#include /* 使用BSD socket，需è¦åŒ…å«sockets.h头文件 */ - -#define BUFSZ 1024 - -static const char send_data[] = "This is TCP Client from RT-Thread."; /* å‘é€ç”¨åˆ°çš„æ•°æ® */ -void tcpclient(const char* url, int port) -{ - char *recv_data; - struct hostent *host; - int sock, bytes_received; - struct sockaddr_in server_addr; - - /* 通过函数入å£å‚æ•°url获得host地å€ï¼ˆå¦‚果是域å，会åšåŸŸå解æžï¼‰ */ - host = gethostbyname(url); - - /* 分é…用于存放接收数æ®çš„缓冲 */ - recv_data = rt_malloc(BUFSZ); - if (recv_data == RT_NULL) - { - rt_kprintf("No memory\n"); - return; - } - - /* 创建一个socket，类型是SOCKET_STREAM，TCP类型 */ - if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1) - { - /* 创建socket失败 */ - rt_kprintf("Socket error\n"); - - /* 释放接收缓冲 */ - rt_free(recv_data); - return; - } - - /* åˆå§‹åŒ–预连接的æœåŠ¡ç«¯åœ°å€ */ - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(port); - server_addr.sin_addr = *((struct in_addr *)host->h_addr); - rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero)); - - /* 连接到æœåŠ¡ç«¯ */ - if (connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1) - { - /* 连接失败 */ - rt_kprintf("Connect fail!\n"); - lwip_close(sock); - - /*释放接收缓冲 */ - rt_free(recv_data); - return; - } - - while(1) - { - /* 从sock连接中接收最大BUFSZ - 1å­—èŠ‚æ•°æ® */ - bytes_received = recv(sock, recv_data, BUFSZ - 1, 0); - if (bytes_received <= 0) - { - /* 接收失败，关闭这个连接 */ - lwip_close(sock); - - /* 释放接收缓冲 */ - rt_free(recv_data); - break; - } - - /* 有接收到数æ®ï¼ŒæŠŠæœ«ç«¯æ¸…零 */ - recv_data[bytes_received] = '\0'; - - if (strcmp(recv_data , "q") == 0 || strcmp(recv_data , "Q") == 0) - { - /* 如果是首字æ¯æ˜¯q或Q，关闭这个连接 */ - lwip_close(sock); - - /* 释放接收缓冲 */ - rt_free(recv_data); - break; - } - else - { - /* åœ¨æŽ§åˆ¶ç»ˆç«¯æ˜¾ç¤ºæ”¶åˆ°çš„æ•°æ® */ - rt_kprintf("\nRecieved data = %s " , recv_data); - } - - /* å‘é€æ•°æ®åˆ°sock连接 */ - send(sock,send_data,strlen(send_data), 0); - } - - return; -} - -#ifdef RT_USING_FINSH -#include -/* 输出tcpclient函数到finsh shell中 */ -FINSH_FUNCTION_EXPORT(tcpclient, startup tcp client); -#endif +#include +#include /* 为了解æžä¸»æœºå，需è¦åŒ…å«netdb.h头文件 */ +#include /* 使用BSD socket，需è¦åŒ…å«sockets.h头文件 */ + +#define BUFSZ 1024 + +static const char send_data[] = "This is TCP Client from RT-Thread."; /* å‘é€ç”¨åˆ°çš„æ•°æ® */ +void tcpclient(const char* url, int port) +{ + char *recv_data; + struct hostent *host; + int sock, bytes_received; + struct sockaddr_in server_addr; + + /* 通过函数入å£å‚æ•°url获得host地å€ï¼ˆå¦‚果是域å，会åšåŸŸå解æžï¼‰ */ + host = gethostbyname(url); + + /* 分é…用于存放接收数æ®çš„缓冲 */ + recv_data = rt_malloc(BUFSZ); + if (recv_data == RT_NULL) + { + rt_kprintf("No memory\n"); + return; + } + + /* 创建一个socket，类型是SOCKET_STREAM，TCP类型 */ + if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1) + { + /* 创建socket失败 */ + rt_kprintf("Socket error\n"); + + /* 释放接收缓冲 */ + rt_free(recv_data); + return; + } + + /* åˆå§‹åŒ–预连接的æœåŠ¡ç«¯åœ°å€ */ + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(port); + server_addr.sin_addr = *((struct in_addr *)host->h_addr); + rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero)); + + /* 连接到æœåŠ¡ç«¯ */ + if (connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1) + { + /* 连接失败 */ + rt_kprintf("Connect fail!\n"); + lwip_close(sock); + + /*释放接收缓冲 */ + rt_free(recv_data); + return; + } + + while(1) + { + /* 从sock连接中接收最大BUFSZ - 1å­—èŠ‚æ•°æ® */ + bytes_received = recv(sock, recv_data, BUFSZ - 1, 0); + if (bytes_received <= 0) + { + /* 接收失败，关闭这个连接 */ + lwip_close(sock); + + /* 释放接收缓冲 */ + rt_free(recv_data); + break; + } + + /* 有接收到数æ®ï¼ŒæŠŠæœ«ç«¯æ¸…零 */ + recv_data[bytes_received] = '\0'; + + if (strcmp(recv_data , "q") == 0 || strcmp(recv_data , "Q") == 0) + { + /* 如果是首字æ¯æ˜¯q或Q，关闭这个连接 */ + lwip_close(sock); + + /* 释放接收缓冲 */ + rt_free(recv_data); + break; + } + else + { + /* åœ¨æŽ§åˆ¶ç»ˆç«¯æ˜¾ç¤ºæ”¶åˆ°çš„æ•°æ® */ + rt_kprintf("\nRecieved data = %s " , recv_data); + } + + /* å‘é€æ•°æ®åˆ°sock连接 */ + send(sock,send_data,strlen(send_data), 0); + } + + return; +} + +#ifdef RT_USING_FINSH +#include +/* 输出tcpclient函数到finsh shell中 */ +FINSH_FUNCTION_EXPORT(tcpclient, startup tcp client); +#endif diff --git a/examples/network/tcpsendpacket.c b/examples/network/tcpsendpacket.c index 328b9df7c9c230e6881e4773bf6726d63135c35c..50841e0149d192bc244c42a0fc41e40a41d133d4 100644 --- a/examples/network/tcpsendpacket.c +++ b/examples/network/tcpsendpacket.c @@ -1,63 +1,63 @@ -#include -#include /* ΪÁ˽âÎöÖ÷»úÃû£¬ÐèÒª°üº¬netdb.hÍ·Îļþ */ -#include /* ʹÓÃBSD socket£¬ÐèÒª°üº¬sockets.hÍ·Îļþ */ - -void tcp_senddata(const char* url, int port, int length) -{ - struct hostent *host; - int sock, err, result, timeout, index; - struct sockaddr_in server_addr; - rt_uint8_t *buffer_ptr; - - /* ͨ¹ýº¯ÊýÈë¿Ú²ÎÊýurl»ñµÃhostµØÖ·£¨Èç¹ûÊÇÓòÃû£¬»á×öÓòÃû½âÎö£© */ - host = gethostbyname(url); - /* ´´½¨Ò»¸ösocket£¬ÀàÐÍÊÇSOCKET_STREAM£¬TCPÀàÐÍ */ - if ((sock = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP)) == -1) - { - /* ´´½¨socketʧ°Ü */ - rt_kprintf("Socket error\n"); - return; - } - - /* ÉñÆæÄÚ´æ */ - buffer_ptr = rt_malloc(length); - /* ¹¹Ôì·¢ÉúÊý¾Ý */ - for (index = 0; index < length; index ++) - buffer_ptr[index] = index & 0xff; - - timeout = 100; - /* ÉèÖ÷¢Ëͳ¬Ê±Ê±¼ä100ms */ - lwip_setsockopt(sock, SOL_SOCKET, SO_SNDTIMEO, &timeout, sizeof(timeout)); - /* ³õʼ»¯Ô¤Á¬½ÓµÄ·þÎñ¶ËµØÖ· */ - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(port); - server_addr.sin_addr = *((struct in_addr *)host->h_addr); - rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero)); - - /* Á¬½Óµ½·þÎñ¶Ë */ - err = connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)); - rt_kprintf("TCP thread connect error code: %d\n", err); - - while(1) - { - /* ·¢ËÍÊý¾Ýµ½sockÁ¬½Ó */ - result = send(sock, buffer_ptr, length, MSG_DONTWAIT); - if(result == -1) //Êý¾Ý·¢ËÍ´íÎó´¦Àí - { - rt_kprintf("TCP thread send error: %d\n", result); - lwip_close(sock); //¹Ø±ÕÁ¬½Ó£¬ÖØд´½¨Á¬½Ó - rt_thread_delay(10); - if ((sock = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP)) == -1) - rt_kprintf("TCP Socket error:%d\n",sock); - err = connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)); - rt_kprintf("TCP thread connect error code: %d\n", err); - } - } -} - -#ifdef RT_USING_FINSH -#include -/* Êä³ötcpclientº¯Êýµ½finsh shellÖÐ */ -FINSH_FUNCTION_EXPORT(tcp_senddata, send a packet through tcp connection); -#endif - +#include +#include /* ΪÁ˽âÎöÖ÷»úÃû£¬ÐèÒª°üº¬netdb.hÍ·Îļþ */ +#include /* ʹÓÃBSD socket£¬ÐèÒª°üº¬sockets.hÍ·Îļþ */ + +void tcp_senddata(const char* url, int port, int length) +{ + struct hostent *host; + int sock, err, result, timeout, index; + struct sockaddr_in server_addr; + rt_uint8_t *buffer_ptr; + + /* ͨ¹ýº¯ÊýÈë¿Ú²ÎÊýurl»ñµÃhostµØÖ·£¨Èç¹ûÊÇÓòÃû£¬»á×öÓòÃû½âÎö£© */ + host = gethostbyname(url); + /* ´´½¨Ò»¸ösocket£¬ÀàÐÍÊÇSOCKET_STREAM£¬TCPÀàÐÍ */ + if ((sock = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP)) == -1) + { + /* ´´½¨socketʧ°Ü */ + rt_kprintf("Socket error\n"); + return; + } + + /* ÉñÆæÄÚ´æ */ + buffer_ptr = rt_malloc(length); + /* ¹¹Ôì·¢ÉúÊý¾Ý */ + for (index = 0; index < length; index ++) + buffer_ptr[index] = index & 0xff; + + timeout = 100; + /* ÉèÖ÷¢Ëͳ¬Ê±Ê±¼ä100ms */ + lwip_setsockopt(sock, SOL_SOCKET, SO_SNDTIMEO, &timeout, sizeof(timeout)); + /* ³õʼ»¯Ô¤Á¬½ÓµÄ·þÎñ¶ËµØÖ· */ + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(port); + server_addr.sin_addr = *((struct in_addr *)host->h_addr); + rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero)); + + /* Á¬½Óµ½·þÎñ¶Ë */ + err = connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)); + rt_kprintf("TCP thread connect error code: %d\n", err); + + while(1) + { + /* ·¢ËÍÊý¾Ýµ½sockÁ¬½Ó */ + result = send(sock, buffer_ptr, length, MSG_DONTWAIT); + if(result == -1) //Êý¾Ý·¢ËÍ´íÎó´¦Àí + { + rt_kprintf("TCP thread send error: %d\n", result); + lwip_close(sock); //¹Ø±ÕÁ¬½Ó£¬ÖØд´½¨Á¬½Ó + rt_thread_delay(10); + if ((sock = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP)) == -1) + rt_kprintf("TCP Socket error:%d\n",sock); + err = connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)); + rt_kprintf("TCP thread connect error code: %d\n", err); + } + } +} + +#ifdef RT_USING_FINSH +#include +/* Êä³ötcpclientº¯Êýµ½finsh shellÖÐ */ +FINSH_FUNCTION_EXPORT(tcp_senddata, send a packet through tcp connection); +#endif + diff --git a/examples/network/tcpserver.c b/examples/network/tcpserver.c index 6d83acc1b29b77d8859a3a0dc8d0cda2e04119c4..54b8c9301d4ed71513c5984c12a82f6d66e22a47 100644 --- a/examples/network/tcpserver.c +++ b/examples/network/tcpserver.c @@ -1,122 +1,122 @@ -#include -#include /* 使用BSD Socket接å£å¿…须包å«sockets.h这个头文件 */ - -static const char send_data[] = "This is TCP Server from RT-Thread."; /* å‘é€ç”¨åˆ°çš„æ•°æ® */ -void tcpserv(void* parameter) -{ - char *recv_data; /* 用于接收的指针，åŽé¢ä¼šåšä¸€æ¬¡åŠ¨æ€åˆ†é…以请求å¯ç”¨å†…å­˜ */ - rt_uint32_t sin_size; - int sock, connected, bytes_received; - struct sockaddr_in server_addr, client_addr; - rt_bool_t stop = RT_FALSE; /* åœæ­¢æ ‡å¿— */ - - recv_data = rt_malloc(1024); /* 分é…接收用的数æ®ç¼“冲 */ - if (recv_data == RT_NULL) - { - rt_kprintf("No memory\n"); - return; - } - - /* 一个socket在使用å‰ï¼Œéœ€è¦é¢„先创建出æ¥ï¼ŒæŒ‡å®šSOCK_STREAM为TCPçš„socket */ - if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1) - { - /* åˆ›å»ºå¤±è´¥çš„é”™è¯¯å¤„ç† */ - rt_kprintf("Socket error\n"); - - /* 释放已分é…的接收缓冲 */ - rt_free(recv_data); - return; - } - - /* åˆå§‹åŒ–æœåŠ¡ç«¯åœ°å€ */ - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(5000); /* æœåŠ¡ç«¯å·¥ä½œçš„ç«¯å£ */ - server_addr.sin_addr.s_addr = INADDR_ANY; - rt_memset(&(server_addr.sin_zero),8, sizeof(server_addr.sin_zero)); - - /* 绑定socket到æœåŠ¡ç«¯åœ°å€ */ - if (bind(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1) - { - /* 绑定失败 */ - rt_kprintf("Unable to bind\n"); - - /* 释放已分é…的接收缓冲 */ - rt_free(recv_data); - return; - } - - /* 在socketä¸Šè¿›è¡Œç›‘å¬ */ - if (listen(sock, 5) == -1) - { - rt_kprintf("Listen error\n"); - - /* release recv buffer */ - rt_free(recv_data); - return; - } - - rt_kprintf("\nTCPServer Waiting for client on port 5000...\n"); - while(stop != RT_TRUE) - { - sin_size = sizeof(struct sockaddr_in); - - /* 接å—一个客户端连接socket的请求，这个函数调用是阻塞å¼çš„ */ - connected = accept(sock, (struct sockaddr *)&client_addr, &sin_size); - /* 返回的是连接æˆåŠŸçš„socket */ - - /* 接å—返回的client_addr指å‘了客户端的地å€ä¿¡æ¯ */ - rt_kprintf("I got a connection from (%s , %d)\n", - inet_ntoa(client_addr.sin_addr),ntohs(client_addr.sin_port)); - - /* å®¢æˆ·ç«¯è¿žæŽ¥çš„å¤„ç† */ - while (1) - { - /* å‘é€æ•°æ®åˆ°connected socket */ - send(connected, send_data, strlen(send_data), 0); - - /* 从connected socket中接收数æ®ï¼ŒæŽ¥æ”¶buffer是1024大å°ï¼Œä½†å¹¶ä¸ä¸€å®šèƒ½å¤Ÿæ”¶åˆ°1024大å°çš„æ•°æ® */ - bytes_received = recv(connected,recv_data, 1024, 0); - if (bytes_received <= 0) - { - /* 接收失败，关闭这个connected socket */ - lwip_close(connected); - break; - } - - /* 有接收到数æ®ï¼ŒæŠŠæœ«ç«¯æ¸…零 */ - recv_data[bytes_received] = '\0'; - if (strcmp(recv_data , "q") == 0 || strcmp(recv_data , "Q") == 0) - { - /* 如果是首字æ¯æ˜¯q或Q，关闭这个连接 */ - lwip_close(connected); - break; - } - else if (strcmp(recv_data, "exit") == 0) - { - /* 如果接收的是exit，则关闭整个æœåŠ¡ç«¯ */ - lwip_close(connected); - stop = RT_TRUE; - break; - } - else - { - /* åœ¨æŽ§åˆ¶ç»ˆç«¯æ˜¾ç¤ºæ”¶åˆ°çš„æ•°æ® */ - rt_kprintf("RECIEVED DATA = %s \n" , recv_data); - } - } - } - - /* 退出æœåŠ¡ */ - lwip_close(sock); - - /* 释放接收缓冲 */ - rt_free(recv_data); - - return ; -} - -#ifdef RT_USING_FINSH -#include -/* 输出tcpserv函数到finsh shell中 */ -FINSH_FUNCTION_EXPORT(tcpserv, startup tcp server); -#endif +#include +#include /* 使用BSD Socket接å£å¿…须包å«sockets.h这个头文件 */ + +static const char send_data[] = "This is TCP Server from RT-Thread."; /* å‘é€ç”¨åˆ°çš„æ•°æ® */ +void tcpserv(void* parameter) +{ + char *recv_data; /* 用于接收的指针，åŽé¢ä¼šåšä¸€æ¬¡åŠ¨æ€åˆ†é…以请求å¯ç”¨å†…å­˜ */ + rt_uint32_t sin_size; + int sock, connected, bytes_received; + struct sockaddr_in server_addr, client_addr; + rt_bool_t stop = RT_FALSE; /* åœæ­¢æ ‡å¿— */ + + recv_data = rt_malloc(1024); /* 分é…接收用的数æ®ç¼“冲 */ + if (recv_data == RT_NULL) + { + rt_kprintf("No memory\n"); + return; + } + + /* 一个socket在使用å‰ï¼Œéœ€è¦é¢„先创建出æ¥ï¼ŒæŒ‡å®šSOCK_STREAM为TCPçš„socket */ + if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1) + { + /* åˆ›å»ºå¤±è´¥çš„é”™è¯¯å¤„ç† */ + rt_kprintf("Socket error\n"); + + /* 释放已分é…的接收缓冲 */ + rt_free(recv_data); + return; + } + + /* åˆå§‹åŒ–æœåŠ¡ç«¯åœ°å€ */ + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(5000); /* æœåŠ¡ç«¯å·¥ä½œçš„ç«¯å£ */ + server_addr.sin_addr.s_addr = INADDR_ANY; + rt_memset(&(server_addr.sin_zero),8, sizeof(server_addr.sin_zero)); + + /* 绑定socket到æœåŠ¡ç«¯åœ°å€ */ + if (bind(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1) + { + /* 绑定失败 */ + rt_kprintf("Unable to bind\n"); + + /* 释放已分é…的接收缓冲 */ + rt_free(recv_data); + return; + } + + /* 在socketä¸Šè¿›è¡Œç›‘å¬ */ + if (listen(sock, 5) == -1) + { + rt_kprintf("Listen error\n"); + + /* release recv buffer */ + rt_free(recv_data); + return; + } + + rt_kprintf("\nTCPServer Waiting for client on port 5000...\n"); + while(stop != RT_TRUE) + { + sin_size = sizeof(struct sockaddr_in); + + /* 接å—一个客户端连接socket的请求，这个函数调用是阻塞å¼çš„ */ + connected = accept(sock, (struct sockaddr *)&client_addr, &sin_size); + /* 返回的是连接æˆåŠŸçš„socket */ + + /* 接å—返回的client_addr指å‘了客户端的地å€ä¿¡æ¯ */ + rt_kprintf("I got a connection from (%s , %d)\n", + inet_ntoa(client_addr.sin_addr),ntohs(client_addr.sin_port)); + + /* å®¢æˆ·ç«¯è¿žæŽ¥çš„å¤„ç† */ + while (1) + { + /* å‘é€æ•°æ®åˆ°connected socket */ + send(connected, send_data, strlen(send_data), 0); + + /* 从connected socket中接收数æ®ï¼ŒæŽ¥æ”¶buffer是1024大å°ï¼Œä½†å¹¶ä¸ä¸€å®šèƒ½å¤Ÿæ”¶åˆ°1024大å°çš„æ•°æ® */ + bytes_received = recv(connected,recv_data, 1024, 0); + if (bytes_received <= 0) + { + /* 接收失败，关闭这个connected socket */ + lwip_close(connected); + break; + } + + /* 有接收到数æ®ï¼ŒæŠŠæœ«ç«¯æ¸…零 */ + recv_data[bytes_received] = '\0'; + if (strcmp(recv_data , "q") == 0 || strcmp(recv_data , "Q") == 0) + { + /* 如果是首字æ¯æ˜¯q或Q，关闭这个连接 */ + lwip_close(connected); + break; + } + else if (strcmp(recv_data, "exit") == 0) + { + /* 如果接收的是exit，则关闭整个æœåŠ¡ç«¯ */ + lwip_close(connected); + stop = RT_TRUE; + break; + } + else + { + /* åœ¨æŽ§åˆ¶ç»ˆç«¯æ˜¾ç¤ºæ”¶åˆ°çš„æ•°æ® */ + rt_kprintf("RECIEVED DATA = %s \n" , recv_data); + } + } + } + + /* 退出æœåŠ¡ */ + lwip_close(sock); + + /* 释放接收缓冲 */ + rt_free(recv_data); + + return ; +} + +#ifdef RT_USING_FINSH +#include +/* 输出tcpserv函数到finsh shell中 */ +FINSH_FUNCTION_EXPORT(tcpserv, startup tcp server); +#endif diff --git a/examples/network/udpclient.c b/examples/network/udpclient.c index 041adb32c50d1e1e4ac7c0262d352538e5994658..50e0d39784ddfd5f7cbd22673ca3fd7303d46ea0 100644 --- a/examples/network/udpclient.c +++ b/examples/network/udpclient.c @@ -1,50 +1,50 @@ -#include -#include /* 为了解æžä¸»æœºå，需è¦åŒ…å«netdb.h头文件 */ -#include /* 使用BSD socket，需è¦åŒ…å«sockets.h头文件 */ - -const char send_data[] = "This is UDP Client from RT-Thread.\n"; /* å‘é€ç”¨åˆ°çš„æ•°æ® */ -void udpclient(const char* url, int port, int count) -{ - int sock; - struct hostent *host; - struct sockaddr_in server_addr; - - /* 通过函数入å£å‚æ•°url获得host地å€ï¼ˆå¦‚果是域å，会åšåŸŸå解æžï¼‰ */ - host= (struct hostent *) gethostbyname(url); - - /* 创建一个socket，类型是SOCK_DGRAM，UDP类型 */ - if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) == -1) - { - rt_kprintf("Socket error\n"); - return; - } - - /* åˆå§‹åŒ–预连接的æœåŠ¡ç«¯åœ°å€ */ - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(port); - server_addr.sin_addr = *((struct in_addr *)host->h_addr); - rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero)); - - /* 总计å‘é€countæ¬¡æ•°æ® */ - while (count) - { - /* å‘é€æ•°æ®åˆ°æœåŠ¡è¿œç«¯ */ - sendto(sock, send_data, strlen(send_data), 0, - (struct sockaddr *)&server_addr, sizeof(struct sockaddr)); - - /* 线程休眠一段时间 */ - rt_thread_delay(50); - - /* 计数值å‡ä¸€ */ - count --; - } - - /* 关闭这个socket */ - lwip_close(sock); -} - -#ifdef RT_USING_FINSH -#include -/* 输出udpclient函数到finsh shell中 */ -FINSH_FUNCTION_EXPORT(udpclient, startup udp client); -#endif +#include +#include /* 为了解æžä¸»æœºå，需è¦åŒ…å«netdb.h头文件 */ +#include /* 使用BSD socket，需è¦åŒ…å«sockets.h头文件 */ + +const char send_data[] = "This is UDP Client from RT-Thread.\n"; /* å‘é€ç”¨åˆ°çš„æ•°æ® */ +void udpclient(const char* url, int port, int count) +{ + int sock; + struct hostent *host; + struct sockaddr_in server_addr; + + /* 通过函数入å£å‚æ•°url获得host地å€ï¼ˆå¦‚果是域å，会åšåŸŸå解æžï¼‰ */ + host= (struct hostent *) gethostbyname(url); + + /* 创建一个socket，类型是SOCK_DGRAM，UDP类型 */ + if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) == -1) + { + rt_kprintf("Socket error\n"); + return; + } + + /* åˆå§‹åŒ–预连接的æœåŠ¡ç«¯åœ°å€ */ + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(port); + server_addr.sin_addr = *((struct in_addr *)host->h_addr); + rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero)); + + /* 总计å‘é€countæ¬¡æ•°æ® */ + while (count) + { + /* å‘é€æ•°æ®åˆ°æœåŠ¡è¿œç«¯ */ + sendto(sock, send_data, strlen(send_data), 0, + (struct sockaddr *)&server_addr, sizeof(struct sockaddr)); + + /* 线程休眠一段时间 */ + rt_thread_delay(50); + + /* 计数值å‡ä¸€ */ + count --; + } + + /* 关闭这个socket */ + lwip_close(sock); +} + +#ifdef RT_USING_FINSH +#include +/* 输出udpclient函数到finsh shell中 */ +FINSH_FUNCTION_EXPORT(udpclient, startup udp client); +#endif diff --git a/examples/network/udpserver.c b/examples/network/udpserver.c index ee84e9d06122edfb0bc530ea4a2216dbecd922e3..cacd93b8393a0bd91517511dc6d2959eea9789c9 100644 --- a/examples/network/udpserver.c +++ b/examples/network/udpserver.c @@ -1,86 +1,86 @@ -#include -#include /* 使用BSD socket，需è¦åŒ…å«sockets.h头文件 */ - -#define BUFSZ 1024 - -void udpserv(void* paramemter) -{ - int sock; - int bytes_read; - char *recv_data; - rt_uint32_t addr_len; - struct sockaddr_in server_addr, client_addr; - - /* 分é…接收用的数æ®ç¼“冲 */ - recv_data = rt_malloc(BUFSZ); - if (recv_data == RT_NULL) - { - /* 分é…内存失败，返回 */ - rt_kprintf("No memory\n"); - return; - } - - /* 创建一个socket，类型是SOCK_DGRAM，UDP类型 */ - if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) == -1) - { - rt_kprintf("Socket error\n"); - - /* 释放接收用的数æ®ç¼“冲 */ - rt_free(recv_data); - return; - } - - /* åˆå§‹åŒ–æœåŠ¡ç«¯åœ°å€ */ - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(5000); - server_addr.sin_addr.s_addr = INADDR_ANY; - rt_memset(&(server_addr.sin_zero),0, sizeof(server_addr.sin_zero)); - - /* 绑定socket到æœåŠ¡ç«¯åœ°å€ */ - if (bind(sock,(struct sockaddr *)&server_addr, - sizeof(struct sockaddr)) == -1) - { - /* 绑定地å€å¤±è´¥ */ - rt_kprintf("Bind error\n"); - - /* 释放接收用的数æ®ç¼“冲 */ - rt_free(recv_data); - return; - } - - addr_len = sizeof(struct sockaddr); - rt_kprintf("UDPServer Waiting for client on port 5000...\n"); - - while (1) - { - /* 从sock中收å–最大BUFSZ - 1å­—èŠ‚æ•°æ® */ - bytes_read = recvfrom(sock, recv_data, BUFSZ - 1, 0, - (struct sockaddr *)&client_addr, &addr_len); - /* UDPä¸åŒäºŽTCP，它基本ä¸ä¼šå‡ºçŽ°æ”¶å–çš„æ•°æ®å¤±è´¥çš„情况，除éžè®¾ç½®äº†è¶…时等待 */ - - recv_data[bytes_read] = '\0'; /* 把末端清零 */ - - /* è¾“å‡ºæŽ¥æ”¶çš„æ•°æ® */ - rt_kprintf("\n(%s , %d) said : ",inet_ntoa(client_addr.sin_addr), - ntohs(client_addr.sin_port)); - rt_kprintf("%s", recv_data); - - /* 如果接收数æ®æ˜¯exit，退出 */ - if (strcmp(recv_data, "exit") == 0) - { - lwip_close(sock); - - /* 释放接收用的数æ®ç¼“冲 */ - rt_free(recv_data); - break; - } - } - - return; -} - -#ifdef RT_USING_FINSH -#include -/* 输出udpserv函数到finsh shell中 */ -FINSH_FUNCTION_EXPORT(udpserv, startup udp server); -#endif +#include +#include /* 使用BSD socket，需è¦åŒ…å«sockets.h头文件 */ + +#define BUFSZ 1024 + +void udpserv(void* paramemter) +{ + int sock; + int bytes_read; + char *recv_data; + rt_uint32_t addr_len; + struct sockaddr_in server_addr, client_addr; + + /* 分é…接收用的数æ®ç¼“冲 */ + recv_data = rt_malloc(BUFSZ); + if (recv_data == RT_NULL) + { + /* 分é…内存失败，返回 */ + rt_kprintf("No memory\n"); + return; + } + + /* 创建一个socket，类型是SOCK_DGRAM，UDP类型 */ + if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) == -1) + { + rt_kprintf("Socket error\n"); + + /* 释放接收用的数æ®ç¼“冲 */ + rt_free(recv_data); + return; + } + + /* åˆå§‹åŒ–æœåŠ¡ç«¯åœ°å€ */ + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(5000); + server_addr.sin_addr.s_addr = INADDR_ANY; + rt_memset(&(server_addr.sin_zero),0, sizeof(server_addr.sin_zero)); + + /* 绑定socket到æœåŠ¡ç«¯åœ°å€ */ + if (bind(sock,(struct sockaddr *)&server_addr, + sizeof(struct sockaddr)) == -1) + { + /* 绑定地å€å¤±è´¥ */ + rt_kprintf("Bind error\n"); + + /* 释放接收用的数æ®ç¼“冲 */ + rt_free(recv_data); + return; + } + + addr_len = sizeof(struct sockaddr); + rt_kprintf("UDPServer Waiting for client on port 5000...\n"); + + while (1) + { + /* 从sock中收å–最大BUFSZ - 1å­—èŠ‚æ•°æ® */ + bytes_read = recvfrom(sock, recv_data, BUFSZ - 1, 0, + (struct sockaddr *)&client_addr, &addr_len); + /* UDPä¸åŒäºŽTCP，它基本ä¸ä¼šå‡ºçŽ°æ”¶å–çš„æ•°æ®å¤±è´¥çš„情况，除éžè®¾ç½®äº†è¶…时等待 */ + + recv_data[bytes_read] = '\0'; /* 把末端清零 */ + + /* è¾“å‡ºæŽ¥æ”¶çš„æ•°æ® */ + rt_kprintf("\n(%s , %d) said : ",inet_ntoa(client_addr.sin_addr), + ntohs(client_addr.sin_port)); + rt_kprintf("%s", recv_data); + + /* 如果接收数æ®æ˜¯exit，退出 */ + if (strcmp(recv_data, "exit") == 0) + { + lwip_close(sock); + + /* 释放接收用的数æ®ç¼“冲 */ + rt_free(recv_data); + break; + } + } + + return; +} + +#ifdef RT_USING_FINSH +#include +/* 输出udpserv函数到finsh shell中 */ +FINSH_FUNCTION_EXPORT(udpserv, startup udp server); +#endif diff --git a/examples/test/dhry.h b/examples/test/dhry.h index 02e7180e594aaaf351d0f0b8b4e5145679b1f34a..8f472338023eff50518d31bc66bc34c783ee27e6 100644 --- a/examples/test/dhry.h +++ b/examples/test/dhry.h @@ -1,412 +1,412 @@ -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry.h (part 1 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * Siemens AG, AUT E 51 - * Postfach 3220 - * 8520 Erlangen - * Germany (West) - * Phone: [+49]-9131-7-20330 - * (8-17 Central European Time) - * Usenet: ..!mcsun!unido!estevax!weicker - * - * Original Version (in Ada) published in - * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), - * pp. 1013 - 1030, together with the statistics - * on which the distribution of statements etc. is based. - * - * In this C version, the following C library functions are used: - * - strcpy, strcmp (inside the measurement loop) - * - printf, scanf (outside the measurement loop) - * In addition, Berkeley UNIX system calls "times ()" or "time ()" - * are used for execution time measurement. For measurements - * on other systems, these calls have to be changed. - * - * Collection of Results: - * Reinhold Weicker (address see above) and - * - * Rick Richardson - * PC Research. Inc. - * 94 Apple Orchard Drive - * Tinton Falls, NJ 07724 - * Phone: (201) 389-8963 (9-17 EST) - * Usenet: ...!uunet!pcrat!rick - * - * Please send results to Rick Richardson and/or Reinhold Weicker. - * Complete information should be given on hardware and software used. - * Hardware information includes: Machine type, CPU, type and size - * of caches; for microprocessors: clock frequency, memory speed - * (number of wait states). - * Software information includes: Compiler (and runtime library) - * manufacturer and version, compilation switches, OS version. - * The Operating System version may give an indication about the - * compiler; Dhrystone itself performs no OS calls in the measurement loop. - * - * The complete output generated by the program should be mailed - * such that at least some checks for correctness can be made. - * - *************************************************************************** - * - * History: This version C/2.1 has been made for two reasons: - * - * 1) There is an obvious need for a common C version of - * Dhrystone, since C is at present the most popular system - * programming language for the class of processors - * (microcomputers, minicomputers) where Dhrystone is used most. - * There should be, as far as possible, only one C version of - * Dhrystone such that results can be compared without - * restrictions. In the past, the C versions distributed - * by Rick Richardson (Version 1.1) and by Reinhold Weicker - * had small (though not significant) differences. - * - * 2) As far as it is possible without changes to the Dhrystone - * statistics, optimizing compilers should be prevented from - * removing significant statements. - * - * This C version has been developed in cooperation with - * Rick Richardson (Tinton Falls, NJ), it incorporates many - * ideas from the "Version 1.1" distributed previously by - * him over the UNIX network Usenet. - * I also thank Chaim Benedelac (National Semiconductor), - * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), - * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) - * for their help with comments on earlier versions of the - * benchmark. - * - * Changes: In the initialization part, this version follows mostly - * Rick Richardson's version distributed via Usenet, not the - * version distributed earlier via floppy disk by Reinhold Weicker. - * As a concession to older compilers, names have been made - * unique within the first 8 characters. - * Inside the measurement loop, this version follows the - * version previously distributed by Reinhold Weicker. - * - * At several places in the benchmark, code has been added, - * but within the measurement loop only in branches that - * are not executed. The intention is that optimizing compilers - * should be prevented from moving code out of the measurement - * loop, or from removing code altogether. Since the statements - * that are executed within the measurement loop have NOT been - * changed, the numbers defining the "Dhrystone distribution" - * (distribution of statements, operand types and locality) - * still hold. Except for sophisticated optimizing compilers, - * execution times for this version should be the same as - * for previous versions. - * - * Since it has proven difficult to subtract the time for the - * measurement loop overhead in a correct way, the loop check - * has been made a part of the benchmark. This does have - * an impact - though a very minor one - on the distribution - * statistics which have been updated for this version. - * - * All changes within the measurement loop are described - * and discussed in the companion paper "Rationale for - * Dhrystone version 2". - * - * Because of the self-imposed limitation that the order and - * distribution of the executed statements should not be - * changed, there are still cases where optimizing compilers - * may not generate code for some statements. To a certain - * degree, this is unavoidable for small synthetic benchmarks. - * Users of the benchmark are advised to check code listings - * whether code is generated for all statements of Dhrystone. - * - * Version 2.1 is identical to version 2.0 distributed via - * the UNIX network Usenet in March 1988 except that it corrects - * some minor deficiencies that were found by users of version 2.0. - * The only change within the measurement loop is that a - * non-executed "else" part was added to the "if" statement in - * Func_3, and a non-executed "else" part removed from Proc_3. - * - *************************************************************************** - * - * Defines: The following "Defines" are possible: - * -DREG=register (default: Not defined) - * As an approximation to what an average C programmer - * might do, the "register" storage class is applied - * (if enabled by -DREG=register) - * - for local variables, if they are used (dynamically) - * five or more times - * - for parameters if they are used (dynamically) - * six or more times - * Note that an optimal "register" strategy is - * compiler-dependent, and that "register" declarations - * do not necessarily lead to faster execution. - * -DNOSTRUCTASSIGN (default: Not defined) - * Define if the C compiler does not support - * assignment of structures. - * -DNOENUMS (default: Not defined) - * Define if the C compiler does not support - * enumeration types. - * -DTIMES (default) - * -DTIME - * The "times" function of UNIX (returning process times) - * or the "time" function (returning wallclock time) - * is used for measurement. - * For single user machines, "time ()" is adequate. For - * multi-user machines where you cannot get single-user - * access, use the "times ()" function. If you have - * neither, use a stopwatch in the dead of night. - * "printf"s are provided marking the points "Start Timer" - * and "Stop Timer". DO NOT use the UNIX "time(1)" - * command, as this will measure the total time to - * run this program, which will (erroneously) include - * the time to allocate storage (malloc) and to perform - * the initialization. - * -DHZ=nnn - * In Berkeley UNIX, the function "times" returns process - * time in 1/HZ seconds, with HZ = 60 for most systems. - * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY - * A VALUE. - * - *************************************************************************** - * - * Compilation model and measurement (IMPORTANT): - * - * This C version of Dhrystone consists of three files: - * - dhry.h (this file, containing global definitions and comments) - * - dhry_1.c (containing the code corresponding to Ada package Pack_1) - * - dhry_2.c (containing the code corresponding to Ada package Pack_2) - * - * The following "ground rules" apply for measurements: - * - Separate compilation - * - No procedure merging - * - Otherwise, compiler optimizations are allowed but should be indicated - * - Default results are those without register declarations - * See the companion paper "Rationale for Dhrystone Version 2" for a more - * detailed discussion of these ground rules. - * - * For 16-Bit processors (e.g. 80186, 80286), times for all compilation - * models ("small", "medium", "large" etc.) should be given if possible, - * together with a definition of these models for the compiler system used. - * - ************************************************************************** - * - * Dhrystone (C version) statistics: - * - * [Comment from the first distribution, updated for version 2. - * Note that because of language differences, the numbers are slightly - * different from the Ada version.] - * - * The following program contains statements of a high level programming - * language (here: C) in a distribution considered representative: - * - * assignments 52 (51.0 %) - * control statements 33 (32.4 %) - * procedure, function calls 17 (16.7 %) - * - * 103 statements are dynamically executed. The program is balanced with - * respect to the three aspects: - * - * - statement type - * - operand type - * - operand locality - * operand global, local, parameter, or constant. - * - * The combination of these three aspects is balanced only approximately. - * - * 1. Statement Type: - * ----------------- number - * - * V1 = V2 9 - * (incl. V1 = F(..) - * V = Constant 12 - * Assignment, 7 - * with array element - * Assignment, 6 - * with record component - * -- - * 34 34 - * - * X = Y +|-|"&&"|"|" Z 5 - * X = Y +|-|"==" Constant 6 - * X = X +|- 1 3 - * X = Y *|/ Z 2 - * X = Expression, 1 - * two operators - * X = Expression, 1 - * three operators - * -- - * 18 18 - * - * if .... 14 - * with "else" 7 - * without "else" 7 - * executed 3 - * not executed 4 - * for ... 7 | counted every time - * while ... 4 | the loop condition - * do ... while 1 | is evaluated - * switch ... 1 - * break 1 - * declaration with 1 - * initialization - * -- - * 34 34 - * - * P (...) procedure call 11 - * user procedure 10 - * library procedure 1 - * X = F (...) - * function call 6 - * user function 5 - * library function 1 - * -- - * 17 17 - * --- - * 103 - * - * The average number of parameters in procedure or function calls - * is 1.82 (not counting the function values as implicit parameters). - * - * - * 2. Operators - * ------------ - * number approximate - * percentage - * - * Arithmetic 32 50.8 - * - * + 21 33.3 - * - 7 11.1 - * * 3 4.8 - * / (int div) 1 1.6 - * - * Comparison 27 42.8 - * - * == 9 14.3 - * /= 4 6.3 - * > 1 1.6 - * < 3 4.8 - * >= 1 1.6 - * <= 9 14.3 - * - * Logic 4 6.3 - * - * && (AND-THEN) 1 1.6 - * | (OR) 1 1.6 - * ! (NOT) 2 3.2 - * - * -- ----- - * 63 100.1 - * - * - * 3. Operand Type (counted once per operand reference): - * --------------- - * number approximate - * percentage - * - * Integer 175 72.3 % - * Character 45 18.6 % - * Pointer 12 5.0 % - * String30 6 2.5 % - * Array 2 0.8 % - * Record 2 0.8 % - * --- ------- - * 242 100.0 % - * - * When there is an access path leading to the final operand (e.g. a record - * component), only the final data type on the access path is counted. - * - * - * 4. Operand Locality: - * ------------------- - * number approximate - * percentage - * - * local variable 114 47.1 % - * global variable 22 9.1 % - * parameter 45 18.6 % - * value 23 9.5 % - * reference 22 9.1 % - * function result 6 2.5 % - * constant 55 22.7 % - * --- ------- - * 242 100.0 % - * - * - * The program does not compute anything meaningful, but it is syntactically - * and semantically correct. All variables have a value assigned to them - * before they are used as a source operand. - * - * There has been no explicit effort to account for the effects of a - * cache, or to balance the use of long or short displacements for code or - * data. - * - *************************************************************************** - */ - -/* Compiler and system dependent definitions: */ - -#define Mic_secs_Per_Second 1000000.0 - /* Berkeley UNIX C returns process times in seconds/HZ */ - -#ifdef NOSTRUCTASSIGN -#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) -#else -#define structassign(d, s) d = s -#endif - -#ifdef NOENUM -#define Ident_1 0 -#define Ident_2 1 -#define Ident_3 2 -#define Ident_4 3 -#define Ident_5 4 - typedef int Enumeration; -#else - typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} - Enumeration; -#endif - /* for boolean and enumeration types in Ada, Pascal */ - -/* General definitions: */ - -// #include - /* for strcpy, strcmp */ -#include - -#define Null 0 - /* Value of a Null pointer */ -#define true 1 -#define false 0 - -typedef int One_Thirty; -typedef int One_Fifty; -typedef char Capital_Letter; -typedef int Boolean; -typedef char Str_30 [31]; -typedef int Arr_1_Dim [50]; -typedef int Arr_2_Dim [50] [50]; - -typedef struct record - { - struct record *Ptr_Comp; - Enumeration Discr; - union { - struct { - Enumeration Enum_Comp; - int Int_Comp; - char Str_Comp [31]; - } var_1; - struct { - Enumeration E_Comp_2; - char Str_2_Comp [31]; - } var_2; - struct { - char Ch_1_Comp; - char Ch_2_Comp; - } var_3; - } variant; - } Rec_Type, *Rec_Pointer; - - +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry.h (part 1 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * Siemens AG, AUT E 51 + * Postfach 3220 + * 8520 Erlangen + * Germany (West) + * Phone: [+49]-9131-7-20330 + * (8-17 Central European Time) + * Usenet: ..!mcsun!unido!estevax!weicker + * + * Original Version (in Ada) published in + * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), + * pp. 1013 - 1030, together with the statistics + * on which the distribution of statements etc. is based. + * + * In this C version, the following C library functions are used: + * - strcpy, strcmp (inside the measurement loop) + * - printf, scanf (outside the measurement loop) + * In addition, Berkeley UNIX system calls "times ()" or "time ()" + * are used for execution time measurement. For measurements + * on other systems, these calls have to be changed. + * + * Collection of Results: + * Reinhold Weicker (address see above) and + * + * Rick Richardson + * PC Research. Inc. + * 94 Apple Orchard Drive + * Tinton Falls, NJ 07724 + * Phone: (201) 389-8963 (9-17 EST) + * Usenet: ...!uunet!pcrat!rick + * + * Please send results to Rick Richardson and/or Reinhold Weicker. + * Complete information should be given on hardware and software used. + * Hardware information includes: Machine type, CPU, type and size + * of caches; for microprocessors: clock frequency, memory speed + * (number of wait states). + * Software information includes: Compiler (and runtime library) + * manufacturer and version, compilation switches, OS version. + * The Operating System version may give an indication about the + * compiler; Dhrystone itself performs no OS calls in the measurement loop. + * + * The complete output generated by the program should be mailed + * such that at least some checks for correctness can be made. + * + *************************************************************************** + * + * History: This version C/2.1 has been made for two reasons: + * + * 1) There is an obvious need for a common C version of + * Dhrystone, since C is at present the most popular system + * programming language for the class of processors + * (microcomputers, minicomputers) where Dhrystone is used most. + * There should be, as far as possible, only one C version of + * Dhrystone such that results can be compared without + * restrictions. In the past, the C versions distributed + * by Rick Richardson (Version 1.1) and by Reinhold Weicker + * had small (though not significant) differences. + * + * 2) As far as it is possible without changes to the Dhrystone + * statistics, optimizing compilers should be prevented from + * removing significant statements. + * + * This C version has been developed in cooperation with + * Rick Richardson (Tinton Falls, NJ), it incorporates many + * ideas from the "Version 1.1" distributed previously by + * him over the UNIX network Usenet. + * I also thank Chaim Benedelac (National Semiconductor), + * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), + * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) + * for their help with comments on earlier versions of the + * benchmark. + * + * Changes: In the initialization part, this version follows mostly + * Rick Richardson's version distributed via Usenet, not the + * version distributed earlier via floppy disk by Reinhold Weicker. + * As a concession to older compilers, names have been made + * unique within the first 8 characters. + * Inside the measurement loop, this version follows the + * version previously distributed by Reinhold Weicker. + * + * At several places in the benchmark, code has been added, + * but within the measurement loop only in branches that + * are not executed. The intention is that optimizing compilers + * should be prevented from moving code out of the measurement + * loop, or from removing code altogether. Since the statements + * that are executed within the measurement loop have NOT been + * changed, the numbers defining the "Dhrystone distribution" + * (distribution of statements, operand types and locality) + * still hold. Except for sophisticated optimizing compilers, + * execution times for this version should be the same as + * for previous versions. + * + * Since it has proven difficult to subtract the time for the + * measurement loop overhead in a correct way, the loop check + * has been made a part of the benchmark. This does have + * an impact - though a very minor one - on the distribution + * statistics which have been updated for this version. + * + * All changes within the measurement loop are described + * and discussed in the companion paper "Rationale for + * Dhrystone version 2". + * + * Because of the self-imposed limitation that the order and + * distribution of the executed statements should not be + * changed, there are still cases where optimizing compilers + * may not generate code for some statements. To a certain + * degree, this is unavoidable for small synthetic benchmarks. + * Users of the benchmark are advised to check code listings + * whether code is generated for all statements of Dhrystone. + * + * Version 2.1 is identical to version 2.0 distributed via + * the UNIX network Usenet in March 1988 except that it corrects + * some minor deficiencies that were found by users of version 2.0. + * The only change within the measurement loop is that a + * non-executed "else" part was added to the "if" statement in + * Func_3, and a non-executed "else" part removed from Proc_3. + * + *************************************************************************** + * + * Defines: The following "Defines" are possible: + * -DREG=register (default: Not defined) + * As an approximation to what an average C programmer + * might do, the "register" storage class is applied + * (if enabled by -DREG=register) + * - for local variables, if they are used (dynamically) + * five or more times + * - for parameters if they are used (dynamically) + * six or more times + * Note that an optimal "register" strategy is + * compiler-dependent, and that "register" declarations + * do not necessarily lead to faster execution. + * -DNOSTRUCTASSIGN (default: Not defined) + * Define if the C compiler does not support + * assignment of structures. + * -DNOENUMS (default: Not defined) + * Define if the C compiler does not support + * enumeration types. + * -DTIMES (default) + * -DTIME + * The "times" function of UNIX (returning process times) + * or the "time" function (returning wallclock time) + * is used for measurement. + * For single user machines, "time ()" is adequate. For + * multi-user machines where you cannot get single-user + * access, use the "times ()" function. If you have + * neither, use a stopwatch in the dead of night. + * "printf"s are provided marking the points "Start Timer" + * and "Stop Timer". DO NOT use the UNIX "time(1)" + * command, as this will measure the total time to + * run this program, which will (erroneously) include + * the time to allocate storage (malloc) and to perform + * the initialization. + * -DHZ=nnn + * In Berkeley UNIX, the function "times" returns process + * time in 1/HZ seconds, with HZ = 60 for most systems. + * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY + * A VALUE. + * + *************************************************************************** + * + * Compilation model and measurement (IMPORTANT): + * + * This C version of Dhrystone consists of three files: + * - dhry.h (this file, containing global definitions and comments) + * - dhry_1.c (containing the code corresponding to Ada package Pack_1) + * - dhry_2.c (containing the code corresponding to Ada package Pack_2) + * + * The following "ground rules" apply for measurements: + * - Separate compilation + * - No procedure merging + * - Otherwise, compiler optimizations are allowed but should be indicated + * - Default results are those without register declarations + * See the companion paper "Rationale for Dhrystone Version 2" for a more + * detailed discussion of these ground rules. + * + * For 16-Bit processors (e.g. 80186, 80286), times for all compilation + * models ("small", "medium", "large" etc.) should be given if possible, + * together with a definition of these models for the compiler system used. + * + ************************************************************************** + * + * Dhrystone (C version) statistics: + * + * [Comment from the first distribution, updated for version 2. + * Note that because of language differences, the numbers are slightly + * different from the Ada version.] + * + * The following program contains statements of a high level programming + * language (here: C) in a distribution considered representative: + * + * assignments 52 (51.0 %) + * control statements 33 (32.4 %) + * procedure, function calls 17 (16.7 %) + * + * 103 statements are dynamically executed. The program is balanced with + * respect to the three aspects: + * + * - statement type + * - operand type + * - operand locality + * operand global, local, parameter, or constant. + * + * The combination of these three aspects is balanced only approximately. + * + * 1. Statement Type: + * ----------------- number + * + * V1 = V2 9 + * (incl. V1 = F(..) + * V = Constant 12 + * Assignment, 7 + * with array element + * Assignment, 6 + * with record component + * -- + * 34 34 + * + * X = Y +|-|"&&"|"|" Z 5 + * X = Y +|-|"==" Constant 6 + * X = X +|- 1 3 + * X = Y *|/ Z 2 + * X = Expression, 1 + * two operators + * X = Expression, 1 + * three operators + * -- + * 18 18 + * + * if .... 14 + * with "else" 7 + * without "else" 7 + * executed 3 + * not executed 4 + * for ... 7 | counted every time + * while ... 4 | the loop condition + * do ... while 1 | is evaluated + * switch ... 1 + * break 1 + * declaration with 1 + * initialization + * -- + * 34 34 + * + * P (...) procedure call 11 + * user procedure 10 + * library procedure 1 + * X = F (...) + * function call 6 + * user function 5 + * library function 1 + * -- + * 17 17 + * --- + * 103 + * + * The average number of parameters in procedure or function calls + * is 1.82 (not counting the function values as implicit parameters). + * + * + * 2. Operators + * ------------ + * number approximate + * percentage + * + * Arithmetic 32 50.8 + * + * + 21 33.3 + * - 7 11.1 + * * 3 4.8 + * / (int div) 1 1.6 + * + * Comparison 27 42.8 + * + * == 9 14.3 + * /= 4 6.3 + * > 1 1.6 + * < 3 4.8 + * >= 1 1.6 + * <= 9 14.3 + * + * Logic 4 6.3 + * + * && (AND-THEN) 1 1.6 + * | (OR) 1 1.6 + * ! (NOT) 2 3.2 + * + * -- ----- + * 63 100.1 + * + * + * 3. Operand Type (counted once per operand reference): + * --------------- + * number approximate + * percentage + * + * Integer 175 72.3 % + * Character 45 18.6 % + * Pointer 12 5.0 % + * String30 6 2.5 % + * Array 2 0.8 % + * Record 2 0.8 % + * --- ------- + * 242 100.0 % + * + * When there is an access path leading to the final operand (e.g. a record + * component), only the final data type on the access path is counted. + * + * + * 4. Operand Locality: + * ------------------- + * number approximate + * percentage + * + * local variable 114 47.1 % + * global variable 22 9.1 % + * parameter 45 18.6 % + * value 23 9.5 % + * reference 22 9.1 % + * function result 6 2.5 % + * constant 55 22.7 % + * --- ------- + * 242 100.0 % + * + * + * The program does not compute anything meaningful, but it is syntactically + * and semantically correct. All variables have a value assigned to them + * before they are used as a source operand. + * + * There has been no explicit effort to account for the effects of a + * cache, or to balance the use of long or short displacements for code or + * data. + * + *************************************************************************** + */ + +/* Compiler and system dependent definitions: */ + +#define Mic_secs_Per_Second 1000000.0 + /* Berkeley UNIX C returns process times in seconds/HZ */ + +#ifdef NOSTRUCTASSIGN +#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) +#else +#define structassign(d, s) d = s +#endif + +#ifdef NOENUM +#define Ident_1 0 +#define Ident_2 1 +#define Ident_3 2 +#define Ident_4 3 +#define Ident_5 4 + typedef int Enumeration; +#else + typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} + Enumeration; +#endif + /* for boolean and enumeration types in Ada, Pascal */ + +/* General definitions: */ + +// #include + /* for strcpy, strcmp */ +#include + +#define Null 0 + /* Value of a Null pointer */ +#define true 1 +#define false 0 + +typedef int One_Thirty; +typedef int One_Fifty; +typedef char Capital_Letter; +typedef int Boolean; +typedef char Str_30 [31]; +typedef int Arr_1_Dim [50]; +typedef int Arr_2_Dim [50] [50]; + +typedef struct record + { + struct record *Ptr_Comp; + Enumeration Discr; + union { + struct { + Enumeration Enum_Comp; + int Int_Comp; + char Str_Comp [31]; + } var_1; + struct { + Enumeration E_Comp_2; + char Str_2_Comp [31]; + } var_2; + struct { + char Ch_1_Comp; + char Ch_2_Comp; + } var_3; + } variant; + } Rec_Type, *Rec_Pointer; + + diff --git a/examples/test/dhry_1.c b/examples/test/dhry_1.c index 18cdfec2910103f538f8373371430dc9de7c178b..b45b9ddafa7f67f70b4dea8fad71c9c0f91679ad 100644 --- a/examples/test/dhry_1.c +++ b/examples/test/dhry_1.c @@ -1,349 +1,349 @@ -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry_1.c (part 2 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * - **************************************************************************** - */ - -#define NUMBER_OF_RUNS 1000000 - -#include "dhry.h" -#define printf rt_kprintf - -/* Global Variables: */ - -Rec_Pointer Ptr_Glob, - Next_Ptr_Glob; -int Int_Glob; -Boolean Bool_Glob; -char Ch_1_Glob, - Ch_2_Glob; -int Arr_1_Glob [50]; -int Arr_2_Glob [50] [50]; - -Enumeration Func_1 (); - -/* forward declaration necessary since Enumeration may not simply be int */ - -#ifndef REG - Boolean Reg = false; -#define REG - /* REG becomes defined as empty */ - /* i.e. no register variables */ -#else - Boolean Reg = true; -#endif - -/* variables for time measurement: */ - -float Begin_Time, - End_Time, - User_Time; -float Microseconds, - Dhrystones_Per_Second; - -/* end of variables for time measurement */ - -void dhry_test(void) -/*****/ - - /* main program, corresponds to procedures */ - /* Main and Proc_0 in the Ada version */ -{ - One_Fifty Int_1_Loc; - REG One_Fifty Int_2_Loc; - One_Fifty Int_3_Loc; - REG char Ch_Index; - Enumeration Enum_Loc; - Str_30 Str_1_Loc; - Str_30 Str_2_Loc; - REG int Run_Index; - REG int Number_Of_Runs; - - /* Initializations */ - - Next_Ptr_Glob = (Rec_Pointer) rt_malloc (sizeof (Rec_Type)); - Ptr_Glob = (Rec_Pointer) rt_malloc (sizeof (Rec_Type)); - - Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; - Ptr_Glob->Discr = Ident_1; - Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; - Ptr_Glob->variant.var_1.Int_Comp = 40; - rt_strncpy (Ptr_Glob->variant.var_1.Str_Comp, - "DHRYSTONE PROGRAM, SOME STRING", sizeof(Ptr_Glob->variant.var_1.Str_Comp)); - rt_strncpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING", sizeof(Str_1_Loc)); - - Arr_2_Glob [8][7] = 10; - /* Was missing in published program. Without this statement, */ - /* Arr_2_Glob [8][7] would have an undefined value. */ - /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ - /* overflow may occur for this array element. */ - - printf ("\n"); - printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); - printf ("\n"); - if (Reg) - { - printf ("Program compiled with 'register' attribute\n"); - printf ("\n"); - } - else - { - printf ("Program compiled without 'register' attribute\n"); - printf ("\n"); - } - printf ("Please give the number of runs through the benchmark: "); - - Number_Of_Runs = NUMBER_OF_RUNS; - printf ("%d\n", Number_Of_Runs); - - printf ("\n"); - - printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); - - /***************/ - /* Start timer */ - /***************/ - -// Add your timer initializing code here - - Begin_Time = rt_tick_get(); /* get start tick */ - - for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) - { - - Proc_5(); - Proc_4(); - /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ - Int_1_Loc = 2; - Int_2_Loc = 3; - rt_strncpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING", sizeof(Str_2_Loc)); - Enum_Loc = Ident_2; - Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); - /* Bool_Glob == 1 */ - while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ - { - Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; - /* Int_3_Loc == 7 */ - Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); - /* Int_3_Loc == 7 */ - Int_1_Loc += 1; - } /* while */ - /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ - Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); - /* Int_Glob == 5 */ - Proc_1 (Ptr_Glob); - for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) - /* loop body executed twice */ - { - if (Enum_Loc == Func_1 (Ch_Index, 'C')) - /* then, not executed */ - { - Proc_6 (Ident_1, &Enum_Loc); - rt_strncpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING", sizeof(Str_2_Loc)); - Int_2_Loc = Run_Index; - Int_Glob = Run_Index; - } - } - /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ - Int_2_Loc = Int_2_Loc * Int_1_Loc; - Int_1_Loc = Int_2_Loc / Int_3_Loc; - Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; - /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ - Proc_2 (&Int_1_Loc); - /* Int_1_Loc == 5 */ - - } /* loop "for Run_Index" */ - - /**************/ - /* Stop timer */ - /**************/ - - End_Time = rt_tick_get(); // Get end tick - - printf ("Execution ends\n"); - printf ("\n"); - printf ("Final values of the variables used in the benchmark:\n"); - printf ("\n"); - printf ("Int_Glob: %d\n", Int_Glob); - printf (" should be: %d\n", 5); - printf ("Bool_Glob: %d\n", Bool_Glob); - printf (" should be: %d\n", 1); - printf ("Ch_1_Glob: %c\n", Ch_1_Glob); - printf (" should be: %c\n", 'A'); - printf ("Ch_2_Glob: %c\n", Ch_2_Glob); - printf (" should be: %c\n", 'B'); - printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); - printf (" should be: %d\n", 7); - printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); - printf (" should be: Number_Of_Runs + 10\n"); - printf ("Ptr_Glob->\n"); - printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); - printf (" should be: (implementation-dependent)\n"); - printf (" Discr: %d\n", Ptr_Glob->Discr); - printf (" should be: %d\n", 0); - printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); - printf (" should be: %d\n", 2); - printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); - printf (" should be: %d\n", 17); - printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); - printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); - printf ("Next_Ptr_Glob->\n"); - printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); - printf (" should be: (implementation-dependent), same as above\n"); - printf (" Discr: %d\n", Next_Ptr_Glob->Discr); - printf (" should be: %d\n", 0); - printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); - printf (" should be: %d\n", 1); - printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); - printf (" should be: %d\n", 18); - printf (" Str_Comp: %s\n", - Next_Ptr_Glob->variant.var_1.Str_Comp); - printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); - printf ("Int_1_Loc: %d\n", Int_1_Loc); - printf (" should be: %d\n", 5); - printf ("Int_2_Loc: %d\n", Int_2_Loc); - printf (" should be: %d\n", 13); - printf ("Int_3_Loc: %d\n", Int_3_Loc); - printf (" should be: %d\n", 7); - printf ("Enum_Loc: %d\n", Enum_Loc); - printf (" should be: %d\n", 1); - printf ("Str_1_Loc: %s\n", Str_1_Loc); - printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); - printf ("Str_2_Loc: %s\n", Str_2_Loc); - printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); - printf ("\n"); - - User_Time = (End_Time - Begin_Time) / RT_TICK_PER_SECOND; - - Microseconds = (float) User_Time * Mic_secs_Per_Second - / (float) Number_Of_Runs; - Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time; - - printf ("Microseconds for one run through Dhrystone: "); - printf ("%6d \n", (int)Microseconds); - printf ("Dhrystones per Second: "); - printf ("%6d \n", (int)Dhrystones_Per_Second); - printf ("Dhrystones MIPS: "); - printf ("%6d \n", (int)(Dhrystones_Per_Second / 1757.0)); - printf ("\n"); - -} - -Proc_1 (Ptr_Val_Par) -/******************/ - -REG Rec_Pointer Ptr_Val_Par; - /* executed once */ -{ - REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; - /* == Ptr_Glob_Next */ - /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ - /* corresponds to "rename" in Ada, "with" in Pascal */ - - structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); - Ptr_Val_Par->variant.var_1.Int_Comp = 5; - Next_Record->variant.var_1.Int_Comp - = Ptr_Val_Par->variant.var_1.Int_Comp; - Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; - Proc_3 (&Next_Record->Ptr_Comp); - /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp - == Ptr_Glob->Ptr_Comp */ - if (Next_Record->Discr == Ident_1) - /* then, executed */ - { - Next_Record->variant.var_1.Int_Comp = 6; - Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, - &Next_Record->variant.var_1.Enum_Comp); - Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; - Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, - &Next_Record->variant.var_1.Int_Comp); - } - else /* not executed */ - structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); -} /* Proc_1 */ - - -Proc_2 (Int_Par_Ref) -/******************/ - /* executed once */ - /* *Int_Par_Ref == 1, becomes 4 */ - -One_Fifty *Int_Par_Ref; -{ - One_Fifty Int_Loc; - Enumeration Enum_Loc; - - Int_Loc = *Int_Par_Ref + 10; - do /* executed once */ - if (Ch_1_Glob == 'A') - /* then, executed */ - { - Int_Loc -= 1; - *Int_Par_Ref = Int_Loc - Int_Glob; - Enum_Loc = Ident_1; - } /* if */ - while (Enum_Loc != Ident_1); /* true */ -} /* Proc_2 */ - - -Proc_3 (Ptr_Ref_Par) -/******************/ - /* executed once */ - /* Ptr_Ref_Par becomes Ptr_Glob */ - -Rec_Pointer *Ptr_Ref_Par; - -{ - if (Ptr_Glob != Null) - /* then, executed */ - *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; - Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); -} /* Proc_3 */ - - -Proc_4 () /* without parameters */ -/*******/ - /* executed once */ -{ - Boolean Bool_Loc; - - Bool_Loc = Ch_1_Glob == 'A'; - Bool_Glob = Bool_Loc | Bool_Glob; - Ch_2_Glob = 'B'; -} /* Proc_4 */ - - -Proc_5 () /* without parameters */ -/*******/ - /* executed once */ -{ - Ch_1_Glob = 'A'; - Bool_Glob = false; -} /* Proc_5 */ - - - /* Procedure for the assignment of structures, */ - /* if the C compiler doesn't support this feature */ -#ifdef NOSTRUCTASSIGN -memcpy (d, s, l) -register char *d; -register char *s; -register int l; -{ - while (l--) *d++ = *s++; -} -#endif - -#include -FINSH_FUNCTION_EXPORT(dhry_test, dhry test); +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_1.c (part 2 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + **************************************************************************** + */ + +#define NUMBER_OF_RUNS 1000000 + +#include "dhry.h" +#define printf rt_kprintf + +/* Global Variables: */ + +Rec_Pointer Ptr_Glob, + Next_Ptr_Glob; +int Int_Glob; +Boolean Bool_Glob; +char Ch_1_Glob, + Ch_2_Glob; +int Arr_1_Glob [50]; +int Arr_2_Glob [50] [50]; + +Enumeration Func_1 (); + +/* forward declaration necessary since Enumeration may not simply be int */ + +#ifndef REG + Boolean Reg = false; +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#else + Boolean Reg = true; +#endif + +/* variables for time measurement: */ + +float Begin_Time, + End_Time, + User_Time; +float Microseconds, + Dhrystones_Per_Second; + +/* end of variables for time measurement */ + +void dhry_test(void) +/*****/ + + /* main program, corresponds to procedures */ + /* Main and Proc_0 in the Ada version */ +{ + One_Fifty Int_1_Loc; + REG One_Fifty Int_2_Loc; + One_Fifty Int_3_Loc; + REG char Ch_Index; + Enumeration Enum_Loc; + Str_30 Str_1_Loc; + Str_30 Str_2_Loc; + REG int Run_Index; + REG int Number_Of_Runs; + + /* Initializations */ + + Next_Ptr_Glob = (Rec_Pointer) rt_malloc (sizeof (Rec_Type)); + Ptr_Glob = (Rec_Pointer) rt_malloc (sizeof (Rec_Type)); + + Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; + Ptr_Glob->Discr = Ident_1; + Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; + Ptr_Glob->variant.var_1.Int_Comp = 40; + rt_strncpy (Ptr_Glob->variant.var_1.Str_Comp, + "DHRYSTONE PROGRAM, SOME STRING", sizeof(Ptr_Glob->variant.var_1.Str_Comp)); + rt_strncpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING", sizeof(Str_1_Loc)); + + Arr_2_Glob [8][7] = 10; + /* Was missing in published program. Without this statement, */ + /* Arr_2_Glob [8][7] would have an undefined value. */ + /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ + /* overflow may occur for this array element. */ + + printf ("\n"); + printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); + printf ("\n"); + if (Reg) + { + printf ("Program compiled with 'register' attribute\n"); + printf ("\n"); + } + else + { + printf ("Program compiled without 'register' attribute\n"); + printf ("\n"); + } + printf ("Please give the number of runs through the benchmark: "); + + Number_Of_Runs = NUMBER_OF_RUNS; + printf ("%d\n", Number_Of_Runs); + + printf ("\n"); + + printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); + + /***************/ + /* Start timer */ + /***************/ + +// Add your timer initializing code here + + Begin_Time = rt_tick_get(); /* get start tick */ + + for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) + { + + Proc_5(); + Proc_4(); + /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ + Int_1_Loc = 2; + Int_2_Loc = 3; + rt_strncpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING", sizeof(Str_2_Loc)); + Enum_Loc = Ident_2; + Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); + /* Bool_Glob == 1 */ + while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ + { + Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; + /* Int_3_Loc == 7 */ + Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); + /* Int_3_Loc == 7 */ + Int_1_Loc += 1; + } /* while */ + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); + /* Int_Glob == 5 */ + Proc_1 (Ptr_Glob); + for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) + /* loop body executed twice */ + { + if (Enum_Loc == Func_1 (Ch_Index, 'C')) + /* then, not executed */ + { + Proc_6 (Ident_1, &Enum_Loc); + rt_strncpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING", sizeof(Str_2_Loc)); + Int_2_Loc = Run_Index; + Int_Glob = Run_Index; + } + } + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Int_2_Loc = Int_2_Loc * Int_1_Loc; + Int_1_Loc = Int_2_Loc / Int_3_Loc; + Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; + /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ + Proc_2 (&Int_1_Loc); + /* Int_1_Loc == 5 */ + + } /* loop "for Run_Index" */ + + /**************/ + /* Stop timer */ + /**************/ + + End_Time = rt_tick_get(); // Get end tick + + printf ("Execution ends\n"); + printf ("\n"); + printf ("Final values of the variables used in the benchmark:\n"); + printf ("\n"); + printf ("Int_Glob: %d\n", Int_Glob); + printf (" should be: %d\n", 5); + printf ("Bool_Glob: %d\n", Bool_Glob); + printf (" should be: %d\n", 1); + printf ("Ch_1_Glob: %c\n", Ch_1_Glob); + printf (" should be: %c\n", 'A'); + printf ("Ch_2_Glob: %c\n", Ch_2_Glob); + printf (" should be: %c\n", 'B'); + printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); + printf (" should be: %d\n", 7); + printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); + printf (" should be: Number_Of_Runs + 10\n"); + printf ("Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent)\n"); + printf (" Discr: %d\n", Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 2); + printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 17); + printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Next_Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent), same as above\n"); + printf (" Discr: %d\n", Next_Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 1); + printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 18); + printf (" Str_Comp: %s\n", + Next_Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Int_1_Loc: %d\n", Int_1_Loc); + printf (" should be: %d\n", 5); + printf ("Int_2_Loc: %d\n", Int_2_Loc); + printf (" should be: %d\n", 13); + printf ("Int_3_Loc: %d\n", Int_3_Loc); + printf (" should be: %d\n", 7); + printf ("Enum_Loc: %d\n", Enum_Loc); + printf (" should be: %d\n", 1); + printf ("Str_1_Loc: %s\n", Str_1_Loc); + printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); + printf ("Str_2_Loc: %s\n", Str_2_Loc); + printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); + printf ("\n"); + + User_Time = (End_Time - Begin_Time) / RT_TICK_PER_SECOND; + + Microseconds = (float) User_Time * Mic_secs_Per_Second + / (float) Number_Of_Runs; + Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time; + + printf ("Microseconds for one run through Dhrystone: "); + printf ("%6d \n", (int)Microseconds); + printf ("Dhrystones per Second: "); + printf ("%6d \n", (int)Dhrystones_Per_Second); + printf ("Dhrystones MIPS: "); + printf ("%6d \n", (int)(Dhrystones_Per_Second / 1757.0)); + printf ("\n"); + +} + +Proc_1 (Ptr_Val_Par) +/******************/ + +REG Rec_Pointer Ptr_Val_Par; + /* executed once */ +{ + REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; + /* == Ptr_Glob_Next */ + /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ + /* corresponds to "rename" in Ada, "with" in Pascal */ + + structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); + Ptr_Val_Par->variant.var_1.Int_Comp = 5; + Next_Record->variant.var_1.Int_Comp + = Ptr_Val_Par->variant.var_1.Int_Comp; + Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; + Proc_3 (&Next_Record->Ptr_Comp); + /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp + == Ptr_Glob->Ptr_Comp */ + if (Next_Record->Discr == Ident_1) + /* then, executed */ + { + Next_Record->variant.var_1.Int_Comp = 6; + Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, + &Next_Record->variant.var_1.Enum_Comp); + Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; + Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, + &Next_Record->variant.var_1.Int_Comp); + } + else /* not executed */ + structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); +} /* Proc_1 */ + + +Proc_2 (Int_Par_Ref) +/******************/ + /* executed once */ + /* *Int_Par_Ref == 1, becomes 4 */ + +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + Enumeration Enum_Loc; + + Int_Loc = *Int_Par_Ref + 10; + do /* executed once */ + if (Ch_1_Glob == 'A') + /* then, executed */ + { + Int_Loc -= 1; + *Int_Par_Ref = Int_Loc - Int_Glob; + Enum_Loc = Ident_1; + } /* if */ + while (Enum_Loc != Ident_1); /* true */ +} /* Proc_2 */ + + +Proc_3 (Ptr_Ref_Par) +/******************/ + /* executed once */ + /* Ptr_Ref_Par becomes Ptr_Glob */ + +Rec_Pointer *Ptr_Ref_Par; + +{ + if (Ptr_Glob != Null) + /* then, executed */ + *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; + Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); +} /* Proc_3 */ + + +Proc_4 () /* without parameters */ +/*******/ + /* executed once */ +{ + Boolean Bool_Loc; + + Bool_Loc = Ch_1_Glob == 'A'; + Bool_Glob = Bool_Loc | Bool_Glob; + Ch_2_Glob = 'B'; +} /* Proc_4 */ + + +Proc_5 () /* without parameters */ +/*******/ + /* executed once */ +{ + Ch_1_Glob = 'A'; + Bool_Glob = false; +} /* Proc_5 */ + + + /* Procedure for the assignment of structures, */ + /* if the C compiler doesn't support this feature */ +#ifdef NOSTRUCTASSIGN +memcpy (d, s, l) +register char *d; +register char *s; +register int l; +{ + while (l--) *d++ = *s++; +} +#endif + +#include +FINSH_FUNCTION_EXPORT(dhry_test, dhry test); diff --git a/examples/test/fs_test.c b/examples/test/fs_test.c index bc18a196f1cdc42da8d35f0447326f185ef33f60..2404b82e591bb47a9efeda6c69f7288674596c41 100644 --- a/examples/test/fs_test.c +++ b/examples/test/fs_test.c @@ -1,297 +1,297 @@ -/* - * File : fs_test.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE. - * - * Change Logs: - * Date Author Notes - * 2011-01-02 aozima the first version. - * 2011-03-17 aozima fix some bug. - * 2011-03-18 aozima to dynamic thread. - */ - -#include -#include - -static rt_uint32_t stop_flag = 0; -static rt_thread_t fsrw1_thread = RT_NULL; -static rt_thread_t fsrw2_thread = RT_NULL; - -#define fsrw1_fn "/test1.dat" -#define fsrw1_data_len 120 /* Less than 256 */ -static void fsrw1_thread_entry(void* parameter) -{ - int fd; - int index,length; - rt_uint32_t round; - rt_uint32_t tick_start,tick_end,read_speed,write_speed; - - static rt_uint8_t write_data1[fsrw1_data_len]; - static rt_uint8_t read_data1[fsrw1_data_len]; - - round = 1; - - while(1) - { - if( stop_flag ) - { - rt_kprintf("thread fsrw2 error,thread fsrw1 quit!\r\n"); - fsrw1_thread = RT_NULL; - stop_flag = 0; - return; - } - - /* creat file */ - fd = open(fsrw1_fn, O_WRONLY | O_CREAT | O_TRUNC, 0); - if (fd < 0) - { - rt_kprintf("fsrw1 open file for write failed\n"); - stop_flag = 1; - fsrw1_thread = RT_NULL; - return; - } - - /* plan write data */ - for (index = 0; index < fsrw1_data_len; index ++) - { - write_data1[index] = index; - } - - /* write 8000 times */ - tick_start = rt_tick_get(); - for(index=0; index<8000; index++) - { - length = write(fd, write_data1, fsrw1_data_len); - if (length != fsrw1_data_len) - { - rt_kprintf("fsrw1 write data failed\n"); - close(fd); - fsrw1_thread = RT_NULL; - stop_flag = 1; - return; - } - } - tick_end = rt_tick_get(); - write_speed = fsrw1_data_len*8000UL*RT_TICK_PER_SECOND/(tick_end-tick_start); - - /* close file */ - close(fd); - - /* open file read only */ - fd = open(fsrw1_fn, O_RDONLY, 0); - if (fd < 0) - { - rt_kprintf("fsrw1 open file for read failed\n"); - stop_flag = 1; - fsrw1_thread = RT_NULL; - return; - } - - /* verify data */ - tick_start = rt_tick_get(); - for(index=0; index<8000; index++) - { - rt_uint32_t i; - - length = read(fd, read_data1, fsrw1_data_len); - if (length != fsrw1_data_len) - { - rt_kprintf("fsrw1 read file failed\r\n"); - close(fd); - stop_flag = 1; - fsrw1_thread = RT_NULL; - return; - } - for(i=0; i -FINSH_FUNCTION_EXPORT(fs_test, file system R/W test. e.g: fs_test(3)); -#endif +/* + * File : fs_test.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE. + * + * Change Logs: + * Date Author Notes + * 2011-01-02 aozima the first version. + * 2011-03-17 aozima fix some bug. + * 2011-03-18 aozima to dynamic thread. + */ + +#include +#include + +static rt_uint32_t stop_flag = 0; +static rt_thread_t fsrw1_thread = RT_NULL; +static rt_thread_t fsrw2_thread = RT_NULL; + +#define fsrw1_fn "/test1.dat" +#define fsrw1_data_len 120 /* Less than 256 */ +static void fsrw1_thread_entry(void* parameter) +{ + int fd; + int index,length; + rt_uint32_t round; + rt_uint32_t tick_start,tick_end,read_speed,write_speed; + + static rt_uint8_t write_data1[fsrw1_data_len]; + static rt_uint8_t read_data1[fsrw1_data_len]; + + round = 1; + + while(1) + { + if( stop_flag ) + { + rt_kprintf("thread fsrw2 error,thread fsrw1 quit!\r\n"); + fsrw1_thread = RT_NULL; + stop_flag = 0; + return; + } + + /* creat file */ + fd = open(fsrw1_fn, O_WRONLY | O_CREAT | O_TRUNC, 0); + if (fd < 0) + { + rt_kprintf("fsrw1 open file for write failed\n"); + stop_flag = 1; + fsrw1_thread = RT_NULL; + return; + } + + /* plan write data */ + for (index = 0; index < fsrw1_data_len; index ++) + { + write_data1[index] = index; + } + + /* write 8000 times */ + tick_start = rt_tick_get(); + for(index=0; index<8000; index++) + { + length = write(fd, write_data1, fsrw1_data_len); + if (length != fsrw1_data_len) + { + rt_kprintf("fsrw1 write data failed\n"); + close(fd); + fsrw1_thread = RT_NULL; + stop_flag = 1; + return; + } + } + tick_end = rt_tick_get(); + write_speed = fsrw1_data_len*8000UL*RT_TICK_PER_SECOND/(tick_end-tick_start); + + /* close file */ + close(fd); + + /* open file read only */ + fd = open(fsrw1_fn, O_RDONLY, 0); + if (fd < 0) + { + rt_kprintf("fsrw1 open file for read failed\n"); + stop_flag = 1; + fsrw1_thread = RT_NULL; + return; + } + + /* verify data */ + tick_start = rt_tick_get(); + for(index=0; index<8000; index++) + { + rt_uint32_t i; + + length = read(fd, read_data1, fsrw1_data_len); + if (length != fsrw1_data_len) + { + rt_kprintf("fsrw1 read file failed\r\n"); + close(fd); + stop_flag = 1; + fsrw1_thread = RT_NULL; + return; + } + for(i=0; i +FINSH_FUNCTION_EXPORT(fs_test, file system R/W test. e.g: fs_test(3)); +#endif diff --git a/examples/test/mem_test.c b/examples/test/mem_test.c index 595578e1268899a0a0bb377dd0ec9c1125416eb3..2e94bca2d07198fe49ccc8e6cf54655e6821f506 100644 --- a/examples/test/mem_test.c +++ b/examples/test/mem_test.c @@ -1,105 +1,105 @@ -#include - -#include -#include - -#define printf rt_kprintf - -void mem_test(uint32_t address, uint32_t size ) -{ - uint32_t i; - - printf("memtest,address: 0x%08X size: 0x%08X\r\n", address, size); - - /**< 8bit test */ - { - uint8_t * p_uint8_t = (uint8_t *)address; - for(i=0; i -FINSH_FUNCTION_EXPORT(mem_test, mem_test(0xA0000000, 0x00100000) ); -#endif +#include + +#include +#include + +#define printf rt_kprintf + +void mem_test(uint32_t address, uint32_t size ) +{ + uint32_t i; + + printf("memtest,address: 0x%08X size: 0x%08X\r\n", address, size); + + /**< 8bit test */ + { + uint8_t * p_uint8_t = (uint8_t *)address; + for(i=0; i +FINSH_FUNCTION_EXPORT(mem_test, mem_test(0xA0000000, 0x00100000) ); +#endif diff --git a/examples/test/net_test.c b/examples/test/net_test.c index 849b03bbccd8f471ecba680f0012abe9836ea1b8..e4961622c735ebf78e8077a45392b1498bfe7f29 100644 --- a/examples/test/net_test.c +++ b/examples/test/net_test.c @@ -1,282 +1,282 @@ -/* - * Net Test Utilities for RT-Thread - */ -#include -#include -#include -#include -/* - * UDP echo server - */ -#define UDP_ECHO_PORT 7 -rt_thread_t udpecho_tid = RT_NULL; -void udpecho_entry(void *parameter) -{ - struct netconn *conn; - struct netbuf *buf; - struct ip_addr *addr; - unsigned short port; - - conn = netconn_new(NETCONN_UDP); - netconn_bind(conn, IP_ADDR_ANY, 7); - - while(1) - { - /* received data to buffer */ - buf = netconn_recv(conn); - - addr = netbuf_fromaddr(buf); - port = netbuf_fromport(buf); - - /* send the data to buffer */ - netconn_connect(conn, addr, port); - - /* reset address, and send to client */ - buf->addr = RT_NULL; - netconn_send(conn, buf); - - /* release buffer */ - netbuf_delete(buf); - } -} -/* - * UDP socket echo server - */ -#define UDP_SOCKET_ECHO_PORT 700 -#define UDP_SOCKET_BUFFER_SIZE 4096 -rt_thread_t udpecho_socket_tid = RT_NULL; -void udpecho_socket_entry(void *parameter) -{ - int sock; - int bytes_read; - char *recv_data; - rt_uint32_t addr_len; - struct sockaddr_in server_addr, client_addr; - - /* allocate the data buffer */ - recv_data = rt_malloc(UDP_SOCKET_BUFFER_SIZE); - if (recv_data == RT_NULL) - { - /* no memory yet */ - rt_kprintf("no memory\n"); - goto _exit; - } - /* create a UDP socket */ - if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) == -1) - { - rt_kprintf("create socket error\n"); - goto _exit; - } - - /* initialize server address */ - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(UDP_SOCKET_ECHO_PORT); - server_addr.sin_addr.s_addr = INADDR_ANY; - rt_memset(&(server_addr.sin_zero),0, sizeof(server_addr.sin_zero)); - - /* bind socket to server address */ - if (bind(sock,(struct sockaddr *)&server_addr, - sizeof(struct sockaddr)) == -1) - { - /* bind failed */ - rt_kprintf("bind error\n"); - goto _exit; - } - - addr_len = sizeof(struct sockaddr); - while (1) - { - /* try to receive from UDP socket */ - bytes_read = recvfrom(sock, recv_data, UDP_SOCKET_BUFFER_SIZE, 0, - (struct sockaddr *)&client_addr, &addr_len); - - /* send back */ - sendto(sock, recv_data, bytes_read, 0, - (struct sockaddr *)&client_addr, addr_len); - } - -_exit: - rt_free(recv_data); - return; -} - -/* - * TCP echo server - */ -#define TCP_ECHO_PORT 7 -rt_thread_t tcpecho_tid = RT_NULL; -void tcpecho_entry(void *parameter) -{ - struct netconn *conn, *newconn; - err_t err; - - /* Create a new connection identifier. */ - conn = netconn_new(NETCONN_TCP); - - /* Bind connection to well known port number 7. */ - netconn_bind(conn, NULL, TCP_ECHO_PORT); - - /* Tell connection to go into listening mode. */ - netconn_listen(conn); - - while(1) - { - /* Grab new connection. */ - newconn = netconn_accept(conn); - /* Process the new connection. */ - if(newconn != NULL) - { - struct netbuf *buf; - void *data; - u16_t len; - - while((buf = netconn_recv(newconn)) != NULL) - { - do - { - netbuf_data(buf, &data, &len); - err = netconn_write(newconn, data, len, NETCONN_COPY); - if(err != ERR_OK){} - } - while(netbuf_next(buf) >= 0); - netbuf_delete(buf); - } - /* Close connection and discard connection identifier. */ - netconn_delete(newconn); - } - } -} - -/* - * TCP socket echo server - */ -#define TCP_SOCKET_ECHO_PORT 700 -#define TCP_SOCKET_BUFFER_SIZE 4096 -rt_thread_t tcpecho_socket_tid = RT_NULL; -void tcpecho_socket_entry(void *parameter) -{ - char *recv_data; - rt_uint32_t sin_size; - int sock = -1, connected, bytes_received; - struct sockaddr_in server_addr, client_addr; - - recv_data = rt_malloc(TCP_SOCKET_BUFFER_SIZE); - if (recv_data == RT_NULL) - { - rt_kprintf("no memory\n"); - goto _exit; - } - - /* create a TCP socket */ - if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1) - { - rt_kprintf("create socket error\n"); - goto _exit; - } - - /* initialize server address */ - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(TCP_SOCKET_ECHO_PORT); - server_addr.sin_addr.s_addr = INADDR_ANY; - rt_memset(&(server_addr.sin_zero),8, sizeof(server_addr.sin_zero)); - - /* bind to server address */ - if (bind(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1) - { - rt_kprintf("bind address failed\n"); - goto _exit; - } - - /* listen */ - if (listen(sock, 5) == -1) - { - rt_kprintf("listen error\n"); - goto _exit; - } - - sin_size = sizeof(struct sockaddr_in); - while(1) - { - /* accept client connected */ - connected = accept(sock, (struct sockaddr *)&client_addr, &sin_size); - if (connected > 0) - { - int timeout; - - /* set timeout option */ - timeout = 5000; /* 5second */ - setsockopt(connected, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout)); - - /* handle this client */ - while (1) - { - /* receive data from this connection */ - bytes_received = recv(connected,recv_data, TCP_SOCKET_BUFFER_SIZE, 0); - if (bytes_received <= 0) - { - rt_kprintf("close client connection, errno: %d, socket error: %d\n", - rt_get_errno(), - lwip_get_error()); - /* connection closed. */ - lwip_close(connected); - break; - } - - /* send data to client */ - send(connected, recv_data, bytes_received, 0); - } - } - } - -_exit: - /* close socket */ - if (sock != -1) lwip_close(sock); - rt_free(recv_data); - - return ; -} - -/* - * NetIO TCP server - */ - -/* network test utilities entry */ -void net_test(void) -{ - /* start UDP echo server */ - if (udpecho_tid == RT_NULL) - { - udpecho_tid = rt_thread_create("uecho", - udpecho_entry, RT_NULL, - 512, RT_THREAD_PRIORITY_MAX/2, 5); - if (udpecho_tid != RT_NULL) - rt_thread_startup(udpecho_tid); - } - if (udpecho_socket_tid == RT_NULL) - { - udpecho_socket_tid = rt_thread_create("uecho_s", - udpecho_socket_entry, RT_NULL, - 512, RT_THREAD_PRIORITY_MAX/2 + 1, 5); - if (udpecho_socket_tid != RT_NULL) - rt_thread_startup(udpecho_socket_tid); - } - - if (tcpecho_tid == RT_NULL) - { - tcpecho_tid = rt_thread_create("techo", - tcpecho_entry, RT_NULL, - 512, RT_THREAD_PRIORITY_MAX/2 + 2, 5); - if (tcpecho_tid != RT_NULL) - rt_thread_startup(tcpecho_tid); - } - if (tcpecho_socket_tid == RT_NULL) - { - tcpecho_socket_tid = rt_thread_create("techo_s", - tcpecho_socket_entry, RT_NULL, - 512, RT_THREAD_PRIORITY_MAX/2 + 3, 5); - if (tcpecho_socket_tid != RT_NULL) - rt_thread_startup(tcpecho_socket_tid); - } -} -FINSH_FUNCTION_EXPORT(net_test, network test); - +/* + * Net Test Utilities for RT-Thread + */ +#include +#include +#include +#include +/* + * UDP echo server + */ +#define UDP_ECHO_PORT 7 +rt_thread_t udpecho_tid = RT_NULL; +void udpecho_entry(void *parameter) +{ + struct netconn *conn; + struct netbuf *buf; + struct ip_addr *addr; + unsigned short port; + + conn = netconn_new(NETCONN_UDP); + netconn_bind(conn, IP_ADDR_ANY, 7); + + while(1) + { + /* received data to buffer */ + buf = netconn_recv(conn); + + addr = netbuf_fromaddr(buf); + port = netbuf_fromport(buf); + + /* send the data to buffer */ + netconn_connect(conn, addr, port); + + /* reset address, and send to client */ + buf->addr = RT_NULL; + netconn_send(conn, buf); + + /* release buffer */ + netbuf_delete(buf); + } +} +/* + * UDP socket echo server + */ +#define UDP_SOCKET_ECHO_PORT 700 +#define UDP_SOCKET_BUFFER_SIZE 4096 +rt_thread_t udpecho_socket_tid = RT_NULL; +void udpecho_socket_entry(void *parameter) +{ + int sock; + int bytes_read; + char *recv_data; + rt_uint32_t addr_len; + struct sockaddr_in server_addr, client_addr; + + /* allocate the data buffer */ + recv_data = rt_malloc(UDP_SOCKET_BUFFER_SIZE); + if (recv_data == RT_NULL) + { + /* no memory yet */ + rt_kprintf("no memory\n"); + goto _exit; + } + /* create a UDP socket */ + if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) == -1) + { + rt_kprintf("create socket error\n"); + goto _exit; + } + + /* initialize server address */ + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(UDP_SOCKET_ECHO_PORT); + server_addr.sin_addr.s_addr = INADDR_ANY; + rt_memset(&(server_addr.sin_zero),0, sizeof(server_addr.sin_zero)); + + /* bind socket to server address */ + if (bind(sock,(struct sockaddr *)&server_addr, + sizeof(struct sockaddr)) == -1) + { + /* bind failed */ + rt_kprintf("bind error\n"); + goto _exit; + } + + addr_len = sizeof(struct sockaddr); + while (1) + { + /* try to receive from UDP socket */ + bytes_read = recvfrom(sock, recv_data, UDP_SOCKET_BUFFER_SIZE, 0, + (struct sockaddr *)&client_addr, &addr_len); + + /* send back */ + sendto(sock, recv_data, bytes_read, 0, + (struct sockaddr *)&client_addr, addr_len); + } + +_exit: + rt_free(recv_data); + return; +} + +/* + * TCP echo server + */ +#define TCP_ECHO_PORT 7 +rt_thread_t tcpecho_tid = RT_NULL; +void tcpecho_entry(void *parameter) +{ + struct netconn *conn, *newconn; + err_t err; + + /* Create a new connection identifier. */ + conn = netconn_new(NETCONN_TCP); + + /* Bind connection to well known port number 7. */ + netconn_bind(conn, NULL, TCP_ECHO_PORT); + + /* Tell connection to go into listening mode. */ + netconn_listen(conn); + + while(1) + { + /* Grab new connection. */ + newconn = netconn_accept(conn); + /* Process the new connection. */ + if(newconn != NULL) + { + struct netbuf *buf; + void *data; + u16_t len; + + while((buf = netconn_recv(newconn)) != NULL) + { + do + { + netbuf_data(buf, &data, &len); + err = netconn_write(newconn, data, len, NETCONN_COPY); + if(err != ERR_OK){} + } + while(netbuf_next(buf) >= 0); + netbuf_delete(buf); + } + /* Close connection and discard connection identifier. */ + netconn_delete(newconn); + } + } +} + +/* + * TCP socket echo server + */ +#define TCP_SOCKET_ECHO_PORT 700 +#define TCP_SOCKET_BUFFER_SIZE 4096 +rt_thread_t tcpecho_socket_tid = RT_NULL; +void tcpecho_socket_entry(void *parameter) +{ + char *recv_data; + rt_uint32_t sin_size; + int sock = -1, connected, bytes_received; + struct sockaddr_in server_addr, client_addr; + + recv_data = rt_malloc(TCP_SOCKET_BUFFER_SIZE); + if (recv_data == RT_NULL) + { + rt_kprintf("no memory\n"); + goto _exit; + } + + /* create a TCP socket */ + if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1) + { + rt_kprintf("create socket error\n"); + goto _exit; + } + + /* initialize server address */ + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(TCP_SOCKET_ECHO_PORT); + server_addr.sin_addr.s_addr = INADDR_ANY; + rt_memset(&(server_addr.sin_zero),8, sizeof(server_addr.sin_zero)); + + /* bind to server address */ + if (bind(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1) + { + rt_kprintf("bind address failed\n"); + goto _exit; + } + + /* listen */ + if (listen(sock, 5) == -1) + { + rt_kprintf("listen error\n"); + goto _exit; + } + + sin_size = sizeof(struct sockaddr_in); + while(1) + { + /* accept client connected */ + connected = accept(sock, (struct sockaddr *)&client_addr, &sin_size); + if (connected > 0) + { + int timeout; + + /* set timeout option */ + timeout = 5000; /* 5second */ + setsockopt(connected, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout)); + + /* handle this client */ + while (1) + { + /* receive data from this connection */ + bytes_received = recv(connected,recv_data, TCP_SOCKET_BUFFER_SIZE, 0); + if (bytes_received <= 0) + { + rt_kprintf("close client connection, errno: %d, socket error: %d\n", + rt_get_errno(), + lwip_get_error()); + /* connection closed. */ + lwip_close(connected); + break; + } + + /* send data to client */ + send(connected, recv_data, bytes_received, 0); + } + } + } + +_exit: + /* close socket */ + if (sock != -1) lwip_close(sock); + rt_free(recv_data); + + return ; +} + +/* + * NetIO TCP server + */ + +/* network test utilities entry */ +void net_test(void) +{ + /* start UDP echo server */ + if (udpecho_tid == RT_NULL) + { + udpecho_tid = rt_thread_create("uecho", + udpecho_entry, RT_NULL, + 512, RT_THREAD_PRIORITY_MAX/2, 5); + if (udpecho_tid != RT_NULL) + rt_thread_startup(udpecho_tid); + } + if (udpecho_socket_tid == RT_NULL) + { + udpecho_socket_tid = rt_thread_create("uecho_s", + udpecho_socket_entry, RT_NULL, + 512, RT_THREAD_PRIORITY_MAX/2 + 1, 5); + if (udpecho_socket_tid != RT_NULL) + rt_thread_startup(udpecho_socket_tid); + } + + if (tcpecho_tid == RT_NULL) + { + tcpecho_tid = rt_thread_create("techo", + tcpecho_entry, RT_NULL, + 512, RT_THREAD_PRIORITY_MAX/2 + 2, 5); + if (tcpecho_tid != RT_NULL) + rt_thread_startup(tcpecho_tid); + } + if (tcpecho_socket_tid == RT_NULL) + { + tcpecho_socket_tid = rt_thread_create("techo_s", + tcpecho_socket_entry, RT_NULL, + 512, RT_THREAD_PRIORITY_MAX/2 + 3, 5); + if (tcpecho_socket_tid != RT_NULL) + rt_thread_startup(tcpecho_socket_tid); + } +} +FINSH_FUNCTION_EXPORT(net_test, network test); + diff --git a/libcpu/arm/AT91SAM7S/AT91SAM7S.h b/libcpu/arm/AT91SAM7S/AT91SAM7S.h index 3f0fef709775f7cf78df5768d353ae1d427f1a4b..0c8d652c198ebb1ee947abbb6c3784147661dc05 100644 --- a/libcpu/arm/AT91SAM7S/AT91SAM7S.h +++ b/libcpu/arm/AT91SAM7S/AT91SAM7S.h @@ -57,11 +57,11 @@ extern "C" { #define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ #define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ -/* ========== Register definition for PITC peripheral ========== */ -#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ -#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ -#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ -#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ +#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ +#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ +#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ /* ========== Register definition for UDP peripheral ========== */ #define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ @@ -241,42 +241,42 @@ extern "C" { #define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ #define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ -/******************************************************************************/ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ -/******************************************************************************/ -#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91C_ID_SYS 1 /* System Peripheral */ -#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ +/******************************************************************************/ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ +/******************************************************************************/ +#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS 1 /* System Peripheral */ +#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ #define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ -#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ -#define AT91C_ID_US0 6 /* USART 0 */ -#define AT91C_ID_US1 7 /* USART 1 */ -#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ -#define AT91C_ID_TWI 9 /* Two-Wire Interface */ -#define AT91C_ID_PWMC 10 /* PWM Controller */ -#define AT91C_ID_UDP 11 /* USB Device Port */ -#define AT91C_ID_TC0 12 /* Timer Counter 0 */ -#define AT91C_ID_TC1 13 /* Timer Counter 1 */ -#define AT91C_ID_TC2 14 /* Timer Counter 2 */ -#define AT91C_ID_15 15 /* Reserved */ -#define AT91C_ID_16 16 /* Reserved */ -#define AT91C_ID_17 17 /* Reserved */ -#define AT91C_ID_18 18 /* Reserved */ -#define AT91C_ID_19 19 /* Reserved */ -#define AT91C_ID_20 20 /* Reserved */ -#define AT91C_ID_21 21 /* Reserved */ -#define AT91C_ID_22 22 /* Reserved */ -#define AT91C_ID_23 23 /* Reserved */ -#define AT91C_ID_24 24 /* Reserved */ -#define AT91C_ID_25 25 /* Reserved */ -#define AT91C_ID_26 26 /* Reserved */ -#define AT91C_ID_27 27 /* Reserved */ -#define AT91C_ID_28 28 /* Reserved */ -#define AT91C_ID_29 29 /* Reserved */ -#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ +#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ +#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ +#define AT91C_ID_US0 6 /* USART 0 */ +#define AT91C_ID_US1 7 /* USART 1 */ +#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ +#define AT91C_ID_TWI 9 /* Two-Wire Interface */ +#define AT91C_ID_PWMC 10 /* PWM Controller */ +#define AT91C_ID_UDP 11 /* USB Device Port */ +#define AT91C_ID_TC0 12 /* Timer Counter 0 */ +#define AT91C_ID_TC1 13 /* Timer Counter 1 */ +#define AT91C_ID_TC2 14 /* Timer Counter 2 */ +#define AT91C_ID_15 15 /* Reserved */ +#define AT91C_ID_16 16 /* Reserved */ +#define AT91C_ID_17 17 /* Reserved */ +#define AT91C_ID_18 18 /* Reserved */ +#define AT91C_ID_19 19 /* Reserved */ +#define AT91C_ID_20 20 /* Reserved */ +#define AT91C_ID_21 21 /* Reserved */ +#define AT91C_ID_22 22 /* Reserved */ +#define AT91C_ID_23 23 /* Reserved */ +#define AT91C_ID_24 24 /* Reserved */ +#define AT91C_ID_25 25 /* Reserved */ +#define AT91C_ID_26 26 /* Reserved */ +#define AT91C_ID_27 27 /* Reserved */ +#define AT91C_ID_28 28 /* Reserved */ +#define AT91C_ID_29 29 /* Reserved */ +#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ /*****************************/ /* CPU Mode */ diff --git a/libcpu/arm/AT91SAM7S/context_rvds.S b/libcpu/arm/AT91SAM7S/context_rvds.S index e24fa62a3dd5dd1f46ed2c32255752e171173e46..641ec7a6b1a18b5d8fff4b927e2ad5549ca65f01 100644 --- a/libcpu/arm/AT91SAM7S/context_rvds.S +++ b/libcpu/arm/AT91SAM7S/context_rvds.S @@ -12,12 +12,12 @@ ; * 2009-01-20 Bernard first version ; */ -NOINT EQU 0xc0 ; disable interrupt in psr +NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 + AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1 + MSR cpsr_c, r1 BX lr - ENDP + ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 + MSR cpsr_c, r0 BX lr ENDP @@ -63,7 +63,7 @@ rt_hw_context_switch PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP + ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP + ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread + IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] + STR r1, [r2] BX lr - ENDP - + ENDP + END \ No newline at end of file diff --git a/libcpu/arm/AT91SAM7S/interrupt.c b/libcpu/arm/AT91SAM7S/interrupt.c index cd80a5d408e00c370ea1b4b975b0428d4f4441e6..fd84a72ea3a94fb62f7061d29a72e8f8828c7a18 100644 --- a/libcpu/arm/AT91SAM7S/interrupt.c +++ b/libcpu/arm/AT91SAM7S/interrupt.c @@ -56,11 +56,11 @@ void rt_hw_interrupt_init() * @param vector the interrupt number */ void rt_hw_interrupt_mask(int vector) -{ +{ /* disable interrupt */ - AT91C_AIC_IDCR = 1 << vector; - - /* clear interrupt */ + AT91C_AIC_IDCR = 1 << vector; + + /* clear interrupt */ AT91C_AIC_ICCR = 1 << vector; } diff --git a/libcpu/arm/AT91SAM7S/serial.c b/libcpu/arm/AT91SAM7S/serial.c index c939de88b485798d316bcc850fbc02bef4f9630e..77a7bd86087764e99ae9f43c82ac3f79d36e6031 100644 --- a/libcpu/arm/AT91SAM7S/serial.c +++ b/libcpu/arm/AT91SAM7S/serial.c @@ -9,7 +9,7 @@ * * Change Logs: * Date Author Notes - * 2006-08-23 Bernard first version + * 2006-08-23 Bernard first version * 2009-05-14 Bernard add RT-THread device interface */ @@ -17,142 +17,142 @@ #include #include "AT91SAM7S.h" -#include "serial.h" +#include "serial.h" /** * @addtogroup AT91SAM7 */ -/*@{*/ -typedef volatile rt_uint32_t REG32; -struct rt_at91serial_hw -{ - REG32 US_CR; // Control Register - REG32 US_MR; // Mode Register - REG32 US_IER; // Interrupt Enable Register - REG32 US_IDR; // Interrupt Disable Register - REG32 US_IMR; // Interrupt Mask Register - REG32 US_CSR; // Channel Status Register - REG32 US_RHR; // Receiver Holding Register - REG32 US_THR; // Transmitter Holding Register - REG32 US_BRGR; // Baud Rate Generator Register - REG32 US_RTOR; // Receiver Time-out Register - REG32 US_TTGR; // Transmitter Time-guard Register - REG32 Reserved0[5]; // - REG32 US_FIDI; // FI_DI_Ratio Register - REG32 US_NER; // Nb Errors Register - REG32 Reserved1[1]; // - REG32 US_IF; // IRDA_FILTER Register - REG32 Reserved2[44]; // - REG32 US_RPR; // Receive Pointer Register - REG32 US_RCR; // Receive Counter Register - REG32 US_TPR; // Transmit Pointer Register - REG32 US_TCR; // Transmit Counter Register - REG32 US_RNPR; // Receive Next Pointer Register - REG32 US_RNCR; // Receive Next Counter Register - REG32 US_TNPR; // Transmit Next Pointer Register - REG32 US_TNCR; // Transmit Next Counter Register - REG32 US_PTCR; // PDC Transfer Control Register - REG32 US_PTSR; // PDC Transfer Status Register -}; - -struct rt_at91serial -{ - struct rt_device parent; - - struct rt_at91serial_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; - - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; -}; -#ifdef RT_USING_UART1 -struct rt_at91serial serial1; -#endif -#ifdef RT_USING_UART2 -struct rt_at91serial serial2; -#endif - -static void rt_hw_serial_isr(int irqno) -{ - rt_base_t level; - struct rt_device* device; - struct rt_at91serial* serial = RT_NULL; - - if (irqno == AT91C_ID_US0) - { -#ifdef RT_USING_UART1 - /* serial 1 */ - serial = &serial1; -#endif - } - else if (irqno == AT91C_ID_US1) - { -#ifdef RT_USING_UART2 - /* serial 2 */ - serial = &serial2; -#endif - } - RT_ASSERT(serial != RT_NULL); - - /* get generic device object */ - device = (rt_device_t)serial; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; - - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); - - /* ack interrupt */ - AT91C_AIC_EOICR = 1; -} - -static rt_err_t rt_serial_init (rt_device_t dev) -{ - rt_uint32_t bd; - struct rt_at91serial* serial = (struct rt_at91serial*) dev; - - RT_ASSERT(serial != RT_NULL); - /* must be US0 or US1 */ - RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || - (serial->peripheral_id == AT91C_ID_US1))); - - /* Enable Clock for USART */ - AT91C_PMC_PCER = 1 << serial->peripheral_id; +/*@{*/ +typedef volatile rt_uint32_t REG32; +struct rt_at91serial_hw +{ + REG32 US_CR; // Control Register + REG32 US_MR; // Mode Register + REG32 US_IER; // Interrupt Enable Register + REG32 US_IDR; // Interrupt Disable Register + REG32 US_IMR; // Interrupt Mask Register + REG32 US_CSR; // Channel Status Register + REG32 US_RHR; // Receiver Holding Register + REG32 US_THR; // Transmitter Holding Register + REG32 US_BRGR; // Baud Rate Generator Register + REG32 US_RTOR; // Receiver Time-out Register + REG32 US_TTGR; // Transmitter Time-guard Register + REG32 Reserved0[5]; // + REG32 US_FIDI; // FI_DI_Ratio Register + REG32 US_NER; // Nb Errors Register + REG32 Reserved1[1]; // + REG32 US_IF; // IRDA_FILTER Register + REG32 Reserved2[44]; // + REG32 US_RPR; // Receive Pointer Register + REG32 US_RCR; // Receive Counter Register + REG32 US_TPR; // Transmit Pointer Register + REG32 US_TCR; // Transmit Counter Register + REG32 US_RNPR; // Receive Next Pointer Register + REG32 US_RNCR; // Receive Next Counter Register + REG32 US_TNPR; // Transmit Next Pointer Register + REG32 US_TNCR; // Transmit Next Counter Register + REG32 US_PTCR; // PDC Transfer Control Register + REG32 US_PTSR; // PDC Transfer Status Register +}; + +struct rt_at91serial +{ + struct rt_device parent; + + struct rt_at91serial_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; + + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; +}; +#ifdef RT_USING_UART1 +struct rt_at91serial serial1; +#endif +#ifdef RT_USING_UART2 +struct rt_at91serial serial2; +#endif + +static void rt_hw_serial_isr(int irqno) +{ + rt_base_t level; + struct rt_device* device; + struct rt_at91serial* serial = RT_NULL; + + if (irqno == AT91C_ID_US0) + { +#ifdef RT_USING_UART1 + /* serial 1 */ + serial = &serial1; +#endif + } + else if (irqno == AT91C_ID_US1) + { +#ifdef RT_USING_UART2 + /* serial 2 */ + serial = &serial2; +#endif + } + RT_ASSERT(serial != RT_NULL); + + /* get generic device object */ + device = (rt_device_t)serial; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; + + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); + + /* ack interrupt */ + AT91C_AIC_EOICR = 1; +} + +static rt_err_t rt_serial_init (rt_device_t dev) +{ + rt_uint32_t bd; + struct rt_at91serial* serial = (struct rt_at91serial*) dev; + + RT_ASSERT(serial != RT_NULL); + /* must be US0 or US1 */ + RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || + (serial->peripheral_id == AT91C_ID_US1))); + + /* Enable Clock for USART */ + AT91C_PMC_PCER = 1 << serial->peripheral_id; /* Enable RxD0 and TxDO Pin */ - if (serial->peripheral_id == AT91C_ID_US0) - { + if (serial->peripheral_id == AT91C_ID_US0) + { /* set pinmux */ - AT91C_PIO_PDR = (1 << 5) | (1 << 6); - } - else if (serial->peripheral_id == AT91C_ID_US1) - { + AT91C_PIO_PDR = (1 << 5) | (1 << 6); + } + else if (serial->peripheral_id == AT91C_ID_US1) + { /* set pinmux */ - AT91C_PIO_PDR = (1 << 21) | (1 << 22); - } + AT91C_PIO_PDR = (1 << 21) | (1 << 22); + } serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ AT91C_US_RSTTX | /* Reset Transmitter */ @@ -165,143 +165,143 @@ static rt_err_t rt_serial_init (rt_device_t dev) AT91C_US_PAR_NONE | /* No Parity */ AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - /* set baud rate divisor */ - bd = ((MCK*10)/(serial->baudrate * 16)); - if ((bd % 10) >= 5) bd = (bd / 10) + 1; - else bd /= 10; - - serial->hw_base->US_BRGR = bd; + /* set baud rate divisor */ + bd = ((MCK*10)/(serial->baudrate * 16)); + if ((bd % 10) >= 5) bd = (bd / 10) + 1; + else bd /= 10; + + serial->hw_base->US_BRGR = bd; serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */ - - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; - - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - - return RT_EOK; -} - -static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ - - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); - AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); - rt_hw_interrupt_umask(serial->peripheral_id); - } - - return RT_EOK; -} - -static rt_err_t rt_serial_close(rt_device_t dev) -{ - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ - } + AT91C_US_TXEN; /* Transmitter Enable */ + + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; + + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + + return RT_EOK; +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ + + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); + AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); + rt_hw_interrupt_umask(serial->peripheral_id); + } return RT_EOK; -} - -static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; - - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ + } + + return RT_EOK; +} + +static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; + + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { /* Wait for Full Rx Buffer */ while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); /* Read Character */ - *ptr = serial->hw_base->US_RHR; - ptr ++; + *ptr = serial->hw_base->US_RHR; + ptr ++; size --; - } - - return (rt_size_t)ptr - (rt_size_t)buffer; - } - - return 0; -} - -static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ + } + + return (rt_size_t)ptr - (rt_size_t)buffer; + } + + return 0; +} + +static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ if (*ptr == '\n') { while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); @@ -312,76 +312,76 @@ static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buf while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); /* Transmit Character */ - serial->hw_base->US_THR = *ptr; + serial->hw_base->US_THR = *ptr; ptr ++; size --; - } - } - else - { - while (size) - { + } + } + else + { + while (size) + { /* Wait for Empty Tx Buffer */ while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - } - - return (rt_size_t)ptr - (rt_size_t)buffer; -} - -static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) -{ - return RT_EOK; -} - -rt_err_t rt_hw_serial_init() -{ - rt_device_t device; - -#ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; - - /* init serial device private data */ - serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; - serial1.peripheral_id = AT91C_ID_US0; - serial1.baudrate = 115200; - - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); -#endif - -#ifdef RT_USING_UART2 - device = (rt_device_t) &serial2; - - serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; - serial2.peripheral_id = AT91C_ID_US1; - serial2.baudrate = 115200; - - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - - /* register uart2 on device subsystem */ - rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); -#endif - - return RT_EOK; -} - + serial->hw_base->US_THR = *ptr; + ptr ++; size --; + } + } + } + + return (rt_size_t)ptr - (rt_size_t)buffer; +} + +static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +rt_err_t rt_hw_serial_init() +{ + rt_device_t device; + +#ifdef RT_USING_UART1 + device = (rt_device_t) &serial1; + + /* init serial device private data */ + serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; + serial1.peripheral_id = AT91C_ID_US0; + serial1.baudrate = 115200; + + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); +#endif + +#ifdef RT_USING_UART2 + device = (rt_device_t) &serial2; + + serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; + serial2.peripheral_id = AT91C_ID_US1; + serial2.baudrate = 115200; + + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + + /* register uart2 on device subsystem */ + rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); +#endif + + return RT_EOK; +} + /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/serial.h b/libcpu/arm/AT91SAM7S/serial.h index 5fe0928c9a9669c4e077c1c34c8b412d8487453d..401b0c3129435d12bcbd496c8f0c45a89c7312d4 100644 --- a/libcpu/arm/AT91SAM7S/serial.h +++ b/libcpu/arm/AT91SAM7S/serial.h @@ -1,14 +1,14 @@ -#ifndef __RT_SERIAL_H__ -#define __RT_SERIAL_H__ - -#ifndef AT91C_BASE_US0 -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#endif - -#ifndef AT91C_BASE_US1 -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#endif - +#ifndef __RT_SERIAL_H__ +#define __RT_SERIAL_H__ + +#ifndef AT91C_BASE_US0 +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#endif + +#ifndef AT91C_BASE_US1 +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#endif + #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ @@ -52,5 +52,5 @@ #define MCK 48054857 #define BR 115200 /* Baud Rate */ #define BRD (MCK/16/BR) /* Baud Rate Divisor */ - -#endif + +#endif diff --git a/libcpu/arm/AT91SAM7S/start_rvds.S b/libcpu/arm/AT91SAM7S/start_rvds.S index a4e403c1af615841d91eb448b7cdff45e9d5855d..84274bbe20901582c3b5c01c4a2429cbeecc5618 100644 --- a/libcpu/arm/AT91SAM7S/start_rvds.S +++ b/libcpu/arm/AT91SAM7S/start_rvds.S @@ -1,499 +1,499 @@ -;/*****************************************************************************/ -;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -;/* -; * The SAM7.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * REMAP: when set the startup code remaps exception vectors from -; * on-chip RAM to address 0. -; * -; * RAM_INTVEC: when set the startup code copies exception vectors -; * from on-chip Flash to on-chip RAM. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -; Internal Memory Base Addresses -FLASH_BASE EQU 0x00100000 -RAM_BASE EQU 0x00200000 - - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000100 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000100 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -; Reset Controller (RSTC) definitions -RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address -RSTC_MR EQU 0x08 ; RSTC_MR Offset - -;/* -;// Reset Controller (RSTC) -;// URSTEN: User Reset Enable -;// Enables NRST Pin to generate Reset -;// ERSTL: External Reset Length <0-15> -;// External Reset Time in 2^(ERSTL+1) Slow Clock Cycles -;// -;*/ -RSTC_SETUP EQU 1 -RSTC_MR_Val EQU 0xA5000401 - - -; Embedded Flash Controller (EFC) definitions -EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address -EFC0_FMR EQU 0x60 ; EFC0_FMR Offset -EFC1_FMR EQU 0x70 ; EFC1_FMR Offset - -;// Embedded Flash Controller 0 (EFC0) -;// FMCN: Flash Microsecond Cycle Number <0-255> -;// Number of Master Clock Cycles in 1us -;// FWS: Flash Wait State -;// <0=> Read: 1 cycle / Write: 2 cycles -;// <1=> Read: 2 cycle / Write: 3 cycles -;// <2=> Read: 3 cycle / Write: 4 cycles -;// <3=> Read: 4 cycle / Write: 4 cycles -;// -EFC0_SETUP EQU 1 -EFC0_FMR_Val EQU 0x00320100 - -;// Embedded Flash Controller 1 (EFC1) -;// FMCN: Flash Microsecond Cycle Number <0-255> -;// Number of Master Clock Cycles in 1us -;// FWS: Flash Wait State -;// <0=> Read: 1 cycle / Write: 2 cycles -;// <1=> Read: 2 cycle / Write: 3 cycles -;// <2=> Read: 3 cycle / Write: 4 cycles -;// <3=> Read: 4 cycle / Write: 4 cycles -;// -EFC1_SETUP EQU 0 -EFC1_FMR_Val EQU 0x00320100 - - -; Watchdog Timer (WDT) definitions -WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address -WDT_MR EQU 0x04 ; WDT_MR Offset - -;// Watchdog Timer (WDT) -;// WDV: Watchdog Counter Value <0-4095> -;// WDD: Watchdog Delta Value <0-4095> -;// WDFIEN: Watchdog Fault Interrupt Enable -;// WDRSTEN: Watchdog Reset Enable -;// WDRPROC: Watchdog Reset Processor -;// WDDBGHLT: Watchdog Debug Halt -;// WDIDLEHLT: Watchdog Idle Halt -;// WDDIS: Watchdog Disable -;// -WDT_SETUP EQU 1 -WDT_MR_Val EQU 0x00008000 - - -; Power Mangement Controller (PMC) definitions -PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address -PMC_MOR EQU 0x20 ; PMC_MOR Offset -PMC_MCFR EQU 0x24 ; PMC_MCFR Offset -PMC_PLLR EQU 0x2C ; PMC_PLLR Offset -PMC_MCKR EQU 0x30 ; PMC_MCKR Offset -PMC_SR EQU 0x68 ; PMC_SR Offset -PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable -PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass -PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time -PMC_DIV EQU (0xFF<<0) ; PLL Divider -PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter -PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range -PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier -PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider -PMC_CSS EQU (3<<0) ; Clock Source Selection -PMC_PRES EQU (7<<2) ; Prescaler Selection -PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable -PMC_LOCK EQU (1<<2) ; PLL Lock Status -PMC_MCKRDY EQU (1<<3) ; Master Clock Status - -;// Power Mangement Controller (PMC) -;// Main Oscillator -;// MOSCEN: Main Oscillator Enable -;// OSCBYPASS: Oscillator Bypass -;// OSCCOUNT: Main Oscillator Startup Time <0-255> -;// -;// Phase Locked Loop (PLL) -;// DIV: PLL Divider <0-255> -;// MUL: PLL Multiplier <0-2047> -;// PLL Output is multiplied by MUL+1 -;// OUT: PLL Clock Frequency Range -;// <0=> 80..160MHz <1=> Reserved -;// <2=> 150..220MHz <3=> Reserved -;// PLLCOUNT: PLL Lock Counter <0-63> -;// USBDIV: USB Clock Divider -;// <0=> None <1=> 2 <2=> 4 <3=> Reserved -;// -;// CSS: Clock Source Selection -;// <0=> Slow Clock -;// <1=> Main Clock -;// <2=> Reserved -;// <3=> PLL Clock -;// PRES: Prescaler -;// <0=> None -;// <1=> Clock / 2 <2=> Clock / 4 -;// <3=> Clock / 8 <4=> Clock / 16 -;// <5=> Clock / 32 <6=> Clock / 64 -;// <7=> Reserved -;// -PMC_SETUP EQU 1 -PMC_MOR_Val EQU 0x00000601 -PMC_PLLR_Val EQU 0x00191C05 -PMC_MCKR_Val EQU 0x00000007 - - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC,Reset_Addr - LDR PC,Undef_Addr - LDR PC,SWI_Addr - LDR PC,PAbt_Addr - LDR PC,DAbt_Addr - NOP ; Reserved Vector - LDR PC,IRQ_Addr - LDR PC,FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B PAbt_Handler -DAbt_Handler B DAbt_Handler -FIQ_Handler B FIQ_Handler - - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Setup RSTC - IF RSTC_SETUP != 0 - LDR R0, =RSTC_BASE - LDR R1, =RSTC_MR_Val - STR R1, [R0, #RSTC_MR] - ENDIF - - -; Setup EFC0 - IF EFC0_SETUP != 0 - LDR R0, =EFC_BASE - LDR R1, =EFC0_FMR_Val - STR R1, [R0, #EFC0_FMR] - ENDIF - -; Setup EFC1 - IF EFC1_SETUP != 0 - LDR R0, =EFC_BASE - LDR R1, =EFC1_FMR_Val - STR R1, [R0, #EFC1_FMR] - ENDIF - -; Setup WDT - IF WDT_SETUP != 0 - LDR R0, =WDT_BASE - LDR R1, =WDT_MR_Val - STR R1, [R0, #WDT_MR] - ENDIF - - -; Setup PMC - IF PMC_SETUP != 0 - LDR R0, =PMC_BASE - -; Setup Main Oscillator - LDR R1, =PMC_MOR_Val - STR R1, [R0, #PMC_MOR] - -; Wait until Main Oscillator is stablilized - IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0 -MOSCS_Loop LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MOSCS - BEQ MOSCS_Loop - ENDIF - -; Setup the PLL - IF (PMC_PLLR_Val:AND:PMC_MUL) != 0 - LDR R1, =PMC_PLLR_Val - STR R1, [R0, #PMC_PLLR] - -; Wait until PLL is stabilized -PLL_Loop LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_LOCK - BEQ PLL_Loop - ENDIF - -; Select Clock - IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected - LDR R1, =PMC_MCKR_Val - AND R1, #PMC_CSS - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy1 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy1 - LDR R1, =PMC_MCKR_Val - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy2 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy2 - ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected - LDR R1, =PMC_MCKR_Val - AND R1, #PMC_PRES - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy1 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy1 - LDR R1, =PMC_MCKR_Val - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy2 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy2 - ENDIF ; Select Clock - ENDIF ; PMC_SETUP - - -; Copy Exception Vectors to Internal RAM - - IF :DEF:RAM_INTVEC - ADR R8, Vectors ; Source - LDR R9, =RAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - ENDIF - - -; Remap on-chip RAM to address 0 - -MC_BASE EQU 0xFFFFFF00 ; MC Base Address -MC_RCR EQU 0x00 ; MC_RCR Offset - - IF :DEF:REMAP - LDR R0, =MC_BASE - MOV R1, #1 - STR R1, [R0, #MC_RCR] ; Remap - ENDIF - - -; Setup Stack for each mode - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; MSR CPSR_c, #Mode_USR - IF :DEF:__MICROLIB - - EXPORT __initial_sp - - ELSE - - ; No usr mode stack here. - ;MOV SP, R0 - ;SUB SL, SP, #USR_Stack_Size - - ENDIF - - -; Enter the C code - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + IRQ_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - END +;/*****************************************************************************/ +;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The SAM7.S code is executed after CPU Reset. This file may be +; * translated with the following SET symbols. In uVision these SET +; * symbols are entered under Options - ASM - Define. +; * +; * REMAP: when set the startup code remaps exception vectors from +; * on-chip RAM to address 0. +; * +; * RAM_INTVEC: when set the startup code copies exception vectors +; * from on-chip Flash to on-chip RAM. +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +; Internal Memory Base Addresses +FLASH_BASE EQU 0x00100000 +RAM_BASE EQU 0x00200000 + + +;// Stack Configuration (Stack Sizes in Bytes) +;// Undefined Mode <0x0-0xFFFFFFFF:8> +;// Supervisor Mode <0x0-0xFFFFFFFF:8> +;// Abort Mode <0x0-0xFFFFFFFF:8> +;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// Interrupt Mode <0x0-0xFFFFFFFF:8> +;// User/System Mode <0x0-0xFFFFFFFF:8> +;// + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size +Stack_Top + + +;// Heap Configuration +;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +; Reset Controller (RSTC) definitions +RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address +RSTC_MR EQU 0x08 ; RSTC_MR Offset + +;/* +;// Reset Controller (RSTC) +;// URSTEN: User Reset Enable +;// Enables NRST Pin to generate Reset +;// ERSTL: External Reset Length <0-15> +;// External Reset Time in 2^(ERSTL+1) Slow Clock Cycles +;// +;*/ +RSTC_SETUP EQU 1 +RSTC_MR_Val EQU 0xA5000401 + + +; Embedded Flash Controller (EFC) definitions +EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address +EFC0_FMR EQU 0x60 ; EFC0_FMR Offset +EFC1_FMR EQU 0x70 ; EFC1_FMR Offset + +;// Embedded Flash Controller 0 (EFC0) +;// FMCN: Flash Microsecond Cycle Number <0-255> +;// Number of Master Clock Cycles in 1us +;// FWS: Flash Wait State +;// <0=> Read: 1 cycle / Write: 2 cycles +;// <1=> Read: 2 cycle / Write: 3 cycles +;// <2=> Read: 3 cycle / Write: 4 cycles +;// <3=> Read: 4 cycle / Write: 4 cycles +;// +EFC0_SETUP EQU 1 +EFC0_FMR_Val EQU 0x00320100 + +;// Embedded Flash Controller 1 (EFC1) +;// FMCN: Flash Microsecond Cycle Number <0-255> +;// Number of Master Clock Cycles in 1us +;// FWS: Flash Wait State +;// <0=> Read: 1 cycle / Write: 2 cycles +;// <1=> Read: 2 cycle / Write: 3 cycles +;// <2=> Read: 3 cycle / Write: 4 cycles +;// <3=> Read: 4 cycle / Write: 4 cycles +;// +EFC1_SETUP EQU 0 +EFC1_FMR_Val EQU 0x00320100 + + +; Watchdog Timer (WDT) definitions +WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address +WDT_MR EQU 0x04 ; WDT_MR Offset + +;// Watchdog Timer (WDT) +;// WDV: Watchdog Counter Value <0-4095> +;// WDD: Watchdog Delta Value <0-4095> +;// WDFIEN: Watchdog Fault Interrupt Enable +;// WDRSTEN: Watchdog Reset Enable +;// WDRPROC: Watchdog Reset Processor +;// WDDBGHLT: Watchdog Debug Halt +;// WDIDLEHLT: Watchdog Idle Halt +;// WDDIS: Watchdog Disable +;// +WDT_SETUP EQU 1 +WDT_MR_Val EQU 0x00008000 + + +; Power Mangement Controller (PMC) definitions +PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address +PMC_MOR EQU 0x20 ; PMC_MOR Offset +PMC_MCFR EQU 0x24 ; PMC_MCFR Offset +PMC_PLLR EQU 0x2C ; PMC_PLLR Offset +PMC_MCKR EQU 0x30 ; PMC_MCKR Offset +PMC_SR EQU 0x68 ; PMC_SR Offset +PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable +PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass +PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time +PMC_DIV EQU (0xFF<<0) ; PLL Divider +PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter +PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range +PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier +PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider +PMC_CSS EQU (3<<0) ; Clock Source Selection +PMC_PRES EQU (7<<2) ; Prescaler Selection +PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable +PMC_LOCK EQU (1<<2) ; PLL Lock Status +PMC_MCKRDY EQU (1<<3) ; Master Clock Status + +;// Power Mangement Controller (PMC) +;// Main Oscillator +;// MOSCEN: Main Oscillator Enable +;// OSCBYPASS: Oscillator Bypass +;// OSCCOUNT: Main Oscillator Startup Time <0-255> +;// +;// Phase Locked Loop (PLL) +;// DIV: PLL Divider <0-255> +;// MUL: PLL Multiplier <0-2047> +;// PLL Output is multiplied by MUL+1 +;// OUT: PLL Clock Frequency Range +;// <0=> 80..160MHz <1=> Reserved +;// <2=> 150..220MHz <3=> Reserved +;// PLLCOUNT: PLL Lock Counter <0-63> +;// USBDIV: USB Clock Divider +;// <0=> None <1=> 2 <2=> 4 <3=> Reserved +;// +;// CSS: Clock Source Selection +;// <0=> Slow Clock +;// <1=> Main Clock +;// <2=> Reserved +;// <3=> PLL Clock +;// PRES: Prescaler +;// <0=> None +;// <1=> Clock / 2 <2=> Clock / 4 +;// <3=> Clock / 8 <4=> Clock / 16 +;// <5=> Clock / 32 <6=> Clock / 64 +;// <7=> Reserved +;// +PMC_SETUP EQU 1 +PMC_MOR_Val EQU 0x00000601 +PMC_PLLR_Val EQU 0x00191C05 +PMC_MCKR_Val EQU 0x00000007 + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + +Vectors LDR PC,Reset_Addr + LDR PC,Undef_Addr + LDR PC,SWI_Addr + LDR PC,PAbt_Addr + LDR PC,DAbt_Addr + NOP ; Reserved Vector + LDR PC,IRQ_Addr + LDR PC,FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B PAbt_Handler +DAbt_Handler B DAbt_Handler +FIQ_Handler B FIQ_Handler + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; Setup RSTC + IF RSTC_SETUP != 0 + LDR R0, =RSTC_BASE + LDR R1, =RSTC_MR_Val + STR R1, [R0, #RSTC_MR] + ENDIF + + +; Setup EFC0 + IF EFC0_SETUP != 0 + LDR R0, =EFC_BASE + LDR R1, =EFC0_FMR_Val + STR R1, [R0, #EFC0_FMR] + ENDIF + +; Setup EFC1 + IF EFC1_SETUP != 0 + LDR R0, =EFC_BASE + LDR R1, =EFC1_FMR_Val + STR R1, [R0, #EFC1_FMR] + ENDIF + +; Setup WDT + IF WDT_SETUP != 0 + LDR R0, =WDT_BASE + LDR R1, =WDT_MR_Val + STR R1, [R0, #WDT_MR] + ENDIF + + +; Setup PMC + IF PMC_SETUP != 0 + LDR R0, =PMC_BASE + +; Setup Main Oscillator + LDR R1, =PMC_MOR_Val + STR R1, [R0, #PMC_MOR] + +; Wait until Main Oscillator is stablilized + IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0 +MOSCS_Loop LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MOSCS + BEQ MOSCS_Loop + ENDIF + +; Setup the PLL + IF (PMC_PLLR_Val:AND:PMC_MUL) != 0 + LDR R1, =PMC_PLLR_Val + STR R1, [R0, #PMC_PLLR] + +; Wait until PLL is stabilized +PLL_Loop LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_LOCK + BEQ PLL_Loop + ENDIF + +; Select Clock + IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected + LDR R1, =PMC_MCKR_Val + AND R1, #PMC_CSS + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy1 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy1 + LDR R1, =PMC_MCKR_Val + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy2 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy2 + ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected + LDR R1, =PMC_MCKR_Val + AND R1, #PMC_PRES + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy1 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy1 + LDR R1, =PMC_MCKR_Val + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy2 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy2 + ENDIF ; Select Clock + ENDIF ; PMC_SETUP + + +; Copy Exception Vectors to Internal RAM + + IF :DEF:RAM_INTVEC + ADR R8, Vectors ; Source + LDR R9, =RAM_BASE ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + ENDIF + + +; Remap on-chip RAM to address 0 + +MC_BASE EQU 0xFFFFFF00 ; MC Base Address +MC_RCR EQU 0x00 ; MC_RCR Offset + + IF :DEF:REMAP + LDR R0, =MC_BASE + MOV R1, #1 + STR R1, [R0, #MC_RCR] ; Remap + ENDIF + + +; Setup Stack for each mode + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; MSR CPSR_c, #Mode_USR + IF :DEF:__MICROLIB + + EXPORT __initial_sp + + ELSE + + ; No usr mode stack here. + ;MOV SP, R0 + ;SUB SL, SP, #USR_Stack_Size + + ENDIF + + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + IRQ_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + END diff --git a/libcpu/arm/AT91SAM7X/start_rvds.S b/libcpu/arm/AT91SAM7X/start_rvds.S index eaee2a39eab2f09adc8e6697fa3bb861ec67db81..976096563c34d746bb6cdecbd8db40386fbec50b 100644 --- a/libcpu/arm/AT91SAM7X/start_rvds.S +++ b/libcpu/arm/AT91SAM7X/start_rvds.S @@ -1,517 +1,517 @@ -;/*****************************************************************************/ -;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -;/* -; * The SAM7.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * REMAP: when set the startup code remaps exception vectors from -; * on-chip RAM to address 0. -; * -; * RAM_INTVEC: when set the startup code copies exception vectors -; * from on-chip Flash to on-chip RAM. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -; 2009-12-28 MingBai Bug fix (USR mode stack removed). -; 2009-12-29 MingBai Merge svc and irq stack, add abort handler. - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -; Internal Memory Base Addresses -FLASH_BASE EQU 0x00100000 -RAM_BASE EQU 0x00200000 - - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000000 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000000 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -; Reset Controller (RSTC) definitions -RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address -RSTC_MR EQU 0x08 ; RSTC_MR Offset - -;/* -;// Reset Controller (RSTC) -;// URSTEN: User Reset Enable -;// Enables NRST Pin to generate Reset -;// ERSTL: External Reset Length <0-15> -;// External Reset Time in 2^(ERSTL+1) Slow Clock Cycles -;// -;*/ -RSTC_SETUP EQU 1 -RSTC_MR_Val EQU 0xA5000401 - - -; Embedded Flash Controller (EFC) definitions -EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address -EFC0_FMR EQU 0x60 ; EFC0_FMR Offset -EFC1_FMR EQU 0x70 ; EFC1_FMR Offset - -;// Embedded Flash Controller 0 (EFC0) -;// FMCN: Flash Microsecond Cycle Number <0-255> -;// Number of Master Clock Cycles in 1us -;// FWS: Flash Wait State -;// <0=> Read: 1 cycle / Write: 2 cycles -;// <1=> Read: 2 cycle / Write: 3 cycles -;// <2=> Read: 3 cycle / Write: 4 cycles -;// <3=> Read: 4 cycle / Write: 4 cycles -;// -EFC0_SETUP EQU 1 -EFC0_FMR_Val EQU 0x00320100 - -;// Embedded Flash Controller 1 (EFC1) -;// FMCN: Flash Microsecond Cycle Number <0-255> -;// Number of Master Clock Cycles in 1us -;// FWS: Flash Wait State -;// <0=> Read: 1 cycle / Write: 2 cycles -;// <1=> Read: 2 cycle / Write: 3 cycles -;// <2=> Read: 3 cycle / Write: 4 cycles -;// <3=> Read: 4 cycle / Write: 4 cycles -;// -EFC1_SETUP EQU 0 -EFC1_FMR_Val EQU 0x00320100 - - -; Watchdog Timer (WDT) definitions -WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address -WDT_MR EQU 0x04 ; WDT_MR Offset - -;// Watchdog Timer (WDT) -;// WDV: Watchdog Counter Value <0-4095> -;// WDD: Watchdog Delta Value <0-4095> -;// WDFIEN: Watchdog Fault Interrupt Enable -;// WDRSTEN: Watchdog Reset Enable -;// WDRPROC: Watchdog Reset Processor -;// WDDBGHLT: Watchdog Debug Halt -;// WDIDLEHLT: Watchdog Idle Halt -;// WDDIS: Watchdog Disable -;// -WDT_SETUP EQU 1 -WDT_MR_Val EQU 0x00008000 - - -; Power Mangement Controller (PMC) definitions -PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address -PMC_MOR EQU 0x20 ; PMC_MOR Offset -PMC_MCFR EQU 0x24 ; PMC_MCFR Offset -PMC_PLLR EQU 0x2C ; PMC_PLLR Offset -PMC_MCKR EQU 0x30 ; PMC_MCKR Offset -PMC_SR EQU 0x68 ; PMC_SR Offset -PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable -PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass -PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time -PMC_DIV EQU (0xFF<<0) ; PLL Divider -PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter -PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range -PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier -PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider -PMC_CSS EQU (3<<0) ; Clock Source Selection -PMC_PRES EQU (7<<2) ; Prescaler Selection -PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable -PMC_LOCK EQU (1<<2) ; PLL Lock Status -PMC_MCKRDY EQU (1<<3) ; Master Clock Status - -;// Power Mangement Controller (PMC) -;// Main Oscillator -;// MOSCEN: Main Oscillator Enable -;// OSCBYPASS: Oscillator Bypass -;// OSCCOUNT: Main Oscillator Startup Time <0-255> -;// -;// Phase Locked Loop (PLL) -;// DIV: PLL Divider <0-255> -;// MUL: PLL Multiplier <0-2047> -;// PLL Output is multiplied by MUL+1 -;// OUT: PLL Clock Frequency Range -;// <0=> 80..160MHz <1=> Reserved -;// <2=> 150..220MHz <3=> Reserved -;// PLLCOUNT: PLL Lock Counter <0-63> -;// USBDIV: USB Clock Divider -;// <0=> None <1=> 2 <2=> 4 <3=> Reserved -;// -;// CSS: Clock Source Selection -;// <0=> Slow Clock -;// <1=> Main Clock -;// <2=> Reserved -;// <3=> PLL Clock -;// PRES: Prescaler -;// <0=> None -;// <1=> Clock / 2 <2=> Clock / 4 -;// <3=> Clock / 8 <4=> Clock / 16 -;// <5=> Clock / 32 <6=> Clock / 64 -;// <7=> Reserved -;// -PMC_SETUP EQU 1 -PMC_MOR_Val EQU 0x00000601 -PMC_PLLR_Val EQU 0x00191C05 -PMC_MCKR_Val EQU 0x00000007 - - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC,Reset_Addr - LDR PC,Undef_Addr - LDR PC,SWI_Addr - LDR PC,PAbt_Addr - LDR PC,DAbt_Addr - NOP ; Reserved Vector - LDR PC,IRQ_Addr - LDR PC,FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B Abort_Handler -DAbt_Handler B Abort_Handler -FIQ_Handler B FIQ_Handler - - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Setup RSTC - IF RSTC_SETUP != 0 - LDR R0, =RSTC_BASE - LDR R1, =RSTC_MR_Val - STR R1, [R0, #RSTC_MR] - ENDIF - - -; Setup EFC0 - IF EFC0_SETUP != 0 - LDR R0, =EFC_BASE - LDR R1, =EFC0_FMR_Val - STR R1, [R0, #EFC0_FMR] - ENDIF - -; Setup EFC1 - IF EFC1_SETUP != 0 - LDR R0, =EFC_BASE - LDR R1, =EFC1_FMR_Val - STR R1, [R0, #EFC1_FMR] - ENDIF - -; Setup WDT - IF WDT_SETUP != 0 - LDR R0, =WDT_BASE - LDR R1, =WDT_MR_Val - STR R1, [R0, #WDT_MR] - ENDIF - - -; Setup PMC - IF PMC_SETUP != 0 - LDR R0, =PMC_BASE - -; Setup Main Oscillator - LDR R1, =PMC_MOR_Val - STR R1, [R0, #PMC_MOR] - -; Wait until Main Oscillator is stablilized - IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0 -MOSCS_Loop LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MOSCS - BEQ MOSCS_Loop - ENDIF - -; Setup the PLL - IF (PMC_PLLR_Val:AND:PMC_MUL) != 0 - LDR R1, =PMC_PLLR_Val - STR R1, [R0, #PMC_PLLR] - -; Wait until PLL is stabilized -PLL_Loop LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_LOCK - BEQ PLL_Loop - ENDIF - -; Select Clock - IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected - LDR R1, =PMC_MCKR_Val - AND R1, #PMC_CSS - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy1 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy1 - LDR R1, =PMC_MCKR_Val - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy2 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy2 - ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected - LDR R1, =PMC_MCKR_Val - AND R1, #PMC_PRES - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy1 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy1 - LDR R1, =PMC_MCKR_Val - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy2 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy2 - ENDIF ; Select Clock - ENDIF ; PMC_SETUP - - -; Copy Exception Vectors to Internal RAM - - IF :DEF:RAM_INTVEC - ADR R8, Vectors ; Source - LDR R9, =RAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - ENDIF - - -; Remap on-chip RAM to address 0 - -MC_BASE EQU 0xFFFFFF00 ; MC Base Address -MC_RCR EQU 0x00 ; MC_RCR Offset - - IF :DEF:REMAP - LDR R0, =MC_BASE - MOV R1, #1 - STR R1, [R0, #MC_RCR] ; Remap - ENDIF - - -; Setup Stack for each mode - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ;SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ;SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ;SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ;SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ; SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; MSR CPSR_c, #Mode_USR - IF :DEF:__MICROLIB - - EXPORT __initial_sp - - ELSE - - ; No usr mode stack here. - ;MOV SP, R0 - ;SUB SL, SP, #USR_Stack_Size - - ENDIF - - -; Enter the C code - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - IMPORT rt_hw_trap_abort - IMPORT rt_interrupt_nest - -Abort_Handler PROC - EXPORT Abort_Handler - stmfd sp!, {r0-r12,lr} - LDR r0, =rt_interrupt_nest - LDR r1, [r0] - CMP r1, #0 -DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system. - bl rt_interrupt_enter - bl rt_hw_trap_abort - bl rt_interrupt_leave - b SWITCH - ENDP - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return -SWITCH LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + IRQ_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - END +;/*****************************************************************************/ +;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The SAM7.S code is executed after CPU Reset. This file may be +; * translated with the following SET symbols. In uVision these SET +; * symbols are entered under Options - ASM - Define. +; * +; * REMAP: when set the startup code remaps exception vectors from +; * on-chip RAM to address 0. +; * +; * RAM_INTVEC: when set the startup code copies exception vectors +; * from on-chip Flash to on-chip RAM. +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +; 2009-12-28 MingBai Bug fix (USR mode stack removed). +; 2009-12-29 MingBai Merge svc and irq stack, add abort handler. + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +; Internal Memory Base Addresses +FLASH_BASE EQU 0x00100000 +RAM_BASE EQU 0x00200000 + + +;// Stack Configuration (Stack Sizes in Bytes) +;// Undefined Mode <0x0-0xFFFFFFFF:8> +;// Supervisor Mode <0x0-0xFFFFFFFF:8> +;// Abort Mode <0x0-0xFFFFFFFF:8> +;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// Interrupt Mode <0x0-0xFFFFFFFF:8> +;// User/System Mode <0x0-0xFFFFFFFF:8> +;// + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000000 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000000 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size +Stack_Top + + +;// Heap Configuration +;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +; Reset Controller (RSTC) definitions +RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address +RSTC_MR EQU 0x08 ; RSTC_MR Offset + +;/* +;// Reset Controller (RSTC) +;// URSTEN: User Reset Enable +;// Enables NRST Pin to generate Reset +;// ERSTL: External Reset Length <0-15> +;// External Reset Time in 2^(ERSTL+1) Slow Clock Cycles +;// +;*/ +RSTC_SETUP EQU 1 +RSTC_MR_Val EQU 0xA5000401 + + +; Embedded Flash Controller (EFC) definitions +EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address +EFC0_FMR EQU 0x60 ; EFC0_FMR Offset +EFC1_FMR EQU 0x70 ; EFC1_FMR Offset + +;// Embedded Flash Controller 0 (EFC0) +;// FMCN: Flash Microsecond Cycle Number <0-255> +;// Number of Master Clock Cycles in 1us +;// FWS: Flash Wait State +;// <0=> Read: 1 cycle / Write: 2 cycles +;// <1=> Read: 2 cycle / Write: 3 cycles +;// <2=> Read: 3 cycle / Write: 4 cycles +;// <3=> Read: 4 cycle / Write: 4 cycles +;// +EFC0_SETUP EQU 1 +EFC0_FMR_Val EQU 0x00320100 + +;// Embedded Flash Controller 1 (EFC1) +;// FMCN: Flash Microsecond Cycle Number <0-255> +;// Number of Master Clock Cycles in 1us +;// FWS: Flash Wait State +;// <0=> Read: 1 cycle / Write: 2 cycles +;// <1=> Read: 2 cycle / Write: 3 cycles +;// <2=> Read: 3 cycle / Write: 4 cycles +;// <3=> Read: 4 cycle / Write: 4 cycles +;// +EFC1_SETUP EQU 0 +EFC1_FMR_Val EQU 0x00320100 + + +; Watchdog Timer (WDT) definitions +WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address +WDT_MR EQU 0x04 ; WDT_MR Offset + +;// Watchdog Timer (WDT) +;// WDV: Watchdog Counter Value <0-4095> +;// WDD: Watchdog Delta Value <0-4095> +;// WDFIEN: Watchdog Fault Interrupt Enable +;// WDRSTEN: Watchdog Reset Enable +;// WDRPROC: Watchdog Reset Processor +;// WDDBGHLT: Watchdog Debug Halt +;// WDIDLEHLT: Watchdog Idle Halt +;// WDDIS: Watchdog Disable +;// +WDT_SETUP EQU 1 +WDT_MR_Val EQU 0x00008000 + + +; Power Mangement Controller (PMC) definitions +PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address +PMC_MOR EQU 0x20 ; PMC_MOR Offset +PMC_MCFR EQU 0x24 ; PMC_MCFR Offset +PMC_PLLR EQU 0x2C ; PMC_PLLR Offset +PMC_MCKR EQU 0x30 ; PMC_MCKR Offset +PMC_SR EQU 0x68 ; PMC_SR Offset +PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable +PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass +PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time +PMC_DIV EQU (0xFF<<0) ; PLL Divider +PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter +PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range +PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier +PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider +PMC_CSS EQU (3<<0) ; Clock Source Selection +PMC_PRES EQU (7<<2) ; Prescaler Selection +PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable +PMC_LOCK EQU (1<<2) ; PLL Lock Status +PMC_MCKRDY EQU (1<<3) ; Master Clock Status + +;// Power Mangement Controller (PMC) +;// Main Oscillator +;// MOSCEN: Main Oscillator Enable +;// OSCBYPASS: Oscillator Bypass +;// OSCCOUNT: Main Oscillator Startup Time <0-255> +;// +;// Phase Locked Loop (PLL) +;// DIV: PLL Divider <0-255> +;// MUL: PLL Multiplier <0-2047> +;// PLL Output is multiplied by MUL+1 +;// OUT: PLL Clock Frequency Range +;// <0=> 80..160MHz <1=> Reserved +;// <2=> 150..220MHz <3=> Reserved +;// PLLCOUNT: PLL Lock Counter <0-63> +;// USBDIV: USB Clock Divider +;// <0=> None <1=> 2 <2=> 4 <3=> Reserved +;// +;// CSS: Clock Source Selection +;// <0=> Slow Clock +;// <1=> Main Clock +;// <2=> Reserved +;// <3=> PLL Clock +;// PRES: Prescaler +;// <0=> None +;// <1=> Clock / 2 <2=> Clock / 4 +;// <3=> Clock / 8 <4=> Clock / 16 +;// <5=> Clock / 32 <6=> Clock / 64 +;// <7=> Reserved +;// +PMC_SETUP EQU 1 +PMC_MOR_Val EQU 0x00000601 +PMC_PLLR_Val EQU 0x00191C05 +PMC_MCKR_Val EQU 0x00000007 + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + +Vectors LDR PC,Reset_Addr + LDR PC,Undef_Addr + LDR PC,SWI_Addr + LDR PC,PAbt_Addr + LDR PC,DAbt_Addr + NOP ; Reserved Vector + LDR PC,IRQ_Addr + LDR PC,FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B Abort_Handler +DAbt_Handler B Abort_Handler +FIQ_Handler B FIQ_Handler + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; Setup RSTC + IF RSTC_SETUP != 0 + LDR R0, =RSTC_BASE + LDR R1, =RSTC_MR_Val + STR R1, [R0, #RSTC_MR] + ENDIF + + +; Setup EFC0 + IF EFC0_SETUP != 0 + LDR R0, =EFC_BASE + LDR R1, =EFC0_FMR_Val + STR R1, [R0, #EFC0_FMR] + ENDIF + +; Setup EFC1 + IF EFC1_SETUP != 0 + LDR R0, =EFC_BASE + LDR R1, =EFC1_FMR_Val + STR R1, [R0, #EFC1_FMR] + ENDIF + +; Setup WDT + IF WDT_SETUP != 0 + LDR R0, =WDT_BASE + LDR R1, =WDT_MR_Val + STR R1, [R0, #WDT_MR] + ENDIF + + +; Setup PMC + IF PMC_SETUP != 0 + LDR R0, =PMC_BASE + +; Setup Main Oscillator + LDR R1, =PMC_MOR_Val + STR R1, [R0, #PMC_MOR] + +; Wait until Main Oscillator is stablilized + IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0 +MOSCS_Loop LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MOSCS + BEQ MOSCS_Loop + ENDIF + +; Setup the PLL + IF (PMC_PLLR_Val:AND:PMC_MUL) != 0 + LDR R1, =PMC_PLLR_Val + STR R1, [R0, #PMC_PLLR] + +; Wait until PLL is stabilized +PLL_Loop LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_LOCK + BEQ PLL_Loop + ENDIF + +; Select Clock + IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected + LDR R1, =PMC_MCKR_Val + AND R1, #PMC_CSS + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy1 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy1 + LDR R1, =PMC_MCKR_Val + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy2 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy2 + ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected + LDR R1, =PMC_MCKR_Val + AND R1, #PMC_PRES + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy1 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy1 + LDR R1, =PMC_MCKR_Val + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy2 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy2 + ENDIF ; Select Clock + ENDIF ; PMC_SETUP + + +; Copy Exception Vectors to Internal RAM + + IF :DEF:RAM_INTVEC + ADR R8, Vectors ; Source + LDR R9, =RAM_BASE ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + ENDIF + + +; Remap on-chip RAM to address 0 + +MC_BASE EQU 0xFFFFFF00 ; MC Base Address +MC_RCR EQU 0x00 ; MC_RCR Offset + + IF :DEF:REMAP + LDR R0, =MC_BASE + MOV R1, #1 + STR R1, [R0, #MC_RCR] ; Remap + ENDIF + + +; Setup Stack for each mode + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ;SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ;SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ;SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ;SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ; SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; MSR CPSR_c, #Mode_USR + IF :DEF:__MICROLIB + + EXPORT __initial_sp + + ELSE + + ; No usr mode stack here. + ;MOV SP, R0 + ;SUB SL, SP, #USR_Stack_Size + + ENDIF + + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + IMPORT rt_hw_trap_abort + IMPORT rt_interrupt_nest + +Abort_Handler PROC + EXPORT Abort_Handler + stmfd sp!, {r0-r12,lr} + LDR r0, =rt_interrupt_nest + LDR r1, [r0] + CMP r1, #0 +DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system. + bl rt_interrupt_enter + bl rt_hw_trap_abort + bl rt_interrupt_leave + b SWITCH + ENDP + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return +SWITCH LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + IRQ_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + END diff --git a/libcpu/arm/AT91SAM7X/trap.c b/libcpu/arm/AT91SAM7X/trap.c index 8bc0559d23ffd8ddd12478a08b2cdcb08824fef6..2e137fc009e3a045275ee8d55e3d055d8266c64a 100644 --- a/libcpu/arm/AT91SAM7X/trap.c +++ b/libcpu/arm/AT91SAM7X/trap.c @@ -36,12 +36,12 @@ void rt_hw_trap_fiq() { rt_kprintf("fast interrupt request\n"); } - + extern struct rt_thread* rt_current_thread; void rt_hw_trap_abort() -{ - rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); - rt_thread_suspend(rt_current_thread); +{ + rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); + rt_thread_suspend(rt_current_thread); rt_schedule(); } diff --git a/libcpu/arm/at91sam926x/cpu.c b/libcpu/arm/at91sam926x/cpu.c index fff3e59b34b9d29f3e11ae2c170f75996d0e3367..abda8deb295841eea14c3efccbd5784ada1794ff 100755 --- a/libcpu/arm/at91sam926x/cpu.c +++ b/libcpu/arm/at91sam926x/cpu.c @@ -1,193 +1,193 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety modified from mini2440 - */ - -#include -#include -#include "at91sam926x.h" - -/** - * @addtogroup AT91SAM926X - */ -/*@{*/ - -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) - -#ifdef __GNUC__ -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} -#endif - -#ifdef __CC_ARM -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm - { - mrc p15, 0, i, c1, c0, 0 - } - - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} -#endif - -/** - * enable I-Cache - * - */ -void rt_hw_cpu_icache_enable() -{ - cache_enable(ICACHE_MASK); -} - -/** - * disable I-Cache - * - */ -void rt_hw_cpu_icache_disable() -{ - cache_disable(ICACHE_MASK); -} - -/** - * return the status of I-Cache - * - */ -rt_base_t rt_hw_cpu_icache_status() -{ - return (cp15_rd() & ICACHE_MASK); -} - -/** - * enable D-Cache - * - */ -void rt_hw_cpu_dcache_enable() -{ - cache_enable(DCACHE_MASK); -} - -/** - * disable D-Cache - * - */ -void rt_hw_cpu_dcache_disable() -{ - cache_disable(DCACHE_MASK); -} - -/** - * return the status of D-Cache - * - */ -rt_base_t rt_hw_cpu_dcache_status() -{ - return (cp15_rd() & DCACHE_MASK); -} - -static void at91sam9260_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - -static void at91sam9260_poweroff(void) -{ - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); -} - -/** - * reset cpu by dog's time-out - * - */ -void rt_hw_cpu_reset() -{ - - rt_kprintf("Restarting system...\n"); - at91sam9260_reset(); - - while(1); /* loop forever and wait for reset to happen */ - - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -void rt_hw_cpu_shutdown() -{ - rt_uint32_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - at91sam9260_poweroff(); - while (level) - { - RT_ASSERT(0); - } -} - -/*@}*/ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety modified from mini2440 + */ + +#include +#include +#include "at91sam926x.h" + +/** + * @addtogroup AT91SAM926X + */ +/*@{*/ + +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) + +#ifdef __GNUC__ +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} +#endif + +#ifdef __CC_ARM +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + __asm + { + mrc p15, 0, i, c1, c0, 0 + } + + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} +#endif + +/** + * enable I-Cache + * + */ +void rt_hw_cpu_icache_enable() +{ + cache_enable(ICACHE_MASK); +} + +/** + * disable I-Cache + * + */ +void rt_hw_cpu_icache_disable() +{ + cache_disable(ICACHE_MASK); +} + +/** + * return the status of I-Cache + * + */ +rt_base_t rt_hw_cpu_icache_status() +{ + return (cp15_rd() & ICACHE_MASK); +} + +/** + * enable D-Cache + * + */ +void rt_hw_cpu_dcache_enable() +{ + cache_enable(DCACHE_MASK); +} + +/** + * disable D-Cache + * + */ +void rt_hw_cpu_dcache_disable() +{ + cache_disable(DCACHE_MASK); +} + +/** + * return the status of D-Cache + * + */ +rt_base_t rt_hw_cpu_dcache_status() +{ + return (cp15_rd() & DCACHE_MASK); +} + +static void at91sam9260_reset(void) +{ + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); +} + +static void at91sam9260_poweroff(void) +{ + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); +} + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + + rt_kprintf("Restarting system...\n"); + at91sam9260_reset(); + + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + at91sam9260_poweroff(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/libcpu/arm/at91sam926x/mmu.c b/libcpu/arm/at91sam926x/mmu.c index 59ae7824d600957810b6af3b2a77249ef81812b7..32c903eaa25fed6634117aa9a1cc741ecba29892 100755 --- a/libcpu/arm/at91sam926x/mmu.c +++ b/libcpu/arm/at91sam926x/mmu.c @@ -1,395 +1,395 @@ -/* - * File : mmu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety modified from mini2440 - */ - -#include -#include "at91sam926x.h" - -#define _MMUTT_STARTADDRESS 0x33FF0000 - -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) - -#ifdef __GNUC__ -void mmu_setttbase(register rt_uint32_t i) -{ - asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); -} - -void mmu_set_domain(register rt_uint32_t i) -{ - asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); -} - -void mmu_enable() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= 0x1; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~0x1; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_icache() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 12); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_dcache() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 2); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_icache() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 12); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_dcache() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 2); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 1); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 1); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_clean_invalidated_cache_index(int index) -{ - asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); -} - -void mmu_invalidate_tlb() -{ - asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); -} - -void mmu_invalidate_icache() -{ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); -} -#endif - -#ifdef __CC_ARM -void mmu_setttbase(rt_uint32_t i) -{ - __asm - { - mcr p15, 0, i, c2, c0, 0 - } -} - -void mmu_set_domain(rt_uint32_t i) -{ - __asm - { - mcr p15,0, i, c3, c0, 0 - } -} - -void mmu_enable() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_icache() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_dcache() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_icache() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_dcache() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_clean_invalidated_cache_index(int index) -{ - __asm - { - mcr p15, 0, index, c7, c14, 2 - } -} - -void mmu_invalidate_tlb() -{ - register rt_uint32_t value; - - value = 0; - __asm - { - mcr p15, 0, value, c8, c7, 0 - } -} - -void mmu_invalidate_icache() -{ - register rt_uint32_t value; - - value = 0; - - __asm - { - mcr p15, 0, value, c7, c5, 0 - } -} -#endif - -void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) -{ - volatile rt_uint32_t *pTT; - volatile int i,nSec; - pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20); - nSec=(vaddrEnd>>20)-(vaddrStart>>20); - for(i=0;i<=nSec;i++) - { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; - } -} - -void rt_hw_mmu_init(void) -{ -#if 0 - int i,j; - //========================== IMPORTANT NOTE ========================= - //The current stack and code area can't be re-mapped in this routine. - //If you want memory map mapped freely, your own sophiscated mmu - //initialization code is needed. - //=================================================================== - - mmu_disable_dcache(); - mmu_disable_icache(); - - //If write-back is used,the DCache should be cleared. - for(i=0;i<64;i++) - for(j=0;j<8;j++) - mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); - - mmu_invalidate_icache(); - - //To complete mmu_Init() fast, Icache may be turned on here. - mmu_enable_icache(); - - mmu_disable(); - mmu_invalidate_tlb(); - - //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); - mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 - mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 - mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 - mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 - mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 - mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 - //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 - mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 - mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 - //30f00000->30100000, 31000000->30200000 - mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 - mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 - - mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 - mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 - - mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR - mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR - mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR - mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used - mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR - - mmu_setttbase(_MMUTT_STARTADDRESS); - - /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ - mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); - - mmu_enable_alignfault(); - - mmu_enable(); - - /* ICache enable */ - mmu_enable_icache(); - /* DCache should be turned on after mmu is turned on. */ - mmu_enable_dcache(); -#endif -} - +/* + * File : mmu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety modified from mini2440 + */ + +#include +#include "at91sam926x.h" + +#define _MMUTT_STARTADDRESS 0x33FF0000 + +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) + +#ifdef __GNUC__ +void mmu_setttbase(register rt_uint32_t i) +{ + asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); +} + +void mmu_set_domain(register rt_uint32_t i) +{ + asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); +} + +void mmu_enable() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= 0x1; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~0x1; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_icache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 12); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_dcache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 2); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_icache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 12); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_dcache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 2); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 1); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 1); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_clean_invalidated_cache_index(int index) +{ + asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); +} + +void mmu_invalidate_tlb() +{ + asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); +} + +void mmu_invalidate_icache() +{ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); +} +#endif + +#ifdef __CC_ARM +void mmu_setttbase(rt_uint32_t i) +{ + __asm + { + mcr p15, 0, i, c2, c0, 0 + } +} + +void mmu_set_domain(rt_uint32_t i) +{ + __asm + { + mcr p15,0, i, c3, c0, 0 + } +} + +void mmu_enable() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_icache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_dcache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_icache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_dcache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_clean_invalidated_cache_index(int index) +{ + __asm + { + mcr p15, 0, index, c7, c14, 2 + } +} + +void mmu_invalidate_tlb() +{ + register rt_uint32_t value; + + value = 0; + __asm + { + mcr p15, 0, value, c8, c7, 0 + } +} + +void mmu_invalidate_icache() +{ + register rt_uint32_t value; + + value = 0; + + __asm + { + mcr p15, 0, value, c7, c5, 0 + } +} +#endif + +void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) +{ + volatile rt_uint32_t *pTT; + volatile int i,nSec; + pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20); + nSec=(vaddrEnd>>20)-(vaddrStart>>20); + for(i=0;i<=nSec;i++) + { + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; + } +} + +void rt_hw_mmu_init(void) +{ +#if 0 + int i,j; + //========================== IMPORTANT NOTE ========================= + //The current stack and code area can't be re-mapped in this routine. + //If you want memory map mapped freely, your own sophiscated mmu + //initialization code is needed. + //=================================================================== + + mmu_disable_dcache(); + mmu_disable_icache(); + + //If write-back is used,the DCache should be cleared. + for(i=0;i<64;i++) + for(j=0;j<8;j++) + mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); + + mmu_invalidate_icache(); + + //To complete mmu_Init() fast, Icache may be turned on here. + mmu_enable_icache(); + + mmu_disable(); + mmu_invalidate_tlb(); + + //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); + mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 + mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 + mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 + mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 + mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 + mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 + //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 + mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 + mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 + //30f00000->30100000, 31000000->30200000 + mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 + mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 + + mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 + mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 + + mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR + mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR + mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR + mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used + mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR + + mmu_setttbase(_MMUTT_STARTADDRESS); + + /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ + mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); + + mmu_enable_alignfault(); + + mmu_enable(); + + /* ICache enable */ + mmu_enable_icache(); + /* DCache should be turned on after mmu is turned on. */ + mmu_enable_dcache(); +#endif +} + diff --git a/libcpu/arm/at91sam926x/serial.h b/libcpu/arm/at91sam926x/serial.h index a1c5471403d546e5ed4c783662bd4b62e82b1fd8..67f6d3c6590686e97d219f789568dea4eaf63163 100755 --- a/libcpu/arm/at91sam926x/serial.h +++ b/libcpu/arm/at91sam926x/serial.h @@ -1,76 +1,76 @@ -#ifndef __RT_HW_SERIAL_H__ -#define __RT_HW_SERIAL_H__ - -#include -#include - -#include "at91sam926x.h" - -#define RXRDY 0x01 -#define TXRDY (1 << 1) -#define BPS 115200 /* serial baudrate */ - -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 - -struct serial_int_rx -{ - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; - -struct serial_int_tx -{ - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; -}; - -typedef struct uartport -{ -/* USART register offsets */ - volatile rt_uint32_t USART_CR; - volatile rt_uint32_t USART_MR; - volatile rt_uint32_t USART_IER; - volatile rt_uint32_t USART_IDR; - volatile rt_uint32_t USART_IMR; - volatile rt_uint32_t USART_CSR; - volatile rt_uint32_t USART_RHR; - volatile rt_uint32_t USART_THR; - volatile rt_uint32_t USART_BRGR; - volatile rt_uint32_t USART_RTOR; - volatile rt_uint32_t USART_TTGR; - volatile rt_uint32_t reseverd0[5]; - volatile rt_uint32_t USART_FIDI; - volatile rt_uint32_t USART_NER; - volatile rt_uint32_t USART_XXR; - volatile rt_uint32_t USART_IFR; - volatile rt_uint32_t reserved1[44]; - volatile rt_uint32_t USART_RPR; - volatile rt_uint32_t USART_RCR; - volatile rt_uint32_t USART_TPR; - volatile rt_uint32_t USART_TCR; - volatile rt_uint32_t USART_RNPR; - volatile rt_uint32_t USART_RNCR; - volatile rt_uint32_t USART_TNPR; - volatile rt_uint32_t USART_TNCR; - volatile rt_uint32_t USART_PTCR; - volatile rt_uint32_t USART_PTSR; -}uartport; - - -struct serial_device -{ - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; - - /* tx structure */ - struct serial_int_tx* int_tx; -}; - -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); - -void rt_hw_serial_isr(rt_device_t device); - -#endif +#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include +#include + +#include "at91sam926x.h" + +#define RXRDY 0x01 +#define TXRDY (1 << 1) +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +typedef struct uartport +{ +/* USART register offsets */ + volatile rt_uint32_t USART_CR; + volatile rt_uint32_t USART_MR; + volatile rt_uint32_t USART_IER; + volatile rt_uint32_t USART_IDR; + volatile rt_uint32_t USART_IMR; + volatile rt_uint32_t USART_CSR; + volatile rt_uint32_t USART_RHR; + volatile rt_uint32_t USART_THR; + volatile rt_uint32_t USART_BRGR; + volatile rt_uint32_t USART_RTOR; + volatile rt_uint32_t USART_TTGR; + volatile rt_uint32_t reseverd0[5]; + volatile rt_uint32_t USART_FIDI; + volatile rt_uint32_t USART_NER; + volatile rt_uint32_t USART_XXR; + volatile rt_uint32_t USART_IFR; + volatile rt_uint32_t reserved1[44]; + volatile rt_uint32_t USART_RPR; + volatile rt_uint32_t USART_RCR; + volatile rt_uint32_t USART_TPR; + volatile rt_uint32_t USART_TCR; + volatile rt_uint32_t USART_RNPR; + volatile rt_uint32_t USART_RNCR; + volatile rt_uint32_t USART_TNPR; + volatile rt_uint32_t USART_TNCR; + volatile rt_uint32_t USART_PTCR; + volatile rt_uint32_t USART_PTSR; +}uartport; + + +struct serial_device +{ + uartport* uart_device; + + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); + +void rt_hw_serial_isr(rt_device_t device); + +#endif diff --git a/libcpu/arm/at91sam926x/start_rvds.S b/libcpu/arm/at91sam926x/start_rvds.S index 7fdb08b30a2c8496f2dcc780b9e9014e3d209490..49ad09ea171042ed5914d7fb64b042c7e2f61ba8 100644 --- a/libcpu/arm/at91sam926x/start_rvds.S +++ b/libcpu/arm/at91sam926x/start_rvds.S @@ -1,315 +1,315 @@ -;/* -; * File : start_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE -; * -; * Change Logs: -; * Date Author Notes -; * 2011-08-14 weety first version -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -SVCMODE EQU 0x13 -MODEMASK EQU 0x1f - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -;----------------------- Stack and Heap Definitions ---------------------------- - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 512 -SVC_Stack_Size EQU 4096 -ABT_Stack_Size EQU 512 -FIQ_Stack_Size EQU 1024 -IRQ_Stack_Size EQU 1024 -USR_Stack_Size EQU 512 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -;----------------------- Memory Definitions ------------------------------------ - -AT91_MATRIX_BASE EQU 0xffffee00 -AT91_MATRIX_MRCR EQU (AT91_MATRIX_BASE + 0x100) -AT91_MATRIX_RCB0 EQU 0x00000001 -AT91_MATRIX_RCB1 EQU 0x00000002 -AT91_AIC_BASE EQU 0xfffff000 -AT91_AIC_IDCR EQU 0x124 -AT91_AIC_ICCR EQU 0x128 - -;----------------------- CODE -------------------------------------------------- - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - - EXPORT Entry_Point -Entry_Point -Vectors LDR PC, Reset_Addr - LDR PC, Undef_Addr - LDR PC, SWI_Addr - LDR PC, PAbt_Addr - LDR PC, DAbt_Addr - NOP - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B PAbt_Handler -;DAbt_Handler B DAbt_Handler -FIQ_Handler B FIQ_Handler - -;* -;************************************************************************* -;* -;* Interrupt handling -;* -;************************************************************************* -;* -; DAbt Handler -DAbt_Handler - IMPORT rt_hw_trap_dabt - - sub sp, sp, #72 - stmia sp, {r0 - r12} ;/* Calling r0-r12 */ - add r8, sp, #60 - stmdb r8, {sp, lr} ;/* Calling SP, LR */ - str lr, [r8, #0] ;/* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] ;/* Save CPSR */ - str r0, [r8, #8] ;/* Save OLD_R0 */ - mov r0, sp - - bl rt_hw_trap_dabt - - -;########################################## -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; set the cpu to SVC32 mode----------------------------------------------------- - - MRS R0,CPSR - BIC R0,R0,#MODEMASK - ORR R0,R0,#SVCMODE - MSR CPSR_cxsf,R0 - LDR R1, =AT91_AIC_BASE - LDR R0, =0xffffffff - STR R0, [R1, #AT91_AIC_IDCR] - STR R0, [R1, #AT91_AIC_ICCR] - -; remap internal ram to 0x00000000 address - LDR R0, =AT91_MATRIX_MRCR - LDR R1, =(AT91_MATRIX_RCB0|AT91_MATRIX_RCB1) - STR R1, [R0] - - -; Copy Exception Vectors to Internal RAM --------------------------------------- - - ADR R8, Vectors ; Source - LDR R9, =0x00 ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - - -; Setup Stack for each mode ---------------------------------------------------- - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; MSR CPSR_c, #Mode_USR - MOV SP, R0 - SUB SL, SP, #USR_Stack_Size - -; Enter the C code ------------------------------------------------------------- - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - - END - +;/* +; * File : start_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2011-08-14 weety first version +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +SVCMODE EQU 0x13 +MODEMASK EQU 0x1f + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +;----------------------- Stack and Heap Definitions ---------------------------- + +;// Stack Configuration (Stack Sizes in Bytes) +;// Undefined Mode <0x0-0xFFFFFFFF:8> +;// Supervisor Mode <0x0-0xFFFFFFFF:8> +;// Abort Mode <0x0-0xFFFFFFFF:8> +;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// Interrupt Mode <0x0-0xFFFFFFFF:8> +;// User/System Mode <0x0-0xFFFFFFFF:8> +;// + +UND_Stack_Size EQU 512 +SVC_Stack_Size EQU 4096 +ABT_Stack_Size EQU 512 +FIQ_Stack_Size EQU 1024 +IRQ_Stack_Size EQU 1024 +USR_Stack_Size EQU 512 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size +Stack_Top + + +;// Heap Configuration +;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +;----------------------- Memory Definitions ------------------------------------ + +AT91_MATRIX_BASE EQU 0xffffee00 +AT91_MATRIX_MRCR EQU (AT91_MATRIX_BASE + 0x100) +AT91_MATRIX_RCB0 EQU 0x00000001 +AT91_MATRIX_RCB1 EQU 0x00000002 +AT91_AIC_BASE EQU 0xfffff000 +AT91_AIC_IDCR EQU 0x124 +AT91_AIC_ICCR EQU 0x128 + +;----------------------- CODE -------------------------------------------------- + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + + EXPORT Entry_Point +Entry_Point +Vectors LDR PC, Reset_Addr + LDR PC, Undef_Addr + LDR PC, SWI_Addr + LDR PC, PAbt_Addr + LDR PC, DAbt_Addr + NOP + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B PAbt_Handler +;DAbt_Handler B DAbt_Handler +FIQ_Handler B FIQ_Handler + +;* +;************************************************************************* +;* +;* Interrupt handling +;* +;************************************************************************* +;* +; DAbt Handler +DAbt_Handler + IMPORT rt_hw_trap_dabt + + sub sp, sp, #72 + stmia sp, {r0 - r12} ;/* Calling r0-r12 */ + add r8, sp, #60 + stmdb r8, {sp, lr} ;/* Calling SP, LR */ + str lr, [r8, #0] ;/* Save calling PC */ + mrs r6, spsr + str r6, [r8, #4] ;/* Save CPSR */ + str r0, [r8, #8] ;/* Save OLD_R0 */ + mov r0, sp + + bl rt_hw_trap_dabt + + +;########################################## +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; set the cpu to SVC32 mode----------------------------------------------------- + + MRS R0,CPSR + BIC R0,R0,#MODEMASK + ORR R0,R0,#SVCMODE + MSR CPSR_cxsf,R0 + LDR R1, =AT91_AIC_BASE + LDR R0, =0xffffffff + STR R0, [R1, #AT91_AIC_IDCR] + STR R0, [R1, #AT91_AIC_ICCR] + +; remap internal ram to 0x00000000 address + LDR R0, =AT91_MATRIX_MRCR + LDR R1, =(AT91_MATRIX_RCB0|AT91_MATRIX_RCB1) + STR R1, [R0] + + +; Copy Exception Vectors to Internal RAM --------------------------------------- + + ADR R8, Vectors ; Source + LDR R9, =0x00 ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + + +; Setup Stack for each mode ---------------------------------------------------- + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; MSR CPSR_c, #Mode_USR + MOV SP, R0 + SUB SL, SP, #USR_Stack_Size + +; Enter the C code ------------------------------------------------------------- + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + + END + diff --git a/libcpu/arm/at91sam926x/system_clock.c b/libcpu/arm/at91sam926x/system_clock.c index 415e5182584533830fd213e5064096cc98990616..8af42bfccf52af4a8da08e335940d8831fad5a46 100755 --- a/libcpu/arm/at91sam926x/system_clock.c +++ b/libcpu/arm/at91sam926x/system_clock.c @@ -1,294 +1,294 @@ -/* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -#include -#include "at91sam926x.h" - -static rt_list_t clocks; - -struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; -}; - -static struct clk clk32k = { - "clk32k", - AT91_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, -}; - -static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, -}; - -static struct clk plla = { - "plla", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, -}; - -static struct clk mck = { - "mck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, -}; - -static struct clk uhpck = { - "uhpck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, -}; - -static struct clk pllb = { - "pllb", - 0, - &main_clk, - {RT_NULL, RT_NULL}, -}; - -static struct clk udpck = { - "udpck", - 0, - &pllb, - {RT_NULL, RT_NULL}, -}; - -static struct clk *const standard_pmc_clocks[] = { - /* four primary clocks */ - &clk32k, - &main_clk, - &plla, - - /* MCK */ - &mck -}; - -/* clocks cannot be de-registered no refcounting necessary */ -struct clk *clk_get(const char *id) -{ - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } - - return RT_NULL; -} - -rt_uint32_t clk_get_rate(struct clk *clk) -{ - rt_uint32_t flags; - rt_uint32_t rate; - - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; -} - -static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) -{ - unsigned mul, div; - - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; - - return freq; -} - -static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) -{ - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - - /* PLL output max 240 MHz (or 180 MHz per errata) */ - if (out_freq > 240000000) - goto fail; - - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; - - /* - * PLL input between 1MHz and 32MHz per spec, but lower - * frequences seem necessary in some cases so allow 100K. - * Warning: some newer products need 2MHz min. - */ - input = main_freq / i; - if (input < 100000) - continue; - if (input > 32000000) - continue; - - mul1 = out_freq / input; - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; - - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; -fail: - return 0; -} - -static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) -{ - if (pll == &pllb && (reg & AT91_PMC_USB96M)) - return freq / 2; - else - return freq; -} - - -/* PLLB generated USB full speed clock init */ -static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) -{ - rt_uint32_t at91_pllb_usb_init; - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - uhpck.parent = &pllb; - - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - - at91_sys_write(AT91_CKGR_PLLBR, 0); - - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); -} - -static struct clk *at91_css_to_clk(unsigned long css) -{ - switch (css) { - case AT91_PMC_CSS_SLOW: - return &clk32k; - case AT91_PMC_CSS_MAIN: - return &main_clk; - case AT91_PMC_CSS_PLLA: - return &plla; - case AT91_PMC_CSS_PLLB: - return &pllb; - } - - return RT_NULL; -} - -#define false 0 -#define true 1 -int at91_clock_init(rt_uint32_t main_clock) -{ - unsigned tmp, freq, mckr; - int i; - int pll_overclock = false; - - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; - - /* report if PLLA is more than mildly overclocked */ - plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if (plla.rate_hz > 209000000) - pll_overclock = true; - if (pll_overclock) - ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - - at91_pllb_usbfs_clock_init(main_clock); - - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = at91_sys_read(AT91_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - - mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ - - /* Register the PMC's standard clocks */ - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - - rt_list_insert_after(&clocks, &pllb.node); - rt_list_insert_after(&clocks, &uhpck.node); - rt_list_insert_after(&clocks, &udpck.node); - - /* MCK and CPU clock are "always on" */ - //clk_enable(&mck); - - /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - freq / 1000000, (unsigned) mck.rate_hz / 1000000, - (unsigned) main_clock / 1000000, - ((unsigned) main_clock % 1000000) / 1000);*///cause blocked - - return 0; -} - -/** - * @brief System Clock Configuration - */ -void rt_hw_clock_init(void) -{ - at91_clock_init(18432000); -} - +/* + * File : clock.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety first version + */ + +#include +#include "at91sam926x.h" + +static rt_list_t clocks; + +struct clk { + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; +}; + +static struct clk clk32k = { + "clk32k", + AT91_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, +}; + +static struct clk main_clk = { + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, +}; + +static struct clk plla = { + "plla", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, +}; + +static struct clk mck = { + "mck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, +}; + +static struct clk uhpck = { + "uhpck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, +}; + +static struct clk pllb = { + "pllb", + 0, + &main_clk, + {RT_NULL, RT_NULL}, +}; + +static struct clk udpck = { + "udpck", + 0, + &pllb, + {RT_NULL, RT_NULL}, +}; + +static struct clk *const standard_pmc_clocks[] = { + /* four primary clocks */ + &clk32k, + &main_clk, + &plla, + + /* MCK */ + &mck +}; + +/* clocks cannot be de-registered no refcounting necessary */ +struct clk *clk_get(const char *id) +{ + struct clk *clk; + rt_list_t *list; + + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; +} + +rt_uint32_t clk_get_rate(struct clk *clk) +{ + rt_uint32_t flags; + rt_uint32_t rate; + + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; +} + +static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) +{ + unsigned mul, div; + + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; + + return freq; +} + +static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) +{ + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; + + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; + + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; + + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; + + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; +fail: + return 0; +} + +static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) +{ + if (pll == &pllb && (reg & AT91_PMC_USB96M)) + return freq / 2; + else + return freq; +} + + +/* PLLB generated USB full speed clock init */ +static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) +{ + rt_uint32_t at91_pllb_usb_init; + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + uhpck.parent = &pllb; + + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); + + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); +} + +static struct clk *at91_css_to_clk(unsigned long css) +{ + switch (css) { + case AT91_PMC_CSS_SLOW: + return &clk32k; + case AT91_PMC_CSS_MAIN: + return &main_clk; + case AT91_PMC_CSS_PLLA: + return &plla; + case AT91_PMC_CSS_PLLB: + return &pllb; + } + + return RT_NULL; +} + +#define false 0 +#define true 1 +int at91_clock_init(rt_uint32_t main_clock) +{ + unsigned tmp, freq, mckr; + int i; + int pll_overclock = false; + + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; + + /* report if PLLA is more than mildly overclocked */ + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + if (plla.rate_hz > 209000000) + pll_overclock = true; + if (pll_overclock) + ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + + at91_pllb_usbfs_clock_init(main_clock); + + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ + + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + + /* Register the PMC's standard clocks */ + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + + rt_list_insert_after(&clocks, &pllb.node); + rt_list_insert_after(&clocks, &uhpck.node); + rt_list_insert_after(&clocks, &udpck.node); + + /* MCK and CPU clock are "always on" */ + //clk_enable(&mck); + + /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + freq / 1000000, (unsigned) mck.rate_hz / 1000000, + (unsigned) main_clock / 1000000, + ((unsigned) main_clock % 1000000) / 1000);*///cause blocked + + return 0; +} + +/** + * @brief System Clock Configuration + */ +void rt_hw_clock_init(void) +{ + at91_clock_init(18432000); +} + diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c index 764c0f5e1b728ac2640a57d6fef7af68f79de5bf..a9f9f63bf82150f8c5ca8ffefbfe5b0cd43036a6 100644 --- a/libcpu/arm/common/backtrace.c +++ b/libcpu/arm/common/backtrace.c @@ -1,67 +1,67 @@ -/* - * File : backtrace.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version from QiuYi implementation - */ - -#include - -#ifdef __GNUC__ -/* --->High Address,Stack Top -PC<-----| -LR | -IP | -FP | -...... | -PC<-| | -LR | | -IP | | -FP---|-- | -...... | -PC | -LR | -IP | -FP--- --->Low Address,Stack Bottom -*/ -void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) -{ - rt_uint32_t i, pc, func_entry; - - pc = *fp; - rt_kprintf("[0x%x]\n", pc-0xC); - - for(i=0; i<10; i++) - { - fp = (rt_uint32_t *)*(fp - 3); - pc = *fp ; - - func_entry = pc - 0xC; - - if(func_entry <= 0x30000000) break; - - if((func_entry == thread_entry)) - { - rt_kprintf("EntryPoint:0x%x\n", func_entry); - - break; - } - - rt_kprintf("[0x%x]\n", func_entry); - } -} -#else -void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) -{ - /* old compiler implementation */ -} -#endif +/* + * File : backtrace.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-07-29 Bernard first version from QiuYi implementation + */ + +#include + +#ifdef __GNUC__ +/* +-->High Address,Stack Top +PC<-----| +LR | +IP | +FP | +...... | +PC<-| | +LR | | +IP | | +FP---|-- | +...... | +PC | +LR | +IP | +FP--- +-->Low Address,Stack Bottom +*/ +void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) +{ + rt_uint32_t i, pc, func_entry; + + pc = *fp; + rt_kprintf("[0x%x]\n", pc-0xC); + + for(i=0; i<10; i++) + { + fp = (rt_uint32_t *)*(fp - 3); + pc = *fp ; + + func_entry = pc - 0xC; + + if(func_entry <= 0x30000000) break; + + if((func_entry == thread_entry)) + { + rt_kprintf("EntryPoint:0x%x\n", func_entry); + + break; + } + + rt_kprintf("[0x%x]\n", func_entry); + } +} +#else +void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) +{ + /* old compiler implementation */ +} +#endif diff --git a/libcpu/arm/common/showmem.c b/libcpu/arm/common/showmem.c index c171a9bcd75b9206d3fa2949ddb021d5cccd7b3f..38f037f83d622a6d2472c45ab7520a26f41f5a18 100644 --- a/libcpu/arm/common/showmem.c +++ b/libcpu/arm/common/showmem.c @@ -1,42 +1,42 @@ -/* - * File : showmem.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version from QiuYi implementation - */ - -#include - -void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) -{ - int i = 0, j =0; - - RT_ASSERT(addr); - - addr = addr & ~0xF; - size = 4*((size + 3)/4); - - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); - - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - - addr += 4; - i++; - } - - rt_kprintf("\n"); - } - - return; -} +/* + * File : showmem.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-07-29 Bernard first version from QiuYi implementation + */ + +#include + +void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) +{ + int i = 0, j =0; + + RT_ASSERT(addr); + + addr = addr & ~0xF; + size = 4*((size + 3)/4); + + while(i < size) + { + rt_kprintf("0x%08x: ", addr ); + + for(j=0; j<4; j++) + { + rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); + + addr += 4; + i++; + } + + rt_kprintf("\n"); + } + + return; +} diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S index 500e46d065c872a7c0c986f733eaf02edce107c1..9b8a7dddb12e56093bb23e7186d011506fa5018c 100644 --- a/libcpu/arm/cortex-m0/context_iar.S +++ b/libcpu/arm/cortex-m0/context_iar.S @@ -1,201 +1,201 @@ -;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009, RT-Thread Development Team -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE -; * -; * Change Logs: -; * Date Author Notes -; * 2010-01-25 Bernard first version -; * 2012-06-01 aozima set pendsv priority to 0xFF. -; * 2012-08-17 aozima fixed bug: store r8 - r11. -; */ - -;/** -; * @addtogroup CORTEX-M0 -; */ -;/*@{*/ - -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ - EXPORT rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS r0, PRIMASK - CPSID I - BX LR - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ - EXPORT rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR PRIMASK, r0 - BX LR - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ - EXPORT rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOVS r3, #0x1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - -; r0 --> swith from thread stack -; r1 --> swith to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack - EXPORT PendSV_Handler -PendSV_Handler: - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #0x00 - BEQ pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOVS r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CMP r1, #0x00 - BEQ swtich_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - - SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - - STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack - - MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} - MOV r5, r9 - MOV r6, r10 - MOV r7, r11 - STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack - -swtich_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack - PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} - - LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} - MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} - MOV r9, r5 - MOV r10, r6 - MOV r11, r7 - - POP {r4 - r7} ; pop {r4 - r7} from MSP - - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - MOVS r0, #0x04 - RSBS r0, r0, #0x00 - BX r0 - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ - EXPORT rt_hw_context_switch_to -rt_hw_context_switch_to: - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOVS r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOVS r0, #1 - STR r0, [r1] - - ; set the PendSV exception priority - LDR r0, =NVIC_SHPR3 - LDR r1, =NVIC_PENDSV_PRI - LDR r2, [r0,#0x00] ; read - ORRS r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - NOP - - ; enable interrupts at processor level - CPSIE I - - ; never reach here! - -; compatible with old version - EXPORT rt_hw_interrupt_thread_switch -rt_hw_interrupt_thread_switch: - BX lr - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler: - - ; get current context - MRS r0, psp ; get fault thread stack pointer - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {pc} - - END +;/* +; * File : context_iar.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2010-01-25 Bernard first version +; * 2012-06-01 aozima set pendsv priority to 0xFF. +; * 2012-08-17 aozima fixed bug: store r8 - r11. +; */ + +;/** +; * @addtogroup CORTEX-M0 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOVS r3, #0x1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + EXPORT PendSV_Handler +PendSV_Handler: + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #0x00 + BEQ pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOVS r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CMP r1, #0x00 + BEQ swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + + STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack + + MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 + STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack + PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} + + LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} + MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} + MOV r9, r5 + MOV r10, r6 + MOV r11, r7 + + POP {r4 - r7} ; pop {r4 - r7} from MSP + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + MOVS r0, #0x04 + RSBS r0, r0, #0x00 + BX r0 + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOVS r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOVS r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SHPR3 + LDR r1, =NVIC_PENDSV_PRI + LDR r2, [r0,#0x00] ; read + ORRS r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + NOP + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + +; compatible with old version + EXPORT rt_hw_interrupt_thread_switch +rt_hw_interrupt_thread_switch: + BX lr + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler: + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {pc} + + END diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S index 29bef74684c94b45cf4e4012ea64095a7c2c3d2c..1194d8f4aeacbef618b432e375f7f0c5eb21760d 100644 --- a/libcpu/arm/cortex-m0/context_rvds.S +++ b/libcpu/arm/cortex-m0/context_rvds.S @@ -1,210 +1,210 @@ -;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009, RT-Thread Development Team -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE -; * -; * Change Logs: -; * Date Author Notes -; * 2010-01-25 Bernard first version -; * 2012-06-01 aozima set pendsv priority to 0xFF. -; * 2012-08-17 aozima fixed bug: store r8 - r11. -; */ - -;/** -; * @addtogroup CORTEX-M0 -; */ -;/*@{*/ - -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, PRIMASK - CPSID I - BX LR - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR PRIMASK, r0 - BX LR - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch_interrupt -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOVS r3, #0x01 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - ENDP - -; r0 --> swith from thread stack -; r1 --> swith to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack -PendSV_Handler PROC - EXPORT PendSV_Handler - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #0x00 - BEQ pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOVS r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CMP r1, #0x00 - BEQ swtich_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - - SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - - STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack - - MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} - MOV r5, r9 - MOV r6, r10 - MOV r7, r11 - STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack - -swtich_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack - PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} - - LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} - MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} - MOV r9, r5 - MOV r10, r6 - MOV r11, r7 - - POP {r4 - r7} ; pop {r4 - r7} from MSP - - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - MOVS r0, #0x04 - RSBS r0, r0, #0x00 - BX r0 - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOVS r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOVS r0, #1 - STR r0, [r1] - - ; set the PendSV exception priority - LDR r0, =NVIC_SHPR3 - LDR r1, =NVIC_PENDSV_PRI - LDR r2, [r0,#0x00] ; read - ORRS r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - NOP - - ; enable interrupts at processor level - CPSIE I - - ; never reach here! - ENDP - -; compatible with old version -rt_hw_interrupt_thread_switch PROC - EXPORT rt_hw_interrupt_thread_switch - BX lr - ENDP - - IMPORT rt_hw_hard_fault_exception - -HardFault_Handler PROC - EXPORT HardFault_Handler - - ; get current context - MRS r0, psp ; get fault thread stack pointer - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {pc} - ENDP - - END +;/* +; * File : context_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2010-01-25 Bernard first version +; * 2012-06-01 aozima set pendsv priority to 0xFF. +; * 2012-08-17 aozima fixed bug: store r8 - r11. +; */ + +;/** +; * @addtogroup CORTEX-M0 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOVS r3, #0x01 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #0x00 + BEQ pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOVS r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CMP r1, #0x00 + BEQ swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + + STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack + + MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 + STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack + PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} + + LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} + MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} + MOV r9, r5 + MOV r10, r6 + MOV r11, r7 + + POP {r4 - r7} ; pop {r4 - r7} from MSP + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + MOVS r0, #0x04 + RSBS r0, r0, #0x00 + BX r0 + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOVS r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOVS r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SHPR3 + LDR r1, =NVIC_PENDSV_PRI + LDR r2, [r0,#0x00] ; read + ORRS r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + NOP + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + ENDP + + IMPORT rt_hw_hard_fault_exception + +HardFault_Handler PROC + EXPORT HardFault_Handler + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {pc} + ENDP + + END diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S index 6c981bdfb36d461ff30e15081d31c1a6d1c4b8be..c0cf140dafa1dd360be2613fdffb8b38bbd27945 100644 --- a/libcpu/arm/cortex-m3/context_gcc.S +++ b/libcpu/arm/cortex-m3/context_gcc.S @@ -1,186 +1,186 @@ -/* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-10-11 Bernard First version - * 2010-12-29 onelife Modify for EFM32 - * 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S - * 2011-07-12 onelife Add interrupt context check function - */ - - .cpu cortex-m3 - .fpu softvfp - .syntax unified - .thumb - .text - - .equ ICSR, 0xE000ED04 /* interrupt control state register */ - .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ - - .equ SHPR3, 0xE000ED20 /* system priority register (3) */ - .equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */ - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ - .global rt_hw_interrupt_disable - .type rt_hw_interrupt_disable, %function -rt_hw_interrupt_disable: - MRS R0, PRIMASK - CPSID I - BX LR - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ - .global rt_hw_interrupt_enable - .type rt_hw_interrupt_enable, %function -rt_hw_interrupt_enable: - MSR PRIMASK, R0 - BX LR - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * R0 --> from - * R1 --> to - */ - .global rt_hw_context_switch_interrupt - .type rt_hw_context_switch_interrupt, %function - .global rt_hw_context_switch - .type rt_hw_context_switch, %function -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - /* set rt_thread_switch_interrupt_flag to 1 */ - LDR R2, =rt_thread_switch_interrupt_flag - LDR R3, [R2] - CMP R3, #1 - BEQ _reswitch - MOV R3, #1 - STR R3, [R2] - - LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - STR R0, [R2] - -_reswitch: - LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - STR R1, [R2] - - LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */ - LDR R1, =PENDSVSET_BIT - STR R1, [R0] - BX LR - -/* R0 --> swith from thread stack - * R1 --> swith to thread stack - * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack - */ - .global PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - /* disable interrupt to protect context switch */ - MRS R2, PRIMASK - CPSID I - - /* get rt_thread_switch_interrupt_flag */ - LDR R0, =rt_thread_switch_interrupt_flag - LDR R1, [R0] - CBZ R1, pendsv_exit /* pendsv aLReady handled */ - - /* clear rt_thread_switch_interrupt_flag to 0 */ - MOV R1, #0 - STR R1, [R0] - - LDR R0, =rt_interrupt_from_thread - LDR R1, [R0] - CBZ R1, swtich_to_thread /* skip register save at the first time */ - - MRS R1, PSP /* get from thread stack pointer */ - STMFD R1!, {R4 - R11} /* push R4 - R11 register */ - LDR R0, [R0] - STR R1, [R0] /* update from thread stack pointer */ - -swtich_to_thread: - LDR R1, =rt_interrupt_to_thread - LDR R1, [R1] - LDR R1, [R1] /* load thread stack pointer */ - - LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */ - MSR PSP, R1 /* update stack pointer */ - -pendsv_exit: - /* restore interrupt */ - MSR PRIMASK, R2 - - ORR LR, LR, #0x04 - BX LR - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * R0 --> to - */ - .global rt_hw_context_switch_to - .type rt_hw_context_switch_to, %function -rt_hw_context_switch_to: - LDR R1, =rt_interrupt_to_thread - STR R0, [R1] - - /* set from thread to 0 */ - LDR R1, =rt_interrupt_from_thread - MOV R0, #0 - STR R0, [R1] - - /* set interrupt flag to 1 */ - LDR R1, =rt_thread_switch_interrupt_flag - MOV R0, #1 - STR R0, [R1] - - /* set the PendSV exception priority */ - LDR R0, =SHPR3 - LDR R1, =PENDSV_PRI_LOWEST - LDR.W R2, [R0,#0] /* read */ - ORR R1, R1, R2 /* modify */ - STR R1, [R0] /* write-back */ - - LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */ - LDR R1, =PENDSVSET_BIT - STR R1, [R0] - - CPSIE I /* enable interrupts at processor level */ - - /* never reach here! */ - -/* compatible with old version */ - .global rt_hw_interrupt_thread_switch - .type rt_hw_interrupt_thread_switch, %function -rt_hw_interrupt_thread_switch: - BX LR - NOP - - .global HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - /* get current context */ - MRS R0, PSP /* get fault thread stack pointer */ - PUSH {LR} - BL rt_hw_hard_fault_exception - POP {LR} - - ORR LR, LR, #0x04 - BX LR - -/* - * rt_uint32_t rt_hw_interrupt_check(void); - * R0 --> state - */ - .global rt_hw_interrupt_check - .type rt_hw_interrupt_check, %function -rt_hw_interrupt_check: - MRS R0, IPSR - BX LR +/* + * File : context_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-10-11 Bernard First version + * 2010-12-29 onelife Modify for EFM32 + * 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S + * 2011-07-12 onelife Add interrupt context check function + */ + + .cpu cortex-m3 + .fpu softvfp + .syntax unified + .thumb + .text + + .equ ICSR, 0xE000ED04 /* interrupt control state register */ + .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ + + .equ SHPR3, 0xE000ED20 /* system priority register (3) */ + .equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ + .global rt_hw_interrupt_disable + .type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + MRS R0, PRIMASK + CPSID I + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .global rt_hw_interrupt_enable + .type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + MSR PRIMASK, R0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * R0 --> from + * R1 --> to + */ + .global rt_hw_context_switch_interrupt + .type rt_hw_context_switch_interrupt, %function + .global rt_hw_context_switch + .type rt_hw_context_switch, %function +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + /* set rt_thread_switch_interrupt_flag to 1 */ + LDR R2, =rt_thread_switch_interrupt_flag + LDR R3, [R2] + CMP R3, #1 + BEQ _reswitch + MOV R3, #1 + STR R3, [R2] + + LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + STR R0, [R2] + +_reswitch: + LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + STR R1, [R2] + + LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */ + LDR R1, =PENDSVSET_BIT + STR R1, [R0] + BX LR + +/* R0 --> swith from thread stack + * R1 --> swith to thread stack + * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack + */ + .global PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + /* disable interrupt to protect context switch */ + MRS R2, PRIMASK + CPSID I + + /* get rt_thread_switch_interrupt_flag */ + LDR R0, =rt_thread_switch_interrupt_flag + LDR R1, [R0] + CBZ R1, pendsv_exit /* pendsv aLReady handled */ + + /* clear rt_thread_switch_interrupt_flag to 0 */ + MOV R1, #0 + STR R1, [R0] + + LDR R0, =rt_interrupt_from_thread + LDR R1, [R0] + CBZ R1, swtich_to_thread /* skip register save at the first time */ + + MRS R1, PSP /* get from thread stack pointer */ + STMFD R1!, {R4 - R11} /* push R4 - R11 register */ + LDR R0, [R0] + STR R1, [R0] /* update from thread stack pointer */ + +swtich_to_thread: + LDR R1, =rt_interrupt_to_thread + LDR R1, [R1] + LDR R1, [R1] /* load thread stack pointer */ + + LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */ + MSR PSP, R1 /* update stack pointer */ + +pendsv_exit: + /* restore interrupt */ + MSR PRIMASK, R2 + + ORR LR, LR, #0x04 + BX LR + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * R0 --> to + */ + .global rt_hw_context_switch_to + .type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LDR R1, =rt_interrupt_to_thread + STR R0, [R1] + + /* set from thread to 0 */ + LDR R1, =rt_interrupt_from_thread + MOV R0, #0 + STR R0, [R1] + + /* set interrupt flag to 1 */ + LDR R1, =rt_thread_switch_interrupt_flag + MOV R0, #1 + STR R0, [R1] + + /* set the PendSV exception priority */ + LDR R0, =SHPR3 + LDR R1, =PENDSV_PRI_LOWEST + LDR.W R2, [R0,#0] /* read */ + ORR R1, R1, R2 /* modify */ + STR R1, [R0] /* write-back */ + + LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */ + LDR R1, =PENDSVSET_BIT + STR R1, [R0] + + CPSIE I /* enable interrupts at processor level */ + + /* never reach here! */ + +/* compatible with old version */ + .global rt_hw_interrupt_thread_switch + .type rt_hw_interrupt_thread_switch, %function +rt_hw_interrupt_thread_switch: + BX LR + NOP + + .global HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + /* get current context */ + MRS R0, PSP /* get fault thread stack pointer */ + PUSH {LR} + BL rt_hw_hard_fault_exception + POP {LR} + + ORR LR, LR, #0x04 + BX LR + +/* + * rt_uint32_t rt_hw_interrupt_check(void); + * R0 --> state + */ + .global rt_hw_interrupt_check + .type rt_hw_interrupt_check, %function +rt_hw_interrupt_check: + MRS R0, IPSR + BX LR diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S index 51c4967765b7dc6441f9e1d1a7268e58e3793276..7f2e8e67d16432c08235d7fc9f9524aac7ea8a47 100644 --- a/libcpu/arm/cortex-m3/context_rvds.S +++ b/libcpu/arm/cortex-m3/context_rvds.S @@ -1,188 +1,188 @@ -;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009, RT-Thread Development Team -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version -; */ - -;/** -; * @addtogroup CORTEX-M3 -; */ -;/*@{*/ - -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, PRIMASK - CPSID I - BX LR - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR PRIMASK, r0 - BX LR - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch_interrupt -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - ENDP - -; r0 --> swith from thread stack -; r1 --> swith to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack -PendSV_Handler PROC - EXPORT PendSV_Handler - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CBZ r1, pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOV r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CBZ r1, swtich_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - STMFD r1!, {r4 - r11} ; push r4 - r11 register - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - -swtich_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMFD r1!, {r4 - r11} ; pop r4 - r11 register - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - ORR lr, lr, #0x04 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - ; set the PendSV exception priority - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] ; read - ORR r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - ; enable interrupts at processor level - CPSIE I - - ; never reach here! - ENDP - -; compatible with old version -rt_hw_interrupt_thread_switch PROC - EXPORT rt_hw_interrupt_thread_switch - BX lr - NOP - ENDP - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler PROC - - ; get current context - MRS r0, psp ; get fault thread stack pointer - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {lr} - - ORR lr, lr, #0x04 - BX lr - ENDP - - END +;/* +; * File : context_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; */ + +;/** +; * @addtogroup CORTEX-M3 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + STMFD r1!, {r4 - r11} ; push r4 - r11 register + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + NOP + ENDP + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler PROC + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + ENDP + + END diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S index 8f50096d5767a35c2b336c345e66202a5ffbdb2e..97c3f1b44e2e810ea12a92aff0d3e1f5589f4e16 100644 --- a/libcpu/arm/cortex-m4/context_gcc.S +++ b/libcpu/arm/cortex-m4/context_gcc.S @@ -1,188 +1,188 @@ -/* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-10-11 Bernard first version - * 2012-01-01 aozima support context switch load/store FPU register. - */ - -/** - * @addtogroup STM32 - */ -/*@{*/ - -.cpu cortex-m4 -.syntax unified -.thumb -.text - -.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ -.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ -.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ -.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.global rt_hw_interrupt_disable -.type rt_hw_interrupt_disable, %function -rt_hw_interrupt_disable: - MRS r0, PRIMASK - CPSID I - BX LR - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.global rt_hw_interrupt_enable -.type rt_hw_interrupt_enable, %function -rt_hw_interrupt_enable: - MSR PRIMASK, r0 - BX LR - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.global rt_hw_context_switch_interrupt -.type rt_hw_context_switch_interrupt, %function -.global rt_hw_context_switch -.type rt_hw_context_switch, %function - -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - /* set rt_thread_switch_interrupt_flag to 1 */ - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - STR r0, [r2] - -_reswitch: - LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - -/* r0 --> swith from thread stack - * r1 --> swith to thread stack - * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack - */ -.global PendSV_Handler -.type PendSV_Handler, %function -PendSV_Handler: - /* disable interrupt to protect context switch */ - MRS r2, PRIMASK - CPSID I - - /* get rt_thread_switch_interrupt_flag */ - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CBZ r1, pendsv_exit /* pendsv already handled */ - - /* clear rt_thread_switch_interrupt_flag to 0 */ - MOV r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CBZ r1, swtich_to_thread /* skip register save at the first time */ - - MRS r1, psp /* get from thread stack pointer */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - VSTMDB r1!, {d8 - d15} /* push FPU register s16~s31 */ -#endif - - STMFD r1!, {r4 - r11} /* push r4 - r11 register */ - LDR r0, [r0] - STR r1, [r0] /* update from thread stack pointer */ - -swtich_to_thread: - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] /* load thread stack pointer */ - - LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - VLDMIA r1!, {d8 - d15} /* pop FPU register s16~s31 */ -#endif - - MSR psp, r1 /* update stack pointer */ - -pendsv_exit: - /* restore interrupt */ - MSR PRIMASK, r2 - - ORR lr, lr, #0x04 - BX lr - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.global rt_hw_context_switch_to -.type rt_hw_context_switch_to, %function -rt_hw_context_switch_to: - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - /* set from thread to 0 */ - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - /* set interrupt flag to 1 */ - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - /* set the PendSV exception priority */ - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] /* read */ - ORR r1,r1,r2 /* modify */ - STR r1, [r0] /* write-back */ - - LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - CPSIE I /* enable interrupts at processor level */ - - /* never reach here! */ - -/* compatible with old version */ -.global rt_hw_interrupt_thread_switch -.type rt_hw_interrupt_thread_switch, %function -rt_hw_interrupt_thread_switch: - BX lr - NOP - -.global HardFault_Handler -.type HardFault_Handler, %function -HardFault_Handler: - /* get current context */ - MRS r0, psp /* get fault thread stack pointer */ - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {lr} - - ORR lr, lr, #0x04 - BX lr +/* + * File : context_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-10-11 Bernard first version + * 2012-01-01 aozima support context switch load/store FPU register. + */ + +/** + * @addtogroup STM32 + */ +/*@{*/ + +.cpu cortex-m4 +.syntax unified +.thumb +.text + +.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ +.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ +.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ +.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.global rt_hw_interrupt_disable +.type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.global rt_hw_interrupt_enable +.type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.global rt_hw_context_switch_interrupt +.type rt_hw_context_switch_interrupt, %function +.global rt_hw_context_switch +.type rt_hw_context_switch, %function + +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + /* set rt_thread_switch_interrupt_flag to 1 */ + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + STR r0, [r2] + +_reswitch: + LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +/* r0 --> swith from thread stack + * r1 --> swith to thread stack + * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + */ +.global PendSV_Handler +.type PendSV_Handler, %function +PendSV_Handler: + /* disable interrupt to protect context switch */ + MRS r2, PRIMASK + CPSID I + + /* get rt_thread_switch_interrupt_flag */ + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit /* pendsv already handled */ + + /* clear rt_thread_switch_interrupt_flag to 0 */ + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, swtich_to_thread /* skip register save at the first time */ + + MRS r1, psp /* get from thread stack pointer */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + VSTMDB r1!, {d8 - d15} /* push FPU register s16~s31 */ +#endif + + STMFD r1!, {r4 - r11} /* push r4 - r11 register */ + LDR r0, [r0] + STR r1, [r0] /* update from thread stack pointer */ + +swtich_to_thread: + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] /* load thread stack pointer */ + + LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + VLDMIA r1!, {d8 - d15} /* pop FPU register s16~s31 */ +#endif + + MSR psp, r1 /* update stack pointer */ + +pendsv_exit: + /* restore interrupt */ + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.global rt_hw_context_switch_to +.type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + /* set from thread to 0 */ + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + /* set interrupt flag to 1 */ + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + /* set the PendSV exception priority */ + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] /* read */ + ORR r1,r1,r2 /* modify */ + STR r1, [r0] /* write-back */ + + LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + CPSIE I /* enable interrupts at processor level */ + + /* never reach here! */ + +/* compatible with old version */ +.global rt_hw_interrupt_thread_switch +.type rt_hw_interrupt_thread_switch, %function +rt_hw_interrupt_thread_switch: + BX lr + NOP + +.global HardFault_Handler +.type HardFault_Handler, %function +HardFault_Handler: + /* get current context */ + MRS r0, psp /* get fault thread stack pointer */ + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S index 0a28a37a90d4540c562804a17620a09baea3aee9..db3f3704735f71e1ef65180acbde021bdcd20ce2 100644 --- a/libcpu/arm/cortex-m4/context_iar.S +++ b/libcpu/arm/cortex-m4/context_iar.S @@ -1,187 +1,187 @@ -;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009, RT-Thread Development Team -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version -; * 2009-09-27 Bernard add protect when contex switch occurs -; * 2012-01-01 aozima support context switch load/store FPU register. -; */ - -;/** -; * @addtogroup STM32 -; */ -;/*@{*/ - -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ - EXPORT rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS r0, PRIMASK - CPSID I - BX LR - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ - EXPORT rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR PRIMASK, r0 - BX LR - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ - EXPORT rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - -; r0 --> swith from thread stack -; r1 --> swith to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack - EXPORT PendSV_Handler -PendSV_Handler: - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CBZ r1, pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOV r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CBZ r1, swtich_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - -#if defined ( __ARMVFP__ ) - VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31 -#endif - - STMFD r1!, {r4 - r11} ; push r4 - r11 register - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - -swtich_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMFD r1!, {r4 - r11} ; pop r4 - r11 register - -#if defined ( __ARMVFP__ ) - VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31 -#endif - - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - ORR lr, lr, #0x04 - BX lr - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ - EXPORT rt_hw_context_switch_to -rt_hw_context_switch_to: - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - ; set the PendSV exception priority - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] ; read - ORR r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - CPSIE I ; enable interrupts at processor level - - ; never reach here! - -; compatible with old version - EXPORT rt_hw_interrupt_thread_switch -rt_hw_interrupt_thread_switch: - BX lr - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler: - - ; get current context - MRS r0, psp ; get fault thread stack pointer - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {lr} - - ORR lr, lr, #0x04 - BX lr - - END +;/* +; * File : context_iar.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; * 2009-09-27 Bernard add protect when contex switch occurs +; * 2012-01-01 aozima support context switch load/store FPU register. +; */ + +;/** +; * @addtogroup STM32 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + EXPORT PendSV_Handler +PendSV_Handler: + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + +#if defined ( __ARMVFP__ ) + VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31 +#endif + + STMFD r1!, {r4 - r11} ; push r4 - r11 register + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + +#if defined ( __ARMVFP__ ) + VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31 +#endif + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + CPSIE I ; enable interrupts at processor level + + ; never reach here! + +; compatible with old version + EXPORT rt_hw_interrupt_thread_switch +rt_hw_interrupt_thread_switch: + BX lr + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler: + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + + END diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S index 1bc7b1104508ae953482f02a0b3fae65ce5ef5c3..ee72c44d01d4841162c8478e6a05be2da6f2df31 100644 --- a/libcpu/arm/cortex-m4/context_rvds.S +++ b/libcpu/arm/cortex-m4/context_rvds.S @@ -1,199 +1,199 @@ -;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009, RT-Thread Development Team -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version. -; * 2012-01-01 aozima support context switch load/store FPU register. -; */ - -;/** -; * @addtogroup STM32 -; */ -;/*@{*/ - -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, PRIMASK - CPSID I - BX LR - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR PRIMASK, r0 - BX LR - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch_interrupt -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - ENDP - -; r0 --> swith from thread stack -; r1 --> swith to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack -PendSV_Handler PROC - EXPORT PendSV_Handler - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CBZ r1, pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOV r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CBZ r1, swtich_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - - IF {FPU} != "SoftVFP" - VSTMFD r1!, {d8 - d15} ; push FPU register s16~s31 - ENDIF - - STMFD r1!, {r4 - r11} ; push r4 - r11 register - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - -swtich_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMFD r1!, {r4 - r11} ; pop r4 - r11 register - - IF {FPU} != "SoftVFP" - VLDMFD r1!, {d8 - d15} ; pop FPU register s16~s31 - ENDIF - - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - ORR lr, lr, #0x04 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - ; set the PendSV exception priority - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] ; read - ORR r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - ; enable interrupts at processor level - CPSIE I - - ; never reach here! - ENDP - -; compatible with old version -rt_hw_interrupt_thread_switch PROC - EXPORT rt_hw_interrupt_thread_switch - BX lr - NOP - ENDP - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler PROC - - ; get current context - MRS r0, psp ; get fault thread stack pointer - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {lr} - - ORR lr, lr, #0x04 - BX lr - ENDP - - END +;/* +; * File : context_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version. +; * 2012-01-01 aozima support context switch load/store FPU register. +; */ + +;/** +; * @addtogroup STM32 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + IF {FPU} != "SoftVFP" + VSTMFD r1!, {d8 - d15} ; push FPU register s16~s31 + ENDIF + + STMFD r1!, {r4 - r11} ; push r4 - r11 register + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + + IF {FPU} != "SoftVFP" + VLDMFD r1!, {d8 - d15} ; pop FPU register s16~s31 + ENDIF + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + NOP + ENDP + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler PROC + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + ENDP + + END diff --git a/libcpu/arm/lpc214x/context_rvds.S b/libcpu/arm/lpc214x/context_rvds.S index b3a3b5bf8ea9a1c3212f936998a4d8f23cdb8bdd..762b67d42e6fd3e2b8bb43bad3a7ab96d2f2a83d 100644 --- a/libcpu/arm/lpc214x/context_rvds.S +++ b/libcpu/arm/lpc214x/context_rvds.S @@ -24,12 +24,12 @@ Mode_SYS EQU 0x1F I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled -NOINT EQU 0xc0 ; disable interrupt in psr +NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 + AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -38,16 +38,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1 + MSR cpsr_c, r1 BX lr - ENDP + ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 + MSR cpsr_c, r0 BX lr ENDP @@ -77,7 +77,7 @@ _ARM_MODE MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP + ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -93,14 +93,14 @@ rt_hw_context_switch_to PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP + ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread + IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -114,9 +114,9 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] + STR r1, [r2] BX lr - ENDP + ENDP ; /* ; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) diff --git a/libcpu/arm/lpc214x/cpuport.c b/libcpu/arm/lpc214x/cpuport.c index 7986dad54b9224f709dbc73094e32b85f8a87fa3..512ff89f086b1d7fff9949e84666a3cb449121c1 100644 --- a/libcpu/arm/lpc214x/cpuport.c +++ b/libcpu/arm/lpc214x/cpuport.c @@ -1,30 +1,30 @@ -/* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-06-15 aozima the first version for lpc214x - */ - -#include -#include "lpc214x.h" - -#define MAX_HANDLERS 32 -#define SVCMODE 0x13 - -extern rt_uint32_t rt_interrupt_nest; +/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-06-15 aozima the first version for lpc214x + */ + +#include +#include "lpc214x.h" + +#define MAX_HANDLERS 32 +#define SVCMODE 0x13 + +extern rt_uint32_t rt_interrupt_nest; /** * @addtogroup LPC214x */ -/*@{*/ - +/*@{*/ + /** * This function will initialize thread stack * @@ -56,25 +56,25 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, *(--stk) = 0; /* r2 */ *(--stk) = 0; /* r1 */ *(--stk) = (unsigned long)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else + else *(--stk) = SVCMODE; /* arm mode */ /* return task's current stack address */ return (rt_uint8_t *)stk; -} +} -/* exception and interrupt handler table */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; rt_uint32_t rt_thread_switch_interrupt_flag; - + void rt_hw_interrupt_handler(int vector) { rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} +} /** * This function will initialize hardware interrupt @@ -82,21 +82,21 @@ void rt_hw_interrupt_handler(int vector) void rt_hw_interrupt_init() { rt_base_t index; - rt_uint32_t *vect_addr, *vect_ctl; - - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - /* set all to IRQ */ - VICIntSelect = 0; + rt_uint32_t *vect_addr, *vect_ctl; + + /* initialize VIC*/ + VICIntEnClr = 0xffffffff; + VICVectAddr = 0; + /* set all to IRQ */ + VICIntSelect = 0; for (index = 0; index < MAX_HANDLERS; index ++) { - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); - vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); - - *vect_addr = (rt_uint32_t)rt_hw_interrupt_handler; - *vect_ctl = 0xF; + vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); + vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); + + *vect_addr = (rt_uint32_t)rt_hw_interrupt_handler; + *vect_ctl = 0xF; } /* init interrupt nest, and context in thread sp */ @@ -104,26 +104,26 @@ void rt_hw_interrupt_init() rt_interrupt_from_thread = 0; rt_interrupt_to_thread = 0; rt_thread_switch_interrupt_flag = 0; -} +} /** * This function will mask a interrupt. * @param vector the interrupt number */ void rt_hw_interrupt_mask(int vector) -{ - VICIntEnClr = (1 << vector); -} - +{ + VICIntEnClr = (1 << vector); +} + /** * This function will un-mask a interrupt. * @param vector the interrupt number */ void rt_hw_interrupt_umask(int vector) -{ +{ VICIntEnable = (1 << vector); -} - +} + /** * This function will install a interrupt service routine to a interrupt. * @param vector the interrupt number @@ -131,21 +131,21 @@ void rt_hw_interrupt_umask(int vector) * @param old_handler the old interrupt service routine */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) -{ +{ if(vector >= 0 && vector < MAX_HANDLERS) { - /* get VIC address */ - rt_uint32_t* vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (vector << 2)); - rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); - - /* assign IRQ slot and enable this slot */ - *vect_ctl = 0x20 | (vector & 0x1F); - + /* get VIC address */ + rt_uint32_t* vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (vector << 2)); + rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); + + /* assign IRQ slot and enable this slot */ + *vect_ctl = 0x20 | (vector & 0x1F); + if (old_handler != RT_NULL) *old_handler = (rt_isr_handler_t) *vect_addr; if (new_handler != RT_NULL) *vect_addr = (rt_uint32_t) new_handler; } -} - +} + /** * this function will reset CPU * @@ -163,22 +163,22 @@ void rt_hw_cpu_shutdown() rt_kprintf("shutdown...\n"); while (1); -} - +} + void rt_hw_trap_irq() -{ - rt_isr_handler_t isr_func; - - isr_func = (rt_isr_handler_t) VICVectAddr; - isr_func(0); - - /* acknowledge Interrupt */ - // VICVectAddr = 0; +{ + rt_isr_handler_t isr_func; + + isr_func = (rt_isr_handler_t) VICVectAddr; + isr_func(0); + + /* acknowledge Interrupt */ + // VICVectAddr = 0; } void rt_hw_trap_fiq() { rt_kprintf("fast interrupt request\n"); } - + /*@}*/ diff --git a/libcpu/arm/lpc214x/lpc214x.h b/libcpu/arm/lpc214x/lpc214x.h index ddf655a4839f0c229d00e0bd3e6351485b1e78f3..1805bc6c03884d94fcc8d27a3d6d87402b71e673 100644 --- a/libcpu/arm/lpc214x/lpc214x.h +++ b/libcpu/arm/lpc214x/lpc214x.h @@ -1,393 +1,393 @@ -/***********************************************************************/ -/* This file is part of the uVision/ARM development tools */ -/* Copyright KEIL ELEKTRONIK GmbH 2002-2005 */ -/***********************************************************************/ -/* */ -/* LPC214X.H: Header file for Philips LPC2141/42/44/46/48 */ -/* */ -/***********************************************************************/ - -#ifndef __LPC214x_H -#define __LPC214x_H - -/* Vectored Interrupt Controller (VIC) */ -#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000)) -#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004)) -#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008)) -#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C)) -#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010)) -#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014)) -#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018)) -#define VICSoftIntClr (*((volatile unsigned long *) 0xFFFFF01C)) -#define VICProtection (*((volatile unsigned long *) 0xFFFFF020)) -#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030)) -#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034)) -#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100)) -#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104)) -#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108)) -#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C)) -#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110)) -#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114)) -#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118)) -#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C)) -#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120)) -#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124)) -#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128)) -#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C)) -#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130)) -#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134)) -#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138)) -#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C)) -#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200)) -#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204)) -#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208)) -#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C)) -#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210)) -#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214)) -#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218)) -#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C)) -#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220)) -#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224)) -#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228)) -#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C)) -#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230)) -#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234)) -#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238)) -#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C)) - -/* Pin Connect Block */ -#define PINSEL0 (*((volatile unsigned long *) 0xE002C000)) -#define PINSEL1 (*((volatile unsigned long *) 0xE002C004)) -#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) - -/* General Purpose Input/Output (GPIO) */ -#define IOPIN0 (*((volatile unsigned long *) 0xE0028000)) -#define IOSET0 (*((volatile unsigned long *) 0xE0028004)) -#define IODIR0 (*((volatile unsigned long *) 0xE0028008)) -#define IOCLR0 (*((volatile unsigned long *) 0xE002800C)) -#define IOPIN1 (*((volatile unsigned long *) 0xE0028010)) -#define IOSET1 (*((volatile unsigned long *) 0xE0028014)) -#define IODIR1 (*((volatile unsigned long *) 0xE0028018)) -#define IOCLR1 (*((volatile unsigned long *) 0xE002801C)) -#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) -#define IO0SET (*((volatile unsigned long *) 0xE0028004)) -#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) -#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) -#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) -#define IO1SET (*((volatile unsigned long *) 0xE0028014)) -#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) -#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) -#define FIO0DIR (*((volatile unsigned long *) 0x3FFFC000)) -#define FIO0MASK (*((volatile unsigned long *) 0x3FFFC010)) -#define FIO0PIN (*((volatile unsigned long *) 0x3FFFC014)) -#define FIO0SET (*((volatile unsigned long *) 0x3FFFC018)) -#define FIO0CLR (*((volatile unsigned long *) 0x3FFFC01C)) -#define FIO1DIR (*((volatile unsigned long *) 0x3FFFC020)) -#define FIO1MASK (*((volatile unsigned long *) 0x3FFFC030)) -#define FIO1PIN (*((volatile unsigned long *) 0x3FFFC034)) -#define FIO1SET (*((volatile unsigned long *) 0x3FFFC038)) -#define FIO1CLR (*((volatile unsigned long *) 0x3FFFC03C)) - -/* Memory Accelerator Module (MAM) */ -#define MAMCR (*((volatile unsigned char *) 0xE01FC000)) -#define MAMTIM (*((volatile unsigned char *) 0xE01FC004)) -#define MEMMAP (*((volatile unsigned char *) 0xE01FC040)) - -/* Phase Locked Loop 0 (PLL0) */ -#define PLL0CON (*((volatile unsigned char *) 0xE01FC080)) -#define PLL0CFG (*((volatile unsigned char *) 0xE01FC084)) -#define PLL0STAT (*((volatile unsigned short*) 0xE01FC088)) -#define PLL0FEED (*((volatile unsigned char *) 0xE01FC08C)) - -/* Phase Locked Loop 1 (PLL1) */ -#define PLL1CON (*((volatile unsigned char *) 0xE01FC0A0)) -#define PLL1CFG (*((volatile unsigned char *) 0xE01FC0A4)) -#define PLL1STAT (*((volatile unsigned short*) 0xE01FC0A8)) -#define PLL1FEED (*((volatile unsigned char *) 0xE01FC0AC)) - -/* VPB Divider */ -#define VPBDIV (*((volatile unsigned char *) 0xE01FC100)) - -/* Power Control */ -#define PCON (*((volatile unsigned char *) 0xE01FC0C0)) -#define PCONP (*((volatile unsigned long *) 0xE01FC0C4)) - -/* External Interrupts */ -#define EXTINT (*((volatile unsigned char *) 0xE01FC140)) -#define INTWAKE (*((volatile unsigned short*) 0xE01FC144)) -#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) -#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) - -/* Reset */ -#define RSID (*((volatile unsigned char *) 0xE01FC180)) - -/* Code Security / Debugging */ -#define CSPR (*((volatile unsigned char *) 0xE01FC184)) - -/* System Control Miscellaneous */ -#define SCS (*((volatile unsigned long *) 0xE01FC1A0)) - -/* Timer 0 */ -#define T0IR (*((volatile unsigned long *) 0xE0004000)) -#define T0TCR (*((volatile unsigned long *) 0xE0004004)) -#define T0TC (*((volatile unsigned long *) 0xE0004008)) -#define T0PR (*((volatile unsigned long *) 0xE000400C)) -#define T0PC (*((volatile unsigned long *) 0xE0004010)) -#define T0MCR (*((volatile unsigned long *) 0xE0004014)) -#define T0MR0 (*((volatile unsigned long *) 0xE0004018)) -#define T0MR1 (*((volatile unsigned long *) 0xE000401C)) -#define T0MR2 (*((volatile unsigned long *) 0xE0004020)) -#define T0MR3 (*((volatile unsigned long *) 0xE0004024)) -#define T0CCR (*((volatile unsigned long *) 0xE0004028)) -#define T0CR0 (*((volatile unsigned long *) 0xE000402C)) -#define T0CR1 (*((volatile unsigned long *) 0xE0004030)) -#define T0CR2 (*((volatile unsigned long *) 0xE0004034)) -#define T0CR3 (*((volatile unsigned long *) 0xE0004038)) -#define T0EMR (*((volatile unsigned long *) 0xE000403C)) -#define T0CTCR (*((volatile unsigned long *) 0xE0004070)) - -/* Timer 1 */ -#define T1IR (*((volatile unsigned long *) 0xE0008000)) -#define T1TCR (*((volatile unsigned long *) 0xE0008004)) -#define T1TC (*((volatile unsigned long *) 0xE0008008)) -#define T1PR (*((volatile unsigned long *) 0xE000800C)) -#define T1PC (*((volatile unsigned long *) 0xE0008010)) -#define T1MCR (*((volatile unsigned long *) 0xE0008014)) -#define T1MR0 (*((volatile unsigned long *) 0xE0008018)) -#define T1MR1 (*((volatile unsigned long *) 0xE000801C)) -#define T1MR2 (*((volatile unsigned long *) 0xE0008020)) -#define T1MR3 (*((volatile unsigned long *) 0xE0008024)) -#define T1CCR (*((volatile unsigned long *) 0xE0008028)) -#define T1CR0 (*((volatile unsigned long *) 0xE000802C)) -#define T1CR1 (*((volatile unsigned long *) 0xE0008030)) -#define T1CR2 (*((volatile unsigned long *) 0xE0008034)) -#define T1CR3 (*((volatile unsigned long *) 0xE0008038)) -#define T1EMR (*((volatile unsigned long *) 0xE000803C)) -#define T1CTCR (*((volatile unsigned long *) 0xE0008070)) - -/* Pulse Width Modulator (PWM) */ -#define PWMIR (*((volatile unsigned long *) 0xE0014000)) -#define PWMTCR (*((volatile unsigned long *) 0xE0014004)) -#define PWMTC (*((volatile unsigned long *) 0xE0014008)) -#define PWMPR (*((volatile unsigned long *) 0xE001400C)) -#define PWMPC (*((volatile unsigned long *) 0xE0014010)) -#define PWMMCR (*((volatile unsigned long *) 0xE0014014)) -#define PWMMR0 (*((volatile unsigned long *) 0xE0014018)) -#define PWMMR1 (*((volatile unsigned long *) 0xE001401C)) -#define PWMMR2 (*((volatile unsigned long *) 0xE0014020)) -#define PWMMR3 (*((volatile unsigned long *) 0xE0014024)) -#define PWMMR4 (*((volatile unsigned long *) 0xE0014040)) -#define PWMMR5 (*((volatile unsigned long *) 0xE0014044)) -#define PWMMR6 (*((volatile unsigned long *) 0xE0014048)) -#define PWMPCR (*((volatile unsigned long *) 0xE001404C)) -#define PWMLER (*((volatile unsigned long *) 0xE0014050)) - -/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ -#define U0RBR (*((volatile unsigned char *) 0xE000C000)) -#define U0THR (*((volatile unsigned char *) 0xE000C000)) -#define U0IER (*((volatile unsigned long *) 0xE000C004)) -#define U0IIR (*((volatile unsigned long *) 0xE000C008)) -#define U0FCR (*((volatile unsigned char *) 0xE000C008)) -#define U0LCR (*((volatile unsigned char *) 0xE000C00C)) -#define U0MCR (*((volatile unsigned char *) 0xE000C010)) -#define U0LSR (*((volatile unsigned char *) 0xE000C014)) -#define U0MSR (*((volatile unsigned char *) 0xE000C018)) -#define U0SCR (*((volatile unsigned char *) 0xE000C01C)) -#define U0DLL (*((volatile unsigned char *) 0xE000C000)) -#define U0DLM (*((volatile unsigned char *) 0xE000C004)) -#define U0ACR (*((volatile unsigned long *) 0xE000C020)) -#define U0FDR (*((volatile unsigned long *) 0xE000C028)) -#define U0TER (*((volatile unsigned char *) 0xE000C030)) - -/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ -#define U1RBR (*((volatile unsigned char *) 0xE0010000)) -#define U1THR (*((volatile unsigned char *) 0xE0010000)) -#define U1IER (*((volatile unsigned long *) 0xE0010004)) -#define U1IIR (*((volatile unsigned long *) 0xE0010008)) -#define U1FCR (*((volatile unsigned char *) 0xE0010008)) -#define U1LCR (*((volatile unsigned char *) 0xE001000C)) -#define U1MCR (*((volatile unsigned char *) 0xE0010010)) -#define U1LSR (*((volatile unsigned char *) 0xE0010014)) -#define U1MSR (*((volatile unsigned char *) 0xE0010018)) -#define U1SCR (*((volatile unsigned char *) 0xE001001C)) -#define U1DLL (*((volatile unsigned char *) 0xE0010000)) -#define U1DLM (*((volatile unsigned char *) 0xE0010004)) -#define U1ACR (*((volatile unsigned long *) 0xE0010020)) -#define U1FDR (*((volatile unsigned long *) 0xE0010028)) -#define U1TER (*((volatile unsigned char *) 0xE0010030)) - -/* I2C Interface 0 */ -#define I2C0CONSET (*((volatile unsigned char *) 0xE001C000)) -#define I2C0STAT (*((volatile unsigned char *) 0xE001C004)) -#define I2C0DAT (*((volatile unsigned char *) 0xE001C008)) -#define I2C0ADR (*((volatile unsigned char *) 0xE001C00C)) -#define I2C0SCLH (*((volatile unsigned short*) 0xE001C010)) -#define I2C0SCLL (*((volatile unsigned short*) 0xE001C014)) -#define I2C0CONCLR (*((volatile unsigned char *) 0xE001C018)) - -/* I2C Interface 1 */ -#define I2C1CONSET (*((volatile unsigned char *) 0xE005C000)) -#define I2C1STAT (*((volatile unsigned char *) 0xE005C004)) -#define I2C1DAT (*((volatile unsigned char *) 0xE005C008)) -#define I2C1ADR (*((volatile unsigned char *) 0xE005C00C)) -#define I2C1SCLH (*((volatile unsigned short*) 0xE005C010)) -#define I2C1SCLL (*((volatile unsigned short*) 0xE005C014)) -#define I2C1CONCLR (*((volatile unsigned char *) 0xE005C018)) - -/* SPI0 (Serial Peripheral Interface 0) */ -#define S0SPCR (*((volatile unsigned short*) 0xE0020000)) -#define S0SPSR (*((volatile unsigned char *) 0xE0020004)) -#define S0SPDR (*((volatile unsigned short*) 0xE0020008)) -#define S0SPCCR (*((volatile unsigned char *) 0xE002000C)) -#define S0SPINT (*((volatile unsigned char *) 0xE002001C)) - -/* SSP Controller (SPI1) */ -#define SSPCR0 (*((volatile unsigned short*) 0xE0068000)) -#define SSPCR1 (*((volatile unsigned char *) 0xE0068004)) -#define SSPDR (*((volatile unsigned short*) 0xE0068008)) -#define SSPSR (*((volatile unsigned char *) 0xE006800C)) -#define SSPCPSR (*((volatile unsigned char *) 0xE0068010)) -#define SSPIMSC (*((volatile unsigned char *) 0xE0068014)) -#define SSPRIS (*((volatile unsigned char *) 0xE0068018)) -#define SSPMIS (*((volatile unsigned char *) 0xE006801C)) -#define SSPICR (*((volatile unsigned char *) 0xE0068020)) - -/* Real Time Clock */ -#define ILR (*((volatile unsigned char *) 0xE0024000)) -#define CTC (*((volatile unsigned short*) 0xE0024004)) -#define CCR (*((volatile unsigned char *) 0xE0024008)) -#define CIIR (*((volatile unsigned char *) 0xE002400C)) -#define AMR (*((volatile unsigned char *) 0xE0024010)) -#define CTIME0 (*((volatile unsigned long *) 0xE0024014)) -#define CTIME1 (*((volatile unsigned long *) 0xE0024018)) -#define CTIME2 (*((volatile unsigned long *) 0xE002401C)) -#define SEC (*((volatile unsigned char *) 0xE0024020)) -#define MIN (*((volatile unsigned char *) 0xE0024024)) -#define HOUR (*((volatile unsigned char *) 0xE0024028)) -#define DOM (*((volatile unsigned char *) 0xE002402C)) -#define DOW (*((volatile unsigned char *) 0xE0024030)) -#define DOY (*((volatile unsigned short*) 0xE0024034)) -#define MONTH (*((volatile unsigned char *) 0xE0024038)) -#define YEAR (*((volatile unsigned short*) 0xE002403C)) -#define ALSEC (*((volatile unsigned char *) 0xE0024060)) -#define ALMIN (*((volatile unsigned char *) 0xE0024064)) -#define ALHOUR (*((volatile unsigned char *) 0xE0024068)) -#define ALDOM (*((volatile unsigned char *) 0xE002406C)) -#define ALDOW (*((volatile unsigned char *) 0xE0024070)) -#define ALDOY (*((volatile unsigned short*) 0xE0024074)) -#define ALMON (*((volatile unsigned char *) 0xE0024078)) -#define ALYEAR (*((volatile unsigned short*) 0xE002407C)) -#define PREINT (*((volatile unsigned short*) 0xE0024080)) -#define PREFRAC (*((volatile unsigned short*) 0xE0024084)) - -/* A/D Converter 0 (AD0) */ -#define AD0CR (*((volatile unsigned long *) 0xE0034000)) -#define AD0GDR (*((volatile unsigned long *) 0xE0034004)) -#define AD0STAT (*((volatile unsigned long *) 0xE0034030)) -#define AD0INTEN (*((volatile unsigned long *) 0xE003400C)) -#define AD0DR0 (*((volatile unsigned long *) 0xE0034010)) -#define AD0DR1 (*((volatile unsigned long *) 0xE0034014)) -#define AD0DR2 (*((volatile unsigned long *) 0xE0034018)) -#define AD0DR3 (*((volatile unsigned long *) 0xE003401C)) -#define AD0DR4 (*((volatile unsigned long *) 0xE0034020)) -#define AD0DR5 (*((volatile unsigned long *) 0xE0034024)) -#define AD0DR6 (*((volatile unsigned long *) 0xE0034028)) -#define AD0DR7 (*((volatile unsigned long *) 0xE003402C)) - -/* A/D Converter 1 (AD1) */ -#define AD1CR (*((volatile unsigned long *) 0xE0060000)) -#define AD1GDR (*((volatile unsigned long *) 0xE0060004)) -#define AD1STAT (*((volatile unsigned long *) 0xE0060030)) -#define AD1INTEN (*((volatile unsigned long *) 0xE006000C)) -#define AD1DR0 (*((volatile unsigned long *) 0xE0060010)) -#define AD1DR1 (*((volatile unsigned long *) 0xE0060014)) -#define AD1DR2 (*((volatile unsigned long *) 0xE0060018)) -#define AD1DR3 (*((volatile unsigned long *) 0xE006001C)) -#define AD1DR4 (*((volatile unsigned long *) 0xE0060020)) -#define AD1DR5 (*((volatile unsigned long *) 0xE0060024)) -#define AD1DR6 (*((volatile unsigned long *) 0xE0060028)) -#define AD1DR7 (*((volatile unsigned long *) 0xE006002C)) - -/* A/D Converter Global */ -#define ADGSR (*((volatile unsigned long *) 0xE0034008)) - -/* D/A Converter */ -#define DACR (*((volatile unsigned long *) 0xE006C000)) - -/* Watchdog */ -#define WDMOD (*((volatile unsigned char *) 0xE0000000)) -#define WDTC (*((volatile unsigned long *) 0xE0000004)) -#define WDFEED (*((volatile unsigned char *) 0xE0000008)) -#define WDTV (*((volatile unsigned long *) 0xE000000C)) - -/* USB Controller */ -#define USBIntSt (*((volatile unsigned long *) 0xE01FC1C0)) -#define USBDevIntSt (*((volatile unsigned long *) 0xE0090000)) -#define USBDevIntEn (*((volatile unsigned long *) 0xE0090004)) -#define USBDevIntClr (*((volatile unsigned long *) 0xE0090008)) -#define USBDevIntSet (*((volatile unsigned long *) 0xE009000C)) -#define USBDevIntPri (*((volatile unsigned char *) 0xE009002C)) -#define USBEpIntSt (*((volatile unsigned long *) 0xE0090030)) -#define USBEpIntEn (*((volatile unsigned long *) 0xE0090034)) -#define USBEpIntClr (*((volatile unsigned long *) 0xE0090038)) -#define USBEpIntSet (*((volatile unsigned long *) 0xE009003C)) -#define USBEpIntPri (*((volatile unsigned long *) 0xE0090040)) -#define USBReEp (*((volatile unsigned long *) 0xE0090044)) -#define USBEpInd (*((volatile unsigned long *) 0xE0090048)) -#define USBMaxPSize (*((volatile unsigned long *) 0xE009004C)) -#define USBRxData (*((volatile unsigned long *) 0xE0090018)) -#define USBRxPLen (*((volatile unsigned long *) 0xE0090020)) -#define USBTxData (*((volatile unsigned long *) 0xE009001C)) -#define USBTxPLen (*((volatile unsigned long *) 0xE0090024)) -#define USBCtrl (*((volatile unsigned long *) 0xE0090028)) -#define USBCmdCode (*((volatile unsigned long *) 0xE0090010)) -#define USBCmdData (*((volatile unsigned long *) 0xE0090014)) -#define USBDMARSt (*((volatile unsigned long *) 0xE0090050)) -#define USBDMARClr (*((volatile unsigned long *) 0xE0090054)) -#define USBDMARSet (*((volatile unsigned long *) 0xE0090058)) -#define USBUDCAH (*((volatile unsigned long *) 0xE0090080)) -#define USBEpDMASt (*((volatile unsigned long *) 0xE0090084)) -#define USBEpDMAEn (*((volatile unsigned long *) 0xE0090088)) -#define USBEpDMADis (*((volatile unsigned long *) 0xE009008C)) -#define USBDMAIntSt (*((volatile unsigned long *) 0xE0090090)) -#define USBDMAIntEn (*((volatile unsigned long *) 0xE0090094)) -#define USBEoTIntSt (*((volatile unsigned long *) 0xE00900A0)) -#define USBEoTIntClr (*((volatile unsigned long *) 0xE00900A4)) -#define USBEoTIntSet (*((volatile unsigned long *) 0xE00900A8)) -#define USBNDDRIntSt (*((volatile unsigned long *) 0xE00900AC)) -#define USBNDDRIntClr (*((volatile unsigned long *) 0xE00900B0)) -#define USBNDDRIntSet (*((volatile unsigned long *) 0xE00900B4)) -#define USBSysErrIntSt (*((volatile unsigned long *) 0xE00900B8)) -#define USBSysErrIntClr (*((volatile unsigned long *) 0xE00900BC)) -#define USBSysErrIntSet (*((volatile unsigned long *) 0xE00900C0)) - -#define VIC_BASE_ADDR 0xFFFFF000 - -enum LPC214x_INT -{ - WDT_INT = 0, - SW_INT_reserved, - DbgCommRx_INT, - DbgCommTx_INT, - TIMER0_INT, - TIMER1_INT, - UART0_INT, - UART1_INT, - PWM0_INT, - I2C0_INT, - SP0_INT, - SP1_INT, - PLL_INT, - RTC_INT, - EINT0_INT, - EINT1_INT, - EINT2_INT, - EINT3_INT, - ADC0_INT, - I2C1_INT, - BOD_INT, - ADC1_INT, - USB_INT -}; - -#endif // __LPC214x_H +/***********************************************************************/ +/* This file is part of the uVision/ARM development tools */ +/* Copyright KEIL ELEKTRONIK GmbH 2002-2005 */ +/***********************************************************************/ +/* */ +/* LPC214X.H: Header file for Philips LPC2141/42/44/46/48 */ +/* */ +/***********************************************************************/ + +#ifndef __LPC214x_H +#define __LPC214x_H + +/* Vectored Interrupt Controller (VIC) */ +#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000)) +#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004)) +#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008)) +#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C)) +#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010)) +#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014)) +#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018)) +#define VICSoftIntClr (*((volatile unsigned long *) 0xFFFFF01C)) +#define VICProtection (*((volatile unsigned long *) 0xFFFFF020)) +#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030)) +#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034)) +#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100)) +#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104)) +#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108)) +#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C)) +#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110)) +#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114)) +#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118)) +#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C)) +#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120)) +#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124)) +#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128)) +#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C)) +#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130)) +#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134)) +#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138)) +#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C)) +#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200)) +#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204)) +#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208)) +#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C)) +#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210)) +#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214)) +#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218)) +#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C)) +#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220)) +#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224)) +#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228)) +#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C)) +#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230)) +#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234)) +#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238)) +#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C)) + +/* Pin Connect Block */ +#define PINSEL0 (*((volatile unsigned long *) 0xE002C000)) +#define PINSEL1 (*((volatile unsigned long *) 0xE002C004)) +#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) + +/* General Purpose Input/Output (GPIO) */ +#define IOPIN0 (*((volatile unsigned long *) 0xE0028000)) +#define IOSET0 (*((volatile unsigned long *) 0xE0028004)) +#define IODIR0 (*((volatile unsigned long *) 0xE0028008)) +#define IOCLR0 (*((volatile unsigned long *) 0xE002800C)) +#define IOPIN1 (*((volatile unsigned long *) 0xE0028010)) +#define IOSET1 (*((volatile unsigned long *) 0xE0028014)) +#define IODIR1 (*((volatile unsigned long *) 0xE0028018)) +#define IOCLR1 (*((volatile unsigned long *) 0xE002801C)) +#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) +#define IO0SET (*((volatile unsigned long *) 0xE0028004)) +#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) +#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) +#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) +#define IO1SET (*((volatile unsigned long *) 0xE0028014)) +#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) +#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) +#define FIO0DIR (*((volatile unsigned long *) 0x3FFFC000)) +#define FIO0MASK (*((volatile unsigned long *) 0x3FFFC010)) +#define FIO0PIN (*((volatile unsigned long *) 0x3FFFC014)) +#define FIO0SET (*((volatile unsigned long *) 0x3FFFC018)) +#define FIO0CLR (*((volatile unsigned long *) 0x3FFFC01C)) +#define FIO1DIR (*((volatile unsigned long *) 0x3FFFC020)) +#define FIO1MASK (*((volatile unsigned long *) 0x3FFFC030)) +#define FIO1PIN (*((volatile unsigned long *) 0x3FFFC034)) +#define FIO1SET (*((volatile unsigned long *) 0x3FFFC038)) +#define FIO1CLR (*((volatile unsigned long *) 0x3FFFC03C)) + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*((volatile unsigned char *) 0xE01FC000)) +#define MAMTIM (*((volatile unsigned char *) 0xE01FC004)) +#define MEMMAP (*((volatile unsigned char *) 0xE01FC040)) + +/* Phase Locked Loop 0 (PLL0) */ +#define PLL0CON (*((volatile unsigned char *) 0xE01FC080)) +#define PLL0CFG (*((volatile unsigned char *) 0xE01FC084)) +#define PLL0STAT (*((volatile unsigned short*) 0xE01FC088)) +#define PLL0FEED (*((volatile unsigned char *) 0xE01FC08C)) + +/* Phase Locked Loop 1 (PLL1) */ +#define PLL1CON (*((volatile unsigned char *) 0xE01FC0A0)) +#define PLL1CFG (*((volatile unsigned char *) 0xE01FC0A4)) +#define PLL1STAT (*((volatile unsigned short*) 0xE01FC0A8)) +#define PLL1FEED (*((volatile unsigned char *) 0xE01FC0AC)) + +/* VPB Divider */ +#define VPBDIV (*((volatile unsigned char *) 0xE01FC100)) + +/* Power Control */ +#define PCON (*((volatile unsigned char *) 0xE01FC0C0)) +#define PCONP (*((volatile unsigned long *) 0xE01FC0C4)) + +/* External Interrupts */ +#define EXTINT (*((volatile unsigned char *) 0xE01FC140)) +#define INTWAKE (*((volatile unsigned short*) 0xE01FC144)) +#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) +#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) + +/* Reset */ +#define RSID (*((volatile unsigned char *) 0xE01FC180)) + +/* Code Security / Debugging */ +#define CSPR (*((volatile unsigned char *) 0xE01FC184)) + +/* System Control Miscellaneous */ +#define SCS (*((volatile unsigned long *) 0xE01FC1A0)) + +/* Timer 0 */ +#define T0IR (*((volatile unsigned long *) 0xE0004000)) +#define T0TCR (*((volatile unsigned long *) 0xE0004004)) +#define T0TC (*((volatile unsigned long *) 0xE0004008)) +#define T0PR (*((volatile unsigned long *) 0xE000400C)) +#define T0PC (*((volatile unsigned long *) 0xE0004010)) +#define T0MCR (*((volatile unsigned long *) 0xE0004014)) +#define T0MR0 (*((volatile unsigned long *) 0xE0004018)) +#define T0MR1 (*((volatile unsigned long *) 0xE000401C)) +#define T0MR2 (*((volatile unsigned long *) 0xE0004020)) +#define T0MR3 (*((volatile unsigned long *) 0xE0004024)) +#define T0CCR (*((volatile unsigned long *) 0xE0004028)) +#define T0CR0 (*((volatile unsigned long *) 0xE000402C)) +#define T0CR1 (*((volatile unsigned long *) 0xE0004030)) +#define T0CR2 (*((volatile unsigned long *) 0xE0004034)) +#define T0CR3 (*((volatile unsigned long *) 0xE0004038)) +#define T0EMR (*((volatile unsigned long *) 0xE000403C)) +#define T0CTCR (*((volatile unsigned long *) 0xE0004070)) + +/* Timer 1 */ +#define T1IR (*((volatile unsigned long *) 0xE0008000)) +#define T1TCR (*((volatile unsigned long *) 0xE0008004)) +#define T1TC (*((volatile unsigned long *) 0xE0008008)) +#define T1PR (*((volatile unsigned long *) 0xE000800C)) +#define T1PC (*((volatile unsigned long *) 0xE0008010)) +#define T1MCR (*((volatile unsigned long *) 0xE0008014)) +#define T1MR0 (*((volatile unsigned long *) 0xE0008018)) +#define T1MR1 (*((volatile unsigned long *) 0xE000801C)) +#define T1MR2 (*((volatile unsigned long *) 0xE0008020)) +#define T1MR3 (*((volatile unsigned long *) 0xE0008024)) +#define T1CCR (*((volatile unsigned long *) 0xE0008028)) +#define T1CR0 (*((volatile unsigned long *) 0xE000802C)) +#define T1CR1 (*((volatile unsigned long *) 0xE0008030)) +#define T1CR2 (*((volatile unsigned long *) 0xE0008034)) +#define T1CR3 (*((volatile unsigned long *) 0xE0008038)) +#define T1EMR (*((volatile unsigned long *) 0xE000803C)) +#define T1CTCR (*((volatile unsigned long *) 0xE0008070)) + +/* Pulse Width Modulator (PWM) */ +#define PWMIR (*((volatile unsigned long *) 0xE0014000)) +#define PWMTCR (*((volatile unsigned long *) 0xE0014004)) +#define PWMTC (*((volatile unsigned long *) 0xE0014008)) +#define PWMPR (*((volatile unsigned long *) 0xE001400C)) +#define PWMPC (*((volatile unsigned long *) 0xE0014010)) +#define PWMMCR (*((volatile unsigned long *) 0xE0014014)) +#define PWMMR0 (*((volatile unsigned long *) 0xE0014018)) +#define PWMMR1 (*((volatile unsigned long *) 0xE001401C)) +#define PWMMR2 (*((volatile unsigned long *) 0xE0014020)) +#define PWMMR3 (*((volatile unsigned long *) 0xE0014024)) +#define PWMMR4 (*((volatile unsigned long *) 0xE0014040)) +#define PWMMR5 (*((volatile unsigned long *) 0xE0014044)) +#define PWMMR6 (*((volatile unsigned long *) 0xE0014048)) +#define PWMPCR (*((volatile unsigned long *) 0xE001404C)) +#define PWMLER (*((volatile unsigned long *) 0xE0014050)) + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define U0RBR (*((volatile unsigned char *) 0xE000C000)) +#define U0THR (*((volatile unsigned char *) 0xE000C000)) +#define U0IER (*((volatile unsigned long *) 0xE000C004)) +#define U0IIR (*((volatile unsigned long *) 0xE000C008)) +#define U0FCR (*((volatile unsigned char *) 0xE000C008)) +#define U0LCR (*((volatile unsigned char *) 0xE000C00C)) +#define U0MCR (*((volatile unsigned char *) 0xE000C010)) +#define U0LSR (*((volatile unsigned char *) 0xE000C014)) +#define U0MSR (*((volatile unsigned char *) 0xE000C018)) +#define U0SCR (*((volatile unsigned char *) 0xE000C01C)) +#define U0DLL (*((volatile unsigned char *) 0xE000C000)) +#define U0DLM (*((volatile unsigned char *) 0xE000C004)) +#define U0ACR (*((volatile unsigned long *) 0xE000C020)) +#define U0FDR (*((volatile unsigned long *) 0xE000C028)) +#define U0TER (*((volatile unsigned char *) 0xE000C030)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define U1RBR (*((volatile unsigned char *) 0xE0010000)) +#define U1THR (*((volatile unsigned char *) 0xE0010000)) +#define U1IER (*((volatile unsigned long *) 0xE0010004)) +#define U1IIR (*((volatile unsigned long *) 0xE0010008)) +#define U1FCR (*((volatile unsigned char *) 0xE0010008)) +#define U1LCR (*((volatile unsigned char *) 0xE001000C)) +#define U1MCR (*((volatile unsigned char *) 0xE0010010)) +#define U1LSR (*((volatile unsigned char *) 0xE0010014)) +#define U1MSR (*((volatile unsigned char *) 0xE0010018)) +#define U1SCR (*((volatile unsigned char *) 0xE001001C)) +#define U1DLL (*((volatile unsigned char *) 0xE0010000)) +#define U1DLM (*((volatile unsigned char *) 0xE0010004)) +#define U1ACR (*((volatile unsigned long *) 0xE0010020)) +#define U1FDR (*((volatile unsigned long *) 0xE0010028)) +#define U1TER (*((volatile unsigned char *) 0xE0010030)) + +/* I2C Interface 0 */ +#define I2C0CONSET (*((volatile unsigned char *) 0xE001C000)) +#define I2C0STAT (*((volatile unsigned char *) 0xE001C004)) +#define I2C0DAT (*((volatile unsigned char *) 0xE001C008)) +#define I2C0ADR (*((volatile unsigned char *) 0xE001C00C)) +#define I2C0SCLH (*((volatile unsigned short*) 0xE001C010)) +#define I2C0SCLL (*((volatile unsigned short*) 0xE001C014)) +#define I2C0CONCLR (*((volatile unsigned char *) 0xE001C018)) + +/* I2C Interface 1 */ +#define I2C1CONSET (*((volatile unsigned char *) 0xE005C000)) +#define I2C1STAT (*((volatile unsigned char *) 0xE005C004)) +#define I2C1DAT (*((volatile unsigned char *) 0xE005C008)) +#define I2C1ADR (*((volatile unsigned char *) 0xE005C00C)) +#define I2C1SCLH (*((volatile unsigned short*) 0xE005C010)) +#define I2C1SCLL (*((volatile unsigned short*) 0xE005C014)) +#define I2C1CONCLR (*((volatile unsigned char *) 0xE005C018)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define S0SPCR (*((volatile unsigned short*) 0xE0020000)) +#define S0SPSR (*((volatile unsigned char *) 0xE0020004)) +#define S0SPDR (*((volatile unsigned short*) 0xE0020008)) +#define S0SPCCR (*((volatile unsigned char *) 0xE002000C)) +#define S0SPINT (*((volatile unsigned char *) 0xE002001C)) + +/* SSP Controller (SPI1) */ +#define SSPCR0 (*((volatile unsigned short*) 0xE0068000)) +#define SSPCR1 (*((volatile unsigned char *) 0xE0068004)) +#define SSPDR (*((volatile unsigned short*) 0xE0068008)) +#define SSPSR (*((volatile unsigned char *) 0xE006800C)) +#define SSPCPSR (*((volatile unsigned char *) 0xE0068010)) +#define SSPIMSC (*((volatile unsigned char *) 0xE0068014)) +#define SSPRIS (*((volatile unsigned char *) 0xE0068018)) +#define SSPMIS (*((volatile unsigned char *) 0xE006801C)) +#define SSPICR (*((volatile unsigned char *) 0xE0068020)) + +/* Real Time Clock */ +#define ILR (*((volatile unsigned char *) 0xE0024000)) +#define CTC (*((volatile unsigned short*) 0xE0024004)) +#define CCR (*((volatile unsigned char *) 0xE0024008)) +#define CIIR (*((volatile unsigned char *) 0xE002400C)) +#define AMR (*((volatile unsigned char *) 0xE0024010)) +#define CTIME0 (*((volatile unsigned long *) 0xE0024014)) +#define CTIME1 (*((volatile unsigned long *) 0xE0024018)) +#define CTIME2 (*((volatile unsigned long *) 0xE002401C)) +#define SEC (*((volatile unsigned char *) 0xE0024020)) +#define MIN (*((volatile unsigned char *) 0xE0024024)) +#define HOUR (*((volatile unsigned char *) 0xE0024028)) +#define DOM (*((volatile unsigned char *) 0xE002402C)) +#define DOW (*((volatile unsigned char *) 0xE0024030)) +#define DOY (*((volatile unsigned short*) 0xE0024034)) +#define MONTH (*((volatile unsigned char *) 0xE0024038)) +#define YEAR (*((volatile unsigned short*) 0xE002403C)) +#define ALSEC (*((volatile unsigned char *) 0xE0024060)) +#define ALMIN (*((volatile unsigned char *) 0xE0024064)) +#define ALHOUR (*((volatile unsigned char *) 0xE0024068)) +#define ALDOM (*((volatile unsigned char *) 0xE002406C)) +#define ALDOW (*((volatile unsigned char *) 0xE0024070)) +#define ALDOY (*((volatile unsigned short*) 0xE0024074)) +#define ALMON (*((volatile unsigned char *) 0xE0024078)) +#define ALYEAR (*((volatile unsigned short*) 0xE002407C)) +#define PREINT (*((volatile unsigned short*) 0xE0024080)) +#define PREFRAC (*((volatile unsigned short*) 0xE0024084)) + +/* A/D Converter 0 (AD0) */ +#define AD0CR (*((volatile unsigned long *) 0xE0034000)) +#define AD0GDR (*((volatile unsigned long *) 0xE0034004)) +#define AD0STAT (*((volatile unsigned long *) 0xE0034030)) +#define AD0INTEN (*((volatile unsigned long *) 0xE003400C)) +#define AD0DR0 (*((volatile unsigned long *) 0xE0034010)) +#define AD0DR1 (*((volatile unsigned long *) 0xE0034014)) +#define AD0DR2 (*((volatile unsigned long *) 0xE0034018)) +#define AD0DR3 (*((volatile unsigned long *) 0xE003401C)) +#define AD0DR4 (*((volatile unsigned long *) 0xE0034020)) +#define AD0DR5 (*((volatile unsigned long *) 0xE0034024)) +#define AD0DR6 (*((volatile unsigned long *) 0xE0034028)) +#define AD0DR7 (*((volatile unsigned long *) 0xE003402C)) + +/* A/D Converter 1 (AD1) */ +#define AD1CR (*((volatile unsigned long *) 0xE0060000)) +#define AD1GDR (*((volatile unsigned long *) 0xE0060004)) +#define AD1STAT (*((volatile unsigned long *) 0xE0060030)) +#define AD1INTEN (*((volatile unsigned long *) 0xE006000C)) +#define AD1DR0 (*((volatile unsigned long *) 0xE0060010)) +#define AD1DR1 (*((volatile unsigned long *) 0xE0060014)) +#define AD1DR2 (*((volatile unsigned long *) 0xE0060018)) +#define AD1DR3 (*((volatile unsigned long *) 0xE006001C)) +#define AD1DR4 (*((volatile unsigned long *) 0xE0060020)) +#define AD1DR5 (*((volatile unsigned long *) 0xE0060024)) +#define AD1DR6 (*((volatile unsigned long *) 0xE0060028)) +#define AD1DR7 (*((volatile unsigned long *) 0xE006002C)) + +/* A/D Converter Global */ +#define ADGSR (*((volatile unsigned long *) 0xE0034008)) + +/* D/A Converter */ +#define DACR (*((volatile unsigned long *) 0xE006C000)) + +/* Watchdog */ +#define WDMOD (*((volatile unsigned char *) 0xE0000000)) +#define WDTC (*((volatile unsigned long *) 0xE0000004)) +#define WDFEED (*((volatile unsigned char *) 0xE0000008)) +#define WDTV (*((volatile unsigned long *) 0xE000000C)) + +/* USB Controller */ +#define USBIntSt (*((volatile unsigned long *) 0xE01FC1C0)) +#define USBDevIntSt (*((volatile unsigned long *) 0xE0090000)) +#define USBDevIntEn (*((volatile unsigned long *) 0xE0090004)) +#define USBDevIntClr (*((volatile unsigned long *) 0xE0090008)) +#define USBDevIntSet (*((volatile unsigned long *) 0xE009000C)) +#define USBDevIntPri (*((volatile unsigned char *) 0xE009002C)) +#define USBEpIntSt (*((volatile unsigned long *) 0xE0090030)) +#define USBEpIntEn (*((volatile unsigned long *) 0xE0090034)) +#define USBEpIntClr (*((volatile unsigned long *) 0xE0090038)) +#define USBEpIntSet (*((volatile unsigned long *) 0xE009003C)) +#define USBEpIntPri (*((volatile unsigned long *) 0xE0090040)) +#define USBReEp (*((volatile unsigned long *) 0xE0090044)) +#define USBEpInd (*((volatile unsigned long *) 0xE0090048)) +#define USBMaxPSize (*((volatile unsigned long *) 0xE009004C)) +#define USBRxData (*((volatile unsigned long *) 0xE0090018)) +#define USBRxPLen (*((volatile unsigned long *) 0xE0090020)) +#define USBTxData (*((volatile unsigned long *) 0xE009001C)) +#define USBTxPLen (*((volatile unsigned long *) 0xE0090024)) +#define USBCtrl (*((volatile unsigned long *) 0xE0090028)) +#define USBCmdCode (*((volatile unsigned long *) 0xE0090010)) +#define USBCmdData (*((volatile unsigned long *) 0xE0090014)) +#define USBDMARSt (*((volatile unsigned long *) 0xE0090050)) +#define USBDMARClr (*((volatile unsigned long *) 0xE0090054)) +#define USBDMARSet (*((volatile unsigned long *) 0xE0090058)) +#define USBUDCAH (*((volatile unsigned long *) 0xE0090080)) +#define USBEpDMASt (*((volatile unsigned long *) 0xE0090084)) +#define USBEpDMAEn (*((volatile unsigned long *) 0xE0090088)) +#define USBEpDMADis (*((volatile unsigned long *) 0xE009008C)) +#define USBDMAIntSt (*((volatile unsigned long *) 0xE0090090)) +#define USBDMAIntEn (*((volatile unsigned long *) 0xE0090094)) +#define USBEoTIntSt (*((volatile unsigned long *) 0xE00900A0)) +#define USBEoTIntClr (*((volatile unsigned long *) 0xE00900A4)) +#define USBEoTIntSet (*((volatile unsigned long *) 0xE00900A8)) +#define USBNDDRIntSt (*((volatile unsigned long *) 0xE00900AC)) +#define USBNDDRIntClr (*((volatile unsigned long *) 0xE00900B0)) +#define USBNDDRIntSet (*((volatile unsigned long *) 0xE00900B4)) +#define USBSysErrIntSt (*((volatile unsigned long *) 0xE00900B8)) +#define USBSysErrIntClr (*((volatile unsigned long *) 0xE00900BC)) +#define USBSysErrIntSet (*((volatile unsigned long *) 0xE00900C0)) + +#define VIC_BASE_ADDR 0xFFFFF000 + +enum LPC214x_INT +{ + WDT_INT = 0, + SW_INT_reserved, + DbgCommRx_INT, + DbgCommTx_INT, + TIMER0_INT, + TIMER1_INT, + UART0_INT, + UART1_INT, + PWM0_INT, + I2C0_INT, + SP0_INT, + SP1_INT, + PLL_INT, + RTC_INT, + EINT0_INT, + EINT1_INT, + EINT2_INT, + EINT3_INT, + ADC0_INT, + I2C1_INT, + BOD_INT, + ADC1_INT, + USB_INT +}; + +#endif // __LPC214x_H diff --git a/libcpu/arm/lpc214x/start_rvds.S b/libcpu/arm/lpc214x/start_rvds.S index bee5c64de3ef3b6ef93ec5d3c59ff87132841030..bef523bc74cf0e06b7bdf8a0ef56b32cab9b4b1c 100644 --- a/libcpu/arm/lpc214x/start_rvds.S +++ b/libcpu/arm/lpc214x/start_rvds.S @@ -1,464 +1,464 @@ -;/*****************************************************************************/ -;/* STARTUP.S: Startup file for Philips LPC2000 */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -;/* -; * The STARTUP.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * REMAP: when set the startup code initializes the register MEMMAP -; * which overwrites the settings of the CPU configuration pins. The -; * startup and interrupt vectors are remapped from: -; * 0x00000000 default setting (not remapped) -; * 0x80000000 when EXTMEM_MODE is used -; * 0x40000000 when RAM_MODE is used -; * -; * EXTMEM_MODE: when set the device is configured for code execution -; * from external memory starting at address 0x80000000. -; * -; * RAM_MODE: when set the device is configured for code execution -; * from on-chip RAM starting at address 0x40000000. -; * -; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable -; * the external BUS at startup. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000100 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000100 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size - -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -; VPBDIV definitions -VPBDIV EQU 0xE01FC100 ; VPBDIV Address - -;// VPBDIV Setup -;// Peripheral Bus Clock Rate -;// VPBDIV: VPB Clock -;// <0=> VPB Clock = CPU Clock / 4 -;// <1=> VPB Clock = CPU Clock -;// <2=> VPB Clock = CPU Clock / 2 -;// XCLKDIV: XCLK Pin -;// <0=> XCLK Pin = CPU Clock / 4 -;// <1=> XCLK Pin = CPU Clock -;// <2=> XCLK Pin = CPU Clock / 2 -;// -VPBDIV_SETUP EQU 0 -VPBDIV_Val EQU 0x00000000 - - -; Phase Locked Loop (PLL) definitions -PLL_BASE EQU 0xE01FC080 ; PLL Base Address -PLLCON_OFS EQU 0x00 ; PLL Control Offset -PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset -PLLSTAT_OFS EQU 0x08 ; PLL Status Offset -PLLFEED_OFS EQU 0x0C ; PLL Feed Offset -PLLCON_PLLE EQU (1<<0) ; PLL Enable -PLLCON_PLLC EQU (1<<1) ; PLL Connect -PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier -PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider -PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status - -;// PLL Setup -;// MSEL: PLL Multiplier Selection -;// <1-32><#-1> -;// M Value -;// PSEL: PLL Divider Selection -;// <0=> 1 <1=> 2 <2=> 4 <3=> 8 -;// P Value -;// -PLL_SETUP EQU 1 -PLLCFG_Val EQU 0x00000024 - - -; Memory Accelerator Module (MAM) definitions -MAM_BASE EQU 0xE01FC000 ; MAM Base Address -MAMCR_OFS EQU 0x00 ; MAM Control Offset -MAMTIM_OFS EQU 0x04 ; MAM Timing Offset - -;// MAM Setup -;// MAM Control -;// <0=> Disabled -;// <1=> Partially Enabled -;// <2=> Fully Enabled -;// Mode -;// MAM Timing -;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 -;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 -;// Fetch Cycles -;// -MAM_SETUP EQU 1 -MAMCR_Val EQU 0x00000002 -MAMTIM_Val EQU 0x00000004 - - -; External Memory Controller (EMC) definitions -EMC_BASE EQU 0xFFE00000 ; EMC Base Address -BCFG0_OFS EQU 0x00 ; BCFG0 Offset -BCFG1_OFS EQU 0x04 ; BCFG1 Offset -BCFG2_OFS EQU 0x08 ; BCFG2 Offset -BCFG3_OFS EQU 0x0C ; BCFG3 Offset - -;// External Memory Controller (EMC) -EMC_SETUP EQU 0 - -;// Bank Configuration 0 (BCFG0) -;// IDCY: Idle Cycles <0-15> -;// WST1: Wait States 1 <0-31> -;// WST2: Wait States 2 <0-31> -;// RBLE: Read Byte Lane Enable -;// WP: Write Protect -;// BM: Burst ROM -;// MW: Memory Width <0=> 8-bit <1=> 16-bit -;// <2=> 32-bit <3=> Reserved -;// -BCFG0_SETUP EQU 0 -BCFG0_Val EQU 0x0000FBEF - -;// Bank Configuration 1 (BCFG1) -;// IDCY: Idle Cycles <0-15> -;// WST1: Wait States 1 <0-31> -;// WST2: Wait States 2 <0-31> -;// RBLE: Read Byte Lane Enable -;// WP: Write Protect -;// BM: Burst ROM -;// MW: Memory Width <0=> 8-bit <1=> 16-bit -;// <2=> 32-bit <3=> Reserved -;// -BCFG1_SETUP EQU 0 -BCFG1_Val EQU 0x0000FBEF - -;// Bank Configuration 2 (BCFG2) -;// IDCY: Idle Cycles <0-15> -;// WST1: Wait States 1 <0-31> -;// WST2: Wait States 2 <0-31> -;// RBLE: Read Byte Lane Enable -;// WP: Write Protect -;// BM: Burst ROM -;// MW: Memory Width <0=> 8-bit <1=> 16-bit -;// <2=> 32-bit <3=> Reserved -;// -BCFG2_SETUP EQU 0 -BCFG2_Val EQU 0x0000FBEF - -;// Bank Configuration 3 (BCFG3) -;// IDCY: Idle Cycles <0-15> -;// WST1: Wait States 1 <0-31> -;// WST2: Wait States 2 <0-31> -;// RBLE: Read Byte Lane Enable -;// WP: Write Protect -;// BM: Burst ROM -;// MW: Memory Width <0=> 8-bit <1=> 16-bit -;// <2=> 32-bit <3=> Reserved -;// -BCFG3_SETUP EQU 0 -BCFG3_Val EQU 0x0000FBEF - -;// End of EMC - - -; External Memory Pins definitions -PINSEL2 EQU 0xE002C014 ; PINSEL2 Address -PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3, - ; D0..31, A2..23, JTAG Pins - - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC, Reset_Addr - LDR PC, Undef_Addr - LDR PC, SWI_Addr - LDR PC, PAbt_Addr - LDR PC, DAbt_Addr - NOP ; Reserved Vector - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B PAbt_Handler -DAbt_Handler B DAbt_Handler -FIQ_Handler B FIQ_Handler - - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Setup External Memory Pins - IF :DEF:EXTERNAL_MODE - LDR R0, =PINSEL2 - LDR R1, =PINSEL2_Val - STR R1, [R0] - ENDIF - - -; Setup External Memory Controller - IF EMC_SETUP <> 0 - LDR R0, =EMC_BASE - - IF BCFG0_SETUP <> 0 - LDR R1, =BCFG0_Val - STR R1, [R0, #BCFG0_OFS] - ENDIF - - IF BCFG1_SETUP <> 0 - LDR R1, =BCFG1_Val - STR R1, [R0, #BCFG1_OFS] - ENDIF - - IF BCFG2_SETUP <> 0 - LDR R1, =BCFG2_Val - STR R1, [R0, #BCFG2_OFS] - ENDIF - - IF BCFG3_SETUP <> 0 - LDR R1, =BCFG3_Val - STR R1, [R0, #BCFG3_OFS] - ENDIF - - ENDIF ; EMC_SETUP - - -; Setup VPBDIV - IF VPBDIV_SETUP <> 0 - LDR R0, =VPBDIV - LDR R1, =VPBDIV_Val - STR R1, [R0] - ENDIF - - -; Setup PLL - IF PLL_SETUP <> 0 - LDR R0, =PLL_BASE - MOV R1, #0xAA - MOV R2, #0x55 - -; Configure and Enable PLL - MOV R3, #PLLCFG_Val - STR R3, [R0, #PLLCFG_OFS] - MOV R3, #PLLCON_PLLE - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - -; Wait until PLL Locked -PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] - ANDS R3, R3, #PLLSTAT_PLOCK - BEQ PLL_Loop - -; Switch to PLL Clock - MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - ENDIF ; PLL_SETUP - - -; Setup MAM - IF MAM_SETUP <> 0 - LDR R0, =MAM_BASE - MOV R1, #MAMTIM_Val - STR R1, [R0, #MAMTIM_OFS] - MOV R1, #MAMCR_Val - STR R1, [R0, #MAMCR_OFS] - ENDIF ; MAM_SETUP - - -; Memory Mapping (when Interrupt Vectors are in RAM) -MEMMAP EQU 0xE01FC040 ; Memory Mapping Control - IF :DEF:REMAP - LDR R0, =MEMMAP - IF :DEF:EXTMEM_MODE - MOV R1, #3 - ELIF :DEF:RAM_MODE - MOV R1, #2 - ELSE - MOV R1, #1 - ENDIF - STR R1, [R0] - ENDIF - - -; Initialise Interrupt System -; ... - - -; Setup Stack for each mode - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ; SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; RT-Thread does not use user mode - ; MSR CPSR_c, #Mode_USR - IF :DEF:__MICROLIB - - EXPORT __initial_sp - - ELSE - - ; MOV SP, R0 - ; SUB SL, SP, #USR_Stack_Size - - ENDIF - -; Enter the C code - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - IMPORT rt_hw_context_switch_interrupt_do - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - END +;/*****************************************************************************/ +;/* STARTUP.S: Startup file for Philips LPC2000 */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The STARTUP.S code is executed after CPU Reset. This file may be +; * translated with the following SET symbols. In uVision these SET +; * symbols are entered under Options - ASM - Define. +; * +; * REMAP: when set the startup code initializes the register MEMMAP +; * which overwrites the settings of the CPU configuration pins. The +; * startup and interrupt vectors are remapped from: +; * 0x00000000 default setting (not remapped) +; * 0x80000000 when EXTMEM_MODE is used +; * 0x40000000 when RAM_MODE is used +; * +; * EXTMEM_MODE: when set the device is configured for code execution +; * from external memory starting at address 0x80000000. +; * +; * RAM_MODE: when set the device is configured for code execution +; * from on-chip RAM starting at address 0x40000000. +; * +; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable +; * the external BUS at startup. +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +;// Stack Configuration (Stack Sizes in Bytes) +;// Undefined Mode <0x0-0xFFFFFFFF:8> +;// Supervisor Mode <0x0-0xFFFFFFFF:8> +;// Abort Mode <0x0-0xFFFFFFFF:8> +;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// Interrupt Mode <0x0-0xFFFFFFFF:8> +;// User/System Mode <0x0-0xFFFFFFFF:8> +;// + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size + +Stack_Top + + +;// Heap Configuration +;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +; VPBDIV definitions +VPBDIV EQU 0xE01FC100 ; VPBDIV Address + +;// VPBDIV Setup +;// Peripheral Bus Clock Rate +;// VPBDIV: VPB Clock +;// <0=> VPB Clock = CPU Clock / 4 +;// <1=> VPB Clock = CPU Clock +;// <2=> VPB Clock = CPU Clock / 2 +;// XCLKDIV: XCLK Pin +;// <0=> XCLK Pin = CPU Clock / 4 +;// <1=> XCLK Pin = CPU Clock +;// <2=> XCLK Pin = CPU Clock / 2 +;// +VPBDIV_SETUP EQU 0 +VPBDIV_Val EQU 0x00000000 + + +; Phase Locked Loop (PLL) definitions +PLL_BASE EQU 0xE01FC080 ; PLL Base Address +PLLCON_OFS EQU 0x00 ; PLL Control Offset +PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset +PLLSTAT_OFS EQU 0x08 ; PLL Status Offset +PLLFEED_OFS EQU 0x0C ; PLL Feed Offset +PLLCON_PLLE EQU (1<<0) ; PLL Enable +PLLCON_PLLC EQU (1<<1) ; PLL Connect +PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier +PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider +PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status + +;// PLL Setup +;// MSEL: PLL Multiplier Selection +;// <1-32><#-1> +;// M Value +;// PSEL: PLL Divider Selection +;// <0=> 1 <1=> 2 <2=> 4 <3=> 8 +;// P Value +;// +PLL_SETUP EQU 1 +PLLCFG_Val EQU 0x00000024 + + +; Memory Accelerator Module (MAM) definitions +MAM_BASE EQU 0xE01FC000 ; MAM Base Address +MAMCR_OFS EQU 0x00 ; MAM Control Offset +MAMTIM_OFS EQU 0x04 ; MAM Timing Offset + +;// MAM Setup +;// MAM Control +;// <0=> Disabled +;// <1=> Partially Enabled +;// <2=> Fully Enabled +;// Mode +;// MAM Timing +;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 +;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +;// Fetch Cycles +;// +MAM_SETUP EQU 1 +MAMCR_Val EQU 0x00000002 +MAMTIM_Val EQU 0x00000004 + + +; External Memory Controller (EMC) definitions +EMC_BASE EQU 0xFFE00000 ; EMC Base Address +BCFG0_OFS EQU 0x00 ; BCFG0 Offset +BCFG1_OFS EQU 0x04 ; BCFG1 Offset +BCFG2_OFS EQU 0x08 ; BCFG2 Offset +BCFG3_OFS EQU 0x0C ; BCFG3 Offset + +;// External Memory Controller (EMC) +EMC_SETUP EQU 0 + +;// Bank Configuration 0 (BCFG0) +;// IDCY: Idle Cycles <0-15> +;// WST1: Wait States 1 <0-31> +;// WST2: Wait States 2 <0-31> +;// RBLE: Read Byte Lane Enable +;// WP: Write Protect +;// BM: Burst ROM +;// MW: Memory Width <0=> 8-bit <1=> 16-bit +;// <2=> 32-bit <3=> Reserved +;// +BCFG0_SETUP EQU 0 +BCFG0_Val EQU 0x0000FBEF + +;// Bank Configuration 1 (BCFG1) +;// IDCY: Idle Cycles <0-15> +;// WST1: Wait States 1 <0-31> +;// WST2: Wait States 2 <0-31> +;// RBLE: Read Byte Lane Enable +;// WP: Write Protect +;// BM: Burst ROM +;// MW: Memory Width <0=> 8-bit <1=> 16-bit +;// <2=> 32-bit <3=> Reserved +;// +BCFG1_SETUP EQU 0 +BCFG1_Val EQU 0x0000FBEF + +;// Bank Configuration 2 (BCFG2) +;// IDCY: Idle Cycles <0-15> +;// WST1: Wait States 1 <0-31> +;// WST2: Wait States 2 <0-31> +;// RBLE: Read Byte Lane Enable +;// WP: Write Protect +;// BM: Burst ROM +;// MW: Memory Width <0=> 8-bit <1=> 16-bit +;// <2=> 32-bit <3=> Reserved +;// +BCFG2_SETUP EQU 0 +BCFG2_Val EQU 0x0000FBEF + +;// Bank Configuration 3 (BCFG3) +;// IDCY: Idle Cycles <0-15> +;// WST1: Wait States 1 <0-31> +;// WST2: Wait States 2 <0-31> +;// RBLE: Read Byte Lane Enable +;// WP: Write Protect +;// BM: Burst ROM +;// MW: Memory Width <0=> 8-bit <1=> 16-bit +;// <2=> 32-bit <3=> Reserved +;// +BCFG3_SETUP EQU 0 +BCFG3_Val EQU 0x0000FBEF + +;// End of EMC + + +; External Memory Pins definitions +PINSEL2 EQU 0xE002C014 ; PINSEL2 Address +PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3, + ; D0..31, A2..23, JTAG Pins + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + +Vectors LDR PC, Reset_Addr + LDR PC, Undef_Addr + LDR PC, SWI_Addr + LDR PC, PAbt_Addr + LDR PC, DAbt_Addr + NOP ; Reserved Vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B PAbt_Handler +DAbt_Handler B DAbt_Handler +FIQ_Handler B FIQ_Handler + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; Setup External Memory Pins + IF :DEF:EXTERNAL_MODE + LDR R0, =PINSEL2 + LDR R1, =PINSEL2_Val + STR R1, [R0] + ENDIF + + +; Setup External Memory Controller + IF EMC_SETUP <> 0 + LDR R0, =EMC_BASE + + IF BCFG0_SETUP <> 0 + LDR R1, =BCFG0_Val + STR R1, [R0, #BCFG0_OFS] + ENDIF + + IF BCFG1_SETUP <> 0 + LDR R1, =BCFG1_Val + STR R1, [R0, #BCFG1_OFS] + ENDIF + + IF BCFG2_SETUP <> 0 + LDR R1, =BCFG2_Val + STR R1, [R0, #BCFG2_OFS] + ENDIF + + IF BCFG3_SETUP <> 0 + LDR R1, =BCFG3_Val + STR R1, [R0, #BCFG3_OFS] + ENDIF + + ENDIF ; EMC_SETUP + + +; Setup VPBDIV + IF VPBDIV_SETUP <> 0 + LDR R0, =VPBDIV + LDR R1, =VPBDIV_Val + STR R1, [R0] + ENDIF + + +; Setup PLL + IF PLL_SETUP <> 0 + LDR R0, =PLL_BASE + MOV R1, #0xAA + MOV R2, #0x55 + +; Configure and Enable PLL + MOV R3, #PLLCFG_Val + STR R3, [R0, #PLLCFG_OFS] + MOV R3, #PLLCON_PLLE + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + +; Wait until PLL Locked +PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] + ANDS R3, R3, #PLLSTAT_PLOCK + BEQ PLL_Loop + +; Switch to PLL Clock + MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + ENDIF ; PLL_SETUP + + +; Setup MAM + IF MAM_SETUP <> 0 + LDR R0, =MAM_BASE + MOV R1, #MAMTIM_Val + STR R1, [R0, #MAMTIM_OFS] + MOV R1, #MAMCR_Val + STR R1, [R0, #MAMCR_OFS] + ENDIF ; MAM_SETUP + + +; Memory Mapping (when Interrupt Vectors are in RAM) +MEMMAP EQU 0xE01FC040 ; Memory Mapping Control + IF :DEF:REMAP + LDR R0, =MEMMAP + IF :DEF:EXTMEM_MODE + MOV R1, #3 + ELIF :DEF:RAM_MODE + MOV R1, #2 + ELSE + MOV R1, #1 + ENDIF + STR R1, [R0] + ENDIF + + +; Initialise Interrupt System +; ... + + +; Setup Stack for each mode + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ; SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; RT-Thread does not use user mode + ; MSR CPSR_c, #Mode_USR + IF :DEF:__MICROLIB + + EXPORT __initial_sp + + ELSE + + ; MOV SP, R0 + ; SUB SL, SP, #USR_Stack_Size + + ENDIF + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + IMPORT rt_hw_context_switch_interrupt_do + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + END diff --git a/libcpu/arm/lpc214x/startup_gcc.S b/libcpu/arm/lpc214x/startup_gcc.S index 1c25f3bd2ea0acee3764b0a59816750c718928fa..ce13d5708305cb0c30c6ce566f0db13e7fdd237b 100644 --- a/libcpu/arm/lpc214x/startup_gcc.S +++ b/libcpu/arm/lpc214x/startup_gcc.S @@ -1,312 +1,312 @@ - .extern main /* ÒýÈëÍⲿCÈë¿Ú */ - - .extern rt_interrupt_enter - .extern rt_interrupt_leave - .extern rt_thread_switch_interrupt_flag - .extern rt_interrupt_from_thread - .extern rt_interrupt_to_thread - .extern rt_hw_trap_irq - - .global start - .global endless_loop - .global rt_hw_context_switch_interrupt_do - - /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ - .set MODE_USR, 0x10 /* User Mode */ - .set MODE_FIQ, 0x11 /* FIQ Mode */ - .set MODE_IRQ, 0x12 /* IRQ Mode */ - .set MODE_SVC, 0x13 /* Supervisor Mode */ - .set MODE_ABT, 0x17 /* Abort Mode */ - .set MODE_UND, 0x1B /* Undefined Mode */ - .set MODE_SYS, 0x1F /* System Mode */ - - .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ - .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ - .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ - .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ - - /* VPBDIV definitions*/ - .equ VPBDIV, 0xE01FC100 - .set VPBDIV_VALUE, 0x00000000 - - /* Phase Locked Loop (PLL) definitions*/ - .equ PLL_BASE, 0xE01FC080 /* PLL Base Address */ - .equ PLLCON_OFS, 0x00 /* PLL Control Offset */ - .equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */ - .equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */ - .equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */ - .equ PLLCON_PLLE, (1<<0) /* PLL Enable */ - .equ PLLCON_PLLC, (1<<1) /* PLL Connect */ - .equ PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */ - .equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */ - .equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */ - .equ PLLCFG_Val, 0x00000024 /* MSEL: PLL Multiplier Selection, PSEL: PLL Divider Selection */ - - .equ MEMMAP, 0xE01FC040 /*Memory Mapping Control*/ - - - /* Memory Accelerator Module (MAM) definitions*/ - .equ MAM_BASE, 0xE01FC000 - .equ MAMCR_OFS, 0x00 - .equ MAMTIM_OFS, 0x04 - .equ MAMCR_Val, 0x00000002 - .equ MAMTIM_Val, 0x00000004 - - .equ VICIntEnClr, 0xFFFFF014 - .equ VICIntSelect, 0xFFFFF00C -/************* Ä¿±êÅäÖýáÊø *************/ - - -/* Setup the operating mode & stack.*/ -/* --------------------------------- */ - .global _reset -_reset: - .code 32 - .align 0 - -/************************* PLL_SETUP **********************************/ - ldr r0, =PLL_BASE - mov r1, #0xAA - mov r2, #0x55 - -/* Configure and Enable PLL */ - mov r3, #PLLCFG_Val - str r3, [r0, #PLLCFG_OFS] - mov r3, #PLLCON_PLLE - str r3, [r0, #PLLCON_OFS] - str r1, [r0, #PLLFEED_OFS] - str r2, [r0, #PLLFEED_OFS] - -/* Wait until PLL Locked */ -PLL_Locked_loop: - ldr r3, [r0, #PLLSTAT_OFS] - ands r3, r3, #PLLSTAT_PLOCK - beq PLL_Locked_loop - -/* Switch to PLL Clock */ - mov r3, #(PLLCON_PLLE|PLLCON_PLLC) - str r3, [r0, #PLLCON_OFS] - str r1, [r0, #PLLFEED_OFS] - str R2, [r0, #PLLFEED_OFS] -/************************* PLL_SETUP **********************************/ - -/************************ Setup VPBDIV ********************************/ - ldr r0, =VPBDIV - ldr r1, =VPBDIV_VALUE - str r1, [r0] -/************************ Setup VPBDIV ********************************/ - -/************** Setup MAM **************/ - ldr r0, =MAM_BASE - mov r1, #MAMTIM_Val - str r1, [r0, #MAMTIM_OFS] - mov r1, #MAMCR_Val - str r1, [r0, #MAMCR_OFS] -/************** Setup MAM **************/ - -/************************ setup stack *********************************/ - ldr r0, .undefined_stack_top - sub r0, r0, #4 - msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ - mov sp, r0 - - ldr r0, .abort_stack_top - sub r0, r0, #4 - msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ - mov sp, r0 - - ldr r0, .fiq_stack_top - sub r0, r0, #4 - msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ - mov sp, r0 - - ldr r0, .irq_stack_top - sub r0, r0, #4 - msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ - mov sp, r0 - - ldr r0, .svc_stack_top - sub r0, r0, #4 - msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ - mov sp, r0 -/************************ setup stack ********************************/ - - /* copy .data to SRAM */ - ldr r1, =_sidata /* .data start in image */ - ldr r2, =_edata /* .data end in image */ - ldr r3, =_sdata /* sram data start */ -data_loop: - ldr r0, [r1, #0] - str r0, [r3] - - add r1, r1, #4 - add r3, r3, #4 - - cmp r3, r2 /* check if data to clear */ - blo data_loop /* loop until done */ - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* enter C code */ - bl main - - .align 0 - .undefined_stack_top: - .word _undefined_stack_top - .abort_stack_top: - .word _abort_stack_top - .fiq_stack_top: - .word _fiq_stack_top - .irq_stack_top: - .word _irq_stack_top - .svc_stack_top: - .word _svc_stack_top -/*********************** END Clear BSS ******************************/ - -.section .init,"ax" -.code 32 -.align 0 -.globl _start -_start: - - ldr pc, __start /* reset - _start */ - ldr pc, _undf /* undefined - _undf */ - ldr pc, _swi /* SWI - _swi */ - ldr pc, _pabt /* program abort - _pabt */ - ldr pc, _dabt /* data abort - _dabt */ - .word 0xB8A06F58 /* reserved */ - ldr pc, __IRQ_Handler /* IRQ - read the VIC */ - ldr pc, _fiq /* FIQ - _fiq */ - -__start:.word _reset -_undf: .word __undf /* undefined */ -_swi: .word __swi /* SWI */ -_pabt: .word __pabt /* program abort */ -_dabt: .word __dabt /* data abort */ -temp1: .word 0 -__IRQ_Handler: .word IRQ_Handler -_fiq: .word __fiq /* FIQ */ - -__undf: b . /* undefined */ -__swi : b . -__pabt: b . /* program abort */ -__dabt: b . /* data abort */ -__fiq : b . /* FIQ */ - -/* IRQÈë¿Ú */ -IRQ_Handler : - stmfd sp!, {r0-r12,lr} /* ¶ÔR0 ¨C R12£¬LR¼Ä´æÆ÷ѹջ */ - bl rt_interrupt_enter /* ֪ͨRT-Thread½øÈëÖжÏģʽ */ - bl rt_hw_trap_irq /* ÏàÓ¦ÖжϷþÎñÀý³Ì´¦Àí */ - bl rt_interrupt_leave /* ; ֪ͨRT-ThreadÒªÀ뿪ÖжÏģʽ */ - - /* Èç¹ûÉèÖÃÁËrt_thread_switch_interrupt_flag£¬½øÐÐÖжÏÖеÄÏß³ÌÉÏÏÂÎÄ´¦Àí */ - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do /* ÖжÏÖÐÇл»·¢Éú */ - /* Èç¹ûÌøתÁË£¬½«²»»á»ØÀ´ */ - ldmfd sp!, {r0-r12,lr} /* »Ö¸´Õ» */ - subs pc, lr, #4 /* ´ÓIRQÖзµ»Ø */ - -/* -* void rt_hw_context_switch_interrupt_do(rt_base_t flag) -* ÖжϽáÊøºóµÄÉÏÏÂÎÄÇл» -*/ -rt_hw_context_switch_interrupt_do: - mov r1, #0 /* clear flag */ - /* Çå³þÖжÏÖÐÇл»±êÖ¾ */ - str r1, [r0] /* */ - - ldmfd sp!, {r0-r12,lr}/* reload saved registers */ - /* ÏȻָ´±»ÖжÏÏ̵߳ÄÉÏÏÂÎÄ */ - stmfd sp!, {r0-r3} /* save r0-r3 */ - /* ¶ÔR0 ¨C R3ѹջ£¬ÒòΪºóÃæ»áÓõ½ */ - mov r1, sp /* °Ñ´Ë´¦µÄÕ»Öµ±£´æµ½R1 */ - add sp, sp, #16 /* restore sp */ - /* »Ö¸´IRQµÄÕ»£¬ºóÃæ»áÌø³öIRQģʽ */ - sub r2, lr, #4 /* save old task's pc to r2 */ - /* ±£´æÇл»³öÏ̵߳ÄPCµ½R2 */ - - mrs r3, spsr /* disable interrupt ±£´æÖжÏÇ°µÄCPSRµ½R3¼Ä´æÆ÷ */ - /* »ñµÃSPSR¼Ä´æÆ÷Öµ */ - orr r0, r3, #I_BIT|F_BIT - msr spsr_c, r0 /* ¹Ø±ÕSPSRÖеÄIRQ/FIQÖÐ¶Ï */ - - ldr r0, =.+8 /* °Ñµ±Ç°µØÖ·+8ÔØÈëµ½R0¼Ä´æÆ÷ÖÐ switch to interrupted task's stack */ - movs pc, r0 /* Í˳öIRQģʽ£¬ÓÉÓÚSPSR±»ÉèÖóɹØÖжÏģʽ */ - /* ËùÒÔ´ÓIRQ·µ»Øºó£¬Öжϲ¢Ã»Óдò¿ª - ; R0¼Ä´æÆ÷ÖеÄλÖÃʵ¼Ê¾ÍÊÇÏÂÒ»ÌõÖ¸Á - ; ¼´PC¼ÌÐøÍùÏÂ×ß - ; ´Ëʱ - ; ģʽÒѾ­»»³ÉÖжÏÇ°µÄSVCģʽ£¬ - ; SP¼Ä´æÆ÷Ò²ÊÇSVCģʽϵÄÕ»¼Ä´æÆ÷ - ; R1±£´æIRQģʽϵÄÕ»Ö¸Õë - ; R2±£´æÇл»³öÏ̵߳ÄPC - ; R3±£´æÇл»³öÏ̵߳ÄCPSR */ - stmfd sp!, {r2} /* push old task's pc */ - /* ±£´æÇл»³öÈÎÎñµÄPC */ - stmfd sp!, {r4-r12,lr}/* push old task's lr,r12-r4 */ - /* ±£´æR4 ¨C R12£¬LR¼Ä´æÆ÷ */ - mov r4, r1 /* Special optimised code below */ - /* R1±£´æÓÐѹջR0 ¨C R3´¦µÄջλÖà */ - mov r5, r3 /* R3Çл»³öÏ̵߳ÄCPSR */ - ldmfd r4!, {r0-r3} /* »Ö¸´R0 ¨C R3 */ - stmfd sp!, {r0-r3} /* push old task's r3-r0 */ - /* R0 ¨C R3ѹջµ½Çл»³öÏß³Ì */ - stmfd sp!, {r5} /* push old task's psr */ - /* Çл»³öÏß³ÌCPSRѹջ */ - mrs r4, spsr - stmfd sp!, {r4} /* push old task's spsr */ - /* Çл»³öÏß³ÌSPSRѹջ */ - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] /* store sp in preempted tasks's TCB */ - /* ±£´æÇл»³öÏ̵߳ÄSPÖ¸Õë */ - - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] /* get new task's stack pointer */ - /* »ñµÃÇл»µ½Ï̵߳ÄÕ» */ - - ldmfd sp!, {r4} /* pop new task's spsr */ - /* »Ö¸´SPSR */ - msr SPSR_cxsf, r4 - ldmfd sp!, {r4} /* pop new task's psr */ - /* »Ö¸´CPSR */ - msr CPSR_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */ - /* »Ö¸´R0 ¨C R12£¬LR¼°PC¼Ä´æÆ÷ */ - -/* ´úÂë¼ÓÃܹ¦ÄÜ */ -#if defined(CODE_PROTECTION) -.org 0x01FC -.word 0x87654321 -#endif - + .extern main /* ÒýÈëÍⲿCÈë¿Ú */ + + .extern rt_interrupt_enter + .extern rt_interrupt_leave + .extern rt_thread_switch_interrupt_flag + .extern rt_interrupt_from_thread + .extern rt_interrupt_to_thread + .extern rt_hw_trap_irq + + .global start + .global endless_loop + .global rt_hw_context_switch_interrupt_do + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ + + /* VPBDIV definitions*/ + .equ VPBDIV, 0xE01FC100 + .set VPBDIV_VALUE, 0x00000000 + + /* Phase Locked Loop (PLL) definitions*/ + .equ PLL_BASE, 0xE01FC080 /* PLL Base Address */ + .equ PLLCON_OFS, 0x00 /* PLL Control Offset */ + .equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */ + .equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */ + .equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */ + .equ PLLCON_PLLE, (1<<0) /* PLL Enable */ + .equ PLLCON_PLLC, (1<<1) /* PLL Connect */ + .equ PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */ + .equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */ + .equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */ + .equ PLLCFG_Val, 0x00000024 /* MSEL: PLL Multiplier Selection, PSEL: PLL Divider Selection */ + + .equ MEMMAP, 0xE01FC040 /*Memory Mapping Control*/ + + + /* Memory Accelerator Module (MAM) definitions*/ + .equ MAM_BASE, 0xE01FC000 + .equ MAMCR_OFS, 0x00 + .equ MAMTIM_OFS, 0x04 + .equ MAMCR_Val, 0x00000002 + .equ MAMTIM_Val, 0x00000004 + + .equ VICIntEnClr, 0xFFFFF014 + .equ VICIntSelect, 0xFFFFF00C +/************* Ä¿±êÅäÖýáÊø *************/ + + +/* Setup the operating mode & stack.*/ +/* --------------------------------- */ + .global _reset +_reset: + .code 32 + .align 0 + +/************************* PLL_SETUP **********************************/ + ldr r0, =PLL_BASE + mov r1, #0xAA + mov r2, #0x55 + +/* Configure and Enable PLL */ + mov r3, #PLLCFG_Val + str r3, [r0, #PLLCFG_OFS] + mov r3, #PLLCON_PLLE + str r3, [r0, #PLLCON_OFS] + str r1, [r0, #PLLFEED_OFS] + str r2, [r0, #PLLFEED_OFS] + +/* Wait until PLL Locked */ +PLL_Locked_loop: + ldr r3, [r0, #PLLSTAT_OFS] + ands r3, r3, #PLLSTAT_PLOCK + beq PLL_Locked_loop + +/* Switch to PLL Clock */ + mov r3, #(PLLCON_PLLE|PLLCON_PLLC) + str r3, [r0, #PLLCON_OFS] + str r1, [r0, #PLLFEED_OFS] + str R2, [r0, #PLLFEED_OFS] +/************************* PLL_SETUP **********************************/ + +/************************ Setup VPBDIV ********************************/ + ldr r0, =VPBDIV + ldr r1, =VPBDIV_VALUE + str r1, [r0] +/************************ Setup VPBDIV ********************************/ + +/************** Setup MAM **************/ + ldr r0, =MAM_BASE + mov r1, #MAMTIM_Val + str r1, [r0, #MAMTIM_OFS] + mov r1, #MAMCR_Val + str r1, [r0, #MAMCR_OFS] +/************** Setup MAM **************/ + +/************************ setup stack *********************************/ + ldr r0, .undefined_stack_top + sub r0, r0, #4 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ + mov sp, r0 + + ldr r0, .abort_stack_top + sub r0, r0, #4 + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + + ldr r0, .fiq_stack_top + sub r0, r0, #4 + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + + ldr r0, .irq_stack_top + sub r0, r0, #4 + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + + ldr r0, .svc_stack_top + sub r0, r0, #4 + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 +/************************ setup stack ********************************/ + + /* copy .data to SRAM */ + ldr r1, =_sidata /* .data start in image */ + ldr r2, =_edata /* .data end in image */ + ldr r3, =_sdata /* sram data start */ +data_loop: + ldr r0, [r1, #0] + str r0, [r3] + + add r1, r1, #4 + add r3, r3, #4 + + cmp r3, r2 /* check if data to clear */ + blo data_loop /* loop until done */ + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + + + /* call C++ constructors of global objects */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r1} + b ctor_loop +ctor_end: + + /* enter C code */ + bl main + + .align 0 + .undefined_stack_top: + .word _undefined_stack_top + .abort_stack_top: + .word _abort_stack_top + .fiq_stack_top: + .word _fiq_stack_top + .irq_stack_top: + .word _irq_stack_top + .svc_stack_top: + .word _svc_stack_top +/*********************** END Clear BSS ******************************/ + +.section .init,"ax" +.code 32 +.align 0 +.globl _start +_start: + + ldr pc, __start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + .word 0xB8A06F58 /* reserved */ + ldr pc, __IRQ_Handler /* IRQ - read the VIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +__start:.word _reset +_undf: .word __undf /* undefined */ +_swi: .word __swi /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +temp1: .word 0 +__IRQ_Handler: .word IRQ_Handler +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__swi : b . +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq : b . /* FIQ */ + +/* IRQÈë¿Ú */ +IRQ_Handler : + stmfd sp!, {r0-r12,lr} /* ¶ÔR0 ¨C R12£¬LR¼Ä´æÆ÷ѹջ */ + bl rt_interrupt_enter /* ֪ͨRT-Thread½øÈëÖжÏģʽ */ + bl rt_hw_trap_irq /* ÏàÓ¦ÖжϷþÎñÀý³Ì´¦Àí */ + bl rt_interrupt_leave /* ; ֪ͨRT-ThreadÒªÀ뿪ÖжÏģʽ */ + + /* Èç¹ûÉèÖÃÁËrt_thread_switch_interrupt_flag£¬½øÐÐÖжÏÖеÄÏß³ÌÉÏÏÂÎÄ´¦Àí */ + ldr r0, =rt_thread_switch_interrupt_flag + ldr r1, [r0] + cmp r1, #1 + beq rt_hw_context_switch_interrupt_do /* ÖжÏÖÐÇл»·¢Éú */ + /* Èç¹ûÌøתÁË£¬½«²»»á»ØÀ´ */ + ldmfd sp!, {r0-r12,lr} /* »Ö¸´Õ» */ + subs pc, lr, #4 /* ´ÓIRQÖзµ»Ø */ + +/* +* void rt_hw_context_switch_interrupt_do(rt_base_t flag) +* ÖжϽáÊøºóµÄÉÏÏÂÎÄÇл» +*/ +rt_hw_context_switch_interrupt_do: + mov r1, #0 /* clear flag */ + /* Çå³þÖжÏÖÐÇл»±êÖ¾ */ + str r1, [r0] /* */ + + ldmfd sp!, {r0-r12,lr}/* reload saved registers */ + /* ÏȻָ´±»ÖжÏÏ̵߳ÄÉÏÏÂÎÄ */ + stmfd sp!, {r0-r3} /* save r0-r3 */ + /* ¶ÔR0 ¨C R3ѹջ£¬ÒòΪºóÃæ»áÓõ½ */ + mov r1, sp /* °Ñ´Ë´¦µÄÕ»Öµ±£´æµ½R1 */ + add sp, sp, #16 /* restore sp */ + /* »Ö¸´IRQµÄÕ»£¬ºóÃæ»áÌø³öIRQģʽ */ + sub r2, lr, #4 /* save old task's pc to r2 */ + /* ±£´æÇл»³öÏ̵߳ÄPCµ½R2 */ + + mrs r3, spsr /* disable interrupt ±£´æÖжÏÇ°µÄCPSRµ½R3¼Ä´æÆ÷ */ + /* »ñµÃSPSR¼Ä´æÆ÷Öµ */ + orr r0, r3, #I_BIT|F_BIT + msr spsr_c, r0 /* ¹Ø±ÕSPSRÖеÄIRQ/FIQÖÐ¶Ï */ + + ldr r0, =.+8 /* °Ñµ±Ç°µØÖ·+8ÔØÈëµ½R0¼Ä´æÆ÷ÖÐ switch to interrupted task's stack */ + movs pc, r0 /* Í˳öIRQģʽ£¬ÓÉÓÚSPSR±»ÉèÖóɹØÖжÏģʽ */ + /* ËùÒÔ´ÓIRQ·µ»Øºó£¬Öжϲ¢Ã»Óдò¿ª + ; R0¼Ä´æÆ÷ÖеÄλÖÃʵ¼Ê¾ÍÊÇÏÂÒ»ÌõÖ¸Á + ; ¼´PC¼ÌÐøÍùÏÂ×ß + ; ´Ëʱ + ; ģʽÒѾ­»»³ÉÖжÏÇ°µÄSVCģʽ£¬ + ; SP¼Ä´æÆ÷Ò²ÊÇSVCģʽϵÄÕ»¼Ä´æÆ÷ + ; R1±£´æIRQģʽϵÄÕ»Ö¸Õë + ; R2±£´æÇл»³öÏ̵߳ÄPC + ; R3±£´æÇл»³öÏ̵߳ÄCPSR */ + stmfd sp!, {r2} /* push old task's pc */ + /* ±£´æÇл»³öÈÎÎñµÄPC */ + stmfd sp!, {r4-r12,lr}/* push old task's lr,r12-r4 */ + /* ±£´æR4 ¨C R12£¬LR¼Ä´æÆ÷ */ + mov r4, r1 /* Special optimised code below */ + /* R1±£´æÓÐѹջR0 ¨C R3´¦µÄջλÖà */ + mov r5, r3 /* R3Çл»³öÏ̵߳ÄCPSR */ + ldmfd r4!, {r0-r3} /* »Ö¸´R0 ¨C R3 */ + stmfd sp!, {r0-r3} /* push old task's r3-r0 */ + /* R0 ¨C R3ѹջµ½Çл»³öÏß³Ì */ + stmfd sp!, {r5} /* push old task's psr */ + /* Çл»³öÏß³ÌCPSRѹջ */ + mrs r4, spsr + stmfd sp!, {r4} /* push old task's spsr */ + /* Çл»³öÏß³ÌSPSRѹջ */ + + ldr r4, =rt_interrupt_from_thread + ldr r5, [r4] + str sp, [r5] /* store sp in preempted tasks's TCB */ + /* ±£´æÇл»³öÏ̵߳ÄSPÖ¸Õë */ + + ldr r6, =rt_interrupt_to_thread + ldr r6, [r6] + ldr sp, [r6] /* get new task's stack pointer */ + /* »ñµÃÇл»µ½Ï̵߳ÄÕ» */ + + ldmfd sp!, {r4} /* pop new task's spsr */ + /* »Ö¸´SPSR */ + msr SPSR_cxsf, r4 + ldmfd sp!, {r4} /* pop new task's psr */ + /* »Ö¸´CPSR */ + msr CPSR_cxsf, r4 + + ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */ + /* »Ö¸´R0 ¨C R12£¬LR¼°PC¼Ä´æÆ÷ */ + +/* ´úÂë¼ÓÃܹ¦ÄÜ */ +#if defined(CODE_PROTECTION) +.org 0x01FC +.word 0x87654321 +#endif + diff --git a/libcpu/arm/lpc24xx/LPC24xx.h b/libcpu/arm/lpc24xx/LPC24xx.h index 01cbeec6696b7ab7be1dea284dc90b145f78b7a6..7c70fd1aa5815863edd244afc751599a7685a1c9 100644 --- a/libcpu/arm/lpc24xx/LPC24xx.h +++ b/libcpu/arm/lpc24xx/LPC24xx.h @@ -1,1201 +1,1201 @@ -/* - * File : LPC2478.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-12-11 xuxinming first version - */ - -#ifndef __LPC24xx_H -#define __LPC24xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define MCLK (72000000) - -/* Vectored Interrupt Controller (VIC) */ -#define VIC_BASE_ADDR 0xFFFFF000 -#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) -#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) -#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) -#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) -#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) -#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) -#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) -#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) -#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) -#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024)) - -#define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100)) -#define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104)) -#define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108)) -#define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C)) -#define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110)) -#define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114)) -#define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118)) -#define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C)) -#define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120)) -#define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124)) -#define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128)) -#define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C)) -#define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130)) -#define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134)) -#define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138)) -#define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C)) -#define VICVectAddr16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140)) -#define VICVectAddr17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144)) -#define VICVectAddr18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148)) -#define VICVectAddr19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C)) -#define VICVectAddr20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150)) -#define VICVectAddr21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154)) -#define VICVectAddr22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158)) -#define VICVectAddr23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C)) -#define VICVectAddr24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160)) -#define VICVectAddr25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164)) -#define VICVectAddr26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168)) -#define VICVectAddr27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C)) -#define VICVectAddr28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170)) -#define VICVectAddr29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174)) -#define VICVectAddr30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178)) -#define VICVectAddr31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C)) - -/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx, -these registers are known as "VICVectPriority(x)". */ -#define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200)) -#define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204)) -#define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208)) -#define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C)) -#define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210)) -#define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214)) -#define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218)) -#define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C)) -#define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220)) -#define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224)) -#define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228)) -#define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C)) -#define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230)) -#define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234)) -#define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238)) -#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C)) -#define VICVectCntl16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240)) -#define VICVectCntl17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244)) -#define VICVectCntl18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248)) -#define VICVectCntl19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C)) -#define VICVectCntl20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250)) -#define VICVectCntl21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254)) -#define VICVectCntl22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258)) -#define VICVectCntl23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C)) -#define VICVectCntl24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260)) -#define VICVectCntl25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264)) -#define VICVectCntl26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268)) -#define VICVectCntl27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C)) -#define VICVectCntl28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270)) -#define VICVectCntl29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274)) -#define VICVectCntl30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278)) -#define VICVectCntl31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C)) - -#define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00)) - - -/* Pin Connect Block */ -#define PINSEL_BASE_ADDR 0xE002C000 -#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) -#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) -#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) -#define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C)) -#define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10)) -#define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14)) -#define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18)) -#define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C)) -#define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20)) -#define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24)) -#define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28)) -#define PINSEL11 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x2C)) - -#define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40)) -#define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44)) -#define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48)) -#define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C)) -#define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50)) -#define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54)) -#define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58)) -#define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C)) -#define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60)) -#define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) - -/* General Purpose Input/Output (GPIO) */ -#define GPIO_BASE_ADDR 0xE0028000 -#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) -#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) -#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) -#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C)) -#define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10)) -#define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14)) -#define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18)) -#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) - -/* GPIO Interrupt Registers */ -#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) -#define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) -#define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) -#define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) -#define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) - -#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) -#define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) -#define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) -#define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) -#define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC)) - -#define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) - -#define PARTCFG_BASE_ADDR 0x3FFF8000 -#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) - -/* Fast I/O setup */ -#define FIO_BASE_ADDR 0x3FFFC000 -#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) -#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) -#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) -#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) -#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) - -#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) -#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) -#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) -#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) -#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) - -#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) -#define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) -#define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) -#define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) -#define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) - -#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) -#define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) -#define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) -#define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) -#define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) - -#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) -#define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) -#define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) -#define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) -#define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) - -/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ -#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) - -#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) -#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) -#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) -#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) - -#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) - -#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) -#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) -#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) -#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) -#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) - -#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) - -#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) - -#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) - -#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) -#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) -#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) -#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) - -#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) - -#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) -#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) -#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) -#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) -#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) - -#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) - -#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) - -#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) - -#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) -#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) -#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) -#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) -#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) - -#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) - -#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) -#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) -#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) -#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) -#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) - -#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) - -#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) - -#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) - -#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) -#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) -#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) -#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) -#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) - -#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) - -#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) -#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) -#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) -#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) -#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) - -#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) - -#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) - -#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) - -#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) -#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) -#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) -#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) -#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) - -#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) - -#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) -#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) -#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) -#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) -#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) - -#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) - -#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) - - -/* System Control Block(SCB) modules include Memory Accelerator Module, -Phase Locked Loop, VPB divider, Power Control, External Interrupt, -Reset, and Code Security/Debugging */ -#define SCB_BASE_ADDR 0xE01FC000 - -/* Memory Accelerator Module (MAM) */ -#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) -#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004)) -#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040)) - -/* Phase Locked Loop (PLL) */ -#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080)) -#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084)) -#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088)) -#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C)) - -/* Power Control */ -#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0)) -#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4)) - -/* Clock Divider */ -#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104)) -#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108)) -#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) -#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) -#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) - -/* External Interrupts */ -#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) -#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) -#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148)) -#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C)) - -/* Reset, reset source identification */ -#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180)) - -/* RSID, code security protection */ -#define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184)) - -/* AHB configuration */ -#define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188)) -#define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) - -/* System Controls and Status */ -#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) - -/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers -are for LPC24xx only. */ -#define STATIC_MEM0_BASE 0x80000000 -#define STATIC_MEM1_BASE 0x81000000 -#define STATIC_MEM2_BASE 0x82000000 -#define STATIC_MEM3_BASE 0x83000000 - -#define DYNAMIC_MEM0_BASE 0xA0000000 -#define DYNAMIC_MEM1_BASE 0xB0000000 -#define DYNAMIC_MEM2_BASE 0xC0000000 -#define DYNAMIC_MEM3_BASE 0xD0000000 - -/* External Memory Controller (EMC) */ -#define EMC_BASE_ADDR 0xFFE08000 -#define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) -#define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) -#define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) - -/* Dynamic RAM access registers */ -#define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020)) -#define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024)) -#define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028)) -#define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030)) -#define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034)) -#define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038)) -#define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C)) -#define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040)) -#define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044)) -#define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048)) -#define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C)) -#define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050)) -#define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054)) -#define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058)) - -#define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100)) -#define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104)) -#define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140)) -#define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144)) -#define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160)) -#define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164)) -#define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180)) -#define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184)) - -/* static RAM access registers */ -#define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200)) -#define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204)) -#define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208)) -#define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C)) -#define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210)) -#define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214)) -#define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218)) - -#define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220)) -#define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224)) -#define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228)) -#define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C)) -#define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230)) -#define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234)) -#define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238)) - -#define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240)) -#define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244)) -#define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248)) -#define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C)) -#define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250)) -#define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254)) -#define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258)) - -#define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260)) -#define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264)) -#define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268)) -#define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C)) -#define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270)) -#define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274)) -#define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278)) - -#define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) - - -/* Timer 0 */ -#define TMR0_BASE_ADDR 0xE0004000 -#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) -#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) -#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) -#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C)) -#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10)) -#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14)) -#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18)) -#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C)) -#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20)) -#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24)) -#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28)) -#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C)) -#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30)) -#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34)) -#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38)) -#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C)) -#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) - -/* Timer 1 */ -#define TMR1_BASE_ADDR 0xE0008000 -#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) -#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) -#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) -#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C)) -#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10)) -#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14)) -#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18)) -#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C)) -#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20)) -#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24)) -#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28)) -#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C)) -#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30)) -#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34)) -#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38)) -#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C)) -#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) - -/* Timer 2 */ -#define TMR2_BASE_ADDR 0xE0070000 -#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) -#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) -#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) -#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C)) -#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10)) -#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14)) -#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18)) -#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C)) -#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20)) -#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24)) -#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28)) -#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C)) -#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30)) -#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34)) -#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38)) -#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C)) -#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) - -/* Timer 3 */ -#define TMR3_BASE_ADDR 0xE0074000 -#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) -#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) -#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) -#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C)) -#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10)) -#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14)) -#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18)) -#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C)) -#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20)) -#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24)) -#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28)) -#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C)) -#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30)) -#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34)) -#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38)) -#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C)) -#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70)) - - -/* Pulse Width Modulator (PWM) */ -#define PWM0_BASE_ADDR 0xE0014000 -#define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) -#define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) -#define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) -#define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C)) -#define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10)) -#define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14)) -#define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18)) -#define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C)) -#define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20)) -#define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24)) -#define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28)) -#define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C)) -#define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30)) -#define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34)) -#define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38)) -#define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C)) -#define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40)) -#define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44)) -#define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48)) -#define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C)) -#define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) -#define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) - -#define PWM1_BASE_ADDR 0xE0018000 -#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) -#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) -#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) -#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C)) -#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10)) -#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14)) -#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18)) -#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C)) -#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20)) -#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24)) -#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28)) -#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C)) -#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30)) -#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34)) -#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38)) -#define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C)) -#define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40)) -#define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44)) -#define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48)) -#define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C)) -#define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50)) -#define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70)) - - -/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ -#define UART0_BASE_ADDR 0xE000C000 -#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) -#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) -#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) -#define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) -#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) -#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) -#define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) -#define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C)) -#define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14)) -#define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C)) -#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20)) -#define U0ICR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24)) -#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28)) -#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) - -/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ -#define UART1_BASE_ADDR 0xE0010000 -#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) -#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) -#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) -#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) -#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) -#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) -#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) -#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C)) -#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10)) -#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14)) -#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18)) -#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C)) -#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20)) -#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28)) -#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) - -/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ -#define UART2_BASE_ADDR 0xE0078000 -#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) -#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) -#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) -#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) -#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) -#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) -#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) -#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C)) -#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14)) -#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C)) -#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20)) -#define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24)) -#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28)) -#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) - -/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ -#define UART3_BASE_ADDR 0xE007C000 -#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) -#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) -#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) -#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) -#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) -#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) -#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) -#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C)) -#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14)) -#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C)) -#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20)) -#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24)) -#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28)) -#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) - -/* I2C Interface 0 */ -#define I2C0_BASE_ADDR 0xE001C000 -#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) -#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) -#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) -#define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C)) -#define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10)) -#define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14)) -#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) - -/* I2C Interface 1 */ -#define I2C1_BASE_ADDR 0xE005C000 -#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) -#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) -#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) -#define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C)) -#define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10)) -#define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14)) -#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) - -/* I2C Interface 2 */ -#define I2C2_BASE_ADDR 0xE0080000 -#define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) -#define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) -#define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) -#define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C)) -#define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10)) -#define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14)) -#define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) - -/* SPI0 (Serial Peripheral Interface 0) */ -#define SPI0_BASE_ADDR 0xE0020000 -#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) -#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) -#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) -#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C)) -#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) - -/* SSP0 Controller */ -#define SSP0_BASE_ADDR 0xE0068000 -#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) -#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) -#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) -#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C)) -#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10)) -#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14)) -#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18)) -#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C)) -#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20)) -#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) - -/* SSP1 Controller */ -#define SSP1_BASE_ADDR 0xE0030000 -#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) -#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) -#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) -#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C)) -#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10)) -#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14)) -#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18)) -#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C)) -#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20)) -#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24)) - - -/* Real Time Clock */ -#define RTC_BASE_ADDR 0xE0024000 -#define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) -#define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) -#define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) -#define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C)) -#define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10)) -#define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14)) -#define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18)) -#define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C)) -#define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20)) -#define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24)) -#define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28)) -#define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C)) -#define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30)) -#define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34)) -#define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38)) -#define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C)) -#define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40)) -#define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60)) -#define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64)) -#define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68)) -#define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C)) -#define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70)) -#define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74)) -#define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78)) -#define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C)) -#define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80)) -#define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84)) - - -/* A/D Converter 0 (AD0) */ -#define AD0_BASE_ADDR 0xE0034000 -#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) -#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) -#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) -#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10)) -#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14)) -#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18)) -#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C)) -#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20)) -#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24)) -#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28)) -#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C)) -#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30)) - - -/* D/A Converter */ -#define DAC_BASE_ADDR 0xE006C000 -#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) - - -/* Watchdog */ -#define WDG_BASE_ADDR 0xE0000000 -#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) -#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) -#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) -#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C)) -#define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) - -/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ -#define CAN_ACCEPT_BASE_ADDR 0xE003C000 -#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) -#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) -#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) -#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) -#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) -#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) -#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) -#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) - -#define CAN_CENTRAL_BASE_ADDR 0xE0040000 -#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) -#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) -#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) - -#define CAN1_BASE_ADDR 0xE0044000 -#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) -#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) -#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) -#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) -#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) -#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) -#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) -#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) -#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) -#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) -#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) -#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) - -#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) -#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) -#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) -#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) -#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) -#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) -#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) -#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) -#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) -#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) -#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) -#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) - -#define CAN2_BASE_ADDR 0xE0048000 -#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) -#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) -#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) -#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) -#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) -#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) -#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) -#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) -#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) -#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) -#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) -#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) - -#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) -#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) -#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) -#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) -#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) -#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) -#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) -#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) -#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) -#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) -#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) -#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) - - -/* MultiMedia Card Interface(MCI) Controller */ -#define MCI_BASE_ADDR 0xE008C000 -#define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) -#define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) -#define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) -#define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C)) -#define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10)) -#define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14)) -#define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18)) -#define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C)) -#define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20)) -#define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24)) -#define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28)) -#define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C)) -#define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30)) -#define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34)) -#define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38)) -#define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C)) -#define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40)) -#define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48)) -#define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80)) - - -/* I2S Interface Controller (I2S) */ -#define I2S_BASE_ADDR 0xE0088000 -#define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) -#define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) -#define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) -#define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C)) -#define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10)) -#define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14)) -#define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18)) -#define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C)) -#define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20)) -#define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24)) - - -/* General-purpose DMA Controller */ -#define DMA_BASE_ADDR 0xFFE04000 -#define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) -#define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) -#define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) -#define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C)) -#define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010)) -#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014)) -#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018)) -#define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C)) -#define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020)) -#define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024)) -#define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028)) -#define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C)) -#define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030)) -#define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034)) - -/* DMA channel 0 registers */ -#define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100)) -#define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104)) -#define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108)) -#define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C)) -#define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110)) - -/* DMA channel 1 registers */ -#define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120)) -#define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124)) -#define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128)) -#define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C)) -#define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130)) - - -/* USB Controller */ -#define USB_INT_BASE_ADDR 0xE01FC1C0 -#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ - -#define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) - -/* USB Device Interrupt Registers */ -#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00)) -#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04)) -#define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08)) -#define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C)) -#define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C)) - -/* USB Device Endpoint Interrupt Registers */ -#define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30)) -#define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34)) -#define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38)) -#define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C)) -#define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40)) - -/* USB Device Endpoint Realization Registers */ -#define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44)) -#define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48)) -#define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C)) - -/* USB Device Command Reagisters */ -#define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10)) -#define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14)) - -/* USB Device Data Transfer Registers */ -#define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18)) -#define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C)) -#define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20)) -#define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24)) -#define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28)) - -/* USB Device DMA Registers */ -#define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50)) -#define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54)) -#define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58)) -#define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80)) -#define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84)) -#define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88)) -#define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C)) -#define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90)) -#define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94)) -#define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0)) -#define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4)) -#define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8)) -#define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC)) -#define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0)) -#define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4)) -#define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8)) -#define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC)) -#define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0)) - -/* USB Host and OTG registers are for LPC24xx only */ -/* USB Host Controller */ -#define USBHC_BASE_ADDR 0xFFE0C000 -#define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) -#define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) -#define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) -#define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C)) -#define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10)) -#define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14)) -#define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18)) -#define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C)) -#define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20)) -#define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24)) -#define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28)) -#define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C)) -#define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30)) -#define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34)) -#define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38)) -#define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C)) -#define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40)) -#define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44)) -#define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48)) -#define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C)) -#define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50)) -#define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54)) -#define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) - -/* USB OTG Controller */ -#define USBOTG_BASE_ADDR 0xFFE0C100 -#define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) -#define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) -#define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) -#define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) -/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ -#define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) -#define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) - -#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 -#define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) -#define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) -#define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) -#define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08)) -#define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) -#define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) - -/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are -OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ -#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 -#define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) -#define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) - -/* Note: below three register name convention is for LPC23xx USB device only, match -with the spec. update in USB Device Section. */ -#define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) -#define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) -#define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) - -/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ -#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ -#define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ -#define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ -#define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ -#define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ -#define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ -#define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ -#define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ -#define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ -#define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ -#define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ -#define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ -#define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ -#define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ -#define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ - -#define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ -#define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ -#define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ - -#define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ -#define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ -#define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ -#define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ -#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ -#define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ -#define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ -#define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ -#define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ -#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ -#define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ -#define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ - -#define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ -#define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ -#define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ - -#define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ -#define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ - -#define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ -#define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ -#define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ - -#define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ -#define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ - -#define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ -#define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ -#define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ -#define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ - -#define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ -#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ - -/* LCD Controller registers */ -#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ -#define LCD_CFG (*(volatile unsigned long *)(0xE01FC1B8)) -#define LCD_TIMH (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000)) -#define LCD_TIMV (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004)) -#define LCD_POL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x008)) -#define LCD_LE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x00C)) -#define LCD_UPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x010)) -#define LCD_LPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x014)) -#define LCD_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x018)) -#define LCD_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x01C)) -#define LCD_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x020)) -#define LCD_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x024)) -#define LCD_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x028)) -#define LCD_UPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x02C)) -#define LCD_LPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x030)) -#define LCD_PAL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x200)) -#define CRSR_IMG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x800)) -#define CRSR_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC00)) -#define CRSR_CFG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC04)) -#define CRSR_PAL0 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC08)) -#define CRSR_PAL1 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC0C)) -#define CRSR_XY (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC10)) -#define CRSR_CLIP (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC14)) -#define CRSR_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC20)) -#define CRSR_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC24)) -#define CRSR_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC28)) -#define CRSR_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC2C)) - -struct rt_hw_register -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; -}; - -#ifdef __cplusplus -} -#endif - -#endif // __LPC24xx_H - +/* + * File : LPC2478.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-12-11 xuxinming first version + */ + +#ifndef __LPC24xx_H +#define __LPC24xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define MCLK (72000000) + +/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) +#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024)) + +#define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100)) +#define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104)) +#define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108)) +#define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C)) +#define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110)) +#define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114)) +#define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118)) +#define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C)) +#define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120)) +#define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124)) +#define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128)) +#define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C)) +#define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130)) +#define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134)) +#define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138)) +#define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C)) +#define VICVectAddr16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140)) +#define VICVectAddr17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144)) +#define VICVectAddr18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148)) +#define VICVectAddr19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C)) +#define VICVectAddr20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150)) +#define VICVectAddr21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154)) +#define VICVectAddr22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158)) +#define VICVectAddr23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C)) +#define VICVectAddr24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160)) +#define VICVectAddr25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164)) +#define VICVectAddr26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168)) +#define VICVectAddr27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C)) +#define VICVectAddr28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170)) +#define VICVectAddr29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174)) +#define VICVectAddr30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178)) +#define VICVectAddr31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C)) + +/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx, +these registers are known as "VICVectPriority(x)". */ +#define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200)) +#define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204)) +#define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208)) +#define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C)) +#define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210)) +#define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214)) +#define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218)) +#define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C)) +#define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220)) +#define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224)) +#define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228)) +#define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C)) +#define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230)) +#define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234)) +#define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238)) +#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C)) +#define VICVectCntl16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240)) +#define VICVectCntl17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244)) +#define VICVectCntl18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248)) +#define VICVectCntl19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C)) +#define VICVectCntl20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250)) +#define VICVectCntl21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254)) +#define VICVectCntl22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258)) +#define VICVectCntl23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C)) +#define VICVectCntl24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260)) +#define VICVectCntl25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264)) +#define VICVectCntl26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268)) +#define VICVectCntl27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C)) +#define VICVectCntl28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270)) +#define VICVectCntl29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274)) +#define VICVectCntl30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278)) +#define VICVectCntl31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C)) + +#define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00)) + + +/* Pin Connect Block */ +#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) +#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) +#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) +#define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C)) +#define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10)) +#define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14)) +#define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18)) +#define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C)) +#define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20)) +#define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24)) +#define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28)) +#define PINSEL11 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x2C)) + +#define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40)) +#define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44)) +#define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48)) +#define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C)) +#define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50)) +#define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54)) +#define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58)) +#define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C)) +#define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60)) +#define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) + +/* General Purpose Input/Output (GPIO) */ +#define GPIO_BASE_ADDR 0xE0028000 +#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) +#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) +#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) +#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C)) +#define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10)) +#define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14)) +#define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18)) +#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) + +/* GPIO Interrupt Registers */ +#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) +#define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) +#define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) +#define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) + +#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) +#define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) +#define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) +#define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC)) + +#define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) + +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) + +/* Fast I/O setup */ +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) +#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) +#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) +#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) +#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) + +#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) +#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) +#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) +#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) +#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) + +#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) +#define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) +#define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) +#define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) +#define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) + +#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) +#define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) +#define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) +#define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) +#define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) + +#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) +#define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) +#define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) +#define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) +#define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) + +#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) + +#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) + +#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) + +#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) +#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) + +#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) + +#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) + +#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) + +#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) + +#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) + +#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) + +#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) + + +/* System Control Block(SCB) modules include Memory Accelerator Module, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Reset, and Code Security/Debugging */ +#define SCB_BASE_ADDR 0xE01FC000 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) +#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004)) +#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080)) +#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084)) +#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088)) +#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C)) + +/* Power Control */ +#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0)) +#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4)) + +/* Clock Divider */ +#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104)) +#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108)) +#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) +#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) +#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) + +/* External Interrupts */ +#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) +#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) +#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148)) +#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C)) + +/* Reset, reset source identification */ +#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180)) + +/* RSID, code security protection */ +#define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184)) + +/* AHB configuration */ +#define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188)) +#define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) + +/* System Controls and Status */ +#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) + +/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers +are for LPC24xx only. */ +#define STATIC_MEM0_BASE 0x80000000 +#define STATIC_MEM1_BASE 0x81000000 +#define STATIC_MEM2_BASE 0x82000000 +#define STATIC_MEM3_BASE 0x83000000 + +#define DYNAMIC_MEM0_BASE 0xA0000000 +#define DYNAMIC_MEM1_BASE 0xB0000000 +#define DYNAMIC_MEM2_BASE 0xC0000000 +#define DYNAMIC_MEM3_BASE 0xD0000000 + +/* External Memory Controller (EMC) */ +#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) +#define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) +#define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) + +/* Dynamic RAM access registers */ +#define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020)) +#define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024)) +#define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028)) +#define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030)) +#define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034)) +#define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038)) +#define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C)) +#define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040)) +#define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044)) +#define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048)) +#define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C)) +#define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050)) +#define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054)) +#define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058)) + +#define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100)) +#define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104)) +#define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140)) +#define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144)) +#define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160)) +#define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164)) +#define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180)) +#define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184)) + +/* static RAM access registers */ +#define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200)) +#define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204)) +#define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208)) +#define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C)) +#define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210)) +#define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214)) +#define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218)) + +#define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220)) +#define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224)) +#define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228)) +#define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C)) +#define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230)) +#define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234)) +#define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238)) + +#define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240)) +#define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244)) +#define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248)) +#define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C)) +#define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250)) +#define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254)) +#define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258)) + +#define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260)) +#define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264)) +#define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268)) +#define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C)) +#define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270)) +#define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274)) +#define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278)) + +#define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) + + +/* Timer 0 */ +#define TMR0_BASE_ADDR 0xE0004000 +#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) +#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) +#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) +#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C)) +#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10)) +#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14)) +#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18)) +#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C)) +#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20)) +#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24)) +#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28)) +#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C)) +#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30)) +#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34)) +#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38)) +#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C)) +#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) + +/* Timer 1 */ +#define TMR1_BASE_ADDR 0xE0008000 +#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) +#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) +#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) +#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C)) +#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10)) +#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14)) +#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18)) +#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C)) +#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20)) +#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24)) +#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28)) +#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C)) +#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30)) +#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34)) +#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38)) +#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C)) +#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) + +/* Timer 2 */ +#define TMR2_BASE_ADDR 0xE0070000 +#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) +#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) +#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) +#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C)) +#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10)) +#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14)) +#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18)) +#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C)) +#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20)) +#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24)) +#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28)) +#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C)) +#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30)) +#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34)) +#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38)) +#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C)) +#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) + +/* Timer 3 */ +#define TMR3_BASE_ADDR 0xE0074000 +#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) +#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) +#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) +#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C)) +#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10)) +#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14)) +#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18)) +#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C)) +#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20)) +#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24)) +#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28)) +#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C)) +#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30)) +#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34)) +#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38)) +#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C)) +#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70)) + + +/* Pulse Width Modulator (PWM) */ +#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) +#define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) +#define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) +#define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C)) +#define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10)) +#define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14)) +#define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18)) +#define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C)) +#define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20)) +#define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24)) +#define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28)) +#define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C)) +#define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30)) +#define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34)) +#define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38)) +#define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C)) +#define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40)) +#define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44)) +#define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48)) +#define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C)) +#define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) +#define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) + +#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) +#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) +#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) +#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C)) +#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10)) +#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14)) +#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18)) +#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C)) +#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20)) +#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24)) +#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28)) +#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C)) +#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30)) +#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34)) +#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38)) +#define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C)) +#define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40)) +#define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44)) +#define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48)) +#define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C)) +#define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50)) +#define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70)) + + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define UART0_BASE_ADDR 0xE000C000 +#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) +#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) +#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) +#define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) +#define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C)) +#define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14)) +#define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C)) +#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20)) +#define U0ICR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24)) +#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28)) +#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define UART1_BASE_ADDR 0xE0010000 +#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) +#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) +#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) +#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) +#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C)) +#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10)) +#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14)) +#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18)) +#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C)) +#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20)) +#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28)) +#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#define UART2_BASE_ADDR 0xE0078000 +#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) +#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) +#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) +#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) +#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C)) +#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14)) +#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C)) +#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20)) +#define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24)) +#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28)) +#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#define UART3_BASE_ADDR 0xE007C000 +#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) +#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) +#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) +#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) +#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C)) +#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14)) +#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C)) +#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20)) +#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24)) +#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28)) +#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) + +/* I2C Interface 0 */ +#define I2C0_BASE_ADDR 0xE001C000 +#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) +#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) +#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) +#define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C)) +#define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10)) +#define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14)) +#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) + +/* I2C Interface 1 */ +#define I2C1_BASE_ADDR 0xE005C000 +#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) +#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) +#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) +#define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C)) +#define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10)) +#define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14)) +#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) + +/* I2C Interface 2 */ +#define I2C2_BASE_ADDR 0xE0080000 +#define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) +#define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) +#define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) +#define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C)) +#define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10)) +#define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14)) +#define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) +#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) +#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) +#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C)) +#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) + +/* SSP0 Controller */ +#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) +#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) +#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) +#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C)) +#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10)) +#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14)) +#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18)) +#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C)) +#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20)) +#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) + +/* SSP1 Controller */ +#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) +#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) +#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) +#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C)) +#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10)) +#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14)) +#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18)) +#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C)) +#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20)) +#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24)) + + +/* Real Time Clock */ +#define RTC_BASE_ADDR 0xE0024000 +#define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) +#define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) +#define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) +#define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C)) +#define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10)) +#define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14)) +#define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18)) +#define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C)) +#define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20)) +#define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24)) +#define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28)) +#define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C)) +#define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30)) +#define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34)) +#define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38)) +#define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C)) +#define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40)) +#define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60)) +#define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64)) +#define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68)) +#define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C)) +#define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70)) +#define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74)) +#define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78)) +#define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C)) +#define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80)) +#define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84)) + + +/* A/D Converter 0 (AD0) */ +#define AD0_BASE_ADDR 0xE0034000 +#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) +#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) +#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) +#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10)) +#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14)) +#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18)) +#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C)) +#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20)) +#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24)) +#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28)) +#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C)) +#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30)) + + +/* D/A Converter */ +#define DAC_BASE_ADDR 0xE006C000 +#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) + + +/* Watchdog */ +#define WDG_BASE_ADDR 0xE0000000 +#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) +#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) +#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) +#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C)) +#define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) + +#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) + +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) + +#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) + + +/* MultiMedia Card Interface(MCI) Controller */ +#define MCI_BASE_ADDR 0xE008C000 +#define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) +#define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) +#define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) +#define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C)) +#define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10)) +#define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14)) +#define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18)) +#define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C)) +#define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20)) +#define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24)) +#define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28)) +#define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C)) +#define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30)) +#define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34)) +#define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38)) +#define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C)) +#define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40)) +#define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48)) +#define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80)) + + +/* I2S Interface Controller (I2S) */ +#define I2S_BASE_ADDR 0xE0088000 +#define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) +#define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) +#define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) +#define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C)) +#define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10)) +#define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14)) +#define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18)) +#define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C)) +#define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20)) +#define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24)) + + +/* General-purpose DMA Controller */ +#define DMA_BASE_ADDR 0xFFE04000 +#define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) +#define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) +#define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) +#define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C)) +#define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010)) +#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014)) +#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018)) +#define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C)) +#define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020)) +#define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024)) +#define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028)) +#define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C)) +#define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030)) +#define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034)) + +/* DMA channel 0 registers */ +#define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100)) +#define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104)) +#define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108)) +#define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C)) +#define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110)) + +/* DMA channel 1 registers */ +#define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120)) +#define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124)) +#define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128)) +#define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C)) +#define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130)) + + +/* USB Controller */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ + +#define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00)) +#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04)) +#define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08)) +#define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C)) +#define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C)) + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30)) +#define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34)) +#define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38)) +#define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C)) +#define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40)) + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44)) +#define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48)) +#define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C)) + +/* USB Device Command Reagisters */ +#define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10)) +#define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14)) + +/* USB Device Data Transfer Registers */ +#define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18)) +#define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C)) +#define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20)) +#define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24)) +#define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28)) + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50)) +#define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54)) +#define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58)) +#define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80)) +#define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84)) +#define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88)) +#define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C)) +#define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90)) +#define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94)) +#define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0)) +#define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4)) +#define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8)) +#define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC)) +#define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0)) +#define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4)) +#define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8)) +#define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC)) +#define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0)) + +/* USB Host and OTG registers are for LPC24xx only */ +/* USB Host Controller */ +#define USBHC_BASE_ADDR 0xFFE0C000 +#define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) +#define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) +#define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) +#define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C)) +#define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10)) +#define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14)) +#define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18)) +#define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C)) +#define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20)) +#define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24)) +#define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28)) +#define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C)) +#define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30)) +#define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34)) +#define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38)) +#define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C)) +#define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40)) +#define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44)) +#define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48)) +#define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C)) +#define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50)) +#define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54)) +#define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) + +/* USB OTG Controller */ +#define USBOTG_BASE_ADDR 0xFFE0C100 +#define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) +#define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) +#define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) +#define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) +/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ +#define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) +#define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) + +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) +#define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08)) +#define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) +#define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) + +/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are +OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) +#define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) + +/* Note: below three register name convention is for LPC23xx USB device only, match +with the spec. update in USB Device Section. */ +#define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) +#define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) +#define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) + +/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ +#define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ +#define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ +#define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ +#define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ +#define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ +#define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ +#define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ +#define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ +#define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ +#define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ +#define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ +#define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ +#define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ + +#define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ +#define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ +#define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ + +#define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ +#define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ +#define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ +#define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ +#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ +#define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ +#define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ +#define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ +#define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ +#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ +#define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ +#define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ + +#define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ +#define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ +#define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ + +#define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ +#define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ + +#define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ +#define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ +#define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ + +#define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ +#define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ + +#define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ +#define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ +#define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ +#define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ + +#define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ +#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ + +/* LCD Controller registers */ +#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ +#define LCD_CFG (*(volatile unsigned long *)(0xE01FC1B8)) +#define LCD_TIMH (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000)) +#define LCD_TIMV (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004)) +#define LCD_POL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x008)) +#define LCD_LE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x00C)) +#define LCD_UPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x010)) +#define LCD_LPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x014)) +#define LCD_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x018)) +#define LCD_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x01C)) +#define LCD_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x020)) +#define LCD_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x024)) +#define LCD_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x028)) +#define LCD_UPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x02C)) +#define LCD_LPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x030)) +#define LCD_PAL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x200)) +#define CRSR_IMG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x800)) +#define CRSR_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC00)) +#define CRSR_CFG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC04)) +#define CRSR_PAL0 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC08)) +#define CRSR_PAL1 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC0C)) +#define CRSR_XY (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC10)) +#define CRSR_CLIP (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC14)) +#define CRSR_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC20)) +#define CRSR_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC24)) +#define CRSR_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC28)) +#define CRSR_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC2C)) + +struct rt_hw_register +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; +}; + +#ifdef __cplusplus +} +#endif + +#endif // __LPC24xx_H + diff --git a/libcpu/arm/lpc24xx/context_rvds.S b/libcpu/arm/lpc24xx/context_rvds.S index a867d7d552de1f0dbeabd0e53d82c5c326a039bf..ecd20e4bbe818933206afb1c9bfd9028250745f5 100644 --- a/libcpu/arm/lpc24xx/context_rvds.S +++ b/libcpu/arm/lpc24xx/context_rvds.S @@ -13,12 +13,12 @@ ; * 2011-07-22 Bernard added thumb mode porting ; */ -NOINT EQU 0xc0 ; disable interrupt in psr +NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 + AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -27,16 +27,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1 + MSR cpsr_c, r1 BX lr - ENDP + ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 + MSR cpsr_c, r0 BX lr ENDP @@ -50,24 +50,24 @@ rt_hw_context_switch PROC STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) STMFD sp!, {r0-r12, lr} ; push lr & register file - MRS r4, cpsr - TST lr, #0x01 - BEQ _ARM_MODE - ORR r4, r4, #0x20 ; it's thumb code - -_ARM_MODE + MRS r4, cpsr + TST lr, #0x01 + BEQ _ARM_MODE + ORR r4, r4, #0x20 ; it's thumb code + +_ARM_MODE STMFD sp!, {r4} ; push cpsr STR sp, [r0] ; store sp in preempted tasks TCB LDR sp, [r1] ; get new task stack pointer - LDMFD sp!, {r4} ; pop new task cpsr to spsr - MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task cpsr to spsr + MSR spsr_cxsf, r4 BIC r4, r4, #0x20 ; must be ARM mode MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP + ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -77,20 +77,20 @@ rt_hw_context_switch_to PROC EXPORT rt_hw_context_switch_to LDR sp, [r0] ; get new task stack pointer - LDMFD sp!, {r4} ; pop new task cpsr to spsr - MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task cpsr to spsr + MSR spsr_cxsf, r4 BIC r4, r4, #0x20 ; must be ARM mode MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP + ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread + IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -104,8 +104,8 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] + STR r1, [r2] BX lr - ENDP - + ENDP + END \ No newline at end of file diff --git a/libcpu/arm/lpc24xx/stack.c b/libcpu/arm/lpc24xx/stack.c index c07176a8742eaa14dce3a61ec1c6782401cc5a9b..ad6419da4bc16d6a02f8eed9dd5f3704c5f8ce3e 100644 --- a/libcpu/arm/lpc24xx/stack.c +++ b/libcpu/arm/lpc24xx/stack.c @@ -12,7 +12,7 @@ * 2008-12-11 XuXinming first version */ #include -#include "LPC24xx.h" +#include "LPC24xx.h" /** * @addtogroup LPC2478 @@ -49,13 +49,13 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, *(--stk) = 0; /* r3 */ *(--stk) = 0; /* r2 */ *(--stk) = 0; /* r1 */ - *(--stk) = (unsigned long)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ + *(--stk) = (unsigned long)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ /* return task's current stack address */ return (rt_uint8_t *)stk; diff --git a/libcpu/arm/lpc24xx/start_rvds.S b/libcpu/arm/lpc24xx/start_rvds.S index 162bfecfc2e3218169e34162ee9c3cce30800483..e49cf2df45bf03ecd77bd06ace0c5e883ccc1372 100644 --- a/libcpu/arm/lpc24xx/start_rvds.S +++ b/libcpu/arm/lpc24xx/start_rvds.S @@ -1,1632 +1,1632 @@ -;/*****************************************************************************/ -;/* LPC2400.S: Startup file for Philips LPC2400 device series */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2007-2008 Keil - An ARM Company. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - -;/* -; * The LPC2400.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock -; * (used mostly when clock is already initialized from script .ini -; * file). -; * -; * NO_EMC_SETUP: when set the startup code will not initialize -; * External Bus Controller. -; * -; * RAM_INTVEC: when set the startup code copies exception vectors -; * from on-chip Flash to on-chip RAM. -; * -; * REMAP: when set the startup code initializes the register MEMMAP -; * which overwrites the settings of the CPU configuration pins. The -; * startup and interrupt vectors are remapped from: -; * 0x00000000 default setting (not remapped) -; * 0x40000000 when RAM_MODE is used -; * 0x80000000 when EXTMEM_MODE is used -; * -; * EXTMEM_MODE: when set the device is configured for code execution -; * from external memory starting at address 0x80000000. -; * -; * RAM_MODE: when set the device is configured for code execution -; * from on-chip RAM starting at address 0x40000000. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - -;----------------------- Memory Definitions ------------------------------------ - -; Internal Memory Base Addresses -FLASH_BASE EQU 0x00000000 -RAM_BASE EQU 0x40000000 -EXTMEM_BASE EQU 0x80000000 - -; External Memory Base Addresses -STA_MEM0_BASE EQU 0x80000000 -STA_MEM1_BASE EQU 0x81000000 -STA_MEM2_BASE EQU 0x82000000 -STA_MEM3_BASE EQU 0x83000000 -DYN_MEM0_BASE EQU 0xA0000000 -DYN_MEM1_BASE EQU 0xB0000000 -DYN_MEM2_BASE EQU 0xC0000000 -DYN_MEM3_BASE EQU 0xD0000000 - - -;----------------------- Stack and Heap Definitions ---------------------------- - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000100 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000100 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size - -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -;----------------------- Clock Definitions ------------------------------------- - -; System Control Block (SCB) Module Definitions -SCB_BASE EQU 0xE01FC000 ; SCB Base Address -PLLCON_OFS EQU 0x80 ; PLL Control Offset -PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset -PLLSTAT_OFS EQU 0x88 ; PLL Status Offset -PLLFEED_OFS EQU 0x8C ; PLL Feed Offset -CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset -USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset -CLKSRCSEL_OFS EQU 0x10C ; Clock Source Sel Reg Offset -SCS_OFS EQU 0x1A0 ; Sys Control and Status Reg Offset -PCLKSEL0_OFS EQU 0x1A8 ; Periph Clock Sel Reg 0 Offset -PCLKSEL1_OFS EQU 0x1AC ; Periph Clock Sel Reg 0 Offset - -PCON_OFS EQU 0x0C0 ; Power Mode Control Reg Offset -PCONP_OFS EQU 0x0C4 ; Power Control for Periphs Reg Offset - -; Constants -OSCRANGE EQU (1<<4) ; Oscillator Range Select -OSCEN EQU (1<<5) ; Main oscillator Enable -OSCSTAT EQU (1<<6) ; Main Oscillator Status -PLLCON_PLLE EQU (1<<0) ; PLL Enable -PLLCON_PLLC EQU (1<<1) ; PLL Connect -PLLSTAT_M EQU (0x7FFF<<0) ; PLL M Value -PLLSTAT_N EQU (0xFF<<16) ; PLL N Value -PLLSTAT_PLOCK EQU (1<<26) ; PLL Lock Status - -;// Clock Setup -;// System Controls and Status Register (SYS) -;// OSCRANGE: Main Oscillator Range Select -;// <0=> 1 MHz to 20 MHz -;// <1=> 15 MHz to 24 MHz -;// OSCEN: Main Oscillator Enable -;// -;// -;// -;// PLL Clock Source Select Register (CLKSRCSEL) -;// CLKSRC: PLL Clock Source Selection -;// <0=> Internal RC oscillator -;// <1=> Main oscillator -;// <2=> RTC oscillator -;// -;// -;// PLL Configuration Register (PLLCFG) -;// PLL_clk = (2* M * PLL_clk_src) / N -;// MSEL: PLL Multiplier Selection -;// <1-32768><#-1> -;// M Value -;// NSEL: PLL Divider Selection -;// <1-256><#-1> -;// N Value -;// -;// -;// CPU Clock Configuration Register (CCLKCFG) -;// CCLKSEL: Divide Value for CPU Clock from PLL -;// <1-256><#-1> -;// -;// -;// USB Clock Configuration Register (USBCLKCFG) -;// USBSEL: Divide Value for USB Clock from PLL -;// <1-16><#-1> -;// -;// -;// Peripheral Clock Selection Register 0 (PCLKSEL0) -;// PCLK_WDT: Peripheral Clock Selection for WDT -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_UART0: Peripheral Clock Selection for UART0 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_UART1: Peripheral Clock Selection for UART1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_PWM0: Peripheral Clock Selection for PWM0 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_PWM1: Peripheral Clock Selection for PWM1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_I2C0: Peripheral Clock Selection for I2C0 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_SPI: Peripheral Clock Selection for SPI -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_RTC: Peripheral Clock Selection for RTC -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_SSP1: Peripheral Clock Selection for SSP1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_DAC: Peripheral Clock Selection for DAC -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_ADC: Peripheral Clock Selection for ADC -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_CAN1: Peripheral Clock Selection for CAN1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 6 -;// PCLK_CAN2: Peripheral Clock Selection for CAN2 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 6 -;// PCLK_ACF: Peripheral Clock Selection for ACF -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 6 -;// -;// -;// Peripheral Clock Selection Register 1 (PCLKSEL1) -;// PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_GPIO: Peripheral Clock Selection for GPIOs -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_PCB: Peripheral Clock Selection for Pin Connect Block -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_I2C1: Peripheral Clock Selection for I2C1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_SSP0: Peripheral Clock Selection for SSP0 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_UART2: Peripheral Clock Selection for UART2 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_UART3: Peripheral Clock Selection for UART3 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_I2C2: Peripheral Clock Selection for I2C2 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_I2S: Peripheral Clock Selection for I2S -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_MCI: Peripheral Clock Selection for MCI -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_SYSCON: Peripheral Clock Selection for System Control Block -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// -;// -CLOCK_SETUP EQU 1 -SCS_Val EQU 0x00000020 -CLKSRCSEL_Val EQU 0x00000001 -PLLCFG_Val EQU 0x0000000B -CCLKCFG_Val EQU 0x00000004 -USBCLKCFG_Val EQU 0x00000005 -PCLKSEL0_Val EQU 0x00000000 -PCLKSEL1_Val EQU 0x00000000 - - -;----------------------- Memory Accelerator Module (MAM) Definitions ----------- - -MAM_BASE EQU 0xE01FC000 ; MAM Base Address -MAMCR_OFS EQU 0x00 ; MAM Control Offset -MAMTIM_OFS EQU 0x04 ; MAM Timing Offset - -;// MAM Setup -;// MAM Control -;// <0=> Disabled -;// <1=> Partially Enabled -;// <2=> Fully Enabled -;// Mode -;// MAM Timing -;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 -;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 -;// Fetch Cycles -;// -MAM_SETUP EQU 1 -MAMCR_Val EQU 0x00000002 -MAMTIM_Val EQU 0x00000004 - - -;----------------------- Pin Connect Block Definitions ------------------------- - -PCB_BASE EQU 0xE002C000 ; PCB Base Address -PINSEL0_OFS EQU 0x00 ; PINSEL0 Address Offset -PINSEL1_OFS EQU 0x04 ; PINSEL1 Address Offset -PINSEL2_OFS EQU 0x08 ; PINSEL2 Address Offset -PINSEL3_OFS EQU 0x0C ; PINSEL3 Address Offset -PINSEL4_OFS EQU 0x10 ; PINSEL4 Address Offset -PINSEL5_OFS EQU 0x14 ; PINSEL5 Address Offset -PINSEL6_OFS EQU 0x18 ; PINSEL6 Address Offset -PINSEL7_OFS EQU 0x1C ; PINSEL7 Address Offset -PINSEL8_OFS EQU 0x20 ; PINSEL8 Address Offset -PINSEL9_OFS EQU 0x24 ; PINSEL9 Address Offset -PINSEL10_OFS EQU 0x28 ; PINSEL10 Address Offset - - -;----------------------- External Memory Controller (EMC) Definitons ----------- - -EMC_BASE EQU 0xFFE08000 ; EMC Base Address - -EMC_CTRL_OFS EQU 0x000 -EMC_STAT_OFS EQU 0x004 -EMC_CONFIG_OFS EQU 0x008 -EMC_DYN_CTRL_OFS EQU 0x020 -EMC_DYN_RFSH_OFS EQU 0x024 -EMC_DYN_RD_CFG_OFS EQU 0x028 -EMC_DYN_RP_OFS EQU 0x030 -EMC_DYN_RAS_OFS EQU 0x034 -EMC_DYN_SREX_OFS EQU 0x038 -EMC_DYN_APR_OFS EQU 0x03C -EMC_DYN_DAL_OFS EQU 0x040 -EMC_DYN_WR_OFS EQU 0x044 -EMC_DYN_RC_OFS EQU 0x048 -EMC_DYN_RFC_OFS EQU 0x04C -EMC_DYN_XSR_OFS EQU 0x050 -EMC_DYN_RRD_OFS EQU 0x054 -EMC_DYN_MRD_OFS EQU 0x058 -EMC_DYN_CFG0_OFS EQU 0x100 -EMC_DYN_RASCAS0_OFS EQU 0x104 -EMC_DYN_CFG1_OFS EQU 0x140 -EMC_DYN_RASCAS1_OFS EQU 0x144 -EMC_DYN_CFG2_OFS EQU 0x160 -EMC_DYN_RASCAS2_OFS EQU 0x164 -EMC_DYN_CFG3_OFS EQU 0x180 -EMC_DYN_RASCAS3_OFS EQU 0x184 -EMC_STA_CFG0_OFS EQU 0x200 -EMC_STA_WWEN0_OFS EQU 0x204 -EMC_STA_WOEN0_OFS EQU 0x208 -EMC_STA_WRD0_OFS EQU 0x20C -EMC_STA_WPAGE0_OFS EQU 0x210 -EMC_STA_WWR0_OFS EQU 0x214 -EMC_STA_WTURN0_OFS EQU 0x218 -EMC_STA_CFG1_OFS EQU 0x220 -EMC_STA_WWEN1_OFS EQU 0x224 -EMC_STA_WOEN1_OFS EQU 0x228 -EMC_STA_WRD1_OFS EQU 0x22C -EMC_STA_WPAGE1_OFS EQU 0x230 -EMC_STA_WWR1_OFS EQU 0x234 -EMC_STA_WTURN1_OFS EQU 0x238 -EMC_STA_CFG2_OFS EQU 0x240 -EMC_STA_WWEN2_OFS EQU 0x244 -EMC_STA_WOEN2_OFS EQU 0x248 -EMC_STA_WRD2_OFS EQU 0x24C -EMC_STA_WPAGE2_OFS EQU 0x250 -EMC_STA_WWR2_OFS EQU 0x254 -EMC_STA_WTURN2_OFS EQU 0x258 -EMC_STA_CFG3_OFS EQU 0x260 -EMC_STA_WWEN3_OFS EQU 0x264 -EMC_STA_WOEN3_OFS EQU 0x268 -EMC_STA_WRD3_OFS EQU 0x26C -EMC_STA_WPAGE3_OFS EQU 0x270 -EMC_STA_WWR3_OFS EQU 0x274 -EMC_STA_WTURN3_OFS EQU 0x278 -EMC_STA_EXT_W_OFS EQU 0x880 - -; Constants -NORMAL_CMD EQU (0x0 << 7) ; NORMAL Command -MODE_CMD EQU (0x1 << 7) ; MODE Command -PALL_CMD EQU (0x2 << 7) ; Precharge All Command -NOP_CMD EQU (0x3 << 7) ; NOP Command - -BUFEN_Const EQU (1 << 19) ; Buffer enable bit -EMC_PCONP_Const EQU (1 << 11) ; PCONP val to enable power for EMC - -; External Memory Pins definitions -; pin functions for SDRAM, NOR and NAND flash interfacing -EMC_PINSEL5_Val EQU 0x05010115 ; !CAS, !RAS, CLKOUT0, !DYCS0, DQMOUT0, DQMOUT1 -EMC_PINSEL6_Val EQU 0x55555555 ; D0 .. D15 -EMC_PINSEL8_Val EQU 0x55555555 ; A0 .. A15 -EMC_PINSEL9_Val EQU 0x50055555; ; A16 .. A23, !OE, !WE, !CS0, !CS1 - -;// External Memory Controller Setup (EMC) --------------------------------- -;// External Memory Controller Setup (EMC) -EMC_SETUP EQU 0 - -;// EMC Control Register (EMCControl) -;// Controls operation of the memory controller -;// L: Low-power mode enable -;// M: Address mirror enable -;// E: EMC enable -;// -EMC_CTRL_Val EQU 0x00000001 - -;// EMC Configuration Register (EMCConfig) -;// Configures operation of the memory controller -;// CCLK: CLKOUT ratio -;// <0=> 1:1 -;// <1=> 1:2 -;// Endian mode -;// <0=> Little-endian -;// <1=> Big-endian -;// -EMC_CONFIG_Val EQU 0x00000000 - -;// Dynamic Memory Interface Setup --------------------------------------- -;// Dynamic Memory Interface Setup -EMC_DYNAMIC_SETUP EQU 1 - -;// Dynamic Memory Refresh Timer Register (EMCDynamicRefresh) -;// Configures dynamic memory refresh operation -;// REFRESH: Refresh timer <0x000-0x7FF> -;// 0 = refresh disabled, 0x01-0x7FF: value * 16 CCLKS -;// -EMC_DYN_RFSH_Val EQU 0x0000001C - -;// Dynamic Memory Read Configuration Register (EMCDynamicReadConfig) -;// Configures the dynamic memory read strategy -;// RD: Read data strategy -;// <0=> Clock out delayed strategy -;// <1=> Command delayed strategy -;// <2=> Command delayed strategy plus one clock cycle -;// <3=> Command delayed strategy plus two clock cycles -;// -EMC_DYN_RD_CFG_Val EQU 0x00000001 - -;// Dynamic Memory Timings -;// Dynamic Memory Percentage Command Period Register (EMCDynamictRP) -;// tRP: Precharge command period <1-16> <#-1> -;// The delay is in EMCCLK cycles -;// This value is normally found in SDRAM data sheets as tRP -;// -;// Dynamic Memory Active to Precharge Command Period Register (EMCDynamictRAS) -;// tRAS: Active to precharge command period <1-16> <#-1> -;// The delay is in EMCCLK cycles -;// This value is normally found in SDRAM data sheets as tRAS -;// -;// Dynamic Memory Self-refresh Exit Time Register (EMCDynamictSREX) -;// tSREX: Self-refresh exit time <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tSREX, -;// for devices without this parameter you use the same value as tXSR -;// -;// Dynamic Memory Last Data Out to Active Time Register (EMCDynamictAPR) -;// tAPR: Last-data-out to active command time <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tAPR -;// -;// Dynamic Memory Data-in to Active Command Time Register (EMCDynamictDAL) -;// tDAL: Data-in to active command time <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tDAL or tAPW -;// -;// Dynamic Memory Write Recovery Time Register (EMCDynamictWR) -;// tWR: Write recovery time <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tWR, tDPL, tRWL, or tRDL -;// -;// Dynamic Memory Active to Active Command Period Register (EMCDynamictRC) -;// tRC: Active to active command period <1-32> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tRC -;// -;// Dynamic Memory Auto-refresh Period Register (EMCDynamictRFC) -;// tRFC: Auto-refresh period and auto-refresh to active command period <1-32> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tRFC or tRC -;// -;// Dynamic Memory Exit Self-refresh Register (EMCDynamictXSR) -;// tXSR: Exit self-refresh to active command time <1-32> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tXSR -;// -;// Dynamic Memory Active Bank A to Active Bank B Time Register (EMCDynamicRRD) -;// tRRD: Active bank A to active bank B latency <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tRRD -;// -;// Dynamic Memory Load Mode Register to Active Command Time (EMCDynamictMRD) -;// tMRD: Load mode register to active command time <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tMRD or tRSA -;// -;// -EMC_DYN_RP_Val EQU 0x00000002 -EMC_DYN_RAS_Val EQU 0x00000003 -EMC_DYN_SREX_Val EQU 0x00000007 -EMC_DYN_APR_Val EQU 0x00000002 -EMC_DYN_DAL_Val EQU 0x00000005 -EMC_DYN_WR_Val EQU 0x00000001 -EMC_DYN_RC_Val EQU 0x00000005 -EMC_DYN_RFC_Val EQU 0x00000005 -EMC_DYN_XSR_Val EQU 0x00000007 -EMC_DYN_RRD_Val EQU 0x00000001 -EMC_DYN_MRD_Val EQU 0x00000002 - -;// Configure External Bus Behaviour for Dynamic CS0 Area -EMC_DYNCS0_SETUP EQU 1 - -;// Dynamic Memory Configuration Register (EMCDynamicConfig0) -;// Defines the configuration information for the dynamic memory CS0 -;// P: Write protect -;// B: Buffer enable -;// AM 14: External bus data width -;// <0=> 16 bit -;// <1=> 32 bit -;// AM 12: External bus memory type -;// <0=> High-performance -;// <1=> Low-power SDRAM -;// AM 11..7: External bus address mapping (Row, Bank, Column) -;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 -;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 -;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 -;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 -;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 -;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 -;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 -;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 -;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 -;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 -;// MD: Memory device -;// <0=> SDRAM -;// <1=> Low-power SDRAM -;// <2=> Micron SyncFlash -;// -EMC_DYN_CFG0_Val EQU 0x00080680 - -;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS0) -;// Controls the RAS and CAS latencies for the dynamic memory CS0 -;// CAS: CAS latency -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// RAS: RAS latency (active to read/write delay) -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// -EMC_DYN_RASCAS0_Val EQU 0x00000303 - -;// End of Dynamic Setup for CS0 Area - - -;// Configure External Bus Behaviour for Dynamic CS1 Area -EMC_DYNCS1_SETUP EQU 0 - -;// Dynamic Memory Configuration Register (EMCDynamicConfig1) -;// Defines the configuration information for the dynamic memory CS1 -;// P: Write protect -;// B: Buffer enable -;// AM 14: External bus data width -;// <0=> 16 bit -;// <1=> 32 bit -;// AM 12: External bus memory type -;// <0=> High-performance -;// <1=> Low-power SDRAM -;// AM 11..7: External bus address mapping (Row, Bank, Column) -;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 -;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 -;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 -;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 -;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 -;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 -;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 -;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 -;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 -;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 -;// MD: Memory device -;// <0=> SDRAM -;// <1=> Low-power SDRAM -;// <2=> Micron SyncFlash -;// -EMC_DYN_CFG1_Val EQU 0x00000000 - -;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS1) -;// Controls the RAS and CAS latencies for the dynamic memory CS1 -;// CAS: CAS latency -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// RAS: RAS latency (active to read/write delay) -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// -EMC_DYN_RASCAS1_Val EQU 0x00000303 - -;// End of Dynamic Setup for CS1 Area - -;// Configure External Bus Behaviour for Dynamic CS2 Area -EMC_DYNCS2_SETUP EQU 0 - -;// Dynamic Memory Configuration Register (EMCDynamicConfig2) -;// Defines the configuration information for the dynamic memory CS2 -;// P: Write protect -;// B: Buffer enable -;// AM 14: External bus data width -;// <0=> 16 bit -;// <1=> 32 bit -;// AM 12: External bus memory type -;// <0=> High-performance -;// <1=> Low-power SDRAM -;// AM 11..7: External bus address mapping (Row, Bank, Column) -;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 -;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 -;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 -;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 -;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 -;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 -;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 -;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 -;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 -;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 -;// MD: Memory device -;// <0=> SDRAM -;// <1=> Low-power SDRAM -;// <2=> Micron SyncFlash -;// -EMC_DYN_CFG2_Val EQU 0x00000000 - -;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS2) -;// Controls the RAS and CAS latencies for the dynamic memory CS2 -;// CAS: CAS latency -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// RAS: RAS latency (active to read/write delay) -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// -EMC_DYN_RASCAS2_Val EQU 0x00000303 - -;// End of Dynamic Setup for CS2 Area - -;// Configure External Bus Behaviour for Dynamic CS3 Area -EMC_DYNCS3_SETUP EQU 0 - -;// Dynamic Memory Configuration Register (EMCDynamicConfig3) -;// Defines the configuration information for the dynamic memory CS3 -;// P: Write protect -;// B: Buffer enable -;// AM 14: External bus data width -;// <0=> 16 bit -;// <1=> 32 bit -;// AM 12: External bus memory type -;// <0=> High-performance -;// <1=> Low-power SDRAM -;// AM 11..7: External bus address mapping (Row, Bank, Column) -;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 -;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 -;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 -;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 -;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 -;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 -;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 -;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 -;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 -;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 -;// MD: Memory device -;// <0=> SDRAM -;// <1=> Low-power SDRAM -;// <2=> Micron SyncFlash -;// -EMC_DYN_CFG3_Val EQU 0x00000000 - -;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS3) -;// Controls the RAS and CAS latencies for the dynamic memory CS3 -;// CAS: CAS latency -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// RAS: RAS latency (active to read/write delay) -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// -EMC_DYN_RASCAS3_Val EQU 0x00000303 - -;// End of Dynamic Setup for CS3 Area - -;// End of Dynamic Setup - -;// Static Memory Interface Setup ---------------------------------------- -;// Static Memory Interface Setup -EMC_STATIC_SETUP EQU 1 - -;// Configure External Bus Behaviour for Static CS0 Area --------------- -;// Configure External Bus Behaviour for Static CS0 Area -EMC_STACS0_SETUP EQU 1 - -;// Static Memory Configuration Register (EMCStaticConfig0) -;// Defines the configuration information for the static memory CS0 -;// WP: Write protect -;// B: Buffer enable -;// EW: Extended wait enable -;// PB: Byte lane state -;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW -;// <1=> For reads BLSn are LOW, for writes BLSn are LOW -;// PC: Chip select polarity -;// <0=> Active LOW chip select -;// <1=> Active HIGH chip select -;// PM: Page mode enable -;// MW: Memory width -;// <0=> 8 bit -;// <1=> 16 bit -;// <2=> 32 bit -;// -EMC_STA_CFG0_Val EQU 0x00000081 - -;// Static Memory Write Enable Delay Register (EMCStaticWaitWen0) -;// Selects the delay from CS0 to write enable -;// WAITWEN: Wait write enable <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WWEN0_Val EQU 0x00000002 - -;// Static Memory Output Enable Delay register (EMCStaticWaitOen0) -;// Selects the delay from CS0 or address change, whichever is later, to output enable -;// WAITOEN: Wait output enable <0-15> -;// The delay is in CCLK cycles -;// -EMC_STA_WOEN0_Val EQU 0x00000002 - -;// Static Memory Read Delay Register (EMCStaticWaitRd0) -;// Selects the delay from CS0 to a read access -;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WRD0_Val EQU 0x0000001F - -;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) -;// Selects the delay for asynchronous page mode sequential accesses for CS0 -;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WPAGE0_Val EQU 0x0000001F - -;// Static Memory Write Delay Register (EMCStaticWaitWr0) -;// Selects the delay from CS0 to a write access -;// WAITWR: Write wait states <2-33> <#-2> -;// The delay is in CCLK cycles -;// -EMC_STA_WWR0_Val EQU 0x0000001F - -;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn0) -;// Selects the number of bus turnaround cycles for CS0 -;// WAITTURN: Bus turnaround cycles <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WTURN0_Val EQU 0x0000000F - -;// End of Static Setup for Static CS0 Area - -;// Configure External Bus Behaviour for Static CS1 Area --------------- -;// Configure External Bus Behaviour for Static CS1 Area -EMC_STACS1_SETUP EQU 0 - -;// Static Memory Configuration Register (EMCStaticConfig1) -;// Defines the configuration information for the static memory CS1 -;// WP: Write protect -;// B: Buffer enable -;// EW: Extended wait enable -;// PB: Byte lane state -;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW -;// <1=> For reads BLSn are LOW, for writes BLSn are LOW -;// PC: Chip select polarity -;// <0=> Active LOW chip select -;// <1=> Active HIGH chip select -;// PM: Page mode enable -;// MW: Memory width -;// <0=> 8 bit -;// <1=> 16 bit -;// <2=> 32 bit -;// -EMC_STA_CFG1_Val EQU 0x00000000 - -;// Static Memory Write Enable Delay Register (EMCStaticWaitWen1) -;// Selects the delay from CS1 to write enable -;// WAITWEN: Wait write enable <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WWEN1_Val EQU 0x00000000 - -;// Static Memory Output Enable Delay register (EMCStaticWaitOen1) -;// Selects the delay from CS1 or address change, whichever is later, to output enable -;// WAITOEN: Wait output enable <0-15> -;// The delay is in CCLK cycles -;// -EMC_STA_WOEN1_Val EQU 0x00000000 - -;// Static Memory Read Delay Register (EMCStaticWaitRd1) -;// Selects the delay from CS1 to a read access -;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WRD1_Val EQU 0x0000001F - -;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) -;// Selects the delay for asynchronous page mode sequential accesses for CS1 -;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WPAGE1_Val EQU 0x0000001F - -;// Static Memory Write Delay Register (EMCStaticWaitWr1) -;// Selects the delay from CS1 to a write access -;// WAITWR: Write wait states <2-33> <#-2> -;// The delay is in CCLK cycles -;// -EMC_STA_WWR1_Val EQU 0x0000001F - -;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn1) -;// Selects the number of bus turnaround cycles for CS1 -;// WAITTURN: Bus turnaround cycles <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WTURN1_Val EQU 0x0000000F - -;// End of Static Setup for Static CS1 Area - -;// Configure External Bus Behaviour for Static CS2 Area --------------- -;// Configure External Bus Behaviour for Static CS2 Area -EMC_STACS2_SETUP EQU 0 - -;// Static Memory Configuration Register (EMCStaticConfig2) -;// Defines the configuration information for the static memory CS2 -;// WP: Write protect -;// B: Buffer enable -;// EW: Extended wait enable -;// PB: Byte lane state -;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW -;// <1=> For reads BLSn are LOW, for writes BLSn are LOW -;// PC: Chip select polarity -;// <0=> Active LOW chip select -;// <1=> Active HIGH chip select -;// PM: Page mode enable -;// MW: Memory width -;// <0=> 8 bit -;// <1=> 16 bit -;// <2=> 32 bit -;// -EMC_STA_CFG2_Val EQU 0x00000000 - -;// Static Memory Write Enable Delay Register (EMCStaticWaitWen2) -;// Selects the delay from CS2 to write enable -;// WAITWEN: Wait write enable <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WWEN2_Val EQU 0x00000000 - -;// Static Memory Output Enable Delay register (EMCStaticWaitOen2) -;// Selects the delay from CS2 or address change, whichever is later, to output enable -;// WAITOEN: Wait output enable <0-15> -;// The delay is in CCLK cycles -;// -EMC_STA_WOEN2_Val EQU 0x00000000 - -;// Static Memory Read Delay Register (EMCStaticWaitRd2) -;// Selects the delay from CS2 to a read access -;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WRD2_Val EQU 0x0000001F - -;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage2) -;// Selects the delay for asynchronous page mode sequential accesses for CS2 -;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WPAGE2_Val EQU 0x0000001F - -;// Static Memory Write Delay Register (EMCStaticWaitWr2) -;// Selects the delay from CS2 to a write access -;// WAITWR: Write wait states <2-33> <#-2> -;// The delay is in CCLK cycles -;// -EMC_STA_WWR2_Val EQU 0x0000001F - -;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn2) -;// Selects the number of bus turnaround cycles for CS2 -;// WAITTURN: Bus turnaround cycles <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WTURN2_Val EQU 0x0000000F - -;// End of Static Setup for Static CS2 Area - -;// Configure External Bus Behaviour for Static CS3 Area --------------- -;// Configure External Bus Behaviour for Static CS3 Area -EMC_STACS3_SETUP EQU 0 - -;// Static Memory Configuration Register (EMCStaticConfig3) -;// Defines the configuration information for the static memory CS3 -;// WP: Write protect -;// B: Buffer enable -;// EW: Extended wait enable -;// PB: Byte lane state -;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW -;// <1=> For reads BLSn are LOW, for writes BLSn are LOW -;// PC: Chip select polarity -;// <0=> Active LOW chip select -;// <1=> Active HIGH chip select -;// PM: Page mode enable -;// MW: Memory width -;// <0=> 8 bit -;// <1=> 16 bit -;// <2=> 32 bit -;// -EMC_STA_CFG3_Val EQU 0x00000000 - -;// Static Memory Write Enable Delay Register (EMCStaticWaitWen3) -;// Selects the delay from CS3 to write enable -;// WAITWEN: Wait write enable <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WWEN3_Val EQU 0x00000000 - -;// Static Memory Output Enable Delay register (EMCStaticWaitOen3) -;// Selects the delay from CS3 or address change, whichever is later, to output enable -;// WAITOEN: Wait output enable <0-15> -;// The delay is in CCLK cycles -;// -EMC_STA_WOEN3_Val EQU 0x00000000 - -;// Static Memory Read Delay Register (EMCStaticWaitRd3) -;// Selects the delay from CS3 to a read access -;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WRD3_Val EQU 0x0000001F - -;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage3) -;// Selects the delay for asynchronous page mode sequential accesses for CS3 -;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WPAGE3_Val EQU 0x0000001F - -;// Static Memory Write Delay Register (EMCStaticWaitWr3) -;// Selects the delay from CS3 to a write access -;// WAITWR: Write wait states <2-33> <#-2> -;// The delay is in CCLK cycles -;// -EMC_STA_WWR3_Val EQU 0x0000001F - -;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn3) -;// Selects the number of bus turnaround cycles for CS3 -;// WAITTURN: Bus turnaround cycles <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WTURN3_Val EQU 0x0000000F - -;// End of Static Setup for Static CS3 Area - -;// Static Memory Extended Wait Register (EMCStaticExtendedWait) -;// Time long static memory read and write transfers -;// EXTENDEDWAIT: Extended wait time out <0-1023> -;// The delay is in (16 * CCLK) cycles -;// -EMC_STA_EXT_W_Val EQU 0x00000000 - -;// End of Static Setup - -;// End of EMC Setup - - - PRESERVE8 - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC, Reset_Addr - LDR PC, Undef_Addr - LDR PC, SWI_Addr - LDR PC, PAbt_Addr - LDR PC, DAbt_Addr - NOP ; Reserved Vector - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - - -; Exception Handler - IMPORT rt_hw_trap_udef - IMPORT rt_hw_trap_swi - IMPORT rt_hw_trap_pabt - IMPORT rt_hw_trap_dabt - IMPORT rt_hw_trap_fiq - -; Prepare Fatal Context - MACRO - prepare_fatal - STMFD sp!, {r0-r3} - MOV r1, sp - ADD sp, sp, #16 - SUB r2, lr, #4 - MRS r3, spsr - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC - - STMFD sp!, {r0} ; old r0 - ; get sp - ADD r0, sp, #4 - STMFD sp!, {r3} ; cpsr - STMFD sp!, {r2} ; pc - STMFD sp!, {lr} ; lr - STMFD sp!, {r0} ; sp - STMFD sp!, {r4-r12} - - MOV r4, r1 - - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} - - MOV r0, sp - MEND - -Undef_Handler - prepare_fatal - BL rt_hw_trap_irq - B . - -SWI_Handler - prepare_fatal - BL rt_hw_trap_swi - B . - -PAbt_Handler - prepare_fatal - BL rt_hw_trap_pabt - B . - -DAbt_Handler - prepare_fatal - BL rt_hw_trap_dabt - B . - -FIQ_Handler - prepare_fatal - BL rt_hw_trap_fiq - B . - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Clock Setup ------------------------------------------------------------------ - - IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) - LDR R0, =SCB_BASE - MOV R1, #0xAA - MOV R2, #0x55 - -; Configure and Enable PLL - LDR R3, =SCS_Val ; Enable main oscillator - STR R3, [R0, #SCS_OFS] - - IF (SCS_Val:AND:OSCEN) != 0 -OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize - ANDS R3, R3, #OSCSTAT - BEQ OSC_Loop - ENDIF - - LDR R3, =CLKSRCSEL_Val ; Select PLL source clock - STR R3, [R0, #CLKSRCSEL_OFS] - LDR R3, =PLLCFG_Val - STR R3, [R0, #PLLCFG_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - MOV R3, #PLLCON_PLLE - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - - IF (CLKSRCSEL_Val:AND:3) != 2 -; Wait until PLL Locked (if source is not RTC oscillator) -PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] - ANDS R3, R3, #PLLSTAT_PLOCK - BEQ PLL_Loop - ELSE -; Wait at least 200 cycles (if source is RTC oscillator) - MOV R3, #(200/4) -PLL_Loop SUBS R3, R3, #1 - BNE PLL_Loop - ENDIF - -M_N_Lock LDR R3, [R0, #PLLSTAT_OFS] - LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N) - AND R3, R3, R4 - LDR R4, =PLLCFG_Val - EORS R3, R3, R4 - BNE M_N_Lock - -; Setup CPU clock divider - MOV R3, #CCLKCFG_Val - STR R3, [R0, #CCLKCFG_OFS] - -; Setup USB clock divider - LDR R3, =USBCLKCFG_Val - STR R3, [R0, #USBCLKCFG_OFS] - -; Setup Peripheral Clock - LDR R3, =PCLKSEL0_Val - STR R3, [R0, #PCLKSEL0_OFS] - LDR R3, =PCLKSEL1_Val - STR R3, [R0, #PCLKSEL1_OFS] - -; Switch to PLL Clock - MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - ENDIF ; CLOCK_SETUP - - -; Setup Memory Accelerator Module ---------------------------------------------- - - IF MAM_SETUP != 0 - LDR R0, =MAM_BASE - MOV R1, #MAMTIM_Val - STR R1, [R0, #MAMTIM_OFS] - MOV R1, #MAMCR_Val - STR R1, [R0, #MAMCR_OFS] - ENDIF ; MAM_SETUP - - -; Setup External Memory Controller --------------------------------------------- - - IF (:LNOT:(:DEF:NO_EMC_SETUP)):LAND:(EMC_SETUP != 0) - LDR R0, =EMC_BASE - LDR R1, =SCB_BASE - LDR R2, =PCB_BASE - - LDR R4, =EMC_PCONP_Const ; Enable EMC - LDR R3, [R1, #PCONP_OFS] - ORR R4, R4, R3 - STR R4, [R1, #PCONP_OFS] - - LDR R4, =EMC_CTRL_Val - STR R4, [R0, #EMC_CTRL_OFS] - LDR R4, =EMC_CONFIG_Val - STR R4, [R0, #EMC_CONFIG_OFS] - -; Setup pin functions for External Bus functionality - LDR R4, =EMC_PINSEL5_Val - STR R4, [R2, #PINSEL5_OFS] - LDR R4, =EMC_PINSEL6_Val - STR R4, [R2, #PINSEL6_OFS] - LDR R4, =EMC_PINSEL8_Val - STR R4, [R2, #PINSEL8_OFS] - LDR R4, =EMC_PINSEL9_Val - STR R4, [R2, #PINSEL9_OFS] - -; Setup Dynamic Memory Interface - IF (EMC_DYNAMIC_SETUP != 0) - - LDR R4, =EMC_DYN_RP_Val - STR R4, [R0, #EMC_DYN_RP_OFS] - LDR R4, =EMC_DYN_RAS_Val - STR R4, [R0, #EMC_DYN_RAS_OFS] - LDR R4, =EMC_DYN_SREX_Val - STR R4, [R0, #EMC_DYN_SREX_OFS] - LDR R4, =EMC_DYN_APR_Val - STR R4, [R0, #EMC_DYN_APR_OFS] - LDR R4, =EMC_DYN_DAL_Val - STR R4, [R0, #EMC_DYN_DAL_OFS] - LDR R4, =EMC_DYN_WR_Val - STR R4, [R0, #EMC_DYN_WR_OFS] - LDR R4, =EMC_DYN_RC_Val - STR R4, [R0, #EMC_DYN_RC_OFS] - LDR R4, =EMC_DYN_RFC_Val - STR R4, [R0, #EMC_DYN_RFC_OFS] - LDR R4, =EMC_DYN_XSR_Val - STR R4, [R0, #EMC_DYN_XSR_OFS] - LDR R4, =EMC_DYN_RRD_Val - STR R4, [R0, #EMC_DYN_RRD_OFS] - LDR R4, =EMC_DYN_MRD_Val - STR R4, [R0, #EMC_DYN_MRD_OFS] - - LDR R4, =EMC_DYN_RD_CFG_Val - STR R4, [R0, #EMC_DYN_RD_CFG_OFS] - - IF (EMC_DYNCS0_SETUP != 0) - LDR R4, =EMC_DYN_RASCAS0_Val - STR R4, [R0, #EMC_DYN_RASCAS0_OFS] - LDR R4, =EMC_DYN_CFG0_Val - MVN R5, #BUFEN_Const - AND R4, R4, R5 - STR R4, [R0, #EMC_DYN_CFG0_OFS] - ENDIF - IF (EMC_DYNCS1_SETUP != 0) - LDR R4, =EMC_DYN_RASCAS1_Val - STR R4, [R0, #EMC_DYN_RASCAS1_OFS] - LDR R4, =EMC_DYN_CFG1_Val - MVN R5, =BUFEN_Const - AND R4, R4, R5 - STR R4, [R0, #EMC_DYN_CFG1_OFS] - ENDIF - IF (EMC_DYNCS2_SETUP != 0) - LDR R4, =EMC_DYN_RASCAS2_Val - STR R4, [R0, #EMC_DYN_RASCAS2_OFS] - LDR R4, =EMC_DYN_CFG2_Val - MVN R5, =BUFEN_Const - AND R4, R4, R5 - STR R4, [R0, #EMC_DYN_CFG2_OFS] - ENDIF - IF (EMC_DYNCS3_SETUP != 0) - LDR R4, =EMC_DYN_RASCAS3_Val - STR R4, [R0, #EMC_DYN_RASCAS3_OFS] - LDR R4, =EMC_DYN_CFG3_Val - MVN R5, =BUFEN_Const - AND R4, R4, R5 - STR R4, [R0, #EMC_DYN_CFG3_OFS] - ENDIF - - LDR R6, =1440000 ; Number of cycles to delay -Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms proc clk 57.6 MHz - BNE Wait_0 ; BNE (3 cyc) + SUBS (1 cyc) = 4 cyc - - LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command - STR R4, [R0, #EMC_DYN_CTRL_OFS] - - LDR R6, =2880000 ; Number of cycles to delay -Wait_1 SUBS R6, R6, #1 ; Delay ~200 ms proc clk 57.6 MHz - BNE Wait_1 - - LDR R4, =(PALL_CMD:OR:0x03) ; Write Precharge All Command - STR R4, [R0, #EMC_DYN_CTRL_OFS] - - MOV R4, #2 - STR R4, [R0, #EMC_DYN_RFSH_OFS] - - MOV R6, #64 ; Number of cycles to delay -Wait_2 SUBS R6, R6, #1 ; Delay - BNE Wait_2 - - LDR R4, =EMC_DYN_RFSH_Val - STR R4, [R0, #EMC_DYN_RFSH_OFS] - - LDR R4, =(MODE_CMD:OR:0x03) ; Write MODE Command - STR R4, [R0, #EMC_DYN_CTRL_OFS] - - ; Dummy read - IF (EMC_DYNCS0_SETUP != 0) - LDR R4, =DYN_MEM0_BASE - MOV R5, #(0x33 << 12) - ADD R4, R4, R5 - LDR R4, [R4, #0] - ENDIF - IF (EMC_DYNCS1_SETUP != 0) - LDR R4, =DYN_MEM1_BASE - MOV R5, #(0x33 << 12) - ADD R4, R4, R5 - LDR R4, [R4, #0] - ENDIF - IF (EMC_DYNCS2_SETUP != 0) - LDR R4, =DYN_MEM2_BASE - MOV R5, #(0x33 << 12) - ADD R4, R4, R5 - LDR R4, [R4, #0] - ENDIF - IF (EMC_DYNCS3_SETUP != 0) - LDR R4, =DYN_MEM3_BASE - MOV R5, #(0x33 << 12) - ADD R4, R4, R5 - LDR R4, [R4, #0] - ENDIF - - LDR R4, =NORMAL_CMD ; Write NORMAL Command - STR R4, [R0, #EMC_DYN_CTRL_OFS] - - ; Enable buffer if requested by settings - IF (EMC_DYNCS0_SETUP != 0):LAND:((EMC_DYN_CFG0_Val:AND:BUFEN_Const) != 0) - LDR R4, =EMC_DYN_CFG0_Val - STR R4, [R0, #EMC_DYN_CFG0_OFS] - ENDIF - IF (EMC_DYNCS1_SETUP != 0):LAND:((EMC_DYN_CFG1_Val:AND:BUFEN_Const) != 0) - LDR R4, =EMC_DYN_CFG1_Val - STR R4, [R0, #EMC_DYN_CFG1_OFS] - ENDIF - IF (EMC_DYNCS2_SETUP != 0):LAND:((EMC_DYN_CFG2_Val:AND:BUFEN_Const) != 0) - LDR R4, =EMC_DYN_CFG2_Val - STR R4, [R0, #EMC_DYN_CFG2_OFS] - ENDIF - IF (EMC_DYNCS3_SETUP != 0):LAND:((EMC_DYN_CFG3_Val:AND:BUFEN_Const) != 0) - LDR R4, =EMC_DYN_CFG3_Val - STR R4, [R0, #EMC_DYN_CFG3_OFS] - ENDIF - - LDR R6, =14400 ; Number of cycles to delay -Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz - BNE Wait_3 - - ENDIF ; EMC_DYNAMIC_SETUP - -; Setup Static Memory Interface - IF (EMC_STATIC_SETUP != 0) - - LDR R6, =1440000 ; Number of cycles to delay -Wait_4 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 57.6 MHz - BNE Wait_4 - - IF (EMC_STACS0_SETUP != 0) - LDR R4, =EMC_STA_CFG0_Val - STR R4, [R0, #EMC_STA_CFG0_OFS] - LDR R4, =EMC_STA_WWEN0_Val - STR R4, [R0, #EMC_STA_WWEN0_OFS] - LDR R4, =EMC_STA_WOEN0_Val - STR R4, [R0, #EMC_STA_WOEN0_OFS] - LDR R4, =EMC_STA_WRD0_Val - STR R4, [R0, #EMC_STA_WRD0_OFS] - LDR R4, =EMC_STA_WPAGE0_Val - STR R4, [R0, #EMC_STA_WPAGE0_OFS] - LDR R4, =EMC_STA_WWR0_Val - STR R4, [R0, #EMC_STA_WWR0_OFS] - LDR R4, =EMC_STA_WTURN0_Val - STR R4, [R0, #EMC_STA_WTURN0_OFS] - ENDIF - - IF (EMC_STACS1_SETUP != 0) - LDR R4, =EMC_STA_CFG1_Val - STR R4, [R0, #EMC_STA_CFG1_OFS] - LDR R4, =EMC_STA_WWEN1_Val - STR R4, [R0, #EMC_STA_WWEN1_OFS] - LDR R4, =EMC_STA_WOEN1_Val - STR R4, [R0, #EMC_STA_WOEN1_OFS] - LDR R4, =EMC_STA_WRD1_Val - STR R4, [R0, #EMC_STA_WRD1_OFS] - LDR R4, =EMC_STA_WPAGE1_Val - STR R4, [R0, #EMC_STA_WPAGE1_OFS] - LDR R4, =EMC_STA_WWR1_Val - STR R4, [R0, #EMC_STA_WWR1_OFS] - LDR R4, =EMC_STA_WTURN1_Val - STR R4, [R0, #EMC_STA_WTURN1_OFS] - ENDIF - - IF (EMC_STACS2_SETUP != 0) - LDR R4, =EMC_STA_CFG2_Val - STR R4, [R0, #EMC_STA_CFG2_OFS] - LDR R4, =EMC_STA_WWEN2_Val - STR R4, [R0, #EMC_STA_WWEN2_OFS] - LDR R4, =EMC_STA_WOEN2_Val - STR R4, [R0, #EMC_STA_WOEN2_OFS] - LDR R4, =EMC_STA_WRD2_Val - STR R4, [R0, #EMC_STA_WRD2_OFS] - LDR R4, =EMC_STA_WPAGE2_Val - STR R4, [R0, #EMC_STA_WPAGE2_OFS] - LDR R4, =EMC_STA_WWR2_Val - STR R4, [R0, #EMC_STA_WWR2_OFS] - LDR R4, =EMC_STA_WTURN2_Val - STR R4, [R0, #EMC_STA_WTURN2_OFS] - ENDIF - - IF (EMC_STACS3_SETUP != 0) - LDR R4, =EMC_STA_CFG3_Val - STR R4, [R0, #EMC_STA_CFG3_OFS] - LDR R4, =EMC_STA_WWEN3_Val - STR R4, [R0, #EMC_STA_WWEN3_OFS] - LDR R4, =EMC_STA_WOEN3_Val - STR R4, [R0, #EMC_STA_WOEN3_OFS] - LDR R4, =EMC_STA_WRD3_Val - STR R4, [R0, #EMC_STA_WRD3_OFS] - LDR R4, =EMC_STA_WPAGE3_Val - STR R4, [R0, #EMC_STA_WPAGE3_OFS] - LDR R4, =EMC_STA_WWR3_Val - STR R4, [R0, #EMC_STA_WWR3_OFS] - LDR R4, =EMC_STA_WTURN3_Val - STR R4, [R0, #EMC_STA_WTURN3_OFS] - ENDIF - - LDR R6, =144000 ; Number of cycles to delay -Wait_5 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 57.6 MHz - BNE Wait_5 - - LDR R4, =EMC_STA_EXT_W_Val - LDR R5, =EMC_STA_EXT_W_OFS - ADD R5, R5, R0 - STR R4, [R5, #0] - - ENDIF ; EMC_STATIC_SETUP - - ENDIF ; EMC_SETUP - - -; Copy Exception Vectors to Internal RAM --------------------------------------- - - IF :DEF:RAM_INTVEC - ADR R8, Vectors ; Source - LDR R9, =RAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - ENDIF - - -; Memory Mapping (when Interrupt Vectors are in RAM) --------------------------- - -MEMMAP EQU 0xE01FC040 ; Memory Mapping Control - IF :DEF:REMAP - LDR R0, =MEMMAP - IF :DEF:EXTMEM_MODE - MOV R1, #3 - ELIF :DEF:RAM_MODE - MOV R1, #2 - ELSE - MOV R1, #1 - ENDIF - STR R1, [R0] - ENDIF - - -; Setup Stack for each mode ---------------------------------------------------- - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - - IF :DEF:__MICROLIB - EXPORT __initial_sp - ELSE - ENDIF - -; Enter the C code ------------------------------------------------------------- - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's cpsr to spsr - MSR spsr_cxsf, r4 - BIC r4, r4, #0x20 ; must be ARM mode - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - - END +;/*****************************************************************************/ +;/* LPC2400.S: Startup file for Philips LPC2400 device series */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2007-2008 Keil - An ARM Company. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + +;/* +; * The LPC2400.S code is executed after CPU Reset. This file may be +; * translated with the following SET symbols. In uVision these SET +; * symbols are entered under Options - ASM - Define. +; * +; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock +; * (used mostly when clock is already initialized from script .ini +; * file). +; * +; * NO_EMC_SETUP: when set the startup code will not initialize +; * External Bus Controller. +; * +; * RAM_INTVEC: when set the startup code copies exception vectors +; * from on-chip Flash to on-chip RAM. +; * +; * REMAP: when set the startup code initializes the register MEMMAP +; * which overwrites the settings of the CPU configuration pins. The +; * startup and interrupt vectors are remapped from: +; * 0x00000000 default setting (not remapped) +; * 0x40000000 when RAM_MODE is used +; * 0x80000000 when EXTMEM_MODE is used +; * +; * EXTMEM_MODE: when set the device is configured for code execution +; * from external memory starting at address 0x80000000. +; * +; * RAM_MODE: when set the device is configured for code execution +; * from on-chip RAM starting at address 0x40000000. +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + +;----------------------- Memory Definitions ------------------------------------ + +; Internal Memory Base Addresses +FLASH_BASE EQU 0x00000000 +RAM_BASE EQU 0x40000000 +EXTMEM_BASE EQU 0x80000000 + +; External Memory Base Addresses +STA_MEM0_BASE EQU 0x80000000 +STA_MEM1_BASE EQU 0x81000000 +STA_MEM2_BASE EQU 0x82000000 +STA_MEM3_BASE EQU 0x83000000 +DYN_MEM0_BASE EQU 0xA0000000 +DYN_MEM1_BASE EQU 0xB0000000 +DYN_MEM2_BASE EQU 0xC0000000 +DYN_MEM3_BASE EQU 0xD0000000 + + +;----------------------- Stack and Heap Definitions ---------------------------- + +;// Stack Configuration (Stack Sizes in Bytes) +;// Undefined Mode <0x0-0xFFFFFFFF:8> +;// Supervisor Mode <0x0-0xFFFFFFFF:8> +;// Abort Mode <0x0-0xFFFFFFFF:8> +;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// Interrupt Mode <0x0-0xFFFFFFFF:8> +;// User/System Mode <0x0-0xFFFFFFFF:8> +;// + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size + +Stack_Top + + +;// Heap Configuration +;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +;----------------------- Clock Definitions ------------------------------------- + +; System Control Block (SCB) Module Definitions +SCB_BASE EQU 0xE01FC000 ; SCB Base Address +PLLCON_OFS EQU 0x80 ; PLL Control Offset +PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset +PLLSTAT_OFS EQU 0x88 ; PLL Status Offset +PLLFEED_OFS EQU 0x8C ; PLL Feed Offset +CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset +USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset +CLKSRCSEL_OFS EQU 0x10C ; Clock Source Sel Reg Offset +SCS_OFS EQU 0x1A0 ; Sys Control and Status Reg Offset +PCLKSEL0_OFS EQU 0x1A8 ; Periph Clock Sel Reg 0 Offset +PCLKSEL1_OFS EQU 0x1AC ; Periph Clock Sel Reg 0 Offset + +PCON_OFS EQU 0x0C0 ; Power Mode Control Reg Offset +PCONP_OFS EQU 0x0C4 ; Power Control for Periphs Reg Offset + +; Constants +OSCRANGE EQU (1<<4) ; Oscillator Range Select +OSCEN EQU (1<<5) ; Main oscillator Enable +OSCSTAT EQU (1<<6) ; Main Oscillator Status +PLLCON_PLLE EQU (1<<0) ; PLL Enable +PLLCON_PLLC EQU (1<<1) ; PLL Connect +PLLSTAT_M EQU (0x7FFF<<0) ; PLL M Value +PLLSTAT_N EQU (0xFF<<16) ; PLL N Value +PLLSTAT_PLOCK EQU (1<<26) ; PLL Lock Status + +;// Clock Setup +;// System Controls and Status Register (SYS) +;// OSCRANGE: Main Oscillator Range Select +;// <0=> 1 MHz to 20 MHz +;// <1=> 15 MHz to 24 MHz +;// OSCEN: Main Oscillator Enable +;// +;// +;// +;// PLL Clock Source Select Register (CLKSRCSEL) +;// CLKSRC: PLL Clock Source Selection +;// <0=> Internal RC oscillator +;// <1=> Main oscillator +;// <2=> RTC oscillator +;// +;// +;// PLL Configuration Register (PLLCFG) +;// PLL_clk = (2* M * PLL_clk_src) / N +;// MSEL: PLL Multiplier Selection +;// <1-32768><#-1> +;// M Value +;// NSEL: PLL Divider Selection +;// <1-256><#-1> +;// N Value +;// +;// +;// CPU Clock Configuration Register (CCLKCFG) +;// CCLKSEL: Divide Value for CPU Clock from PLL +;// <1-256><#-1> +;// +;// +;// USB Clock Configuration Register (USBCLKCFG) +;// USBSEL: Divide Value for USB Clock from PLL +;// <1-16><#-1> +;// +;// +;// Peripheral Clock Selection Register 0 (PCLKSEL0) +;// PCLK_WDT: Peripheral Clock Selection for WDT +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_UART0: Peripheral Clock Selection for UART0 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_UART1: Peripheral Clock Selection for UART1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_PWM0: Peripheral Clock Selection for PWM0 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_PWM1: Peripheral Clock Selection for PWM1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_I2C0: Peripheral Clock Selection for I2C0 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_SPI: Peripheral Clock Selection for SPI +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_RTC: Peripheral Clock Selection for RTC +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_SSP1: Peripheral Clock Selection for SSP1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_DAC: Peripheral Clock Selection for DAC +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_ADC: Peripheral Clock Selection for ADC +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_CAN1: Peripheral Clock Selection for CAN1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 6 +;// PCLK_CAN2: Peripheral Clock Selection for CAN2 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 6 +;// PCLK_ACF: Peripheral Clock Selection for ACF +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 6 +;// +;// +;// Peripheral Clock Selection Register 1 (PCLKSEL1) +;// PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_GPIO: Peripheral Clock Selection for GPIOs +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_PCB: Peripheral Clock Selection for Pin Connect Block +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_I2C1: Peripheral Clock Selection for I2C1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_SSP0: Peripheral Clock Selection for SSP0 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_UART2: Peripheral Clock Selection for UART2 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_UART3: Peripheral Clock Selection for UART3 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_I2C2: Peripheral Clock Selection for I2C2 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_I2S: Peripheral Clock Selection for I2S +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_MCI: Peripheral Clock Selection for MCI +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// PCLK_SYSCON: Peripheral Clock Selection for System Control Block +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// +;// +CLOCK_SETUP EQU 1 +SCS_Val EQU 0x00000020 +CLKSRCSEL_Val EQU 0x00000001 +PLLCFG_Val EQU 0x0000000B +CCLKCFG_Val EQU 0x00000004 +USBCLKCFG_Val EQU 0x00000005 +PCLKSEL0_Val EQU 0x00000000 +PCLKSEL1_Val EQU 0x00000000 + + +;----------------------- Memory Accelerator Module (MAM) Definitions ----------- + +MAM_BASE EQU 0xE01FC000 ; MAM Base Address +MAMCR_OFS EQU 0x00 ; MAM Control Offset +MAMTIM_OFS EQU 0x04 ; MAM Timing Offset + +;// MAM Setup +;// MAM Control +;// <0=> Disabled +;// <1=> Partially Enabled +;// <2=> Fully Enabled +;// Mode +;// MAM Timing +;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 +;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +;// Fetch Cycles +;// +MAM_SETUP EQU 1 +MAMCR_Val EQU 0x00000002 +MAMTIM_Val EQU 0x00000004 + + +;----------------------- Pin Connect Block Definitions ------------------------- + +PCB_BASE EQU 0xE002C000 ; PCB Base Address +PINSEL0_OFS EQU 0x00 ; PINSEL0 Address Offset +PINSEL1_OFS EQU 0x04 ; PINSEL1 Address Offset +PINSEL2_OFS EQU 0x08 ; PINSEL2 Address Offset +PINSEL3_OFS EQU 0x0C ; PINSEL3 Address Offset +PINSEL4_OFS EQU 0x10 ; PINSEL4 Address Offset +PINSEL5_OFS EQU 0x14 ; PINSEL5 Address Offset +PINSEL6_OFS EQU 0x18 ; PINSEL6 Address Offset +PINSEL7_OFS EQU 0x1C ; PINSEL7 Address Offset +PINSEL8_OFS EQU 0x20 ; PINSEL8 Address Offset +PINSEL9_OFS EQU 0x24 ; PINSEL9 Address Offset +PINSEL10_OFS EQU 0x28 ; PINSEL10 Address Offset + + +;----------------------- External Memory Controller (EMC) Definitons ----------- + +EMC_BASE EQU 0xFFE08000 ; EMC Base Address + +EMC_CTRL_OFS EQU 0x000 +EMC_STAT_OFS EQU 0x004 +EMC_CONFIG_OFS EQU 0x008 +EMC_DYN_CTRL_OFS EQU 0x020 +EMC_DYN_RFSH_OFS EQU 0x024 +EMC_DYN_RD_CFG_OFS EQU 0x028 +EMC_DYN_RP_OFS EQU 0x030 +EMC_DYN_RAS_OFS EQU 0x034 +EMC_DYN_SREX_OFS EQU 0x038 +EMC_DYN_APR_OFS EQU 0x03C +EMC_DYN_DAL_OFS EQU 0x040 +EMC_DYN_WR_OFS EQU 0x044 +EMC_DYN_RC_OFS EQU 0x048 +EMC_DYN_RFC_OFS EQU 0x04C +EMC_DYN_XSR_OFS EQU 0x050 +EMC_DYN_RRD_OFS EQU 0x054 +EMC_DYN_MRD_OFS EQU 0x058 +EMC_DYN_CFG0_OFS EQU 0x100 +EMC_DYN_RASCAS0_OFS EQU 0x104 +EMC_DYN_CFG1_OFS EQU 0x140 +EMC_DYN_RASCAS1_OFS EQU 0x144 +EMC_DYN_CFG2_OFS EQU 0x160 +EMC_DYN_RASCAS2_OFS EQU 0x164 +EMC_DYN_CFG3_OFS EQU 0x180 +EMC_DYN_RASCAS3_OFS EQU 0x184 +EMC_STA_CFG0_OFS EQU 0x200 +EMC_STA_WWEN0_OFS EQU 0x204 +EMC_STA_WOEN0_OFS EQU 0x208 +EMC_STA_WRD0_OFS EQU 0x20C +EMC_STA_WPAGE0_OFS EQU 0x210 +EMC_STA_WWR0_OFS EQU 0x214 +EMC_STA_WTURN0_OFS EQU 0x218 +EMC_STA_CFG1_OFS EQU 0x220 +EMC_STA_WWEN1_OFS EQU 0x224 +EMC_STA_WOEN1_OFS EQU 0x228 +EMC_STA_WRD1_OFS EQU 0x22C +EMC_STA_WPAGE1_OFS EQU 0x230 +EMC_STA_WWR1_OFS EQU 0x234 +EMC_STA_WTURN1_OFS EQU 0x238 +EMC_STA_CFG2_OFS EQU 0x240 +EMC_STA_WWEN2_OFS EQU 0x244 +EMC_STA_WOEN2_OFS EQU 0x248 +EMC_STA_WRD2_OFS EQU 0x24C +EMC_STA_WPAGE2_OFS EQU 0x250 +EMC_STA_WWR2_OFS EQU 0x254 +EMC_STA_WTURN2_OFS EQU 0x258 +EMC_STA_CFG3_OFS EQU 0x260 +EMC_STA_WWEN3_OFS EQU 0x264 +EMC_STA_WOEN3_OFS EQU 0x268 +EMC_STA_WRD3_OFS EQU 0x26C +EMC_STA_WPAGE3_OFS EQU 0x270 +EMC_STA_WWR3_OFS EQU 0x274 +EMC_STA_WTURN3_OFS EQU 0x278 +EMC_STA_EXT_W_OFS EQU 0x880 + +; Constants +NORMAL_CMD EQU (0x0 << 7) ; NORMAL Command +MODE_CMD EQU (0x1 << 7) ; MODE Command +PALL_CMD EQU (0x2 << 7) ; Precharge All Command +NOP_CMD EQU (0x3 << 7) ; NOP Command + +BUFEN_Const EQU (1 << 19) ; Buffer enable bit +EMC_PCONP_Const EQU (1 << 11) ; PCONP val to enable power for EMC + +; External Memory Pins definitions +; pin functions for SDRAM, NOR and NAND flash interfacing +EMC_PINSEL5_Val EQU 0x05010115 ; !CAS, !RAS, CLKOUT0, !DYCS0, DQMOUT0, DQMOUT1 +EMC_PINSEL6_Val EQU 0x55555555 ; D0 .. D15 +EMC_PINSEL8_Val EQU 0x55555555 ; A0 .. A15 +EMC_PINSEL9_Val EQU 0x50055555; ; A16 .. A23, !OE, !WE, !CS0, !CS1 + +;// External Memory Controller Setup (EMC) --------------------------------- +;// External Memory Controller Setup (EMC) +EMC_SETUP EQU 0 + +;// EMC Control Register (EMCControl) +;// Controls operation of the memory controller +;// L: Low-power mode enable +;// M: Address mirror enable +;// E: EMC enable +;// +EMC_CTRL_Val EQU 0x00000001 + +;// EMC Configuration Register (EMCConfig) +;// Configures operation of the memory controller +;// CCLK: CLKOUT ratio +;// <0=> 1:1 +;// <1=> 1:2 +;// Endian mode +;// <0=> Little-endian +;// <1=> Big-endian +;// +EMC_CONFIG_Val EQU 0x00000000 + +;// Dynamic Memory Interface Setup --------------------------------------- +;// Dynamic Memory Interface Setup +EMC_DYNAMIC_SETUP EQU 1 + +;// Dynamic Memory Refresh Timer Register (EMCDynamicRefresh) +;// Configures dynamic memory refresh operation +;// REFRESH: Refresh timer <0x000-0x7FF> +;// 0 = refresh disabled, 0x01-0x7FF: value * 16 CCLKS +;// +EMC_DYN_RFSH_Val EQU 0x0000001C + +;// Dynamic Memory Read Configuration Register (EMCDynamicReadConfig) +;// Configures the dynamic memory read strategy +;// RD: Read data strategy +;// <0=> Clock out delayed strategy +;// <1=> Command delayed strategy +;// <2=> Command delayed strategy plus one clock cycle +;// <3=> Command delayed strategy plus two clock cycles +;// +EMC_DYN_RD_CFG_Val EQU 0x00000001 + +;// Dynamic Memory Timings +;// Dynamic Memory Percentage Command Period Register (EMCDynamictRP) +;// tRP: Precharge command period <1-16> <#-1> +;// The delay is in EMCCLK cycles +;// This value is normally found in SDRAM data sheets as tRP +;// +;// Dynamic Memory Active to Precharge Command Period Register (EMCDynamictRAS) +;// tRAS: Active to precharge command period <1-16> <#-1> +;// The delay is in EMCCLK cycles +;// This value is normally found in SDRAM data sheets as tRAS +;// +;// Dynamic Memory Self-refresh Exit Time Register (EMCDynamictSREX) +;// tSREX: Self-refresh exit time <1-16> <#-1> +;// The delay is in CCLK cycles +;// This value is normally found in SDRAM data sheets as tSREX, +;// for devices without this parameter you use the same value as tXSR +;// +;// Dynamic Memory Last Data Out to Active Time Register (EMCDynamictAPR) +;// tAPR: Last-data-out to active command time <1-16> <#-1> +;// The delay is in CCLK cycles +;// This value is normally found in SDRAM data sheets as tAPR +;// +;// Dynamic Memory Data-in to Active Command Time Register (EMCDynamictDAL) +;// tDAL: Data-in to active command time <1-16> <#-1> +;// The delay is in CCLK cycles +;// This value is normally found in SDRAM data sheets as tDAL or tAPW +;// +;// Dynamic Memory Write Recovery Time Register (EMCDynamictWR) +;// tWR: Write recovery time <1-16> <#-1> +;// The delay is in CCLK cycles +;// This value is normally found in SDRAM data sheets as tWR, tDPL, tRWL, or tRDL +;// +;// Dynamic Memory Active to Active Command Period Register (EMCDynamictRC) +;// tRC: Active to active command period <1-32> <#-1> +;// The delay is in CCLK cycles +;// This value is normally found in SDRAM data sheets as tRC +;// +;// Dynamic Memory Auto-refresh Period Register (EMCDynamictRFC) +;// tRFC: Auto-refresh period and auto-refresh to active command period <1-32> <#-1> +;// The delay is in CCLK cycles +;// This value is normally found in SDRAM data sheets as tRFC or tRC +;// +;// Dynamic Memory Exit Self-refresh Register (EMCDynamictXSR) +;// tXSR: Exit self-refresh to active command time <1-32> <#-1> +;// The delay is in CCLK cycles +;// This value is normally found in SDRAM data sheets as tXSR +;// +;// Dynamic Memory Active Bank A to Active Bank B Time Register (EMCDynamicRRD) +;// tRRD: Active bank A to active bank B latency <1-16> <#-1> +;// The delay is in CCLK cycles +;// This value is normally found in SDRAM data sheets as tRRD +;// +;// Dynamic Memory Load Mode Register to Active Command Time (EMCDynamictMRD) +;// tMRD: Load mode register to active command time <1-16> <#-1> +;// The delay is in CCLK cycles +;// This value is normally found in SDRAM data sheets as tMRD or tRSA +;// +;// +EMC_DYN_RP_Val EQU 0x00000002 +EMC_DYN_RAS_Val EQU 0x00000003 +EMC_DYN_SREX_Val EQU 0x00000007 +EMC_DYN_APR_Val EQU 0x00000002 +EMC_DYN_DAL_Val EQU 0x00000005 +EMC_DYN_WR_Val EQU 0x00000001 +EMC_DYN_RC_Val EQU 0x00000005 +EMC_DYN_RFC_Val EQU 0x00000005 +EMC_DYN_XSR_Val EQU 0x00000007 +EMC_DYN_RRD_Val EQU 0x00000001 +EMC_DYN_MRD_Val EQU 0x00000002 + +;// Configure External Bus Behaviour for Dynamic CS0 Area +EMC_DYNCS0_SETUP EQU 1 + +;// Dynamic Memory Configuration Register (EMCDynamicConfig0) +;// Defines the configuration information for the dynamic memory CS0 +;// P: Write protect +;// B: Buffer enable +;// AM 14: External bus data width +;// <0=> 16 bit +;// <1=> 32 bit +;// AM 12: External bus memory type +;// <0=> High-performance +;// <1=> Low-power SDRAM +;// AM 11..7: External bus address mapping (Row, Bank, Column) +;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 +;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 +;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 +;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 +;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 +;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 +;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 +;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 +;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 +;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 +;// MD: Memory device +;// <0=> SDRAM +;// <1=> Low-power SDRAM +;// <2=> Micron SyncFlash +;// +EMC_DYN_CFG0_Val EQU 0x00080680 + +;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS0) +;// Controls the RAS and CAS latencies for the dynamic memory CS0 +;// CAS: CAS latency +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// RAS: RAS latency (active to read/write delay) +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// +EMC_DYN_RASCAS0_Val EQU 0x00000303 + +;// End of Dynamic Setup for CS0 Area + + +;// Configure External Bus Behaviour for Dynamic CS1 Area +EMC_DYNCS1_SETUP EQU 0 + +;// Dynamic Memory Configuration Register (EMCDynamicConfig1) +;// Defines the configuration information for the dynamic memory CS1 +;// P: Write protect +;// B: Buffer enable +;// AM 14: External bus data width +;// <0=> 16 bit +;// <1=> 32 bit +;// AM 12: External bus memory type +;// <0=> High-performance +;// <1=> Low-power SDRAM +;// AM 11..7: External bus address mapping (Row, Bank, Column) +;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 +;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 +;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 +;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 +;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 +;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 +;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 +;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 +;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 +;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 +;// MD: Memory device +;// <0=> SDRAM +;// <1=> Low-power SDRAM +;// <2=> Micron SyncFlash +;// +EMC_DYN_CFG1_Val EQU 0x00000000 + +;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS1) +;// Controls the RAS and CAS latencies for the dynamic memory CS1 +;// CAS: CAS latency +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// RAS: RAS latency (active to read/write delay) +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// +EMC_DYN_RASCAS1_Val EQU 0x00000303 + +;// End of Dynamic Setup for CS1 Area + +;// Configure External Bus Behaviour for Dynamic CS2 Area +EMC_DYNCS2_SETUP EQU 0 + +;// Dynamic Memory Configuration Register (EMCDynamicConfig2) +;// Defines the configuration information for the dynamic memory CS2 +;// P: Write protect +;// B: Buffer enable +;// AM 14: External bus data width +;// <0=> 16 bit +;// <1=> 32 bit +;// AM 12: External bus memory type +;// <0=> High-performance +;// <1=> Low-power SDRAM +;// AM 11..7: External bus address mapping (Row, Bank, Column) +;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 +;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 +;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 +;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 +;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 +;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 +;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 +;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 +;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 +;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 +;// MD: Memory device +;// <0=> SDRAM +;// <1=> Low-power SDRAM +;// <2=> Micron SyncFlash +;// +EMC_DYN_CFG2_Val EQU 0x00000000 + +;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS2) +;// Controls the RAS and CAS latencies for the dynamic memory CS2 +;// CAS: CAS latency +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// RAS: RAS latency (active to read/write delay) +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// +EMC_DYN_RASCAS2_Val EQU 0x00000303 + +;// End of Dynamic Setup for CS2 Area + +;// Configure External Bus Behaviour for Dynamic CS3 Area +EMC_DYNCS3_SETUP EQU 0 + +;// Dynamic Memory Configuration Register (EMCDynamicConfig3) +;// Defines the configuration information for the dynamic memory CS3 +;// P: Write protect +;// B: Buffer enable +;// AM 14: External bus data width +;// <0=> 16 bit +;// <1=> 32 bit +;// AM 12: External bus memory type +;// <0=> High-performance +;// <1=> Low-power SDRAM +;// AM 11..7: External bus address mapping (Row, Bank, Column) +;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 +;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 +;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 +;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 +;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 +;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 +;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 +;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 +;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 +;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 +;// MD: Memory device +;// <0=> SDRAM +;// <1=> Low-power SDRAM +;// <2=> Micron SyncFlash +;// +EMC_DYN_CFG3_Val EQU 0x00000000 + +;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS3) +;// Controls the RAS and CAS latencies for the dynamic memory CS3 +;// CAS: CAS latency +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// RAS: RAS latency (active to read/write delay) +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// +EMC_DYN_RASCAS3_Val EQU 0x00000303 + +;// End of Dynamic Setup for CS3 Area + +;// End of Dynamic Setup + +;// Static Memory Interface Setup ---------------------------------------- +;// Static Memory Interface Setup +EMC_STATIC_SETUP EQU 1 + +;// Configure External Bus Behaviour for Static CS0 Area --------------- +;// Configure External Bus Behaviour for Static CS0 Area +EMC_STACS0_SETUP EQU 1 + +;// Static Memory Configuration Register (EMCStaticConfig0) +;// Defines the configuration information for the static memory CS0 +;// WP: Write protect +;// B: Buffer enable +;// EW: Extended wait enable +;// PB: Byte lane state +;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW +;// <1=> For reads BLSn are LOW, for writes BLSn are LOW +;// PC: Chip select polarity +;// <0=> Active LOW chip select +;// <1=> Active HIGH chip select +;// PM: Page mode enable +;// MW: Memory width +;// <0=> 8 bit +;// <1=> 16 bit +;// <2=> 32 bit +;// +EMC_STA_CFG0_Val EQU 0x00000081 + +;// Static Memory Write Enable Delay Register (EMCStaticWaitWen0) +;// Selects the delay from CS0 to write enable +;// WAITWEN: Wait write enable <1-16> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WWEN0_Val EQU 0x00000002 + +;// Static Memory Output Enable Delay register (EMCStaticWaitOen0) +;// Selects the delay from CS0 or address change, whichever is later, to output enable +;// WAITOEN: Wait output enable <0-15> +;// The delay is in CCLK cycles +;// +EMC_STA_WOEN0_Val EQU 0x00000002 + +;// Static Memory Read Delay Register (EMCStaticWaitRd0) +;// Selects the delay from CS0 to a read access +;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WRD0_Val EQU 0x0000001F + +;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) +;// Selects the delay for asynchronous page mode sequential accesses for CS0 +;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WPAGE0_Val EQU 0x0000001F + +;// Static Memory Write Delay Register (EMCStaticWaitWr0) +;// Selects the delay from CS0 to a write access +;// WAITWR: Write wait states <2-33> <#-2> +;// The delay is in CCLK cycles +;// +EMC_STA_WWR0_Val EQU 0x0000001F + +;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn0) +;// Selects the number of bus turnaround cycles for CS0 +;// WAITTURN: Bus turnaround cycles <1-16> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WTURN0_Val EQU 0x0000000F + +;// End of Static Setup for Static CS0 Area + +;// Configure External Bus Behaviour for Static CS1 Area --------------- +;// Configure External Bus Behaviour for Static CS1 Area +EMC_STACS1_SETUP EQU 0 + +;// Static Memory Configuration Register (EMCStaticConfig1) +;// Defines the configuration information for the static memory CS1 +;// WP: Write protect +;// B: Buffer enable +;// EW: Extended wait enable +;// PB: Byte lane state +;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW +;// <1=> For reads BLSn are LOW, for writes BLSn are LOW +;// PC: Chip select polarity +;// <0=> Active LOW chip select +;// <1=> Active HIGH chip select +;// PM: Page mode enable +;// MW: Memory width +;// <0=> 8 bit +;// <1=> 16 bit +;// <2=> 32 bit +;// +EMC_STA_CFG1_Val EQU 0x00000000 + +;// Static Memory Write Enable Delay Register (EMCStaticWaitWen1) +;// Selects the delay from CS1 to write enable +;// WAITWEN: Wait write enable <1-16> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WWEN1_Val EQU 0x00000000 + +;// Static Memory Output Enable Delay register (EMCStaticWaitOen1) +;// Selects the delay from CS1 or address change, whichever is later, to output enable +;// WAITOEN: Wait output enable <0-15> +;// The delay is in CCLK cycles +;// +EMC_STA_WOEN1_Val EQU 0x00000000 + +;// Static Memory Read Delay Register (EMCStaticWaitRd1) +;// Selects the delay from CS1 to a read access +;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WRD1_Val EQU 0x0000001F + +;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) +;// Selects the delay for asynchronous page mode sequential accesses for CS1 +;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WPAGE1_Val EQU 0x0000001F + +;// Static Memory Write Delay Register (EMCStaticWaitWr1) +;// Selects the delay from CS1 to a write access +;// WAITWR: Write wait states <2-33> <#-2> +;// The delay is in CCLK cycles +;// +EMC_STA_WWR1_Val EQU 0x0000001F + +;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn1) +;// Selects the number of bus turnaround cycles for CS1 +;// WAITTURN: Bus turnaround cycles <1-16> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WTURN1_Val EQU 0x0000000F + +;// End of Static Setup for Static CS1 Area + +;// Configure External Bus Behaviour for Static CS2 Area --------------- +;// Configure External Bus Behaviour for Static CS2 Area +EMC_STACS2_SETUP EQU 0 + +;// Static Memory Configuration Register (EMCStaticConfig2) +;// Defines the configuration information for the static memory CS2 +;// WP: Write protect +;// B: Buffer enable +;// EW: Extended wait enable +;// PB: Byte lane state +;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW +;// <1=> For reads BLSn are LOW, for writes BLSn are LOW +;// PC: Chip select polarity +;// <0=> Active LOW chip select +;// <1=> Active HIGH chip select +;// PM: Page mode enable +;// MW: Memory width +;// <0=> 8 bit +;// <1=> 16 bit +;// <2=> 32 bit +;// +EMC_STA_CFG2_Val EQU 0x00000000 + +;// Static Memory Write Enable Delay Register (EMCStaticWaitWen2) +;// Selects the delay from CS2 to write enable +;// WAITWEN: Wait write enable <1-16> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WWEN2_Val EQU 0x00000000 + +;// Static Memory Output Enable Delay register (EMCStaticWaitOen2) +;// Selects the delay from CS2 or address change, whichever is later, to output enable +;// WAITOEN: Wait output enable <0-15> +;// The delay is in CCLK cycles +;// +EMC_STA_WOEN2_Val EQU 0x00000000 + +;// Static Memory Read Delay Register (EMCStaticWaitRd2) +;// Selects the delay from CS2 to a read access +;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WRD2_Val EQU 0x0000001F + +;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage2) +;// Selects the delay for asynchronous page mode sequential accesses for CS2 +;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WPAGE2_Val EQU 0x0000001F + +;// Static Memory Write Delay Register (EMCStaticWaitWr2) +;// Selects the delay from CS2 to a write access +;// WAITWR: Write wait states <2-33> <#-2> +;// The delay is in CCLK cycles +;// +EMC_STA_WWR2_Val EQU 0x0000001F + +;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn2) +;// Selects the number of bus turnaround cycles for CS2 +;// WAITTURN: Bus turnaround cycles <1-16> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WTURN2_Val EQU 0x0000000F + +;// End of Static Setup for Static CS2 Area + +;// Configure External Bus Behaviour for Static CS3 Area --------------- +;// Configure External Bus Behaviour for Static CS3 Area +EMC_STACS3_SETUP EQU 0 + +;// Static Memory Configuration Register (EMCStaticConfig3) +;// Defines the configuration information for the static memory CS3 +;// WP: Write protect +;// B: Buffer enable +;// EW: Extended wait enable +;// PB: Byte lane state +;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW +;// <1=> For reads BLSn are LOW, for writes BLSn are LOW +;// PC: Chip select polarity +;// <0=> Active LOW chip select +;// <1=> Active HIGH chip select +;// PM: Page mode enable +;// MW: Memory width +;// <0=> 8 bit +;// <1=> 16 bit +;// <2=> 32 bit +;// +EMC_STA_CFG3_Val EQU 0x00000000 + +;// Static Memory Write Enable Delay Register (EMCStaticWaitWen3) +;// Selects the delay from CS3 to write enable +;// WAITWEN: Wait write enable <1-16> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WWEN3_Val EQU 0x00000000 + +;// Static Memory Output Enable Delay register (EMCStaticWaitOen3) +;// Selects the delay from CS3 or address change, whichever is later, to output enable +;// WAITOEN: Wait output enable <0-15> +;// The delay is in CCLK cycles +;// +EMC_STA_WOEN3_Val EQU 0x00000000 + +;// Static Memory Read Delay Register (EMCStaticWaitRd3) +;// Selects the delay from CS3 to a read access +;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WRD3_Val EQU 0x0000001F + +;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage3) +;// Selects the delay for asynchronous page mode sequential accesses for CS3 +;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WPAGE3_Val EQU 0x0000001F + +;// Static Memory Write Delay Register (EMCStaticWaitWr3) +;// Selects the delay from CS3 to a write access +;// WAITWR: Write wait states <2-33> <#-2> +;// The delay is in CCLK cycles +;// +EMC_STA_WWR3_Val EQU 0x0000001F + +;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn3) +;// Selects the number of bus turnaround cycles for CS3 +;// WAITTURN: Bus turnaround cycles <1-16> <#-1> +;// The delay is in CCLK cycles +;// +EMC_STA_WTURN3_Val EQU 0x0000000F + +;// End of Static Setup for Static CS3 Area + +;// Static Memory Extended Wait Register (EMCStaticExtendedWait) +;// Time long static memory read and write transfers +;// EXTENDEDWAIT: Extended wait time out <0-1023> +;// The delay is in (16 * CCLK) cycles +;// +EMC_STA_EXT_W_Val EQU 0x00000000 + +;// End of Static Setup + +;// End of EMC Setup + + + PRESERVE8 + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + +Vectors LDR PC, Reset_Addr + LDR PC, Undef_Addr + LDR PC, SWI_Addr + LDR PC, PAbt_Addr + LDR PC, DAbt_Addr + NOP ; Reserved Vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + + +; Exception Handler + IMPORT rt_hw_trap_udef + IMPORT rt_hw_trap_swi + IMPORT rt_hw_trap_pabt + IMPORT rt_hw_trap_dabt + IMPORT rt_hw_trap_fiq + +; Prepare Fatal Context + MACRO + prepare_fatal + STMFD sp!, {r0-r3} + MOV r1, sp + ADD sp, sp, #16 + SUB r2, lr, #4 + MRS r3, spsr + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC + + STMFD sp!, {r0} ; old r0 + ; get sp + ADD r0, sp, #4 + STMFD sp!, {r3} ; cpsr + STMFD sp!, {r2} ; pc + STMFD sp!, {lr} ; lr + STMFD sp!, {r0} ; sp + STMFD sp!, {r4-r12} + + MOV r4, r1 + + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} + + MOV r0, sp + MEND + +Undef_Handler + prepare_fatal + BL rt_hw_trap_irq + B . + +SWI_Handler + prepare_fatal + BL rt_hw_trap_swi + B . + +PAbt_Handler + prepare_fatal + BL rt_hw_trap_pabt + B . + +DAbt_Handler + prepare_fatal + BL rt_hw_trap_dabt + B . + +FIQ_Handler + prepare_fatal + BL rt_hw_trap_fiq + B . + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; Clock Setup ------------------------------------------------------------------ + + IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) + LDR R0, =SCB_BASE + MOV R1, #0xAA + MOV R2, #0x55 + +; Configure and Enable PLL + LDR R3, =SCS_Val ; Enable main oscillator + STR R3, [R0, #SCS_OFS] + + IF (SCS_Val:AND:OSCEN) != 0 +OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize + ANDS R3, R3, #OSCSTAT + BEQ OSC_Loop + ENDIF + + LDR R3, =CLKSRCSEL_Val ; Select PLL source clock + STR R3, [R0, #CLKSRCSEL_OFS] + LDR R3, =PLLCFG_Val + STR R3, [R0, #PLLCFG_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + MOV R3, #PLLCON_PLLE + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + + IF (CLKSRCSEL_Val:AND:3) != 2 +; Wait until PLL Locked (if source is not RTC oscillator) +PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] + ANDS R3, R3, #PLLSTAT_PLOCK + BEQ PLL_Loop + ELSE +; Wait at least 200 cycles (if source is RTC oscillator) + MOV R3, #(200/4) +PLL_Loop SUBS R3, R3, #1 + BNE PLL_Loop + ENDIF + +M_N_Lock LDR R3, [R0, #PLLSTAT_OFS] + LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N) + AND R3, R3, R4 + LDR R4, =PLLCFG_Val + EORS R3, R3, R4 + BNE M_N_Lock + +; Setup CPU clock divider + MOV R3, #CCLKCFG_Val + STR R3, [R0, #CCLKCFG_OFS] + +; Setup USB clock divider + LDR R3, =USBCLKCFG_Val + STR R3, [R0, #USBCLKCFG_OFS] + +; Setup Peripheral Clock + LDR R3, =PCLKSEL0_Val + STR R3, [R0, #PCLKSEL0_OFS] + LDR R3, =PCLKSEL1_Val + STR R3, [R0, #PCLKSEL1_OFS] + +; Switch to PLL Clock + MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + ENDIF ; CLOCK_SETUP + + +; Setup Memory Accelerator Module ---------------------------------------------- + + IF MAM_SETUP != 0 + LDR R0, =MAM_BASE + MOV R1, #MAMTIM_Val + STR R1, [R0, #MAMTIM_OFS] + MOV R1, #MAMCR_Val + STR R1, [R0, #MAMCR_OFS] + ENDIF ; MAM_SETUP + + +; Setup External Memory Controller --------------------------------------------- + + IF (:LNOT:(:DEF:NO_EMC_SETUP)):LAND:(EMC_SETUP != 0) + LDR R0, =EMC_BASE + LDR R1, =SCB_BASE + LDR R2, =PCB_BASE + + LDR R4, =EMC_PCONP_Const ; Enable EMC + LDR R3, [R1, #PCONP_OFS] + ORR R4, R4, R3 + STR R4, [R1, #PCONP_OFS] + + LDR R4, =EMC_CTRL_Val + STR R4, [R0, #EMC_CTRL_OFS] + LDR R4, =EMC_CONFIG_Val + STR R4, [R0, #EMC_CONFIG_OFS] + +; Setup pin functions for External Bus functionality + LDR R4, =EMC_PINSEL5_Val + STR R4, [R2, #PINSEL5_OFS] + LDR R4, =EMC_PINSEL6_Val + STR R4, [R2, #PINSEL6_OFS] + LDR R4, =EMC_PINSEL8_Val + STR R4, [R2, #PINSEL8_OFS] + LDR R4, =EMC_PINSEL9_Val + STR R4, [R2, #PINSEL9_OFS] + +; Setup Dynamic Memory Interface + IF (EMC_DYNAMIC_SETUP != 0) + + LDR R4, =EMC_DYN_RP_Val + STR R4, [R0, #EMC_DYN_RP_OFS] + LDR R4, =EMC_DYN_RAS_Val + STR R4, [R0, #EMC_DYN_RAS_OFS] + LDR R4, =EMC_DYN_SREX_Val + STR R4, [R0, #EMC_DYN_SREX_OFS] + LDR R4, =EMC_DYN_APR_Val + STR R4, [R0, #EMC_DYN_APR_OFS] + LDR R4, =EMC_DYN_DAL_Val + STR R4, [R0, #EMC_DYN_DAL_OFS] + LDR R4, =EMC_DYN_WR_Val + STR R4, [R0, #EMC_DYN_WR_OFS] + LDR R4, =EMC_DYN_RC_Val + STR R4, [R0, #EMC_DYN_RC_OFS] + LDR R4, =EMC_DYN_RFC_Val + STR R4, [R0, #EMC_DYN_RFC_OFS] + LDR R4, =EMC_DYN_XSR_Val + STR R4, [R0, #EMC_DYN_XSR_OFS] + LDR R4, =EMC_DYN_RRD_Val + STR R4, [R0, #EMC_DYN_RRD_OFS] + LDR R4, =EMC_DYN_MRD_Val + STR R4, [R0, #EMC_DYN_MRD_OFS] + + LDR R4, =EMC_DYN_RD_CFG_Val + STR R4, [R0, #EMC_DYN_RD_CFG_OFS] + + IF (EMC_DYNCS0_SETUP != 0) + LDR R4, =EMC_DYN_RASCAS0_Val + STR R4, [R0, #EMC_DYN_RASCAS0_OFS] + LDR R4, =EMC_DYN_CFG0_Val + MVN R5, #BUFEN_Const + AND R4, R4, R5 + STR R4, [R0, #EMC_DYN_CFG0_OFS] + ENDIF + IF (EMC_DYNCS1_SETUP != 0) + LDR R4, =EMC_DYN_RASCAS1_Val + STR R4, [R0, #EMC_DYN_RASCAS1_OFS] + LDR R4, =EMC_DYN_CFG1_Val + MVN R5, =BUFEN_Const + AND R4, R4, R5 + STR R4, [R0, #EMC_DYN_CFG1_OFS] + ENDIF + IF (EMC_DYNCS2_SETUP != 0) + LDR R4, =EMC_DYN_RASCAS2_Val + STR R4, [R0, #EMC_DYN_RASCAS2_OFS] + LDR R4, =EMC_DYN_CFG2_Val + MVN R5, =BUFEN_Const + AND R4, R4, R5 + STR R4, [R0, #EMC_DYN_CFG2_OFS] + ENDIF + IF (EMC_DYNCS3_SETUP != 0) + LDR R4, =EMC_DYN_RASCAS3_Val + STR R4, [R0, #EMC_DYN_RASCAS3_OFS] + LDR R4, =EMC_DYN_CFG3_Val + MVN R5, =BUFEN_Const + AND R4, R4, R5 + STR R4, [R0, #EMC_DYN_CFG3_OFS] + ENDIF + + LDR R6, =1440000 ; Number of cycles to delay +Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms proc clk 57.6 MHz + BNE Wait_0 ; BNE (3 cyc) + SUBS (1 cyc) = 4 cyc + + LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command + STR R4, [R0, #EMC_DYN_CTRL_OFS] + + LDR R6, =2880000 ; Number of cycles to delay +Wait_1 SUBS R6, R6, #1 ; Delay ~200 ms proc clk 57.6 MHz + BNE Wait_1 + + LDR R4, =(PALL_CMD:OR:0x03) ; Write Precharge All Command + STR R4, [R0, #EMC_DYN_CTRL_OFS] + + MOV R4, #2 + STR R4, [R0, #EMC_DYN_RFSH_OFS] + + MOV R6, #64 ; Number of cycles to delay +Wait_2 SUBS R6, R6, #1 ; Delay + BNE Wait_2 + + LDR R4, =EMC_DYN_RFSH_Val + STR R4, [R0, #EMC_DYN_RFSH_OFS] + + LDR R4, =(MODE_CMD:OR:0x03) ; Write MODE Command + STR R4, [R0, #EMC_DYN_CTRL_OFS] + + ; Dummy read + IF (EMC_DYNCS0_SETUP != 0) + LDR R4, =DYN_MEM0_BASE + MOV R5, #(0x33 << 12) + ADD R4, R4, R5 + LDR R4, [R4, #0] + ENDIF + IF (EMC_DYNCS1_SETUP != 0) + LDR R4, =DYN_MEM1_BASE + MOV R5, #(0x33 << 12) + ADD R4, R4, R5 + LDR R4, [R4, #0] + ENDIF + IF (EMC_DYNCS2_SETUP != 0) + LDR R4, =DYN_MEM2_BASE + MOV R5, #(0x33 << 12) + ADD R4, R4, R5 + LDR R4, [R4, #0] + ENDIF + IF (EMC_DYNCS3_SETUP != 0) + LDR R4, =DYN_MEM3_BASE + MOV R5, #(0x33 << 12) + ADD R4, R4, R5 + LDR R4, [R4, #0] + ENDIF + + LDR R4, =NORMAL_CMD ; Write NORMAL Command + STR R4, [R0, #EMC_DYN_CTRL_OFS] + + ; Enable buffer if requested by settings + IF (EMC_DYNCS0_SETUP != 0):LAND:((EMC_DYN_CFG0_Val:AND:BUFEN_Const) != 0) + LDR R4, =EMC_DYN_CFG0_Val + STR R4, [R0, #EMC_DYN_CFG0_OFS] + ENDIF + IF (EMC_DYNCS1_SETUP != 0):LAND:((EMC_DYN_CFG1_Val:AND:BUFEN_Const) != 0) + LDR R4, =EMC_DYN_CFG1_Val + STR R4, [R0, #EMC_DYN_CFG1_OFS] + ENDIF + IF (EMC_DYNCS2_SETUP != 0):LAND:((EMC_DYN_CFG2_Val:AND:BUFEN_Const) != 0) + LDR R4, =EMC_DYN_CFG2_Val + STR R4, [R0, #EMC_DYN_CFG2_OFS] + ENDIF + IF (EMC_DYNCS3_SETUP != 0):LAND:((EMC_DYN_CFG3_Val:AND:BUFEN_Const) != 0) + LDR R4, =EMC_DYN_CFG3_Val + STR R4, [R0, #EMC_DYN_CFG3_OFS] + ENDIF + + LDR R6, =14400 ; Number of cycles to delay +Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz + BNE Wait_3 + + ENDIF ; EMC_DYNAMIC_SETUP + +; Setup Static Memory Interface + IF (EMC_STATIC_SETUP != 0) + + LDR R6, =1440000 ; Number of cycles to delay +Wait_4 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 57.6 MHz + BNE Wait_4 + + IF (EMC_STACS0_SETUP != 0) + LDR R4, =EMC_STA_CFG0_Val + STR R4, [R0, #EMC_STA_CFG0_OFS] + LDR R4, =EMC_STA_WWEN0_Val + STR R4, [R0, #EMC_STA_WWEN0_OFS] + LDR R4, =EMC_STA_WOEN0_Val + STR R4, [R0, #EMC_STA_WOEN0_OFS] + LDR R4, =EMC_STA_WRD0_Val + STR R4, [R0, #EMC_STA_WRD0_OFS] + LDR R4, =EMC_STA_WPAGE0_Val + STR R4, [R0, #EMC_STA_WPAGE0_OFS] + LDR R4, =EMC_STA_WWR0_Val + STR R4, [R0, #EMC_STA_WWR0_OFS] + LDR R4, =EMC_STA_WTURN0_Val + STR R4, [R0, #EMC_STA_WTURN0_OFS] + ENDIF + + IF (EMC_STACS1_SETUP != 0) + LDR R4, =EMC_STA_CFG1_Val + STR R4, [R0, #EMC_STA_CFG1_OFS] + LDR R4, =EMC_STA_WWEN1_Val + STR R4, [R0, #EMC_STA_WWEN1_OFS] + LDR R4, =EMC_STA_WOEN1_Val + STR R4, [R0, #EMC_STA_WOEN1_OFS] + LDR R4, =EMC_STA_WRD1_Val + STR R4, [R0, #EMC_STA_WRD1_OFS] + LDR R4, =EMC_STA_WPAGE1_Val + STR R4, [R0, #EMC_STA_WPAGE1_OFS] + LDR R4, =EMC_STA_WWR1_Val + STR R4, [R0, #EMC_STA_WWR1_OFS] + LDR R4, =EMC_STA_WTURN1_Val + STR R4, [R0, #EMC_STA_WTURN1_OFS] + ENDIF + + IF (EMC_STACS2_SETUP != 0) + LDR R4, =EMC_STA_CFG2_Val + STR R4, [R0, #EMC_STA_CFG2_OFS] + LDR R4, =EMC_STA_WWEN2_Val + STR R4, [R0, #EMC_STA_WWEN2_OFS] + LDR R4, =EMC_STA_WOEN2_Val + STR R4, [R0, #EMC_STA_WOEN2_OFS] + LDR R4, =EMC_STA_WRD2_Val + STR R4, [R0, #EMC_STA_WRD2_OFS] + LDR R4, =EMC_STA_WPAGE2_Val + STR R4, [R0, #EMC_STA_WPAGE2_OFS] + LDR R4, =EMC_STA_WWR2_Val + STR R4, [R0, #EMC_STA_WWR2_OFS] + LDR R4, =EMC_STA_WTURN2_Val + STR R4, [R0, #EMC_STA_WTURN2_OFS] + ENDIF + + IF (EMC_STACS3_SETUP != 0) + LDR R4, =EMC_STA_CFG3_Val + STR R4, [R0, #EMC_STA_CFG3_OFS] + LDR R4, =EMC_STA_WWEN3_Val + STR R4, [R0, #EMC_STA_WWEN3_OFS] + LDR R4, =EMC_STA_WOEN3_Val + STR R4, [R0, #EMC_STA_WOEN3_OFS] + LDR R4, =EMC_STA_WRD3_Val + STR R4, [R0, #EMC_STA_WRD3_OFS] + LDR R4, =EMC_STA_WPAGE3_Val + STR R4, [R0, #EMC_STA_WPAGE3_OFS] + LDR R4, =EMC_STA_WWR3_Val + STR R4, [R0, #EMC_STA_WWR3_OFS] + LDR R4, =EMC_STA_WTURN3_Val + STR R4, [R0, #EMC_STA_WTURN3_OFS] + ENDIF + + LDR R6, =144000 ; Number of cycles to delay +Wait_5 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 57.6 MHz + BNE Wait_5 + + LDR R4, =EMC_STA_EXT_W_Val + LDR R5, =EMC_STA_EXT_W_OFS + ADD R5, R5, R0 + STR R4, [R5, #0] + + ENDIF ; EMC_STATIC_SETUP + + ENDIF ; EMC_SETUP + + +; Copy Exception Vectors to Internal RAM --------------------------------------- + + IF :DEF:RAM_INTVEC + ADR R8, Vectors ; Source + LDR R9, =RAM_BASE ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + ENDIF + + +; Memory Mapping (when Interrupt Vectors are in RAM) --------------------------- + +MEMMAP EQU 0xE01FC040 ; Memory Mapping Control + IF :DEF:REMAP + LDR R0, =MEMMAP + IF :DEF:EXTMEM_MODE + MOV R1, #3 + ELIF :DEF:RAM_MODE + MOV R1, #2 + ELSE + MOV R1, #1 + ENDIF + STR R1, [R0] + ENDIF + + +; Setup Stack for each mode ---------------------------------------------------- + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + + IF :DEF:__MICROLIB + EXPORT __initial_sp + ELSE + ENDIF + +; Enter the C code ------------------------------------------------------------- + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's cpsr to spsr + MSR spsr_cxsf, r4 + BIC r4, r4, #0x20 ; must be ARM mode + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + + END diff --git a/libcpu/arm/s3c24x0/context_rvds.S b/libcpu/arm/s3c24x0/context_rvds.S index 6fe5c5ea07acc5dd8df95fc4186afc1ccccb40dd..54d655afe1d2f6346d29cbaa30ab7d71423b9ecc 100644 --- a/libcpu/arm/s3c24x0/context_rvds.S +++ b/libcpu/arm/s3c24x0/context_rvds.S @@ -12,12 +12,12 @@ ; * 2009-01-20 Bernard first version ; */ -NOINT EQU 0xc0 ; disable interrupt in psr +NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 + AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1 + MSR cpsr_c, r1 BX lr - ENDP + ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 + MSR cpsr_c, r0 BX lr ENDP @@ -63,7 +63,7 @@ rt_hw_context_switch PROC MSR spsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc - ENDP + ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP + ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread + IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] + STR r1, [r2] BX lr - ENDP - + ENDP + END \ No newline at end of file diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c index a9845f4125dba918c9760839847c268281d044b6..907f08145aa9240603bfe2e7a124e5b455788cfa 100644 --- a/libcpu/arm/s3c24x0/cpu.c +++ b/libcpu/arm/s3c24x0/cpu.c @@ -1,190 +1,190 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - */ - -#include -#include -#include "s3c24x0.h" - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) - -#ifdef __GNUC__ -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} -#endif - -#ifdef __CC_ARM -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm - { - mrc p15, 0, i, c1, c0, 0 - } - - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} -#endif - -/** - * enable I-Cache - * - */ -void rt_hw_cpu_icache_enable() -{ - cache_enable(ICACHE_MASK); -} - -/** - * disable I-Cache - * - */ -void rt_hw_cpu_icache_disable() -{ - cache_disable(ICACHE_MASK); -} - -/** - * return the status of I-Cache - * - */ -rt_base_t rt_hw_cpu_icache_status() -{ - return (cp15_rd() & ICACHE_MASK); -} - -/** - * enable D-Cache - * - */ -void rt_hw_cpu_dcache_enable() -{ - cache_enable(DCACHE_MASK); -} - -/** - * disable D-Cache - * - */ -void rt_hw_cpu_dcache_disable() -{ - cache_disable(DCACHE_MASK); -} - -/** - * return the status of D-Cache - * - */ -rt_base_t rt_hw_cpu_dcache_status() -{ - return (cp15_rd() & DCACHE_MASK); -} - -/** - * reset cpu by dog's time-out - * - */ -void rt_hw_cpu_reset() -{ - /* Disable all interrupt except the WDT */ - INTMSK = (~((rt_uint32_t)1 << INTWDT)); - - /* Disable watchdog */ - WTCON = 0x0000; - - /* Initialize watchdog timer count register */ - WTCNT = 0x0001; - - /* Enable watchdog timer; assert reset at timer timeout */ - WTCON = 0x0021; - - while(1); /* loop forever and wait for reset to happen */ - - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -void rt_hw_cpu_shutdown() -{ - rt_uint32_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } -} - -/*@}*/ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + */ + +#include +#include +#include "s3c24x0.h" + +/** + * @addtogroup S3C24X0 + */ +/*@{*/ + +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) + +#ifdef __GNUC__ +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} +#endif + +#ifdef __CC_ARM +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + __asm + { + mrc p15, 0, i, c1, c0, 0 + } + + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} +#endif + +/** + * enable I-Cache + * + */ +void rt_hw_cpu_icache_enable() +{ + cache_enable(ICACHE_MASK); +} + +/** + * disable I-Cache + * + */ +void rt_hw_cpu_icache_disable() +{ + cache_disable(ICACHE_MASK); +} + +/** + * return the status of I-Cache + * + */ +rt_base_t rt_hw_cpu_icache_status() +{ + return (cp15_rd() & ICACHE_MASK); +} + +/** + * enable D-Cache + * + */ +void rt_hw_cpu_dcache_enable() +{ + cache_enable(DCACHE_MASK); +} + +/** + * disable D-Cache + * + */ +void rt_hw_cpu_dcache_disable() +{ + cache_disable(DCACHE_MASK); +} + +/** + * return the status of D-Cache + * + */ +rt_base_t rt_hw_cpu_dcache_status() +{ + return (cp15_rd() & DCACHE_MASK); +} + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + /* Disable all interrupt except the WDT */ + INTMSK = (~((rt_uint32_t)1 << INTWDT)); + + /* Disable watchdog */ + WTCON = 0x0000; + + /* Initialize watchdog timer count register */ + WTCNT = 0x0001; + + /* Enable watchdog timer; assert reset at timer timeout */ + WTCON = 0x0021; + + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c index cb14c4cab74340e5d4d882c19c277f92bcdc318b..2bc79deca62193ef277a067af6c50618b4afe1e3 100644 --- a/libcpu/arm/s3c24x0/mmu.c +++ b/libcpu/arm/s3c24x0/mmu.c @@ -1,394 +1,394 @@ -/* - * File : mmu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-04-25 Yi.qiu first version - * 2009-12-18 Bernard port to armcc - */ - -#include -#include "s3c24x0.h" - -#define _MMUTT_STARTADDRESS 0x33FF0000 - -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) - -#ifdef __GNUC__ -void mmu_setttbase(register rt_uint32_t i) -{ - asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); -} - -void mmu_set_domain(register rt_uint32_t i) -{ - asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); -} - -void mmu_enable() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= 0x1; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~0x1; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_icache() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 12); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_dcache() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 2); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_icache() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 12); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_dcache() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 2); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 1); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 1); - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_clean_invalidated_cache_index(int index) -{ - asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); -} - -void mmu_invalidate_tlb() -{ - asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); -} - -void mmu_invalidate_icache() -{ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); -} -#endif - -#ifdef __CC_ARM -void mmu_setttbase(rt_uint32_t i) -{ - __asm - { - mcr p15, 0, i, c2, c0, 0 - } -} - -void mmu_set_domain(rt_uint32_t i) -{ - __asm - { - mcr p15,0, i, c3, c0, 0 - } -} - -void mmu_enable() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_icache() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_dcache() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_icache() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_dcache() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_clean_invalidated_cache_index(int index) -{ - __asm - { - mcr p15, 0, index, c7, c14, 2 - } -} - -void mmu_invalidate_tlb() -{ - register rt_uint32_t value; - - value = 0; - __asm - { - mcr p15, 0, value, c8, c7, 0 - } -} - -void mmu_invalidate_icache() -{ - register rt_uint32_t value; - - value = 0; - - __asm - { - mcr p15, 0, value, c7, c5, 0 - } -} -#endif - -void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) -{ - volatile rt_uint32_t *pTT; - volatile int i,nSec; - pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20); - nSec=(vaddrEnd>>20)-(vaddrStart>>20); - for(i=0;i<=nSec;i++) - { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; - } -} - -void rt_hw_mmu_init(void) -{ - int i,j; - //========================== IMPORTANT NOTE ========================= - //The current stack and code area can't be re-mapped in this routine. - //If you want memory map mapped freely, your own sophiscated mmu - //initialization code is needed. - //=================================================================== - - mmu_disable_dcache(); - mmu_disable_icache(); - - //If write-back is used,the DCache should be cleared. - for(i=0;i<64;i++) - for(j=0;j<8;j++) - mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); - - mmu_invalidate_icache(); - - //To complete mmu_Init() fast, Icache may be turned on here. - mmu_enable_icache(); - - mmu_disable(); - mmu_invalidate_tlb(); - - //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); - mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 - mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 - mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 - mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 - mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 - mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 - //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 - mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 - mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 - //30f00000->30100000, 31000000->30200000 - mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 - mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 - - mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 - mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 - - mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR - mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR - mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR - mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used - mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR - - mmu_setttbase(_MMUTT_STARTADDRESS); - - /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ - mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); - - mmu_enable_alignfault(); - - mmu_enable(); - - /* ICache enable */ - mmu_enable_icache(); - /* DCache should be turned on after mmu is turned on. */ - mmu_enable_dcache(); -} - +/* + * File : mmu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-04-25 Yi.qiu first version + * 2009-12-18 Bernard port to armcc + */ + +#include +#include "s3c24x0.h" + +#define _MMUTT_STARTADDRESS 0x33FF0000 + +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) + +#ifdef __GNUC__ +void mmu_setttbase(register rt_uint32_t i) +{ + asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); +} + +void mmu_set_domain(register rt_uint32_t i) +{ + asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); +} + +void mmu_enable() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= 0x1; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~0x1; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_icache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 12); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_dcache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 2); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_icache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 12); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_dcache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 2); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 1); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 1); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_clean_invalidated_cache_index(int index) +{ + asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); +} + +void mmu_invalidate_tlb() +{ + asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); +} + +void mmu_invalidate_icache() +{ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); +} +#endif + +#ifdef __CC_ARM +void mmu_setttbase(rt_uint32_t i) +{ + __asm + { + mcr p15, 0, i, c2, c0, 0 + } +} + +void mmu_set_domain(rt_uint32_t i) +{ + __asm + { + mcr p15,0, i, c3, c0, 0 + } +} + +void mmu_enable() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_icache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_dcache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_icache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_dcache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_clean_invalidated_cache_index(int index) +{ + __asm + { + mcr p15, 0, index, c7, c14, 2 + } +} + +void mmu_invalidate_tlb() +{ + register rt_uint32_t value; + + value = 0; + __asm + { + mcr p15, 0, value, c8, c7, 0 + } +} + +void mmu_invalidate_icache() +{ + register rt_uint32_t value; + + value = 0; + + __asm + { + mcr p15, 0, value, c7, c5, 0 + } +} +#endif + +void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) +{ + volatile rt_uint32_t *pTT; + volatile int i,nSec; + pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20); + nSec=(vaddrEnd>>20)-(vaddrStart>>20); + for(i=0;i<=nSec;i++) + { + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; + } +} + +void rt_hw_mmu_init(void) +{ + int i,j; + //========================== IMPORTANT NOTE ========================= + //The current stack and code area can't be re-mapped in this routine. + //If you want memory map mapped freely, your own sophiscated mmu + //initialization code is needed. + //=================================================================== + + mmu_disable_dcache(); + mmu_disable_icache(); + + //If write-back is used,the DCache should be cleared. + for(i=0;i<64;i++) + for(j=0;j<8;j++) + mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); + + mmu_invalidate_icache(); + + //To complete mmu_Init() fast, Icache may be turned on here. + mmu_enable_icache(); + + mmu_disable(); + mmu_invalidate_tlb(); + + //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); + mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 + mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 + mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 + mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 + mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 + mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 + //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 + mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 + mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 + //30f00000->30100000, 31000000->30200000 + mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 + mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 + + mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 + mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 + + mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR + mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR + mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR + mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used + mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR + + mmu_setttbase(_MMUTT_STARTADDRESS); + + /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ + mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); + + mmu_enable_alignfault(); + + mmu_enable(); + + /* ICache enable */ + mmu_enable_icache(); + /* DCache should be turned on after mmu is turned on. */ + mmu_enable_dcache(); +} + diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c index 5d1193586f51801e84d2bbcd73399012a7af73d5..0f05acd687584707d750bd77cdf2f8817a569062 100644 --- a/libcpu/arm/s3c24x0/rtc.c +++ b/libcpu/arm/s3c24x0/rtc.c @@ -1,189 +1,189 @@ -/* - * File : rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-04-26 yi.qiu first version - * 2010-03-18 Gary Lee add functions such as GregorianDay - * and rtc_time_to_tm - * 2009-03-20 yi.qiu clean up - */ - -#include -#include -#include - -// #define RTC_DEBUG - -#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ -#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ -#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) -#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) - -/** - * This function get rtc time - */ -void rt_hw_rtc_get(struct tm *ti) -{ - rt_uint8_t sec, min, hour, mday, wday, mon, year; - - /* enable access to RTC registers */ - RTCCON |= RTC_ENABLE; - - /* read RTC registers */ - do - { - sec = BCDSEC; - min = BCDMIN; - hour = BCDHOUR; - mday = BCDDATE; - wday = BCDDAY; - mon = BCDMON; - year = BCDYEAR; - } while (sec != BCDSEC); - -#ifdef RTC_DEBUG - rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", - sec, min, hour, mday, wday, mon, year); -#endif - - /* disable access to RTC registers */ - RTC_DISABLE - - ti->tm_sec = BCD2BIN(sec & 0x7F); - ti->tm_min = BCD2BIN(min & 0x7F); - ti->tm_hour = BCD2BIN(hour & 0x3F); - ti->tm_mday = BCD2BIN(mday & 0x3F); - ti->tm_mon = BCD2BIN(mon & 0x1F); - ti->tm_year = BCD2BIN(year); - ti->tm_wday = BCD2BIN(wday & 0x07); - ti->tm_yday = 0; - ti->tm_isdst = 0; -} - -/** - * This function set rtc time - */ -void rt_hw_rtc_set(struct tm *ti) -{ - rt_uint8_t sec, min, hour, mday, wday, mon, year; - - year = BIN2BCD(ti->tm_year); - mon = BIN2BCD(ti->tm_mon); - wday = BIN2BCD(ti->tm_wday); - mday = BIN2BCD(ti->tm_mday); - hour = BIN2BCD(ti->tm_hour); - min = BIN2BCD(ti->tm_min); - sec = BIN2BCD(ti->tm_sec); - - /* enable access to RTC registers */ - RTC_ENABLE - - do{ - /* write RTC registers */ - BCDSEC = sec; - BCDMIN = min; - BCDHOUR = hour; - BCDDATE = mday; - BCDDAY = wday; - BCDMON = mon; - BCDYEAR = year; - }while (sec != BCDSEC); - - /* disable access to RTC registers */ - RTC_DISABLE -} - -/** - * This function reset rtc - */ -void rt_hw_rtc_reset (void) -{ - RTCCON = (RTCCON & ~0x06) | 0x08; - RTCCON &= ~(0x08|0x01); -} - -static struct rt_device rtc; -static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag) -{ - RTC_ENABLE - return RT_EOK; -} - -static rt_err_t rtc_close(rt_device_t dev) -{ - RTC_DISABLE - return RT_EOK; -} - -static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - return RT_EOK; -} - -static rt_err_t rtc_control(rt_device_t dev, rt_uint8_t cmd, void *args) -{ - struct tm tm, *tm_ptr; - time_t *time; - RT_ASSERT(dev != RT_NULL); - - time = (time_t *)args; - switch (cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - /* read device */ - rt_hw_rtc_get(&tm); - *((rt_time_t *)args) = mktime(&tm); - break; - - case RT_DEVICE_CTRL_RTC_SET_TIME: - tm_ptr = localtime(time); - /* write device */ - rt_hw_rtc_set(tm_ptr); - break; - } - - return RT_EOK; -} - -void rt_hw_rtc_init(void) -{ - rtc.type = RT_Device_Class_RTC; - - /* register rtc device */ - rtc.init = RT_NULL; - rtc.open = rtc_open; - rtc.close = rtc_close; - rtc.read = rtc_read; - rtc.write = RT_NULL; - rtc.control = rtc_control; - - /* no private */ - rtc.user_data = RT_NULL; - - rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); -} - -#ifdef RT_USING_FINSH -#include -void list_date() -{ - time_t time; - rt_device_t device; - - device = rt_device_find("rtc"); - if (device != RT_NULL) - { - rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); - - rt_kprintf("%d, %s\n", time, ctime(&time)); - } -} -FINSH_FUNCTION_EXPORT(list_date, list date); -#endif +/* + * File : rtc.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-04-26 yi.qiu first version + * 2010-03-18 Gary Lee add functions such as GregorianDay + * and rtc_time_to_tm + * 2009-03-20 yi.qiu clean up + */ + +#include +#include +#include + +// #define RTC_DEBUG + +#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ +#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ +#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) +#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) + +/** + * This function get rtc time + */ +void rt_hw_rtc_get(struct tm *ti) +{ + rt_uint8_t sec, min, hour, mday, wday, mon, year; + + /* enable access to RTC registers */ + RTCCON |= RTC_ENABLE; + + /* read RTC registers */ + do + { + sec = BCDSEC; + min = BCDMIN; + hour = BCDHOUR; + mday = BCDDATE; + wday = BCDDAY; + mon = BCDMON; + year = BCDYEAR; + } while (sec != BCDSEC); + +#ifdef RTC_DEBUG + rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", + sec, min, hour, mday, wday, mon, year); +#endif + + /* disable access to RTC registers */ + RTC_DISABLE + + ti->tm_sec = BCD2BIN(sec & 0x7F); + ti->tm_min = BCD2BIN(min & 0x7F); + ti->tm_hour = BCD2BIN(hour & 0x3F); + ti->tm_mday = BCD2BIN(mday & 0x3F); + ti->tm_mon = BCD2BIN(mon & 0x1F); + ti->tm_year = BCD2BIN(year); + ti->tm_wday = BCD2BIN(wday & 0x07); + ti->tm_yday = 0; + ti->tm_isdst = 0; +} + +/** + * This function set rtc time + */ +void rt_hw_rtc_set(struct tm *ti) +{ + rt_uint8_t sec, min, hour, mday, wday, mon, year; + + year = BIN2BCD(ti->tm_year); + mon = BIN2BCD(ti->tm_mon); + wday = BIN2BCD(ti->tm_wday); + mday = BIN2BCD(ti->tm_mday); + hour = BIN2BCD(ti->tm_hour); + min = BIN2BCD(ti->tm_min); + sec = BIN2BCD(ti->tm_sec); + + /* enable access to RTC registers */ + RTC_ENABLE + + do{ + /* write RTC registers */ + BCDSEC = sec; + BCDMIN = min; + BCDHOUR = hour; + BCDDATE = mday; + BCDDAY = wday; + BCDMON = mon; + BCDYEAR = year; + }while (sec != BCDSEC); + + /* disable access to RTC registers */ + RTC_DISABLE +} + +/** + * This function reset rtc + */ +void rt_hw_rtc_reset (void) +{ + RTCCON = (RTCCON & ~0x06) | 0x08; + RTCCON &= ~(0x08|0x01); +} + +static struct rt_device rtc; +static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + RTC_ENABLE + return RT_EOK; +} + +static rt_err_t rtc_close(rt_device_t dev) +{ + RTC_DISABLE + return RT_EOK; +} + +static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + return RT_EOK; +} + +static rt_err_t rtc_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + struct tm tm, *tm_ptr; + time_t *time; + RT_ASSERT(dev != RT_NULL); + + time = (time_t *)args; + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + /* read device */ + rt_hw_rtc_get(&tm); + *((rt_time_t *)args) = mktime(&tm); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + tm_ptr = localtime(time); + /* write device */ + rt_hw_rtc_set(tm_ptr); + break; + } + + return RT_EOK; +} + +void rt_hw_rtc_init(void) +{ + rtc.type = RT_Device_Class_RTC; + + /* register rtc device */ + rtc.init = RT_NULL; + rtc.open = rtc_open; + rtc.close = rtc_close; + rtc.read = rtc_read; + rtc.write = RT_NULL; + rtc.control = rtc_control; + + /* no private */ + rtc.user_data = RT_NULL; + + rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); +} + +#ifdef RT_USING_FINSH +#include +void list_date() +{ + time_t time; + rt_device_t device; + + device = rt_device_find("rtc"); + if (device != RT_NULL) + { + rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); + + rt_kprintf("%d, %s\n", time, ctime(&time)); + } +} +FINSH_FUNCTION_EXPORT(list_date, list date); +#endif diff --git a/libcpu/arm/s3c24x0/rtc.h b/libcpu/arm/s3c24x0/rtc.h index fa4ea397eaeddd062576f724da10c1837b711d9a..f7073e259be3b0ffc4346d46d1754a692bf0c1be 100644 --- a/libcpu/arm/s3c24x0/rtc.h +++ b/libcpu/arm/s3c24x0/rtc.h @@ -1,21 +1,21 @@ -/* - * File : rtc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-03-20 yi.qiu the first version - */ - -#ifndef __RTC_H__ -#define __RTC_H__ - -void rt_hw_rtc_init(void); - -#endif - +/* + * File : rtc.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-20 yi.qiu the first version + */ + +#ifndef __RTC_H__ +#define __RTC_H__ + +void rt_hw_rtc_init(void); + +#endif + diff --git a/libcpu/arm/s3c24x0/s3c24x0.h b/libcpu/arm/s3c24x0/s3c24x0.h index c5de9ee396035bf61bbbb48f6c11d157bf7db0a5..8308148c3b49db20e6c3407c776ad7b002d958eb 100644 --- a/libcpu/arm/s3c24x0/s3c24x0.h +++ b/libcpu/arm/s3c24x0/s3c24x0.h @@ -1,611 +1,611 @@ -/* - * File : s3c24x0.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-12-11 Bernard first version - */ - -#ifndef __S3C24X0_H__ -#define __S3C24X0_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -// Memory control -#define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status -#define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control -#define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control -#define BANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl -#define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control -#define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control -#define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control -#define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control -#define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control -#define REFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM efresh -#define BANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size -#define MRSRB6 (*(volatile unsigned *)0x4800002c) //Mode egister set for SDRAM -#define MRSRB7 (*(volatile unsigned *)0x48000030) //Mode egister set for SDRAM - - -// USB Host - - -// INTERRUPT -#define SRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status -#define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control -#define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control -#define PRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control -#define INTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status -#define INTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset -#define SUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending -#define INTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask - - -// DMA -#define DISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source -#define DISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control -#define DIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination -#define DIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control -#define DCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control -#define DSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status -#define DCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source -#define DCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination -#define DMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger - -#define DISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source -#define DISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control -#define DIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination -#define DIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control -#define DCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control -#define DSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status -#define DCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source -#define DCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination -#define DMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger - -#define DISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source -#define DISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control -#define DIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination -#define DIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control -#define DCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control -#define DSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status -#define DCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source -#define DCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination -#define DMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger - -#define DISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source -#define DISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control -#define DIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination -#define DIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control -#define DCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control -#define DSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status -#define DCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source -#define DCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination -#define DMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger - - -// CLOCK & POWER MANAGEMENT -#define LOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter -#define MPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control -#define UPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control -#define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control -#define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control -#define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control -#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control - - -// LCD CONTROLLER -#define LCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1 -#define LCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2 -#define LCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3 -#define LCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4 -#define LCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5 -#define LCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1 -#define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2 -#define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set -#define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table -#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table -#define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table -#define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode -#define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette -#define LCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending -#define LCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source -#define LCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask -#define LPCSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control -#define PALETTE 0x4d000400 //Palette start address - - -// NAND flash -#define NFCONF (*(volatile unsigned *)0x4e000000) //NAND Flash configuration -#define NFCMD (*(volatile unsigned *)0x4e000004) //NADD Flash command -#define NFADDR (*(volatile unsigned *)0x4e000008) //NAND Flash address -#define NFDATA (*(volatile unsigned *)0x4e00000c) //NAND Flash data -#define NFSTAT (*(volatile unsigned *)0x4e000010) //NAND Flash operation status -#define NFECC (*(volatile unsigned *)0x4e000014) //NAND Flash ECC -#define NFECC0 (*(volatile unsigned *)0x4e000014) -#define NFECC1 (*(volatile unsigned *)0x4e000015) -#define NFECC2 (*(volatile unsigned *)0x4e000016) - -// UART -#define U0BASE (*(volatile unsigned *)0x50000000) //UART 0 Line control -#define ULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control -#define UCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control -#define UFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control -#define UMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control -#define USTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status -#define URXB0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status -#define UFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status -#define UMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status -#define UBRD0 (*(volatile unsigned *)0x50000028) //UART 0 Baud ate divisor - -#define U1BASE (*(volatile unsigned *)0x50004000) //UART 1 Line control -#define ULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control -#define UCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control -#define UFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control -#define UMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control -#define USTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status -#define URXB1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status -#define UFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status -#define UMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status -#define UBRD1 (*(volatile unsigned *)0x50004028) //UART 1 Baud ate divisor - -#define U2BASE *(volatile unsigned *)0x50008000 //UART 2 Line control -#define ULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control -#define UCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control -#define UFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control -#define UMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control -#define USTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status -#define URXB2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status -#define UFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status -#define UMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status -#define UBRD2 (*(volatile unsigned *)0x50008028) //UART 2 Baud ate divisor - -#ifdef __BIG_ENDIAN -#define UTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold -#define URXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer -#define UTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold -#define URXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer -#define UTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold -#define URXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer - -#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch) -#define RdURXH0() (*(volatile unsigned char *)0x50000027) -#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch) -#define RdURXH1() (*(volatile unsigned char *)0x50004027) -#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch) -#define RdURXH2() (*(volatile unsigned char *)0x50008027) - -#else //Little Endian -#define UTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold -#define URXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer -#define UTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold -#define URXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer -#define UTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold -#define URXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer - -#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) -#define RdURXH0() (*(volatile unsigned char *)0x50000024) -#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) -#define RdURXH1() (*(volatile unsigned char *)0x50004024) -#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) -#define RdURXH2() (*(volatile unsigned char *)0x50008024) - -#endif - - -// PWM TIMER -#define TCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration -#define TCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration -#define TCON (*(volatile unsigned *)0x51000008) //Timer control -#define TCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0 -#define TCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0 -#define TCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0 -#define TCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1 -#define TCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1 -#define TCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1 -#define TCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2 -#define TCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2 -#define TCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2 -#define TCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3 -#define TCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3 -#define TCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3 -#define TCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4 -#define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4 - -// Added for 2440 -#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) -#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 -#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 -#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register - - -// USB DEVICE -#ifdef __BIG_ENDIAN -#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address -#define PWR_REG (*(volatile unsigned char *)0x52000147) //Power management -#define EP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear -#define USB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear -#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable -#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016f) -#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte -#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte -#define INDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index -#define MAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet -#define EP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status -#define IN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status -#define IN_CSR2_REG (*(volatile unsigned char *)0x5200018b) -#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status -#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000197) -#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count -#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f) -#define EP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO -#define EP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO -#define EP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO -#define EP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO -#define EP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO -#define EP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control -#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter -#define EP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter -#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter -#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213) -#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217) -#define EP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control -#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter -#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter -#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter -#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b) -#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f) -#define EP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control -#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter -#define EP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter -#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter -#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253) -#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257) -#define EP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control -#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter -#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter -#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter -#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b) -#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f) - -#else // Little Endian -#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address -#define PWR_REG (*(volatile unsigned char *)0x52000144) //Power management -#define EP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear -#define USB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear -#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable -#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016c) -#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte -#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte -#define INDEX_REG (*(volatile unsigned char *)0x52000178) //Register index -#define MAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet -#define EP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status -#define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status -#define IN_CSR2_REG (*(volatile unsigned char *)0x52000188) -#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status -#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194) -#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count -#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c) -#define EP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO -#define EP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO -#define EP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO -#define EP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO -#define EP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO -#define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control -#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter -#define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter -#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter -#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210) -#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214) -#define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control -#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter -#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter -#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter -#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228) -#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c) -#define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control -#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter -#define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter -#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter -#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250) -#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254) -#define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control -#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter -#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter -#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter -#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268) -#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c) -#endif // __BIG_ENDIAN - - -// WATCH DOG TIMER -#define WTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode -#define WTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data -#define WTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count - - -// IIC -#define IICCON (*(volatile unsigned *)0x54000000) //IIC control -#define IICSTAT (*(volatile unsigned *)0x54000004) //IIC status -#define IICADD (*(volatile unsigned *)0x54000008) //IIC address -#define IICDS (*(volatile unsigned *)0x5400000c) //IIC data shift - - -// IIS -#define IISCON (*(volatile unsigned *)0x55000000) //IIS Control -#define IISMOD (*(volatile unsigned *)0x55000004) //IIS Mode -#define IISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler -#define IISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control - -#ifdef __BIG_ENDIAN -#define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry - -#else //Little Endian -#define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry - -#endif - - -// I/O PORT -#define GPACON (*(volatile unsigned *)0x56000000) //Port A control -#define GPADAT (*(volatile unsigned *)0x56000004) //Port A data - -#define GPBCON (*(volatile unsigned *)0x56000010) //Port B control -#define GPBDAT (*(volatile unsigned *)0x56000014) //Port B data -#define GPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B - -#define GPCCON (*(volatile unsigned *)0x56000020) //Port C control -#define GPCDAT (*(volatile unsigned *)0x56000024) //Port C data -#define GPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C - -#define GPDCON (*(volatile unsigned *)0x56000030) //Port D control -#define GPDDAT (*(volatile unsigned *)0x56000034) //Port D data -#define GPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D - -#define GPECON (*(volatile unsigned *)0x56000040) //Port E control -#define GPEDAT (*(volatile unsigned *)0x56000044) //Port E data -#define GPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E - -#define GPFCON (*(volatile unsigned *)0x56000050) //Port F control -#define GPFDAT (*(volatile unsigned *)0x56000054) //Port F data -#define GPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F - -#define GPGCON (*(volatile unsigned *)0x56000060) //Port G control -#define GPGDAT (*(volatile unsigned *)0x56000064) //Port G data -#define GPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G - -#define GPHCON (*(volatile unsigned *)0x56000070) //Port H control -#define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data -#define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H - -#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control -#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data -#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J - -#define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control -#define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control -#define EXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control egister 0 -#define EXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control egister 1 -#define EXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control egister 2 -#define EINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved -#define EINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved -#define EINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control egister 2 -#define EINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control egister 3 -#define EINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask -#define EINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending -#define GSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status -#define GSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32410000) -#define GSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type -#define GSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode -#define GSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode - - -// RTC -#ifdef __BIG_ENDIAN -#define RTCCON (*(volatile unsigned char *)0x57000043) //RTC control -#define TICNT (*(volatile unsigned char *)0x57000047) //Tick time count -#define RTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control -#define ALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second -#define ALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute -#define ALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour -#define ALMDATE (*(volatile unsigned char *)0x57000063) //Alarm day <-- May 06, 2002 SOP -#define ALMMON (*(volatile unsigned char *)0x57000067) //Alarm month -#define ALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year -#define RTCRST (*(volatile unsigned char *)0x5700006f) //RTC ound eset -#define BCDSEC (*(volatile unsigned char *)0x57000073) //BCD second -#define BCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute -#define BCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour -#define BCDDATE (*(volatile unsigned char *)0x5700007f) //BCD day <-- May 06, 2002 SOP -#define BCDDAY (*(volatile unsigned char *)0x57000083) //BCD date <-- May 06, 2002 SOP -#define BCDMON (*(volatile unsigned char *)0x57000087) //BCD month -#define BCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year - -#else //Little Endian -#define RTCCON (*(volatile unsigned char *)0x57000040) //RTC control -#define TICNT (*(volatile unsigned char *)0x57000044) //Tick time count -#define RTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control -#define ALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second -#define ALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute -#define ALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour -#define ALMDATE (*(volatile unsigned char *)0x57000060) //Alarm day <-- May 06, 2002 SOP -#define ALMMON (*(volatile unsigned char *)0x57000064) //Alarm month -#define ALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year -#define RTCRST (*(volatile unsigned char *)0x5700006c) //RTC ound eset -#define BCDSEC (*(volatile unsigned char *)0x57000070) //BCD second -#define BCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute -#define BCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour -#define BCDDATE (*(volatile unsigned char *)0x5700007c) //BCD day <-- May 06, 2002 SOP -#define BCDDAY (*(volatile unsigned char *)0x57000080) //BCD date <-- May 06, 2002 SOP -#define BCDMON (*(volatile unsigned char *)0x57000084) //BCD month -#define BCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year -#endif //RTC - - -// ADC -#define ADCCON (*(volatile unsigned *)0x58000000) //ADC control -#define ADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control -#define ADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay -#define ADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0 -#define ADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1 - -// SPI -#define SPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control -#define SPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status -#define SPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control -#define SPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud ate prescaler -#define SPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data -#define SPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data - -#define SPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control -#define SPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status -#define SPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control -#define SPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud ate prescaler -#define SPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data -#define SPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data - - -// SD Interface -#define SDICON (*(volatile unsigned *)0x5a000000) //SDI control -#define SDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud ate prescaler -#define SDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument -#define SDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control -#define SDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status -#define SDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI esponse 0 -#define SDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI esponse 1 -#define SDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI esponse 2 -#define SDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI esponse 3 -#define SDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer -#define SDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size -#define SDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control -#define SDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data emain counter -#define SDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status -#define SDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status -#define SDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask - -#ifdef __BIG_ENDIAN /* edited for 2440A */ -#define SDIDAT (*(volatile unsigned *)0x5a00004c) -#else // Little Endian -#define SDIDAT (*(volatile unsigned *)0x5a000040) -#endif //SD Interface - -// PENDING BIT -#define INTEINT0 (0) -#define INTEINT1 (1) -#define INTEINT2 (2) -#define INTEINT3 (3) -#define INTEINT4_7 (4) -#define INTEINT8_23 (5) -#define INTNOTUSED6 (6) -#define INTBAT_FLT (7) -#define INTTICK (8) -#define INTWDT (9) -#define INTTIMER0 (10) -#define INTTIMER1 (11) -#define INTTIMER2 (12) -#define INTTIMER3 (13) -#define INTTIMER4 (14) -#define INTUART2 (15) -#define INTLCD (16) -#define INTDMA0 (17) -#define INTDMA1 (18) -#define INTDMA2 (19) -#define INTDMA3 (20) -#define INTSDI (21) -#define INTSPI0 (22) -#define INTUART1 (23) -//#define INTNOTUSED24 (24) -#define INTNIC (24) -#define INTUSBD (25) -#define INTUSBH (26) -#define INTIIC (27) -#define INTUART0 (28) -#define INTSPI1 (29) -#define INTRTC (30) -#define INTADC (31) -#define BIT_ALLMSK (0xffffffff) - -#define BIT_SUB_ALLMSK (0x7ff) -#define INTSUB_ADC (10) -#define INTSUB_TC (9) -#define INTSUB_ERR2 (8) -#define INTSUB_TXD2 (7) -#define INTSUB_RXD2 (6) -#define INTSUB_ERR1 (5) -#define INTSUB_TXD1 (4) -#define INTSUB_RXD1 (3) -#define INTSUB_ERR0 (2) -#define INTSUB_TXD0 (1) -#define INTSUB_RXD0 (0) - -#define BIT_SUB_ADC (0x1<<10) -#define BIT_SUB_TC (0x1<<9) -#define BIT_SUB_ERR2 (0x1<<8) -#define BIT_SUB_TXD2 (0x1<<7) -#define BIT_SUB_RXD2 (0x1<<6) -#define BIT_SUB_ERR1 (0x1<<5) -#define BIT_SUB_TXD1 (0x1<<4) -#define BIT_SUB_RXD1 (0x1<<3) -#define BIT_SUB_ERR0 (0x1<<2) -#define BIT_SUB_TXD0 (0x1<<1) -#define BIT_SUB_RXD0 (0x1<<0) - -#define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;} -//Wait until INTPND is changed for the case that the ISR is very short. - -#define INTGLOBAL 32 - -/*****************************/ -/* CPU Mode */ -/*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -struct rt_hw_register -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; -}; - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif +/* + * File : s3c24x0.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-12-11 Bernard first version + */ + +#ifndef __S3C24X0_H__ +#define __S3C24X0_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @addtogroup S3C24X0 + */ +/*@{*/ + +// Memory control +#define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status +#define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control +#define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control +#define BANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl +#define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control +#define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control +#define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control +#define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control +#define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control +#define REFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM efresh +#define BANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size +#define MRSRB6 (*(volatile unsigned *)0x4800002c) //Mode egister set for SDRAM +#define MRSRB7 (*(volatile unsigned *)0x48000030) //Mode egister set for SDRAM + + +// USB Host + + +// INTERRUPT +#define SRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status +#define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control +#define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control +#define PRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control +#define INTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status +#define INTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset +#define SUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending +#define INTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask + + +// DMA +#define DISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source +#define DISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control +#define DIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination +#define DIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control +#define DCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control +#define DSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status +#define DCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source +#define DCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination +#define DMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger + +#define DISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source +#define DISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control +#define DIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination +#define DIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control +#define DCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control +#define DSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status +#define DCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source +#define DCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination +#define DMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger + +#define DISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source +#define DISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control +#define DIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination +#define DIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control +#define DCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control +#define DSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status +#define DCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source +#define DCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination +#define DMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger + +#define DISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source +#define DISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control +#define DIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination +#define DIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control +#define DCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control +#define DSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status +#define DCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source +#define DCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination +#define DMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger + + +// CLOCK & POWER MANAGEMENT +#define LOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter +#define MPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control +#define UPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control +#define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control +#define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control +#define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control +#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control + + +// LCD CONTROLLER +#define LCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1 +#define LCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2 +#define LCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3 +#define LCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4 +#define LCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5 +#define LCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1 +#define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2 +#define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set +#define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table +#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table +#define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table +#define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode +#define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette +#define LCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending +#define LCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source +#define LCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask +#define LPCSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control +#define PALETTE 0x4d000400 //Palette start address + + +// NAND flash +#define NFCONF (*(volatile unsigned *)0x4e000000) //NAND Flash configuration +#define NFCMD (*(volatile unsigned *)0x4e000004) //NADD Flash command +#define NFADDR (*(volatile unsigned *)0x4e000008) //NAND Flash address +#define NFDATA (*(volatile unsigned *)0x4e00000c) //NAND Flash data +#define NFSTAT (*(volatile unsigned *)0x4e000010) //NAND Flash operation status +#define NFECC (*(volatile unsigned *)0x4e000014) //NAND Flash ECC +#define NFECC0 (*(volatile unsigned *)0x4e000014) +#define NFECC1 (*(volatile unsigned *)0x4e000015) +#define NFECC2 (*(volatile unsigned *)0x4e000016) + +// UART +#define U0BASE (*(volatile unsigned *)0x50000000) //UART 0 Line control +#define ULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control +#define UCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control +#define UFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control +#define UMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control +#define USTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status +#define URXB0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status +#define UFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status +#define UMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status +#define UBRD0 (*(volatile unsigned *)0x50000028) //UART 0 Baud ate divisor + +#define U1BASE (*(volatile unsigned *)0x50004000) //UART 1 Line control +#define ULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control +#define UCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control +#define UFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control +#define UMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control +#define USTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status +#define URXB1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status +#define UFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status +#define UMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status +#define UBRD1 (*(volatile unsigned *)0x50004028) //UART 1 Baud ate divisor + +#define U2BASE *(volatile unsigned *)0x50008000 //UART 2 Line control +#define ULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control +#define UCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control +#define UFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control +#define UMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control +#define USTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status +#define URXB2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status +#define UFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status +#define UMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status +#define UBRD2 (*(volatile unsigned *)0x50008028) //UART 2 Baud ate divisor + +#ifdef __BIG_ENDIAN +#define UTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold +#define URXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer +#define UTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold +#define URXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer +#define UTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold +#define URXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000027) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004027) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008027) + +#else //Little Endian +#define UTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold +#define URXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer +#define UTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold +#define URXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer +#define UTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold +#define URXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000024) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004024) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008024) + +#endif + + +// PWM TIMER +#define TCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration +#define TCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration +#define TCON (*(volatile unsigned *)0x51000008) //Timer control +#define TCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0 +#define TCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0 +#define TCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0 +#define TCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1 +#define TCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1 +#define TCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1 +#define TCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2 +#define TCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2 +#define TCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2 +#define TCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3 +#define TCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3 +#define TCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3 +#define TCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4 +#define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4 + +// Added for 2440 +#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) +#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 +#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 +#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register + + +// USB DEVICE +#ifdef __BIG_ENDIAN +#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address +#define PWR_REG (*(volatile unsigned char *)0x52000147) //Power management +#define EP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear +#define USB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear +#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable +#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016f) +#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte +#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte +#define INDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index +#define MAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet +#define EP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status +#define IN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status +#define IN_CSR2_REG (*(volatile unsigned char *)0x5200018b) +#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status +#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000197) +#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count +#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f) +#define EP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO +#define EP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO +#define EP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO +#define EP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO +#define EP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO +#define EP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control +#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter +#define EP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter +#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter +#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213) +#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217) +#define EP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control +#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter +#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter +#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter +#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b) +#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f) +#define EP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control +#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter +#define EP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter +#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter +#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253) +#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257) +#define EP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control +#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter +#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter +#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter +#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b) +#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f) + +#else // Little Endian +#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address +#define PWR_REG (*(volatile unsigned char *)0x52000144) //Power management +#define EP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear +#define USB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear +#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable +#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016c) +#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte +#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte +#define INDEX_REG (*(volatile unsigned char *)0x52000178) //Register index +#define MAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet +#define EP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status +#define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status +#define IN_CSR2_REG (*(volatile unsigned char *)0x52000188) +#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status +#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194) +#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count +#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c) +#define EP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO +#define EP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO +#define EP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO +#define EP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO +#define EP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO +#define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control +#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter +#define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter +#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter +#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210) +#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214) +#define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control +#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter +#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter +#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter +#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228) +#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c) +#define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control +#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter +#define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter +#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter +#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250) +#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254) +#define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control +#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter +#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter +#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter +#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268) +#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c) +#endif // __BIG_ENDIAN + + +// WATCH DOG TIMER +#define WTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode +#define WTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data +#define WTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count + + +// IIC +#define IICCON (*(volatile unsigned *)0x54000000) //IIC control +#define IICSTAT (*(volatile unsigned *)0x54000004) //IIC status +#define IICADD (*(volatile unsigned *)0x54000008) //IIC address +#define IICDS (*(volatile unsigned *)0x5400000c) //IIC data shift + + +// IIS +#define IISCON (*(volatile unsigned *)0x55000000) //IIS Control +#define IISMOD (*(volatile unsigned *)0x55000004) //IIS Mode +#define IISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler +#define IISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control + +#ifdef __BIG_ENDIAN +#define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry + +#else //Little Endian +#define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry + +#endif + + +// I/O PORT +#define GPACON (*(volatile unsigned *)0x56000000) //Port A control +#define GPADAT (*(volatile unsigned *)0x56000004) //Port A data + +#define GPBCON (*(volatile unsigned *)0x56000010) //Port B control +#define GPBDAT (*(volatile unsigned *)0x56000014) //Port B data +#define GPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B + +#define GPCCON (*(volatile unsigned *)0x56000020) //Port C control +#define GPCDAT (*(volatile unsigned *)0x56000024) //Port C data +#define GPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C + +#define GPDCON (*(volatile unsigned *)0x56000030) //Port D control +#define GPDDAT (*(volatile unsigned *)0x56000034) //Port D data +#define GPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D + +#define GPECON (*(volatile unsigned *)0x56000040) //Port E control +#define GPEDAT (*(volatile unsigned *)0x56000044) //Port E data +#define GPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E + +#define GPFCON (*(volatile unsigned *)0x56000050) //Port F control +#define GPFDAT (*(volatile unsigned *)0x56000054) //Port F data +#define GPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F + +#define GPGCON (*(volatile unsigned *)0x56000060) //Port G control +#define GPGDAT (*(volatile unsigned *)0x56000064) //Port G data +#define GPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G + +#define GPHCON (*(volatile unsigned *)0x56000070) //Port H control +#define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data +#define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H + +#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control +#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data +#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J + +#define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control +#define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control +#define EXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control egister 0 +#define EXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control egister 1 +#define EXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control egister 2 +#define EINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved +#define EINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved +#define EINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control egister 2 +#define EINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control egister 3 +#define EINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask +#define EINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending +#define GSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status +#define GSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32410000) +#define GSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type +#define GSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode +#define GSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode + + +// RTC +#ifdef __BIG_ENDIAN +#define RTCCON (*(volatile unsigned char *)0x57000043) //RTC control +#define TICNT (*(volatile unsigned char *)0x57000047) //Tick time count +#define RTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control +#define ALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second +#define ALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute +#define ALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour +#define ALMDATE (*(volatile unsigned char *)0x57000063) //Alarm day <-- May 06, 2002 SOP +#define ALMMON (*(volatile unsigned char *)0x57000067) //Alarm month +#define ALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year +#define RTCRST (*(volatile unsigned char *)0x5700006f) //RTC ound eset +#define BCDSEC (*(volatile unsigned char *)0x57000073) //BCD second +#define BCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute +#define BCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour +#define BCDDATE (*(volatile unsigned char *)0x5700007f) //BCD day <-- May 06, 2002 SOP +#define BCDDAY (*(volatile unsigned char *)0x57000083) //BCD date <-- May 06, 2002 SOP +#define BCDMON (*(volatile unsigned char *)0x57000087) //BCD month +#define BCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year + +#else //Little Endian +#define RTCCON (*(volatile unsigned char *)0x57000040) //RTC control +#define TICNT (*(volatile unsigned char *)0x57000044) //Tick time count +#define RTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control +#define ALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second +#define ALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute +#define ALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour +#define ALMDATE (*(volatile unsigned char *)0x57000060) //Alarm day <-- May 06, 2002 SOP +#define ALMMON (*(volatile unsigned char *)0x57000064) //Alarm month +#define ALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year +#define RTCRST (*(volatile unsigned char *)0x5700006c) //RTC ound eset +#define BCDSEC (*(volatile unsigned char *)0x57000070) //BCD second +#define BCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute +#define BCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour +#define BCDDATE (*(volatile unsigned char *)0x5700007c) //BCD day <-- May 06, 2002 SOP +#define BCDDAY (*(volatile unsigned char *)0x57000080) //BCD date <-- May 06, 2002 SOP +#define BCDMON (*(volatile unsigned char *)0x57000084) //BCD month +#define BCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year +#endif //RTC + + +// ADC +#define ADCCON (*(volatile unsigned *)0x58000000) //ADC control +#define ADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control +#define ADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay +#define ADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0 +#define ADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1 + +// SPI +#define SPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control +#define SPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status +#define SPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control +#define SPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud ate prescaler +#define SPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data +#define SPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data + +#define SPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control +#define SPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status +#define SPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control +#define SPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud ate prescaler +#define SPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data +#define SPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data + + +// SD Interface +#define SDICON (*(volatile unsigned *)0x5a000000) //SDI control +#define SDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud ate prescaler +#define SDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument +#define SDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control +#define SDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status +#define SDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI esponse 0 +#define SDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI esponse 1 +#define SDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI esponse 2 +#define SDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI esponse 3 +#define SDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer +#define SDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size +#define SDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control +#define SDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data emain counter +#define SDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status +#define SDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status +#define SDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask + +#ifdef __BIG_ENDIAN /* edited for 2440A */ +#define SDIDAT (*(volatile unsigned *)0x5a00004c) +#else // Little Endian +#define SDIDAT (*(volatile unsigned *)0x5a000040) +#endif //SD Interface + +// PENDING BIT +#define INTEINT0 (0) +#define INTEINT1 (1) +#define INTEINT2 (2) +#define INTEINT3 (3) +#define INTEINT4_7 (4) +#define INTEINT8_23 (5) +#define INTNOTUSED6 (6) +#define INTBAT_FLT (7) +#define INTTICK (8) +#define INTWDT (9) +#define INTTIMER0 (10) +#define INTTIMER1 (11) +#define INTTIMER2 (12) +#define INTTIMER3 (13) +#define INTTIMER4 (14) +#define INTUART2 (15) +#define INTLCD (16) +#define INTDMA0 (17) +#define INTDMA1 (18) +#define INTDMA2 (19) +#define INTDMA3 (20) +#define INTSDI (21) +#define INTSPI0 (22) +#define INTUART1 (23) +//#define INTNOTUSED24 (24) +#define INTNIC (24) +#define INTUSBD (25) +#define INTUSBH (26) +#define INTIIC (27) +#define INTUART0 (28) +#define INTSPI1 (29) +#define INTRTC (30) +#define INTADC (31) +#define BIT_ALLMSK (0xffffffff) + +#define BIT_SUB_ALLMSK (0x7ff) +#define INTSUB_ADC (10) +#define INTSUB_TC (9) +#define INTSUB_ERR2 (8) +#define INTSUB_TXD2 (7) +#define INTSUB_RXD2 (6) +#define INTSUB_ERR1 (5) +#define INTSUB_TXD1 (4) +#define INTSUB_RXD1 (3) +#define INTSUB_ERR0 (2) +#define INTSUB_TXD0 (1) +#define INTSUB_RXD0 (0) + +#define BIT_SUB_ADC (0x1<<10) +#define BIT_SUB_TC (0x1<<9) +#define BIT_SUB_ERR2 (0x1<<8) +#define BIT_SUB_TXD2 (0x1<<7) +#define BIT_SUB_RXD2 (0x1<<6) +#define BIT_SUB_ERR1 (0x1<<5) +#define BIT_SUB_TXD1 (0x1<<4) +#define BIT_SUB_RXD1 (0x1<<3) +#define BIT_SUB_ERR0 (0x1<<2) +#define BIT_SUB_TXD0 (0x1<<1) +#define BIT_SUB_RXD0 (0x1<<0) + +#define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;} +//Wait until INTPND is changed for the case that the ISR is very short. + +#define INTGLOBAL 32 + +/*****************************/ +/* CPU Mode */ +/*****************************/ +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +struct rt_hw_register +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; +}; + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif diff --git a/libcpu/arm/s3c24x0/serial.h b/libcpu/arm/s3c24x0/serial.h index 1015f2a9357c1f7be048c8061d10429b4e68580c..e3deb5b8871c18f1dff7d9da07631a98785b589c 100644 --- a/libcpu/arm/s3c24x0/serial.h +++ b/libcpu/arm/s3c24x0/serial.h @@ -1,58 +1,58 @@ -#ifndef __RT_HW_SERIAL_H__ -#define __RT_HW_SERIAL_H__ - -#include -#include - -#include "s3c24x0.h" - -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ - -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 - -struct serial_int_rx -{ - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; - -struct serial_int_tx -{ - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; -}; - -typedef struct uartport -{ - volatile rt_uint32_t ulcon; - volatile rt_uint32_t ucon; - volatile rt_uint32_t ufcon; - volatile rt_uint32_t umcon; - volatile rt_uint32_t ustat; - volatile rt_uint32_t urxb; - volatile rt_uint32_t ufstat; - volatile rt_uint32_t umstat; - volatile rt_uint32_t utxh; - volatile rt_uint32_t urxh; - volatile rt_uint32_t ubrd; -}uartport; - -struct serial_device -{ - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; - - /* tx structure */ - struct serial_int_tx* int_tx; -}; - -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); - -void rt_hw_serial_isr(rt_device_t device); - -#endif +#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include +#include + +#include "s3c24x0.h" + +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +typedef struct uartport +{ + volatile rt_uint32_t ulcon; + volatile rt_uint32_t ucon; + volatile rt_uint32_t ufcon; + volatile rt_uint32_t umcon; + volatile rt_uint32_t ustat; + volatile rt_uint32_t urxb; + volatile rt_uint32_t ufstat; + volatile rt_uint32_t umstat; + volatile rt_uint32_t utxh; + volatile rt_uint32_t urxh; + volatile rt_uint32_t ubrd; +}uartport; + +struct serial_device +{ + uartport* uart_device; + + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); + +void rt_hw_serial_isr(rt_device_t device); + +#endif diff --git a/libcpu/arm/s3c24x0/start_rvds.S b/libcpu/arm/s3c24x0/start_rvds.S index 38872cd93b0ef7d7247eb23956a8c727e76d04ab..dd5e9cc3098f2ce4d210823808fa3245438120b6 100644 --- a/libcpu/arm/s3c24x0/start_rvds.S +++ b/libcpu/arm/s3c24x0/start_rvds.S @@ -1,1190 +1,1190 @@ -;/*****************************************************************************/ -;/* S3C2440.S: Startup file for Samsung S3C440 */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -;/* -; * The S3C2440.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock -; * (used mostly when clock is already initialized from script .ini -; * file). -; * -; * NO_MC_SETUP: when set the startup code will not initialize Memory -; * Controller (used mostly when clock is already initialized from script -; * .ini file). -; * -; * NO_GP_SETUP: when set the startup code will not initialize General Ports -; * (used mostly when clock is already initialized from script .ini -; * file). -; * -; * RAM_INTVEC: when set the startup code copies exception vectors -; * from execution address to on-chip RAM. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -;----------------------- Stack and Heap Definitions ---------------------------- - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000100 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000100 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -;----------------------- Memory Definitions ------------------------------------ - -; Internal Memory Base Addresses -IRAM_BASE EQU 0x40000000 - - -;----------------------- Watchdog Timer Definitions ---------------------------- - -WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address -WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset -WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset -WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset - -;// Watchdog Timer Setup -;// Watchdog Timer Control Register (WTCON) -;// Prescaler Value <0-255> -;// Watchdog Timer Enable -;// Clock Division Factor -;// <0=> 16 <1=> 32 <2=> 64 <3=> 128 -;// Interrupt Generation Enable -;// Reset Enable -;// -;// Watchdog Timer Data Register (WTDAT) -;// Count Reload Value <0-65535> -;// -;// Watchdog Timer Setup -WT_SETUP EQU 1 -WTCON_Val EQU 0x00000000 -WTDAT_Val EQU 0x00008000 - - -;----------------------- Clock and Power Management Definitions ---------------- - -CLOCK_BASE EQU 0x4C000000 ; Clock Base Address -LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset -MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset -UPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset -CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset -CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset -CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset -CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset - -;// Clock Setup -;// PLL Lock Time Count Register (LOCKTIME) -;// U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF> -;// M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF> -;// -;// MPLL Configuration Register (MPLLCON) -;// MPLL = (2 * m * Fin) / (p * 2^s) -;// m: Main Divider m Value <9-256><#-8> -;// m = MDIV + 8 -;// p: Pre-divider p Value <3-64><#-2> -;// p = PDIV + 2 -;// s: Post Divider s Value <0-3> -;// s = SDIV -;// -;// UPLL Configuration Register (UPLLCON) -;// UPLL = ( m * Fin) / (p * 2^s) -;// m: Main Divider m Value <8-263><#-8> -;// m = MDIV + 8 -;// p: Pre-divider p Value <2-65><#-2> -;// p = PDIV + 2 -;// s: Post Divider s Value <0-3> -;// s = SDIV -;// -;// Clock Generation Control Register (CLKCON) -;// AC97 Enable -;// Camera Enable -;// SPI Enable -;// IIS Enable -;// IIC Enable -;// ADC + Touch Screen Enable -;// RTC Enable -;// GPIO Enable -;// UART2 Enable -;// UART1 Enable -;// UART0 Enable -;// SDI Enable -;// PWMTIMER Enable -;// USB Device Enable -;// USB Host Enable -;// LCDC Enable -;// NAND FLASH Controller Enable -;// SLEEP Enable -;// IDLE BIT Enable -;// -;// Clock Slow Control Register (CLKSLOW) -;// UCLK_ON: UCLK ON -;// MPLL_OFF: Turn off PLL -;// SLOW_BIT: Slow Mode Enable -;// SLOW_VAL: Slow Clock Divider <0-7> -;// -;// Clock Divider Control Register (CLKDIVN) -;// DIVN_UPLL: UCLK Select -;// <0=> UCLK = UPLL clock -;// <1=> UCLK = UPLL clock / 2 -;// HDIVN: HCLK Select -;// <0=> HCLK = FCLK -;// <1=> HCLK = FCLK / 2 -;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8 -;// <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6 -;// PDIVN: PCLK Select -;// <0=> PCLK = HCLK -;// <1=> PCLK = HCLK / 2 -;// -;// Camera Clock Divider Control Register (CAMDIVN) -;// DVS_EN: ARM Core Clock Select -;// <0=> ARM core runs at FCLK -;// <1=> ARM core runs at HCLK -;// HCLK4_HALF: HDIVN Division Rate Change Bit -;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4 -;// <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8 -;// HCLK3_HALF: HDIVN Division Rate Change Bit -;// <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3 -;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6 -;// CAMCLK Select -;// <0=> CAMCLK = UPLL -;// <1=> CAMCLK = UPLL / CAMCLK_DIV -;// CAMCLK_DIV: CAMCLK Divider <0-15> -;// Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1)) -;// Divider is used only if CAMCLK_SEL = 1 -;// -;// Clock Setup -CLOCK_SETUP EQU 0 -LOCKTIME_Val EQU 0x0FFF0FFF -MPLLCON_Val EQU 0x00043011 -UPLLCON_Val EQU 0x00038021 -CLKCON_Val EQU 0x001FFFF0 -CLKSLOW_Val EQU 0x00000004 -CLKDIVN_Val EQU 0x0000000F -CAMDIVN_Val EQU 0x00000000 - - -;----------------------- Memory Controller Definitions ------------------------- - -MC_BASE EQU 0x48000000 ; Memory Controller Base Address -BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset -BANKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset -BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset -BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset -BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset -BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset -BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset -BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset -BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset -REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset -BANKSIZE_OFS EQU 0x28 ; Flexible Bank Size Register Offset -MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset -MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset - -;// Memory Controller Setup -;// Bus Width and Wait Control Register (BWSCON) -;// ST7: Use UB/LB for Bank 7 -;// WS7: Enable Wait Status for Bank 7 -;// DW7: Data Bus Width for Bank 7 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST6: Use UB/LB for Bank 6 -;// WS6: Enable Wait Status for Bank 6 -;// DW6: Data Bus Width for Bank 6 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST5: Use UB/LB for Bank 5 -;// WS5: Enable Wait Status for Bank 5 -;// DW5: Data Bus Width for Bank 5 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST4: Use UB/LB for Bank 4 -;// WS4: Enable Wait Status for Bank 4 -;// DW4: Data Bus Width for Bank 4 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST3: Use UB/LB for Bank 3 -;// WS3: Enable Wait Status for Bank 3 -;// DW3: Data Bus Width for Bank 3 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST2: Use UB/LB for Bank 2 -;// WS2: Enable Wait Status for Bank 2 -;// DW2: Data Bus Width for Bank 2 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST1: Use UB/LB for Bank 1 -;// WS1: Enable Wait Status for Bank 1 -;// DW1: Data Bus Width for Bank 1 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// DW0: Indicate Data Bus Width for Bank 0 -;// <1=> 16-bit <2=> 32-bit -;// -;// Bank 0 Control Register (BANKCON0) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 1 Control Register (BANKCON1) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 2 Control Register (BANKCON2) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 3 Control Register (BANKCON3) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 4 Control Register (BANKCON4) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 5 Control Register (BANKCON5) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 6 Control Register (BANKCON6) -;// Memory Type Selection -;// <0=> ROM or SRAM <3=> SDRAM -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay -;// Parameter depends on Memory Type: if type SRAM then parameter is Tacp, -;// if type is SDRAM then parameter is Trcd -;// For SDRAM 6 cycles setting is not allowed -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC/SCAN: Page Mode Configuration / Column Address Number <0-3> -;// Parameter depends on Memory Type: if type SRAM then parameter is PMC, -;// if type is SDRAM then parameter is SCAN -;// -;// Bank 7 Control Register (BANKCON7) -;// Memory Type Selection -;// <0=> ROM or SRAM <3=> SDRAM -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay -;// Parameter depends on Memory Type: if type SRAM then parameter is Tacp, -;// if type is SDRAM then parameter is Trcd -;// For SDRAM 6 cycles setting is not allowed -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC/SCAN: Page Mode Configuration / Column Address Number <0-3> -;// Parameter depends on Memory Type: if type SRAM then parameter is PMC, -;// if type is SDRAM then parameter is SCAN -;// -;// SDRAM Refresh Control Register (REFRESH) -;// REFEN: SDRAM Refresh Enable -;// TREFMD: SDRAM Refresh Mode -;// <0=> CBR/Auto Refresh <1=> Self Refresh -;// Trp: SDRAM RAS Pre-charge Time -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved -;// Tsrc: SDRAM Semi Row Cycle Time -;// SDRAM Row cycle time: Trc = Tsrc + Trp -;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks -;// Refresh Counter <0-1023> -;// Refresh Period = (2048 - Refresh Count + 1) / HCLK -;// -;// Flexible Bank Size Register (BANKSIZE) -;// BURST_EN: ARM Core Burst Operation Enable -;// SCKE_EN: SDRAM Power Down Mode Enable -;// SCLK_EN: SCLK Enabled During SDRAM Access Cycle -;// <0=> SCLK is always active <1=> SCLK is active only during the access -;// BK76MAP: BANK6 and BANK7 Memory Map -;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB -;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB -;// Refresh Counter <0-1023> -;// Refresh Period = (2048 - Refresh Count + 1) / HCLK -;// -;// SDRAM Mode Register Set Register 6 (MRSRB6) -;// WBL: Write Burst Length -;// <0=> Burst (Fixed) -;// TM: Test Mode -;// <0=> Mode register set (Fixed) -;// CL: CAS Latency -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks -;// BT: Burst Type -;// <0=> Sequential (Fixed) -;// BL: Burst Length -;// <0=> 1 (Fixed) -;// -;// SDRAM Mode Register Set Register 7 (MRSRB7) -;// WBL: Write Burst Length -;// <0=> Burst (Fixed) -;// TM: Test Mode -;// <0=> Mode register set (Fixed) -;// CL: CAS Latency -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks -;// BT: Burst Type -;// <0=> Sequential (Fixed) -;// BL: Burst Length -;// <0=> 1 (Fixed) -;// -;// Memory Controller Setup -MC_SETUP EQU 0 -BWSCON_Val EQU 0x22000000 -BANKCON0_Val EQU 0x00000700 -BANKCON1_Val EQU 0x00000700 -BANKCON2_Val EQU 0x00000700 -BANKCON3_Val EQU 0x00000700 -BANKCON4_Val EQU 0x00000700 -BANKCON5_Val EQU 0x00000700 -BANKCON6_Val EQU 0x00018005 -BANKCON7_Val EQU 0x00018005 -REFRESH_Val EQU 0x008404F3 -BANKSIZE_Val EQU 0x00000032 -MRSRB6_Val EQU 0x00000020 -MRSRB7_Val EQU 0x00000020 - - -;----------------------- I/O Port Definitions ---------------------------------- - -GPA_BASE EQU 0x56000000 ; GPA Base Address -GPB_BASE EQU 0x56000010 ; GPB Base Address -GPC_BASE EQU 0x56000020 ; GPC Base Address -GPD_BASE EQU 0x56000030 ; GPD Base Address -GPE_BASE EQU 0x56000040 ; GPE Base Address -GPF_BASE EQU 0x56000050 ; GPF Base Address -GPG_BASE EQU 0x56000060 ; GPG Base Address -GPH_BASE EQU 0x56000070 ; GPH Base Address -GPJ_BASE EQU 0x560000D0 ; GPJ Base Address -GPCON_OFS EQU 0x00 ; Control Register Offset -GPDAT_OFS EQU 0x04 ; Data Register Offset -GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset - -;// I/O Setup -GP_SETUP EQU 1 - -;// Port A Settings -;// Port A Control Register (GPACON) -;// GPA22 <0=> Output <1=> nFCE -;// GPA21 <0=> Output <1=> nRSTOUT -;// GPA20 <0=> Output <1=> nFRE -;// GPA19 <0=> Output <1=> nFWE -;// GPA18 <0=> Output <1=> ALE -;// GPA17 <0=> Output <1=> CLE -;// GPA16 <0=> Output <1=> nGCS[5] -;// GPA15 <0=> Output <1=> nGCS[4] -;// GPA14 <0=> Output <1=> nGCS[3] -;// GPA13 <0=> Output <1=> nGCS[2] -;// GPA12 <0=> Output <1=> nGCS[1] -;// GPA11 <0=> Output <1=> ADDR26 -;// GPA10 <0=> Output <1=> ADDR25 -;// GPA9 <0=> Output <1=> ADDR24 -;// GPA8 <0=> Output <1=> ADDR23 -;// GPA7 <0=> Output <1=> ADDR22 -;// GPA6 <0=> Output <1=> ADDR21 -;// GPA5 <0=> Output <1=> ADDR20 -;// GPA4 <0=> Output <1=> ADDR19 -;// GPA3 <0=> Output <1=> ADDR18 -;// GPA2 <0=> Output <1=> ADDR17 -;// GPA1 <0=> Output <1=> ADDR16 -;// GPA0 <0=> Output <1=> ADDR0 -;// -;// -GPA_SETUP EQU 0 -GPACON_Val EQU 0x000003FF - -;// Port B Settings -;// Port B Control Register (GPBCON) -;// GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved -;// GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved -;// GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved -;// GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved -;// GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved -;// GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved -;// GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved -;// GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved -;// GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved -;// GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved -;// GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved -;// -;// Port B Pull-up Settings Register (GPBUP) -;// GPB10 Pull-up Disable -;// GPB9 Pull-up Disable -;// GPB8 Pull-up Disable -;// GPB7 Pull-up Disable -;// GPB6 Pull-up Disable -;// GPB5 Pull-up Disable -;// GPB4 Pull-up Disable -;// GPB3 Pull-up Disable -;// GPB2 Pull-up Disable -;// GPB1 Pull-up Disable -;// GPB0 Pull-up Disable -;// -;// -GPB_SETUP EQU 0 -GPBCON_Val EQU 0x00000000 -GPBUP_Val EQU 0x00000000 - -;// Port C Settings -;// Port C Control Register (GPCCON) -;// GPC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved -;// GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved -;// GPC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved -;// GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved -;// GPC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved -;// GPC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved -;// GPC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved -;// GPC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved -;// GPC7 <0=> Input <1=> Output <2=> LCD_LPCREVB <3=> Reserved -;// GPC6 <0=> Input <1=> Output <2=> LCD_LPCREV <3=> Reserved -;// GPC5 <0=> Input <1=> Output <2=> LCD_LPCOE <3=> Reserved -;// GPC4 <0=> Input <1=> Output <2=> VM <3=> I2SSDI -;// GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved -;// GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved -;// GPC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved -;// GPC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved -;// -;// Port C Pull-up Settings Register (GPCUP) -;// GPC15 Pull-up Disable -;// GPC14 Pull-up Disable -;// GPC13 Pull-up Disable -;// GPC12 Pull-up Disable -;// GPC11 Pull-up Disable -;// GPC10 Pull-up Disable -;// GPC9 Pull-up Disable -;// GPC8 Pull-up Disable -;// GPC7 Pull-up Disable -;// GPC6 Pull-up Disable -;// GPC5 Pull-up Disable -;// GPC4 Pull-up Disable -;// GPC3 Pull-up Disable -;// GPC2 Pull-up Disable -;// GPC1 Pull-up Disable -;// GPC0 Pull-up Disable -;// -;// -GPC_SETUP EQU 0 -GPCCON_Val EQU 0x00000000 -GPCUP_Val EQU 0x00000000 - -;// Port D Settings -;// Port D Control Register (GPDCON) -;// GPD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0 -;// GPD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1 -;// GPD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved -;// GPD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved -;// GPD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved -;// GPD10 <0=> Input <1=> Output <2=> VD[18] <3=> SPICLK1 -;// GPD9 <0=> Input <1=> Output <2=> VD[17] <3=> SPIMOSI1 -;// GPD8 <0=> Input <1=> Output <2=> VD[16] <3=> SPIMISO1 -;// GPD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved -;// GPD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved -;// GPD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved -;// GPD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved -;// GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved -;// GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved -;// GPD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved -;// GPD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved -;// -;// Port D Pull-up Settings Register (GPDUP) -;// GPD15 Pull-up Disable -;// GPD14 Pull-up Disable -;// GPD13 Pull-up Disable -;// GPD12 Pull-up Disable -;// GPD11 Pull-up Disable -;// GPD10 Pull-up Disable -;// GPD9 Pull-up Disable -;// GPD8 Pull-up Disable -;// GPD7 Pull-up Disable -;// GPD6 Pull-up Disable -;// GPD5 Pull-up Disable -;// GPD4 Pull-up Disable -;// GPD3 Pull-up Disable -;// GPD2 Pull-up Disable -;// GPD1 Pull-up Disable -;// GPD0 Pull-up Disable -;// -;// -GPD_SETUP EQU 0 -GPDCON_Val EQU 0x00000000 -GPDUP_Val EQU 0x00000000 - -;// Port E Settings -;// Port E Control Register (GPECON) -;// GPE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved -;// This pad is open-drain, and has no pull-up option. -;// GPE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved -;// This pad is open-drain, and has no pull-up option. -;// GPE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved -;// GPE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved -;// GPE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved -;// GPE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved -;// GPE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved -;// GPE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved -;// GPE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved -;// GPE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved -;// GPE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved -;// GPE4 <0=> Input <1=> Output <2=> I2SDO <3=> AC_SDATA_OUT -;// GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN -;// GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET -;// GPE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> AC_BIT_CLK -;// GPE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> AC_SYNC -;// -;// Port E Pull-up Settings Register (GPEUP) -;// GPE13 Pull-up Disable -;// GPE12 Pull-up Disable -;// GPE11 Pull-up Disable -;// GPE10 Pull-up Disable -;// GPE9 Pull-up Disable -;// GPE8 Pull-up Disable -;// GPE7 Pull-up Disable -;// GPE6 Pull-up Disable -;// GPE5 Pull-up Disable -;// GPE4 Pull-up Disable -;// GPE3 Pull-up Disable -;// GPE2 Pull-up Disable -;// GPE1 Pull-up Disable -;// GPE0 Pull-up Disable -;// -;// -GPE_SETUP EQU 0 -GPECON_Val EQU 0x00000000 -GPEUP_Val EQU 0x00000000 - -;// Port F Settings -;// Port F Control Register (GPFCON) -;// GPF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved -;// GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved -;// GPF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved -;// GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved -;// GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved -;// GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved -;// GPF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved -;// GPF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved -;// -;// Port F Pull-up Settings Register (GPFUP) -;// GPF7 Pull-up Disable -;// GPF6 Pull-up Disable -;// GPF5 Pull-up Disable -;// GPF4 Pull-up Disable -;// GPF3 Pull-up Disable -;// GPF2 Pull-up Disable -;// GPF1 Pull-up Disable -;// GPF0 Pull-up Disable -;// -;// -GPF_SETUP EQU 1 -GPFCON_Val EQU 0x000000AA -GPFUP_Val EQU 0x0000000F - -;// Port G Settings -;// Port G Control Register (GPGCON) -;// GPG15 <0=> Input <1=> Output <2=> EINT[23] <3=> Reserved -;// GPG14 <0=> Input <1=> Output <2=> EINT[22] <3=> Reserved -;// GPG13 <0=> Input <1=> Output <2=> EINT[21] <3=> Reserved -;// GPG12 <0=> Input <1=> Output <2=> EINT[20] <3=> Reserved -;// GPG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK[1] -;// GPG10 <0=> Input <1=> Output <2=> EINT[18] <3=> nCTS1 -;// GPG9 <0=> Input <1=> Output <2=> EINT[17] <3=> nRTS1 -;// GPG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved -;// GPG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1 -;// GPG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1 -;// GPG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1 -;// GPG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN -;// GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1 -;// GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0 -;// GPG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved -;// GPG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved -;// -;// Port G Pull-up Settings Register (GPGUP) -;// GPG15 Pull-up Disable -;// GPG14 Pull-up Disable -;// GPG13 Pull-up Disable -;// GPG12 Pull-up Disable -;// GPG11 Pull-up Disable -;// GPG10 Pull-up Disable -;// GPG9 Pull-up Disable -;// GPG8 Pull-up Disable -;// GPG7 Pull-up Disable -;// GPG6 Pull-up Disable -;// GPG5 Pull-up Disable -;// GPG4 Pull-up Disable -;// GPG3 Pull-up Disable -;// GPG2 Pull-up Disable -;// GPG1 Pull-up Disable -;// GPG0 Pull-up Disable -;// -;// -GPG_SETUP EQU 0 -GPGCON_Val EQU 0x00000000 -GPGUP_Val EQU 0x00000000 - -;// Port H Settings -;// Port H Control Register (GPHCON) -;// GPH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved -;// GPH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved -;// GPH8 <0=> Input <1=> Output <2=> UEXTCLK <3=> Reserved -;// GPH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1 -;// GPH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1 -;// GPH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved -;// GPH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved -;// GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved -;// GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved -;// GPH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved -;// GPH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved -;// -;// Port H Pull-up Settings Register (GPHUP) -;// GPH10 Pull-up Disable -;// GPH9 Pull-up Disable -;// GPH8 Pull-up Disable -;// GPH7 Pull-up Disable -;// GPH6 Pull-up Disable -;// GPH5 Pull-up Disable -;// GPH4 Pull-up Disable -;// GPH3 Pull-up Disable -;// GPH2 Pull-up Disable -;// GPH1 Pull-up Disable -;// GPH0 Pull-up Disable -;// -;// -GPH_SETUP EQU 0 -GPHCON_Val EQU 0x00000000 -GPHUP_Val EQU 0x00000000 - -;// Port J Settings -;// Port J Control Register (GPJCON) -;// GPJ12 <0=> Input <1=> Output <2=> CAMRESET <3=> Reserved -;// GPJ11 <0=> Input <1=> Output <2=> CAMCLKOUT <3=> Reserved -;// GPJ10 <0=> Input <1=> Output <2=> CAMHREF <3=> Reserved -;// GPJ9 <0=> Input <1=> Output <2=> CAMVSYNC <3=> Reserved -;// GPJ8 <0=> Input <1=> Output <2=> CAMPCLK <3=> Reserved -;// GPJ7 <0=> Input <1=> Output <2=> CAMDATA[7] <3=> Reserved -;// GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved -;// GPJ5 <0=> Input <1=> Output <2=> CAMDATA[5] <3=> Reserved -;// GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved -;// GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved -;// GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved -;// GPJ1 <0=> Input <1=> Output <2=> CAMDATA[1] <3=> Reserved -;// GPJ0 <0=> Input <1=> Output <2=> CAMDATA[0] <3=> Reserved -;// -;// Port J Pull-up Settings Register (GPJUP) -;// GPJ12 Pull-up Disable -;// GPJ11 Pull-up Disable -;// GPJ10 Pull-up Disable -;// GPJ9 Pull-up Disable -;// GPJ8 Pull-up Disable -;// GPJ7 Pull-up Disable -;// GPJ6 Pull-up Disable -;// GPJ5 Pull-up Disable -;// GPJ4 Pull-up Disable -;// GPJ3 Pull-up Disable -;// GPJ2 Pull-up Disable -;// GPJ1 Pull-up Disable -;// GPJ0 Pull-up Disable -;// -;// -GPJ_SETUP EQU 0 -GPJCON_Val EQU 0x00000000 -GPJUP_Val EQU 0x00000000 - -;// I/O Setup - - -;----------------------- CODE -------------------------------------------------- - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - - EXPORT Entry_Point -Entry_Point -Vectors LDR PC, Reset_Addr - LDR PC, Undef_Addr - LDR PC, SWI_Addr - LDR PC, PAbt_Addr - LDR PC, DAbt_Addr - NOP - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B PAbt_Handler -;DAbt_Handler B DAbt_Handler -FIQ_Handler B FIQ_Handler - -;* -;************************************************************************* -;* -;* Interrupt handling -;* -;************************************************************************* -;* -; DAbt Handler -DAbt_Handler - IMPORT rt_hw_trap_dabt - - sub sp, sp, #72 - stmia sp, {r0 - r12} ;/* Calling r0-r12 */ - add r8, sp, #60 - stmdb r8, {sp, lr} ;/* Calling SP, LR */ - str lr, [r8, #0] ;/* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] ;/* Save CPSR */ - str r0, [r8, #8] ;/* Save OLD_R0 */ - mov r0, sp - - bl rt_hw_trap_dabt - - -;########################################## -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Watchdog Setup --------------------------------------------------------------- - - IF WT_SETUP != 0 - LDR R0, =WT_BASE - LDR R1, =WTCON_Val - LDR R2, =WTDAT_Val - STR R2, [R0, #WTCNT_OFS] - STR R2, [R0, #WTDAT_OFS] - STR R1, [R0, #WTCON_OFS] - ENDIF - - -; Clock Setup ------------------------------------------------------------------ - - IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) - LDR R0, =CLOCK_BASE - LDR R1, =LOCKTIME_Val - STR R1, [R0, #LOCKTIME_OFS] - MOV R1, #CLKDIVN_Val - STR R1, [R0, #CLKDIVN_OFS] - LDR R1, =CAMDIVN_Val - STR R1, [R0, #CAMDIVN_OFS] - LDR R1, =MPLLCON_Val - STR R1, [R0, #MPLLCON_OFS] - LDR R1, =UPLLCON_Val - STR R1, [R0, #UPLLCON_OFS] - MOV R1, #CLKSLOW_Val - STR R1, [R0, #CLKSLOW_OFS] - LDR R1, =CLKCON_Val - STR R1, [R0, #CLKCON_OFS] - ENDIF - - -; Memory Controller Setup ------------------------------------------------------ - - IF (:LNOT:(:DEF:NO_MC_SETUP)):LAND:(CLOCK_SETUP != 0) - LDR R0, =MC_BASE - LDR R1, =BWSCON_Val - STR R1, [R0, #BWSCON_OFS] - LDR R1, =BANKCON0_Val - STR R1, [R0, #BANKCON0_OFS] - LDR R1, =BANKCON1_Val - STR R1, [R0, #BANKCON1_OFS] - LDR R1, =BANKCON2_Val - STR R1, [R0, #BANKCON2_OFS] - LDR R1, =BANKCON3_Val - STR R1, [R0, #BANKCON3_OFS] - LDR R1, =BANKCON4_Val - STR R1, [R0, #BANKCON4_OFS] - LDR R1, =BANKCON5_Val - STR R1, [R0, #BANKCON5_OFS] - LDR R1, =BANKCON6_Val - STR R1, [R0, #BANKCON6_OFS] - LDR R1, =BANKCON7_Val - STR R1, [R0, #BANKCON7_OFS] - LDR R1, =REFRESH_Val - STR R1, [R0, #REFRESH_OFS] - MOV R1, #BANKSIZE_Val - STR R1, [R0, #BANKSIZE_OFS] - MOV R1, #MRSRB6_Val - STR R1, [R0, #MRSRB6_OFS] - MOV R1, #MRSRB7_Val - STR R1, [R0, #MRSRB7_OFS] - ENDIF - - -; I/O Pins Setup --------------------------------------------------------------- - - IF (:LNOT:(:DEF:NO_GP_SETUP)):LAND:(GP_SETUP != 0) - - IF GPA_SETUP != 0 - LDR R0, =GPA_BASE - LDR R1, =GPACON_Val - STR R1, [R0, #GPCON_OFS] - ENDIF - - IF GPB_SETUP != 0 - LDR R0, =GPB_BASE - LDR R1, =GPBCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPBUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPC_SETUP != 0 - LDR R0, =GPC_BASE - LDR R1, =GPCCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPCUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPD_SETUP != 0 - LDR R0, =GPD_BASE - LDR R1, =GPDCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPDUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPE_SETUP != 0 - LDR R0, =GPE_BASE - LDR R1, =GPECON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPEUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPF_SETUP != 0 - LDR R0, =GPF_BASE - LDR R1, =GPFCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPFUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPG_SETUP != 0 - LDR R0, =GPG_BASE - LDR R1, =GPGCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPGUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPH_SETUP != 0 - LDR R0, =GPH_BASE - LDR R1, =GPHCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPHUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPJ_SETUP != 0 - LDR R0, =GPJ_BASE - LDR R1, =GPJCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPJUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - ENDIF - - -; Copy Exception Vectors to Internal RAM --------------------------------------- - - IF :DEF:RAM_INTVEC - ADR R8, Vectors ; Source - LDR R9, =IRAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - ENDIF - - -; Setup Stack for each mode ---------------------------------------------------- - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; MSR CPSR_c, #Mode_USR - MOV SP, R0 - SUB SL, SP, #USR_Stack_Size - -; Enter the C code ------------------------------------------------------------- - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - - END - +;/*****************************************************************************/ +;/* S3C2440.S: Startup file for Samsung S3C440 */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The S3C2440.S code is executed after CPU Reset. This file may be +; * translated with the following SET symbols. In uVision these SET +; * symbols are entered under Options - ASM - Define. +; * +; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock +; * (used mostly when clock is already initialized from script .ini +; * file). +; * +; * NO_MC_SETUP: when set the startup code will not initialize Memory +; * Controller (used mostly when clock is already initialized from script +; * .ini file). +; * +; * NO_GP_SETUP: when set the startup code will not initialize General Ports +; * (used mostly when clock is already initialized from script .ini +; * file). +; * +; * RAM_INTVEC: when set the startup code copies exception vectors +; * from execution address to on-chip RAM. +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +;----------------------- Stack and Heap Definitions ---------------------------- + +;// Stack Configuration (Stack Sizes in Bytes) +;// Undefined Mode <0x0-0xFFFFFFFF:8> +;// Supervisor Mode <0x0-0xFFFFFFFF:8> +;// Abort Mode <0x0-0xFFFFFFFF:8> +;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// Interrupt Mode <0x0-0xFFFFFFFF:8> +;// User/System Mode <0x0-0xFFFFFFFF:8> +;// + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size +Stack_Top + + +;// Heap Configuration +;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +;----------------------- Memory Definitions ------------------------------------ + +; Internal Memory Base Addresses +IRAM_BASE EQU 0x40000000 + + +;----------------------- Watchdog Timer Definitions ---------------------------- + +WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address +WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset +WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset +WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset + +;// Watchdog Timer Setup +;// Watchdog Timer Control Register (WTCON) +;// Prescaler Value <0-255> +;// Watchdog Timer Enable +;// Clock Division Factor +;// <0=> 16 <1=> 32 <2=> 64 <3=> 128 +;// Interrupt Generation Enable +;// Reset Enable +;// +;// Watchdog Timer Data Register (WTDAT) +;// Count Reload Value <0-65535> +;// +;// Watchdog Timer Setup +WT_SETUP EQU 1 +WTCON_Val EQU 0x00000000 +WTDAT_Val EQU 0x00008000 + + +;----------------------- Clock and Power Management Definitions ---------------- + +CLOCK_BASE EQU 0x4C000000 ; Clock Base Address +LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset +MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset +UPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset +CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset +CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset +CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset +CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset + +;// Clock Setup +;// PLL Lock Time Count Register (LOCKTIME) +;// U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF> +;// M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF> +;// +;// MPLL Configuration Register (MPLLCON) +;// MPLL = (2 * m * Fin) / (p * 2^s) +;// m: Main Divider m Value <9-256><#-8> +;// m = MDIV + 8 +;// p: Pre-divider p Value <3-64><#-2> +;// p = PDIV + 2 +;// s: Post Divider s Value <0-3> +;// s = SDIV +;// +;// UPLL Configuration Register (UPLLCON) +;// UPLL = ( m * Fin) / (p * 2^s) +;// m: Main Divider m Value <8-263><#-8> +;// m = MDIV + 8 +;// p: Pre-divider p Value <2-65><#-2> +;// p = PDIV + 2 +;// s: Post Divider s Value <0-3> +;// s = SDIV +;// +;// Clock Generation Control Register (CLKCON) +;// AC97 Enable +;// Camera Enable +;// SPI Enable +;// IIS Enable +;// IIC Enable +;// ADC + Touch Screen Enable +;// RTC Enable +;// GPIO Enable +;// UART2 Enable +;// UART1 Enable +;// UART0 Enable +;// SDI Enable +;// PWMTIMER Enable +;// USB Device Enable +;// USB Host Enable +;// LCDC Enable +;// NAND FLASH Controller Enable +;// SLEEP Enable +;// IDLE BIT Enable +;// +;// Clock Slow Control Register (CLKSLOW) +;// UCLK_ON: UCLK ON +;// MPLL_OFF: Turn off PLL +;// SLOW_BIT: Slow Mode Enable +;// SLOW_VAL: Slow Clock Divider <0-7> +;// +;// Clock Divider Control Register (CLKDIVN) +;// DIVN_UPLL: UCLK Select +;// <0=> UCLK = UPLL clock +;// <1=> UCLK = UPLL clock / 2 +;// HDIVN: HCLK Select +;// <0=> HCLK = FCLK +;// <1=> HCLK = FCLK / 2 +;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8 +;// <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6 +;// PDIVN: PCLK Select +;// <0=> PCLK = HCLK +;// <1=> PCLK = HCLK / 2 +;// +;// Camera Clock Divider Control Register (CAMDIVN) +;// DVS_EN: ARM Core Clock Select +;// <0=> ARM core runs at FCLK +;// <1=> ARM core runs at HCLK +;// HCLK4_HALF: HDIVN Division Rate Change Bit +;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4 +;// <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8 +;// HCLK3_HALF: HDIVN Division Rate Change Bit +;// <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3 +;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6 +;// CAMCLK Select +;// <0=> CAMCLK = UPLL +;// <1=> CAMCLK = UPLL / CAMCLK_DIV +;// CAMCLK_DIV: CAMCLK Divider <0-15> +;// Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1)) +;// Divider is used only if CAMCLK_SEL = 1 +;// +;// Clock Setup +CLOCK_SETUP EQU 0 +LOCKTIME_Val EQU 0x0FFF0FFF +MPLLCON_Val EQU 0x00043011 +UPLLCON_Val EQU 0x00038021 +CLKCON_Val EQU 0x001FFFF0 +CLKSLOW_Val EQU 0x00000004 +CLKDIVN_Val EQU 0x0000000F +CAMDIVN_Val EQU 0x00000000 + + +;----------------------- Memory Controller Definitions ------------------------- + +MC_BASE EQU 0x48000000 ; Memory Controller Base Address +BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset +BANKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset +BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset +BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset +BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset +BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset +BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset +BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset +BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset +REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset +BANKSIZE_OFS EQU 0x28 ; Flexible Bank Size Register Offset +MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset +MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset + +;// Memory Controller Setup +;// Bus Width and Wait Control Register (BWSCON) +;// ST7: Use UB/LB for Bank 7 +;// WS7: Enable Wait Status for Bank 7 +;// DW7: Data Bus Width for Bank 7 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// ST6: Use UB/LB for Bank 6 +;// WS6: Enable Wait Status for Bank 6 +;// DW6: Data Bus Width for Bank 6 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// ST5: Use UB/LB for Bank 5 +;// WS5: Enable Wait Status for Bank 5 +;// DW5: Data Bus Width for Bank 5 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// ST4: Use UB/LB for Bank 4 +;// WS4: Enable Wait Status for Bank 4 +;// DW4: Data Bus Width for Bank 4 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// ST3: Use UB/LB for Bank 3 +;// WS3: Enable Wait Status for Bank 3 +;// DW3: Data Bus Width for Bank 3 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// ST2: Use UB/LB for Bank 2 +;// WS2: Enable Wait Status for Bank 2 +;// DW2: Data Bus Width for Bank 2 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// ST1: Use UB/LB for Bank 1 +;// WS1: Enable Wait Status for Bank 1 +;// DW1: Data Bus Width for Bank 1 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// DW0: Indicate Data Bus Width for Bank 0 +;// <1=> 16-bit <2=> 32-bit +;// +;// Bank 0 Control Register (BANKCON0) +;// Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// +;// Bank 1 Control Register (BANKCON1) +;// Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// +;// Bank 2 Control Register (BANKCON2) +;// Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// +;// Bank 3 Control Register (BANKCON3) +;// Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// +;// Bank 4 Control Register (BANKCON4) +;// Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// +;// Bank 5 Control Register (BANKCON5) +;// Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// +;// Bank 6 Control Register (BANKCON6) +;// Memory Type Selection +;// <0=> ROM or SRAM <3=> SDRAM +;// Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay +;// Parameter depends on Memory Type: if type SRAM then parameter is Tacp, +;// if type is SDRAM then parameter is Trcd +;// For SDRAM 6 cycles setting is not allowed +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// PMC/SCAN: Page Mode Configuration / Column Address Number <0-3> +;// Parameter depends on Memory Type: if type SRAM then parameter is PMC, +;// if type is SDRAM then parameter is SCAN +;// +;// Bank 7 Control Register (BANKCON7) +;// Memory Type Selection +;// <0=> ROM or SRAM <3=> SDRAM +;// Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay +;// Parameter depends on Memory Type: if type SRAM then parameter is Tacp, +;// if type is SDRAM then parameter is Trcd +;// For SDRAM 6 cycles setting is not allowed +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// PMC/SCAN: Page Mode Configuration / Column Address Number <0-3> +;// Parameter depends on Memory Type: if type SRAM then parameter is PMC, +;// if type is SDRAM then parameter is SCAN +;// +;// SDRAM Refresh Control Register (REFRESH) +;// REFEN: SDRAM Refresh Enable +;// TREFMD: SDRAM Refresh Mode +;// <0=> CBR/Auto Refresh <1=> Self Refresh +;// Trp: SDRAM RAS Pre-charge Time +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved +;// Tsrc: SDRAM Semi Row Cycle Time +;// SDRAM Row cycle time: Trc = Tsrc + Trp +;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks +;// Refresh Counter <0-1023> +;// Refresh Period = (2048 - Refresh Count + 1) / HCLK +;// +;// Flexible Bank Size Register (BANKSIZE) +;// BURST_EN: ARM Core Burst Operation Enable +;// SCKE_EN: SDRAM Power Down Mode Enable +;// SCLK_EN: SCLK Enabled During SDRAM Access Cycle +;// <0=> SCLK is always active <1=> SCLK is active only during the access +;// BK76MAP: BANK6 and BANK7 Memory Map +;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB +;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB +;// Refresh Counter <0-1023> +;// Refresh Period = (2048 - Refresh Count + 1) / HCLK +;// +;// SDRAM Mode Register Set Register 6 (MRSRB6) +;// WBL: Write Burst Length +;// <0=> Burst (Fixed) +;// TM: Test Mode +;// <0=> Mode register set (Fixed) +;// CL: CAS Latency +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks +;// BT: Burst Type +;// <0=> Sequential (Fixed) +;// BL: Burst Length +;// <0=> 1 (Fixed) +;// +;// SDRAM Mode Register Set Register 7 (MRSRB7) +;// WBL: Write Burst Length +;// <0=> Burst (Fixed) +;// TM: Test Mode +;// <0=> Mode register set (Fixed) +;// CL: CAS Latency +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks +;// BT: Burst Type +;// <0=> Sequential (Fixed) +;// BL: Burst Length +;// <0=> 1 (Fixed) +;// +;// Memory Controller Setup +MC_SETUP EQU 0 +BWSCON_Val EQU 0x22000000 +BANKCON0_Val EQU 0x00000700 +BANKCON1_Val EQU 0x00000700 +BANKCON2_Val EQU 0x00000700 +BANKCON3_Val EQU 0x00000700 +BANKCON4_Val EQU 0x00000700 +BANKCON5_Val EQU 0x00000700 +BANKCON6_Val EQU 0x00018005 +BANKCON7_Val EQU 0x00018005 +REFRESH_Val EQU 0x008404F3 +BANKSIZE_Val EQU 0x00000032 +MRSRB6_Val EQU 0x00000020 +MRSRB7_Val EQU 0x00000020 + + +;----------------------- I/O Port Definitions ---------------------------------- + +GPA_BASE EQU 0x56000000 ; GPA Base Address +GPB_BASE EQU 0x56000010 ; GPB Base Address +GPC_BASE EQU 0x56000020 ; GPC Base Address +GPD_BASE EQU 0x56000030 ; GPD Base Address +GPE_BASE EQU 0x56000040 ; GPE Base Address +GPF_BASE EQU 0x56000050 ; GPF Base Address +GPG_BASE EQU 0x56000060 ; GPG Base Address +GPH_BASE EQU 0x56000070 ; GPH Base Address +GPJ_BASE EQU 0x560000D0 ; GPJ Base Address +GPCON_OFS EQU 0x00 ; Control Register Offset +GPDAT_OFS EQU 0x04 ; Data Register Offset +GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset + +;// I/O Setup +GP_SETUP EQU 1 + +;// Port A Settings +;// Port A Control Register (GPACON) +;// GPA22 <0=> Output <1=> nFCE +;// GPA21 <0=> Output <1=> nRSTOUT +;// GPA20 <0=> Output <1=> nFRE +;// GPA19 <0=> Output <1=> nFWE +;// GPA18 <0=> Output <1=> ALE +;// GPA17 <0=> Output <1=> CLE +;// GPA16 <0=> Output <1=> nGCS[5] +;// GPA15 <0=> Output <1=> nGCS[4] +;// GPA14 <0=> Output <1=> nGCS[3] +;// GPA13 <0=> Output <1=> nGCS[2] +;// GPA12 <0=> Output <1=> nGCS[1] +;// GPA11 <0=> Output <1=> ADDR26 +;// GPA10 <0=> Output <1=> ADDR25 +;// GPA9 <0=> Output <1=> ADDR24 +;// GPA8 <0=> Output <1=> ADDR23 +;// GPA7 <0=> Output <1=> ADDR22 +;// GPA6 <0=> Output <1=> ADDR21 +;// GPA5 <0=> Output <1=> ADDR20 +;// GPA4 <0=> Output <1=> ADDR19 +;// GPA3 <0=> Output <1=> ADDR18 +;// GPA2 <0=> Output <1=> ADDR17 +;// GPA1 <0=> Output <1=> ADDR16 +;// GPA0 <0=> Output <1=> ADDR0 +;// +;// +GPA_SETUP EQU 0 +GPACON_Val EQU 0x000003FF + +;// Port B Settings +;// Port B Control Register (GPBCON) +;// GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved +;// GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved +;// GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved +;// GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved +;// GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved +;// GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved +;// GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved +;// GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved +;// GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved +;// GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved +;// GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved +;// +;// Port B Pull-up Settings Register (GPBUP) +;// GPB10 Pull-up Disable +;// GPB9 Pull-up Disable +;// GPB8 Pull-up Disable +;// GPB7 Pull-up Disable +;// GPB6 Pull-up Disable +;// GPB5 Pull-up Disable +;// GPB4 Pull-up Disable +;// GPB3 Pull-up Disable +;// GPB2 Pull-up Disable +;// GPB1 Pull-up Disable +;// GPB0 Pull-up Disable +;// +;// +GPB_SETUP EQU 0 +GPBCON_Val EQU 0x00000000 +GPBUP_Val EQU 0x00000000 + +;// Port C Settings +;// Port C Control Register (GPCCON) +;// GPC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved +;// GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved +;// GPC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved +;// GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved +;// GPC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved +;// GPC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved +;// GPC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved +;// GPC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved +;// GPC7 <0=> Input <1=> Output <2=> LCD_LPCREVB <3=> Reserved +;// GPC6 <0=> Input <1=> Output <2=> LCD_LPCREV <3=> Reserved +;// GPC5 <0=> Input <1=> Output <2=> LCD_LPCOE <3=> Reserved +;// GPC4 <0=> Input <1=> Output <2=> VM <3=> I2SSDI +;// GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved +;// GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved +;// GPC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved +;// GPC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved +;// +;// Port C Pull-up Settings Register (GPCUP) +;// GPC15 Pull-up Disable +;// GPC14 Pull-up Disable +;// GPC13 Pull-up Disable +;// GPC12 Pull-up Disable +;// GPC11 Pull-up Disable +;// GPC10 Pull-up Disable +;// GPC9 Pull-up Disable +;// GPC8 Pull-up Disable +;// GPC7 Pull-up Disable +;// GPC6 Pull-up Disable +;// GPC5 Pull-up Disable +;// GPC4 Pull-up Disable +;// GPC3 Pull-up Disable +;// GPC2 Pull-up Disable +;// GPC1 Pull-up Disable +;// GPC0 Pull-up Disable +;// +;// +GPC_SETUP EQU 0 +GPCCON_Val EQU 0x00000000 +GPCUP_Val EQU 0x00000000 + +;// Port D Settings +;// Port D Control Register (GPDCON) +;// GPD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0 +;// GPD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1 +;// GPD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved +;// GPD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved +;// GPD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved +;// GPD10 <0=> Input <1=> Output <2=> VD[18] <3=> SPICLK1 +;// GPD9 <0=> Input <1=> Output <2=> VD[17] <3=> SPIMOSI1 +;// GPD8 <0=> Input <1=> Output <2=> VD[16] <3=> SPIMISO1 +;// GPD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved +;// GPD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved +;// GPD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved +;// GPD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved +;// GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved +;// GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved +;// GPD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved +;// GPD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved +;// +;// Port D Pull-up Settings Register (GPDUP) +;// GPD15 Pull-up Disable +;// GPD14 Pull-up Disable +;// GPD13 Pull-up Disable +;// GPD12 Pull-up Disable +;// GPD11 Pull-up Disable +;// GPD10 Pull-up Disable +;// GPD9 Pull-up Disable +;// GPD8 Pull-up Disable +;// GPD7 Pull-up Disable +;// GPD6 Pull-up Disable +;// GPD5 Pull-up Disable +;// GPD4 Pull-up Disable +;// GPD3 Pull-up Disable +;// GPD2 Pull-up Disable +;// GPD1 Pull-up Disable +;// GPD0 Pull-up Disable +;// +;// +GPD_SETUP EQU 0 +GPDCON_Val EQU 0x00000000 +GPDUP_Val EQU 0x00000000 + +;// Port E Settings +;// Port E Control Register (GPECON) +;// GPE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved +;// This pad is open-drain, and has no pull-up option. +;// GPE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved +;// This pad is open-drain, and has no pull-up option. +;// GPE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved +;// GPE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved +;// GPE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved +;// GPE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved +;// GPE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved +;// GPE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved +;// GPE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved +;// GPE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved +;// GPE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved +;// GPE4 <0=> Input <1=> Output <2=> I2SDO <3=> AC_SDATA_OUT +;// GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN +;// GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET +;// GPE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> AC_BIT_CLK +;// GPE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> AC_SYNC +;// +;// Port E Pull-up Settings Register (GPEUP) +;// GPE13 Pull-up Disable +;// GPE12 Pull-up Disable +;// GPE11 Pull-up Disable +;// GPE10 Pull-up Disable +;// GPE9 Pull-up Disable +;// GPE8 Pull-up Disable +;// GPE7 Pull-up Disable +;// GPE6 Pull-up Disable +;// GPE5 Pull-up Disable +;// GPE4 Pull-up Disable +;// GPE3 Pull-up Disable +;// GPE2 Pull-up Disable +;// GPE1 Pull-up Disable +;// GPE0 Pull-up Disable +;// +;// +GPE_SETUP EQU 0 +GPECON_Val EQU 0x00000000 +GPEUP_Val EQU 0x00000000 + +;// Port F Settings +;// Port F Control Register (GPFCON) +;// GPF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved +;// GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved +;// GPF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved +;// GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved +;// GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved +;// GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved +;// GPF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved +;// GPF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved +;// +;// Port F Pull-up Settings Register (GPFUP) +;// GPF7 Pull-up Disable +;// GPF6 Pull-up Disable +;// GPF5 Pull-up Disable +;// GPF4 Pull-up Disable +;// GPF3 Pull-up Disable +;// GPF2 Pull-up Disable +;// GPF1 Pull-up Disable +;// GPF0 Pull-up Disable +;// +;// +GPF_SETUP EQU 1 +GPFCON_Val EQU 0x000000AA +GPFUP_Val EQU 0x0000000F + +;// Port G Settings +;// Port G Control Register (GPGCON) +;// GPG15 <0=> Input <1=> Output <2=> EINT[23] <3=> Reserved +;// GPG14 <0=> Input <1=> Output <2=> EINT[22] <3=> Reserved +;// GPG13 <0=> Input <1=> Output <2=> EINT[21] <3=> Reserved +;// GPG12 <0=> Input <1=> Output <2=> EINT[20] <3=> Reserved +;// GPG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK[1] +;// GPG10 <0=> Input <1=> Output <2=> EINT[18] <3=> nCTS1 +;// GPG9 <0=> Input <1=> Output <2=> EINT[17] <3=> nRTS1 +;// GPG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved +;// GPG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1 +;// GPG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1 +;// GPG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1 +;// GPG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN +;// GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1 +;// GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0 +;// GPG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved +;// GPG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved +;// +;// Port G Pull-up Settings Register (GPGUP) +;// GPG15 Pull-up Disable +;// GPG14 Pull-up Disable +;// GPG13 Pull-up Disable +;// GPG12 Pull-up Disable +;// GPG11 Pull-up Disable +;// GPG10 Pull-up Disable +;// GPG9 Pull-up Disable +;// GPG8 Pull-up Disable +;// GPG7 Pull-up Disable +;// GPG6 Pull-up Disable +;// GPG5 Pull-up Disable +;// GPG4 Pull-up Disable +;// GPG3 Pull-up Disable +;// GPG2 Pull-up Disable +;// GPG1 Pull-up Disable +;// GPG0 Pull-up Disable +;// +;// +GPG_SETUP EQU 0 +GPGCON_Val EQU 0x00000000 +GPGUP_Val EQU 0x00000000 + +;// Port H Settings +;// Port H Control Register (GPHCON) +;// GPH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved +;// GPH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved +;// GPH8 <0=> Input <1=> Output <2=> UEXTCLK <3=> Reserved +;// GPH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1 +;// GPH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1 +;// GPH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved +;// GPH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved +;// GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved +;// GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved +;// GPH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved +;// GPH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved +;// +;// Port H Pull-up Settings Register (GPHUP) +;// GPH10 Pull-up Disable +;// GPH9 Pull-up Disable +;// GPH8 Pull-up Disable +;// GPH7 Pull-up Disable +;// GPH6 Pull-up Disable +;// GPH5 Pull-up Disable +;// GPH4 Pull-up Disable +;// GPH3 Pull-up Disable +;// GPH2 Pull-up Disable +;// GPH1 Pull-up Disable +;// GPH0 Pull-up Disable +;// +;// +GPH_SETUP EQU 0 +GPHCON_Val EQU 0x00000000 +GPHUP_Val EQU 0x00000000 + +;// Port J Settings +;// Port J Control Register (GPJCON) +;// GPJ12 <0=> Input <1=> Output <2=> CAMRESET <3=> Reserved +;// GPJ11 <0=> Input <1=> Output <2=> CAMCLKOUT <3=> Reserved +;// GPJ10 <0=> Input <1=> Output <2=> CAMHREF <3=> Reserved +;// GPJ9 <0=> Input <1=> Output <2=> CAMVSYNC <3=> Reserved +;// GPJ8 <0=> Input <1=> Output <2=> CAMPCLK <3=> Reserved +;// GPJ7 <0=> Input <1=> Output <2=> CAMDATA[7] <3=> Reserved +;// GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved +;// GPJ5 <0=> Input <1=> Output <2=> CAMDATA[5] <3=> Reserved +;// GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved +;// GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved +;// GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved +;// GPJ1 <0=> Input <1=> Output <2=> CAMDATA[1] <3=> Reserved +;// GPJ0 <0=> Input <1=> Output <2=> CAMDATA[0] <3=> Reserved +;// +;// Port J Pull-up Settings Register (GPJUP) +;// GPJ12 Pull-up Disable +;// GPJ11 Pull-up Disable +;// GPJ10 Pull-up Disable +;// GPJ9 Pull-up Disable +;// GPJ8 Pull-up Disable +;// GPJ7 Pull-up Disable +;// GPJ6 Pull-up Disable +;// GPJ5 Pull-up Disable +;// GPJ4 Pull-up Disable +;// GPJ3 Pull-up Disable +;// GPJ2 Pull-up Disable +;// GPJ1 Pull-up Disable +;// GPJ0 Pull-up Disable +;// +;// +GPJ_SETUP EQU 0 +GPJCON_Val EQU 0x00000000 +GPJUP_Val EQU 0x00000000 + +;// I/O Setup + + +;----------------------- CODE -------------------------------------------------- + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + + EXPORT Entry_Point +Entry_Point +Vectors LDR PC, Reset_Addr + LDR PC, Undef_Addr + LDR PC, SWI_Addr + LDR PC, PAbt_Addr + LDR PC, DAbt_Addr + NOP + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B PAbt_Handler +;DAbt_Handler B DAbt_Handler +FIQ_Handler B FIQ_Handler + +;* +;************************************************************************* +;* +;* Interrupt handling +;* +;************************************************************************* +;* +; DAbt Handler +DAbt_Handler + IMPORT rt_hw_trap_dabt + + sub sp, sp, #72 + stmia sp, {r0 - r12} ;/* Calling r0-r12 */ + add r8, sp, #60 + stmdb r8, {sp, lr} ;/* Calling SP, LR */ + str lr, [r8, #0] ;/* Save calling PC */ + mrs r6, spsr + str r6, [r8, #4] ;/* Save CPSR */ + str r0, [r8, #8] ;/* Save OLD_R0 */ + mov r0, sp + + bl rt_hw_trap_dabt + + +;########################################## +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; Watchdog Setup --------------------------------------------------------------- + + IF WT_SETUP != 0 + LDR R0, =WT_BASE + LDR R1, =WTCON_Val + LDR R2, =WTDAT_Val + STR R2, [R0, #WTCNT_OFS] + STR R2, [R0, #WTDAT_OFS] + STR R1, [R0, #WTCON_OFS] + ENDIF + + +; Clock Setup ------------------------------------------------------------------ + + IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) + LDR R0, =CLOCK_BASE + LDR R1, =LOCKTIME_Val + STR R1, [R0, #LOCKTIME_OFS] + MOV R1, #CLKDIVN_Val + STR R1, [R0, #CLKDIVN_OFS] + LDR R1, =CAMDIVN_Val + STR R1, [R0, #CAMDIVN_OFS] + LDR R1, =MPLLCON_Val + STR R1, [R0, #MPLLCON_OFS] + LDR R1, =UPLLCON_Val + STR R1, [R0, #UPLLCON_OFS] + MOV R1, #CLKSLOW_Val + STR R1, [R0, #CLKSLOW_OFS] + LDR R1, =CLKCON_Val + STR R1, [R0, #CLKCON_OFS] + ENDIF + + +; Memory Controller Setup ------------------------------------------------------ + + IF (:LNOT:(:DEF:NO_MC_SETUP)):LAND:(CLOCK_SETUP != 0) + LDR R0, =MC_BASE + LDR R1, =BWSCON_Val + STR R1, [R0, #BWSCON_OFS] + LDR R1, =BANKCON0_Val + STR R1, [R0, #BANKCON0_OFS] + LDR R1, =BANKCON1_Val + STR R1, [R0, #BANKCON1_OFS] + LDR R1, =BANKCON2_Val + STR R1, [R0, #BANKCON2_OFS] + LDR R1, =BANKCON3_Val + STR R1, [R0, #BANKCON3_OFS] + LDR R1, =BANKCON4_Val + STR R1, [R0, #BANKCON4_OFS] + LDR R1, =BANKCON5_Val + STR R1, [R0, #BANKCON5_OFS] + LDR R1, =BANKCON6_Val + STR R1, [R0, #BANKCON6_OFS] + LDR R1, =BANKCON7_Val + STR R1, [R0, #BANKCON7_OFS] + LDR R1, =REFRESH_Val + STR R1, [R0, #REFRESH_OFS] + MOV R1, #BANKSIZE_Val + STR R1, [R0, #BANKSIZE_OFS] + MOV R1, #MRSRB6_Val + STR R1, [R0, #MRSRB6_OFS] + MOV R1, #MRSRB7_Val + STR R1, [R0, #MRSRB7_OFS] + ENDIF + + +; I/O Pins Setup --------------------------------------------------------------- + + IF (:LNOT:(:DEF:NO_GP_SETUP)):LAND:(GP_SETUP != 0) + + IF GPA_SETUP != 0 + LDR R0, =GPA_BASE + LDR R1, =GPACON_Val + STR R1, [R0, #GPCON_OFS] + ENDIF + + IF GPB_SETUP != 0 + LDR R0, =GPB_BASE + LDR R1, =GPBCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPBUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPC_SETUP != 0 + LDR R0, =GPC_BASE + LDR R1, =GPCCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPCUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPD_SETUP != 0 + LDR R0, =GPD_BASE + LDR R1, =GPDCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPDUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPE_SETUP != 0 + LDR R0, =GPE_BASE + LDR R1, =GPECON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPEUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPF_SETUP != 0 + LDR R0, =GPF_BASE + LDR R1, =GPFCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPFUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPG_SETUP != 0 + LDR R0, =GPG_BASE + LDR R1, =GPGCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPGUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPH_SETUP != 0 + LDR R0, =GPH_BASE + LDR R1, =GPHCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPHUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPJ_SETUP != 0 + LDR R0, =GPJ_BASE + LDR R1, =GPJCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPJUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + ENDIF + + +; Copy Exception Vectors to Internal RAM --------------------------------------- + + IF :DEF:RAM_INTVEC + ADR R8, Vectors ; Source + LDR R9, =IRAM_BASE ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + ENDIF + + +; Setup Stack for each mode ---------------------------------------------------- + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; MSR CPSR_c, #Mode_USR + MOV SP, R0 + SUB SL, SP, #USR_Stack_Size + +; Enter the C code ------------------------------------------------------------- + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + + END + diff --git a/libcpu/arm/s3c24x0/system_clock.c b/libcpu/arm/s3c24x0/system_clock.c index bd2a6690db7fd45013ca86be838e8ddbe16f28d9..c87c5966e9814c192d4b18afab24624bcd8d88b8 100644 --- a/libcpu/arm/s3c24x0/system_clock.c +++ b/libcpu/arm/s3c24x0/system_clock.c @@ -1,108 +1,108 @@ -/* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-04-25 Yi.qiu first version - */ - -#include -#include "s3c24x0.h" - -#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz - -#if CONFIG_SYS_CLK_FREQ == 12000000 - /* MPLL=2*12*100/6=400MHz */ - #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ - #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ - #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ - /* UPLL=12*64/8=96MHz */ - #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ - #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ - #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ - /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ - #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ - #define HDIVN 0x2 /* HCLK = FCLK / 4 */ - #define PDIVN 0x1 /* PCLK = HCLK / 2 */ -#endif - -rt_uint32_t PCLK; -rt_uint32_t FCLK; -rt_uint32_t HCLK; -rt_uint32_t UCLK; - -void rt_hw_get_clock(void) -{ - rt_uint32_t val; - rt_uint8_t m, p, s; - - val = MPLLCON; - m = (val>>12)&0xff; - p = (val>>4)&0x3f; - s = val&3; - - FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<>1)&3; - p = val&1; - - switch (m) { - case 0: - HCLK = FCLK; - break; - case 1: - HCLK = FCLK>>1; - break; - case 2: - if(s&2) - HCLK = FCLK>>3; - else - HCLK = FCLK>>2; - break; - case 3: - if(s&1) - HCLK = FCLK/6; - else - HCLK = FCLK/3; - break; -} - - if(p) - PCLK = HCLK>>1; - else - PCLK = HCLK; -} - -void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) -{ - MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); -} - -void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) -{ - UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; -} - -void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) -{ - CLKDIVN = (hdivn<<1) | pdivn; -} - -/** - * @brief System Clock Configuration - */ -void rt_hw_clock_init(void) -{ - LOCKTIME = 0xFFFFFFFF; - rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); - rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); - rt_hw_set_divider(HDIVN, PDIVN); -} - +/* + * File : clock.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-04-25 Yi.qiu first version + */ + +#include +#include "s3c24x0.h" + +#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz + +#if CONFIG_SYS_CLK_FREQ == 12000000 + /* MPLL=2*12*100/6=400MHz */ + #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ + #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ + #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ + /* UPLL=12*64/8=96MHz */ + #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ + #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ + #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ + /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ + #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ + #define HDIVN 0x2 /* HCLK = FCLK / 4 */ + #define PDIVN 0x1 /* PCLK = HCLK / 2 */ +#endif + +rt_uint32_t PCLK; +rt_uint32_t FCLK; +rt_uint32_t HCLK; +rt_uint32_t UCLK; + +void rt_hw_get_clock(void) +{ + rt_uint32_t val; + rt_uint8_t m, p, s; + + val = MPLLCON; + m = (val>>12)&0xff; + p = (val>>4)&0x3f; + s = val&3; + + FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<>1)&3; + p = val&1; + + switch (m) { + case 0: + HCLK = FCLK; + break; + case 1: + HCLK = FCLK>>1; + break; + case 2: + if(s&2) + HCLK = FCLK>>3; + else + HCLK = FCLK>>2; + break; + case 3: + if(s&1) + HCLK = FCLK/6; + else + HCLK = FCLK/3; + break; +} + + if(p) + PCLK = HCLK>>1; + else + PCLK = HCLK; +} + +void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) +{ + MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); +} + +void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) +{ + UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; +} + +void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) +{ + CLKDIVN = (hdivn<<1) | pdivn; +} + +/** + * @brief System Clock Configuration + */ +void rt_hw_clock_init(void) +{ + LOCKTIME = 0xFFFFFFFF; + rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); + rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); + rt_hw_set_divider(HDIVN, PDIVN); +} + diff --git a/libcpu/arm/s3c24x0/trap.c b/libcpu/arm/s3c24x0/trap.c index 09f1c88bcaf779a1d5d3da5477a3570d7d550ae5..bdeae9aab02e93f95cf82c4451fe5380821f97d6 100644 --- a/libcpu/arm/s3c24x0/trap.c +++ b/libcpu/arm/s3c24x0/trap.c @@ -157,7 +157,7 @@ void rt_hw_trap_irq() /* turn to interrupt service routine */ isr_func(intstat); - /* clear pending register */ + /* clear pending register */ /* note: must be the last, if not, may repeat*/ ClearPending(1 << intstat); } diff --git a/libcpu/arm/s3c44b0/context_rvds.S b/libcpu/arm/s3c44b0/context_rvds.S index e24fa62a3dd5dd1f46ed2c32255752e171173e46..641ec7a6b1a18b5d8fff4b927e2ad5549ca65f01 100644 --- a/libcpu/arm/s3c44b0/context_rvds.S +++ b/libcpu/arm/s3c44b0/context_rvds.S @@ -12,12 +12,12 @@ ; * 2009-01-20 Bernard first version ; */ -NOINT EQU 0xc0 ; disable interrupt in psr +NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 + AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1 + MSR cpsr_c, r1 BX lr - ENDP + ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 + MSR cpsr_c, r0 BX lr ENDP @@ -63,7 +63,7 @@ rt_hw_context_switch PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP + ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP + ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread + IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] + STR r1, [r2] BX lr - ENDP - + ENDP + END \ No newline at end of file diff --git a/libcpu/arm/s3c44b0/s3c44b0.h b/libcpu/arm/s3c44b0/s3c44b0.h index 36f9f5a1e4c8c942134a9124ffac3cc64b06aa05..16e8e3a2409567579f5cff336f106588c27531f6 100644 --- a/libcpu/arm/s3c44b0/s3c44b0.h +++ b/libcpu/arm/s3c44b0/s3c44b0.h @@ -213,27 +213,27 @@ extern "C" { #define F_ISPR (S3C_REG(0x1e00038)) #define F_ISPC (S3C_REG(0x1e0003c)) -/********************************/ -/* LCD Controller Registers */ -/********************************/ -#define LCDCON1 (S3C_REG(0x300000)) -#define LCDCON2 (S3C_REG(0x300004)) -#define LCDSADDR1 (S3C_REG(0x300008)) -#define LCDSADDR2 (S3C_REG(0x30000c)) -#define LCDSADDR3 (S3C_REG(0x300010)) -#define REDLUT (S3C_REG(0x300014)) -#define GREENLUT (S3C_REG(0x300018)) -#define BLUELUT (S3C_REG(0x30001c)) -#define DP1_2 (S3C_REG(0x300020)) -#define DP4_7 (S3C_REG(0x300024)) -#define DP3_5 (S3C_REG(0x300028)) -#define DP2_3 (S3C_REG(0x30002c)) -#define DP5_7 (S3C_REG(0x300030)) -#define DP3_4 (S3C_REG(0x300034)) -#define DP4_5 (S3C_REG(0x300038)) -#define DP6_7 (S3C_REG(0x30003c)) -#define LCDCON3 (S3C_REG(0x300040)) -#define DITHMODE (S3C_REG(0x300044)) +/********************************/ +/* LCD Controller Registers */ +/********************************/ +#define LCDCON1 (S3C_REG(0x300000)) +#define LCDCON2 (S3C_REG(0x300004)) +#define LCDSADDR1 (S3C_REG(0x300008)) +#define LCDSADDR2 (S3C_REG(0x30000c)) +#define LCDSADDR3 (S3C_REG(0x300010)) +#define REDLUT (S3C_REG(0x300014)) +#define GREENLUT (S3C_REG(0x300018)) +#define BLUELUT (S3C_REG(0x30001c)) +#define DP1_2 (S3C_REG(0x300020)) +#define DP4_7 (S3C_REG(0x300024)) +#define DP3_5 (S3C_REG(0x300028)) +#define DP2_3 (S3C_REG(0x30002c)) +#define DP5_7 (S3C_REG(0x300030)) +#define DP3_4 (S3C_REG(0x300034)) +#define DP4_5 (S3C_REG(0x300038)) +#define DP6_7 (S3C_REG(0x30003c)) +#define LCDCON3 (S3C_REG(0x300040)) +#define DITHMODE (S3C_REG(0x300044)) /* ZDMA0 */ #define ZDCON0 (S3C_REG(0x1e80000)) diff --git a/libcpu/arm/s3c44b0/start_gcc.S b/libcpu/arm/s3c44b0/start_gcc.S index ff9398c0b76380bc36a8f4bd7908448f3db4184a..17a3d0da7f597836ff80f06f537ccc2d9c232b70 100644 --- a/libcpu/arm/s3c44b0/start_gcc.S +++ b/libcpu/arm/s3c44b0/start_gcc.S @@ -238,20 +238,20 @@ stack_setup: .globl led_on led_on: - ldr r1, =0x1d20014 @ r1<-PDATC - ldr r0, [r1] @ r0<-[r1] - orr r0, r0, #0x0e @ r0=r0 or 0x0e - str r0, [r1] @ r0->[r1] + ldr r1, =0x1d20014 @ r1<-PDATC + ldr r0, [r1] @ r0<-[r1] + orr r0, r0, #0x0e @ r0=r0 or 0x0e + str r0, [r1] @ r0->[r1] mov pc, lr .globl led_off led_off: - ldr r1, =0x1d20010 @ r1<-PCONC - ldr r0, =0x5f555555 @ r0<-0x5f555555 - str r0, [r1] @ r0->[r1] - - ldr r1, =0x1d20014 @ r1<-PDATC - ldr r0, =0x0 @ r0<-00 - str r0, [r1] @ r0->[r1] - - mov pc, lr + ldr r1, =0x1d20010 @ r1<-PCONC + ldr r0, =0x5f555555 @ r0<-0x5f555555 + str r0, [r1] @ r0->[r1] + + ldr r1, =0x1d20014 @ r1<-PDATC + ldr r0, =0x0 @ r0<-00 + str r0, [r1] @ r0->[r1] + + mov pc, lr diff --git a/libcpu/arm/s3c44b0/start_rvds.S b/libcpu/arm/s3c44b0/start_rvds.S index 192120dff5d230c34ac400afd9ce4350331f57f8..b5c9048e12b6b20e4806b5c5e16d26b197f6276d 100644 --- a/libcpu/arm/s3c44b0/start_rvds.S +++ b/libcpu/arm/s3c44b0/start_rvds.S @@ -1,1072 +1,1072 @@ -;/*****************************************************************************/ -;/* S3C44B0X.S: Startup file for Samsung S3C44B0X */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -; *** Startup Code (executed after Reset) *** - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000100 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000100 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -; CPU Wrapper and Bus Priorities definitions -CPUW_BASE EQU 0x01C00000 ; CPU Wrapper Base Address -SYSCFG_OFS EQU 0x00 ; SYSCFG Offset -NCACHBE0_OFS EQU 0x04 ; NCACHBE0 Offset -NCACHBE1_OFS EQU 0x08 ; NCACHBE0 Offset -BUSP_BASE EQU 0x01C40000 ; Bus Priority Base Address -SBUSCON_OFS EQU 0x00 ; SBUSCON Offset - -;// CPU Wrapper and Bus Priorities -;// CPU Wrapper -;// SE: Stall Enable -;// CM: Cache Mode -;// <0=> Disable Cache (8kB SRAM) -;// <1=> Half Cache Enable (4kB Cache, 4kB SRAM) -;// <2=> Reserved -;// <3=> Full Cache Enable (8kB Cache) -;// WE: Write Buffer Enable -;// RSE: Read Stall Enable -;// DA: Data Abort <0=> Enable <1=> Disable -;// Non-cacheable Area 0 -;// Start Address <0x0-0x0FFFF000:0x1000><#/0x1000> -;// SA = (Start Address) / 4k -;// End Address + 1 <0x0-0x10000000:0x1000><#/0x1000> -;// SE = (End Address + 1) / 4k -;// -;// Non-cacheable Area 1 -;// Start Address <0x0-0x0FFFF000:0x1000><#/0x1000> -;// SA = (Start Address) / 4k -;// End Address + 1 <0x0-0x10000000:0x1000><#/0x1000> -;// SE = (End Address + 1) / 4k -;// -;// -;// Bus Priorities -;// FIX: Fixed Priorities -;// LCD_DMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th -;// ZDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th -;// BDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th -;// nBREQ <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th -;// -;// -SYS_SETUP EQU 0 -SYSCFG_Val EQU 0x00000001 -NCACHBE0_Val EQU 0x00000000 -NCACHBE1_Val EQU 0x00000000 -SBUSCON_Val EQU 0x80001B1B - - -;// Vectored Interrupt Mode (for IRQ) -;// EINT0 External Interrupt 0 -;// EINT1 External Interrupt 1 -;// EINT2 External Interrupt 2 -;// EINT3 External Interrupt 3 -;// EINT4567 External Interrupt 4/5/6/7 -;// TICK RTC Time Tick Interrupt -;// ZDMA0 General DMA0 Interrupt -;// ZDMA1 General DMA1 Interrupt -;// BDMA0 Bridge DMA0 Interrupt -;// BDMA1 Bridge DMA1 Interrupt -;// WDT Watchdog Timer Interrupt -;// UERR01 UART0/1 Error Interrupt -;// TIMER0 Timer0 Interrupt -;// TIMER1 Timer1 Interrupt -;// TIMER2 Timer2 Interrupt -;// TIMER3 Timer3 Interrupt -;// TIMER4 Timer4 Interrupt -;// TIMER5 Timer5 Interrupt -;// URXD0 UART0 Rx Interrupt -;// URXD1 UART1 Rx Interrupt -;// IIC IIC Interrupt -;// SIO SIO Interrupt -;// UTXD0 UART0 Tx Interrupt -;// UTXD1 UART1 Tx Interrupt -;// RTC RTC Alarm Interrupt -;// ADC ADC EOC Interrupt -;// -VIM_SETUP EQU 0 -VIM_CFG EQU 0x00000000 - - -; Clock Management definitions -CLK_BASE EQU 0x01D80000 ; Clock Base Address -PLLCON_OFS EQU 0x00 ; PLLCON Offset -CLKCON_OFS EQU 0x04 ; CLKCON Offset -CLKSLOW_OFS EQU 0x08 ; CLKSLOW Offset -LOCKTIME_OFS EQU 0x0C ; LOCKTIME Offset - -;// Clock Management -;// PLL Settings -;// Fpllo = (m * Fin) / (p * 2^s), 20MHz < Fpllo < 66MHz -;// MDIV: Main divider <0x0-0xFF> -;// m = MDIV + 8 -;// PDIV: Pre-divider <0x0-0x3F> -;// p = PDIV + 2, 1MHz <= Fin/p < 2MHz -;// SDIV: Post Divider <0x0-0x03> -;// s = SDIV, Fpllo * 2^s < 170MHz -;// LTIME CNT: PLL Lock Time Count <0x0-0x0FFF> -;// -;// Master Clock -;// PLL Clock: Fout = Fpllo -;// Slow Clock: Fout = Fin / (2 * SLOW_VAL), SLOW_VAL > 0 -;// Slow Clock: Fout = Fin, SLOW_VAL = 0 -;// PLL_OFF: PLL Off -;// PLL is turned Off only when SLOW_BIT = 1 -;// SLOW_BIT: Slow Clock -;// SLOW_VAL: Slow Clock divider <0x0-0x0F> -;// -;// Clock Generation -;// IIS <0=> Disable <1=> Enable -;// IIC <0=> Disable <1=> Enable -;// ADC <0=> Disable <1=> Enable -;// RTC <0=> Disable <1=> Enable -;// GPIO <0=> Disable <1=> Enable -;// UART1 <0=> Disable <1=> Enable -;// UART0 <0=> Disable <1=> Enable -;// BDMA0,1 <0=> Disable <1=> Enable -;// LCDC <0=> Disable <1=> Enable -;// SIO <0=> Disable <1=> Enable -;// ZDMA0,1 <0=> Disable <1=> Enable -;// PWMTIMER <0=> Disable <1=> Enable -;// -;// -CLK_SETUP EQU 1 -PLLCON_Val EQU 0x00038080 -CLKCON_Val EQU 0x00007FF8 -CLKSLOW_Val EQU 0x00000009 -LOCKTIME_Val EQU 0x00000FFF - - -; Watchdog Timer definitions -WT_BASE EQU 0x01D30000 ; WT Base Address -WTCON_OFS EQU 0x00 ; WTCON Offset -WTDAT_OFS EQU 0x04 ; WTDAT Offset -WTCNT_OFS EQU 0x08 ; WTCNT Offset - -;// Watchdog Timer -;// Watchdog Timer Enable/Disable -;// Reset Enable/Disable -;// Interrupt Enable/Disable -;// Clock Select -;// <0=> 1/16 <1=> 1/32 <2=> 1/64 <3=> 1/128 -;// Clock Division Factor -;// Prescaler Value <0x0-0xFF> -;// Time-out Value <0x0-0xFFFF> -;// -WT_SETUP EQU 1 -WTCON_Val EQU 0x00008000 -WTDAT_Val EQU 0x00008000 - - -; Memory Controller definitions -MC_BASE EQU 0x01C80000 ; Memory Controller Base Address - -;// Memory Controller -MC_SETUP EQU 1 - -;// Bank 0 -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 1 -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 2 -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 3 -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 4 -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 5 -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 6 -;// BK76MAP: Bank 6/7 Memory Map -;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// MT: Memory Type -;// <0=> ROM or SRAM -;// <1=> FP DRAMP -;// <2=> EDO DRAM -;// <3=> SDRAM -;// ROM or SRAM -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// FP DRAM or EDO DRAM -;// CAN: Columnn Address Number -;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit -;// Tcp: CAS Pre-charge -;// <0=> 1 clk <1=> 2 clks -;// Tcas: CAS Pulse Width -;// <0=> 1 clk <1=> 2 clks -;// Trcd: RAS to CAS Delay -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// -;// SDRAM -;// SCAN: Columnn Address Number -;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd -;// Trcd: RAS to CAS Delay -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd -;// SCLKEN: SCLK Selection (Bank 6/7) -;// <0=> Normal -;// <1=> Reduced Power -;// BL: Burst Length -;// <0=> 1 -;// BT: Burst Type -;// <0=> Sequential -;// CL: CAS Latency -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks -;// TM: Test Mode -;// <0=> Mode Register Set -;// WBL: Write Burst Length -;// <0=> 0 -;// -;// -;// -;// Bank 7 -;// BK76MAP: Bank 6/7 Memory Map -;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// MT: Memory Type -;// <0=> ROM or SRAM -;// <1=> FP DRAMP -;// <2=> EDO DRAM -;// <3=> SDRAM -;// ROM or SRAM -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// FP DRAM or EDO DRAM -;// CAN: Columnn Address Number -;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit -;// Tcp: CAS Pre-charge -;// <0=> 1 clk <1=> 2 clks -;// Tcas: CAS Pulse Width -;// <0=> 1 clk <1=> 2 clks -;// Trcd: RAS to CAS Delay -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// -;// SDRAM -;// SCAN: Columnn Address Number -;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd -;// Trcd: RAS to CAS Delay -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd -;// SCLKEN: SCLK Selection (Bank 6/7) -;// <0=> Normal -;// <1=> Reduced Power -;// BL: Burst Length -;// <0=> 1 -;// BT: Burst Type -;// <0=> Sequential -;// CL: CAS Latency -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks -;// TM: Test Mode -;// <0=> Mode Register Set -;// WBL: Write Burst Length -;// <0=> 0 -;// -;// -;// -;// Refresh -;// REFEN: DRAM/SDRAM Refresh -;// <0=> Disable <1=> Enable -;// TREFMD: DRAM/SDRAM Refresh Mode -;// <0=> CBR/Auto Refresh -;// <1=> Self Refresh -;// Trp: DRAM/SDRAM RAS Pre-charge Time -;// <0=> 1.5 clks (DRAM) / 2 clks (SDRAM) -;// <1=> 2.5 clks (DRAM) / 3 clks (SDRAM) -;// <2=> 3.5 clks (DRAM) / 4 clks (SDRAM) -;// <3=> 4.5 clks (DRAM) / Rsrvd (SDRAM) -;// Trc: SDRAM RC Min Time -;// <0=> 4 clks <1=> 5 clks <2=> 6 clks <3=> 7 clks -;// Tchr: DRAM CAS Hold Time -;// <0=> 1 clks <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// Refresh Counter <0x0-0x07FF> -;// Refresh Period = (2^11 - Refresh Count + 1) / MCLK -;// -BANKCON0_Val EQU 0x00000700 -BANKCON1_Val EQU 0x00000700 -BANKCON2_Val EQU 0x00000700 -BANKCON3_Val EQU 0x00000700 -BANKCON4_Val EQU 0x00000700 -BANKCON5_Val EQU 0x00000700 -BANKCON6_Val EQU 0x00018008 -BANKCON7_Val EQU 0x00018008 -BWSCON_Val EQU 0x00000000 -REFRESH_Val EQU 0x00AC0000 -BANKSIZE_Val EQU 0x00000000 -MRSRB6_Val EQU 0x00000000 -MRSRB7_Val EQU 0x00000000 - -;// End of MC - - -; I/O Ports definitions -PIO_BASE EQU 0x01D20000 ; PIO Base Address -PCONA_OFS EQU 0x00 ; PCONA Offset -PCONB_OFS EQU 0x08 ; PCONB Offset -PCONC_OFS EQU 0x10 ; PCONC Offset -PCOND_OFS EQU 0x1C ; PCOND Offset -PCONE_OFS EQU 0x28 ; PCONE Offset -PCONF_OFS EQU 0x34 ; PCONF Offset -PCONG_OFS EQU 0x40 ; PCONG Offset -PUPC_OFS EQU 0x18 ; PUPC Offset -PUPD_OFS EQU 0x24 ; PUPD Offset -PUPE_OFS EQU 0x30 ; PUPE Offset -PUPF_OFS EQU 0x3C ; PUPF Offset -PUPG_OFS EQU 0x48 ; PUPG Offset -SPUCR_OFS EQU 0x4C ; SPUCR Offset - -;// I/O Configuration -PIO_SETUP EQU 0 - -;// Port A -;// PA0 <0=> Output <1=> ADDR0 -;// PA1 <0=> Output <1=> ADDR16 -;// PA2 <0=> Output <1=> ADDR17 -;// PA3 <0=> Output <1=> ADDR18 -;// PA4 <0=> Output <1=> ADDR19 -;// PA5 <0=> Output <1=> ADDR20 -;// PA6 <0=> Output <1=> ADDR21 -;// PA7 <0=> Output <1=> ADDR22 -;// PA8 <0=> Output <1=> ADDR23 -;// PA9 <0=> Output <1=> ADDR24 -;// -PIOA_SETUP EQU 1 -PCONA_Val EQU 0x000003FF - -;// Port B -;// PB0 <0=> Output <1=> SCKE -;// PB1 <0=> Output <1=> CKLK -;// PB2 <0=> Output <1=> nSCAS/nCAS2 -;// PB3 <0=> Output <1=> nSRAS/nCAS3 -;// PB4 <0=> Output <1=> nWBE2/nBE2/DQM2 -;// PB5 <0=> Output <1=> nWBE3/nBE3/DQM3 -;// PB6 <0=> Output <1=> nGCS1 -;// PB7 <0=> Output <1=> nGCS2 -;// PB8 <0=> Output <1=> nGCS3 -;// PB9 <0=> Output <1=> nGCS4 -;// PB10 <0=> Output <1=> nGCS5 -;// -PIOB_SETUP EQU 1 -PCONB_Val EQU 0x000007FF - -;// Port C -;// PC0 <0=> Input <1=> Output <2=> DATA16 <3=> IISLRCK -;// PC1 <0=> Input <1=> Output <2=> DATA17 <3=> IISDO -;// PC2 <0=> Input <1=> Output <2=> DATA18 <3=> IISDI -;// PC3 <0=> Input <1=> Output <2=> DATA19 <3=> IISCLK -;// PC4 <0=> Input <1=> Output <2=> DATA20 <3=> VD7 -;// PC5 <0=> Input <1=> Output <2=> DATA21 <3=> VD6 -;// PC6 <0=> Input <1=> Output <2=> DATA22 <3=> VD5 -;// PC7 <0=> Input <1=> Output <2=> DATA23 <3=> VD4 -;// PC8 <0=> Input <1=> Output <2=> DATA24 <3=> nXDACK1 -;// PC9 <0=> Input <1=> Output <2=> DATA25 <3=> nXDREQ1 -;// PC10 <0=> Input <1=> Output <2=> DATA26 <3=> nRTS1 -;// PC11 <0=> Input <1=> Output <2=> DATA27 <3=> nCTS1 -;// PC12 <0=> Input <1=> Output <2=> DATA28 <3=> TxD1 -;// PC13 <0=> Input <1=> Output <2=> DATA29 <3=> RxD1 -;// PC14 <0=> Input <1=> Output <2=> DATA30 <3=> nRTS0 -;// PC15 <0=> Input <1=> Output <2=> DATA31 <3=> nCTS0 -;// Pull-up Resistors -;// PC0 Pull-up <0=> Enabled <1=> Disabled -;// PC1 Pull-up <0=> Enabled <1=> Disabled -;// PC2 Pull-up <0=> Enabled <1=> Disabled -;// PC3 Pull-up <0=> Enabled <1=> Disabled -;// PC4 Pull-up <0=> Enabled <1=> Disabled -;// PC5 Pull-up <0=> Enabled <1=> Disabled -;// PC6 Pull-up <0=> Enabled <1=> Disabled -;// PC7 Pull-up <0=> Enabled <1=> Disabled -;// PC8 Pull-up <0=> Enabled <1=> Disabled -;// PC9 Pull-up <0=> Enabled <1=> Disabled -;// PC10 Pull-up <0=> Enabled <1=> Disabled -;// PC11 Pull-up <0=> Enabled <1=> Disabled -;// PC12 Pull-up <0=> Enabled <1=> Disabled -;// PC13 Pull-up <0=> Enabled <1=> Disabled -;// PC14 Pull-up <0=> Enabled <1=> Disabled -;// PC15 Pull-up <0=> Enabled <1=> Disabled -;// -;// -PIOC_SETUP EQU 1 -PCONC_Val EQU 0xAAAAAAAA -PUPC_Val EQU 0x00000000 - -;// Port D -;// PD0 <0=> Input <1=> Output <2=> VD0 <3=> Reserved -;// PD1 <0=> Input <1=> Output <2=> VD1 <3=> Reserved -;// PD2 <0=> Input <1=> Output <2=> VD2 <3=> Reserved -;// PD3 <0=> Input <1=> Output <2=> VD3 <3=> Reserved -;// PD4 <0=> Input <1=> Output <2=> VCLK <3=> Reserved -;// PD5 <0=> Input <1=> Output <2=> VLINE <3=> Reserved -;// PD6 <0=> Input <1=> Output <2=> VM <3=> Reserved -;// PD7 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved -;// Pull-up Resistors -;// PD0 Pull-up <0=> Enabled <1=> Disabled -;// PD1 Pull-up <0=> Enabled <1=> Disabled -;// PD2 Pull-up <0=> Enabled <1=> Disabled -;// PD3 Pull-up <0=> Enabled <1=> Disabled -;// PD4 Pull-up <0=> Enabled <1=> Disabled -;// PD5 Pull-up <0=> Enabled <1=> Disabled -;// PD6 Pull-up <0=> Enabled <1=> Disabled -;// PD7 Pull-up <0=> Enabled <1=> Disabled -;// -;// -PIOD_SETUP EQU 1 -PCOND_Val EQU 0x00000000 -PUPD_Val EQU 0x00000000 - -;// Port E -;// PE0 <0=> Input <1=> Output <2=> Fpllo <3=> Fout -;// PE1 <0=> Input <1=> Output <2=> TxD0 <3=> Reserved -;// PE2 <0=> Input <1=> Output <2=> RxD0 <3=> Reserved -;// PE3 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved -;// PE4 <0=> Input <1=> Output <2=> TOUT1 <3=> TCLK -;// PE5 <0=> Input <1=> Output <2=> TOUT2 <3=> TCLK -;// PE6 <0=> Input <1=> Output <2=> TOUT3 <3=> VD6 -;// PE7 <0=> Input <1=> Output <2=> TOUT4 <3=> VD7 -;// PE8 <0=> Input <1=> Output <2=> CODECLK <3=> Reserved -;// Pull-up Resistors -;// PE0 Pull-up <0=> Enabled <1=> Disabled -;// PE1 Pull-up <0=> Enabled <1=> Disabled -;// PE2 Pull-up <0=> Enabled <1=> Disabled -;// PE3 Pull-up <0=> Enabled <1=> Disabled -;// PE4 Pull-up <0=> Enabled <1=> Disabled -;// PE5 Pull-up <0=> Enabled <1=> Disabled -;// PE6 Pull-up <0=> Enabled <1=> Disabled -;// PE7 Pull-up <0=> Enabled <1=> Disabled -;// PE8 Pull-up <0=> Enabled <1=> Disabled -;// -;// -PIOE_SETUP EQU 1 -PCONE_Val EQU 0x00000000 -PUPE_Val EQU 0x00000000 - -;// Port F -;// PF0 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved -;// PF1 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved -;// PF2 <0=> Input <1=> Output <2=> nWAIT <3=> Reserved -;// PF3 <0=> Input <1=> Output <2=> nXBACK <3=> nXDACK0 -;// PF4 <0=> Input <1=> Output <2=> nXBREQ <3=> nXDREQ0 -;// PF5 <0=> Input <1=> Output <2=> nRTS1 <3=> SIOTxD -;// <4=> IISLRCK <5=> Reserved <6=> Reserved <7=> Reserved -;// PF6 <0=> Input <1=> Output <2=> TxD1 <3=> SIORDY -;// <4=> IISDO <5=> Reserved <6=> Reserved <7=> Reserved -;// PF7 <0=> Input <1=> Output <2=> RxD1 <3=> SIORxD -;// <4=> IISDI <5=> Reserved <6=> Reserved <7=> Reserved -;// PF8 <0=> Input <1=> Output <2=> nCTS1 <3=> SIOCLK -;// <4=> IISCLK <5=> Reserved <6=> Reserved <7=> Reserved -;// Pull-up Resistors -;// PF0 Pull-up <0=> Enabled <1=> Disabled -;// PF1 Pull-up <0=> Enabled <1=> Disabled -;// PF2 Pull-up <0=> Enabled <1=> Disabled -;// PF3 Pull-up <0=> Enabled <1=> Disabled -;// PF4 Pull-up <0=> Enabled <1=> Disabled -;// PF5 Pull-up <0=> Enabled <1=> Disabled -;// PF6 Pull-up <0=> Enabled <1=> Disabled -;// PF7 Pull-up <0=> Enabled <1=> Disabled -;// PF8 Pull-up <0=> Enabled <1=> Disabled -;// -;// -PIOF_SETUP EQU 1 -PCONF_Val EQU 0x00000000 -PUPF_Val EQU 0x00000000 - -;// Port G -;// PG0 <0=> Input <1=> Output <2=> VD4 <3=> EINT0 -;// PG1 <0=> Input <1=> Output <2=> VD5 <3=> EINT1 -;// PG2 <0=> Input <1=> Output <2=> nCTS0 <3=> EINT2 -;// PG3 <0=> Input <1=> Output <2=> nRTS0 <3=> EINT3 -;// PG4 <0=> Input <1=> Output <2=> IISCLK <3=> EINT4 -;// PG5 <0=> Input <1=> Output <2=> IISDI <3=> EINT5 -;// PG6 <0=> Input <1=> Output <2=> IISDO <3=> EINT6 -;// PG7 <0=> Input <1=> Output <2=> IISLRCK <3=> EINT7 -;// Pull-up Resistors -;// PG0 Pull-up <0=> Enabled <1=> Disabled -;// PG1 Pull-up <0=> Enabled <1=> Disabled -;// PG2 Pull-up <0=> Enabled <1=> Disabled -;// PG3 Pull-up <0=> Enabled <1=> Disabled -;// PG4 Pull-up <0=> Enabled <1=> Disabled -;// PG5 Pull-up <0=> Enabled <1=> Disabled -;// PG6 Pull-up <0=> Enabled <1=> Disabled -;// PG7 Pull-up <0=> Enabled <1=> Disabled -;// -;// -PIOG_SETUP EQU 1 -PCONG_Val EQU 0x00000000 -PUPG_Val EQU 0x00000000 - -;// Special Pull-up -;// SPUCR0: DATA[7:0] Pull-up Resistor -;// <0=> Enabled <1=> Disabled -;// SPUCR1: DATA[15:8] Pull-up Resistor -;// <0=> Enabled <1=> Disabled -;// HZ@STOP -;// <0=> Prevoius state of PAD -;// <1=> HZ @ Stop -;// -PSPU_SETUP EQU 1 -SPUCR_Val EQU 0x00000004 - -;// - - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC, Reset_Addr - LDR PC, Undef_Addr - LDR PC, SWI_Addr - LDR PC, PAbt_Addr - LDR PC, DAbt_Addr - NOP ; Reserved Vector - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B PAbt_Handler -DAbt_Handler B DAbt_Handler -FIQ_Handler B FIQ_Handler - - -; CPU Wrapper and Bus Priorities Configuration - IF SYS_SETUP <> 0 -SYS_CFG - DCD CPUW_BASE - DCD BUSP_BASE - DCD SYSCFG_Val - DCD NCACHBE0_Val - DCD NCACHBE1_Val - DCD SBUSCON_Val - ENDIF - - -; Memory Controller Configuration - IF MC_SETUP <> 0 -MC_CFG - DCD BWSCON_Val - DCD BANKCON0_Val - DCD BANKCON1_Val - DCD BANKCON2_Val - DCD BANKCON3_Val - DCD BANKCON4_Val - DCD BANKCON5_Val - DCD BANKCON6_Val - DCD BANKCON7_Val - DCD REFRESH_Val - DCD BANKSIZE_Val - DCD MRSRB6_Val - DCD MRSRB7_Val - ENDIF - - -; Clock Management Configuration - IF CLK_SETUP <> 0 -CLK_CFG - DCD CLK_BASE - DCD PLLCON_Val - DCD CLKCON_Val - DCD CLKSLOW_Val - DCD LOCKTIME_Val - ENDIF - - -; I/O Configuration - IF PIO_SETUP <> 0 -PIO_CFG - DCD PCONA_Val - DCD PCONB_Val - DCD PCONC_Val - DCD PCOND_Val - DCD PCONE_Val - DCD PCONF_Val - DCD PCONG_Val - DCD PUPC_Val - DCD PUPD_Val - DCD PUPE_Val - DCD PUPF_Val - DCD PUPG_Val - DCD SPUCR_Val - ENDIF - - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - - IF SYS_SETUP <> 0 - ADR R8, SYS_CFG - LDMIA R8, {R0-R5} - STMIA R0, {R2-R4} - STR R5, [R1] - ENDIF - - - IF MC_SETUP <> 0 - ADR R14, MC_CFG - LDMIA R14, {R0-R12} - LDR R14, =MC_BASE - STMIA R14, {R0-R12} - ENDIF - - - IF CLK_SETUP <> 0 - ADR R8, CLK_CFG - LDMIA R8, {R0-R4} - STR R4, [R0, #LOCKTIME_OFS] - STR R1, [R0, #PLLCON_OFS] - STR R3, [R0, #CLKSLOW_OFS] - STR R2, [R0, #CLKCON_OFS] - ENDIF - - - IF WT_SETUP <> 0 - LDR R0, =WT_BASE - LDR R1, =WTCON_Val - LDR R2, =WTDAT_Val - STR R2, [R0, #WTCNT_OFS] - STR R2, [R0, #WTDAT_OFS] - STR R1, [R0, #WTCON_OFS] - ENDIF - - - IF PIO_SETUP <> 0 - ADR R14, PIO_CFG - LDMIA R14, {R0-R12} - LDR R14, =PIO_BASE - - IF PIOA_SETUP <> 0 - STR R0, [R14, #PCONA_OFS] - ENDIF - - IF PIOB_SETUP <> 0 - STR R1, [R14, #PCONB_OFS] - ENDIF - - IF PIOC_SETUP <> 0 - STR R2, [R14, #PCONC_OFS] - STR R7, [R14, #PUPC_OFS] - ENDIF - - IF PIOD_SETUP <> 0 - STR R3, [R14, #PCOND_OFS] - STR R8, [R14, #PUPD_OFS] - ENDIF - - IF PIOE_SETUP <> 0 - STR R4, [R14, #PCONE_OFS] - STR R9, [R14, #PUPE_OFS] - ENDIF - - IF PIOF_SETUP <> 0 - STR R5, [R14, #PCONF_OFS] - STR R10,[R14, #PUPF_OFS] - ENDIF - - IF PIOG_SETUP <> 0 - STR R6, [R14, #PCONG_OFS] - STR R11,[R14, #PUPG_OFS] - ENDIF - - IF PSPU_SETUP <> 0 - STR R12,[R14, #SPUCR_OFS] - ENDIF - - ENDIF - - -; Setup Stack for each mode - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; MSR CPSR_c, #Mode_USR - IF :DEF:__MICROLIB - - EXPORT __initial_sp - - ELSE - - ; MOV SP, R0 - ; SUB SL, SP, #USR_Stack_Size - - ENDIF - - -; Enter the C code - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - - END +;/*****************************************************************************/ +;/* S3C44B0X.S: Startup file for Samsung S3C44B0X */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +; *** Startup Code (executed after Reset) *** + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +;// Stack Configuration (Stack Sizes in Bytes) +;// Undefined Mode <0x0-0xFFFFFFFF:8> +;// Supervisor Mode <0x0-0xFFFFFFFF:8> +;// Abort Mode <0x0-0xFFFFFFFF:8> +;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// Interrupt Mode <0x0-0xFFFFFFFF:8> +;// User/System Mode <0x0-0xFFFFFFFF:8> +;// + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size +Stack_Top + + +;// Heap Configuration +;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +; CPU Wrapper and Bus Priorities definitions +CPUW_BASE EQU 0x01C00000 ; CPU Wrapper Base Address +SYSCFG_OFS EQU 0x00 ; SYSCFG Offset +NCACHBE0_OFS EQU 0x04 ; NCACHBE0 Offset +NCACHBE1_OFS EQU 0x08 ; NCACHBE0 Offset +BUSP_BASE EQU 0x01C40000 ; Bus Priority Base Address +SBUSCON_OFS EQU 0x00 ; SBUSCON Offset + +;// CPU Wrapper and Bus Priorities +;// CPU Wrapper +;// SE: Stall Enable +;// CM: Cache Mode +;// <0=> Disable Cache (8kB SRAM) +;// <1=> Half Cache Enable (4kB Cache, 4kB SRAM) +;// <2=> Reserved +;// <3=> Full Cache Enable (8kB Cache) +;// WE: Write Buffer Enable +;// RSE: Read Stall Enable +;// DA: Data Abort <0=> Enable <1=> Disable +;// Non-cacheable Area 0 +;// Start Address <0x0-0x0FFFF000:0x1000><#/0x1000> +;// SA = (Start Address) / 4k +;// End Address + 1 <0x0-0x10000000:0x1000><#/0x1000> +;// SE = (End Address + 1) / 4k +;// +;// Non-cacheable Area 1 +;// Start Address <0x0-0x0FFFF000:0x1000><#/0x1000> +;// SA = (Start Address) / 4k +;// End Address + 1 <0x0-0x10000000:0x1000><#/0x1000> +;// SE = (End Address + 1) / 4k +;// +;// +;// Bus Priorities +;// FIX: Fixed Priorities +;// LCD_DMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th +;// ZDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th +;// BDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th +;// nBREQ <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th +;// +;// +SYS_SETUP EQU 0 +SYSCFG_Val EQU 0x00000001 +NCACHBE0_Val EQU 0x00000000 +NCACHBE1_Val EQU 0x00000000 +SBUSCON_Val EQU 0x80001B1B + + +;// Vectored Interrupt Mode (for IRQ) +;// EINT0 External Interrupt 0 +;// EINT1 External Interrupt 1 +;// EINT2 External Interrupt 2 +;// EINT3 External Interrupt 3 +;// EINT4567 External Interrupt 4/5/6/7 +;// TICK RTC Time Tick Interrupt +;// ZDMA0 General DMA0 Interrupt +;// ZDMA1 General DMA1 Interrupt +;// BDMA0 Bridge DMA0 Interrupt +;// BDMA1 Bridge DMA1 Interrupt +;// WDT Watchdog Timer Interrupt +;// UERR01 UART0/1 Error Interrupt +;// TIMER0 Timer0 Interrupt +;// TIMER1 Timer1 Interrupt +;// TIMER2 Timer2 Interrupt +;// TIMER3 Timer3 Interrupt +;// TIMER4 Timer4 Interrupt +;// TIMER5 Timer5 Interrupt +;// URXD0 UART0 Rx Interrupt +;// URXD1 UART1 Rx Interrupt +;// IIC IIC Interrupt +;// SIO SIO Interrupt +;// UTXD0 UART0 Tx Interrupt +;// UTXD1 UART1 Tx Interrupt +;// RTC RTC Alarm Interrupt +;// ADC ADC EOC Interrupt +;// +VIM_SETUP EQU 0 +VIM_CFG EQU 0x00000000 + + +; Clock Management definitions +CLK_BASE EQU 0x01D80000 ; Clock Base Address +PLLCON_OFS EQU 0x00 ; PLLCON Offset +CLKCON_OFS EQU 0x04 ; CLKCON Offset +CLKSLOW_OFS EQU 0x08 ; CLKSLOW Offset +LOCKTIME_OFS EQU 0x0C ; LOCKTIME Offset + +;// Clock Management +;// PLL Settings +;// Fpllo = (m * Fin) / (p * 2^s), 20MHz < Fpllo < 66MHz +;// MDIV: Main divider <0x0-0xFF> +;// m = MDIV + 8 +;// PDIV: Pre-divider <0x0-0x3F> +;// p = PDIV + 2, 1MHz <= Fin/p < 2MHz +;// SDIV: Post Divider <0x0-0x03> +;// s = SDIV, Fpllo * 2^s < 170MHz +;// LTIME CNT: PLL Lock Time Count <0x0-0x0FFF> +;// +;// Master Clock +;// PLL Clock: Fout = Fpllo +;// Slow Clock: Fout = Fin / (2 * SLOW_VAL), SLOW_VAL > 0 +;// Slow Clock: Fout = Fin, SLOW_VAL = 0 +;// PLL_OFF: PLL Off +;// PLL is turned Off only when SLOW_BIT = 1 +;// SLOW_BIT: Slow Clock +;// SLOW_VAL: Slow Clock divider <0x0-0x0F> +;// +;// Clock Generation +;// IIS <0=> Disable <1=> Enable +;// IIC <0=> Disable <1=> Enable +;// ADC <0=> Disable <1=> Enable +;// RTC <0=> Disable <1=> Enable +;// GPIO <0=> Disable <1=> Enable +;// UART1 <0=> Disable <1=> Enable +;// UART0 <0=> Disable <1=> Enable +;// BDMA0,1 <0=> Disable <1=> Enable +;// LCDC <0=> Disable <1=> Enable +;// SIO <0=> Disable <1=> Enable +;// ZDMA0,1 <0=> Disable <1=> Enable +;// PWMTIMER <0=> Disable <1=> Enable +;// +;// +CLK_SETUP EQU 1 +PLLCON_Val EQU 0x00038080 +CLKCON_Val EQU 0x00007FF8 +CLKSLOW_Val EQU 0x00000009 +LOCKTIME_Val EQU 0x00000FFF + + +; Watchdog Timer definitions +WT_BASE EQU 0x01D30000 ; WT Base Address +WTCON_OFS EQU 0x00 ; WTCON Offset +WTDAT_OFS EQU 0x04 ; WTDAT Offset +WTCNT_OFS EQU 0x08 ; WTCNT Offset + +;// Watchdog Timer +;// Watchdog Timer Enable/Disable +;// Reset Enable/Disable +;// Interrupt Enable/Disable +;// Clock Select +;// <0=> 1/16 <1=> 1/32 <2=> 1/64 <3=> 1/128 +;// Clock Division Factor +;// Prescaler Value <0x0-0xFF> +;// Time-out Value <0x0-0xFFFF> +;// +WT_SETUP EQU 1 +WTCON_Val EQU 0x00008000 +WTDAT_Val EQU 0x00008000 + + +; Memory Controller definitions +MC_BASE EQU 0x01C80000 ; Memory Controller Base Address + +;// Memory Controller +MC_SETUP EQU 1 + +;// Bank 0 +;// PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// +;// +;// Bank 1 +;// DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// +;// +;// Bank 2 +;// DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// +;// +;// Bank 3 +;// DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// +;// +;// Bank 4 +;// DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// +;// +;// Bank 5 +;// DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// +;// +;// Bank 6 +;// BK76MAP: Bank 6/7 Memory Map +;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M +;// DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// MT: Memory Type +;// <0=> ROM or SRAM +;// <1=> FP DRAMP +;// <2=> EDO DRAM +;// <3=> SDRAM +;// ROM or SRAM +;// PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// +;// FP DRAM or EDO DRAM +;// CAN: Columnn Address Number +;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit +;// Tcp: CAS Pre-charge +;// <0=> 1 clk <1=> 2 clks +;// Tcas: CAS Pulse Width +;// <0=> 1 clk <1=> 2 clks +;// Trcd: RAS to CAS Delay +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// +;// SDRAM +;// SCAN: Columnn Address Number +;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd +;// Trcd: RAS to CAS Delay +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd +;// SCLKEN: SCLK Selection (Bank 6/7) +;// <0=> Normal +;// <1=> Reduced Power +;// BL: Burst Length +;// <0=> 1 +;// BT: Burst Type +;// <0=> Sequential +;// CL: CAS Latency +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks +;// TM: Test Mode +;// <0=> Mode Register Set +;// WBL: Write Burst Length +;// <0=> 0 +;// +;// +;// +;// Bank 7 +;// BK76MAP: Bank 6/7 Memory Map +;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M +;// DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// MT: Memory Type +;// <0=> ROM or SRAM +;// <1=> FP DRAMP +;// <2=> EDO DRAM +;// <3=> SDRAM +;// ROM or SRAM +;// PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// +;// FP DRAM or EDO DRAM +;// CAN: Columnn Address Number +;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit +;// Tcp: CAS Pre-charge +;// <0=> 1 clk <1=> 2 clks +;// Tcas: CAS Pulse Width +;// <0=> 1 clk <1=> 2 clks +;// Trcd: RAS to CAS Delay +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// +;// SDRAM +;// SCAN: Columnn Address Number +;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd +;// Trcd: RAS to CAS Delay +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd +;// SCLKEN: SCLK Selection (Bank 6/7) +;// <0=> Normal +;// <1=> Reduced Power +;// BL: Burst Length +;// <0=> 1 +;// BT: Burst Type +;// <0=> Sequential +;// CL: CAS Latency +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks +;// TM: Test Mode +;// <0=> Mode Register Set +;// WBL: Write Burst Length +;// <0=> 0 +;// +;// +;// +;// Refresh +;// REFEN: DRAM/SDRAM Refresh +;// <0=> Disable <1=> Enable +;// TREFMD: DRAM/SDRAM Refresh Mode +;// <0=> CBR/Auto Refresh +;// <1=> Self Refresh +;// Trp: DRAM/SDRAM RAS Pre-charge Time +;// <0=> 1.5 clks (DRAM) / 2 clks (SDRAM) +;// <1=> 2.5 clks (DRAM) / 3 clks (SDRAM) +;// <2=> 3.5 clks (DRAM) / 4 clks (SDRAM) +;// <3=> 4.5 clks (DRAM) / Rsrvd (SDRAM) +;// Trc: SDRAM RC Min Time +;// <0=> 4 clks <1=> 5 clks <2=> 6 clks <3=> 7 clks +;// Tchr: DRAM CAS Hold Time +;// <0=> 1 clks <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// Refresh Counter <0x0-0x07FF> +;// Refresh Period = (2^11 - Refresh Count + 1) / MCLK +;// +BANKCON0_Val EQU 0x00000700 +BANKCON1_Val EQU 0x00000700 +BANKCON2_Val EQU 0x00000700 +BANKCON3_Val EQU 0x00000700 +BANKCON4_Val EQU 0x00000700 +BANKCON5_Val EQU 0x00000700 +BANKCON6_Val EQU 0x00018008 +BANKCON7_Val EQU 0x00018008 +BWSCON_Val EQU 0x00000000 +REFRESH_Val EQU 0x00AC0000 +BANKSIZE_Val EQU 0x00000000 +MRSRB6_Val EQU 0x00000000 +MRSRB7_Val EQU 0x00000000 + +;// End of MC + + +; I/O Ports definitions +PIO_BASE EQU 0x01D20000 ; PIO Base Address +PCONA_OFS EQU 0x00 ; PCONA Offset +PCONB_OFS EQU 0x08 ; PCONB Offset +PCONC_OFS EQU 0x10 ; PCONC Offset +PCOND_OFS EQU 0x1C ; PCOND Offset +PCONE_OFS EQU 0x28 ; PCONE Offset +PCONF_OFS EQU 0x34 ; PCONF Offset +PCONG_OFS EQU 0x40 ; PCONG Offset +PUPC_OFS EQU 0x18 ; PUPC Offset +PUPD_OFS EQU 0x24 ; PUPD Offset +PUPE_OFS EQU 0x30 ; PUPE Offset +PUPF_OFS EQU 0x3C ; PUPF Offset +PUPG_OFS EQU 0x48 ; PUPG Offset +SPUCR_OFS EQU 0x4C ; SPUCR Offset + +;// I/O Configuration +PIO_SETUP EQU 0 + +;// Port A +;// PA0 <0=> Output <1=> ADDR0 +;// PA1 <0=> Output <1=> ADDR16 +;// PA2 <0=> Output <1=> ADDR17 +;// PA3 <0=> Output <1=> ADDR18 +;// PA4 <0=> Output <1=> ADDR19 +;// PA5 <0=> Output <1=> ADDR20 +;// PA6 <0=> Output <1=> ADDR21 +;// PA7 <0=> Output <1=> ADDR22 +;// PA8 <0=> Output <1=> ADDR23 +;// PA9 <0=> Output <1=> ADDR24 +;// +PIOA_SETUP EQU 1 +PCONA_Val EQU 0x000003FF + +;// Port B +;// PB0 <0=> Output <1=> SCKE +;// PB1 <0=> Output <1=> CKLK +;// PB2 <0=> Output <1=> nSCAS/nCAS2 +;// PB3 <0=> Output <1=> nSRAS/nCAS3 +;// PB4 <0=> Output <1=> nWBE2/nBE2/DQM2 +;// PB5 <0=> Output <1=> nWBE3/nBE3/DQM3 +;// PB6 <0=> Output <1=> nGCS1 +;// PB7 <0=> Output <1=> nGCS2 +;// PB8 <0=> Output <1=> nGCS3 +;// PB9 <0=> Output <1=> nGCS4 +;// PB10 <0=> Output <1=> nGCS5 +;// +PIOB_SETUP EQU 1 +PCONB_Val EQU 0x000007FF + +;// Port C +;// PC0 <0=> Input <1=> Output <2=> DATA16 <3=> IISLRCK +;// PC1 <0=> Input <1=> Output <2=> DATA17 <3=> IISDO +;// PC2 <0=> Input <1=> Output <2=> DATA18 <3=> IISDI +;// PC3 <0=> Input <1=> Output <2=> DATA19 <3=> IISCLK +;// PC4 <0=> Input <1=> Output <2=> DATA20 <3=> VD7 +;// PC5 <0=> Input <1=> Output <2=> DATA21 <3=> VD6 +;// PC6 <0=> Input <1=> Output <2=> DATA22 <3=> VD5 +;// PC7 <0=> Input <1=> Output <2=> DATA23 <3=> VD4 +;// PC8 <0=> Input <1=> Output <2=> DATA24 <3=> nXDACK1 +;// PC9 <0=> Input <1=> Output <2=> DATA25 <3=> nXDREQ1 +;// PC10 <0=> Input <1=> Output <2=> DATA26 <3=> nRTS1 +;// PC11 <0=> Input <1=> Output <2=> DATA27 <3=> nCTS1 +;// PC12 <0=> Input <1=> Output <2=> DATA28 <3=> TxD1 +;// PC13 <0=> Input <1=> Output <2=> DATA29 <3=> RxD1 +;// PC14 <0=> Input <1=> Output <2=> DATA30 <3=> nRTS0 +;// PC15 <0=> Input <1=> Output <2=> DATA31 <3=> nCTS0 +;// Pull-up Resistors +;// PC0 Pull-up <0=> Enabled <1=> Disabled +;// PC1 Pull-up <0=> Enabled <1=> Disabled +;// PC2 Pull-up <0=> Enabled <1=> Disabled +;// PC3 Pull-up <0=> Enabled <1=> Disabled +;// PC4 Pull-up <0=> Enabled <1=> Disabled +;// PC5 Pull-up <0=> Enabled <1=> Disabled +;// PC6 Pull-up <0=> Enabled <1=> Disabled +;// PC7 Pull-up <0=> Enabled <1=> Disabled +;// PC8 Pull-up <0=> Enabled <1=> Disabled +;// PC9 Pull-up <0=> Enabled <1=> Disabled +;// PC10 Pull-up <0=> Enabled <1=> Disabled +;// PC11 Pull-up <0=> Enabled <1=> Disabled +;// PC12 Pull-up <0=> Enabled <1=> Disabled +;// PC13 Pull-up <0=> Enabled <1=> Disabled +;// PC14 Pull-up <0=> Enabled <1=> Disabled +;// PC15 Pull-up <0=> Enabled <1=> Disabled +;// +;// +PIOC_SETUP EQU 1 +PCONC_Val EQU 0xAAAAAAAA +PUPC_Val EQU 0x00000000 + +;// Port D +;// PD0 <0=> Input <1=> Output <2=> VD0 <3=> Reserved +;// PD1 <0=> Input <1=> Output <2=> VD1 <3=> Reserved +;// PD2 <0=> Input <1=> Output <2=> VD2 <3=> Reserved +;// PD3 <0=> Input <1=> Output <2=> VD3 <3=> Reserved +;// PD4 <0=> Input <1=> Output <2=> VCLK <3=> Reserved +;// PD5 <0=> Input <1=> Output <2=> VLINE <3=> Reserved +;// PD6 <0=> Input <1=> Output <2=> VM <3=> Reserved +;// PD7 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved +;// Pull-up Resistors +;// PD0 Pull-up <0=> Enabled <1=> Disabled +;// PD1 Pull-up <0=> Enabled <1=> Disabled +;// PD2 Pull-up <0=> Enabled <1=> Disabled +;// PD3 Pull-up <0=> Enabled <1=> Disabled +;// PD4 Pull-up <0=> Enabled <1=> Disabled +;// PD5 Pull-up <0=> Enabled <1=> Disabled +;// PD6 Pull-up <0=> Enabled <1=> Disabled +;// PD7 Pull-up <0=> Enabled <1=> Disabled +;// +;// +PIOD_SETUP EQU 1 +PCOND_Val EQU 0x00000000 +PUPD_Val EQU 0x00000000 + +;// Port E +;// PE0 <0=> Input <1=> Output <2=> Fpllo <3=> Fout +;// PE1 <0=> Input <1=> Output <2=> TxD0 <3=> Reserved +;// PE2 <0=> Input <1=> Output <2=> RxD0 <3=> Reserved +;// PE3 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved +;// PE4 <0=> Input <1=> Output <2=> TOUT1 <3=> TCLK +;// PE5 <0=> Input <1=> Output <2=> TOUT2 <3=> TCLK +;// PE6 <0=> Input <1=> Output <2=> TOUT3 <3=> VD6 +;// PE7 <0=> Input <1=> Output <2=> TOUT4 <3=> VD7 +;// PE8 <0=> Input <1=> Output <2=> CODECLK <3=> Reserved +;// Pull-up Resistors +;// PE0 Pull-up <0=> Enabled <1=> Disabled +;// PE1 Pull-up <0=> Enabled <1=> Disabled +;// PE2 Pull-up <0=> Enabled <1=> Disabled +;// PE3 Pull-up <0=> Enabled <1=> Disabled +;// PE4 Pull-up <0=> Enabled <1=> Disabled +;// PE5 Pull-up <0=> Enabled <1=> Disabled +;// PE6 Pull-up <0=> Enabled <1=> Disabled +;// PE7 Pull-up <0=> Enabled <1=> Disabled +;// PE8 Pull-up <0=> Enabled <1=> Disabled +;// +;// +PIOE_SETUP EQU 1 +PCONE_Val EQU 0x00000000 +PUPE_Val EQU 0x00000000 + +;// Port F +;// PF0 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved +;// PF1 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved +;// PF2 <0=> Input <1=> Output <2=> nWAIT <3=> Reserved +;// PF3 <0=> Input <1=> Output <2=> nXBACK <3=> nXDACK0 +;// PF4 <0=> Input <1=> Output <2=> nXBREQ <3=> nXDREQ0 +;// PF5 <0=> Input <1=> Output <2=> nRTS1 <3=> SIOTxD +;// <4=> IISLRCK <5=> Reserved <6=> Reserved <7=> Reserved +;// PF6 <0=> Input <1=> Output <2=> TxD1 <3=> SIORDY +;// <4=> IISDO <5=> Reserved <6=> Reserved <7=> Reserved +;// PF7 <0=> Input <1=> Output <2=> RxD1 <3=> SIORxD +;// <4=> IISDI <5=> Reserved <6=> Reserved <7=> Reserved +;// PF8 <0=> Input <1=> Output <2=> nCTS1 <3=> SIOCLK +;// <4=> IISCLK <5=> Reserved <6=> Reserved <7=> Reserved +;// Pull-up Resistors +;// PF0 Pull-up <0=> Enabled <1=> Disabled +;// PF1 Pull-up <0=> Enabled <1=> Disabled +;// PF2 Pull-up <0=> Enabled <1=> Disabled +;// PF3 Pull-up <0=> Enabled <1=> Disabled +;// PF4 Pull-up <0=> Enabled <1=> Disabled +;// PF5 Pull-up <0=> Enabled <1=> Disabled +;// PF6 Pull-up <0=> Enabled <1=> Disabled +;// PF7 Pull-up <0=> Enabled <1=> Disabled +;// PF8 Pull-up <0=> Enabled <1=> Disabled +;// +;// +PIOF_SETUP EQU 1 +PCONF_Val EQU 0x00000000 +PUPF_Val EQU 0x00000000 + +;// Port G +;// PG0 <0=> Input <1=> Output <2=> VD4 <3=> EINT0 +;// PG1 <0=> Input <1=> Output <2=> VD5 <3=> EINT1 +;// PG2 <0=> Input <1=> Output <2=> nCTS0 <3=> EINT2 +;// PG3 <0=> Input <1=> Output <2=> nRTS0 <3=> EINT3 +;// PG4 <0=> Input <1=> Output <2=> IISCLK <3=> EINT4 +;// PG5 <0=> Input <1=> Output <2=> IISDI <3=> EINT5 +;// PG6 <0=> Input <1=> Output <2=> IISDO <3=> EINT6 +;// PG7 <0=> Input <1=> Output <2=> IISLRCK <3=> EINT7 +;// Pull-up Resistors +;// PG0 Pull-up <0=> Enabled <1=> Disabled +;// PG1 Pull-up <0=> Enabled <1=> Disabled +;// PG2 Pull-up <0=> Enabled <1=> Disabled +;// PG3 Pull-up <0=> Enabled <1=> Disabled +;// PG4 Pull-up <0=> Enabled <1=> Disabled +;// PG5 Pull-up <0=> Enabled <1=> Disabled +;// PG6 Pull-up <0=> Enabled <1=> Disabled +;// PG7 Pull-up <0=> Enabled <1=> Disabled +;// +;// +PIOG_SETUP EQU 1 +PCONG_Val EQU 0x00000000 +PUPG_Val EQU 0x00000000 + +;// Special Pull-up +;// SPUCR0: DATA[7:0] Pull-up Resistor +;// <0=> Enabled <1=> Disabled +;// SPUCR1: DATA[15:8] Pull-up Resistor +;// <0=> Enabled <1=> Disabled +;// HZ@STOP +;// <0=> Prevoius state of PAD +;// <1=> HZ @ Stop +;// +PSPU_SETUP EQU 1 +SPUCR_Val EQU 0x00000004 + +;// + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + +Vectors LDR PC, Reset_Addr + LDR PC, Undef_Addr + LDR PC, SWI_Addr + LDR PC, PAbt_Addr + LDR PC, DAbt_Addr + NOP ; Reserved Vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B PAbt_Handler +DAbt_Handler B DAbt_Handler +FIQ_Handler B FIQ_Handler + + +; CPU Wrapper and Bus Priorities Configuration + IF SYS_SETUP <> 0 +SYS_CFG + DCD CPUW_BASE + DCD BUSP_BASE + DCD SYSCFG_Val + DCD NCACHBE0_Val + DCD NCACHBE1_Val + DCD SBUSCON_Val + ENDIF + + +; Memory Controller Configuration + IF MC_SETUP <> 0 +MC_CFG + DCD BWSCON_Val + DCD BANKCON0_Val + DCD BANKCON1_Val + DCD BANKCON2_Val + DCD BANKCON3_Val + DCD BANKCON4_Val + DCD BANKCON5_Val + DCD BANKCON6_Val + DCD BANKCON7_Val + DCD REFRESH_Val + DCD BANKSIZE_Val + DCD MRSRB6_Val + DCD MRSRB7_Val + ENDIF + + +; Clock Management Configuration + IF CLK_SETUP <> 0 +CLK_CFG + DCD CLK_BASE + DCD PLLCON_Val + DCD CLKCON_Val + DCD CLKSLOW_Val + DCD LOCKTIME_Val + ENDIF + + +; I/O Configuration + IF PIO_SETUP <> 0 +PIO_CFG + DCD PCONA_Val + DCD PCONB_Val + DCD PCONC_Val + DCD PCOND_Val + DCD PCONE_Val + DCD PCONF_Val + DCD PCONG_Val + DCD PUPC_Val + DCD PUPD_Val + DCD PUPE_Val + DCD PUPF_Val + DCD PUPG_Val + DCD SPUCR_Val + ENDIF + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + + IF SYS_SETUP <> 0 + ADR R8, SYS_CFG + LDMIA R8, {R0-R5} + STMIA R0, {R2-R4} + STR R5, [R1] + ENDIF + + + IF MC_SETUP <> 0 + ADR R14, MC_CFG + LDMIA R14, {R0-R12} + LDR R14, =MC_BASE + STMIA R14, {R0-R12} + ENDIF + + + IF CLK_SETUP <> 0 + ADR R8, CLK_CFG + LDMIA R8, {R0-R4} + STR R4, [R0, #LOCKTIME_OFS] + STR R1, [R0, #PLLCON_OFS] + STR R3, [R0, #CLKSLOW_OFS] + STR R2, [R0, #CLKCON_OFS] + ENDIF + + + IF WT_SETUP <> 0 + LDR R0, =WT_BASE + LDR R1, =WTCON_Val + LDR R2, =WTDAT_Val + STR R2, [R0, #WTCNT_OFS] + STR R2, [R0, #WTDAT_OFS] + STR R1, [R0, #WTCON_OFS] + ENDIF + + + IF PIO_SETUP <> 0 + ADR R14, PIO_CFG + LDMIA R14, {R0-R12} + LDR R14, =PIO_BASE + + IF PIOA_SETUP <> 0 + STR R0, [R14, #PCONA_OFS] + ENDIF + + IF PIOB_SETUP <> 0 + STR R1, [R14, #PCONB_OFS] + ENDIF + + IF PIOC_SETUP <> 0 + STR R2, [R14, #PCONC_OFS] + STR R7, [R14, #PUPC_OFS] + ENDIF + + IF PIOD_SETUP <> 0 + STR R3, [R14, #PCOND_OFS] + STR R8, [R14, #PUPD_OFS] + ENDIF + + IF PIOE_SETUP <> 0 + STR R4, [R14, #PCONE_OFS] + STR R9, [R14, #PUPE_OFS] + ENDIF + + IF PIOF_SETUP <> 0 + STR R5, [R14, #PCONF_OFS] + STR R10,[R14, #PUPF_OFS] + ENDIF + + IF PIOG_SETUP <> 0 + STR R6, [R14, #PCONG_OFS] + STR R11,[R14, #PUPG_OFS] + ENDIF + + IF PSPU_SETUP <> 0 + STR R12,[R14, #SPUCR_OFS] + ENDIF + + ENDIF + + +; Setup Stack for each mode + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; MSR CPSR_c, #Mode_USR + IF :DEF:__MICROLIB + + EXPORT __initial_sp + + ELSE + + ; MOV SP, R0 + ; SUB SL, SP, #USR_Stack_Size + + ENDIF + + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + + END diff --git a/libcpu/arm/sep4020/clk.c b/libcpu/arm/sep4020/clk.c index 7ed3bb8043c6017e876f2d95fa3093faa49cff67..9de17b307725f8ac07747f1d1853a7da143dde07 100644 --- a/libcpu/arm/sep4020/clk.c +++ b/libcpu/arm/sep4020/clk.c @@ -1,112 +1,112 @@ -/* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-03-20 zchong first version - */ - -#include -#include "sep4020.h" - -#define CLK_IN 4000000 /* Fin = 4.00MHz */ -#define SYSCLK 72000000 /* system clock we want */ - -#define CLK_ESRAM 0 -#define CLK_LCDC 1 -#define CLK_PWM 2 -#define CLK_DMAC 3 -#define CLK_EMI 4 -#define CLK_MMCSD 5 -#define CLK_SSI 7 -#define CLK_UART0 8 -#define CLK_UART1 9 -#define CLK_UART2 10 -#define CLK_UART3 11 -#define CLK_USB 12 -#define CLK_MAC 13 -#define CLK_SMC 14 -#define CLK_I2C 15 -#define CLK_GPT 16 - -static void rt_hw_set_system_clock(void) -{ - rt_uint8_t pv; - - /* pv value*/ - pv = SYSCLK/2/CLK_IN; - /* go to normal mode*/ - *(RP)PMU_PMDR = 0x01; - /* set the clock */ - *(RP)PMU_PMCR = 0x4000 | pv; - /* trige configurate*/ - *(RP)PMU_PMCR = 0xc000 | pv; -} - -static void rt_hw_set_usb_clock(void) -{ - /* set the clock */ - *(RP)PMU_PUCR = 0x000c; - /* trige configurate*/ - *(RP)PMU_PMCR = 0x800c; - -} - -/** - * @brief System Clock Configuration - */ -void rt_hw_clock_init(void) -{ - /* set system clock */ - rt_hw_set_system_clock(); - /* set usb clock */ - rt_hw_set_usb_clock(); -} - -/** - * @brief Get system clock - */ -rt_uint32_t rt_hw_get_clock(void) -{ - rt_uint32_t val; - rt_uint8_t pv, pd, npd; - - /* get PMCR value */ - val =*(RP) PMU_PMCR; - /* get NPD */ - npd = (val >> 14) & 0x01; - /* get PD */ - pd = (val >> 10) & 0x0f; - /* get PV */ - pv = val & 0x7f; - /* caculate the system clock */ - if(npd) - val = 2 * CLK_IN * pv; - else - val = CLK_IN * pv / (pd + 1); - - return(val); -} - -/** - * @brief Enable module clock - */ - void rt_hw_enable_module_clock(rt_uint8_t module) - { - - } - -/** - * @brief Disable module clock - */ - void rt_hw_disable_module_clock(rt_uint8_t module) - { - - } - +/* + * File : clock.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-20 zchong first version + */ + +#include +#include "sep4020.h" + +#define CLK_IN 4000000 /* Fin = 4.00MHz */ +#define SYSCLK 72000000 /* system clock we want */ + +#define CLK_ESRAM 0 +#define CLK_LCDC 1 +#define CLK_PWM 2 +#define CLK_DMAC 3 +#define CLK_EMI 4 +#define CLK_MMCSD 5 +#define CLK_SSI 7 +#define CLK_UART0 8 +#define CLK_UART1 9 +#define CLK_UART2 10 +#define CLK_UART3 11 +#define CLK_USB 12 +#define CLK_MAC 13 +#define CLK_SMC 14 +#define CLK_I2C 15 +#define CLK_GPT 16 + +static void rt_hw_set_system_clock(void) +{ + rt_uint8_t pv; + + /* pv value*/ + pv = SYSCLK/2/CLK_IN; + /* go to normal mode*/ + *(RP)PMU_PMDR = 0x01; + /* set the clock */ + *(RP)PMU_PMCR = 0x4000 | pv; + /* trige configurate*/ + *(RP)PMU_PMCR = 0xc000 | pv; +} + +static void rt_hw_set_usb_clock(void) +{ + /* set the clock */ + *(RP)PMU_PUCR = 0x000c; + /* trige configurate*/ + *(RP)PMU_PMCR = 0x800c; + +} + +/** + * @brief System Clock Configuration + */ +void rt_hw_clock_init(void) +{ + /* set system clock */ + rt_hw_set_system_clock(); + /* set usb clock */ + rt_hw_set_usb_clock(); +} + +/** + * @brief Get system clock + */ +rt_uint32_t rt_hw_get_clock(void) +{ + rt_uint32_t val; + rt_uint8_t pv, pd, npd; + + /* get PMCR value */ + val =*(RP) PMU_PMCR; + /* get NPD */ + npd = (val >> 14) & 0x01; + /* get PD */ + pd = (val >> 10) & 0x0f; + /* get PV */ + pv = val & 0x7f; + /* caculate the system clock */ + if(npd) + val = 2 * CLK_IN * pv; + else + val = CLK_IN * pv / (pd + 1); + + return(val); +} + +/** + * @brief Enable module clock + */ + void rt_hw_enable_module_clock(rt_uint8_t module) + { + + } + +/** + * @brief Disable module clock + */ + void rt_hw_disable_module_clock(rt_uint8_t module) + { + + } + diff --git a/libcpu/arm/sep4020/context_rvds.S b/libcpu/arm/sep4020/context_rvds.S index e24fa62a3dd5dd1f46ed2c32255752e171173e46..641ec7a6b1a18b5d8fff4b927e2ad5549ca65f01 100644 --- a/libcpu/arm/sep4020/context_rvds.S +++ b/libcpu/arm/sep4020/context_rvds.S @@ -12,12 +12,12 @@ ; * 2009-01-20 Bernard first version ; */ -NOINT EQU 0xc0 ; disable interrupt in psr +NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 + AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1 + MSR cpsr_c, r1 BX lr - ENDP + ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 + MSR cpsr_c, r0 BX lr ENDP @@ -63,7 +63,7 @@ rt_hw_context_switch PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP + ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP + ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread + IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] + STR r1, [r2] BX lr - ENDP - + ENDP + END \ No newline at end of file diff --git a/libcpu/arm/sep4020/cpu.c b/libcpu/arm/sep4020/cpu.c index b497c6a0ae95ec3c9b39b6d72575c11a9f793c51..093f3c1b141de1915296ea8ab7ca78f403c8caac 100644 --- a/libcpu/arm/sep4020/cpu.c +++ b/libcpu/arm/sep4020/cpu.c @@ -1,190 +1,190 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - */ - -#include -#include - -extern rt_uint32_t rt_hw_interrupt_disable(void); - -//TODO -#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020 - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) - -#ifdef __GNUC__ -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} -#endif - -#ifdef __CC_ARM -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm - { - mrc p15, 0, i, c1, c0, 0 - } - - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} -#endif - -/** - * enable I-Cache - * - */ -void rt_hw_cpu_icache_enable() -{ - cache_enable(ICACHE_MASK); -} - -/** - * disable I-Cache - * - */ -void rt_hw_cpu_icache_disable() -{ - cache_disable(ICACHE_MASK); -} - -/** - * return the status of I-Cache - * - */ -rt_base_t rt_hw_cpu_icache_status() -{ - return (cp15_rd() & ICACHE_MASK); -} - -/** - * enable D-Cache - * - */ -void rt_hw_cpu_dcache_enable() -{ - cache_enable(DCACHE_MASK); -} - -/** - * disable D-Cache - * - */ -void rt_hw_cpu_dcache_disable() -{ - cache_disable(DCACHE_MASK); -} - -/** - * return the status of D-Cache - * - */ -rt_base_t rt_hw_cpu_dcache_status() -{ - return (cp15_rd() & DCACHE_MASK); -} - -/** - * reset cpu by dog's time-out - * - */ -void rt_hw_cpu_reset() -{ - - /* enable watchdog */ - *(RP)(RTC_CTR) = 0x02; - - /*Enable watchdog reset*/ - *(RP)(RTC_INT_EN) = 0x20; - - /* Initialize watchdog timer count register */ - *(RP)(RTC_WD_CNT) = 0x0001; - - while(1); /* loop forever and wait for reset to happen */ - - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -void rt_hw_cpu_shutdown() -{ - rt_uint32_t UNUSED level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - - RT_ASSERT(RT_NULL); -} - -/*@}*/ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + */ + +#include +#include + +extern rt_uint32_t rt_hw_interrupt_disable(void); + +//TODO +#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020 + +/** + * @addtogroup S3C24X0 + */ +/*@{*/ + +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) + +#ifdef __GNUC__ +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} +#endif + +#ifdef __CC_ARM +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + __asm + { + mrc p15, 0, i, c1, c0, 0 + } + + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} +#endif + +/** + * enable I-Cache + * + */ +void rt_hw_cpu_icache_enable() +{ + cache_enable(ICACHE_MASK); +} + +/** + * disable I-Cache + * + */ +void rt_hw_cpu_icache_disable() +{ + cache_disable(ICACHE_MASK); +} + +/** + * return the status of I-Cache + * + */ +rt_base_t rt_hw_cpu_icache_status() +{ + return (cp15_rd() & ICACHE_MASK); +} + +/** + * enable D-Cache + * + */ +void rt_hw_cpu_dcache_enable() +{ + cache_enable(DCACHE_MASK); +} + +/** + * disable D-Cache + * + */ +void rt_hw_cpu_dcache_disable() +{ + cache_disable(DCACHE_MASK); +} + +/** + * return the status of D-Cache + * + */ +rt_base_t rt_hw_cpu_dcache_status() +{ + return (cp15_rd() & DCACHE_MASK); +} + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + + /* enable watchdog */ + *(RP)(RTC_CTR) = 0x02; + + /*Enable watchdog reset*/ + *(RP)(RTC_INT_EN) = 0x20; + + /* Initialize watchdog timer count register */ + *(RP)(RTC_WD_CNT) = 0x0001; + + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t UNUSED level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + + RT_ASSERT(RT_NULL); +} + +/*@}*/ diff --git a/libcpu/arm/sep4020/interrupt.c b/libcpu/arm/sep4020/interrupt.c index 7126e5acc270dcb1659df84be27cba4b92dce25e..8ed22dc816fe21f8c103aac16d75b6dc447d686a 100644 --- a/libcpu/arm/sep4020/interrupt.c +++ b/libcpu/arm/sep4020/interrupt.c @@ -40,30 +40,30 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) */ void rt_hw_interrupt_init() { - register rt_uint32_t idx; - - /*Make sure all intc registers in proper state*/ - - /*mask all the irq*/ - *(RP)(INTC_IMR) = 0xFFFFFFFF; - - /*enable all the irq*/ - *(RP)(INTC_IER) = 0XFFFFFFFF; - - /*Dont use any forced irq*/ - *(RP)(INTC_IFR) = 0x0; - - /*Disable all the fiq*/ - *(RP)(INTC_FIER) = 0x0; - - /*Mask all the fiq*/ - *(RP)(INTC_FIMR) = 0x0F; - - /*Dont use forced fiq*/ - *(RP)(INTC_FIFR) = 0x0; - - /*Intrrupt priority register*/ - *(RP)(INTC_IPLR) = 0x0; + register rt_uint32_t idx; + + /*Make sure all intc registers in proper state*/ + + /*mask all the irq*/ + *(RP)(INTC_IMR) = 0xFFFFFFFF; + + /*enable all the irq*/ + *(RP)(INTC_IER) = 0XFFFFFFFF; + + /*Dont use any forced irq*/ + *(RP)(INTC_IFR) = 0x0; + + /*Disable all the fiq*/ + *(RP)(INTC_FIER) = 0x0; + + /*Mask all the fiq*/ + *(RP)(INTC_FIMR) = 0x0F; + + /*Dont use forced fiq*/ + *(RP)(INTC_FIFR) = 0x0; + + /*Intrrupt priority register*/ + *(RP)(INTC_IPLR) = 0x0; /* init exceptions table */ for(idx=0; idx < MAX_HANDLERS; idx++) @@ -92,15 +92,15 @@ void rt_hw_interrupt_mask(rt_uint32_t vector) * @param vector the interrupt number */ void rt_hw_interrupt_umask(rt_uint32_t vector) -{ - if(vector == 16) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - } - else +{ + if(vector == 16) + { + rt_kprintf("Interrupt vec %d is not used!\n", vector); + } + else *(RP)(INTC_IMR) &= ~(1 << vector); -} - +} + /** * This function will install a interrupt service routine to a interrupt. @@ -112,9 +112,9 @@ void rt_hw_interrupt_install(rt_uint32_t vector, rt_isr_handler_t new_handler, r { if(vector < MAX_HANDLERS) { - if (*old_handler != RT_NULL) + if (*old_handler != RT_NULL) *old_handler = isr_table[vector]; - if (new_handler != RT_NULL) + if (new_handler != RT_NULL) isr_table[vector] = new_handler; } } diff --git a/libcpu/arm/sep4020/sep4020.h b/libcpu/arm/sep4020/sep4020.h index b4590c2ef06429e5a064b5987b4a7b2fb9bc3899..022fddcc19978899bca66aacf594e3f907f716c1 100644 --- a/libcpu/arm/sep4020/sep4020.h +++ b/libcpu/arm/sep4020/sep4020.h @@ -1,867 +1,867 @@ -#ifndef __SEP4020_H -#define __SEP4020_H - -#include - -/*Core definations*/ -#define SVCMODE -#define Mode_USR 0x10 -#define Mode_FIQ 0x11 -#define Mode_IRQ 0x12 -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define Mode_SYS 0x1F - - - -/* - * ¸÷Ä£¿é¼Ä´æÆ÷»ùÖµ - */ - -#define ESRAM_BASE 0x04000000 -#define INTC_BASE 0x10000000 -#define PMU_BASE 0x10001000 -#define RTC_BASE 0x10002000 -#define WD_BASE 0x10002000 -#define TIMER_BASE 0x10003000 -#define PWM_BASE 0x10004000 -#define UART0_BASE 0X10005000 -#define UART1_BASE 0X10006000 -#define UART2_BASE 0X10007000 -#define UART3_BASE 0X10008000 -#define SSI_BASE 0X10009000 -#define I2S_BASE 0x1000A000 -#define MMC_BASE 0x1000B000 -#define SD_BASE 0x1000B000 -#define SMC0_BASE 0x1000C000 -#define SMC1_BASE 0x1000D000 -#define USBD_BASE 0x1000E000 -#define GPIO_BASE 0x1000F000 -#define EMI_BASE 0x11000000 -#define DMAC_BASE 0x11001000 -#define LCDC_BASE 0x11002000 -#define MAC_BASE 0x11003000 -#define AMBA_BASE 0x11005000 - - -/* - * INTCÄ£¿é - * »ùÖ·: 0x10000000 - */ - -#define INTC_IER (INTC_BASE+0X000) /* IRQÖжÏÔÊÐí¼Ä´æÆ÷ */ -#define INTC_IMR (INTC_BASE+0X008) /* IRQÖжÏÆÁ±Î¼Ä´æÆ÷ */ -#define INTC_IFR (INTC_BASE+0X010) /* IRQÈí¼þÇ¿ÖÆÖжϼĴæÆ÷ */ -#define INTC_IRSR (INTC_BASE+0X018) /* IRQδ´¦ÀíÖжÏ״̬¼Ä´æÆ÷ */ -#define INTC_ISR (INTC_BASE+0X020) /* IRQÖжÏ״̬¼Ä´æÆ÷ */ -#define INTC_IMSR (INTC_BASE+0X028) /* IRQÆÁ±ÎÖжÏ״̬¼Ä´æÆ÷ */ -#define INTC_IFSR (INTC_BASE+0X030) /* IRQÖжÏ×îÖÕ״̬¼Ä´æÆ÷ */ -#define INTC_FIER (INTC_BASE+0X0C0) /* FIQÖжÏÔÊÐí¼Ä´æÆ÷ */ -#define INTC_FIMR (INTC_BASE+0X0C4) /* FIQÖжÏÆÁ±Î¼Ä´æÆ÷ */ -#define INTC_FIFR (INTC_BASE+0X0C8) /* FIQÈí¼þÇ¿ÖÆÖжϼĴæÆ÷ */ -#define INTC_FIRSR (INTC_BASE+0X0CC) /* FIQδ´¦ÀíÖжÏ״̬¼Ä´æÆ÷ */ -#define INTC_FISR (INTC_BASE+0X0D0) /* FIQÖжÏ״̬¼Ä´æÆ÷ */ -#define INTC_FIFSR (INTC_BASE+0X0D4) /* FIQÖжÏ×îÖÕ״̬¼Ä´æÆ÷ */ -#define INTC_IPLR (INTC_BASE+0X0D8) /* IRQÖжÏÓÅÏȼ¶¼Ä´æÆ÷ */ -#define INTC_ICR1 (INTC_BASE+0X0DC) /* IRQÄÚ²¿ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 */ -#define INTC_ICR2 (INTC_BASE+0X0E0) /* IRQÄÚ²¿ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷2 */ -#define INTC_EXICR1 (INTC_BASE+0X0E4) /* IRQÍⲿÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 */ -#define INTC_EXICR2 (INTC_BASE+0X0E8) /* IRQÍⲿÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷2 */ - - -/* - * PMUÄ£¿é - * »ùÖ·: 0x10001000 - */ - -#define PMU_PLTR (PMU_BASE+0X000) /* PLLµÄÎȶ¨¹ý¶Éʱ¼ä */ -#define PMU_PMCR (PMU_BASE+0X004) /* ϵͳÖ÷ʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ */ -#define PMU_PUCR (PMU_BASE+0X008) /* USBʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ */ -#define PMU_PCSR (PMU_BASE+0X00C) /* ÄÚ²¿Ä£¿éʱÖÓÔ´¹©¸øµÄ¿ØÖƼĴæÆ÷ */ -#define PMU_PDSLOW (PMU_BASE+0X010) /* SLOW״̬ÏÂʱÖӵķÖƵÒò×Ó */ -#define PMU_PMDR (PMU_BASE+0X014) /* оƬ¹¤×÷ģʽ¼Ä´æÆ÷ */ -#define PMU_RCTR (PMU_BASE+0X018) /* Reset¿ØÖƼĴæÆ÷ */ -#define PMU_CLRWAKUP (PMU_BASE+0X01C) /* WakeUpÇå³ý¼Ä´æÆ÷ */ - - -/* - * RTCÄ£¿é - * »ùÖ·: 0x10002000 - */ - -#define RTC_STA_YMD (RTC_BASE+0X000) /* Äê, ÔÂ, ÈÕ¼ÆÊý¼Ä´æÆ÷ */ -#define RTC_STA_HMS (RTC_BASE+0X004) /* Сʱ, ·ÖÖÓ, Ãë¼Ä´æÆ÷ */ -#define RTC_ALARM_ALL (RTC_BASE+0X008) /* ¶¨Ê±ÔÂ, ÈÕ, ʱ, ·Ö¼Ä´æÆ÷ */ -#define RTC_CTR (RTC_BASE+0X00C) /* ¿ØÖƼĴæÆ÷ */ -#define RTC_INT_EN (RTC_BASE+0X010) /* ÖжÏʹÄܼĴæÆ÷ */ -#define RTC_INT_STS (RTC_BASE+0X014) /* ÖжÏ״̬¼Ä´æÆ÷ */ -#define RTC_SAMP (RTC_BASE+0X018) /* ²ÉÑùÖÜÆڼĴæÆ÷ */ -#define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog·þÎñ¼Ä´æÆ÷ */ -#define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* ÅäÖÃʱ¼äÈ·ÈϼĴæÆ÷ (ÔÚÅäÖÃʱ¼ä֮ǰÏÈд0xaaaaaaaa) */ -#define RTC_KEY0 (RTC_BASE+0X02C) /* ÃÜÔ¿¼Ä´æÆ÷ */ - -/* - * TIMERÄ£¿é - * »ùÖ·: 0x10003000 - */ - -#define TIMER_T1LCR (TIMER_BASE+0X000) /* ͨµÀ1¼ÓÔؼÆÊý¼Ä´æÆ÷ */ -#define TIMER_T1CCR (TIMER_BASE+0X004) /* ͨµÀ1µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define TIMER_T1CR (TIMER_BASE+0X008) /* ͨµÀ1¿ØÖƼĴæÆ÷ */ -#define TIMER_T1ISCR (TIMER_BASE+0X00C) /* ͨµÀ1ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_T1IMSR (TIMER_BASE+0X010) /* ͨµÀ1ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_T2LCR (TIMER_BASE+0X020) /* ͨµÀ2¼ÓÔؼÆÊý¼Ä´æÆ÷ */ -#define TIMER_T2CCR (TIMER_BASE+0X024) /* ͨµÀ2µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define TIMER_T2CR (TIMER_BASE+0X028) /* ͨµÀ2¿ØÖƼĴæÆ÷ */ -#define TIMER_T2ISCR (TIMER_BASE+0X02C) /* ͨµÀ2ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_T2IMSR (TIMER_BASE+0X030) /* ͨµÀ2ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_T3LCR (TIMER_BASE+0X040) /* ͨµÀ3¼ÓÔؼÆÊý¼Ä´æÆ÷ */ -#define TIMER_T3CCR (TIMER_BASE+0X044) /* ͨµÀ3µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define TIMER_T3CR (TIMER_BASE+0X048) /* ͨµÀ3¿ØÖƼĴæÆ÷ */ -#define TIMER_T3ISCR (TIMER_BASE+0X04C) /* ͨµÀ3ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_T3IMSR (TIMER_BASE+0X050) /* ͨµÀ3ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_T3CAPR (TIMER_BASE+0X054) /* ͨµÀ3²¶»ñ¼Ä´æÆ÷ */ -#define TIMER_T4LCR (TIMER_BASE+0X060) /* ͨµÀ4¼ÓÔؼÆÊý¼Ä´æÆ÷ */ -#define TIMER_T4CCR (TIMER_BASE+0X064) /* ͨµÀ4µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define TIMER_T4CR (TIMER_BASE+0X068) /* ͨµÀ4¿ØÖƼĴæÆ÷ */ -#define TIMER_T4ISCR (TIMER_BASE+0X06C) /* ͨµÀ4ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_T4IMSR (TIMER_BASE+0X070) /* ͨµÀ4ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_T4CAPR (TIMER_BASE+0X074) /* ͨµÀ4²¶»ñ¼Ä´æÆ÷ */ -#define TIMER_T5LCR (TIMER_BASE+0X080) /* ͨµÀ5¼ÓÔؼÆÊý¼Ä´æÆ÷ */ -#define TIMER_T5CCR (TIMER_BASE+0X084) /* ͨµÀ5µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define TIMER_T5CR (TIMER_BASE+0X088) /* ͨµÀ5¿ØÖƼĴæÆ÷ */ -#define TIMER_T5ISCR (TIMER_BASE+0X08C) /* ͨµÀ5ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_T5IMSR (TIMER_BASE+0X090) /* ͨµÀ5ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_T5CAPR (TIMER_BASE+0X094) /* ͨµÀ5²¶»ñ¼Ä´æÆ÷ */ -#define TIMER_T6LCR (TIMER_BASE+0X0A0) /* ͨµÀ6¼ÓÔؼÆÊý¼Ä´æÆ÷ */ -#define TIMER_T6CCR (TIMER_BASE+0X0A4) /* ͨµÀ6µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define TIMER_T6CR (TIMER_BASE+0X0A8) /* ͨµÀ6¿ØÖƼĴæÆ÷ */ -#define TIMER_T6ISCR (TIMER_BASE+0X0AC) /* ͨµÀ6ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_T6IMSR (TIMER_BASE+0X0B0) /* ͨµÀ6ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_T6CAPR (TIMER_BASE+0X0B4) /* ͨµÀ6²¶»ñ¼Ä´æÆ÷ */ -#define TIMER_T7LCR (TIMER_BASE+0X0C0) /* ͨµÀ7¼ÓÔؼÆÊý¼Ä´æÆ÷ */ -#define TIMER_T7CCR (TIMER_BASE+0X0C4) /* ͨµÀ7µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define TIMER_T7CR (TIMER_BASE+0X0C8) /* ͨµÀ7¿ØÖƼĴæÆ÷ */ -#define TIMER_T7ISCR (TIMER_BASE+0X0CC) /* ͨµÀ7ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_T7IMSR (TIMER_BASE+0X0D0) /* ͨµÀ7ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_T8LCR (TIMER_BASE+0X0E0) /* ͨµÀ8¼ÓÔؼÆÊý¼Ä´æÆ÷ */ -#define TIMER_T8CCR (TIMER_BASE+0X0E4) /* ͨµÀ8µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define TIMER_T8CR (TIMER_BASE+0X0E8) /* ͨµÀ8¿ØÖƼĴæÆ÷ */ -#define TIMER_T8ISCR (TIMER_BASE+0X0EC) /* ͨµÀ8ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_T8IMSR (TIMER_BASE+0X0F0) /* ͨµÀ8ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_T9LCR (TIMER_BASE+0X100) /* ͨµÀ9¼ÓÔؼÆÊý¼Ä´æÆ÷ */ -#define TIMER_T9CCR (TIMER_BASE+0X104) /* ͨµÀ9µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define TIMER_T9CR (TIMER_BASE+0X108) /* ͨµÀ9¿ØÖƼĴæÆ÷ */ -#define TIMER_T9ISCR (TIMER_BASE+0X10C) /* ͨµÀ9ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_T9IMSR (TIMER_BASE+0X110) /* ͨµÀ9ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_T10LCR (TIMER_BASE+0X120) /* ͨµÀ10¼ÓÔؼÆÊý¼Ä´æÆ÷ */ -#define TIMER_T10CCR (TIMER_BASE+0X124) /* ͨµÀ10µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ -#define TIMER_T10CR (TIMER_BASE+0X128) /* ͨµÀ10¿ØÖƼĴæÆ÷ */ -#define TIMER_T10ISCR (TIMER_BASE+0X12C) /* ͨµÀ10ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_T10IMSR (TIMER_BASE+0X130) /* ͨµÀ10ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_TIMSR (TIMER_BASE+0X140) /* TIMERÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ -#define TIMER_TISCR (TIMER_BASE+0X144) /* TIMERÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define TIMER_TISR (TIMER_BASE+0X148) /* TIMERÖжÏ״̬¼Ä´æÆ÷ */ - - - -/* - * PWMÄ£¿é - * »ùÖ·: 0x10004000 - */ - -#define PWM0_CTRL (PWM_BASE+0X000) /* PWM0¿ØÖƼĴæÆ÷ */ -#define PWM0_DIV (PWM_BASE+0X004) /* PWM0·ÖƵ¼Ä´æÆ÷ */ -#define PWM0_PERIOD (PWM_BASE+0X008) /* PWM0ÖÜÆڼĴæÆ÷ */ -#define PWM0_DATA (PWM_BASE+0X00C) /* PWM0Êý¾Ý¼Ä´æÆ÷ */ -#define PWM0_CNT (PWM_BASE+0X010) /* PWM0¼ÆÊý¼Ä´æÆ÷ */ -#define PWM0_STATUS (PWM_BASE+0X014) /* PWM0״̬¼Ä´æÆ÷ */ -#define PWM1_CTRL (PWM_BASE+0X020) /* PWM1¿ØÖƼĴæÆ÷ */ -#define PWM1_DIV (PWM_BASE+0X024) /* PWM1·ÖƵ¼Ä´æÆ÷ */ -#define PWM1_PERIOD (PWM_BASE+0X028) /* PWM1ÖÜÆڼĴæÆ÷ */ -#define PWM1_DATA (PWM_BASE+0X02C) /* PWM1Êý¾Ý¼Ä´æÆ÷ */ -#define PWM1_CNT (PWM_BASE+0X030) /* PWM1¼ÆÊý¼Ä´æÆ÷ */ -#define PWM1_STATUS (PWM_BASE+0X034) /* PWM1״̬¼Ä´æÆ÷ */ -#define PWM2_CTRL (PWM_BASE+0X040) /* PWM2¿ØÖƼĴæÆ÷ */ -#define PWM2_DIV (PWM_BASE+0X044) /* PWM2·ÖƵ¼Ä´æÆ÷ */ -#define PWM2_PERIOD (PWM_BASE+0X048) /* PWM2ÖÜÆڼĴæÆ÷ */ -#define PWM2_DATA (PWM_BASE+0X04C) /* PWM2Êý¾Ý¼Ä´æÆ÷ */ -#define PWM2_CNT (PWM_BASE+0X050) /* PWM2¼ÆÊý¼Ä´æÆ÷ */ -#define PWM2_STATUS (PWM_BASE+0X054) /* PWM2״̬¼Ä´æÆ÷ */ -#define PWM3_CTRL (PWM_BASE+0X060) /* PWM3¿ØÖƼĴæÆ÷ */ -#define PWM3_DIV (PWM_BASE+0X064) /* PWM3·ÖƵ¼Ä´æÆ÷ */ -#define PWM3_PERIOD (PWM_BASE+0X068) /* PWM3ÖÜÆڼĴæÆ÷ */ -#define PWM3_DATA (PWM_BASE+0X06C) /* PWM3Êý¾Ý¼Ä´æÆ÷ */ -#define PWM3_CNT (PWM_BASE+0X070) /* PWM3¼ÆÊý¼Ä´æÆ÷ */ -#define PWM3_STATUS (PWM_BASE+0X074) /* PWM3״̬¼Ä´æÆ÷ */ -#define PWM_INTMASK (PWM_BASE+0X080) /* PWMÖжÏÆÁ±Î¼Ä´æÆ÷ */ -#define PWM_INT (PWM_BASE+0X084) /* PWMÖжϼĴæÆ÷ */ -#define PWM_ENABLE (PWM_BASE+0X088) /* PWMʹÄܼĴæÆ÷ */ - - -/* - * UART0Ä£¿é - * »ùÖ·: 0x10005000 - */ - -#define UART0_DLBL (UART0_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ -#define UART0_RXFIFO (UART0_BASE+0X000) /* ½ÓÊÕFIFO */ -#define UART0_TXFIFO (UART0_BASE+0X000) /* ·¢ËÍFIFO */ -#define UART0_DLBH (UART0_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ -#define UART0_IER (UART0_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ -#define UART0_IIR (UART0_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ -#define UART0_FCR (UART0_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ -#define UART0_LCR (UART0_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ -#define UART0_MCR (UART0_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ -#define UART0_LSR (UART0_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ -#define UART0_MSR (UART0_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ - - -/* - * UART1Ä£¿é - * »ùÖ·: 0x10006000 - */ - -#define UART1_DLBL (UART1_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ -#define UART1_RXFIFO (UART1_BASE+0X000) /* ½ÓÊÕFIFO */ -#define UART1_TXFIFO (UART1_BASE+0X000) /* ·¢ËÍFIFO */ -#define UART1_DLBH (UART1_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ -#define UART1_IER (UART1_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ -#define UART1_IIR (UART1_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ -#define UART1_FCR (UART1_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ -#define UART1_LCR (UART1_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ -#define UART1_MCR (UART1_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ -#define UART1_LSR (UART1_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ -#define UART1_MSR (UART1_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ - - -/* - * UART2Ä£¿é - * »ùÖ·: 0x10007000 - */ - -#define UART2_DLBL (UART2_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ -#define UART2_RXFIFO (UART2_BASE+0X000) /* ½ÓÊÕFIFO */ -#define UART2_TXFIFO (UART2_BASE+0X000) /* ·¢ËÍFIFO */ -#define UART2_DLBH (UART2_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ -#define UART2_IER (UART2_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ -#define UART2_IIR (UART2_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ -#define UART2_FCR (UART2_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ -#define UART2_LCR (UART2_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ -#define UART2_MCR (UART2_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ -#define UART2_LSR (UART2_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ -#define UART2_MSR (UART2_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ - - -/* - * UART3Ä£¿é - * »ùÖ·: 0x10008000 - */ - -#define UART3_DLBL (UART3_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ -#define UART3_RXFIFO (UART3_BASE+0X000) /* ½ÓÊÕFIFO */ -#define UART3_TXFIFO (UART3_BASE+0X000) /* ·¢ËÍFIFO */ -#define UART3_DLBH (UART3_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ -#define UART3_IER (UART3_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ -#define UART3_IIR (UART3_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ -#define UART3_FCR (UART3_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ -#define UART3_LCR (UART3_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ -#define UART3_MCR (UART3_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ -#define UART3_LSR (UART3_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ -#define UART3_MSR (UART3_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ - - -/* - * SSIÄ£¿é - * »ùÖ·: 0x10009000 - */ - -#define SSI_CONTROL0 (SSI_BASE+0X000) /* ¿ØÖƼĴæÆ÷0 */ -#define SSI_CONTROL1 (SSI_BASE+0X004) /* ¿ØÖƼĴæÆ÷1 */ -#define SSI_SSIENR (SSI_BASE+0X008) /* SSIʹÄܼĴæÆ÷ */ -#define SSI_MWCR (SSI_BASE+0X00C) /* Microwire¿ØÖƼĴæÆ÷ */ -#define SSI_SER (SSI_BASE+0X010) /* ´ÓÉ豸ʹÄܼĴæÆ÷ */ -#define SSI_BAUDR (SSI_BASE+0X014) /* ²¨ÌØÂÊÉèÖüĴæÆ÷ */ -#define SSI_TXFTLR (SSI_BASE+0X018) /* ·¢ËÍFIFOãÐÖµ¼Ä´æÆ÷ */ -#define SSI_RXFTLR (SSI_BASE+0X01C) /* ½ÓÊÕFIFOãÐÖµ¼Ä´æÆ÷ */ -#define SSI_TXFLR (SSI_BASE+0X020) /* ·¢ËÍFIFO״̬¼Ä´æÆ÷ */ -#define SSI_RXFLR (SSI_BASE+0X024) /* ½ÓÊÕFIFO״̬¼Ä´æÆ÷ */ -#define SSI_SR (SSI_BASE+0X028) /* ״̬¼Ä´æÆ÷ */ -#define SSI_IMR (SSI_BASE+0X02C) /* ÖжÏÆÁ±Î¼Ä´æÆ÷ */ -#define SSI_ISR (SSI_BASE+0X030) /* ÖжÏ×îÖÕ״̬¼Ä´æÆ÷ */ -#define SSI_RISR (SSI_BASE+0X034) /* ÖжÏԭʼ״̬¼Ä´æÆ÷ */ -#define SSI_TXOICR (SSI_BASE+0X038) /* ·¢ËÍFIFOÉÏÒçÖжÏÇå³ý¼Ä´æÆ÷ */ -#define SSI_RXOICR (SSI_BASE+0X03C) /* ½ÓÊÕFIFOÉÏÒçÖжÏÇå³ý¼Ä´æÆ÷ */ -#define SSI_RXUICR (SSI_BASE+0X040) /* ½ÓÊÕFIFOÏÂÒçÖжÏÇå³ý¼Ä´æÆ÷ */ -#define SSI_ICR (SSI_BASE+0X02C) /* ÖжÏÇå³ý¼Ä´æÆ÷ */ -#define SSI_DMACR (SSI_BASE+0X04C) /* DMA¿ØÖƼĴæÆ÷ */ -#define SSI_DMATDLR (SSI_BASE+0X050) /* DMA·¢ËÍ״̬¼Ä´æÆ÷ */ -#define SSI_DMARDLR (SSI_BASE+0X054) /* DMA½ÓÊÕ״̬¼Ä´æÆ÷ */ -#define SSI_DR (SSI_BASE+0X060) /* Êý¾Ý¼Ä´æÆ÷ */ - - -/* - * I2SÄ£¿é - * »ùÖ·: 0x1000A000 - */ - -#define I2S_CTRL (I2S_BASE+0X000) /* I2S¿ØÖƼĴæÆ÷ */ -#define I2S_DATA (I2S_BASE+0X004) /* I2SÊý¾Ý¼Ä´æÆ÷ */ -#define I2S_INT (I2S_BASE+0X008) /* I2SÖжϼĴæÆ÷ */ -#define I2S_STATUS (I2S_BASE+0X00C) /* I2S״̬¼Ä´æÆ÷ */ - - -/* - * SDÄ£¿é - * »ùÖ·: 0x1000B000 - */ - -#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIOʱÖÓ¿ØÖƼĴæÆ÷ */ -#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIOÈí¼þ¸´Î»¼Ä´æÆ÷ */ -#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIOÃüÁî²ÎÊý¼Ä´æÆ÷ */ -#define SDC_COMMAND (SD_BASE+0X0C) /* SDIOÃüÁî¿ØÖƼĴæÆ÷ */ -#define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIOÊý¾Ý¿é³¤¶È¼Ä´æÆ÷ */ -#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIOÊý¾Ý¿éÊýÄ¿¼Ä´æÆ÷ */ -#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO´«ÊäģʽѡÔñ¼Ä´æÆ÷ */ -#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIOÏìÓ¦¼Ä´æÆ÷0 */ -#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIOÏìÓ¦¼Ä´æÆ÷1 */ -#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIOÏìÓ¦¼Ä´æÆ÷2 */ -#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIOÏìÓ¦¼Ä´æÆ÷3 */ -#define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO¶Á³¬Ê±¿ØÖƼĴæÆ÷ */ -#define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIOÖжÏ״̬¼Ä´æÆ÷ */ -#define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIOÖжÏ״̬ÆÁ±Î¼Ä´æÆ÷ */ -#define SDC_READ_BUFER_ACCESS (SD_BASE+0X38) /* SDIO½ÓÊÕFIFO */ -#define SDC_WRITE_BUFER_ACCESS (SD_BASE+0X3c) /* SDIO·¢ËÍFIFO */ - - - -/* - * SMC0Ä£¿é - * »ùÖ·: 0x1000C000 - */ - -#define SMC0_CTRL (SMC0_BASE+0X000) /* SMC0¿ØÖƼĴæÆ÷ */ -#define SMC0_INT (SMC0_BASE+0X004) /* SMC0ÖжϼĴæÆ÷ */ -#define SMC0_FD (SMC0_BASE+0X008) /* SMC0»ù±¾µ¥ÔªÊ±¼ä¼Ä´æÆ÷ */ -#define SMC0_CT (SMC0_BASE+0X00C) /* SMC0×Ö·û´«Êäʱ¼ä¼Ä´æÆ÷ */ -#define SMC0_BT (SMC0_BASE+0X010) /* SMC0¿é´«Êäʱ¼ä¼Ä´æÆ÷ */ - - - -/* - * SMC1Ä£¿é - * »ùÖ·: 0x1000D000 - */ - -#define SMC1_CTRL (SMC1_BASE+0X000) /* SMC1¿ØÖƼĴæÆ÷ */ -#define SMC1_INT (SMC1_BASE+0X004) /* SMC1ÖжϼĴæÆ÷ */ -#define SMC1_FD (SMC1_BASE+0X008) /* SMC1»ù±¾µ¥ÔªÊ±¼ä¼Ä´æÆ÷ */ -#define SMC1_CT (SMC1_BASE+0X00C) /* SMC1×Ö·û´«Êäʱ¼ä¼Ä´æÆ÷ */ -#define SMC1_BT (SMC1_BASE+0X010) /* SMC1¿é´«Êäʱ¼ä¼Ä´æÆ÷ */ - - - -/* - * USBDÄ£¿é - * »ùÖ·: 0x1000E000 - */ - -#define USBD_PROTOCOLINTR (USBD_BASE+0X000) /* USBЭÒéÖжϼĴæÆ÷ */ -#define USBD_INTRMASK (USBD_BASE+0X004) /* USBÖжÏÆÁ±Î¼Ä´æÆ÷ */ -#define USBD_INTRCTRL (USBD_BASE+0X008) /* USBÖжÏÀàÐÍ¿ØÖƼĴæÆ÷ */ -#define USBD_EPINFO (USBD_BASE+0X00C) /* USB»î¶¯¶Ëµã״̬¼Ä´æÆ÷ */ -#define USBD_BCONFIGURATIONVALUE (USBD_BASE+0X010) /* SET_CCONFIGURATION¼Ç¼ */ -#define USBD_BMATTRIBUTES (USBD_BASE+0X014) /* µ±Ç°ÅäÖÃÊôÐԼĴæÆ÷ */ -#define USBD_DEVSPEED (USBD_BASE+0X018) /* µ±Ç°É豸¹¤×÷ËٶȼĴæÆ÷ */ -#define USBD_FRAMENUMBER (USBD_BASE+0X01C) /* ¼Ç¼µ±Ç°SOF°üÄÚµÄÖ¡ºÅ */ -#define USBD_EPTRANSACTIONS0 (USBD_BASE+0X020) /* ¼Ç¼Ï´ÎÒªÇóµÄ´«Êä´ÎÊý */ -#define USBD_EPTRANSACTIONS1 (USBD_BASE+0X024) /* ¼Ç¼Ï´ÎÒªÇóµÄ´«Êä´ÎÊý */ -#define USBD_APPIFUPDATE (USBD_BASE+0X028) /* ½Ó¿ÚºÅ¿ìËÙ¸üмĴæÆ÷ */ -#define USBD_CFGINTERFACE0 (USBD_BASE+0X02C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE1 (USBD_BASE+0X030) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE2 (USBD_BASE+0X034) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE3 (USBD_BASE+0X038) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE4 (USBD_BASE+0X03C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE5 (USBD_BASE+0X040) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE6 (USBD_BASE+0X044) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE7 (USBD_BASE+0X048) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE8 (USBD_BASE+0X04C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE9 (USBD_BASE+0X050) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE10 (USBD_BASE+0X054) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE11 (USBD_BASE+0X058) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE12 (USBD_BASE+0X05C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE13 (USBD_BASE+0X060) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE14 (USBD_BASE+0X064) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE15 (USBD_BASE+0X068) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE16 (USBD_BASE+0X06C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE17 (USBD_BASE+0X070) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE18 (USBD_BASE+0X074) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE19 (USBD_BASE+0X078) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE20 (USBD_BASE+0X07C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE21 (USBD_BASE+0X080) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE22 (USBD_BASE+0X084) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE23 (USBD_BASE+0X088) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE24 (USBD_BASE+0X08C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE25 (USBD_BASE+0X090) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE26 (USBD_BASE+0X094) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE27 (USBD_BASE+0X098) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE28 (USBD_BASE+0X09C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE29 (USBD_BASE+0X0A0) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE30 (USBD_BASE+0X0A4) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_CFGINTERFACE31 (USBD_BASE+0X0A8) /* ¼Ç¼½Ó¿ÚµÄÖµ */ -#define USBD_PKTPASSEDCTRL (USBD_BASE+0X0AC) /* ¼Ç¼³É¹¦½ÓÊյİüÊý */ -#define USBD_PKTDROPPEDCTRL (USBD_BASE+0X0B0) /* ¼Ç¼¶ªÊ§µÄ°üÊý */ -#define USBD_CRCERRCTRL (USBD_BASE+0X0B4) /* ¼Ç¼CRC´íÎóµÄ°üÊý */ -#define USBD_BITSTUFFERRCTRL (USBD_BASE+0X0B8) /* ¼Ç¼λÌî³ä´íÎóµÄ°üÊý */ -#define USBD_PIDERRCTRL (USBD_BASE+0X0BC) /* ¼Ç¼PID´íÎóµÄ°üÊý */ -#define USBD_FRAMINGERRCTL (USBD_BASE+0X0C0) /* ¼Ç¼ÓÐSYNCºÍEOPµÄ°üÊý */ -#define USBD_TXPKTCTRL (USBD_BASE+0X0C4) /* ¼Ç¼·¢ËÍ°üµÄÊýÁ¿ */ -#define USBD_STATCTRLOV (USBD_BASE+0X0C8) /* ¼Ç¼ͳ¼Æ¼Ä´æÆ÷Òç³öÇé¿ö */ -#define USBD_TXLENGTH (USBD_BASE+0X0CC) /* ¼Ç¼ÿ´ÎIN´«ÊäÊÂÎñ°ü³¤¶È */ -#define USBD_RXLENGTH (USBD_BASE+0X0D0) /* ¼Ç¼OUT´«ÊäÊÂÎñ°ü³¤¶È */ -#define USBD_RESUME (USBD_BASE+0X0D4) /* USB»½ÐѼĴæÆ÷ */ -#define USBD_READFLAG (USBD_BASE+0X0D8) /* ¶ÁÒ첽״̬¼Ä´æÆ÷±êÖ¾ */ -#define USBD_RECEIVETYPE (USBD_BASE+0X0DC) /* ´«Êä״̬¼Ä´æÆ÷ */ -#define USBD_APPLOCK (USBD_BASE+0X0E0) /* ËøÐźżĴæÆ÷ */ -#define USBD_EP0OUTADDR (USBD_BASE+0X100) /* ¶Ëµã0¶ËµãºÅºÍ·½Ïò */ -#define USBD_EP0OUTBMATTR (USBD_BASE+0X104) /* ¶Ëµã0ÀàÐͼĴæÆ÷ */ -#define USBD_EP0OUTMAXPKTSIZE (USBD_BASE+0X108) /* ¶Ëµã0×î´ó°ü³ß´ç¼Ä´æÆ÷ */ -#define USBD_EP0OUTIFNUM (USBD_BASE+0X10C) /* ¶Ëµã0½Ó¿ÚºÅ¼Ä´æÆ÷ */ -#define USBD_EP0OUTSTAT (USBD_BASE+0X110) /* ¶Ëµã0״̬¼Ä´æÆ÷ */ -#define USBD_EP0OUTBMREQTYPE (USBD_BASE+0X114) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóÀà */ -#define USBD_EP0OUTBREQUEST (USBD_BASE+0X118) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóÄÚÈÝ */ -#define USBD_EP0OUTWVALUE (USBD_BASE+0X11C) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóÖµ */ -#define USBD_EP0OUTWINDEX (USBD_BASE+0X120) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóË÷Òý */ -#define USBD_EP0OUTWLENGTH (USBD_BASE+0X120) /* ¶Ëµã0 SETUPÊÂÎñÇëÇó³¤¶È */ -#define USBD_EP0OUTSYNCHFRAME (USBD_BASE+0X128) /* ¶Ëµã0ͬ²½°üÖ¡ºÅ */ -#define USBD_EP1OUTADDR (USBD_BASE+0X12C) /* ¶Ëµã1Êä³ö¶ËµãºÅºÍ·½Ïò */ -#define USBD_EP1OUTBMATTR (USBD_BASE+0X130) /* ¶Ëµã1Êä³öÀàÐͼĴæÆ÷ */ -#define USBD_EP1OUTMAXPKTSIZE (USBD_BASE+0X134) /* ¶Ëµã1Êä³ö×î´ó°ü³ß´ç¼Ä´æÆ÷ */ -#define USBD_EP1OUTIFNUM (USBD_BASE+0X138) /* ¶Ëµã1Êä³ö½Ó¿ÚºÅ¼Ä´æÆ÷ */ -#define USBD_EP1OUTSTAT (USBD_BASE+0X13C) /* ¶Ëµã1Êä³ö״̬¼Ä´æÆ÷ */ -#define USBD_EP1OUTBMREQTYPE (USBD_BASE+0X140) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÀàÐÍ */ -#define USBD_EP1OUTBREQUEST (USBD_BASE+0X144) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÄÚÈÝ */ -#define USBD_EP1OUTWVALUE (USBD_BASE+0X148) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÖµ */ -#define USBD_EP1OUTWINDX (USBD_BASE+0X14C) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóË÷Òý */ -#define USBD_EP1OUTWLENGH (USBD_BASE+0X150) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÓò³¤¶È */ -#define USBD_EP1OUTSYNCHFRAME (USBD_BASE+0X154) /* ¶Ëµã1Êä³öͬ²½°üÖ¡ºÅ */ -#define USBD_EP1INADDR (USBD_BASE+0X158) /* ¶Ëµã1ÊäÈë¶ËµãºÅºÍ·½Ïò */ -#define USBD_EP1INBMATTR (USBD_BASE+0X15C) /* ¶Ëµã1ÊäÈëÀàÐͼĴæÆ÷ */ -#define USBD_EP1INMAXPKTSIZE (USBD_BASE+0X160) /* ¶Ëµã1ÊäÈë×î´ó°ü³ß´ç¼Ä´æÆ÷ */ -#define USBD_EP1INIFNUM (USBD_BASE+0X164) /* ¶Ëµã1ÊäÈë½Ó¿ÚºÅ¼Ä´æÆ÷ */ -#define USBD_EP1INSTAT (USBD_BASE+0X168) /* ¶Ëµã1ÊäÈë״̬¼Ä´æÆ÷ */ -#define USBD_EP1INBMREQTYPE (USBD_BASE+0X16C) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÀàÐÍ */ -#define USBD_EP1INBREQUEST (USBD_BASE+0X170) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÄÚÈÝ */ -#define USBD_EP1INWVALUE (USBD_BASE+0X174) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÖµ */ -#define USBD_EP1INWINDEX (USBD_BASE+0X178) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóË÷Òý */ -#define USBD_EP1INWLENGTH (USBD_BASE+0X17C) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÓò³¤¶È */ -#define USBD_EP1INSYNCHFRAME (USBD_BASE+0X180) /* ¶Ëµã1ÊäÈëͬ²½°üÖ¡ºÅ */ -#define USBD_EP2OUTADDR (USBD_BASE+0X184) /* ¶Ëµã2Êä³ö¶ËµãºÅºÍ·½Ïò */ -#define USBD_EP2OUTBMATTR (USBD_BASE+0X188) /* ¶Ëµã2Êä³öÀàÐͼĴæÆ÷ */ -#define USBD_EP2OUTMAXPKTSIZE (USBD_BASE+0X18C) /* ¶Ëµã2Êä³ö×î´ó°ü³ß´ç¼Ä´æÆ÷ */ -#define USBD_EP2OUTIFNUM (USBD_BASE+0X190) /* ¶Ëµã2Êä³ö½Ó¿ÚºÅ¼Ä´æÆ÷ */ -#define USBD_EP2OUTSTAT (USBD_BASE+0X194) /* ¶Ëµã2Êä³ö״̬¼Ä´æÆ÷ */ -#define USBD_EP2OUTBMREQTYPE (USBD_BASE+0X198) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÀàÐÍ */ -#define USBD_EP2OUTBREQUEST (USBD_BASE+0X19C) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÄÚÈÝ */ -#define USBD_EP2OUTWVALUE (USBD_BASE+0X1A0) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÖµ */ -#define USBD_EP2OUTWINDEX (USBD_BASE+0X1A4) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóË÷Òý */ -#define USBD_EP2OUTWLENGTH (USBD_BASE+0X1A8) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÓò³¤¶È */ -#define USBD_EP2OUTSYNCHFRAME (USBD_BASE+0X1AC) /* ¶Ëµã2Êä³öͬ²½°üÖ¡ºÅ */ -#define USBD_EP2INADDR (USBD_BASE+0X1B0) /* ¶Ëµã2ÊäÈë¶ËµãºÅºÍ·½Ïò */ -#define USBD_EP2INBMATTR (USBD_BASE+0X1B4) /* ¶Ëµã2ÊäÈëÀàÐͼĴæÆ÷ */ -#define USBD_EP2INMAXPKTSIZE (USBD_BASE+0X1B8) /* ¶Ëµã2ÊäÈë×î´ó°ü³ß´ç¼Ä´æÆ÷ */ -#define USBD_EP2INIFNUM (USBD_BASE+0X1BC) /* ¶Ëµã2ÊäÈë½Ó¿ÚºÅ¼Ä´æÆ÷ */ -#define USBD_EP2INSTAT (USBD_BASE+0X1C0) /* ¶Ëµã2ÊäÈë״̬¼Ä´æÆ÷ */ -#define USBD_EP2INBMREQTYPE (USBD_BASE+0X1C4) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÀàÐÍ */ -#define USBD_EP2INBREQUEST (USBD_BASE+0X1C8) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÄÚÈÝ */ -#define USBD_EP2INWVALUE (USBD_BASE+0X1CC) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÖµ */ -#define USBD_EP2INWINDEX (USBD_BASE+0X1D0) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóË÷Òý */ -#define USBD_EP2INWLENGTH (USBD_BASE+0X1D4) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÓò³¤¶È */ -#define USBD_EP2INSYNCHFRAME (USBD_BASE+0X1D8) /* ¶Ëµã2ÊäÈëͬ²½°üÖ¡ºÅ */ -#define USBD_RXFIFO (USBD_BASE+0X200) /* ½ÓÊÜFIFO */ -#define USBD_TXFIFO (USBD_BASE+0X300) /* ·¢ËÍFIFO */ - - -/* - * GPIOÄ£¿é - * »ùÖ·: 0x1000F000 - */ - -#define GPIO_DBCLK_DIV (GPIO_BASE+0X000) /* ȥë´Ì²ÉÓÃʱÖÓ·ÖƵ±ÈÅäÖüĴæÆ÷ */ -#define GPIO_PORTA_DIR (GPIO_BASE+0X004) /* A×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ -#define GPIO_PORTA_SEL (GPIO_BASE+0X008) /* A×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ -#define GPIO_PORTA_INCTL (GPIO_BASE+0X00C) /* A×é¶Ë¿ÚͨÓÃÓÃ;ÊäÈëʱÀàÐÍÅäÖüĴæÆ÷ */ -#define GPIO_PORTA_INTRCTL (GPIO_BASE+0X010) /* A×é¶Ë¿ÚÖжϴ¥·¢ÀàÐÍÅäÖüĴæÆ÷ */ -#define GPIO_PORTA_INTRCLR (GPIO_BASE+0X014) /* A×é¶Ë¿ÚͨÓÃÓÃ;ÖжÏÇå³ýÅäÖüĴæÆ÷ */ -#define GPIO_PORTA_DATA (GPIO_BASE+0X018) /* A×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ -#define GPIO_PORTB_DIR (GPIO_BASE+0X01C) /* B×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ -#define GPIO_PORTB_SEL (GPIO_BASE+0X020) /* B×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ -#define GPIO_PORTB_DATA (GPIO_BASE+0X024) /* B×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ -#define GPIO_PORTC_DIR (GPIO_BASE+0X028) /* C×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ -#define GPIO_PORTC_SEL (GPIO_BASE+0X02C) /* C×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ -#define GPIO_PORTC_DATA (GPIO_BASE+0X030) /* C×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ -#define GPIO_PORTD_DIR (GPIO_BASE+0X034) /* D×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ -#define GPIO_PORTD_SEL (GPIO_BASE+0X038) /* D×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ -#define GPIO_PORTD_SPECII (GPIO_BASE+0X03C) /* D×é¶Ë¿ÚרÓÃÓÃ;2Ñ¡ÔñÅäÖüĴæÆ÷ */ -#define GPIO_PORTD_DATA (GPIO_BASE+0X040) /* D×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ -#define GPIO_PORTE_DIR (GPIO_BASE+0X044) /* E×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ -#define GPIO_PORTE_SEL (GPIO_BASE+0X048) /* E×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ -#define GPIO_PORTE_DATA (GPIO_BASE+0X04C) /* E×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ -#define GPIO_PORTF_DIR (GPIO_BASE+0X050) /* F×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ -#define GPIO_PORTF_SEL (GPIO_BASE+0X054) /* F×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ -#define GPIO_PORTF_INCTL (GPIO_BASE+0X058) /* F×é¶Ë¿ÚͨÓÃÓÃ;ÊäÈëʱÀàÐÍÅäÖüĴæÆ÷ */ -#define GPIO_PORTF_INTRCTL (GPIO_BASE+0X05C) /* F×é¶Ë¿ÚÖжϴ¥·¢ÀàÐÍÅäÖüĴæÆ÷ */ -#define GPIO_PORTF_INTRCLR (GPIO_BASE+0X060) /* F×é¶Ë¿ÚͨÓÃÓÃ;ÖжÏÇå³ýÅäÖüĴæÆ÷ */ -#define GPIO_PORTF_DATA (GPIO_BASE+0X064) /* F×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ -#define GPIO_PORTG_DIR (GPIO_BASE+0X068) /* G×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ -#define GPIO_PORTG_SEL (GPIO_BASE+0X06C) /* G×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ -#define GPIO_PORTG_DATA (GPIO_BASE+0X070) /* G×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ -#define GPIO_PORTH_DIR (GPIO_BASE+0X07C) /* H×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ -#define GPIO_PORTH_SEL (GPIO_BASE+0X078) /* H×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ -#define GPIO_PORTH_DATA (GPIO_BASE+0X07C) /* H×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ -#define GPIO_PORTI_DIR (GPIO_BASE+0X080) /* I×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ -#define GPIO_PORTI_SEL (GPIO_BASE+0X084) /* I×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ -#define GPIO_PORTI_DATA (GPIO_BASE+0X088) /* I×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ - - - -/* - * EMIÄ£¿é - * »ùÖ·: 0x11000000 - */ - -#define EMI_CSACONF (EMI_BASE+0X000) /* CSA²ÎÊýÅäÖüĴæÆ÷ */ -#define EMI_CSBCONF (EMI_BASE+0X004) /* CSB²ÎÊýÅäÖüĴæÆ÷ */ -#define EMI_CSCCONF (EMI_BASE+0X008) /* CSC²ÎÊýÅäÖüĴæÆ÷ */ -#define EMI_CSDCONF (EMI_BASE+0X00C) /* CSD²ÎÊýÅäÖüĴæÆ÷ */ -#define EMI_CSECONF (EMI_BASE+0X010) /* CSE²ÎÊýÅäÖüĴæÆ÷ */ -#define EMI_CSFCONF (EMI_BASE+0X014) /* CSF²ÎÊýÅäÖüĴæÆ÷ */ -#define EMI_SDCONF1 (EMI_BASE+0X018) /* SDRAMʱÐòÅäÖüĴæÆ÷1 */ -#define EMI_SDCONF2 (EMI_BASE+0X01C) /* SDRAMʱÐòÅäÖüĴæÆ÷2, SDRAM³õʼ»¯Óõ½µÄÅäÖÃÐÅÏ¢ */ -#define EMI_REMAPCONF (EMI_BASE+0X020) /* Ƭѡ¿Õ¼ä¼°µØÖ·Ó³ÉäREMAPÅäÖüĴæÆ÷ */ -#define EMI_NAND_ADDR1 (EMI_BASE+0X100) /* NAND FLASHµÄµØÖ·¼Ä´æÆ÷1 */ -#define EMI_NAND_COM (EMI_BASE+0X104) /* NAND FLASHµÄ¿ØÖÆ×ּĴæÆ÷ */ -#define EMI_NAND_STA (EMI_BASE+0X10C) /* NAND FLASHµÄ״̬¼Ä´æÆ÷ */ -#define EMI_ERR_ADDR1 (EMI_BASE+0X110) /* ¶Á²Ù×÷³ö´íµÄµØÖ·¼Ä´æÆ÷1 */ -#define EMI_ERR_ADDR2 (EMI_BASE+0X114) /* ¶Á²Ù×÷³ö´íµÄµØÖ·¼Ä´æÆ÷2 */ -#define EMI_NAND_CONF1 (EMI_BASE+0X118) /* NAND FLASHµÄÅäÖÃÆ÷´æÆ÷1 */ -#define EMI_NAND_INTR (EMI_BASE+0X11C) /* NAND FLASHÖжϼĴæÆ÷ */ -#define EMI_NAND_ECC (EMI_BASE+0X120) /* ECCУÑéÍê³É¼Ä´æÆ÷ */ -#define EMI_NAND_IDLE (EMI_BASE+0X124) /* NAND FLASH¿ÕÏмĴæÆ÷ */ -#define EMI_NAND_CONF2 (EMI_BASE+0X128) /* NAND FLASHµÄÅäÖÃÆ÷´æÆ÷2 */ -#define EMI_NAND_ADDR2 (EMI_BASE+0X12C) /* NAND FLASHµÄµØÖ·¼Ä´æÆ÷2 */ -#define EMI_NAND_DATA (EMI_BASE+0X200) /* NAND FLASHµÄÊý¾Ý¼Ä´æÆ÷ */ - - -/* - * DMACÄ£¿é - * »ùÖ·: 0x11001000 - */ - -#define DMAC_INTSTATUS (DMAC_BASE+0X020) /* DAMCÖжÏ״̬¼Ä´æÆ÷¡£ */ -#define DMAC_INTTCSTATUS (DMAC_BASE+0X050) /* DMAC´«ÊäÍê³ÉÖжÏ״̬¼Ä´æÆ÷ */ -#define DMAC_INTTCCLEAR (DMAC_BASE+0X060) /* DMAC´«ÊäÍê³ÉÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define DMAC_INTERRORSTATUS (DMAC_BASE+0X080) /* DMAC´«Êä´íÎóÖжÏ״̬¼Ä´æÆ÷ */ -#define DMAC_INTINTERRCLR (DMAC_BASE+0X090) /* DMAC´«Êä´íÎóÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ -#define DMAC_ENBLDCHNS (DMAC_BASE+0X0B0) /* DMACͨµÀʹÄÜ״̬¼Ä´æÆ÷ */ -#define DMAC_C0SRCADDR (DMAC_BASE+0X000) /* DMACµÀ0Ô´µØÖ·¼Ä´æÆ÷ */ -#define DMAC_C0DESTADD (DMAC_BASE+0X004) /* DMACµÀ0Ä¿µÄµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C0CONTROL (DMAC_BASE+0X00C) /* DMACµÀ0¿ØÖƼĴæÆ÷ */ -#define DMAC_C0CONFIGURATION (DMAC_BASE+0X010) /* DMACµÀ0ÅäÖüĴæÆ÷ */ -#define DMAC_C0DESCRIPTOR (DMAC_BASE+0X01C) /* DMACµÀ0Á´±íµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C1SRCADDR (DMAC_BASE+0X100) /* DMACµÀ1Ô´µØÖ·¼Ä´æÆ÷ */ -#define DMAC_C1DESTADDR (DMAC_BASE+0X104) /* DMACµÀ1Ä¿µÄµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C1CONTROL (DMAC_BASE+0X10C) /* DMACµÀ1¿ØÖƼĴæÆ÷ */ -#define DMAC_C1CONFIGURATION (DMAC_BASE+0X110) /* DMACµÀ1ÅäÖüĴæÆ÷ */ -#define DMAC_C1DESCRIPTOR (DMAC_BASE+0X114) /* DMACµÀ1Á´±íµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C2SRCADDR (DMAC_BASE+0X200) /* DMACµÀ2Ô´µØÖ·¼Ä´æÆ÷ */ -#define DMAC_C2DESTADDR (DMAC_BASE+0X204) /* DMACµÀ2Ä¿µÄµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C2CONTROL (DMAC_BASE+0X20C) /* DMACµÀ2¿ØÖƼĴæÆ÷ */ -#define DMAC_C2CONFIGURATION (DMAC_BASE+0X210) /* DMACµÀ2ÅäÖüĴæÆ÷ */ -#define DMAC_C2DESCRIPTOR (DMAC_BASE+0X214) /* DMACµÀ2Á´±íµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C3SRCADDR (DMAC_BASE+0X300) /* DMACµÀ3Ô´µØÖ·¼Ä´æÆ÷ */ -#define DMAC_C3DESTADDR (DMAC_BASE+0X304) /* DMACµÀ3Ä¿µÄµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C3CONTROL (DMAC_BASE+0X30C) /* DMACµÀ3¿ØÖƼĴæÆ÷ */ -#define DMAC_C3CONFIGURATION (DMAC_BASE+0X310) /* DMACµÀ3ÅäÖüĴæÆ÷ */ -#define DMAC_C3DESCRIPTOR (DMAC_BASE+0X314) /* DMACµÀ3Á´±íµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C4SRCADDR (DMAC_BASE+0X400) /* DMACµÀ4Ô´µØÖ·¼Ä´æÆ÷ */ -#define DMAC_C4DESTADDR (DMAC_BASE+0X404) /* DMACµÀ4Ä¿µÄµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C4CONTROL (DMAC_BASE+0X40C) /* DMACµÀ4¿ØÖƼĴæÆ÷ */ -#define DMAC_C4CONFIGURATION (DMAC_BASE+0X410) /* DMACµÀ4ÅäÖüĴæÆ÷ */ -#define DMAC_C4DESCRIPTOR (DMAC_BASE+0X414) /* DMACµÀ4Á´±íµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C5SRCADDR (DMAC_BASE+0X500) /* DMACµÀ5Ô´µØÖ·¼Ä´æÆ÷ */ -#define DMAC_C5DESTADDR (DMAC_BASE+0X504) /* DMACµÀ5Ä¿µÄµØÖ·¼Ä´æÆ÷ */ -#define DMAC_C5CONTROL (DMAC_BASE+0X50C) /* DMACµÀ5¿ØÖƼĴæÆ÷ */ -#define DMAC_C5CONFIGURATION (DMAC_BASE+0X510) /* DMACµÀ5ÅäÖüĴæÆ÷ */ -#define DMAC_C5DESCRIPTOR (DMAC_BASE+0X514) /* DMACµÀ5Á´±íµØÖ·¼Ä´æÆ÷ */ - - -/* - * LCDCÄ£¿é - * »ùÖ·: 0x11002000 - */ - -#define LCDC_SSA (LCDC_BASE+0X000) /* ÆÁÄ»ÆðʼµØÖ·¼Ä´æÆ÷ */ -#define LCDC_SIZE (LCDC_BASE+0X004) /* ÆÁÄ»³ß´ç¼Ä´æÆ÷ */ -#define LCDC_PCR (LCDC_BASE+0X008) /* Ãæ°åÅäÖüĴæÆ÷ */ -#define LCDC_HCR (LCDC_BASE+0X00C) /* ˮƽÅäÖüĴæÆ÷ */ -#define LCDC_VCR (LCDC_BASE+0X010) /* ´¹Ö±ÅäÖüĴæÆ÷ */ -#define LCDC_PWMR (LCDC_BASE+0X014) /* PWM¶Ô±È¶È¿ØÖƼĴæÆ÷ */ -#define LCDC_LECR (LCDC_BASE+0X018) /* ʹÄÜ¿ØÖƼĴæÆ÷ */ -#define LCDC_DMACR (LCDC_BASE+0X01C) /* DMA¿ØÖƼĴæÆ÷ */ -#define LCDC_LCDISREN (LCDC_BASE+0X020) /* ÖжÏʹÄܼĴæÆ÷ */ -#define LCDC_LCDISR (LCDC_BASE+0X024) /* ÖжÏ״̬¼Ä´æÆ÷ */ -#define LCDC_LGPMR (LCDC_BASE+0X040) /* »Ò¶Èµ÷É«Ó³Éä¼Ä´æÆ÷×é (16¸ö32bit¼Ä´æÆ÷) */ - - -/* - * MACÄ£¿é - * »ùÖ·: 0x11003000 - */ - -#define MAC_CTRL (MAC_BASE+0X000) /* MAC¿ØÖƼĴæÆ÷ */ -#define MAC_INTSRC (MAC_BASE+0X004) /* MACÖжÏÔ´¼Ä´æÆ÷ */ -#define MAC_INTMASK (MAC_BASE+0X008) /* MACÖжÏÆÁ±Î¼Ä´æÆ÷ */ -#define MAC_IPGT (MAC_BASE+0X00C) /* Á¬ÐøÖ¡¼ä¸ô¼Ä´æÆ÷ */ -#define MAC_IPGR1 (MAC_BASE+0X010) /* µÈ´ý´°¿Ú¼Ä´æÆ÷ */ -#define MAC_IPGR2 (MAC_BASE+0X014) /* µÈ´ý´°¿Ú¼Ä´æÆ÷ */ -#define MAC_PACKETLEN (MAC_BASE+0X018) /* Ö¡³¤¶È¼Ä´æÆ÷ */ -#define MAC_COLLCONF (MAC_BASE+0X01C) /* ÅöײÖØ·¢¼Ä´æÆ÷ */ -#define MAC_TXBD_NUM (MAC_BASE+0X020) /* ·¢ËÍÃèÊö·û¼Ä´æÆ÷ */ -#define MAC_FLOWCTRL (MAC_BASE+0X024) /* Á÷¿Ø¼Ä´æÆ÷ */ -#define MAC_MII_CTRL (MAC_BASE+0X028) /* PHY¿ØÖƼĴæÆ÷ */ -#define MAC_MII_CMD (MAC_BASE+0X02C) /* PHYÃüÁî¼Ä´æÆ÷ */ -#define MAC_MII_ADDRESS (MAC_BASE+0X030) /* PHYµØÖ·¼Ä´æÆ÷ */ -#define MAC_MII_TXDATA (MAC_BASE+0X034) /* PHYдÊý¾Ý¼Ä´æÆ÷ */ -#define MAC_MII_RXDATA (MAC_BASE+0X038) /* PHY¶ÁÊý¾Ý¼Ä´æÆ÷ */ -#define MAC_MII_STATUS (MAC_BASE+0X03C) /* PHY״̬¼Ä´æÆ÷ */ -#define MAC_ADDR0 (MAC_BASE+0X040) /* MACµØÖ·¼Ä´æÆ÷ */ -#define MAC_ADDR1 (MAC_BASE+0X044) /* MACµØÖ·¼Ä´æÆ÷ */ -#define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH¼Ä´æÆ÷ */ -#define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH¼Ä´æÆ÷ */ -#define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC¿ØÖÆÖ¡¼Ä´æÆ÷ */ -#define MAC_TX_BD (MAC_BASE+0X400) -#define MAC_RX_BD (MAC_BASE+0X600) - - -/* - ************************************** - * Error Codes: - * IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE, - * parameter error return (-33)/E_PAR, - * hardware error reture (-99)/E_HA - ************************************** - */ - -#define E_OK 0 /* Normal completion */ -#define E_SYS (-5) /* System error */ -#define E_NOMEM (-10) /* Insufficient memory */ -#define E_NOSPT (-17) /* Feature not supported */ -#define E_INOSPT (-18) /* Feature not supported by ITRON/FILE specification */ -#define E_RSFN (-20) /* Reserved function code number */ -#define E_RSATR (-24) /* Reserved attribute */ -#define E_PAR (-33) /* Parameter error */ -#define E_ID (-35) /* Invalid ID number */ -#define E_NOEXS (-52) /* Object does not exist */ -#define E_OBJ (-63) /* Invalid object state */ -#define E_MACV (-65) /* Memory access disabled or memory access violation */ -#define E_OACV (-66) /* Object access violation */ -#define E_CTX (-69) /* Context error */ -#define E_QOVR (-73) /* Queuing or nesting overflow */ -#define E_DLT (-81) /* Object being waited for was deleted */ -#define E_TMOUT (-85) /* Polling failure or timeout exceeded */ -#define E_RLWAI (-86) /* WAIT state was forcibly released */ - -#define E_HA (-99) /* HARD WARE ERROR */ - - -/* - ************************************** - * PMU Ä£¿éʱÖÓ - ************************************** - */ - -#define CLK_SGPT (1 << 16) -#define CLK_SI2S (1 << 15) -#define CLK_SSMC (1 << 14) -#define CLK_SMAC (1 << 13) -#define CLK_SUSB (1 << 12) -#define CLK_SUART3 (1 << 11) -#define CLK_SUART2 (1 << 10) -#define CLK_SUART1 (1 << 9) -#define CLK_SUART0 (1 << 8) -#define CLK_SSSI (1 << 7) -#define CLK_SAC97 (1 << 6) -#define CLK_SMMCSD (1 << 5) -#define CLK_SEMI (1 << 4) -#define CLK_SDMAC (1 << 3) -#define CLK_SPWM (1 << 2) -#define CLK_SLCDC (1 << 1) -#define CLK_SESRAM (1) - - -/*Interrupt Sources*/ - - -#define INTSRC_RTC 31 -#define INTSRC_DMAC 30 -#define INTSRC_EMI 29 -#define INTSRC_MAC 28 -#define INTSRC_TIMER1 27 -#define INTSRC_TIMER2 26 -#define INTSRC_TIMER3 25 -#define INTSRC_UART0 24 -#define INTSRC_UART1 23 -#define INTSRC_UART2 22 -#define INTSRC_UART3 21 -#define INTSRC_PWM 20 -#define INTSRC_LCDC 19 -#define INTSRC_I2S 18 -#define INTSRC_SSI 17 - -#define INTSRC_USB 15 -#define INTSRC_SMC0 14 -#define INTSRC_SMC1 13 -#define INTSRC_SDIO 12 -#define INTSRC_EXINT10 11 -#define INTSRC_EXINT9 10 -#define INTSRC_EXINT8 9 -#define INTSRC_EXINT7 8 -#define INTSRC_EXINT6 7 -#define INTSRC_EXINT5 6 -#define INTSRC_EXINT4 5 -#define INTSRC_EXINT3 4 -#define INTSRC_EXINT2 3 -#define INTSRC_EXINT1 2 -#define INTSRC_EXINT0 1 -#define INTSRC_NULL 0 - - -/*Sereral useful macros*/ -#define set_plevel(plevel) *(RP)INTC_IPLR = plevel //ÉèÖÃÆÕͨÖжϵÄÓÅÏȼ¶ÃÅÏÞ£¬Ö»ÓÐÓÅÏȼ¶´óÓÚ´ËÖµµÄÖжϲÅÄÜͨ¹ý -#define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //ÖÃ1ºó£¬Èí¼þÇ¿ÖƸÃλ¶ÔÓ¦µÄÖжÏÔ´·¢³öÖжÏÐźŠ-#define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //ÖÃ1ºó£¬ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ-#define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //ÖÃ0ºó£¬²»ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ-#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //ÖÃ1ºó£¬ÆÁ±Î¶ÔÓ¦µÄIRQ ÖжÏÐźŠ-#define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //ÖÃ0ºó£¬Í¨¹ý¶ÔÓ¦µÄIRQ ÖжÏÐźŠ-#define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //ÆÁ±Î¶ÔÓ¦µÄIRQ ÖжÏÐźŠ-#define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //ͨ¹ý¶ÔÓ¦µÄIRQ ÖжÏÐźŠ-#define enable_all_irq() *(RP)INTC_IER = 0XFFFFFFFF //ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ-#define disable_all_irq() *(RP)INTC_IER = 0X00000000 //²»ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ-#define InitInt() do{mask_all_irq(); enable_all_irq();}while(0) - -/* - ************************************** - * ËùÓгÌÐòÖÐÓõ½µÄTypedef - ************************************** - */ - -typedef char S8; /* signed 8-bit integer */ -typedef short S16; /* signed 16-bit integer */ -typedef long S32; /* signed 32-bit integer */ -typedef unsigned char U8; /* unsigned 8-bit integer */ -typedef unsigned short U16; /* unsigned 16-bit integer */ -typedef unsigned long U32; /* unsigned 32-bit integer */ - -typedef volatile U32 * RP; -typedef volatile U16 * RP16; -typedef volatile U8 * RP8; - -typedef void *VP; /* pointer to an unpredictable data type */ -typedef void (*FP)(); /* program start address */ - -#ifndef _BOOL_TYPE_ -#define _BOOL_TYPE_ -typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ -#endif - -typedef int ER; /* Error code. A signed integer. */ - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#define __I volatile const /*!< defines 'read only' permissions */ -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ -#define __iomem volatile - - -/*Macros for debug*/ - -#define EOUT(fmt,...) \ - do \ - { \ - rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) - -#define RT_DEBUG -#ifdef RT_DEBUG - #define DBOUT(fmt,...) \ - do \ - { \ - rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) -#else - #define DBOUT(fmt,...) \ - do{}while(0) -#endif - -#ifdef RT_DEBUG - #define ASSERT(arg) \ - if((arg) == 0) \ - { \ - while(1) \ - { \ - rt_kprintf("have a assert failure\n"); \ - } \ - } -#else - #define ASSERT(arg) \ - do \ - { \ - }while(0) -#endif - - -#define write_reg(reg,value) \ - do \ - { \ - *(RP)(reg) = value; \ - }while(0) - -#define read_reg(reg) (*(RP)reg) - - -struct rt_hw_register -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; -}; - - -/*@}*/ - -#endif +#ifndef __SEP4020_H +#define __SEP4020_H + +#include + +/*Core definations*/ +#define SVCMODE +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F + + + +/* + * ¸÷Ä£¿é¼Ä´æÆ÷»ùÖµ + */ + +#define ESRAM_BASE 0x04000000 +#define INTC_BASE 0x10000000 +#define PMU_BASE 0x10001000 +#define RTC_BASE 0x10002000 +#define WD_BASE 0x10002000 +#define TIMER_BASE 0x10003000 +#define PWM_BASE 0x10004000 +#define UART0_BASE 0X10005000 +#define UART1_BASE 0X10006000 +#define UART2_BASE 0X10007000 +#define UART3_BASE 0X10008000 +#define SSI_BASE 0X10009000 +#define I2S_BASE 0x1000A000 +#define MMC_BASE 0x1000B000 +#define SD_BASE 0x1000B000 +#define SMC0_BASE 0x1000C000 +#define SMC1_BASE 0x1000D000 +#define USBD_BASE 0x1000E000 +#define GPIO_BASE 0x1000F000 +#define EMI_BASE 0x11000000 +#define DMAC_BASE 0x11001000 +#define LCDC_BASE 0x11002000 +#define MAC_BASE 0x11003000 +#define AMBA_BASE 0x11005000 + + +/* + * INTCÄ£¿é + * »ùÖ·: 0x10000000 + */ + +#define INTC_IER (INTC_BASE+0X000) /* IRQÖжÏÔÊÐí¼Ä´æÆ÷ */ +#define INTC_IMR (INTC_BASE+0X008) /* IRQÖжÏÆÁ±Î¼Ä´æÆ÷ */ +#define INTC_IFR (INTC_BASE+0X010) /* IRQÈí¼þÇ¿ÖÆÖжϼĴæÆ÷ */ +#define INTC_IRSR (INTC_BASE+0X018) /* IRQδ´¦ÀíÖжÏ״̬¼Ä´æÆ÷ */ +#define INTC_ISR (INTC_BASE+0X020) /* IRQÖжÏ״̬¼Ä´æÆ÷ */ +#define INTC_IMSR (INTC_BASE+0X028) /* IRQÆÁ±ÎÖжÏ״̬¼Ä´æÆ÷ */ +#define INTC_IFSR (INTC_BASE+0X030) /* IRQÖжÏ×îÖÕ״̬¼Ä´æÆ÷ */ +#define INTC_FIER (INTC_BASE+0X0C0) /* FIQÖжÏÔÊÐí¼Ä´æÆ÷ */ +#define INTC_FIMR (INTC_BASE+0X0C4) /* FIQÖжÏÆÁ±Î¼Ä´æÆ÷ */ +#define INTC_FIFR (INTC_BASE+0X0C8) /* FIQÈí¼þÇ¿ÖÆÖжϼĴæÆ÷ */ +#define INTC_FIRSR (INTC_BASE+0X0CC) /* FIQδ´¦ÀíÖжÏ״̬¼Ä´æÆ÷ */ +#define INTC_FISR (INTC_BASE+0X0D0) /* FIQÖжÏ״̬¼Ä´æÆ÷ */ +#define INTC_FIFSR (INTC_BASE+0X0D4) /* FIQÖжÏ×îÖÕ״̬¼Ä´æÆ÷ */ +#define INTC_IPLR (INTC_BASE+0X0D8) /* IRQÖжÏÓÅÏȼ¶¼Ä´æÆ÷ */ +#define INTC_ICR1 (INTC_BASE+0X0DC) /* IRQÄÚ²¿ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 */ +#define INTC_ICR2 (INTC_BASE+0X0E0) /* IRQÄÚ²¿ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷2 */ +#define INTC_EXICR1 (INTC_BASE+0X0E4) /* IRQÍⲿÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 */ +#define INTC_EXICR2 (INTC_BASE+0X0E8) /* IRQÍⲿÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷2 */ + + +/* + * PMUÄ£¿é + * »ùÖ·: 0x10001000 + */ + +#define PMU_PLTR (PMU_BASE+0X000) /* PLLµÄÎȶ¨¹ý¶Éʱ¼ä */ +#define PMU_PMCR (PMU_BASE+0X004) /* ϵͳÖ÷ʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ */ +#define PMU_PUCR (PMU_BASE+0X008) /* USBʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ */ +#define PMU_PCSR (PMU_BASE+0X00C) /* ÄÚ²¿Ä£¿éʱÖÓÔ´¹©¸øµÄ¿ØÖƼĴæÆ÷ */ +#define PMU_PDSLOW (PMU_BASE+0X010) /* SLOW״̬ÏÂʱÖӵķÖƵÒò×Ó */ +#define PMU_PMDR (PMU_BASE+0X014) /* оƬ¹¤×÷ģʽ¼Ä´æÆ÷ */ +#define PMU_RCTR (PMU_BASE+0X018) /* Reset¿ØÖƼĴæÆ÷ */ +#define PMU_CLRWAKUP (PMU_BASE+0X01C) /* WakeUpÇå³ý¼Ä´æÆ÷ */ + + +/* + * RTCÄ£¿é + * »ùÖ·: 0x10002000 + */ + +#define RTC_STA_YMD (RTC_BASE+0X000) /* Äê, ÔÂ, ÈÕ¼ÆÊý¼Ä´æÆ÷ */ +#define RTC_STA_HMS (RTC_BASE+0X004) /* Сʱ, ·ÖÖÓ, Ãë¼Ä´æÆ÷ */ +#define RTC_ALARM_ALL (RTC_BASE+0X008) /* ¶¨Ê±ÔÂ, ÈÕ, ʱ, ·Ö¼Ä´æÆ÷ */ +#define RTC_CTR (RTC_BASE+0X00C) /* ¿ØÖƼĴæÆ÷ */ +#define RTC_INT_EN (RTC_BASE+0X010) /* ÖжÏʹÄܼĴæÆ÷ */ +#define RTC_INT_STS (RTC_BASE+0X014) /* ÖжÏ״̬¼Ä´æÆ÷ */ +#define RTC_SAMP (RTC_BASE+0X018) /* ²ÉÑùÖÜÆڼĴæÆ÷ */ +#define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog·þÎñ¼Ä´æÆ÷ */ +#define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* ÅäÖÃʱ¼äÈ·ÈϼĴæÆ÷ (ÔÚÅäÖÃʱ¼ä֮ǰÏÈд0xaaaaaaaa) */ +#define RTC_KEY0 (RTC_BASE+0X02C) /* ÃÜÔ¿¼Ä´æÆ÷ */ + +/* + * TIMERÄ£¿é + * »ùÖ·: 0x10003000 + */ + +#define TIMER_T1LCR (TIMER_BASE+0X000) /* ͨµÀ1¼ÓÔؼÆÊý¼Ä´æÆ÷ */ +#define TIMER_T1CCR (TIMER_BASE+0X004) /* ͨµÀ1µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define TIMER_T1CR (TIMER_BASE+0X008) /* ͨµÀ1¿ØÖƼĴæÆ÷ */ +#define TIMER_T1ISCR (TIMER_BASE+0X00C) /* ͨµÀ1ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_T1IMSR (TIMER_BASE+0X010) /* ͨµÀ1ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_T2LCR (TIMER_BASE+0X020) /* ͨµÀ2¼ÓÔؼÆÊý¼Ä´æÆ÷ */ +#define TIMER_T2CCR (TIMER_BASE+0X024) /* ͨµÀ2µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define TIMER_T2CR (TIMER_BASE+0X028) /* ͨµÀ2¿ØÖƼĴæÆ÷ */ +#define TIMER_T2ISCR (TIMER_BASE+0X02C) /* ͨµÀ2ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_T2IMSR (TIMER_BASE+0X030) /* ͨµÀ2ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_T3LCR (TIMER_BASE+0X040) /* ͨµÀ3¼ÓÔؼÆÊý¼Ä´æÆ÷ */ +#define TIMER_T3CCR (TIMER_BASE+0X044) /* ͨµÀ3µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define TIMER_T3CR (TIMER_BASE+0X048) /* ͨµÀ3¿ØÖƼĴæÆ÷ */ +#define TIMER_T3ISCR (TIMER_BASE+0X04C) /* ͨµÀ3ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_T3IMSR (TIMER_BASE+0X050) /* ͨµÀ3ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_T3CAPR (TIMER_BASE+0X054) /* ͨµÀ3²¶»ñ¼Ä´æÆ÷ */ +#define TIMER_T4LCR (TIMER_BASE+0X060) /* ͨµÀ4¼ÓÔؼÆÊý¼Ä´æÆ÷ */ +#define TIMER_T4CCR (TIMER_BASE+0X064) /* ͨµÀ4µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define TIMER_T4CR (TIMER_BASE+0X068) /* ͨµÀ4¿ØÖƼĴæÆ÷ */ +#define TIMER_T4ISCR (TIMER_BASE+0X06C) /* ͨµÀ4ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_T4IMSR (TIMER_BASE+0X070) /* ͨµÀ4ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_T4CAPR (TIMER_BASE+0X074) /* ͨµÀ4²¶»ñ¼Ä´æÆ÷ */ +#define TIMER_T5LCR (TIMER_BASE+0X080) /* ͨµÀ5¼ÓÔؼÆÊý¼Ä´æÆ÷ */ +#define TIMER_T5CCR (TIMER_BASE+0X084) /* ͨµÀ5µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define TIMER_T5CR (TIMER_BASE+0X088) /* ͨµÀ5¿ØÖƼĴæÆ÷ */ +#define TIMER_T5ISCR (TIMER_BASE+0X08C) /* ͨµÀ5ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_T5IMSR (TIMER_BASE+0X090) /* ͨµÀ5ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_T5CAPR (TIMER_BASE+0X094) /* ͨµÀ5²¶»ñ¼Ä´æÆ÷ */ +#define TIMER_T6LCR (TIMER_BASE+0X0A0) /* ͨµÀ6¼ÓÔؼÆÊý¼Ä´æÆ÷ */ +#define TIMER_T6CCR (TIMER_BASE+0X0A4) /* ͨµÀ6µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define TIMER_T6CR (TIMER_BASE+0X0A8) /* ͨµÀ6¿ØÖƼĴæÆ÷ */ +#define TIMER_T6ISCR (TIMER_BASE+0X0AC) /* ͨµÀ6ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_T6IMSR (TIMER_BASE+0X0B0) /* ͨµÀ6ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_T6CAPR (TIMER_BASE+0X0B4) /* ͨµÀ6²¶»ñ¼Ä´æÆ÷ */ +#define TIMER_T7LCR (TIMER_BASE+0X0C0) /* ͨµÀ7¼ÓÔؼÆÊý¼Ä´æÆ÷ */ +#define TIMER_T7CCR (TIMER_BASE+0X0C4) /* ͨµÀ7µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define TIMER_T7CR (TIMER_BASE+0X0C8) /* ͨµÀ7¿ØÖƼĴæÆ÷ */ +#define TIMER_T7ISCR (TIMER_BASE+0X0CC) /* ͨµÀ7ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_T7IMSR (TIMER_BASE+0X0D0) /* ͨµÀ7ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_T8LCR (TIMER_BASE+0X0E0) /* ͨµÀ8¼ÓÔؼÆÊý¼Ä´æÆ÷ */ +#define TIMER_T8CCR (TIMER_BASE+0X0E4) /* ͨµÀ8µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define TIMER_T8CR (TIMER_BASE+0X0E8) /* ͨµÀ8¿ØÖƼĴæÆ÷ */ +#define TIMER_T8ISCR (TIMER_BASE+0X0EC) /* ͨµÀ8ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_T8IMSR (TIMER_BASE+0X0F0) /* ͨµÀ8ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_T9LCR (TIMER_BASE+0X100) /* ͨµÀ9¼ÓÔؼÆÊý¼Ä´æÆ÷ */ +#define TIMER_T9CCR (TIMER_BASE+0X104) /* ͨµÀ9µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define TIMER_T9CR (TIMER_BASE+0X108) /* ͨµÀ9¿ØÖƼĴæÆ÷ */ +#define TIMER_T9ISCR (TIMER_BASE+0X10C) /* ͨµÀ9ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_T9IMSR (TIMER_BASE+0X110) /* ͨµÀ9ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_T10LCR (TIMER_BASE+0X120) /* ͨµÀ10¼ÓÔؼÆÊý¼Ä´æÆ÷ */ +#define TIMER_T10CCR (TIMER_BASE+0X124) /* ͨµÀ10µ±Ç°¼ÆÊýÖµ¼Ä´æÆ÷ */ +#define TIMER_T10CR (TIMER_BASE+0X128) /* ͨµÀ10¿ØÖƼĴæÆ÷ */ +#define TIMER_T10ISCR (TIMER_BASE+0X12C) /* ͨµÀ10ÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_T10IMSR (TIMER_BASE+0X130) /* ͨµÀ10ÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_TIMSR (TIMER_BASE+0X140) /* TIMERÖжÏÆÁ±Î״̬¼Ä´æÆ÷ */ +#define TIMER_TISCR (TIMER_BASE+0X144) /* TIMERÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define TIMER_TISR (TIMER_BASE+0X148) /* TIMERÖжÏ״̬¼Ä´æÆ÷ */ + + + +/* + * PWMÄ£¿é + * »ùÖ·: 0x10004000 + */ + +#define PWM0_CTRL (PWM_BASE+0X000) /* PWM0¿ØÖƼĴæÆ÷ */ +#define PWM0_DIV (PWM_BASE+0X004) /* PWM0·ÖƵ¼Ä´æÆ÷ */ +#define PWM0_PERIOD (PWM_BASE+0X008) /* PWM0ÖÜÆڼĴæÆ÷ */ +#define PWM0_DATA (PWM_BASE+0X00C) /* PWM0Êý¾Ý¼Ä´æÆ÷ */ +#define PWM0_CNT (PWM_BASE+0X010) /* PWM0¼ÆÊý¼Ä´æÆ÷ */ +#define PWM0_STATUS (PWM_BASE+0X014) /* PWM0״̬¼Ä´æÆ÷ */ +#define PWM1_CTRL (PWM_BASE+0X020) /* PWM1¿ØÖƼĴæÆ÷ */ +#define PWM1_DIV (PWM_BASE+0X024) /* PWM1·ÖƵ¼Ä´æÆ÷ */ +#define PWM1_PERIOD (PWM_BASE+0X028) /* PWM1ÖÜÆڼĴæÆ÷ */ +#define PWM1_DATA (PWM_BASE+0X02C) /* PWM1Êý¾Ý¼Ä´æÆ÷ */ +#define PWM1_CNT (PWM_BASE+0X030) /* PWM1¼ÆÊý¼Ä´æÆ÷ */ +#define PWM1_STATUS (PWM_BASE+0X034) /* PWM1״̬¼Ä´æÆ÷ */ +#define PWM2_CTRL (PWM_BASE+0X040) /* PWM2¿ØÖƼĴæÆ÷ */ +#define PWM2_DIV (PWM_BASE+0X044) /* PWM2·ÖƵ¼Ä´æÆ÷ */ +#define PWM2_PERIOD (PWM_BASE+0X048) /* PWM2ÖÜÆڼĴæÆ÷ */ +#define PWM2_DATA (PWM_BASE+0X04C) /* PWM2Êý¾Ý¼Ä´æÆ÷ */ +#define PWM2_CNT (PWM_BASE+0X050) /* PWM2¼ÆÊý¼Ä´æÆ÷ */ +#define PWM2_STATUS (PWM_BASE+0X054) /* PWM2״̬¼Ä´æÆ÷ */ +#define PWM3_CTRL (PWM_BASE+0X060) /* PWM3¿ØÖƼĴæÆ÷ */ +#define PWM3_DIV (PWM_BASE+0X064) /* PWM3·ÖƵ¼Ä´æÆ÷ */ +#define PWM3_PERIOD (PWM_BASE+0X068) /* PWM3ÖÜÆڼĴæÆ÷ */ +#define PWM3_DATA (PWM_BASE+0X06C) /* PWM3Êý¾Ý¼Ä´æÆ÷ */ +#define PWM3_CNT (PWM_BASE+0X070) /* PWM3¼ÆÊý¼Ä´æÆ÷ */ +#define PWM3_STATUS (PWM_BASE+0X074) /* PWM3״̬¼Ä´æÆ÷ */ +#define PWM_INTMASK (PWM_BASE+0X080) /* PWMÖжÏÆÁ±Î¼Ä´æÆ÷ */ +#define PWM_INT (PWM_BASE+0X084) /* PWMÖжϼĴæÆ÷ */ +#define PWM_ENABLE (PWM_BASE+0X088) /* PWMʹÄܼĴæÆ÷ */ + + +/* + * UART0Ä£¿é + * »ùÖ·: 0x10005000 + */ + +#define UART0_DLBL (UART0_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ +#define UART0_RXFIFO (UART0_BASE+0X000) /* ½ÓÊÕFIFO */ +#define UART0_TXFIFO (UART0_BASE+0X000) /* ·¢ËÍFIFO */ +#define UART0_DLBH (UART0_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ +#define UART0_IER (UART0_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ +#define UART0_IIR (UART0_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ +#define UART0_FCR (UART0_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ +#define UART0_LCR (UART0_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ +#define UART0_MCR (UART0_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ +#define UART0_LSR (UART0_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ +#define UART0_MSR (UART0_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ + + +/* + * UART1Ä£¿é + * »ùÖ·: 0x10006000 + */ + +#define UART1_DLBL (UART1_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ +#define UART1_RXFIFO (UART1_BASE+0X000) /* ½ÓÊÕFIFO */ +#define UART1_TXFIFO (UART1_BASE+0X000) /* ·¢ËÍFIFO */ +#define UART1_DLBH (UART1_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ +#define UART1_IER (UART1_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ +#define UART1_IIR (UART1_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ +#define UART1_FCR (UART1_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ +#define UART1_LCR (UART1_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ +#define UART1_MCR (UART1_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ +#define UART1_LSR (UART1_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ +#define UART1_MSR (UART1_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ + + +/* + * UART2Ä£¿é + * »ùÖ·: 0x10007000 + */ + +#define UART2_DLBL (UART2_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ +#define UART2_RXFIFO (UART2_BASE+0X000) /* ½ÓÊÕFIFO */ +#define UART2_TXFIFO (UART2_BASE+0X000) /* ·¢ËÍFIFO */ +#define UART2_DLBH (UART2_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ +#define UART2_IER (UART2_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ +#define UART2_IIR (UART2_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ +#define UART2_FCR (UART2_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ +#define UART2_LCR (UART2_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ +#define UART2_MCR (UART2_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ +#define UART2_LSR (UART2_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ +#define UART2_MSR (UART2_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ + + +/* + * UART3Ä£¿é + * »ùÖ·: 0x10008000 + */ + +#define UART3_DLBL (UART3_BASE+0X000) /* ²¨ÌØÂÊÉèÖõͰËλ¼Ä´æÆ÷ */ +#define UART3_RXFIFO (UART3_BASE+0X000) /* ½ÓÊÕFIFO */ +#define UART3_TXFIFO (UART3_BASE+0X000) /* ·¢ËÍFIFO */ +#define UART3_DLBH (UART3_BASE+0X004) /* ²¨ÌØÂÊÉèÖø߰Ëλ¼Ä´æÆ÷ */ +#define UART3_IER (UART3_BASE+0X004) /* ÖжÏʹÄܼĴæÆ÷ */ +#define UART3_IIR (UART3_BASE+0X008) /* ÖжÏʶ±ð¼Ä´æÆ÷ */ +#define UART3_FCR (UART3_BASE+0X008) /* FIFO¿ØÖƼĴæÆ÷ */ +#define UART3_LCR (UART3_BASE+0X00C) /* ÐпØÖƼĴæÆ÷ */ +#define UART3_MCR (UART3_BASE+0X010) /* Modem¿ØÖƼĴæÆ÷ */ +#define UART3_LSR (UART3_BASE+0X014) /* ÐÐ״̬¼Ä´æÆ÷ */ +#define UART3_MSR (UART3_BASE+0X018) /* Modem״̬¼Ä´æÆ÷ */ + + +/* + * SSIÄ£¿é + * »ùÖ·: 0x10009000 + */ + +#define SSI_CONTROL0 (SSI_BASE+0X000) /* ¿ØÖƼĴæÆ÷0 */ +#define SSI_CONTROL1 (SSI_BASE+0X004) /* ¿ØÖƼĴæÆ÷1 */ +#define SSI_SSIENR (SSI_BASE+0X008) /* SSIʹÄܼĴæÆ÷ */ +#define SSI_MWCR (SSI_BASE+0X00C) /* Microwire¿ØÖƼĴæÆ÷ */ +#define SSI_SER (SSI_BASE+0X010) /* ´ÓÉ豸ʹÄܼĴæÆ÷ */ +#define SSI_BAUDR (SSI_BASE+0X014) /* ²¨ÌØÂÊÉèÖüĴæÆ÷ */ +#define SSI_TXFTLR (SSI_BASE+0X018) /* ·¢ËÍFIFOãÐÖµ¼Ä´æÆ÷ */ +#define SSI_RXFTLR (SSI_BASE+0X01C) /* ½ÓÊÕFIFOãÐÖµ¼Ä´æÆ÷ */ +#define SSI_TXFLR (SSI_BASE+0X020) /* ·¢ËÍFIFO״̬¼Ä´æÆ÷ */ +#define SSI_RXFLR (SSI_BASE+0X024) /* ½ÓÊÕFIFO״̬¼Ä´æÆ÷ */ +#define SSI_SR (SSI_BASE+0X028) /* ״̬¼Ä´æÆ÷ */ +#define SSI_IMR (SSI_BASE+0X02C) /* ÖжÏÆÁ±Î¼Ä´æÆ÷ */ +#define SSI_ISR (SSI_BASE+0X030) /* ÖжÏ×îÖÕ״̬¼Ä´æÆ÷ */ +#define SSI_RISR (SSI_BASE+0X034) /* ÖжÏԭʼ״̬¼Ä´æÆ÷ */ +#define SSI_TXOICR (SSI_BASE+0X038) /* ·¢ËÍFIFOÉÏÒçÖжÏÇå³ý¼Ä´æÆ÷ */ +#define SSI_RXOICR (SSI_BASE+0X03C) /* ½ÓÊÕFIFOÉÏÒçÖжÏÇå³ý¼Ä´æÆ÷ */ +#define SSI_RXUICR (SSI_BASE+0X040) /* ½ÓÊÕFIFOÏÂÒçÖжÏÇå³ý¼Ä´æÆ÷ */ +#define SSI_ICR (SSI_BASE+0X02C) /* ÖжÏÇå³ý¼Ä´æÆ÷ */ +#define SSI_DMACR (SSI_BASE+0X04C) /* DMA¿ØÖƼĴæÆ÷ */ +#define SSI_DMATDLR (SSI_BASE+0X050) /* DMA·¢ËÍ״̬¼Ä´æÆ÷ */ +#define SSI_DMARDLR (SSI_BASE+0X054) /* DMA½ÓÊÕ״̬¼Ä´æÆ÷ */ +#define SSI_DR (SSI_BASE+0X060) /* Êý¾Ý¼Ä´æÆ÷ */ + + +/* + * I2SÄ£¿é + * »ùÖ·: 0x1000A000 + */ + +#define I2S_CTRL (I2S_BASE+0X000) /* I2S¿ØÖƼĴæÆ÷ */ +#define I2S_DATA (I2S_BASE+0X004) /* I2SÊý¾Ý¼Ä´æÆ÷ */ +#define I2S_INT (I2S_BASE+0X008) /* I2SÖжϼĴæÆ÷ */ +#define I2S_STATUS (I2S_BASE+0X00C) /* I2S״̬¼Ä´æÆ÷ */ + + +/* + * SDÄ£¿é + * »ùÖ·: 0x1000B000 + */ + +#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIOʱÖÓ¿ØÖƼĴæÆ÷ */ +#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIOÈí¼þ¸´Î»¼Ä´æÆ÷ */ +#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIOÃüÁî²ÎÊý¼Ä´æÆ÷ */ +#define SDC_COMMAND (SD_BASE+0X0C) /* SDIOÃüÁî¿ØÖƼĴæÆ÷ */ +#define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIOÊý¾Ý¿é³¤¶È¼Ä´æÆ÷ */ +#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIOÊý¾Ý¿éÊýÄ¿¼Ä´æÆ÷ */ +#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO´«ÊäģʽѡÔñ¼Ä´æÆ÷ */ +#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIOÏìÓ¦¼Ä´æÆ÷0 */ +#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIOÏìÓ¦¼Ä´æÆ÷1 */ +#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIOÏìÓ¦¼Ä´æÆ÷2 */ +#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIOÏìÓ¦¼Ä´æÆ÷3 */ +#define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO¶Á³¬Ê±¿ØÖƼĴæÆ÷ */ +#define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIOÖжÏ״̬¼Ä´æÆ÷ */ +#define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIOÖжÏ״̬ÆÁ±Î¼Ä´æÆ÷ */ +#define SDC_READ_BUFER_ACCESS (SD_BASE+0X38) /* SDIO½ÓÊÕFIFO */ +#define SDC_WRITE_BUFER_ACCESS (SD_BASE+0X3c) /* SDIO·¢ËÍFIFO */ + + + +/* + * SMC0Ä£¿é + * »ùÖ·: 0x1000C000 + */ + +#define SMC0_CTRL (SMC0_BASE+0X000) /* SMC0¿ØÖƼĴæÆ÷ */ +#define SMC0_INT (SMC0_BASE+0X004) /* SMC0ÖжϼĴæÆ÷ */ +#define SMC0_FD (SMC0_BASE+0X008) /* SMC0»ù±¾µ¥ÔªÊ±¼ä¼Ä´æÆ÷ */ +#define SMC0_CT (SMC0_BASE+0X00C) /* SMC0×Ö·û´«Êäʱ¼ä¼Ä´æÆ÷ */ +#define SMC0_BT (SMC0_BASE+0X010) /* SMC0¿é´«Êäʱ¼ä¼Ä´æÆ÷ */ + + + +/* + * SMC1Ä£¿é + * »ùÖ·: 0x1000D000 + */ + +#define SMC1_CTRL (SMC1_BASE+0X000) /* SMC1¿ØÖƼĴæÆ÷ */ +#define SMC1_INT (SMC1_BASE+0X004) /* SMC1ÖжϼĴæÆ÷ */ +#define SMC1_FD (SMC1_BASE+0X008) /* SMC1»ù±¾µ¥ÔªÊ±¼ä¼Ä´æÆ÷ */ +#define SMC1_CT (SMC1_BASE+0X00C) /* SMC1×Ö·û´«Êäʱ¼ä¼Ä´æÆ÷ */ +#define SMC1_BT (SMC1_BASE+0X010) /* SMC1¿é´«Êäʱ¼ä¼Ä´æÆ÷ */ + + + +/* + * USBDÄ£¿é + * »ùÖ·: 0x1000E000 + */ + +#define USBD_PROTOCOLINTR (USBD_BASE+0X000) /* USBЭÒéÖжϼĴæÆ÷ */ +#define USBD_INTRMASK (USBD_BASE+0X004) /* USBÖжÏÆÁ±Î¼Ä´æÆ÷ */ +#define USBD_INTRCTRL (USBD_BASE+0X008) /* USBÖжÏÀàÐÍ¿ØÖƼĴæÆ÷ */ +#define USBD_EPINFO (USBD_BASE+0X00C) /* USB»î¶¯¶Ëµã״̬¼Ä´æÆ÷ */ +#define USBD_BCONFIGURATIONVALUE (USBD_BASE+0X010) /* SET_CCONFIGURATION¼Ç¼ */ +#define USBD_BMATTRIBUTES (USBD_BASE+0X014) /* µ±Ç°ÅäÖÃÊôÐԼĴæÆ÷ */ +#define USBD_DEVSPEED (USBD_BASE+0X018) /* µ±Ç°É豸¹¤×÷ËٶȼĴæÆ÷ */ +#define USBD_FRAMENUMBER (USBD_BASE+0X01C) /* ¼Ç¼µ±Ç°SOF°üÄÚµÄÖ¡ºÅ */ +#define USBD_EPTRANSACTIONS0 (USBD_BASE+0X020) /* ¼Ç¼Ï´ÎÒªÇóµÄ´«Êä´ÎÊý */ +#define USBD_EPTRANSACTIONS1 (USBD_BASE+0X024) /* ¼Ç¼Ï´ÎÒªÇóµÄ´«Êä´ÎÊý */ +#define USBD_APPIFUPDATE (USBD_BASE+0X028) /* ½Ó¿ÚºÅ¿ìËÙ¸üмĴæÆ÷ */ +#define USBD_CFGINTERFACE0 (USBD_BASE+0X02C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE1 (USBD_BASE+0X030) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE2 (USBD_BASE+0X034) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE3 (USBD_BASE+0X038) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE4 (USBD_BASE+0X03C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE5 (USBD_BASE+0X040) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE6 (USBD_BASE+0X044) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE7 (USBD_BASE+0X048) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE8 (USBD_BASE+0X04C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE9 (USBD_BASE+0X050) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE10 (USBD_BASE+0X054) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE11 (USBD_BASE+0X058) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE12 (USBD_BASE+0X05C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE13 (USBD_BASE+0X060) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE14 (USBD_BASE+0X064) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE15 (USBD_BASE+0X068) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE16 (USBD_BASE+0X06C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE17 (USBD_BASE+0X070) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE18 (USBD_BASE+0X074) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE19 (USBD_BASE+0X078) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE20 (USBD_BASE+0X07C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE21 (USBD_BASE+0X080) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE22 (USBD_BASE+0X084) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE23 (USBD_BASE+0X088) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE24 (USBD_BASE+0X08C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE25 (USBD_BASE+0X090) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE26 (USBD_BASE+0X094) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE27 (USBD_BASE+0X098) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE28 (USBD_BASE+0X09C) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE29 (USBD_BASE+0X0A0) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE30 (USBD_BASE+0X0A4) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_CFGINTERFACE31 (USBD_BASE+0X0A8) /* ¼Ç¼½Ó¿ÚµÄÖµ */ +#define USBD_PKTPASSEDCTRL (USBD_BASE+0X0AC) /* ¼Ç¼³É¹¦½ÓÊյİüÊý */ +#define USBD_PKTDROPPEDCTRL (USBD_BASE+0X0B0) /* ¼Ç¼¶ªÊ§µÄ°üÊý */ +#define USBD_CRCERRCTRL (USBD_BASE+0X0B4) /* ¼Ç¼CRC´íÎóµÄ°üÊý */ +#define USBD_BITSTUFFERRCTRL (USBD_BASE+0X0B8) /* ¼Ç¼λÌî³ä´íÎóµÄ°üÊý */ +#define USBD_PIDERRCTRL (USBD_BASE+0X0BC) /* ¼Ç¼PID´íÎóµÄ°üÊý */ +#define USBD_FRAMINGERRCTL (USBD_BASE+0X0C0) /* ¼Ç¼ÓÐSYNCºÍEOPµÄ°üÊý */ +#define USBD_TXPKTCTRL (USBD_BASE+0X0C4) /* ¼Ç¼·¢ËÍ°üµÄÊýÁ¿ */ +#define USBD_STATCTRLOV (USBD_BASE+0X0C8) /* ¼Ç¼ͳ¼Æ¼Ä´æÆ÷Òç³öÇé¿ö */ +#define USBD_TXLENGTH (USBD_BASE+0X0CC) /* ¼Ç¼ÿ´ÎIN´«ÊäÊÂÎñ°ü³¤¶È */ +#define USBD_RXLENGTH (USBD_BASE+0X0D0) /* ¼Ç¼OUT´«ÊäÊÂÎñ°ü³¤¶È */ +#define USBD_RESUME (USBD_BASE+0X0D4) /* USB»½ÐѼĴæÆ÷ */ +#define USBD_READFLAG (USBD_BASE+0X0D8) /* ¶ÁÒ첽״̬¼Ä´æÆ÷±êÖ¾ */ +#define USBD_RECEIVETYPE (USBD_BASE+0X0DC) /* ´«Êä״̬¼Ä´æÆ÷ */ +#define USBD_APPLOCK (USBD_BASE+0X0E0) /* ËøÐźżĴæÆ÷ */ +#define USBD_EP0OUTADDR (USBD_BASE+0X100) /* ¶Ëµã0¶ËµãºÅºÍ·½Ïò */ +#define USBD_EP0OUTBMATTR (USBD_BASE+0X104) /* ¶Ëµã0ÀàÐͼĴæÆ÷ */ +#define USBD_EP0OUTMAXPKTSIZE (USBD_BASE+0X108) /* ¶Ëµã0×î´ó°ü³ß´ç¼Ä´æÆ÷ */ +#define USBD_EP0OUTIFNUM (USBD_BASE+0X10C) /* ¶Ëµã0½Ó¿ÚºÅ¼Ä´æÆ÷ */ +#define USBD_EP0OUTSTAT (USBD_BASE+0X110) /* ¶Ëµã0״̬¼Ä´æÆ÷ */ +#define USBD_EP0OUTBMREQTYPE (USBD_BASE+0X114) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóÀà */ +#define USBD_EP0OUTBREQUEST (USBD_BASE+0X118) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóÄÚÈÝ */ +#define USBD_EP0OUTWVALUE (USBD_BASE+0X11C) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóÖµ */ +#define USBD_EP0OUTWINDEX (USBD_BASE+0X120) /* ¶Ëµã0 SETUPÊÂÎñÇëÇóË÷Òý */ +#define USBD_EP0OUTWLENGTH (USBD_BASE+0X120) /* ¶Ëµã0 SETUPÊÂÎñÇëÇó³¤¶È */ +#define USBD_EP0OUTSYNCHFRAME (USBD_BASE+0X128) /* ¶Ëµã0ͬ²½°üÖ¡ºÅ */ +#define USBD_EP1OUTADDR (USBD_BASE+0X12C) /* ¶Ëµã1Êä³ö¶ËµãºÅºÍ·½Ïò */ +#define USBD_EP1OUTBMATTR (USBD_BASE+0X130) /* ¶Ëµã1Êä³öÀàÐͼĴæÆ÷ */ +#define USBD_EP1OUTMAXPKTSIZE (USBD_BASE+0X134) /* ¶Ëµã1Êä³ö×î´ó°ü³ß´ç¼Ä´æÆ÷ */ +#define USBD_EP1OUTIFNUM (USBD_BASE+0X138) /* ¶Ëµã1Êä³ö½Ó¿ÚºÅ¼Ä´æÆ÷ */ +#define USBD_EP1OUTSTAT (USBD_BASE+0X13C) /* ¶Ëµã1Êä³ö״̬¼Ä´æÆ÷ */ +#define USBD_EP1OUTBMREQTYPE (USBD_BASE+0X140) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÀàÐÍ */ +#define USBD_EP1OUTBREQUEST (USBD_BASE+0X144) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÄÚÈÝ */ +#define USBD_EP1OUTWVALUE (USBD_BASE+0X148) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÖµ */ +#define USBD_EP1OUTWINDX (USBD_BASE+0X14C) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóË÷Òý */ +#define USBD_EP1OUTWLENGH (USBD_BASE+0X150) /* ¶Ëµã1Êä³öSETUPÊÂÎñÇëÇóÓò³¤¶È */ +#define USBD_EP1OUTSYNCHFRAME (USBD_BASE+0X154) /* ¶Ëµã1Êä³öͬ²½°üÖ¡ºÅ */ +#define USBD_EP1INADDR (USBD_BASE+0X158) /* ¶Ëµã1ÊäÈë¶ËµãºÅºÍ·½Ïò */ +#define USBD_EP1INBMATTR (USBD_BASE+0X15C) /* ¶Ëµã1ÊäÈëÀàÐͼĴæÆ÷ */ +#define USBD_EP1INMAXPKTSIZE (USBD_BASE+0X160) /* ¶Ëµã1ÊäÈë×î´ó°ü³ß´ç¼Ä´æÆ÷ */ +#define USBD_EP1INIFNUM (USBD_BASE+0X164) /* ¶Ëµã1ÊäÈë½Ó¿ÚºÅ¼Ä´æÆ÷ */ +#define USBD_EP1INSTAT (USBD_BASE+0X168) /* ¶Ëµã1ÊäÈë״̬¼Ä´æÆ÷ */ +#define USBD_EP1INBMREQTYPE (USBD_BASE+0X16C) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÀàÐÍ */ +#define USBD_EP1INBREQUEST (USBD_BASE+0X170) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÄÚÈÝ */ +#define USBD_EP1INWVALUE (USBD_BASE+0X174) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÖµ */ +#define USBD_EP1INWINDEX (USBD_BASE+0X178) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóË÷Òý */ +#define USBD_EP1INWLENGTH (USBD_BASE+0X17C) /* ¶Ëµã1ÊäÈëSETUPÊÂÎñÇëÇóÓò³¤¶È */ +#define USBD_EP1INSYNCHFRAME (USBD_BASE+0X180) /* ¶Ëµã1ÊäÈëͬ²½°üÖ¡ºÅ */ +#define USBD_EP2OUTADDR (USBD_BASE+0X184) /* ¶Ëµã2Êä³ö¶ËµãºÅºÍ·½Ïò */ +#define USBD_EP2OUTBMATTR (USBD_BASE+0X188) /* ¶Ëµã2Êä³öÀàÐͼĴæÆ÷ */ +#define USBD_EP2OUTMAXPKTSIZE (USBD_BASE+0X18C) /* ¶Ëµã2Êä³ö×î´ó°ü³ß´ç¼Ä´æÆ÷ */ +#define USBD_EP2OUTIFNUM (USBD_BASE+0X190) /* ¶Ëµã2Êä³ö½Ó¿ÚºÅ¼Ä´æÆ÷ */ +#define USBD_EP2OUTSTAT (USBD_BASE+0X194) /* ¶Ëµã2Êä³ö״̬¼Ä´æÆ÷ */ +#define USBD_EP2OUTBMREQTYPE (USBD_BASE+0X198) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÀàÐÍ */ +#define USBD_EP2OUTBREQUEST (USBD_BASE+0X19C) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÄÚÈÝ */ +#define USBD_EP2OUTWVALUE (USBD_BASE+0X1A0) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÖµ */ +#define USBD_EP2OUTWINDEX (USBD_BASE+0X1A4) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóË÷Òý */ +#define USBD_EP2OUTWLENGTH (USBD_BASE+0X1A8) /* ¶Ëµã2Êä³öSETUPÊÂÎñÇëÇóÓò³¤¶È */ +#define USBD_EP2OUTSYNCHFRAME (USBD_BASE+0X1AC) /* ¶Ëµã2Êä³öͬ²½°üÖ¡ºÅ */ +#define USBD_EP2INADDR (USBD_BASE+0X1B0) /* ¶Ëµã2ÊäÈë¶ËµãºÅºÍ·½Ïò */ +#define USBD_EP2INBMATTR (USBD_BASE+0X1B4) /* ¶Ëµã2ÊäÈëÀàÐͼĴæÆ÷ */ +#define USBD_EP2INMAXPKTSIZE (USBD_BASE+0X1B8) /* ¶Ëµã2ÊäÈë×î´ó°ü³ß´ç¼Ä´æÆ÷ */ +#define USBD_EP2INIFNUM (USBD_BASE+0X1BC) /* ¶Ëµã2ÊäÈë½Ó¿ÚºÅ¼Ä´æÆ÷ */ +#define USBD_EP2INSTAT (USBD_BASE+0X1C0) /* ¶Ëµã2ÊäÈë״̬¼Ä´æÆ÷ */ +#define USBD_EP2INBMREQTYPE (USBD_BASE+0X1C4) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÀàÐÍ */ +#define USBD_EP2INBREQUEST (USBD_BASE+0X1C8) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÄÚÈÝ */ +#define USBD_EP2INWVALUE (USBD_BASE+0X1CC) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÖµ */ +#define USBD_EP2INWINDEX (USBD_BASE+0X1D0) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóË÷Òý */ +#define USBD_EP2INWLENGTH (USBD_BASE+0X1D4) /* ¶Ëµã2ÊäÈëSETUPÊÂÎñÇëÇóÓò³¤¶È */ +#define USBD_EP2INSYNCHFRAME (USBD_BASE+0X1D8) /* ¶Ëµã2ÊäÈëͬ²½°üÖ¡ºÅ */ +#define USBD_RXFIFO (USBD_BASE+0X200) /* ½ÓÊÜFIFO */ +#define USBD_TXFIFO (USBD_BASE+0X300) /* ·¢ËÍFIFO */ + + +/* + * GPIOÄ£¿é + * »ùÖ·: 0x1000F000 + */ + +#define GPIO_DBCLK_DIV (GPIO_BASE+0X000) /* ȥë´Ì²ÉÓÃʱÖÓ·ÖƵ±ÈÅäÖüĴæÆ÷ */ +#define GPIO_PORTA_DIR (GPIO_BASE+0X004) /* A×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ +#define GPIO_PORTA_SEL (GPIO_BASE+0X008) /* A×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ +#define GPIO_PORTA_INCTL (GPIO_BASE+0X00C) /* A×é¶Ë¿ÚͨÓÃÓÃ;ÊäÈëʱÀàÐÍÅäÖüĴæÆ÷ */ +#define GPIO_PORTA_INTRCTL (GPIO_BASE+0X010) /* A×é¶Ë¿ÚÖжϴ¥·¢ÀàÐÍÅäÖüĴæÆ÷ */ +#define GPIO_PORTA_INTRCLR (GPIO_BASE+0X014) /* A×é¶Ë¿ÚͨÓÃÓÃ;ÖжÏÇå³ýÅäÖüĴæÆ÷ */ +#define GPIO_PORTA_DATA (GPIO_BASE+0X018) /* A×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ +#define GPIO_PORTB_DIR (GPIO_BASE+0X01C) /* B×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ +#define GPIO_PORTB_SEL (GPIO_BASE+0X020) /* B×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ +#define GPIO_PORTB_DATA (GPIO_BASE+0X024) /* B×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ +#define GPIO_PORTC_DIR (GPIO_BASE+0X028) /* C×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ +#define GPIO_PORTC_SEL (GPIO_BASE+0X02C) /* C×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ +#define GPIO_PORTC_DATA (GPIO_BASE+0X030) /* C×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ +#define GPIO_PORTD_DIR (GPIO_BASE+0X034) /* D×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ +#define GPIO_PORTD_SEL (GPIO_BASE+0X038) /* D×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ +#define GPIO_PORTD_SPECII (GPIO_BASE+0X03C) /* D×é¶Ë¿ÚרÓÃÓÃ;2Ñ¡ÔñÅäÖüĴæÆ÷ */ +#define GPIO_PORTD_DATA (GPIO_BASE+0X040) /* D×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ +#define GPIO_PORTE_DIR (GPIO_BASE+0X044) /* E×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ +#define GPIO_PORTE_SEL (GPIO_BASE+0X048) /* E×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ +#define GPIO_PORTE_DATA (GPIO_BASE+0X04C) /* E×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ +#define GPIO_PORTF_DIR (GPIO_BASE+0X050) /* F×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ +#define GPIO_PORTF_SEL (GPIO_BASE+0X054) /* F×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ +#define GPIO_PORTF_INCTL (GPIO_BASE+0X058) /* F×é¶Ë¿ÚͨÓÃÓÃ;ÊäÈëʱÀàÐÍÅäÖüĴæÆ÷ */ +#define GPIO_PORTF_INTRCTL (GPIO_BASE+0X05C) /* F×é¶Ë¿ÚÖжϴ¥·¢ÀàÐÍÅäÖüĴæÆ÷ */ +#define GPIO_PORTF_INTRCLR (GPIO_BASE+0X060) /* F×é¶Ë¿ÚͨÓÃÓÃ;ÖжÏÇå³ýÅäÖüĴæÆ÷ */ +#define GPIO_PORTF_DATA (GPIO_BASE+0X064) /* F×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ +#define GPIO_PORTG_DIR (GPIO_BASE+0X068) /* G×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ +#define GPIO_PORTG_SEL (GPIO_BASE+0X06C) /* G×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ +#define GPIO_PORTG_DATA (GPIO_BASE+0X070) /* G×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ +#define GPIO_PORTH_DIR (GPIO_BASE+0X07C) /* H×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ +#define GPIO_PORTH_SEL (GPIO_BASE+0X078) /* H×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ +#define GPIO_PORTH_DATA (GPIO_BASE+0X07C) /* H×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ +#define GPIO_PORTI_DIR (GPIO_BASE+0X080) /* I×é¶Ë¿ÚÊäÈëÊä³ö·½ÏòÅäÖüĴæÆ÷ */ +#define GPIO_PORTI_SEL (GPIO_BASE+0X084) /* I×é¶Ë¿ÚͨÓÃÓÃ;ѡÔñÅäÖüĴæÆ÷ */ +#define GPIO_PORTI_DATA (GPIO_BASE+0X088) /* I×é¶Ë¿ÚͨÓÃÓÃ;Êý¾ÝÅäÖüĴæÆ÷ */ + + + +/* + * EMIÄ£¿é + * »ùÖ·: 0x11000000 + */ + +#define EMI_CSACONF (EMI_BASE+0X000) /* CSA²ÎÊýÅäÖüĴæÆ÷ */ +#define EMI_CSBCONF (EMI_BASE+0X004) /* CSB²ÎÊýÅäÖüĴæÆ÷ */ +#define EMI_CSCCONF (EMI_BASE+0X008) /* CSC²ÎÊýÅäÖüĴæÆ÷ */ +#define EMI_CSDCONF (EMI_BASE+0X00C) /* CSD²ÎÊýÅäÖüĴæÆ÷ */ +#define EMI_CSECONF (EMI_BASE+0X010) /* CSE²ÎÊýÅäÖüĴæÆ÷ */ +#define EMI_CSFCONF (EMI_BASE+0X014) /* CSF²ÎÊýÅäÖüĴæÆ÷ */ +#define EMI_SDCONF1 (EMI_BASE+0X018) /* SDRAMʱÐòÅäÖüĴæÆ÷1 */ +#define EMI_SDCONF2 (EMI_BASE+0X01C) /* SDRAMʱÐòÅäÖüĴæÆ÷2, SDRAM³õʼ»¯Óõ½µÄÅäÖÃÐÅÏ¢ */ +#define EMI_REMAPCONF (EMI_BASE+0X020) /* Ƭѡ¿Õ¼ä¼°µØÖ·Ó³ÉäREMAPÅäÖüĴæÆ÷ */ +#define EMI_NAND_ADDR1 (EMI_BASE+0X100) /* NAND FLASHµÄµØÖ·¼Ä´æÆ÷1 */ +#define EMI_NAND_COM (EMI_BASE+0X104) /* NAND FLASHµÄ¿ØÖÆ×ּĴæÆ÷ */ +#define EMI_NAND_STA (EMI_BASE+0X10C) /* NAND FLASHµÄ״̬¼Ä´æÆ÷ */ +#define EMI_ERR_ADDR1 (EMI_BASE+0X110) /* ¶Á²Ù×÷³ö´íµÄµØÖ·¼Ä´æÆ÷1 */ +#define EMI_ERR_ADDR2 (EMI_BASE+0X114) /* ¶Á²Ù×÷³ö´íµÄµØÖ·¼Ä´æÆ÷2 */ +#define EMI_NAND_CONF1 (EMI_BASE+0X118) /* NAND FLASHµÄÅäÖÃÆ÷´æÆ÷1 */ +#define EMI_NAND_INTR (EMI_BASE+0X11C) /* NAND FLASHÖжϼĴæÆ÷ */ +#define EMI_NAND_ECC (EMI_BASE+0X120) /* ECCУÑéÍê³É¼Ä´æÆ÷ */ +#define EMI_NAND_IDLE (EMI_BASE+0X124) /* NAND FLASH¿ÕÏмĴæÆ÷ */ +#define EMI_NAND_CONF2 (EMI_BASE+0X128) /* NAND FLASHµÄÅäÖÃÆ÷´æÆ÷2 */ +#define EMI_NAND_ADDR2 (EMI_BASE+0X12C) /* NAND FLASHµÄµØÖ·¼Ä´æÆ÷2 */ +#define EMI_NAND_DATA (EMI_BASE+0X200) /* NAND FLASHµÄÊý¾Ý¼Ä´æÆ÷ */ + + +/* + * DMACÄ£¿é + * »ùÖ·: 0x11001000 + */ + +#define DMAC_INTSTATUS (DMAC_BASE+0X020) /* DAMCÖжÏ״̬¼Ä´æÆ÷¡£ */ +#define DMAC_INTTCSTATUS (DMAC_BASE+0X050) /* DMAC´«ÊäÍê³ÉÖжÏ״̬¼Ä´æÆ÷ */ +#define DMAC_INTTCCLEAR (DMAC_BASE+0X060) /* DMAC´«ÊäÍê³ÉÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define DMAC_INTERRORSTATUS (DMAC_BASE+0X080) /* DMAC´«Êä´íÎóÖжÏ״̬¼Ä´æÆ÷ */ +#define DMAC_INTINTERRCLR (DMAC_BASE+0X090) /* DMAC´«Êä´íÎóÖжÏ״̬Çå³ý¼Ä´æÆ÷ */ +#define DMAC_ENBLDCHNS (DMAC_BASE+0X0B0) /* DMACͨµÀʹÄÜ״̬¼Ä´æÆ÷ */ +#define DMAC_C0SRCADDR (DMAC_BASE+0X000) /* DMACµÀ0Ô´µØÖ·¼Ä´æÆ÷ */ +#define DMAC_C0DESTADD (DMAC_BASE+0X004) /* DMACµÀ0Ä¿µÄµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C0CONTROL (DMAC_BASE+0X00C) /* DMACµÀ0¿ØÖƼĴæÆ÷ */ +#define DMAC_C0CONFIGURATION (DMAC_BASE+0X010) /* DMACµÀ0ÅäÖüĴæÆ÷ */ +#define DMAC_C0DESCRIPTOR (DMAC_BASE+0X01C) /* DMACµÀ0Á´±íµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C1SRCADDR (DMAC_BASE+0X100) /* DMACµÀ1Ô´µØÖ·¼Ä´æÆ÷ */ +#define DMAC_C1DESTADDR (DMAC_BASE+0X104) /* DMACµÀ1Ä¿µÄµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C1CONTROL (DMAC_BASE+0X10C) /* DMACµÀ1¿ØÖƼĴæÆ÷ */ +#define DMAC_C1CONFIGURATION (DMAC_BASE+0X110) /* DMACµÀ1ÅäÖüĴæÆ÷ */ +#define DMAC_C1DESCRIPTOR (DMAC_BASE+0X114) /* DMACµÀ1Á´±íµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C2SRCADDR (DMAC_BASE+0X200) /* DMACµÀ2Ô´µØÖ·¼Ä´æÆ÷ */ +#define DMAC_C2DESTADDR (DMAC_BASE+0X204) /* DMACµÀ2Ä¿µÄµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C2CONTROL (DMAC_BASE+0X20C) /* DMACµÀ2¿ØÖƼĴæÆ÷ */ +#define DMAC_C2CONFIGURATION (DMAC_BASE+0X210) /* DMACµÀ2ÅäÖüĴæÆ÷ */ +#define DMAC_C2DESCRIPTOR (DMAC_BASE+0X214) /* DMACµÀ2Á´±íµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C3SRCADDR (DMAC_BASE+0X300) /* DMACµÀ3Ô´µØÖ·¼Ä´æÆ÷ */ +#define DMAC_C3DESTADDR (DMAC_BASE+0X304) /* DMACµÀ3Ä¿µÄµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C3CONTROL (DMAC_BASE+0X30C) /* DMACµÀ3¿ØÖƼĴæÆ÷ */ +#define DMAC_C3CONFIGURATION (DMAC_BASE+0X310) /* DMACµÀ3ÅäÖüĴæÆ÷ */ +#define DMAC_C3DESCRIPTOR (DMAC_BASE+0X314) /* DMACµÀ3Á´±íµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C4SRCADDR (DMAC_BASE+0X400) /* DMACµÀ4Ô´µØÖ·¼Ä´æÆ÷ */ +#define DMAC_C4DESTADDR (DMAC_BASE+0X404) /* DMACµÀ4Ä¿µÄµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C4CONTROL (DMAC_BASE+0X40C) /* DMACµÀ4¿ØÖƼĴæÆ÷ */ +#define DMAC_C4CONFIGURATION (DMAC_BASE+0X410) /* DMACµÀ4ÅäÖüĴæÆ÷ */ +#define DMAC_C4DESCRIPTOR (DMAC_BASE+0X414) /* DMACµÀ4Á´±íµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C5SRCADDR (DMAC_BASE+0X500) /* DMACµÀ5Ô´µØÖ·¼Ä´æÆ÷ */ +#define DMAC_C5DESTADDR (DMAC_BASE+0X504) /* DMACµÀ5Ä¿µÄµØÖ·¼Ä´æÆ÷ */ +#define DMAC_C5CONTROL (DMAC_BASE+0X50C) /* DMACµÀ5¿ØÖƼĴæÆ÷ */ +#define DMAC_C5CONFIGURATION (DMAC_BASE+0X510) /* DMACµÀ5ÅäÖüĴæÆ÷ */ +#define DMAC_C5DESCRIPTOR (DMAC_BASE+0X514) /* DMACµÀ5Á´±íµØÖ·¼Ä´æÆ÷ */ + + +/* + * LCDCÄ£¿é + * »ùÖ·: 0x11002000 + */ + +#define LCDC_SSA (LCDC_BASE+0X000) /* ÆÁÄ»ÆðʼµØÖ·¼Ä´æÆ÷ */ +#define LCDC_SIZE (LCDC_BASE+0X004) /* ÆÁÄ»³ß´ç¼Ä´æÆ÷ */ +#define LCDC_PCR (LCDC_BASE+0X008) /* Ãæ°åÅäÖüĴæÆ÷ */ +#define LCDC_HCR (LCDC_BASE+0X00C) /* ˮƽÅäÖüĴæÆ÷ */ +#define LCDC_VCR (LCDC_BASE+0X010) /* ´¹Ö±ÅäÖüĴæÆ÷ */ +#define LCDC_PWMR (LCDC_BASE+0X014) /* PWM¶Ô±È¶È¿ØÖƼĴæÆ÷ */ +#define LCDC_LECR (LCDC_BASE+0X018) /* ʹÄÜ¿ØÖƼĴæÆ÷ */ +#define LCDC_DMACR (LCDC_BASE+0X01C) /* DMA¿ØÖƼĴæÆ÷ */ +#define LCDC_LCDISREN (LCDC_BASE+0X020) /* ÖжÏʹÄܼĴæÆ÷ */ +#define LCDC_LCDISR (LCDC_BASE+0X024) /* ÖжÏ״̬¼Ä´æÆ÷ */ +#define LCDC_LGPMR (LCDC_BASE+0X040) /* »Ò¶Èµ÷É«Ó³Éä¼Ä´æÆ÷×é (16¸ö32bit¼Ä´æÆ÷) */ + + +/* + * MACÄ£¿é + * »ùÖ·: 0x11003000 + */ + +#define MAC_CTRL (MAC_BASE+0X000) /* MAC¿ØÖƼĴæÆ÷ */ +#define MAC_INTSRC (MAC_BASE+0X004) /* MACÖжÏÔ´¼Ä´æÆ÷ */ +#define MAC_INTMASK (MAC_BASE+0X008) /* MACÖжÏÆÁ±Î¼Ä´æÆ÷ */ +#define MAC_IPGT (MAC_BASE+0X00C) /* Á¬ÐøÖ¡¼ä¸ô¼Ä´æÆ÷ */ +#define MAC_IPGR1 (MAC_BASE+0X010) /* µÈ´ý´°¿Ú¼Ä´æÆ÷ */ +#define MAC_IPGR2 (MAC_BASE+0X014) /* µÈ´ý´°¿Ú¼Ä´æÆ÷ */ +#define MAC_PACKETLEN (MAC_BASE+0X018) /* Ö¡³¤¶È¼Ä´æÆ÷ */ +#define MAC_COLLCONF (MAC_BASE+0X01C) /* ÅöײÖØ·¢¼Ä´æÆ÷ */ +#define MAC_TXBD_NUM (MAC_BASE+0X020) /* ·¢ËÍÃèÊö·û¼Ä´æÆ÷ */ +#define MAC_FLOWCTRL (MAC_BASE+0X024) /* Á÷¿Ø¼Ä´æÆ÷ */ +#define MAC_MII_CTRL (MAC_BASE+0X028) /* PHY¿ØÖƼĴæÆ÷ */ +#define MAC_MII_CMD (MAC_BASE+0X02C) /* PHYÃüÁî¼Ä´æÆ÷ */ +#define MAC_MII_ADDRESS (MAC_BASE+0X030) /* PHYµØÖ·¼Ä´æÆ÷ */ +#define MAC_MII_TXDATA (MAC_BASE+0X034) /* PHYдÊý¾Ý¼Ä´æÆ÷ */ +#define MAC_MII_RXDATA (MAC_BASE+0X038) /* PHY¶ÁÊý¾Ý¼Ä´æÆ÷ */ +#define MAC_MII_STATUS (MAC_BASE+0X03C) /* PHY״̬¼Ä´æÆ÷ */ +#define MAC_ADDR0 (MAC_BASE+0X040) /* MACµØÖ·¼Ä´æÆ÷ */ +#define MAC_ADDR1 (MAC_BASE+0X044) /* MACµØÖ·¼Ä´æÆ÷ */ +#define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH¼Ä´æÆ÷ */ +#define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH¼Ä´æÆ÷ */ +#define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC¿ØÖÆÖ¡¼Ä´æÆ÷ */ +#define MAC_TX_BD (MAC_BASE+0X400) +#define MAC_RX_BD (MAC_BASE+0X600) + + +/* + ************************************** + * Error Codes: + * IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE, + * parameter error return (-33)/E_PAR, + * hardware error reture (-99)/E_HA + ************************************** + */ + +#define E_OK 0 /* Normal completion */ +#define E_SYS (-5) /* System error */ +#define E_NOMEM (-10) /* Insufficient memory */ +#define E_NOSPT (-17) /* Feature not supported */ +#define E_INOSPT (-18) /* Feature not supported by ITRON/FILE specification */ +#define E_RSFN (-20) /* Reserved function code number */ +#define E_RSATR (-24) /* Reserved attribute */ +#define E_PAR (-33) /* Parameter error */ +#define E_ID (-35) /* Invalid ID number */ +#define E_NOEXS (-52) /* Object does not exist */ +#define E_OBJ (-63) /* Invalid object state */ +#define E_MACV (-65) /* Memory access disabled or memory access violation */ +#define E_OACV (-66) /* Object access violation */ +#define E_CTX (-69) /* Context error */ +#define E_QOVR (-73) /* Queuing or nesting overflow */ +#define E_DLT (-81) /* Object being waited for was deleted */ +#define E_TMOUT (-85) /* Polling failure or timeout exceeded */ +#define E_RLWAI (-86) /* WAIT state was forcibly released */ + +#define E_HA (-99) /* HARD WARE ERROR */ + + +/* + ************************************** + * PMU Ä£¿éʱÖÓ + ************************************** + */ + +#define CLK_SGPT (1 << 16) +#define CLK_SI2S (1 << 15) +#define CLK_SSMC (1 << 14) +#define CLK_SMAC (1 << 13) +#define CLK_SUSB (1 << 12) +#define CLK_SUART3 (1 << 11) +#define CLK_SUART2 (1 << 10) +#define CLK_SUART1 (1 << 9) +#define CLK_SUART0 (1 << 8) +#define CLK_SSSI (1 << 7) +#define CLK_SAC97 (1 << 6) +#define CLK_SMMCSD (1 << 5) +#define CLK_SEMI (1 << 4) +#define CLK_SDMAC (1 << 3) +#define CLK_SPWM (1 << 2) +#define CLK_SLCDC (1 << 1) +#define CLK_SESRAM (1) + + +/*Interrupt Sources*/ + + +#define INTSRC_RTC 31 +#define INTSRC_DMAC 30 +#define INTSRC_EMI 29 +#define INTSRC_MAC 28 +#define INTSRC_TIMER1 27 +#define INTSRC_TIMER2 26 +#define INTSRC_TIMER3 25 +#define INTSRC_UART0 24 +#define INTSRC_UART1 23 +#define INTSRC_UART2 22 +#define INTSRC_UART3 21 +#define INTSRC_PWM 20 +#define INTSRC_LCDC 19 +#define INTSRC_I2S 18 +#define INTSRC_SSI 17 + +#define INTSRC_USB 15 +#define INTSRC_SMC0 14 +#define INTSRC_SMC1 13 +#define INTSRC_SDIO 12 +#define INTSRC_EXINT10 11 +#define INTSRC_EXINT9 10 +#define INTSRC_EXINT8 9 +#define INTSRC_EXINT7 8 +#define INTSRC_EXINT6 7 +#define INTSRC_EXINT5 6 +#define INTSRC_EXINT4 5 +#define INTSRC_EXINT3 4 +#define INTSRC_EXINT2 3 +#define INTSRC_EXINT1 2 +#define INTSRC_EXINT0 1 +#define INTSRC_NULL 0 + + +/*Sereral useful macros*/ +#define set_plevel(plevel) *(RP)INTC_IPLR = plevel //ÉèÖÃÆÕͨÖжϵÄÓÅÏȼ¶ÃÅÏÞ£¬Ö»ÓÐÓÅÏȼ¶´óÓÚ´ËÖµµÄÖжϲÅÄÜͨ¹ý +#define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //ÖÃ1ºó£¬Èí¼þÇ¿ÖƸÃλ¶ÔÓ¦µÄÖжÏÔ´·¢³öÖжÏÐźŠ+#define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //ÖÃ1ºó£¬ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ+#define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //ÖÃ0ºó£¬²»ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ+#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //ÖÃ1ºó£¬ÆÁ±Î¶ÔÓ¦µÄIRQ ÖжÏÐźŠ+#define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //ÖÃ0ºó£¬Í¨¹ý¶ÔÓ¦µÄIRQ ÖжÏÐźŠ+#define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //ÆÁ±Î¶ÔÓ¦µÄIRQ ÖжÏÐźŠ+#define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //ͨ¹ý¶ÔÓ¦µÄIRQ ÖжÏÐźŠ+#define enable_all_irq() *(RP)INTC_IER = 0XFFFFFFFF //ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ+#define disable_all_irq() *(RP)INTC_IER = 0X00000000 //²»ÔÊÐíÖжÏÔ´µÄIRQ ÖжÏÐźŠ+#define InitInt() do{mask_all_irq(); enable_all_irq();}while(0) + +/* + ************************************** + * ËùÓгÌÐòÖÐÓõ½µÄTypedef + ************************************** + */ + +typedef char S8; /* signed 8-bit integer */ +typedef short S16; /* signed 16-bit integer */ +typedef long S32; /* signed 32-bit integer */ +typedef unsigned char U8; /* unsigned 8-bit integer */ +typedef unsigned short U16; /* unsigned 16-bit integer */ +typedef unsigned long U32; /* unsigned 32-bit integer */ + +typedef volatile U32 * RP; +typedef volatile U16 * RP16; +typedef volatile U8 * RP8; + +typedef void *VP; /* pointer to an unpredictable data type */ +typedef void (*FP)(); /* program start address */ + +#ifndef _BOOL_TYPE_ +#define _BOOL_TYPE_ +typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ +#endif + +typedef int ER; /* Error code. A signed integer. */ + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#define __I volatile const /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ +#define __iomem volatile + + +/*Macros for debug*/ + +#define EOUT(fmt,...) \ + do \ + { \ + rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) + +#define RT_DEBUG +#ifdef RT_DEBUG + #define DBOUT(fmt,...) \ + do \ + { \ + rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) +#else + #define DBOUT(fmt,...) \ + do{}while(0) +#endif + +#ifdef RT_DEBUG + #define ASSERT(arg) \ + if((arg) == 0) \ + { \ + while(1) \ + { \ + rt_kprintf("have a assert failure\n"); \ + } \ + } +#else + #define ASSERT(arg) \ + do \ + { \ + }while(0) +#endif + + +#define write_reg(reg,value) \ + do \ + { \ + *(RP)(reg) = value; \ + }while(0) + +#define read_reg(reg) (*(RP)reg) + + +struct rt_hw_register +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; +}; + + +/*@}*/ + +#endif diff --git a/libcpu/arm/sep4020/serial.c b/libcpu/arm/sep4020/serial.c index c9dbc3c025b016cdce4bb0e7f8f172700ae29a82..728f7dc1edbed33d2fc7a92bd9a7c2d9a0df46c6 100644 --- a/libcpu/arm/sep4020/serial.c +++ b/libcpu/arm/sep4020/serial.c @@ -1,282 +1,282 @@ -/* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport - */ -#include -#include -#include "serial.h" - -/** - * @addtogroup SEP4020 - */ -/*@{*/ - -/* RT-Thread Device Interface */ -/** - * This function initializes serial - */ -static rt_err_t rt_serial_init (rt_device_t dev) -{ - struct serial_device* uart = (struct serial_device*) dev->user_data; - - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - - return RT_EOK; -} - -/* save a char to serial buffer */ -static void rt_serial_savechar(struct serial_device* uart, char ch) -{ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); -} - -static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - RT_ASSERT(dev != RT_NULL); - return RT_EOK; -} - -static rt_err_t rt_serial_close(rt_device_t dev) -{ - RT_ASSERT(dev != RT_NULL); - return RT_EOK; -} - -static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; - - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; - - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = '\r'; - } - - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); - - ++ptr; --size; - } - } - - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) -{ - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; -} - -/* - * serial register - */ -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) -{ - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); -} - -/* ISR for serial interrupt */ -void rt_hw_serial_isr(rt_device_t device) -{ - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - - /* save on rx buffer */ - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); - } - - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; - - device->rx_indicate(device, rx_length); - } -} - -/*@}*/ - +/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2009-04-20 yi.qiu modified according bernard's stm32 version + * 2010-10-6 wangmeng added sep4020 surpport + */ +#include +#include +#include "serial.h" + +/** + * @addtogroup SEP4020 + */ +/*@{*/ + +/* RT-Thread Device Interface */ +/** + * This function initializes serial + */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + struct serial_device* uart = (struct serial_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; +} + +/* save a char to serial buffer */ +static void rt_serial_savechar(struct serial_device* uart, char ch) +{ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + return RT_EOK; +} + +static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; + + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; + + /* move to next position */ + uart->int_tx->save_index ++; + + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } + + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = '\r'; + } + + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); + + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; +} + +/* + * serial register + */ +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) +{ + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); +} + +/* ISR for serial interrupt */ +void rt_hw_serial_isr(rt_device_t device) +{ + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); + } + + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + device->rx_indicate(device, rx_length); + } +} + +/*@}*/ + diff --git a/libcpu/arm/sep4020/serial.h b/libcpu/arm/sep4020/serial.h index f903c1e1a56e52e94d11af3dd0b78d6fa41a77cb..f0357aacfb5f070b3c7cc3f16b1af3295ac963ef 100644 --- a/libcpu/arm/sep4020/serial.h +++ b/libcpu/arm/sep4020/serial.h @@ -1,90 +1,90 @@ -/* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport - */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#include - -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ - -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 - -/*For sep4020's uart have several secondary function*/ -/*we use union to decribe it*/ - -union dlbl_fifo -{ - rt_uint32_t dlbl; - rt_uint32_t rxfifo; - rt_uint32_t txfifo; -}; - -union dlbh_ier -{ - rt_uint32_t dlbh; - rt_uint32_t ier; -}; - -union iir_fcr -{ - rt_uint32_t iir; - rt_uint32_t fcr; -}; - -struct serial_int_rx -{ - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; - -struct serial_int_tx -{ - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; -}; - -typedef struct uartport -{ - union dlbl_fifo dlbl_fifo; - union dlbh_ier dlbh_ier; - union iir_fcr iir_fcr; - rt_uint32_t lcr; - rt_uint32_t mcr; - rt_uint32_t lsr; - rt_uint32_t msr; -}uartport; - -struct serial_device -{ - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; - - /* tx structure */ - struct serial_int_tx* int_tx; -}; - -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); - -void rt_hw_serial_isr(rt_device_t device); - - -#endif +/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2009-04-20 yi.qiu modified according bernard's stm32 version + * 2010-10-6 wangmeng added sep4020 surpport + */ + +#ifndef __SERIAL_H__ +#define __SERIAL_H__ + +#include + +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +/*For sep4020's uart have several secondary function*/ +/*we use union to decribe it*/ + +union dlbl_fifo +{ + rt_uint32_t dlbl; + rt_uint32_t rxfifo; + rt_uint32_t txfifo; +}; + +union dlbh_ier +{ + rt_uint32_t dlbh; + rt_uint32_t ier; +}; + +union iir_fcr +{ + rt_uint32_t iir; + rt_uint32_t fcr; +}; + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +typedef struct uartport +{ + union dlbl_fifo dlbl_fifo; + union dlbh_ier dlbh_ier; + union iir_fcr iir_fcr; + rt_uint32_t lcr; + rt_uint32_t mcr; + rt_uint32_t lsr; + rt_uint32_t msr; +}uartport; + +struct serial_device +{ + uartport* uart_device; + + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); + +void rt_hw_serial_isr(rt_device_t device); + + +#endif diff --git a/libcpu/arm/sep4020/start_rvds.S b/libcpu/arm/sep4020/start_rvds.S index bb4d20595c5ee497fd2d5597ed6bfddfd161f198..bf5431e03cab595c51782e946f8cdb6b8ed6a750 100644 --- a/libcpu/arm/sep4020/start_rvds.S +++ b/libcpu/arm/sep4020/start_rvds.S @@ -1,385 +1,385 @@ -;============================================================================================== -; star_rvds.s for Keil MDK 4.10 -; -; SEP4020 start up code -; -; Change Logs: -; Date Author Notes -; 2010-03-17 zchong -;============================================================================================= - -PMU_PLTR EQU 0x10001000 ; PLLµÄÎȶ¨¹ý¶Éʱ¼ä -PMU_PMCR EQU 0x10001004 ; ϵͳÖ÷ʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ -PMU_PUCR EQU 0x10001008 ; USBʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ -PMU_PCSR EQU 0x1000100C ; ÄÚ²¿Ä£¿éʱÖÓÔ´¹©¸øµÄ¿ØÖƼĴæÆ÷ -PMU_PDSLOW EQU 0x10001010 ; SLOW״̬ÏÂʱÖӵķÖƵÒò×Ó -PMU_PMDR EQU 0x10001014 ; оƬ¹¤×÷ģʽ¼Ä´æÆ÷ -PMU_RCTR EQU 0x10001018 ; Reset¿ØÖƼĴæÆ÷ -PMU_CLRWAKUP EQU 0x1000101C ; WakeUpÇå³ý¼Ä´æÆ÷ - -RTC_CTR EQU 0x1000200C ; RTC¿ØÖƼĴæÆ÷ - -INTC_IER EQU 0x10000000 ; IRQÖжÏÔÊÐí¼Ä´æÆ÷ -INTC_IMR EQU 0x10000008 ; IRQÖжÏÆÁ±Î¼Ä´æÆ÷ -INTC_IFSR EQU 0x10000030 ; IRQÖжÏ×îÖÕ״̬¼Ä´æÆ÷ -INTC_FIER EQU 0x100000C0 ; FIQÖжÏÔÊÐí¼Ä´æÆ÷ -INTC_FIMR EQU 0x100000C4 ; FIQÖжÏÆÁ±Î¼Ä´æÆ÷ - -EMI_CSACONF EQU 0x11000000 ; CSA²ÎÊýÅäÖüĴæÆ÷ -EMI_CSECONF EQU 0x11000010 ; CSE²ÎÊýÅäÖüĴæÆ÷ -EMI_CSFCONF EQU 0x11000014 ; CSF²ÎÊýÅäÖüĴæÆ÷ -EMI_SDCONF1 EQU 0x11000018 ; SDRAMʱÐòÅäÖüĴæÆ÷1 -EMI_SDCONF2 EQU 0x1100001C ; SDRAMʱÐòÅäÖüĴæÆ÷2, SDRAM³õʼ»¯Óõ½µÄÅäÖÃÐÅÏ¢ -EMI_REMAPCONF EQU 0x11000020 ; Ƭѡ¿Õ¼ä¼°µØÖ·Ó³ÉäREMAPÅäÖüĴæÆ÷ - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled -NOINT EQU 0xc0 -MASK_MODE EQU 0x0000003F -MODE_SVC32 EQU 0x00000013 - -; Internal Memory Base Addresses -FLASH_BASE EQU 0x20000000 -RAM_BASE EQU 0x04000000 -SDRAM_BASE EQU 0x30000000 - -; Stack -Unused_Stack_Size EQU 0x00000100 -Svc_Stack_Size EQU 0x00001000 -Abt_Stack_Size EQU 0x00000000 -Fiq_Stack_Size EQU 0x00000000 -Irq_Stack_Size EQU 0x00001000 -Usr_Stack_Size EQU 0x00000000 - -;SVC STACK - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Svc_Stack SPACE Svc_Stack_Size -__initial_sp -Svc_Stack_Top - -;IRQ STACK - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Irq_Stack SPACE Irq_Stack_Size -Irq_Stack_Top - -;UNUSED STACK - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Unused_Stack SPACE Unused_Stack_Size -Unused_Stack_Top - - -; Heap -Heap_Size EQU 0x0000100 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT Heap_Mem -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - EXPORT Entry_Point -Entry_Point -Vectors LDR PC,Reset_Addr - LDR PC,Undef_Addr - LDR PC,SWI_Addr - LDR PC,PAbt_Addr - LDR PC,DAbt_Addr - NOP ; Reserved Vector - LDR PC,IRQ_Addr - LDR PC,FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B Abort_Handler -DAbt_Handler B Abort_Handler -FIQ_Handler B FIQ_Handler - -Abort_Handler PROC - ARM - EXPORT Abort_Handler -DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system. - ENDP - - -; Reset Handler - ;IMPORT __user_initial_stackheap - EXPORT Reset_Handler -Reset_Handler - -;**************************************************************** -;* Shutdown watchdog -;**************************************************************** - LDR R0,=RTC_CTR - LDR R1,=0x0 - STR R1,[R0] - -;**************************************************************** -;* shutdown interrupts -;**************************************************************** - MRS R0, CPSR - BIC R0, R0, #MASK_MODE - ORR R0, R0, #MODE_SVC32 - ORR R0, R0, #I_Bit - ORR R0, R0, #F_Bit - MSR CPSR_c, r0 - - LDR R0,=INTC_IER - LDR R1,=0x0 - STR R1,[R0] - LDR R0,=INTC_IMR - LDR R1,=0xFFFFFFFF - STR R1,[R0] - - LDR R0,=INTC_FIER - LDR R1,=0x0 - STR R1,[R0] - LDR R0,=INTC_FIMR - LDR R1,=0x0F - STR R1,[R0] - -;**************************************************************** -;* Initialize Stack Pointer -;**************************************************************** - - LDR SP, =Svc_Stack_Top ;init SP_svc - - MOV R4, #0xD2 ;chmod to irq and init SP_irq - MSR cpsr_c, R4 - LDR SP, =Irq_Stack_Top - - MOV R4, #0XD1 ;chomod to fiq and init SP_fiq - MSR cpsr_c, R4 - LDR SP, =Unused_Stack_Top - - MOV R4, #0XD7 ;chomod to abt and init SP_ABT - MSR cpsr_c, R4 - LDR SP, =Unused_Stack_Top - - MOV R4, #0XDB ;chomod to undf and init SP_UNDF - MSR cpsr_c, R4 - LDR SP, =Unused_Stack_Top - - ;chomod to abt and init SP_sys - MOV R4, #0xDF ;all interrupts disabled - MSR cpsr_c, R4 ;SYSTEM mode, @32-bit code mode - LDR SP, =Unused_Stack_Top - - MOV R4, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable - MSR cpsr_c, R4 - - - -;**************************************************************** -;* Initialize PMU & System Clock -;**************************************************************** - - LDR R4, =PMU_PCSR ; ´òËùÓÐÄ£¿éʱÖÓ - LDR R5, =0x0001ffff - STR R5, [ R4 ] - - LDR R4, =PMU_PLTR ; ÅäÖÃPLLÎȶ¨¹ý¶Èʱ¼äΪ±£ÊØÖµ50us*100M. - LDR R5, =0x00fa00fa - STR R5, [ R4 ] - - LDR R4, =PMU_PMDR ; ÓÉSLOWģʽ½øÈëNORMALģʽ - LDR R5, =0x00000001 - STR R5, [ R4 ] - - LDR R4, =PMU_PMCR ; ÅäÖÃϵͳʱÖÓΪ80MHz - LDR R5, =0x00004009 ; 400b -- 88M - STR R5, [ R4 ] - - ;PMU_PMCR¼Ä´æÆ÷µÚ15λÐèÒªÓдӵ͵½¸ßµÄ·­×ª£¬²ÅÄÜ´¥·¢PLLµÄʱÖÓÅäÖà - LDR R4, =PMU_PMCR - LDR R5, =0x0000c009 - STR R5, [ R4 ] - -;**************************************************************** -;* ³õʼ»¯EMI -;**************************************************************** - - IF :DEF:INIT_EMI - - LDR R4, =EMI_CSACONF ; CSAƬѡʱÐò²ÎÊýÅäÖà - LDR R5, =0x08a6a6a1 - STR R5, [ R4 ] - - LDR R4, =EMI_CSECONF ; CSEƬѡʱÐò²ÎÊýÅäÖÃ,×î±£ÊØÅäÖà - LDR R5, =0x8cfffff1 - STR R5, [ R4 ] - - LDR R4, =EMI_SDCONF1 ; SDRAM²ÎÊýÅäÖÃ1 - LDR R5, =0x1E104177 - STR R5, [ R4 ] - - LDR R4, =EMI_SDCONF2 ; SDRAM²ÎÊýÅäÖÃ2 - LDR R5, =0x80001860 - STR R5, [ R4 ] - - ENDIF - -; Copy Exception Vectors to Internal RAM - - IF :DEF:RAM_INTVEC - - ADR R8, Vectors ; Source - LDR R9, =RAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - - ENDIF - -; Remap on-chip RAM to address 0 - - IF :DEF:REMAP - - LDR R0, =EMI_REMAPCONF - IF :DEF:RAM_INTVEC - MOV R1, #0x80000000 - ELSE - MOV R1, #0x0000000b - ENDIF - STR R1, [R0, #0] ; Remap - - ENDIF - -;*************************************************************** -;* Open irq interrupt -;*************************************************************** - - MRS R4, cpsr - BIC R4, R4, #0x80 ; set bit7 to zero - MSR cpsr_c, R4 - -; Enter the C code - IMPORT __main - LDR R0,=__main - BX R0 - - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit :OR F_Bit :OR Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - - - ALIGN - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - EXPORT __initial_sp - - ELSE ;__MICROLIB -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, = (Svc_Stack + Svc_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Svc_Stack - BX LR - ALIGN - ENDIF - END +;============================================================================================== +; star_rvds.s for Keil MDK 4.10 +; +; SEP4020 start up code +; +; Change Logs: +; Date Author Notes +; 2010-03-17 zchong +;============================================================================================= + +PMU_PLTR EQU 0x10001000 ; PLLµÄÎȶ¨¹ý¶Éʱ¼ä +PMU_PMCR EQU 0x10001004 ; ϵͳÖ÷ʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ +PMU_PUCR EQU 0x10001008 ; USBʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ +PMU_PCSR EQU 0x1000100C ; ÄÚ²¿Ä£¿éʱÖÓÔ´¹©¸øµÄ¿ØÖƼĴæÆ÷ +PMU_PDSLOW EQU 0x10001010 ; SLOW״̬ÏÂʱÖӵķÖƵÒò×Ó +PMU_PMDR EQU 0x10001014 ; оƬ¹¤×÷ģʽ¼Ä´æÆ÷ +PMU_RCTR EQU 0x10001018 ; Reset¿ØÖƼĴæÆ÷ +PMU_CLRWAKUP EQU 0x1000101C ; WakeUpÇå³ý¼Ä´æÆ÷ + +RTC_CTR EQU 0x1000200C ; RTC¿ØÖƼĴæÆ÷ + +INTC_IER EQU 0x10000000 ; IRQÖжÏÔÊÐí¼Ä´æÆ÷ +INTC_IMR EQU 0x10000008 ; IRQÖжÏÆÁ±Î¼Ä´æÆ÷ +INTC_IFSR EQU 0x10000030 ; IRQÖжÏ×îÖÕ״̬¼Ä´æÆ÷ +INTC_FIER EQU 0x100000C0 ; FIQÖжÏÔÊÐí¼Ä´æÆ÷ +INTC_FIMR EQU 0x100000C4 ; FIQÖжÏÆÁ±Î¼Ä´æÆ÷ + +EMI_CSACONF EQU 0x11000000 ; CSA²ÎÊýÅäÖüĴæÆ÷ +EMI_CSECONF EQU 0x11000010 ; CSE²ÎÊýÅäÖüĴæÆ÷ +EMI_CSFCONF EQU 0x11000014 ; CSF²ÎÊýÅäÖüĴæÆ÷ +EMI_SDCONF1 EQU 0x11000018 ; SDRAMʱÐòÅäÖüĴæÆ÷1 +EMI_SDCONF2 EQU 0x1100001C ; SDRAMʱÐòÅäÖüĴæÆ÷2, SDRAM³õʼ»¯Óõ½µÄÅäÖÃÐÅÏ¢ +EMI_REMAPCONF EQU 0x11000020 ; Ƭѡ¿Õ¼ä¼°µØÖ·Ó³ÉäREMAPÅäÖüĴæÆ÷ + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled +NOINT EQU 0xc0 +MASK_MODE EQU 0x0000003F +MODE_SVC32 EQU 0x00000013 + +; Internal Memory Base Addresses +FLASH_BASE EQU 0x20000000 +RAM_BASE EQU 0x04000000 +SDRAM_BASE EQU 0x30000000 + +; Stack +Unused_Stack_Size EQU 0x00000100 +Svc_Stack_Size EQU 0x00001000 +Abt_Stack_Size EQU 0x00000000 +Fiq_Stack_Size EQU 0x00000000 +Irq_Stack_Size EQU 0x00001000 +Usr_Stack_Size EQU 0x00000000 + +;SVC STACK + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Svc_Stack SPACE Svc_Stack_Size +__initial_sp +Svc_Stack_Top + +;IRQ STACK + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Irq_Stack SPACE Irq_Stack_Size +Irq_Stack_Top + +;UNUSED STACK + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Unused_Stack SPACE Unused_Stack_Size +Unused_Stack_Top + + +; Heap +Heap_Size EQU 0x0000100 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT Heap_Mem +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + EXPORT Entry_Point +Entry_Point +Vectors LDR PC,Reset_Addr + LDR PC,Undef_Addr + LDR PC,SWI_Addr + LDR PC,PAbt_Addr + LDR PC,DAbt_Addr + NOP ; Reserved Vector + LDR PC,IRQ_Addr + LDR PC,FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B Abort_Handler +DAbt_Handler B Abort_Handler +FIQ_Handler B FIQ_Handler + +Abort_Handler PROC + ARM + EXPORT Abort_Handler +DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system. + ENDP + + +; Reset Handler + ;IMPORT __user_initial_stackheap + EXPORT Reset_Handler +Reset_Handler + +;**************************************************************** +;* Shutdown watchdog +;**************************************************************** + LDR R0,=RTC_CTR + LDR R1,=0x0 + STR R1,[R0] + +;**************************************************************** +;* shutdown interrupts +;**************************************************************** + MRS R0, CPSR + BIC R0, R0, #MASK_MODE + ORR R0, R0, #MODE_SVC32 + ORR R0, R0, #I_Bit + ORR R0, R0, #F_Bit + MSR CPSR_c, r0 + + LDR R0,=INTC_IER + LDR R1,=0x0 + STR R1,[R0] + LDR R0,=INTC_IMR + LDR R1,=0xFFFFFFFF + STR R1,[R0] + + LDR R0,=INTC_FIER + LDR R1,=0x0 + STR R1,[R0] + LDR R0,=INTC_FIMR + LDR R1,=0x0F + STR R1,[R0] + +;**************************************************************** +;* Initialize Stack Pointer +;**************************************************************** + + LDR SP, =Svc_Stack_Top ;init SP_svc + + MOV R4, #0xD2 ;chmod to irq and init SP_irq + MSR cpsr_c, R4 + LDR SP, =Irq_Stack_Top + + MOV R4, #0XD1 ;chomod to fiq and init SP_fiq + MSR cpsr_c, R4 + LDR SP, =Unused_Stack_Top + + MOV R4, #0XD7 ;chomod to abt and init SP_ABT + MSR cpsr_c, R4 + LDR SP, =Unused_Stack_Top + + MOV R4, #0XDB ;chomod to undf and init SP_UNDF + MSR cpsr_c, R4 + LDR SP, =Unused_Stack_Top + + ;chomod to abt and init SP_sys + MOV R4, #0xDF ;all interrupts disabled + MSR cpsr_c, R4 ;SYSTEM mode, @32-bit code mode + LDR SP, =Unused_Stack_Top + + MOV R4, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable + MSR cpsr_c, R4 + + + +;**************************************************************** +;* Initialize PMU & System Clock +;**************************************************************** + + LDR R4, =PMU_PCSR ; ´òËùÓÐÄ£¿éʱÖÓ + LDR R5, =0x0001ffff + STR R5, [ R4 ] + + LDR R4, =PMU_PLTR ; ÅäÖÃPLLÎȶ¨¹ý¶Èʱ¼äΪ±£ÊØÖµ50us*100M. + LDR R5, =0x00fa00fa + STR R5, [ R4 ] + + LDR R4, =PMU_PMDR ; ÓÉSLOWģʽ½øÈëNORMALģʽ + LDR R5, =0x00000001 + STR R5, [ R4 ] + + LDR R4, =PMU_PMCR ; ÅäÖÃϵͳʱÖÓΪ80MHz + LDR R5, =0x00004009 ; 400b -- 88M + STR R5, [ R4 ] + + ;PMU_PMCR¼Ä´æÆ÷µÚ15λÐèÒªÓдӵ͵½¸ßµÄ·­×ª£¬²ÅÄÜ´¥·¢PLLµÄʱÖÓÅäÖà + LDR R4, =PMU_PMCR + LDR R5, =0x0000c009 + STR R5, [ R4 ] + +;**************************************************************** +;* ³õʼ»¯EMI +;**************************************************************** + + IF :DEF:INIT_EMI + + LDR R4, =EMI_CSACONF ; CSAƬѡʱÐò²ÎÊýÅäÖà + LDR R5, =0x08a6a6a1 + STR R5, [ R4 ] + + LDR R4, =EMI_CSECONF ; CSEƬѡʱÐò²ÎÊýÅäÖÃ,×î±£ÊØÅäÖà + LDR R5, =0x8cfffff1 + STR R5, [ R4 ] + + LDR R4, =EMI_SDCONF1 ; SDRAM²ÎÊýÅäÖÃ1 + LDR R5, =0x1E104177 + STR R5, [ R4 ] + + LDR R4, =EMI_SDCONF2 ; SDRAM²ÎÊýÅäÖÃ2 + LDR R5, =0x80001860 + STR R5, [ R4 ] + + ENDIF + +; Copy Exception Vectors to Internal RAM + + IF :DEF:RAM_INTVEC + + ADR R8, Vectors ; Source + LDR R9, =RAM_BASE ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + + ENDIF + +; Remap on-chip RAM to address 0 + + IF :DEF:REMAP + + LDR R0, =EMI_REMAPCONF + IF :DEF:RAM_INTVEC + MOV R1, #0x80000000 + ELSE + MOV R1, #0x0000000b + ENDIF + STR R1, [R0, #0] ; Remap + + ENDIF + +;*************************************************************** +;* Open irq interrupt +;*************************************************************** + + MRS R4, cpsr + BIC R4, R4, #0x80 ; set bit7 to zero + MSR cpsr_c, R4 + +; Enter the C code + IMPORT __main + LDR R0,=__main + BX R0 + + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit :OR F_Bit :OR Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + + + ALIGN + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + EXPORT __initial_sp + + ELSE ;__MICROLIB +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Svc_Stack + Svc_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Svc_Stack + BX LR + ALIGN + ENDIF + END diff --git a/libcpu/arm/sep4020/trap.c b/libcpu/arm/sep4020/trap.c index f471fb2471f404c6253be6091e12b73bed584fd2..e7a6e369f982df0e1e69a8774f72f5c3d42f0c79 100644 --- a/libcpu/arm/sep4020/trap.c +++ b/libcpu/arm/sep4020/trap.c @@ -135,18 +135,18 @@ extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq() { - unsigned long intstat; + unsigned long intstat; rt_uint32_t i = 0; - rt_isr_handler_t isr_func; + rt_isr_handler_t isr_func; /*Get the final intrrupt source*/ - intstat = *(RP)(INTC_IFSR);; + intstat = *(RP)(INTC_IFSR);; - /*Shift to get the intrrupt number*/ - while(intstat != 1) - { - intstat = intstat >> 1; - i++; + /*Shift to get the intrrupt number*/ + while(intstat != 1) + { + intstat = intstat >> 1; + i++; } /* get interrupt service routine */ isr_func = isr_table[i]; diff --git a/libcpu/avr32/uc3/context_gcc.S b/libcpu/avr32/uc3/context_gcc.S index 1201626ba8afde9233e879b95f63dfda87b4cb1f..cbc08e24b217d1f5282e17db1225805eddf894a8 100644 --- a/libcpu/avr32/uc3/context_gcc.S +++ b/libcpu/avr32/uc3/context_gcc.S @@ -1,97 +1,97 @@ -/* - * File : context.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-03-27 Kyle First version - */ - -#define AVR32_SR 0 -#define AVR32_SR_GM_OFFSET 16 - -.text - -/* - * rt_base_t rt_hw_interrupt_disable() - */ -.globl rt_hw_interrupt_disable -.type rt_hw_interrupt_disable, %function -rt_hw_interrupt_disable: - ssrf AVR32_SR_GM_OFFSET - mov pc, lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ -.globl rt_hw_interrupt_enable -.type rt_hw_interrupt_enable, %function -rt_hw_interrupt_enable: - csrf AVR32_SR_GM_OFFSET - mov pc, lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)/* - * r8 --> from - * r9 --> to - */ -.globl rt_hw_context_switch -.type rt_hw_context_switch, %function -rt_hw_context_switch: - ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ - stm --sp, r8-r12, lr /* Push R8-R12, LR */ - st.w --sp, lr /* Push LR (instead of PC) */ - mfsr r8, AVR32_SR /* Read Status Register */ - cbr r8, AVR32_SR_GM_OFFSET /* Clear GM bit */ - st.w --sp, r8 /* Push SR */ - stm --sp, r0-r7 /* Push R0-R7 */ - /* Stack layout: R8-R12, LR, PC, SR, R0-R7 */ - - st.w r12[0], sp /* Store SP in preempted tasks TCB */ - ld.w sp, r11[0] /* Get new task stack pointer */ - - ldm sp++, r0-r7 /* pop R0-R7 */ - ld.w r8, sp++ /* pop SR */ - mtsr AVR32_SR, r8 /* Restore SR */ - ldm sp++, r8-r12, lr, pc/* Pop R8-R12, LR, PC and resume to thread */ - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * r0 --> to - */ -.globl rt_hw_context_switch_to -.type rt_hw_context_switch_to, %function -rt_hw_context_switch_to: - ld.w sp, r12[0] /* Get new task stack pointer */ - - ldm sp++, r0-r7 /* pop R0-R7 */ - ld.w r8, sp++ /* pop SR */ - mtsr AVR32_SR, r8 /* Restore SR */ - ldm sp++, r8-r12, lr, pc/* Pop R8-R12, LR, PC and resume execution */ - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -.type rt_hw_context_switch_interrupt, %function -rt_hw_context_switch_interrupt: - lda.w r8, rt_thread_switch_interrupt_flag - ld.w r9, r8[0] - cp.w r9, 1 - breq _reswitch - mov r9, 1 - st.w r8[0], r9 - lda.w r8, rt_interrupt_from_thread - st.w r8[0], r12 -_reswitch: - lda.w r8, rt_interrupt_to_thread - st.w r8[0], r11 - mov pc, lr +/* + * File : context.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-27 Kyle First version + */ + +#define AVR32_SR 0 +#define AVR32_SR_GM_OFFSET 16 + +.text + +/* + * rt_base_t rt_hw_interrupt_disable() + */ +.globl rt_hw_interrupt_disable +.type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + ssrf AVR32_SR_GM_OFFSET + mov pc, lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ +.globl rt_hw_interrupt_enable +.type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + csrf AVR32_SR_GM_OFFSET + mov pc, lr + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)/* + * r8 --> from + * r9 --> to + */ +.globl rt_hw_context_switch +.type rt_hw_context_switch, %function +rt_hw_context_switch: + ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ + stm --sp, r8-r12, lr /* Push R8-R12, LR */ + st.w --sp, lr /* Push LR (instead of PC) */ + mfsr r8, AVR32_SR /* Read Status Register */ + cbr r8, AVR32_SR_GM_OFFSET /* Clear GM bit */ + st.w --sp, r8 /* Push SR */ + stm --sp, r0-r7 /* Push R0-R7 */ + /* Stack layout: R8-R12, LR, PC, SR, R0-R7 */ + + st.w r12[0], sp /* Store SP in preempted tasks TCB */ + ld.w sp, r11[0] /* Get new task stack pointer */ + + ldm sp++, r0-r7 /* pop R0-R7 */ + ld.w r8, sp++ /* pop SR */ + mtsr AVR32_SR, r8 /* Restore SR */ + ldm sp++, r8-r12, lr, pc/* Pop R8-R12, LR, PC and resume to thread */ + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * r0 --> to + */ +.globl rt_hw_context_switch_to +.type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + ld.w sp, r12[0] /* Get new task stack pointer */ + + ldm sp++, r0-r7 /* pop R0-R7 */ + ld.w r8, sp++ /* pop SR */ + mtsr AVR32_SR, r8 /* Restore SR */ + ldm sp++, r8-r12, lr, pc/* Pop R8-R12, LR, PC and resume execution */ + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +.type rt_hw_context_switch_interrupt, %function +rt_hw_context_switch_interrupt: + lda.w r8, rt_thread_switch_interrupt_flag + ld.w r9, r8[0] + cp.w r9, 1 + breq _reswitch + mov r9, 1 + st.w r8[0], r9 + lda.w r8, rt_interrupt_from_thread + st.w r8[0], r12 +_reswitch: + lda.w r8, rt_interrupt_to_thread + st.w r8[0], r11 + mov pc, lr diff --git a/libcpu/avr32/uc3/cpu.c b/libcpu/avr32/uc3/cpu.c index 503f2737b70255c070bcf9a74b7bc13c464f15c1..b77e78dc5ba2cf94c4bb22862f0d06e7e589276b 100644 --- a/libcpu/avr32/uc3/cpu.c +++ b/libcpu/avr32/uc3/cpu.c @@ -1,42 +1,42 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-03-30 Kyle First version - */ - -#include - -/** - * @addtogroup AVR32UC3 - */ -/*@{*/ - -/** - * reset cpu by dog's time-out - * - */ -void rt_hw_cpu_reset() -{ - /*NOTREACHED*/ -} - -/** - * shutdown CPU - * - */ -void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - RT_ASSERT(0); -} - -/*@}*/ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-30 Kyle First version + */ + +#include + +/** + * @addtogroup AVR32UC3 + */ +/*@{*/ + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + /*NOTREACHED*/ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_kprintf("shutdown...\n"); + + RT_ASSERT(0); +} + +/*@}*/ diff --git a/libcpu/avr32/uc3/exception_gcc.S b/libcpu/avr32/uc3/exception_gcc.S index 1a36606f3bf7b0b9fedc34e09dd8f58efddfa9ec..d5051af2533232670c3c5bca8f33aec61729370b 100644 --- a/libcpu/avr32/uc3/exception_gcc.S +++ b/libcpu/avr32/uc3/exception_gcc.S @@ -1,4 +1,4 @@ -/* This file is part of the ATMEL AVR32-UC3-SoftwareFramework-1.6.0 Release */ +/* This file is part of the ATMEL AVR32-UC3-SoftwareFramework-1.6.0 Release */ /*This file is prepared for Doxygen automatic documentation generation.*/ /*! \file ********************************************************************* @@ -71,7 +71,7 @@ // Export symbol. .global _evba .type _evba, @function -_evba: +_evba: .org 0x000 // Unrecoverable Exception. @@ -193,107 +193,107 @@ _handle_Supervisor_Call: .balign 4 -_int0: +_int0: mov r12, 0 // Pass the int_level parameter to the _get_interrupt_handler function. call _get_interrupt_handler - cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. - breq _spint0 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. - call rt_interrupt_enter - icall r12 - call rt_interrupt_leave - ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ - lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ - ld.w r11, r12[0] - cp.w r11, 0 - brne _spint0 - lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ - ld.w r11, r12[0] - cp.w r11, 1 - breq rt_hw_context_switch_interrupt_do -_spint0: - csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + breq _spint0 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + call rt_interrupt_enter + icall r12 + call rt_interrupt_leave + ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ + lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ + ld.w r11, r12[0] + cp.w r11, 0 + brne _spint0 + lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ + ld.w r11, r12[0] + cp.w r11, 1 + breq rt_hw_context_switch_interrupt_do +_spint0: + csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ rete // If this was a spurious interrupt (R12 == NULL), return from event handler. - - -_int1: - mov r12, 1 // Pass the int_level parameter to the _get_interrupt_handler function. - call _get_interrupt_handler - cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. - breq _spint1 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. - call rt_interrupt_enter - icall r12 - call rt_interrupt_leave - ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ - lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ - ld.w r11, r12[0] - cp.w r11, 0 - brne _spint1 - lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ - ld.w r11, r12[0] - cp.w r11, 1 - breq rt_hw_context_switch_interrupt_do -_spint1: - csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ - rete // If this was a spurious interrupt (R12 == NULL), return from event handler. - - -_int2: - mov r12, 2 // Pass the int_level parameter to the _get_interrupt_handler function. - call _get_interrupt_handler - cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. - breq _spint2 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. - call rt_interrupt_enter - icall r12 - call rt_interrupt_leave - ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ - lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ - ld.w r11, r12[0] - cp.w r11, 0 - brne _spint2 - lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ - ld.w r11, r12[0] - cp.w r11, 1 - breq rt_hw_context_switch_interrupt_do -_spint2: - csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ - rete // If this was a spurious interrupt (R12 == NULL), return from event handler. - - -_int3: - mov r12, 3 // Pass the int_level parameter to the _get_interrupt_handler function. - call _get_interrupt_handler - cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. - breq _spint3 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. - call rt_interrupt_enter - icall r12 - call rt_interrupt_leave - ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ - lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ - ld.w r11, r12[0] - cp.w r11, 0 - brne _spint3 - lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ - ld.w r11, r12[0] - cp.w r11, 1 - breq rt_hw_context_switch_interrupt_do -_spint3: - csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ - rete // If this was a spurious interrupt (R12 == NULL), return from event handler. - - -rt_hw_context_switch_interrupt_do: - mov r11, 0 - st.w r12[0], r11 /* Clear rt_thread_switch_interrupt_flag */ - stm --sp, r0-r7 /* Push R0-R7 */ - lda.w r12, rt_interrupt_from_thread /* Get old thread SP */ - ld.w r12, r12[0] - lda.w r11, rt_interrupt_to_thread /* Get new thread SP */ - ld.w r11, r11[0] - st.w r12[0], sp /* Store old thead SP */ - ld.w sp, r11[0] /* Load new thread SP */ - ldm sp++, r0-r7 /* Pop R0-R7 (new thread) */ + + +_int1: + mov r12, 1 // Pass the int_level parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + breq _spint1 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + call rt_interrupt_enter + icall r12 + call rt_interrupt_leave + ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ + lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ + ld.w r11, r12[0] + cp.w r11, 0 + brne _spint1 + lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ + ld.w r11, r12[0] + cp.w r11, 1 + breq rt_hw_context_switch_interrupt_do +_spint1: + csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +_int2: + mov r12, 2 // Pass the int_level parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + breq _spint2 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + call rt_interrupt_enter + icall r12 + call rt_interrupt_leave + ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ + lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ + ld.w r11, r12[0] + cp.w r11, 0 + brne _spint2 + lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ + ld.w r11, r12[0] + cp.w r11, 1 + breq rt_hw_context_switch_interrupt_do +_spint2: + csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +_int3: + mov r12, 3 // Pass the int_level parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + breq _spint3 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + call rt_interrupt_enter + icall r12 + call rt_interrupt_leave + ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ + lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ + ld.w r11, r12[0] + cp.w r11, 0 + brne _spint3 + lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ + ld.w r11, r12[0] + cp.w r11, 1 + breq rt_hw_context_switch_interrupt_do +_spint3: + csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +rt_hw_context_switch_interrupt_do: + mov r11, 0 + st.w r12[0], r11 /* Clear rt_thread_switch_interrupt_flag */ + stm --sp, r0-r7 /* Push R0-R7 */ + lda.w r12, rt_interrupt_from_thread /* Get old thread SP */ + ld.w r12, r12[0] + lda.w r11, rt_interrupt_to_thread /* Get new thread SP */ + ld.w r11, r11[0] + st.w r12[0], sp /* Store old thead SP */ + ld.w sp, r11[0] /* Load new thread SP */ + ldm sp++, r0-r7 /* Pop R0-R7 (new thread) */ rete /* RETE pops R8-R12, LR, PC, SR automatically */ - + // Constant data area. diff --git a/libcpu/avr32/uc3/interrupt.c b/libcpu/avr32/uc3/interrupt.c index 7cfa71d50e159a52e7ddc95caaaf86cad0da1580..588ce9ae3d455903730c710733d32ba784991f4a 100644 --- a/libcpu/avr32/uc3/interrupt.c +++ b/libcpu/avr32/uc3/interrupt.c @@ -1,19 +1,19 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-03-30 Kyle Ported from STM32 to AVR32. - */ - -#include -#include "compiler.h" - -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-30 Kyle Ported from STM32 to AVR32. + */ + +#include +#include "compiler.h" + +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; diff --git a/libcpu/avr32/uc3/serial.c b/libcpu/avr32/uc3/serial.c index d5ce9defe852a9b51076366e170e834b6c753e08..4deac6b4ab27360102499513129c6ef96ef038b6 100644 --- a/libcpu/avr32/uc3/serial.c +++ b/libcpu/avr32/uc3/serial.c @@ -1,277 +1,277 @@ -/* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-02-05 Bernard first version - * 2009-10-25 Bernard fix rt_serial_read bug when there is no data - * in the buffer. - * 2010-03-29 Bernard cleanup code. - * 2010-03-30 Kyle Ported from STM32 to AVR32. - */ - -#include "serial.h" -#include "compiler.h" -#include "usart.h" - -struct rt_device _rt_usart_device; -struct avr32_serial_int_rx _rt_usart_rx; -struct avr32_serial_device uart = -{ - .uart_device = (avr32_usart_t *) &AVR32_USART1, - .int_rx = &_rt_usart_rx -}; - -/** - * @addtogroup AVR32UC3 - */ -/*@{*/ - -/* RT-Thread Device Interface */ -static rt_err_t rt_serial_init (rt_device_t dev) -{ - struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data; - - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = 0; - uart->int_rx->save_index = 0; - } - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - - return RT_EOK; -} - -static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t rt_serial_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct avr32_serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct avr32_serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* interrupt mode Rx */ - while (size) - { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - /* read a character */ - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size--; - - /* move to next position */ - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (usart_test_hit(uart->uart_device)) - { - *ptr = uart->uart_device->rhr & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct avr32_serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct avr32_serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx, does not support */ - RT_ASSERT(0); - } - else - { - /* polling mode */ - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - usart_putchar(uart->uart_device, (int) *ptr); - - ++ptr; --size; - } - } - else - { - /* write data directly */ - while (size) - { - usart_bw_write_char(uart->uart_device, (int) *ptr); - - ++ptr; --size; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) -{ - struct avr32_serial_device* uart; - - RT_ASSERT(dev != RT_NULL); - - uart = (struct avr32_serial_device*)dev->user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; -} - -/* - * serial register for STM32 - * support STM32F103VB and STM32F103ZE - */ -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial) -{ - RT_ASSERT(device != RT_NULL); - - if ((flag & RT_DEVICE_FLAG_DMA_RX) || - (flag & RT_DEVICE_FLAG_INT_TX)) - { - RT_ASSERT(0); - } - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); -} - -/* ISR for serial interrupt */ -void rt_hw_serial_isr(void) -{ - struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data; - rt_base_t level; - - if (usart_test_hit(uart->uart_device)) - { - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* save character */ - uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - /* invoke callback */ - if (_rt_usart_device.rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; - - _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length); - } - } - else - { - usart_reset_status(uart->uart_device); - } -} - -/*@}*/ +/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-02-05 Bernard first version + * 2009-10-25 Bernard fix rt_serial_read bug when there is no data + * in the buffer. + * 2010-03-29 Bernard cleanup code. + * 2010-03-30 Kyle Ported from STM32 to AVR32. + */ + +#include "serial.h" +#include "compiler.h" +#include "usart.h" + +struct rt_device _rt_usart_device; +struct avr32_serial_int_rx _rt_usart_rx; +struct avr32_serial_device uart = +{ + .uart_device = (avr32_usart_t *) &AVR32_USART1, + .int_rx = &_rt_usart_rx +}; + +/** + * @addtogroup AVR32UC3 + */ +/*@{*/ + +/* RT-Thread Device Interface */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = 0; + uart->int_rx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct avr32_serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct avr32_serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* interrupt mode Rx */ + while (size) + { + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + /* read a character */ + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size--; + + /* move to next position */ + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (usart_test_hit(uart->uart_device)) + { + *ptr = uart->uart_device->rhr & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct avr32_serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct avr32_serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx, does not support */ + RT_ASSERT(0); + } + else + { + /* polling mode */ + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + usart_putchar(uart->uart_device, (int) *ptr); + + ++ptr; --size; + } + } + else + { + /* write data directly */ + while (size) + { + usart_bw_write_char(uart->uart_device, (int) *ptr); + + ++ptr; --size; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) +{ + struct avr32_serial_device* uart; + + RT_ASSERT(dev != RT_NULL); + + uart = (struct avr32_serial_device*)dev->user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; +} + +/* + * serial register for STM32 + * support STM32F103VB and STM32F103ZE + */ +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial) +{ + RT_ASSERT(device != RT_NULL); + + if ((flag & RT_DEVICE_FLAG_DMA_RX) || + (flag & RT_DEVICE_FLAG_INT_TX)) + { + RT_ASSERT(0); + } + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); +} + +/* ISR for serial interrupt */ +void rt_hw_serial_isr(void) +{ + struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data; + rt_base_t level; + + if (usart_test_hit(uart->uart_device)) + { + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* save character */ + uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* invoke callback */ + if (_rt_usart_device.rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length); + } + } + else + { + usart_reset_status(uart->uart_device); + } +} + +/*@}*/ diff --git a/libcpu/avr32/uc3/serial.h b/libcpu/avr32/uc3/serial.h index cadbfd1850b49c6ee6f6b5f52bf8b38d84e4ed40..a17338701b85a04ff2ee18dbdc60451ec7146a74 100644 --- a/libcpu/avr32/uc3/serial.h +++ b/libcpu/avr32/uc3/serial.h @@ -1,53 +1,53 @@ -/* - * File : serial.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first version - * 2010-03-29 Bernard remove interrupt tx and DMA rx mode. - * 2010-03-30 Kyle Ported from STM32 to AVR32. - */ -#ifndef __RT_HW_SERIAL_H__ -#define __RT_HW_SERIAL_H__ - -#include -#include -#include "compiler.h" -#include "usart.h" - -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_DMA_NODE_SIZE 4 - -/* data node for Tx Mode */ -struct avr32_serial_data_node -{ - rt_uint8_t *data_ptr; - rt_size_t data_size; - struct avr32_serial_data_node *next, *prev; -}; - -struct avr32_serial_int_rx -{ - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; - -struct avr32_serial_device -{ - avr32_usart_t *uart_device; - - /* rx structure */ - struct avr32_serial_int_rx* int_rx; -}; - -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial); - -void rt_hw_serial_isr(); - -#endif +/* + * File : serial.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first version + * 2010-03-29 Bernard remove interrupt tx and DMA rx mode. + * 2010-03-30 Kyle Ported from STM32 to AVR32. + */ +#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include +#include +#include "compiler.h" +#include "usart.h" + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_DMA_NODE_SIZE 4 + +/* data node for Tx Mode */ +struct avr32_serial_data_node +{ + rt_uint8_t *data_ptr; + rt_size_t data_size; + struct avr32_serial_data_node *next, *prev; +}; + +struct avr32_serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct avr32_serial_device +{ + avr32_usart_t *uart_device; + + /* rx structure */ + struct avr32_serial_int_rx* int_rx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial); + +void rt_hw_serial_isr(); + +#endif diff --git a/libcpu/avr32/uc3/stack.c b/libcpu/avr32/uc3/stack.c index e187f84ce65eec648f34a158cf7cc479fda385fc..dd43b5edbcc2a86ccf926e9f6bcf64bda2fb1010 100644 --- a/libcpu/avr32/uc3/stack.c +++ b/libcpu/avr32/uc3/stack.c @@ -1,57 +1,57 @@ -/* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-03-30 Kyle First version - */ -#include - -/** - * @addtogroup AVR32UC3 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - unsigned long *stk; - - stk = (unsigned long *)stack_addr; - *(stk) = 0; /* r8 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r12 */ - *(--stk) = (unsigned long)texit; /* lr */ - *(--stk) = (unsigned long)tentry; /* entry point, pc */ - *(--stk) = 0x00600000; /* sr */ - *(--stk) = 0; /* r0 */ - *(--stk) = 0; /* r1 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r7 */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-30 Kyle First version + */ +#include + +/** + * @addtogroup AVR32UC3 + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + + stk = (unsigned long *)stack_addr; + *(stk) = 0; /* r8 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r12 */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = (unsigned long)tentry; /* entry point, pc */ + *(--stk) = 0x00600000; /* sr */ + *(--stk) = 0; /* r0 */ + *(--stk) = 0; /* r1 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r7 */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/blackfin/bf53x/context_vdsp.S b/libcpu/blackfin/bf53x/context_vdsp.S index b955d9ded7fda465dcd55645c0614c201f961241..e9cbdda0f1265a3509ba8fe6b2b13a189b4b4847 100644 --- a/libcpu/blackfin/bf53x/context_vdsp.S +++ b/libcpu/blackfin/bf53x/context_vdsp.S @@ -1,165 +1,165 @@ -/* - * File : context_vdsp.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2012-02-13 mojingxian First version - */ - -.global _rt_hw_interrupt_disable; -.global _rt_hw_interrupt_enable; -.global _interrupt_thread_switch; - -.extern _rt_interrupt_from_thread; -.extern _rt_interrupt_to_thread; -.extern _rt_thread_switch_interrupt_flag; - -.section/DOUBLE64 program; - -/* - * rt_base_t rt_hw_interrupt_disable(); - * return value in R0. - */ -_rt_hw_interrupt_disable: - CLI R0; - -_rt_hw_interrupt_disable.end: - NOP; - NOP; - NOP; - RTS; - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - * R0->level - */ -_rt_hw_interrupt_enable: - STI R0; - -_rt_hw_interrupt_enable.end: - NOP; - NOP; - NOP; - RTS; - -_interrupt_thread_switch: - /* Save context, interrupts disabled by IPEND[4] bit */ - [ -- SP ] = R0; - [ -- SP ] = P1; - [ -- SP ] = RETS; - [ -- SP ] = R1; - [ -- SP ] = R2; - [ -- SP ] = P0; - [ -- SP ] = P2; - [ -- SP ] = ASTAT; - R1 = RETI; /* IPEND[4] is currently set, globally disabling interrupts */ - /* IPEND[4] will stay set when RETI is saved through R1 */ - - [ -- SP ] = R1; - [ -- SP ] = (R7:3, P5:3); - [ -- SP ] = FP; - [ -- SP ] = I0; - [ -- SP ] = I1; - [ -- SP ] = I2; - [ -- SP ] = I3; - [ -- SP ] = B0; - [ -- SP ] = B1; - [ -- SP ] = B2; - [ -- SP ] = B3; - [ -- SP ] = L0; - [ -- SP ] = L1; - [ -- SP ] = L2; - [ -- SP ] = L3; - [ -- SP ] = M0; - [ -- SP ] = M1; - [ -- SP ] = M2; - [ -- SP ] = M3; - R1.L = A0.x; - [ -- SP ] = R1; - R1 = A0.w; - [ -- SP ] = R1; - R1.L = A1.x; - [ -- SP ] = R1; - R1 = A1.w; - [ -- SP ] = R1; - [ -- SP ] = LC0; - R3 = 0; - LC0 = R3; - [ -- SP ] = LC1; - R3 = 0; - LC1 = R3; - [ -- SP ] = LT0; - [ -- SP ] = LT1; - [ -- SP ] = LB0; - [ -- SP ] = LB1; - - /* Context save done so save SP in the TCB */ - P1.h = _rt_interrupt_from_thread; - P1.l = _rt_interrupt_from_thread; - P2 = [ P1 ]; - [ P2 ] = SP; - - /* clear rt_thread_switch_interrupt_flag to 0 */ - P1.h = _rt_thread_switch_interrupt_flag; - P1.l = _rt_thread_switch_interrupt_flag; - R0 = 0; - [ P1 ] = R0; - - /* Get a pointer to the high ready task's TCB */ - P1.h = _rt_interrupt_to_thread; - P1.l = _rt_interrupt_to_thread; - P2 = [ P1 ]; - SP = [ P2 ]; - - /* Restoring CPU context and return to task */ - LB1 = [ SP ++ ]; - LB0 = [ SP ++ ]; - LT1 = [ SP ++ ]; - LT0 = [ SP ++ ]; - LC1 = [ SP ++ ]; - LC0 = [ SP ++ ]; - R0 = [ SP ++ ]; - A1 = R0; - R0 = [ SP ++ ]; - A1.x = R0.L; - R0 = [ SP ++ ]; - A0 = R0; - R0 = [ SP ++ ]; - A0.x = R0.L; - M3 = [ SP ++ ]; - M2 = [ SP ++ ]; - M1 = [ SP ++ ]; - M0 = [ SP ++ ]; - L3 = [ SP ++ ]; - L2 = [ SP ++ ]; - L1 = [ SP ++ ]; - L0 = [ SP ++ ]; - B3 = [ SP ++ ]; - B2 = [ SP ++ ]; - B1 = [ SP ++ ]; - B0 = [ SP ++ ]; - I3 = [ SP ++ ]; - I2 = [ SP ++ ]; - I1 = [ SP ++ ]; - I0 = [ SP ++ ]; - FP = [ SP ++ ]; - (R7:3, P5:3) = [ SP ++ ]; - RETI = [ SP ++ ]; /* IPEND[4] will stay set when RETI popped from stack */ - ASTAT = [ SP ++ ]; - P2 = [ SP ++ ]; - P0 = [ SP ++ ]; - R2 = [ SP ++ ]; - R1 = [ SP ++ ]; - RETS = [ SP ++ ]; - P1 = [ SP ++ ]; - R0 = [ SP ++ ]; - -_interrupt_thread_switch.end: - RTI; - +/* + * File : context_vdsp.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-02-13 mojingxian First version + */ + +.global _rt_hw_interrupt_disable; +.global _rt_hw_interrupt_enable; +.global _interrupt_thread_switch; + +.extern _rt_interrupt_from_thread; +.extern _rt_interrupt_to_thread; +.extern _rt_thread_switch_interrupt_flag; + +.section/DOUBLE64 program; + +/* + * rt_base_t rt_hw_interrupt_disable(); + * return value in R0. + */ +_rt_hw_interrupt_disable: + CLI R0; + +_rt_hw_interrupt_disable.end: + NOP; + NOP; + NOP; + RTS; + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + * R0->level + */ +_rt_hw_interrupt_enable: + STI R0; + +_rt_hw_interrupt_enable.end: + NOP; + NOP; + NOP; + RTS; + +_interrupt_thread_switch: + /* Save context, interrupts disabled by IPEND[4] bit */ + [ -- SP ] = R0; + [ -- SP ] = P1; + [ -- SP ] = RETS; + [ -- SP ] = R1; + [ -- SP ] = R2; + [ -- SP ] = P0; + [ -- SP ] = P2; + [ -- SP ] = ASTAT; + R1 = RETI; /* IPEND[4] is currently set, globally disabling interrupts */ + /* IPEND[4] will stay set when RETI is saved through R1 */ + + [ -- SP ] = R1; + [ -- SP ] = (R7:3, P5:3); + [ -- SP ] = FP; + [ -- SP ] = I0; + [ -- SP ] = I1; + [ -- SP ] = I2; + [ -- SP ] = I3; + [ -- SP ] = B0; + [ -- SP ] = B1; + [ -- SP ] = B2; + [ -- SP ] = B3; + [ -- SP ] = L0; + [ -- SP ] = L1; + [ -- SP ] = L2; + [ -- SP ] = L3; + [ -- SP ] = M0; + [ -- SP ] = M1; + [ -- SP ] = M2; + [ -- SP ] = M3; + R1.L = A0.x; + [ -- SP ] = R1; + R1 = A0.w; + [ -- SP ] = R1; + R1.L = A1.x; + [ -- SP ] = R1; + R1 = A1.w; + [ -- SP ] = R1; + [ -- SP ] = LC0; + R3 = 0; + LC0 = R3; + [ -- SP ] = LC1; + R3 = 0; + LC1 = R3; + [ -- SP ] = LT0; + [ -- SP ] = LT1; + [ -- SP ] = LB0; + [ -- SP ] = LB1; + + /* Context save done so save SP in the TCB */ + P1.h = _rt_interrupt_from_thread; + P1.l = _rt_interrupt_from_thread; + P2 = [ P1 ]; + [ P2 ] = SP; + + /* clear rt_thread_switch_interrupt_flag to 0 */ + P1.h = _rt_thread_switch_interrupt_flag; + P1.l = _rt_thread_switch_interrupt_flag; + R0 = 0; + [ P1 ] = R0; + + /* Get a pointer to the high ready task's TCB */ + P1.h = _rt_interrupt_to_thread; + P1.l = _rt_interrupt_to_thread; + P2 = [ P1 ]; + SP = [ P2 ]; + + /* Restoring CPU context and return to task */ + LB1 = [ SP ++ ]; + LB0 = [ SP ++ ]; + LT1 = [ SP ++ ]; + LT0 = [ SP ++ ]; + LC1 = [ SP ++ ]; + LC0 = [ SP ++ ]; + R0 = [ SP ++ ]; + A1 = R0; + R0 = [ SP ++ ]; + A1.x = R0.L; + R0 = [ SP ++ ]; + A0 = R0; + R0 = [ SP ++ ]; + A0.x = R0.L; + M3 = [ SP ++ ]; + M2 = [ SP ++ ]; + M1 = [ SP ++ ]; + M0 = [ SP ++ ]; + L3 = [ SP ++ ]; + L2 = [ SP ++ ]; + L1 = [ SP ++ ]; + L0 = [ SP ++ ]; + B3 = [ SP ++ ]; + B2 = [ SP ++ ]; + B1 = [ SP ++ ]; + B0 = [ SP ++ ]; + I3 = [ SP ++ ]; + I2 = [ SP ++ ]; + I1 = [ SP ++ ]; + I0 = [ SP ++ ]; + FP = [ SP ++ ]; + (R7:3, P5:3) = [ SP ++ ]; + RETI = [ SP ++ ]; /* IPEND[4] will stay set when RETI popped from stack */ + ASTAT = [ SP ++ ]; + P2 = [ SP ++ ]; + P0 = [ SP ++ ]; + R2 = [ SP ++ ]; + R1 = [ SP ++ ]; + RETS = [ SP ++ ]; + P1 = [ SP ++ ]; + R0 = [ SP ++ ]; + +_interrupt_thread_switch.end: + RTI; + diff --git a/libcpu/blackfin/bf53x/serial.h b/libcpu/blackfin/bf53x/serial.h index 8eef14546ba6ed20201de1e8bfff45a78cffc60d..8d85193634ccf921ba3880af35306908f364ef49 100644 --- a/libcpu/blackfin/bf53x/serial.h +++ b/libcpu/blackfin/bf53x/serial.h @@ -1,56 +1,56 @@ -#ifndef __RT_HW_SERIAL_H__ -#define __RT_HW_SERIAL_H__ - -#include -#include - -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ - -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 - -struct serial_int_rx -{ - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; - -struct serial_int_tx -{ - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; -}; - -typedef struct uartport -{ - volatile rt_uint16_t rbr_thr; //receive buffer register and transmit hold register - volatile rt_uint16_t reserved0; - volatile rt_uint16_t reserved1; - volatile rt_uint16_t reserved2; - volatile rt_uint16_t reserved3; - volatile rt_uint16_t reserved4; - volatile rt_uint16_t reserved5; - volatile rt_uint16_t reserved6; - volatile rt_uint16_t reserved7; - volatile rt_uint16_t reserved8; - volatile rt_uint16_t lsr; //line status register -}uartport; - -struct serial_device -{ - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; - - /* tx structure */ - struct serial_int_tx* int_tx; -}; - -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); - -void rt_hw_serial_isr(rt_device_t device); - -#endif +#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include +#include + +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +typedef struct uartport +{ + volatile rt_uint16_t rbr_thr; //receive buffer register and transmit hold register + volatile rt_uint16_t reserved0; + volatile rt_uint16_t reserved1; + volatile rt_uint16_t reserved2; + volatile rt_uint16_t reserved3; + volatile rt_uint16_t reserved4; + volatile rt_uint16_t reserved5; + volatile rt_uint16_t reserved6; + volatile rt_uint16_t reserved7; + volatile rt_uint16_t reserved8; + volatile rt_uint16_t lsr; //line status register +}uartport; + +struct serial_device +{ + uartport* uart_device; + + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); + +void rt_hw_serial_isr(rt_device_t device); + +#endif diff --git a/libcpu/ia32/backtrace.c b/libcpu/ia32/backtrace.c index d7a152469b5c42e683b652b09847368c77cef4eb..b8f094d90fc9c0fe5200966abd7093900de59e6d 100644 --- a/libcpu/ia32/backtrace.c +++ b/libcpu/ia32/backtrace.c @@ -1,20 +1,20 @@ -/* - * File : backtrace.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version - */ - -#include - -void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) -{ - /* no implementation */ -} +/* + * File : backtrace.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-07-29 Bernard first version + */ + +#include + +void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) +{ + /* no implementation */ +} diff --git a/libcpu/ia32/hdisr_gcc.S b/libcpu/ia32/hdisr_gcc.S index cc622ff52cd6e2c399276fcaf0a19870a41a784d..29f200772f863f4d960de4649f4cb42c82c0ef5e 100644 --- a/libcpu/ia32/hdisr_gcc.S +++ b/libcpu/ia32/hdisr_gcc.S @@ -59,7 +59,7 @@ HDINTERRUPTFNC(irq15, 15) .globl _hdinterrupts .type _hdinterrupts,@function .globl rt_interrupt_enter -.globl rt_interrupt_leave +.globl rt_interrupt_leave .globl isr_table .globl rt_thread_switch_interrupt_flag .globl rt_interrupt_from_thread @@ -73,9 +73,9 @@ _hdinterrupts: movw %ax, %ds movw %ax, %es pushl %esp - + call rt_interrupt_enter - + movl %esp, %eax /* copy esp to eax */ addl $0x2c, %eax /* move to vector address */ movl (%eax), %eax /* vector(eax) = *eax */ diff --git a/libcpu/ia32/interrupt.c b/libcpu/ia32/interrupt.c index 91df04c0ce221ebff2cbe17aa2e5f4d16f53dce5..01086a6266fc2dbe874cd1faed4cd06fd493732a 100644 --- a/libcpu/ia32/interrupt.c +++ b/libcpu/ia32/interrupt.c @@ -1,118 +1,118 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - */ - -#include -#include - -#include - -extern rt_uint32_t rt_interrupt_nest; -extern void rt_hw_idt_init(void); - -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/* exception and interrupt handler table */ -rt_isr_handler_t isr_table[MAX_HANDLERS]; -rt_uint16_t irq_mask_8259A = 0xFFFF; - -/** - * @addtogroup I386 - */ -/*@{*/ - -/** - * This function initializes 8259 interrupt controller - */ -void rt_hw_pic_init() -{ - outb(IO_PIC1, 0x11); - outb(IO_PIC1+1, IRQ_OFFSET); - outb(IO_PIC1+1, 1<> 8)); - } - - /* init interrupt nest, and context */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -void rt_hw_interrupt_handle(int vector) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function initializes interrupt descript table and 8259 interrupt controller - * - */ -void rt_hw_interrupt_init(void) -{ - rt_hw_idt_init(); - rt_hw_pic_init(); -} - -void rt_hw_interrupt_umask(int vector) -{ - irq_mask_8259A = irq_mask_8259A&~(1<> 8)); -} - -void rt_hw_interrupt_mask(int vector) -{ - irq_mask_8259A = irq_mask_8259A | (1<> 8)); -} - -void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) -{ - if(vector < MAX_HANDLERS) - { - if (*old_handler != RT_NULL) *old_handler = isr_table[vector]; - if (new_handler != RT_NULL) isr_table[vector] = new_handler; - } -} - -rt_base_t rt_hw_interrupt_disable(void) -{ - rt_base_t level; - - __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); - return level; -} - -void rt_hw_interrupt_enable(rt_base_t level) -{ - __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); -} - -/*@}*/ +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ + +#include +#include + +#include + +extern rt_uint32_t rt_interrupt_nest; +extern void rt_hw_idt_init(void); + +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/* exception and interrupt handler table */ +rt_isr_handler_t isr_table[MAX_HANDLERS]; +rt_uint16_t irq_mask_8259A = 0xFFFF; + +/** + * @addtogroup I386 + */ +/*@{*/ + +/** + * This function initializes 8259 interrupt controller + */ +void rt_hw_pic_init() +{ + outb(IO_PIC1, 0x11); + outb(IO_PIC1+1, IRQ_OFFSET); + outb(IO_PIC1+1, 1<> 8)); + } + + /* init interrupt nest, and context */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +void rt_hw_interrupt_handle(int vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function initializes interrupt descript table and 8259 interrupt controller + * + */ +void rt_hw_interrupt_init(void) +{ + rt_hw_idt_init(); + rt_hw_pic_init(); +} + +void rt_hw_interrupt_umask(int vector) +{ + irq_mask_8259A = irq_mask_8259A&~(1<> 8)); +} + +void rt_hw_interrupt_mask(int vector) +{ + irq_mask_8259A = irq_mask_8259A | (1<> 8)); +} + +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + if(vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = isr_table[vector]; + if (new_handler != RT_NULL) isr_table[vector] = new_handler; + } +} + +rt_base_t rt_hw_interrupt_disable(void) +{ + rt_base_t level; + + __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); + return level; +} + +void rt_hw_interrupt_enable(rt_base_t level) +{ + __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); +} + +/*@}*/ diff --git a/libcpu/ia32/showmem.c b/libcpu/ia32/showmem.c index c171a9bcd75b9206d3fa2949ddb021d5cccd7b3f..38f037f83d622a6d2472c45ab7520a26f41f5a18 100644 --- a/libcpu/ia32/showmem.c +++ b/libcpu/ia32/showmem.c @@ -1,42 +1,42 @@ -/* - * File : showmem.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version from QiuYi implementation - */ - -#include - -void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) -{ - int i = 0, j =0; - - RT_ASSERT(addr); - - addr = addr & ~0xF; - size = 4*((size + 3)/4); - - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); - - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - - addr += 4; - i++; - } - - rt_kprintf("\n"); - } - - return; -} +/* + * File : showmem.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-07-29 Bernard first version from QiuYi implementation + */ + +#include + +void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) +{ + int i = 0, j =0; + + RT_ASSERT(addr); + + addr = addr & ~0xF; + size = 4*((size + 3)/4); + + while(i < size) + { + rt_kprintf("0x%08x: ", addr ); + + for(j=0; j<4; j++) + { + rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); + + addr += 4; + i++; + } + + rt_kprintf("\n"); + } + + return; +} diff --git a/libcpu/ia32/stack.c b/libcpu/ia32/stack.c index 0331819f71591415934568008ed4f9059e852b76..9d656a73d6ba10ea392f83974fd22be9463044aa 100644 --- a/libcpu/ia32/stack.c +++ b/libcpu/ia32/stack.c @@ -1,59 +1,59 @@ -/* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - */ - -#include - -#include - -/** - * @addtogroup I386 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - unsigned long *stk; - - stk = (unsigned long *)stack_addr; - *(--stk) = (unsigned long)parameter; - *(--stk) = (unsigned long)texit; - *(--stk) = 0x200; /*flags*/ - *(--stk) = 0x08; /*cs*/ - *(--stk) = (unsigned long)tentry; /*eip*/ - *(--stk) = 0; /*irqno*/ - *(--stk) = 0x10; /*ds*/ - *(--stk) = 0x10; /*es*/ - *(--stk) = 0; /*eax*/ - *(--stk) = 0; /*ecx*/ - *(--stk) = 0; /*edx*/ - *(--stk) = 0; /*ebx*/ - *(--stk) = 0; /*esp*/ - *(--stk) = 0; /*ebp*/ - *(--stk) = 0; /*esi*/ - *(--stk) = 0; /*edi*/ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} -/*@}*/ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ + +#include + +#include + +/** + * @addtogroup I386 + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + + stk = (unsigned long *)stack_addr; + *(--stk) = (unsigned long)parameter; + *(--stk) = (unsigned long)texit; + *(--stk) = 0x200; /*flags*/ + *(--stk) = 0x08; /*cs*/ + *(--stk) = (unsigned long)tentry; /*eip*/ + *(--stk) = 0; /*irqno*/ + *(--stk) = 0x10; /*ds*/ + *(--stk) = 0x10; /*es*/ + *(--stk) = 0; /*eax*/ + *(--stk) = 0; /*ecx*/ + *(--stk) = 0; /*edx*/ + *(--stk) = 0; /*ebx*/ + *(--stk) = 0; /*esp*/ + *(--stk) = 0; /*ebp*/ + *(--stk) = 0; /*esi*/ + *(--stk) = 0; /*edi*/ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} +/*@}*/ diff --git a/libcpu/ia32/start_gcc.S b/libcpu/ia32/start_gcc.S index 650309a7f3d7d0fff51206a3969af6ccb4cf976d..84adc83fe24fc697f3fc1c52de5a3ab7e5963066 100644 --- a/libcpu/ia32/start_gcc.S +++ b/libcpu/ia32/start_gcc.S @@ -1,97 +1,97 @@ -/* - * File : start.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-09-15 QiuYi The first version. - * 2012-02-15 aozima update. - */ - -/* the magic number for the multiboot header. */ -#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 - -/* the flags for the multiboot header. */ -#define MULTIBOOT_HEADER_FLAGS 0x00000003 - -#define CONFIG_STACKSIZE 8192 - -/** - * @addtogroup I386 - */ -/*@{*/ - -.section .init, "ax" - -/* the system entry */ -.globl _start -_start: - jmp multiboot_entry - - /* Align 32 bits boundary. */ - .align 4 - - /* multiboot header. */ -multiboot_header: - /* magic */ - .long MULTIBOOT_HEADER_MAGIC - /* flags */ - .long MULTIBOOT_HEADER_FLAGS - /* checksum */ - .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) - -multiboot_entry: - movl $(_end + 0x1000),%esp - - /* reset eflags. */ - pushl $0 - popf - - /*rebuild globe describe table*/ - lgdt mygdtdesc - - movl $0x10,%eax - movw %ax,%ds - movw %ax,%es - movw %ax,%ss - ljmp $0x08, $relocated - -relocated: - /* push the pointer to the multiboot information structure. */ - pushl %ebx - - /* push the magic value. */ - pushl %eax - - call rtthread_startup - - /* never get here */ -spin: - hlt - jmp spin - -.data -.p2align 2 -mygdt: - .word 0,0,0,0 - - .word 0x07FF /* 8Mb - limit=2047 */ - .word 0x0000 - .word 0x9A00 /* code read/exec */ - .word 0x00C0 - - .word 0x07FF /* 8Mb - limit=2047 */ - .word 0x0000 - .word 0x9200 /* data read/write */ - .word 0x00C0 - -mygdtdesc: - .word 0x17 - .long mygdt - -/*@}*/ +/* + * File : start.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-09-15 QiuYi The first version. + * 2012-02-15 aozima update. + */ + +/* the magic number for the multiboot header. */ +#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 + +/* the flags for the multiboot header. */ +#define MULTIBOOT_HEADER_FLAGS 0x00000003 + +#define CONFIG_STACKSIZE 8192 + +/** + * @addtogroup I386 + */ +/*@{*/ + +.section .init, "ax" + +/* the system entry */ +.globl _start +_start: + jmp multiboot_entry + + /* Align 32 bits boundary. */ + .align 4 + + /* multiboot header. */ +multiboot_header: + /* magic */ + .long MULTIBOOT_HEADER_MAGIC + /* flags */ + .long MULTIBOOT_HEADER_FLAGS + /* checksum */ + .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) + +multiboot_entry: + movl $(_end + 0x1000),%esp + + /* reset eflags. */ + pushl $0 + popf + + /*rebuild globe describe table*/ + lgdt mygdtdesc + + movl $0x10,%eax + movw %ax,%ds + movw %ax,%es + movw %ax,%ss + ljmp $0x08, $relocated + +relocated: + /* push the pointer to the multiboot information structure. */ + pushl %ebx + + /* push the magic value. */ + pushl %eax + + call rtthread_startup + + /* never get here */ +spin: + hlt + jmp spin + +.data +.p2align 2 +mygdt: + .word 0,0,0,0 + + .word 0x07FF /* 8Mb - limit=2047 */ + .word 0x0000 + .word 0x9A00 /* code read/exec */ + .word 0x00C0 + + .word 0x07FF /* 8Mb - limit=2047 */ + .word 0x0000 + .word 0x9200 /* data read/write */ + .word 0x00C0 + +mygdtdesc: + .word 0x17 + .long mygdt + +/*@}*/ diff --git a/libcpu/ia32/trap.c b/libcpu/ia32/trap.c index 10595dc5a1158bce63ba4ac766d733ea96a91154..52b9e65ea3537690b918c050a13ab6ee2552c373 100644 --- a/libcpu/ia32/trap.c +++ b/libcpu/ia32/trap.c @@ -1,108 +1,108 @@ -/* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - */ - -#include -#include - -#include - -/* Interrupt descriptor table. (Must be built at run time because - * shifted function addresses can't be represented in relocation records.) - */ -struct Gatedesc idt[256] = { {0}, }; -struct Pseudodesc idt_pd = -{ - 0, sizeof(idt) - 1, (unsigned long) idt, -}; - -/* exception and interrupt handler table */ -extern rt_isr_handler_t isr_table[]; -extern rt_isr_handler_t trap_func[]; -extern rt_isr_handler_t hdinterrupt_func[]; - -/** - * @addtogroup I386 - */ -/*@{*/ - -/** - * this function initializes the interrupt descript table - * - */ -void rt_hw_idt_init(void) -{ - extern void Xdefault; - int i, j, func; - - for(i=0; i +#include + +#include + +/* Interrupt descriptor table. (Must be built at run time because + * shifted function addresses can't be represented in relocation records.) + */ +struct Gatedesc idt[256] = { {0}, }; +struct Pseudodesc idt_pd = +{ + 0, sizeof(idt) - 1, (unsigned long) idt, +}; + +/* exception and interrupt handler table */ +extern rt_isr_handler_t isr_table[]; +extern rt_isr_handler_t trap_func[]; +extern rt_isr_handler_t hdinterrupt_func[]; + +/** + * @addtogroup I386 + */ +/*@{*/ + +/** + * this function initializes the interrupt descript table + * + */ +void rt_hw_idt_init(void) +{ + extern void Xdefault; + int i, j, func; + + for(i=0; i to - * this fucntion is used to perform the first thread switch - */ -rt_hw_context_switch_to: - MOV.W R0, A0 - LDC [A0], ISP - POPM R0,R1,R2,R3,A0,A1,SB,FB - REIT - - END +/* + * File : context.asm + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-04-09 fify the first version + * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction + * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34 + * + * For : Renesas M16C + * Toolchain : IAR's EW for M16C v3.401 + */ + + RSEG CSTACK + + RSEG ISTACK + + RSEG CODE(1) + + EXTERN rt_interrupt_from_thread + EXTERN rt_interrupt_to_thread + + PUBLIC rt_hw_interrupt_disable + PUBLIC rt_hw_interrupt_enable + PUBLIC rt_hw_context_switch_to + PUBLIC os_context_switch + +rt_hw_interrupt_disable: + STC FLG, R0 ;fify 20100419 + FCLR I + RTS + +rt_hw_interrupt_enable: + LDC R0, FLG ;fify 20100419 + RTS + + .EVEN +os_context_switch: + PUSHM R0,R1,R2,R3,A0,A1,SB,FB + + MOV.W rt_interrupt_from_thread, A0 + STC ISP, [A0] + MOV.W rt_interrupt_to_thread, A0 + LDC [A0], ISP + + POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack + REIT ; Return from interrup + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + * this fucntion is used to perform the first thread switch + */ +rt_hw_context_switch_to: + MOV.W R0, A0 + LDC [A0], ISP + POPM R0,R1,R2,R3,A0,A1,SB,FB + REIT + + END diff --git a/libcpu/m16c/m16c62p/context_iar.asm b/libcpu/m16c/m16c62p/context_iar.asm index bd75341f4b5cdc6a2aa1c1080b15e1e6f5e7e37f..9415b2bdeac7f1f80c8c5de6aa22906fdbcaed7c 100644 --- a/libcpu/m16c/m16c62p/context_iar.asm +++ b/libcpu/m16c/m16c62p/context_iar.asm @@ -1,66 +1,66 @@ -/* - * File : context.asm - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-04-09 fify the first version - * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction - * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34 - * - * For : Renesas M16C - * Toolchain : IAR's EW for M16C v3.401 - */ - - RSEG CSTACK - - RSEG ISTACK - - RSEG CODE(1) - - EXTERN rt_interrupt_from_thread - EXTERN rt_interrupt_to_thread - - PUBLIC rt_hw_interrupt_disable - PUBLIC rt_hw_interrupt_enable - PUBLIC rt_hw_context_switch_to - PUBLIC os_context_switch - -rt_hw_interrupt_disable: - STC FLG, R0 ;fify 20100419 - FCLR I - RTS - -rt_hw_interrupt_enable: - LDC R0, FLG ;fify 20100419 - RTS - - .EVEN -os_context_switch: - PUSHM R0,R1,R2,R3,A0,A1,SB,FB - - MOV.W rt_interrupt_from_thread, A0 - STC ISP, [A0] - MOV.W rt_interrupt_to_thread, A0 - LDC [A0], ISP - - POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack - REIT ; Return from interrup - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - * this fucntion is used to perform the first thread switch - */ -rt_hw_context_switch_to: - MOV.W R0, A0 - LDC [A0], ISP - POPM R0,R1,R2,R3,A0,A1,SB,FB - REIT - - END +/* + * File : context.asm + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-04-09 fify the first version + * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction + * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34 + * + * For : Renesas M16C + * Toolchain : IAR's EW for M16C v3.401 + */ + + RSEG CSTACK + + RSEG ISTACK + + RSEG CODE(1) + + EXTERN rt_interrupt_from_thread + EXTERN rt_interrupt_to_thread + + PUBLIC rt_hw_interrupt_disable + PUBLIC rt_hw_interrupt_enable + PUBLIC rt_hw_context_switch_to + PUBLIC os_context_switch + +rt_hw_interrupt_disable: + STC FLG, R0 ;fify 20100419 + FCLR I + RTS + +rt_hw_interrupt_enable: + LDC R0, FLG ;fify 20100419 + RTS + + .EVEN +os_context_switch: + PUSHM R0,R1,R2,R3,A0,A1,SB,FB + + MOV.W rt_interrupt_from_thread, A0 + STC ISP, [A0] + MOV.W rt_interrupt_to_thread, A0 + LDC [A0], ISP + + POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack + REIT ; Return from interrup + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + * this fucntion is used to perform the first thread switch + */ +rt_hw_context_switch_to: + MOV.W R0, A0 + LDC [A0], ISP + POPM R0,R1,R2,R3,A0,A1,SB,FB + REIT + + END diff --git a/libcpu/m16c/m16c62p/cpuport.c b/libcpu/m16c/m16c62p/cpuport.c index 2957bd3d2c4b752057f5c61b4d7ee046ec97cc30..c66f73b72706fc64c835bc8f94b200de268f3bff 100644 --- a/libcpu/m16c/m16c62p/cpuport.c +++ b/libcpu/m16c/m16c62p/cpuport.c @@ -1,116 +1,116 @@ -/* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-02-23 Bernard the first version - * 2012-09-25 lgnq save texit address in to thread stack - */ - -#include - -extern volatile rt_uint8_t rt_interrupt_nest; - -/* switch flag on interrupt and thread pointer to save switch record */ -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint8_t rt_thread_switch_interrupt_flag; - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, - void *parameter, - rt_uint8_t *stack_addr, - void *texit) -{ - rt_uint16_t *pstk16; - rt_uint16_t flag; - - flag = 0x0040; - pstk16 = (rt_uint16_t *)stack_addr; - - *pstk16-- = (rt_uint32_t)texit >> 16L; - *pstk16-- = (rt_uint32_t)texit & 0x0000FFFFL; - - /* Simulate ISR entry */ - *pstk16-- = (flag&0x00FF) | /* The lowest byte of the FLAG register */ - (((rt_uint32_t)tentry>>8)&0x00000F00) | /* The highest nibble of the PC register */ - ((flag<<4)&0xF000); /* The highest nibble of the FLAG register */ - *pstk16-- = (((rt_uint32_t)tentry)&0x0000FFFF); /* The lowest bytes of the PC register */ - - /* Save registers onto stack frame */ - *pstk16-- = (rt_uint16_t)0xFBFB; /* FB register */ - *pstk16-- = (rt_uint16_t)0x3B3B; /* SB register */ - *pstk16-- = (rt_uint16_t)0xA1A1; /* A1 register */ - *pstk16-- = (rt_uint16_t)0xA0A0; /* A0 register */ - *pstk16-- = (rt_uint16_t)0x3333; /* R3 register */ - *pstk16-- = (rt_uint32_t)parameter >> 16L; /* Pass argument in R2 register */ - *pstk16-- = (rt_uint32_t)parameter & 0x0000FFFFL; /* Pass argument in R1 register */ - *pstk16 = (rt_uint16_t)0x0000; /* R0 register */ - - /* return task's current stack address */ - return (rt_uint8_t *)pstk16; -} - -void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) -{ - rt_interrupt_from_thread = from; - rt_interrupt_to_thread = to; - asm("INT #0"); -} - -void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) -{ - if (rt_thread_switch_interrupt_flag != 1) - { - rt_thread_switch_interrupt_flag = 1; - rt_interrupt_from_thread = from; - } - rt_interrupt_to_thread = to; -} - -#if defined(__GNUC__) -rt_base_t rt_hw_interrupt_disable(void) -{ - register rt_uint16_t temp; - - asm("STC FLG, %0":"=r" (temp)); - asm("FCLR I"); - - return (rt_base_t)temp; -} - -void rt_hw_interrupt_enable(rt_base_t level) -{ - register rt_uint16_t temp; - - temp = level & 0xffff; - asm("LDC %0, FLG": :"r" (temp)); -} +/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-23 Bernard the first version + * 2012-09-25 lgnq save texit address in to thread stack + */ + +#include + +extern volatile rt_uint8_t rt_interrupt_nest; + +/* switch flag on interrupt and thread pointer to save switch record */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint8_t rt_thread_switch_interrupt_flag; + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + rt_uint16_t *pstk16; + rt_uint16_t flag; + + flag = 0x0040; + pstk16 = (rt_uint16_t *)stack_addr; + + *pstk16-- = (rt_uint32_t)texit >> 16L; + *pstk16-- = (rt_uint32_t)texit & 0x0000FFFFL; + + /* Simulate ISR entry */ + *pstk16-- = (flag&0x00FF) | /* The lowest byte of the FLAG register */ + (((rt_uint32_t)tentry>>8)&0x00000F00) | /* The highest nibble of the PC register */ + ((flag<<4)&0xF000); /* The highest nibble of the FLAG register */ + *pstk16-- = (((rt_uint32_t)tentry)&0x0000FFFF); /* The lowest bytes of the PC register */ + + /* Save registers onto stack frame */ + *pstk16-- = (rt_uint16_t)0xFBFB; /* FB register */ + *pstk16-- = (rt_uint16_t)0x3B3B; /* SB register */ + *pstk16-- = (rt_uint16_t)0xA1A1; /* A1 register */ + *pstk16-- = (rt_uint16_t)0xA0A0; /* A0 register */ + *pstk16-- = (rt_uint16_t)0x3333; /* R3 register */ + *pstk16-- = (rt_uint32_t)parameter >> 16L; /* Pass argument in R2 register */ + *pstk16-- = (rt_uint32_t)parameter & 0x0000FFFFL; /* Pass argument in R1 register */ + *pstk16 = (rt_uint16_t)0x0000; /* R0 register */ + + /* return task's current stack address */ + return (rt_uint8_t *)pstk16; +} + +void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) +{ + rt_interrupt_from_thread = from; + rt_interrupt_to_thread = to; + asm("INT #0"); +} + +void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) +{ + if (rt_thread_switch_interrupt_flag != 1) + { + rt_thread_switch_interrupt_flag = 1; + rt_interrupt_from_thread = from; + } + rt_interrupt_to_thread = to; +} + +#if defined(__GNUC__) +rt_base_t rt_hw_interrupt_disable(void) +{ + register rt_uint16_t temp; + + asm("STC FLG, %0":"=r" (temp)); + asm("FCLR I"); + + return (rt_base_t)temp; +} + +void rt_hw_interrupt_enable(rt_base_t level) +{ + register rt_uint16_t temp; + + temp = level & 0xffff; + asm("LDC %0, FLG": :"r" (temp)); +} #endif \ No newline at end of file diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h index 7a4fb81398826c2a34374ad97f7876eb3f36e3dc..190e8b110e70c83bde74bae85a43ffe818e1314e 100644 --- a/libcpu/mips/common/asm.h +++ b/libcpu/mips/common/asm.h @@ -1,220 +1,220 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle - * Copyright (C) 1999 by Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - * Copyright (C) 2002 Maciej W. Rozycki - * - * Some useful macros for MIPS assembler code - * - * Some of the routines below contain useless nops that will be optimized - * away by gas in -O mode. These nops are however required to fill delay - * slots in noreorder mode. - */ -#ifndef __ASM_H__ -#define __ASM_H__ - -/* - * LEAF - declare leaf routine - */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp,0,ra - -/* - * NESTED - declare nested routine entry point - */ -#define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp, framesize, rpc - -/* - * END - mark end of function - */ -#define END(function) \ - .end function; \ - .size function,.-function - -/* - * EXPORT - export definition of symbol - */ -#define EXPORT(symbol) \ - .globl symbol; \ -symbol: - -/* - * FEXPORT - export definition of a function symbol - */ -#define FEXPORT(symbol) \ - .globl symbol; \ - .type symbol,@function; \ -symbol: - -/* - * Global data declaration with size. - */ -#define EXPORTS(name,sz) \ - .globl name; \ - .type name,@object; \ - .size name,sz; \ -name: - -/* - * Weak data declaration with size. - */ -#define WEXPORT(name,sz) \ - .weakext name; \ - .type name,@object; \ - .size name,sz; \ -name: - -/* - * Global data reference with size. - */ -#define IMPORT(name, size) \ - .extern name,size - -/* - * Global zeroed data. - */ -#define BSS(name,size) \ - .type name,@object; \ - .comm name,size - -/* - * Local zeroed data. - */ -#define LBSS(name,size) \ - .lcomm name,size - - -/* - * ABS - export absolute symbol - */ -#define ABS(symbol,value) \ - .globl symbol; \ -symbol = value - - -#define TEXT(msg) \ - .pushsection .data; \ -8: .asciiz msg; \ - .popsection; - - -#define ENTRY(name) \ - .globl name; \ - .align 2; \ - .ent name,0; \ - name##: - -/* - * Macros to handle different pointer/register sizes for 32/64-bit code - */ - -/* - * Size of a register - */ -#define SZREG 4 - - -/* - * Use the following macros in assemblercode to load/store registers, - * pointers etc. - */ -#define REG_S sw -#define REG_L lw -#define REG_SUBU subu -#define REG_ADDU addu - - -/* - * How to add/sub/load/store/shift C int variables. - */ -#define INT_ADD add -#define INT_ADDU addu -#define INT_ADDI addi -#define INT_ADDIU addiu -#define INT_SUB sub -#define INT_SUBU subu -#define INT_L lw -#define INT_S sw -#define INT_SLL sll -#define INT_SLLV sllv -#define INT_SRL srl -#define INT_SRLV srlv -#define INT_SRA sra -#define INT_SRAV srav - - - -/* - * How to add/sub/load/store/shift C long variables. - */ -#define LONG_ADD add -#define LONG_ADDU addu -#define LONG_ADDI addi -#define LONG_ADDIU addiu -#define LONG_SUB sub -#define LONG_SUBU subu -#define LONG_L lw -#define LONG_S sw -#define LONG_SLL sll -#define LONG_SLLV sllv -#define LONG_SRL srl -#define LONG_SRLV srlv -#define LONG_SRA sra -#define LONG_SRAV srav - -#define LONG .word -#define LONGSIZE 4 -#define LONGMASK 3 -#define LONGLOG 2 - - - -/* - * How to add/sub/load/store/shift pointers. - */ -#define PTR_ADD add -#define PTR_ADDU addu -#define PTR_ADDI addi -#define PTR_ADDIU addiu -#define PTR_SUB sub -#define PTR_SUBU subu -#define PTR_L lw -#define PTR_S sw -#define PTR_LA la -#define PTR_SLL sll -#define PTR_SLLV sllv -#define PTR_SRL srl -#define PTR_SRLV srlv -#define PTR_SRA sra -#define PTR_SRAV srav - -#define PTR_SCALESHIFT 2 - -#define PTR .word -#define PTRSIZE 4 -#define PTRLOG 2 - - -/* - * Some cp0 registers were extended to 64bit for MIPS III. - */ -#define MFC0 mfc0 -#define MTC0 mtc0 - - -#define SSNOP sll zero, zero, 1 - -#endif /* end of __ASM_H__ */ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle + * Copyright (C) 1999 by Silicon Graphics, Inc. + * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2002 Maciej W. Rozycki + * + * Some useful macros for MIPS assembler code + * + * Some of the routines below contain useless nops that will be optimized + * away by gas in -O mode. These nops are however required to fill delay + * slots in noreorder mode. + */ +#ifndef __ASM_H__ +#define __ASM_H__ + +/* + * LEAF - declare leaf routine + */ +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp,0,ra + +/* + * NESTED - declare nested routine entry point + */ +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp, framesize, rpc + +/* + * END - mark end of function + */ +#define END(function) \ + .end function; \ + .size function,.-function + +/* + * EXPORT - export definition of symbol + */ +#define EXPORT(symbol) \ + .globl symbol; \ +symbol: + +/* + * FEXPORT - export definition of a function symbol + */ +#define FEXPORT(symbol) \ + .globl symbol; \ + .type symbol,@function; \ +symbol: + +/* + * Global data declaration with size. + */ +#define EXPORTS(name,sz) \ + .globl name; \ + .type name,@object; \ + .size name,sz; \ +name: + +/* + * Weak data declaration with size. + */ +#define WEXPORT(name,sz) \ + .weakext name; \ + .type name,@object; \ + .size name,sz; \ +name: + +/* + * Global data reference with size. + */ +#define IMPORT(name, size) \ + .extern name,size + +/* + * Global zeroed data. + */ +#define BSS(name,size) \ + .type name,@object; \ + .comm name,size + +/* + * Local zeroed data. + */ +#define LBSS(name,size) \ + .lcomm name,size + + +/* + * ABS - export absolute symbol + */ +#define ABS(symbol,value) \ + .globl symbol; \ +symbol = value + + +#define TEXT(msg) \ + .pushsection .data; \ +8: .asciiz msg; \ + .popsection; + + +#define ENTRY(name) \ + .globl name; \ + .align 2; \ + .ent name,0; \ + name##: + +/* + * Macros to handle different pointer/register sizes for 32/64-bit code + */ + +/* + * Size of a register + */ +#define SZREG 4 + + +/* + * Use the following macros in assemblercode to load/store registers, + * pointers etc. + */ +#define REG_S sw +#define REG_L lw +#define REG_SUBU subu +#define REG_ADDU addu + + +/* + * How to add/sub/load/store/shift C int variables. + */ +#define INT_ADD add +#define INT_ADDU addu +#define INT_ADDI addi +#define INT_ADDIU addiu +#define INT_SUB sub +#define INT_SUBU subu +#define INT_L lw +#define INT_S sw +#define INT_SLL sll +#define INT_SLLV sllv +#define INT_SRL srl +#define INT_SRLV srlv +#define INT_SRA sra +#define INT_SRAV srav + + + +/* + * How to add/sub/load/store/shift C long variables. + */ +#define LONG_ADD add +#define LONG_ADDU addu +#define LONG_ADDI addi +#define LONG_ADDIU addiu +#define LONG_SUB sub +#define LONG_SUBU subu +#define LONG_L lw +#define LONG_S sw +#define LONG_SLL sll +#define LONG_SLLV sllv +#define LONG_SRL srl +#define LONG_SRLV srlv +#define LONG_SRA sra +#define LONG_SRAV srav + +#define LONG .word +#define LONGSIZE 4 +#define LONGMASK 3 +#define LONGLOG 2 + + + +/* + * How to add/sub/load/store/shift pointers. + */ +#define PTR_ADD add +#define PTR_ADDU addu +#define PTR_ADDI addi +#define PTR_ADDIU addiu +#define PTR_SUB sub +#define PTR_SUBU subu +#define PTR_L lw +#define PTR_S sw +#define PTR_LA la +#define PTR_SLL sll +#define PTR_SLLV sllv +#define PTR_SRL srl +#define PTR_SRLV srlv +#define PTR_SRA sra +#define PTR_SRAV srav + +#define PTR_SCALESHIFT 2 + +#define PTR .word +#define PTRSIZE 4 +#define PTRLOG 2 + + +/* + * Some cp0 registers were extended to 64bit for MIPS III. + */ +#define MFC0 mfc0 +#define MTC0 mtc0 + + +#define SSNOP sll zero, zero, 1 + +#endif /* end of __ASM_H__ */ diff --git a/libcpu/mips/common/cache.c b/libcpu/mips/common/cache.c index de9a112f50da3cbe8424704a8a13103c09a2c1af..e5a9945e3ea3c45eaec8085b67fb1e883c98f462 100644 --- a/libcpu/mips/common/cache.c +++ b/libcpu/mips/common/cache.c @@ -1,114 +1,114 @@ -/* - * File : cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include -#include "mipscfg.h" -#include "cache.h" - - -extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size); -void r4k_cache_init(void) -{ - cache_init(dcache_size, cpu_dcache_line_size()); -} - -void r4k_cache_flush_all(void) -{ - blast_dcache16(); - blast_icache16(); -} - -void r4k_icache_flush_all(void) -{ - blast_icache16(); -} - -void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) -{ - rt_ubase_t end, a; - - if (size > icache_size) - { - blast_icache16(); - } - else - { - rt_ubase_t ic_lsize = cpu_icache_line_size(); - - a = addr & ~(ic_lsize - 1); - end = ((addr + size) - 1) & ~(ic_lsize - 1); - while (1) - { - flush_icache_line(a); - if (a == end) - break; - a += ic_lsize; - } - } -} - -void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) -{ - rt_ubase_t end, a; - rt_ubase_t ic_lsize = cpu_icache_line_size(); - - a = addr & ~(ic_lsize - 1); - end = ((addr + size) - 1) & ~(ic_lsize - 1); - while (1) - { - lock_icache_line(a); - if (a == end) - break; - a += ic_lsize; - } -} - -void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) -{ - rt_ubase_t end, a; - rt_ubase_t dc_lsize = cpu_dcache_line_size(); - - a = addr & ~(dc_lsize - 1); - end = ((addr + size) - 1) & ~(dc_lsize - 1); - while (1) - { - invalidate_dcache_line(a); - if (a == end) - break; - a += dc_lsize; - } -} - -void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) -{ - rt_ubase_t end, a; - - if (size >= dcache_size) - { - blast_dcache16(); - } - else - { - rt_ubase_t dc_lsize = cpu_dcache_line_size(); - - a = addr & ~(dc_lsize - 1); - end = ((addr + size) - 1) & ~(dc_lsize - 1); - while (1) - { - flush_dcache_line(a); - if (a == end) - break; - a += dc_lsize; - } - } -} +/* + * File : cache.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#include +#include "mipscfg.h" +#include "cache.h" + + +extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size); +void r4k_cache_init(void) +{ + cache_init(dcache_size, cpu_dcache_line_size()); +} + +void r4k_cache_flush_all(void) +{ + blast_dcache16(); + blast_icache16(); +} + +void r4k_icache_flush_all(void) +{ + blast_icache16(); +} + +void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + + if (size > icache_size) + { + blast_icache16(); + } + else + { + rt_ubase_t ic_lsize = cpu_icache_line_size(); + + a = addr & ~(ic_lsize - 1); + end = ((addr + size) - 1) & ~(ic_lsize - 1); + while (1) + { + flush_icache_line(a); + if (a == end) + break; + a += ic_lsize; + } + } +} + +void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + rt_ubase_t ic_lsize = cpu_icache_line_size(); + + a = addr & ~(ic_lsize - 1); + end = ((addr + size) - 1) & ~(ic_lsize - 1); + while (1) + { + lock_icache_line(a); + if (a == end) + break; + a += ic_lsize; + } +} + +void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + rt_ubase_t dc_lsize = cpu_dcache_line_size(); + + a = addr & ~(dc_lsize - 1); + end = ((addr + size) - 1) & ~(dc_lsize - 1); + while (1) + { + invalidate_dcache_line(a); + if (a == end) + break; + a += dc_lsize; + } +} + +void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + + if (size >= dcache_size) + { + blast_dcache16(); + } + else + { + rt_ubase_t dc_lsize = cpu_dcache_line_size(); + + a = addr & ~(dc_lsize - 1); + end = ((addr + size) - 1) & ~(dc_lsize - 1); + while (1) + { + flush_dcache_line(a); + if (a == end) + break; + a += dc_lsize; + } + } +} diff --git a/libcpu/mips/common/cache.h b/libcpu/mips/common/cache.h index 579be8ff9b16b11a743e25558aaacdd592b48185..1c7cf41324a67d25da8df928d8c33f091cf59ae1 100644 --- a/libcpu/mips/common/cache.h +++ b/libcpu/mips/common/cache.h @@ -1,232 +1,232 @@ -/* - * Cache operations for the cache instruction. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle - * (C) Copyright 1999 Silicon Graphics, Inc. - */ -#ifndef __CACHE_H__ -#define __CACHE_H__ - - -#define KUSEG 0x00000000 -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 -#define KSEG2 0xc0000000 -#define KSEG3 0xe0000000 - -/* - * Cache Operations available on all MIPS processors with R4000-style caches - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 - -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - -/* - *The lock state is cleared by executing an Index -Invalidate, Index Writeback Invalidate, Hit -Invalidate, or Hit Writeback Invalidate -operation to the locked line, or via an Index -Store Tag operation with the lock bit reset in -the TagLo register. - */ -#define Fetch_And_Lock_I 0x1c -#define Fetch_And_Lock_D 0x1d -/* - * R4000-specific cacheops - */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 - -/* - * R4000SC and R4400SC-specific cacheops - */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -/* - * R5000-specific cacheops - */ -#define R5K_Page_Invalidate_S 0x17 - -/* - * RM7000-specific cacheops - */ -#define Page_Invalidate_T 0x16 - -/* - * R1000-specific cacheops - * - * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. - * Most of the _S cacheops are identical to the R4000SC _SD cacheops. - */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f - - -#ifndef __ASSEMBLER__ - -#ifndef dcache_size -#define dcache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size) -#endif - -#ifndef icache_size -#define icache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size) -#endif - -#ifndef cpu_dcache_line_size -#define cpu_dcache_line_size() g_mips_core.icache_line_size -#endif - -#ifndef cpu_icache_line_size -#define cpu_icache_line_size() g_mips_core.icache_line_size -#endif - -#define cache_op(op, addr) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set mips0 \n" \ - " .set reorder" \ - : \ - : "i" (op), "m" (*(unsigned char *)(addr))) - -#define cache16_unroll32(base, op) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ - " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ - " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ - " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ - " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ - " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ - " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ - " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ - " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ - " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ - " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ - " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ - " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ - " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ - " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ - : \ - : "r" (base), \ - "i" (op)); - - -static inline void flush_icache_line_indexed(rt_ubase_t addr) -{ - cache_op(Index_Invalidate_I, addr); -} - -static inline void flush_dcache_line_indexed(rt_ubase_t addr) -{ - cache_op(Index_Writeback_Inv_D, addr); -} - -static inline void flush_icache_line(rt_ubase_t addr) -{ - cache_op(Hit_Invalidate_I, addr); -} - -static inline void lock_icache_line(rt_ubase_t addr) -{ - cache_op(Fetch_And_Lock_I, addr); -} - -static inline void lock_dcache_line(rt_ubase_t addr) -{ - cache_op(Fetch_And_Lock_D, addr); -} - -static inline void flush_dcache_line(rt_ubase_t addr) -{ - cache_op(Hit_Writeback_Inv_D, addr); -} - -static inline void invalidate_dcache_line(rt_ubase_t addr) -{ - cache_op(Hit_Invalidate_D, addr); -} - -static inline void blast_dcache16(void) -{ - rt_ubase_t start = KSEG0; - rt_ubase_t end = start + dcache_size; - rt_ubase_t addr; - - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr, Index_Writeback_Inv_D); -} - -static inline void inv_dcache16(void) -{ - rt_ubase_t start = KSEG0; - rt_ubase_t end = start + dcache_size; - rt_ubase_t addr; - - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr, Hit_Invalidate_D); -} - -static inline void blast_icache16(void) -{ - rt_ubase_t start = KSEG0; - rt_ubase_t end = start + icache_size; - rt_ubase_t addr; - - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr, Index_Invalidate_I); -} - - - -void r4k_cache_init(void); -void r4k_cache_flush_all(void); -void r4k_icache_flush_all(void); -void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size); -void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size); -void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size); -void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size); - -#endif /*end of __ASSEMBLER__ */ - -#endif /* end of __CACHE_H__ */ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __CACHE_H__ +#define __CACHE_H__ + + +#define KUSEG 0x00000000 +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 +#define KSEG2 0xc0000000 +#define KSEG3 0xe0000000 + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 + +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + +/* + *The lock state is cleared by executing an Index +Invalidate, Index Writeback Invalidate, Hit +Invalidate, or Hit Writeback Invalidate +operation to the locked line, or via an Index +Store Tag operation with the lock bit reset in +the TagLo register. + */ +#define Fetch_And_Lock_I 0x1c +#define Fetch_And_Lock_D 0x1d +/* + * R4000-specific cacheops + */ +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +/* + * R5000-specific cacheops + */ +#define R5K_Page_Invalidate_S 0x17 + +/* + * RM7000-specific cacheops + */ +#define Page_Invalidate_T 0x16 + +/* + * R1000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + + +#ifndef __ASSEMBLER__ + +#ifndef dcache_size +#define dcache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size) +#endif + +#ifndef icache_size +#define icache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size) +#endif + +#ifndef cpu_dcache_line_size +#define cpu_dcache_line_size() g_mips_core.icache_line_size +#endif + +#ifndef cpu_icache_line_size +#define cpu_icache_line_size() g_mips_core.icache_line_size +#endif + +#define cache_op(op, addr) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set mips0 \n" \ + " .set reorder" \ + : \ + : "i" (op), "m" (*(unsigned char *)(addr))) + +#define cache16_unroll32(base, op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ + " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ + " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ + " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ + " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ + " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ + " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ + " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ + " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ + " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ + " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ + " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ + " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ + " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ + " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ + "i" (op)); + + +static inline void flush_icache_line_indexed(rt_ubase_t addr) +{ + cache_op(Index_Invalidate_I, addr); +} + +static inline void flush_dcache_line_indexed(rt_ubase_t addr) +{ + cache_op(Index_Writeback_Inv_D, addr); +} + +static inline void flush_icache_line(rt_ubase_t addr) +{ + cache_op(Hit_Invalidate_I, addr); +} + +static inline void lock_icache_line(rt_ubase_t addr) +{ + cache_op(Fetch_And_Lock_I, addr); +} + +static inline void lock_dcache_line(rt_ubase_t addr) +{ + cache_op(Fetch_And_Lock_D, addr); +} + +static inline void flush_dcache_line(rt_ubase_t addr) +{ + cache_op(Hit_Writeback_Inv_D, addr); +} + +static inline void invalidate_dcache_line(rt_ubase_t addr) +{ + cache_op(Hit_Invalidate_D, addr); +} + +static inline void blast_dcache16(void) +{ + rt_ubase_t start = KSEG0; + rt_ubase_t end = start + dcache_size; + rt_ubase_t addr; + + for (addr = start; addr < end; addr += 0x200) + cache16_unroll32(addr, Index_Writeback_Inv_D); +} + +static inline void inv_dcache16(void) +{ + rt_ubase_t start = KSEG0; + rt_ubase_t end = start + dcache_size; + rt_ubase_t addr; + + for (addr = start; addr < end; addr += 0x200) + cache16_unroll32(addr, Hit_Invalidate_D); +} + +static inline void blast_icache16(void) +{ + rt_ubase_t start = KSEG0; + rt_ubase_t end = start + icache_size; + rt_ubase_t addr; + + for (addr = start; addr < end; addr += 0x200) + cache16_unroll32(addr, Index_Invalidate_I); +} + + + +void r4k_cache_init(void); +void r4k_cache_flush_all(void); +void r4k_icache_flush_all(void); +void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size); +void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size); +void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size); +void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size); + +#endif /*end of __ASSEMBLER__ */ + +#endif /* end of __CACHE_H__ */ diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h index cd776a77cb3c1d66e0f7e0ec600a46c06c98f464..2cb03d20e7f727215c37ca9a8d7f52b906234e43 100644 --- a/libcpu/mips/common/exception.h +++ b/libcpu/mips/common/exception.h @@ -1,166 +1,166 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#ifndef __EXCEPTION_H__ -#define __EXCEPTION_H__ - - -/* - * important register numbers - */ -#define REG_EPC 37 -#define REG_FP 72 -#define REG_SP 29 - -/* - * Stack layout for the GDB exception handler - * Derived from the stack layout described in asm-mips/stackframe.h - * - * The first PTRSIZE*6 bytes are argument save space for C subroutines. - */ -#define NUMREGS 90 - -#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ -#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ -#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ -#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ -#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ -#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ -#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ -#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ -#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ -#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ -#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ -#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ -#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ -#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ -#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ -#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ -#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ -#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ -#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ -#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ -#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ -#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ -#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ -#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ -#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ -#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ -#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ -#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ -#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ -#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ -#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ -#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ - -/* - * Saved special registers - */ -#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ -#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ -#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ -#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ -#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ -#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ - -///* -// * Saved floating point registers -// */ -//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ -//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ -//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ -//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ -//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ -//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ -//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ -//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ -//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ -//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ -//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ -//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ -//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ -//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ -//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ -//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ -//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ -//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ -//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ -//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ -//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ -//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ -//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ -//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ -//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ -//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ -//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ -//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ -//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ -//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ -//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ -//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ -// -//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ -//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ -//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ -// -//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ -// -///* -// * Again, CP0 registers -// */ -//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ -#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */ -#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */ - -#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ -#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ -#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ -#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ -#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ -#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ -#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ -#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ -#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ -#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ -#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ -#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ -#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ -#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ -#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ - -#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) - -/* - * This is the same as above, but for the high-level - * part of the INT stub. - */ -typedef struct pt_regs_s -{ - /* Saved main processor registers. */ - rt_base_t regs[32]; - /* Saved special registers. */ - rt_base_t cp0_status; - rt_base_t hi; - rt_base_t lo; - rt_base_t cp0_badvaddr; - rt_base_t cp0_cause; - rt_base_t cp0_epc; -} pt_regs_t; - -typedef void (* exception_func_t)(pt_regs_t *regs); - -extern exception_func_t sys_exception_handlers[]; -exception_func_t rt_set_except_vector(int n, exception_func_t func); -void install_default_execpt_handle(void); - -#endif /* end of __EXCEPTION_H__ */ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#ifndef __EXCEPTION_H__ +#define __EXCEPTION_H__ + + +/* + * important register numbers + */ +#define REG_EPC 37 +#define REG_FP 72 +#define REG_SP 29 + +/* + * Stack layout for the GDB exception handler + * Derived from the stack layout described in asm-mips/stackframe.h + * + * The first PTRSIZE*6 bytes are argument save space for C subroutines. + */ +#define NUMREGS 90 + +#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ +#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ +#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ +#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ +#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ +#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ +#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ +#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ +#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ +#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ +#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ +#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ +#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ +#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ +#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ +#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ +#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ +#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ +#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ +#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ +#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ +#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ +#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ +#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ +#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ +#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ +#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ +#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ +#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ +#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ +#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ +#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ + +/* + * Saved special registers + */ +#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ +#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ +#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ +#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ +#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ +#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ + +///* +// * Saved floating point registers +// */ +//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ +//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ +//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ +//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ +//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ +//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ +//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ +//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ +//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ +//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ +//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ +//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ +//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ +//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ +//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ +//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ +//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ +//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ +//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ +//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ +//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ +//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ +//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ +//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ +//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ +//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ +//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ +//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ +//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ +//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ +//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ +//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ +// +//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ +//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ +//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ +// +//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ +// +///* +// * Again, CP0 registers +// */ +//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ +#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */ +#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */ + +#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ +#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ +#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ +#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ +#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ +#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ +#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ +#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ +#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ +#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ +#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ +#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ +#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ +#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ +#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ + +#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) + +/* + * This is the same as above, but for the high-level + * part of the INT stub. + */ +typedef struct pt_regs_s +{ + /* Saved main processor registers. */ + rt_base_t regs[32]; + /* Saved special registers. */ + rt_base_t cp0_status; + rt_base_t hi; + rt_base_t lo; + rt_base_t cp0_badvaddr; + rt_base_t cp0_cause; + rt_base_t cp0_epc; +} pt_regs_t; + +typedef void (* exception_func_t)(pt_regs_t *regs); + +extern exception_func_t sys_exception_handlers[]; +exception_func_t rt_set_except_vector(int n, exception_func_t func); +void install_default_execpt_handle(void); + +#endif /* end of __EXCEPTION_H__ */ diff --git a/libcpu/mips/common/mips.inc b/libcpu/mips/common/mips.inc index c1e3e2d4185124cda361d99466da0bfdcc822fb4..a4cd55911e8bb8b1652df6eb87e931ab3db98377 100644 --- a/libcpu/mips/common/mips.inc +++ b/libcpu/mips/common/mips.inc @@ -1,52 +1,52 @@ -/* - * File : mips.inc - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 sangwei first version - */ -#ifndef __MIPS_INC__ -#define __MIPS_INC__ - -#define zero $0 /* wired zero */ -// #define at $1 -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ - -#endif /* end of __MIPS_INC__ */ +/* + * File : mips.inc + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 sangwei first version + */ +#ifndef __MIPS_INC__ +#define __MIPS_INC__ + +#define zero $0 /* wired zero */ +// #define at $1 +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ +#define ra $31 /* return address */ + +#endif /* end of __MIPS_INC__ */ diff --git a/libcpu/mips/common/mipscfg.h b/libcpu/mips/common/mipscfg.h index 1e64d99db9440aee9262200303e3b0fa542fbf5a..b4f30615f87fe4f76a4dfda7334d5d5baded7660 100644 --- a/libcpu/mips/common/mipscfg.h +++ b/libcpu/mips/common/mipscfg.h @@ -1,32 +1,32 @@ -/* - * File : mipscfg.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-27 swkyer first version - */ -#ifndef __MIPSCFG_H__ -#define __MIPSCFG_H__ - - -typedef struct mips32_core_cfg -{ - rt_uint16_t icache_line_size; - rt_uint16_t icache_lines_per_way; - rt_uint16_t icache_ways; - rt_uint16_t dcache_line_size; - rt_uint16_t dcache_lines_per_way; - rt_uint16_t dcache_ways; - - rt_uint16_t max_tlb_entries; /* number of tlb entry */ -} mips32_core_cfg_t; - -extern mips32_core_cfg_t g_mips_core; - -#endif /* end of __MIPSCFG_H__ */ +/* + * File : mipscfg.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#ifndef __MIPSCFG_H__ +#define __MIPSCFG_H__ + + +typedef struct mips32_core_cfg +{ + rt_uint16_t icache_line_size; + rt_uint16_t icache_lines_per_way; + rt_uint16_t icache_ways; + rt_uint16_t dcache_line_size; + rt_uint16_t dcache_lines_per_way; + rt_uint16_t dcache_ways; + + rt_uint16_t max_tlb_entries; /* number of tlb entry */ +} mips32_core_cfg_t; + +extern mips32_core_cfg_t g_mips_core; + +#endif /* end of __MIPSCFG_H__ */ diff --git a/libcpu/mips/common/mipsregs.h b/libcpu/mips/common/mipsregs.h index d29b59d23732a3622d044f961275faa8b4c4ab4a..888d4b13b549258ab92a16ba6302cba8876d3501 100644 --- a/libcpu/mips/common/mipsregs.h +++ b/libcpu/mips/common/mipsregs.h @@ -1,616 +1,616 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - * Modified for further R[236]000 support by Paul M. Antoine, 1996. - * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 07 MIPS Technologies, Inc. - * Copyright (C) 2003, 2004 Maciej W. Rozycki - * - * Change Logs: - * Date Author Notes - * - */ -#ifndef __MIPSREGS_H__ -#define __MIPSREGS_H__ - -/* - * The following macros are especially useful for __asm__ - * inline assembler. - */ -#ifndef __STR -#define __STR(x) #x -#endif -#ifndef STR -#define STR(x) __STR(x) -#endif - -/* - * Configure language - */ -#ifdef __ASSEMBLY__ -#define _ULCAST_ -#else -#define _ULCAST_ (unsigned long) -#endif - -/* - * Coprocessor 0 register names - */ -#define CP0_INDEX $0 -#define CP0_RANDOM $1 -#define CP0_ENTRYLO0 $2 -#define CP0_ENTRYLO1 $3 -#define CP0_CONF $3 -#define CP0_CONTEXT $4 -#define CP0_PAGEMASK $5 -#define CP0_WIRED $6 -#define CP0_INFO $7 -#define CP0_BADVADDR $8 -#define CP0_COUNT $9 -#define CP0_ENTRYHI $10 -#define CP0_COMPARE $11 -#define CP0_STATUS $12 -#define CP0_CAUSE $13 -#define CP0_EPC $14 -#define CP0_PRID $15 -#define CP0_CONFIG $16 -#define CP0_LLADDR $17 -#define CP0_WATCHLO $18 -#define CP0_WATCHHI $19 -#define CP0_XCONTEXT $20 -#define CP0_FRAMEMASK $21 -#define CP0_DIAGNOSTIC $22 -#define CP0_DEBUG $23 -#define CP0_DEPC $24 -#define CP0_PERFORMANCE $25 -#define CP0_ECC $26 -#define CP0_CACHEERR $27 -#define CP0_TAGLO $28 -#define CP0_TAGHI $29 -#define CP0_ERROREPC $30 -#define CP0_DESAVE $31 - -/* - * R4640/R4650 cp0 register names. These registers are listed - * here only for completeness; without MMU these CPUs are not useable - * by Linux. A future ELKS port might take make Linux run on them - * though ... - */ -#define CP0_IBASE $0 -#define CP0_IBOUND $1 -#define CP0_DBASE $2 -#define CP0_DBOUND $3 -#define CP0_CALG $17 -#define CP0_IWATCH $18 -#define CP0_DWATCH $19 - -/* - * Coprocessor 0 Set 1 register names - */ -#define CP0_S1_DERRADDR0 $26 -#define CP0_S1_DERRADDR1 $27 -#define CP0_S1_INTCONTROL $20 - -/* - * Coprocessor 0 Set 2 register names - */ -#define CP0_S2_SRSCTL $12 /* MIPSR2 */ - -/* - * Coprocessor 0 Set 3 register names - */ -#define CP0_S3_SRSMAP $12 /* MIPSR2 */ - -/* - * TX39 Series - */ -#define CP0_TX39_CACHE $7 - -/* - * Coprocessor 1 (FPU) register names - */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 - - -/* - * R4x00 interrupt enable / cause bits - */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) -#define IE_IRQ0 (_ULCAST_(1) << 10) -#define IE_IRQ1 (_ULCAST_(1) << 11) -#define IE_IRQ2 (_ULCAST_(1) << 12) -#define IE_IRQ3 (_ULCAST_(1) << 13) -#define IE_IRQ4 (_ULCAST_(1) << 14) -#define IE_IRQ5 (_ULCAST_(1) << 15) - -/* - * R4x00 interrupt cause bits - */ -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) -#define C_IRQ0 (_ULCAST_(1) << 10) -#define C_IRQ1 (_ULCAST_(1) << 11) -#define C_IRQ2 (_ULCAST_(1) << 12) -#define C_IRQ3 (_ULCAST_(1) << 13) -#define C_IRQ4 (_ULCAST_(1) << 14) -#define C_IRQ5 (_ULCAST_(1) << 15) - -/* - * Bitfields in the R4xx0 cp0 status register - */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_KSU 0x00000018 -# define KSU_USER 0x00000010 -# define KSU_SUPERVISOR 0x00000008 -# define KSU_KERNEL 0x00000000 -#define ST0_UX 0x00000020 -#define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 -#define ST0_DE 0x00010000 -#define ST0_CE 0x00020000 - -/* - * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate - * cacheops in userspace. This bit exists only on RM7000 and RM9000 - * processors. - */ -#define ST0_CO 0x08000000 - -/* - * Bitfields in the R[23]000 cp0 status register. - */ -#define ST0_IEC 0x00000001 -#define ST0_KUC 0x00000002 -#define ST0_IEP 0x00000004 -#define ST0_KUP 0x00000008 -#define ST0_IEO 0x00000010 -#define ST0_KUO 0x00000020 -/* bits 6 & 7 are reserved on R[23]000 */ -#define ST0_ISC 0x00010000 -#define ST0_SWC 0x00020000 -#define ST0_CM 0x00080000 - -/* - * Bits specific to the R4640/R4650 - */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) - -/* - * Enable the MIPS DSP ASE - */ -#define ST0_MX 0x01000000 - -/* - * Bitfields in the TX39 family CP0 Configuration Register 3 - */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 - -/* - * Status register bits available in all MIPS CPUs. - */ -#define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) -#define ST0_CH 0x00040000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_FR 0x04000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#define ST0_XX 0x80000000 /* MIPS IV naming */ - -/* - * Bitfields and bit numbers in the coprocessor 0 cause register. - * - * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. - */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) - -/* - * Bits in the coprocessor 0 config register. - */ -/* Generic bits. */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) - -/* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) - -/* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) - -/* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) - -/* Bits specific to the RM7000. */ -#define RM7K_CONF_SE (_ULCAST_(1) << 3) -#define RM7K_CONF_TE (_ULCAST_(1) << 12) -#define RM7K_CONF_CLK (_ULCAST_(1) << 16) -#define RM7K_CONF_TC (_ULCAST_(1) << 17) -#define RM7K_CONF_SI (_ULCAST_(3) << 20) -#define RM7K_CONF_SC (_ULCAST_(1) << 31) - -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) - -/* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) - -/* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) - -/* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) - -/* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) - -/* - * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. - */ -#define MIPS_CONF1_FP (_ULCAST_(1) << 0) -#define MIPS_CONF1_EP (_ULCAST_(1) << 1) -#define MIPS_CONF1_CA (_ULCAST_(1) << 2) -#define MIPS_CONF1_WR (_ULCAST_(1) << 3) -#define MIPS_CONF1_PC (_ULCAST_(1) << 4) -#define MIPS_CONF1_MD (_ULCAST_(1) << 5) -#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) -#define MIPS_CONF1_DA (_ULCAST_(7) << 7) -#define MIPS_CONF1_DL (_ULCAST_(7) << 10) -#define MIPS_CONF1_DS (_ULCAST_(7) << 13) -#define MIPS_CONF1_IA (_ULCAST_(7) << 16) -#define MIPS_CONF1_IL (_ULCAST_(7) << 19) -#define MIPS_CONF1_IS (_ULCAST_(7) << 22) -#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) - -#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) -#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) -#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) -#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) -#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) -#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) -#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) -#define MIPS_CONF2_TU (_ULCAST_(7) << 28) - -#define MIPS_CONF3_TL (_ULCAST_(1) << 0) -#define MIPS_CONF3_SM (_ULCAST_(1) << 1) -#define MIPS_CONF3_MT (_ULCAST_(1) << 2) -#define MIPS_CONF3_SP (_ULCAST_(1) << 4) -#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) -#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) -#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) -#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) - -/* - * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. - */ -#define MIPS_FPIR_S (_ULCAST_(1) << 16) -#define MIPS_FPIR_D (_ULCAST_(1) << 17) -#define MIPS_FPIR_PS (_ULCAST_(1) << 18) -#define MIPS_FPIR_3D (_ULCAST_(1) << 19) -#define MIPS_FPIR_W (_ULCAST_(1) << 20) -#define MIPS_FPIR_L (_ULCAST_(1) << 21) -#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) - -/* - * R10000 performance counter definitions. - * - * FIXME: The R10000 performance counter opens a nice way to implement CPU - * time accounting with a precission of one cycle. I don't have - * R10000 silicon but just a manual, so ... - */ - -/* - * Events counted by counter #0 - */ -#define CE0_CYCLES 0 -#define CE0_INSN_ISSUED 1 -#define CE0_LPSC_ISSUED 2 -#define CE0_S_ISSUED 3 -#define CE0_SC_ISSUED 4 -#define CE0_SC_FAILED 5 -#define CE0_BRANCH_DECODED 6 -#define CE0_QW_WB_SECONDARY 7 -#define CE0_CORRECTED_ECC_ERRORS 8 -#define CE0_ICACHE_MISSES 9 -#define CE0_SCACHE_I_MISSES 10 -#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 -#define CE0_EXT_INTERVENTIONS_REQ 12 -#define CE0_EXT_INVALIDATE_REQ 13 -#define CE0_VIRTUAL_COHERENCY_COND 14 -#define CE0_INSN_GRADUATED 15 - -/* - * Events counted by counter #1 - */ -#define CE1_CYCLES 0 -#define CE1_INSN_GRADUATED 1 -#define CE1_LPSC_GRADUATED 2 -#define CE1_S_GRADUATED 3 -#define CE1_SC_GRADUATED 4 -#define CE1_FP_INSN_GRADUATED 5 -#define CE1_QW_WB_PRIMARY 6 -#define CE1_TLB_REFILL 7 -#define CE1_BRANCH_MISSPREDICTED 8 -#define CE1_DCACHE_MISS 9 -#define CE1_SCACHE_D_MISSES 10 -#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 -#define CE1_EXT_INTERVENTION_HITS 12 -#define CE1_EXT_INVALIDATE_REQ 13 -#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 -#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 - -/* - * These flags define in which privilege mode the counters count events - */ -#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ -#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ -#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ -#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ - - -#ifndef __ASSEMBLY__ - -/* - * Macros to access the system control coprocessor - */ -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) - -#define read_c0_random() __read_32bit_c0_register($1, 0) -#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) - -#define read_c0_entrylo0() __read_32bit_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, val) - -#define read_c0_entrylo1() __read_32bit_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, val) - -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) - -#define read_c0_context() __read_32bit_c0_register($4, 0) -#define write_c0_context(val) __write_32bit_c0_register($4, 0, val) - -#define read_c0_userlocal() __read_32bit_c0_register($4, 2) -#define write_c0_userlocal(val) __write_32bit_c0_register($4, 2, val) - -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) - -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) - -#define read_c0_info() __read_32bit_c0_register($7, 0) - -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) - -#define read_c0_badvaddr() __read_32bit_c0_register($8, 0) -#define write_c0_badvaddr(val) __write_32bit_c0_register($8, 0, val) - -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) - -#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ -#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) - -#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ -#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) - -#define read_c0_entryhi() __read_32bit_c0_register($10, 0) -#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, val) - -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) - -#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ -#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) - -#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ -#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) - -#define read_c0_status() __read_32bit_c0_register($12, 0) -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) - -#define read_c0_epc() __read_32bit_c0_register($14, 0) -#define write_c0_epc(val) __write_32bit_c0_register($14, 0, val) - -#define read_c0_prid() __read_32bit_c0_register($15, 0) - -#define read_c0_ebase() __read_32bit_c0_register($15, 1) -#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) - -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) - - -#endif /* end of __ASSEMBLY__ */ - -#endif /* end of __MIPSREGS_H__ */ - +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * Copyright (C) 2000 Silicon Graphics, Inc. + * Modified for further R[236]000 support by Paul M. Antoine, 1996. + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 07 MIPS Technologies, Inc. + * Copyright (C) 2003, 2004 Maciej W. Rozycki + * + * Change Logs: + * Date Author Notes + * + */ +#ifndef __MIPSREGS_H__ +#define __MIPSREGS_H__ + +/* + * The following macros are especially useful for __asm__ + * inline assembler. + */ +#ifndef __STR +#define __STR(x) #x +#endif +#ifndef STR +#define STR(x) __STR(x) +#endif + +/* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ULCAST_ +#else +#define _ULCAST_ (unsigned long) +#endif + +/* + * Coprocessor 0 register names + */ +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONF $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_INFO $7 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_DEBUG $23 +#define CP0_DEPC $24 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 +#define CP0_DESAVE $31 + +/* + * R4640/R4650 cp0 register names. These registers are listed + * here only for completeness; without MMU these CPUs are not useable + * by Linux. A future ELKS port might take make Linux run on them + * though ... + */ +#define CP0_IBASE $0 +#define CP0_IBOUND $1 +#define CP0_DBASE $2 +#define CP0_DBOUND $3 +#define CP0_CALG $17 +#define CP0_IWATCH $18 +#define CP0_DWATCH $19 + +/* + * Coprocessor 0 Set 1 register names + */ +#define CP0_S1_DERRADDR0 $26 +#define CP0_S1_DERRADDR1 $27 +#define CP0_S1_INTCONTROL $20 + +/* + * Coprocessor 0 Set 2 register names + */ +#define CP0_S2_SRSCTL $12 /* MIPSR2 */ + +/* + * Coprocessor 0 Set 3 register names + */ +#define CP0_S3_SRSMAP $12 /* MIPSR2 */ + +/* + * TX39 Series + */ +#define CP0_TX39_CACHE $7 + +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_STATUS $31 + + +/* + * R4x00 interrupt enable / cause bits + */ +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_IRQ0 (_ULCAST_(1) << 10) +#define IE_IRQ1 (_ULCAST_(1) << 11) +#define IE_IRQ2 (_ULCAST_(1) << 12) +#define IE_IRQ3 (_ULCAST_(1) << 13) +#define IE_IRQ4 (_ULCAST_(1) << 14) +#define IE_IRQ5 (_ULCAST_(1) << 15) + +/* + * R4x00 interrupt cause bits + */ +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) +#define C_IRQ0 (_ULCAST_(1) << 10) +#define C_IRQ1 (_ULCAST_(1) << 11) +#define C_IRQ2 (_ULCAST_(1) << 12) +#define C_IRQ3 (_ULCAST_(1) << 13) +#define C_IRQ4 (_ULCAST_(1) << 14) +#define C_IRQ5 (_ULCAST_(1) << 15) + +/* + * Bitfields in the R4xx0 cp0 status register + */ +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 + +/* + * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate + * cacheops in userspace. This bit exists only on RM7000 and RM9000 + * processors. + */ +#define ST0_CO 0x08000000 + +/* + * Bitfields in the R[23]000 cp0 status register. + */ +#define ST0_IEC 0x00000001 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 +/* bits 6 & 7 are reserved on R[23]000 */ +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 + +/* + * Bits specific to the R4640/R4650 + */ +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) + +/* + * Enable the MIPS DSP ASE + */ +#define ST0_MX 0x01000000 + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Status register bits available in all MIPS CPUs. + */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ + +/* + * Bitfields and bit numbers in the coprocessor 0 cause register. + * + * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. + */ +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) + +/* + * Bits in the coprocessor 0 config register. + */ +/* Generic bits. */ +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) + +/* Bits common to various processors. */ +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) + +/* Bits specific to the R4xx0. */ +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) + +/* Bits specific to the R5000. */ +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) + +/* Bits specific to the RM7000. */ +#define RM7K_CONF_SE (_ULCAST_(1) << 3) +#define RM7K_CONF_TE (_ULCAST_(1) << 12) +#define RM7K_CONF_CLK (_ULCAST_(1) << 16) +#define RM7K_CONF_TC (_ULCAST_(1) << 17) +#define RM7K_CONF_SI (_ULCAST_(3) << 20) +#define RM7K_CONF_SC (_ULCAST_(1) << 31) + +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) + +/* Bits specific to the VR41xx. */ +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) + +/* Bits specific to the R30xx. */ +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) + +/* Bits specific to the TX49. */ +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) + +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) + +/* + * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. + */ +#define MIPS_CONF1_FP (_ULCAST_(1) << 0) +#define MIPS_CONF1_EP (_ULCAST_(1) << 1) +#define MIPS_CONF1_CA (_ULCAST_(1) << 2) +#define MIPS_CONF1_WR (_ULCAST_(1) << 3) +#define MIPS_CONF1_PC (_ULCAST_(1) << 4) +#define MIPS_CONF1_MD (_ULCAST_(1) << 5) +#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IL (_ULCAST_(7) << 19) +#define MIPS_CONF1_IS (_ULCAST_(7) << 22) +#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) + +#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) +#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) +#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) +#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) +#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) +#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) +#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) +#define MIPS_CONF2_TU (_ULCAST_(7) << 28) + +#define MIPS_CONF3_TL (_ULCAST_(1) << 0) +#define MIPS_CONF3_SM (_ULCAST_(1) << 1) +#define MIPS_CONF3_MT (_ULCAST_(1) << 2) +#define MIPS_CONF3_SP (_ULCAST_(1) << 4) +#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) +#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) +#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) + +/* + * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. + */ +#define MIPS_FPIR_S (_ULCAST_(1) << 16) +#define MIPS_FPIR_D (_ULCAST_(1) << 17) +#define MIPS_FPIR_PS (_ULCAST_(1) << 18) +#define MIPS_FPIR_3D (_ULCAST_(1) << 19) +#define MIPS_FPIR_W (_ULCAST_(1) << 20) +#define MIPS_FPIR_L (_ULCAST_(1) << 21) +#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) + +/* + * R10000 performance counter definitions. + * + * FIXME: The R10000 performance counter opens a nice way to implement CPU + * time accounting with a precission of one cycle. I don't have + * R10000 silicon but just a manual, so ... + */ + +/* + * Events counted by counter #0 + */ +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 + +/* + * Events counted by counter #1 + */ +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 + +/* + * These flags define in which privilege mode the counters count events + */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ + + +#ifndef __ASSEMBLY__ + +/* + * Macros to access the system control coprocessor + */ +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" ((unsigned int)(value))); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" ((unsigned int)(value))); \ +} while (0) + +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) + +#define read_c0_random() __read_32bit_c0_register($1, 0) +#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) + +#define read_c0_entrylo0() __read_32bit_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, val) + +#define read_c0_entrylo1() __read_32bit_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, val) + +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) + +#define read_c0_context() __read_32bit_c0_register($4, 0) +#define write_c0_context(val) __write_32bit_c0_register($4, 0, val) + +#define read_c0_userlocal() __read_32bit_c0_register($4, 2) +#define write_c0_userlocal(val) __write_32bit_c0_register($4, 2, val) + +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) + +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) + +#define read_c0_info() __read_32bit_c0_register($7, 0) + +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_badvaddr() __read_32bit_c0_register($8, 0) +#define write_c0_badvaddr(val) __write_32bit_c0_register($8, 0, val) + +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) + +#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ +#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) + +#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ +#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) + +#define read_c0_entryhi() __read_32bit_c0_register($10, 0) +#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, val) + +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) + +#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ +#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) + +#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ +#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) + +#define read_c0_status() __read_32bit_c0_register($12, 0) +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) + +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) + +#define read_c0_epc() __read_32bit_c0_register($14, 0) +#define write_c0_epc(val) __write_32bit_c0_register($14, 0, val) + +#define read_c0_prid() __read_32bit_c0_register($15, 0) + +#define read_c0_ebase() __read_32bit_c0_register($15, 1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) + + +#endif /* end of __ASSEMBLY__ */ + +#endif /* end of __MIPSREGS_H__ */ + diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index ab4eccb2bc925fb56cee0c0512071856215367a4..96b69ab14f2d6399fdb9ff99ce3f885561c57b9b 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -1,228 +1,228 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle - * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki - */ -#ifndef __STACKFRAME_H__ -#define __STACKFRAME_H__ - -#include "asm.h" -#include "mipsregs.h" - -/* - * Stack layout for the INT exception handler - * Derived from the stack layout described in asm-mips/stackframe.h - * - * The first PTRSIZE*6 bytes are argument save space for C subroutines. - */ - -//#define PT_R0 (PTRSIZE*6) /* 0 */ -#define PT_R0 (0) /* 0 */ -#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ -#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ -#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ -#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ -#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ -#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ -#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ -#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ -#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ -#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ -#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ -#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ -#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ -#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ -#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ -#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ -#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ -#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ -#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ -#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ -#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ -#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ -#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ -#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ -#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ -#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ -#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ -#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ -#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ -#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ -#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ - -/* - * Saved special registers - */ -#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ -#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */ -#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */ -#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ -#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ -#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ - -#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) - - - .macro SAVE_AT - .set push - .set noat - LONG_S $1, PT_R1(sp) - .set pop - .endm - - .macro SAVE_TEMP - mfhi v1 - LONG_S $8, PT_R8(sp) - LONG_S $9, PT_R9(sp) - LONG_S v1, PT_HI(sp) - mflo v1 - LONG_S $10, PT_R10(sp) - LONG_S $11, PT_R11(sp) - LONG_S v1, PT_LO(sp) - LONG_S $12, PT_R12(sp) - LONG_S $13, PT_R13(sp) - LONG_S $14, PT_R14(sp) - LONG_S $15, PT_R15(sp) - LONG_S $24, PT_R24(sp) - .endm - - .macro SAVE_STATIC - LONG_S $16, PT_R16(sp) - LONG_S $17, PT_R17(sp) - LONG_S $18, PT_R18(sp) - LONG_S $19, PT_R19(sp) - LONG_S $20, PT_R20(sp) - LONG_S $21, PT_R21(sp) - LONG_S $22, PT_R22(sp) - LONG_S $23, PT_R23(sp) - LONG_S $30, PT_R30(sp) - .endm - - .macro get_saved_sp - nop - .endm - - .macro SAVE_SOME - .set push - .set noat - .set reorder - move k1, sp -8: move k0, sp - PTR_SUBU sp, k1, PT_SIZE - LONG_S k0, PT_R29(sp) - LONG_S $3, PT_R3(sp) - LONG_S $0, PT_R0(sp) - mfc0 v1, CP0_STATUS - LONG_S $2, PT_R2(sp) - LONG_S v1, PT_STATUS(sp) - LONG_S $4, PT_R4(sp) - mfc0 v1, CP0_CAUSE - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_CAUSE(sp) - LONG_S $6, PT_R6(sp) - MFC0 v1, CP0_EPC - LONG_S $7, PT_R7(sp) - LONG_S v1, PT_EPC(sp) - LONG_S $25, PT_R25(sp) - LONG_S $28, PT_R28(sp) - LONG_S $31, PT_R31(sp) - .set pop - .endm - - .macro SAVE_ALL - SAVE_SOME - SAVE_AT - SAVE_TEMP - SAVE_STATIC - .endm - - .macro RESTORE_AT - .set push - .set noat - LONG_L $1, PT_R1(sp) - .set pop - .endm - - .macro RESTORE_TEMP - LONG_L $24, PT_LO(sp) - LONG_L $8, PT_R8(sp) - LONG_L $9, PT_R9(sp) - mtlo $24 - LONG_L $24, PT_HI(sp) - LONG_L $10, PT_R10(sp) - LONG_L $11, PT_R11(sp) - mthi $24 - LONG_L $12, PT_R12(sp) - LONG_L $13, PT_R13(sp) - LONG_L $14, PT_R14(sp) - LONG_L $15, PT_R15(sp) - LONG_L $24, PT_R24(sp) - .endm - - .macro RESTORE_STATIC - LONG_L $16, PT_R16(sp) - LONG_L $17, PT_R17(sp) - LONG_L $18, PT_R18(sp) - LONG_L $19, PT_R19(sp) - LONG_L $20, PT_R20(sp) - LONG_L $21, PT_R21(sp) - LONG_L $22, PT_R22(sp) - LONG_L $23, PT_R23(sp) - LONG_L $30, PT_R30(sp) - .endm - - .macro RESTORE_SOME - .set push - .set reorder - .set noat - LONG_L v0, PT_STATUS(sp) - mtc0 v0, CP0_STATUS - LONG_L v1, PT_EPC(sp) - MTC0 v1, CP0_EPC - LONG_L $31, PT_R31(sp) - LONG_L $28, PT_R28(sp) - LONG_L $25, PT_R25(sp) - LONG_L $7, PT_R7(sp) - LONG_L $6, PT_R6(sp) - LONG_L $5, PT_R5(sp) - LONG_L $4, PT_R4(sp) - LONG_L $3, PT_R3(sp) - LONG_L $2, PT_R2(sp) - .set pop - .endm - - .macro RESTORE_SP_AND_RET - LONG_L sp, PT_R29(sp) - .set mips3 - eret - .set mips0 - .endm - - - .macro RESTORE_SP - LONG_L sp, PT_R29(sp) - .endm - - .macro RESTORE_ALL - RESTORE_TEMP - RESTORE_STATIC - RESTORE_AT - RESTORE_SOME - RESTORE_SP - .endm - - .macro RESTORE_ALL_AND_RET - RESTORE_TEMP - RESTORE_STATIC - RESTORE_AT - RESTORE_SOME - RESTORE_SP_AND_RET - .endm - -#endif /* end of __STACKFRAME_H__ */ - +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle + * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2007 Maciej W. Rozycki + */ +#ifndef __STACKFRAME_H__ +#define __STACKFRAME_H__ + +#include "asm.h" +#include "mipsregs.h" + +/* + * Stack layout for the INT exception handler + * Derived from the stack layout described in asm-mips/stackframe.h + * + * The first PTRSIZE*6 bytes are argument save space for C subroutines. + */ + +//#define PT_R0 (PTRSIZE*6) /* 0 */ +#define PT_R0 (0) /* 0 */ +#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ +#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ +#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ +#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ +#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ +#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ +#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ +#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ +#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ +#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ +#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ +#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ +#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ +#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ +#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ +#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ +#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ +#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ +#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ +#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ +#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ +#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ +#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ +#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ +#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ +#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ +#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ +#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ +#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ +#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ +#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ + +/* + * Saved special registers + */ +#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ +#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */ +#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */ +#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ +#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ +#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ + +#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) + + + .macro SAVE_AT + .set push + .set noat + LONG_S $1, PT_R1(sp) + .set pop + .endm + + .macro SAVE_TEMP + mfhi v1 + LONG_S $8, PT_R8(sp) + LONG_S $9, PT_R9(sp) + LONG_S v1, PT_HI(sp) + mflo v1 + LONG_S $10, PT_R10(sp) + LONG_S $11, PT_R11(sp) + LONG_S v1, PT_LO(sp) + LONG_S $12, PT_R12(sp) + LONG_S $13, PT_R13(sp) + LONG_S $14, PT_R14(sp) + LONG_S $15, PT_R15(sp) + LONG_S $24, PT_R24(sp) + .endm + + .macro SAVE_STATIC + LONG_S $16, PT_R16(sp) + LONG_S $17, PT_R17(sp) + LONG_S $18, PT_R18(sp) + LONG_S $19, PT_R19(sp) + LONG_S $20, PT_R20(sp) + LONG_S $21, PT_R21(sp) + LONG_S $22, PT_R22(sp) + LONG_S $23, PT_R23(sp) + LONG_S $30, PT_R30(sp) + .endm + + .macro get_saved_sp + nop + .endm + + .macro SAVE_SOME + .set push + .set noat + .set reorder + move k1, sp +8: move k0, sp + PTR_SUBU sp, k1, PT_SIZE + LONG_S k0, PT_R29(sp) + LONG_S $3, PT_R3(sp) + LONG_S $0, PT_R0(sp) + mfc0 v1, CP0_STATUS + LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) + LONG_S $4, PT_R4(sp) + mfc0 v1, CP0_CAUSE + LONG_S $5, PT_R5(sp) + LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) + MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) + LONG_S v1, PT_EPC(sp) + LONG_S $25, PT_R25(sp) + LONG_S $28, PT_R28(sp) + LONG_S $31, PT_R31(sp) + .set pop + .endm + + .macro SAVE_ALL + SAVE_SOME + SAVE_AT + SAVE_TEMP + SAVE_STATIC + .endm + + .macro RESTORE_AT + .set push + .set noat + LONG_L $1, PT_R1(sp) + .set pop + .endm + + .macro RESTORE_TEMP + LONG_L $24, PT_LO(sp) + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) + mtlo $24 + LONG_L $24, PT_HI(sp) + LONG_L $10, PT_R10(sp) + LONG_L $11, PT_R11(sp) + mthi $24 + LONG_L $12, PT_R12(sp) + LONG_L $13, PT_R13(sp) + LONG_L $14, PT_R14(sp) + LONG_L $15, PT_R15(sp) + LONG_L $24, PT_R24(sp) + .endm + + .macro RESTORE_STATIC + LONG_L $16, PT_R16(sp) + LONG_L $17, PT_R17(sp) + LONG_L $18, PT_R18(sp) + LONG_L $19, PT_R19(sp) + LONG_L $20, PT_R20(sp) + LONG_L $21, PT_R21(sp) + LONG_L $22, PT_R22(sp) + LONG_L $23, PT_R23(sp) + LONG_L $30, PT_R30(sp) + .endm + + .macro RESTORE_SOME + .set push + .set reorder + .set noat + LONG_L v0, PT_STATUS(sp) + mtc0 v0, CP0_STATUS + LONG_L v1, PT_EPC(sp) + MTC0 v1, CP0_EPC + LONG_L $31, PT_R31(sp) + LONG_L $28, PT_R28(sp) + LONG_L $25, PT_R25(sp) + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $3, PT_R3(sp) + LONG_L $2, PT_R2(sp) + .set pop + .endm + + .macro RESTORE_SP_AND_RET + LONG_L sp, PT_R29(sp) + .set mips3 + eret + .set mips0 + .endm + + + .macro RESTORE_SP + LONG_L sp, PT_R29(sp) + .endm + + .macro RESTORE_ALL + RESTORE_TEMP + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP + .endm + + .macro RESTORE_ALL_AND_RET + RESTORE_TEMP + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP_AND_RET + .endm + +#endif /* end of __STACKFRAME_H__ */ + diff --git a/libcpu/mips/jz47xx/cache.c b/libcpu/mips/jz47xx/cache.c index e00292675e8fe106dc91d4f99c486436a671589c..8a502cdb126b82bd7ad84f98c8f034a4deb0bb46 100644 --- a/libcpu/mips/jz47xx/cache.c +++ b/libcpu/mips/jz47xx/cache.c @@ -1,93 +1,93 @@ -#include "jz47xx.h" -#include "cache.h" - -#define CACHE_SIZE 16*1024 -#define CACHE_LINE_SIZE 32 -#define KSEG0 0x80000000 - - -#define K0_TO_K1() \ -do { \ - unsigned long __k0_addr; \ - \ - __asm__ __volatile__( \ - "la %0, 1f\n\t" \ - "or %0, %0, %1\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r"(__k0_addr) \ - : "r" (0x20000000) ); \ -} while(0) - -#define K1_TO_K0() \ -do { \ - unsigned long __k0_addr; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "la %0, 1f\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r" (__k0_addr)); \ -} while (0) - -#define INVALIDATE_BTB() \ -do { \ - unsigned long tmp; \ - __asm__ __volatile__( \ - ".set mips32\n\t" \ - "mfc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - "ori %0, 2\n\t" \ - "mtc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - ".set mips2\n\t" \ - : "=&r" (tmp)); \ -} while (0) - -#define SYNC_WB() __asm__ __volatile__ ("sync") - -#define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips32\n\t \n" \ - " cache %0, %1 \n" \ - " .set mips0 \n" \ - " .set reorder" \ - : \ - : "i" (op), "m" (*(unsigned char *)(addr))) - -void __icache_invalidate_all(void) -{ - unsigned int i; - - K0_TO_K1(); - - asm volatile (".set noreorder\n" - ".set mips32\n\t" - "mtc0\t$0,$28\n\t" - "mtc0\t$0,$29\n" - ".set mips0\n" - ".set reorder\n"); - for (i=KSEG0;i from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop - - .globl system_dump - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl mips_irq_handle -mips_irq_handle: - SAVE_ALL - - mfc0 t0, CP0_CAUSE - mfc0 t1, CP0_STATUS - and t0, t1 - - andi t0, 0xff00 - beqz t0, spurious_interrupt - nop - - /* let k0 keep the current context sp */ - move k0, sp - /* switch to kernel stack */ - li sp, SYSTEM_STACK - - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop - -spurious_interrupt: - RESTORE_ALL_AND_RET - - .set reorder +/* + * File : context_gcc.S + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-11 bernard port to Jz4755 + */ +#include "../common/mips.inc" +#include "../common/stackframe.h" +#include "jz47xx.h" + + .section ".text", "ax" + .set noreorder + +/* + * rt_base_t rt_hw_interrupt_disable() + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mfc0 v0, CP0_STATUS + and v1, v0, 0xfffffffe + mtc0 v1, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + mtc0 a0, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + mtc0 ra, CP0_EPC + SAVE_ALL + + sw sp, 0(a0) /* store sp in preempted tasks TCB */ + lw sp, 0(a1) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + lw sp, 0(a0) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + la t0, rt_thread_switch_interrupt_flag + lw t1, 0(t0) + nop + bnez t1, _reswitch + nop + li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ + sw t1, 0(t0) + la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + sw a0, 0(t0) +_reswitch: + la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + sw a1, 0(t0) + jr ra + nop + + .globl system_dump + +/* + * void rt_hw_context_switch_interrupt_do(rt_base_t flag) + */ + .globl rt_interrupt_enter + .globl rt_interrupt_leave + .globl mips_irq_handle +mips_irq_handle: + SAVE_ALL + + mfc0 t0, CP0_CAUSE + mfc0 t1, CP0_STATUS + and t0, t1 + + andi t0, 0xff00 + beqz t0, spurious_interrupt + nop + + /* let k0 keep the current context sp */ + move k0, sp + /* switch to kernel stack */ + li sp, SYSTEM_STACK + + jal rt_interrupt_enter + nop + jal rt_interrupt_dispatch + nop + jal rt_interrupt_leave + nop + + /* switch sp back to thread's context */ + move sp, k0 + + /* + * if rt_thread_switch_interrupt_flag set, jump to + * rt_hw_context_switch_interrupt_do and don't return + */ + la k0, rt_thread_switch_interrupt_flag + lw k1, 0(k0) + beqz k1, spurious_interrupt + nop + sw zero, 0(k0) /* clear flag */ + nop + + /* + * switch to the new thread + */ + la k0, rt_interrupt_from_thread + lw k1, 0(k0) + nop + sw sp, 0(k1) /* store sp in preempted tasks's TCB */ + + la k0, rt_interrupt_to_thread + lw k1, 0(k0) + nop + lw sp, 0(k1) /* get new task's stack pointer */ + j spurious_interrupt + nop + +spurious_interrupt: + RESTORE_ALL_AND_RET + + .set reorder diff --git a/libcpu/mips/jz47xx/cpu.c b/libcpu/mips/jz47xx/cpu.c index 1db6a97c02ec02a8dda27130f2bd52537fe7ac36..f44a44e020b534c26180da93613c556eb35c644b 100644 --- a/libcpu/mips/jz47xx/cpu.c +++ b/libcpu/mips/jz47xx/cpu.c @@ -1,68 +1,68 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2010-09-11 Bernard add CPU reset implementation - */ -#include -#include - -/* Watchdog definitions */ -#define WDT_CLK_PRESCALE_CLK1 ( 0x0 << 3) -#define WDT_CLK_PRESCALE_CLK4 ( 0x1 << 3) -#define WDT_CLK_PRESCALE_CLK16 ( 0x2 << 3) -#define WDT_CLK_PRESCALE_CLK64 ( 0x3 << 3) -#define WDT_CLK_PRESCALE_CLK256 ( 0x4 << 3) -#define WDT_CLK_PRESCALE_CLK1024 ( 0x5 << 3) -#define WDT_CLK_PRESCALE_MASK ( 0x3F << 3) - -#define WDT_CLK_EXTAL ( 0x1 << 2) -#define WDT_CLK_RTC ( 0x1 << 1) -#define WDT_CLK_PCLK ( 0x1 << 0) -#define WDT_CLK_MASK ( 7 ) - -#define WDT_ENABLE ( 1 << 0 ) - -/** - * @addtogroup Jz47xx - */ -/*@{*/ - -/** - * this function will reset CPU - * - */ -void rt_hw_cpu_reset() -{ - /* open the watch-dog */ - WDT_TCSR = WDT_CLK_EXTAL; - WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024; - WDT_TDR = 0x03; - WDT_TCNT = 0x00; - WDT_TCER |= WDT_ENABLE; - - rt_kprintf("reboot system...\n"); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -/*@}*/ - +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2010-09-11 Bernard add CPU reset implementation + */ +#include +#include + +/* Watchdog definitions */ +#define WDT_CLK_PRESCALE_CLK1 ( 0x0 << 3) +#define WDT_CLK_PRESCALE_CLK4 ( 0x1 << 3) +#define WDT_CLK_PRESCALE_CLK16 ( 0x2 << 3) +#define WDT_CLK_PRESCALE_CLK64 ( 0x3 << 3) +#define WDT_CLK_PRESCALE_CLK256 ( 0x4 << 3) +#define WDT_CLK_PRESCALE_CLK1024 ( 0x5 << 3) +#define WDT_CLK_PRESCALE_MASK ( 0x3F << 3) + +#define WDT_CLK_EXTAL ( 0x1 << 2) +#define WDT_CLK_RTC ( 0x1 << 1) +#define WDT_CLK_PCLK ( 0x1 << 0) +#define WDT_CLK_MASK ( 7 ) + +#define WDT_ENABLE ( 1 << 0 ) + +/** + * @addtogroup Jz47xx + */ +/*@{*/ + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset() +{ + /* open the watch-dog */ + WDT_TCSR = WDT_CLK_EXTAL; + WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024; + WDT_TDR = 0x03; + WDT_TCNT = 0x00; + WDT_TCER |= WDT_ENABLE; + + rt_kprintf("reboot system...\n"); + while (1); +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + +/*@}*/ + diff --git a/libcpu/mips/jz47xx/exception.c b/libcpu/mips/jz47xx/exception.c index de14c0969c6a2da0333e4b22a8f250db1bdecf04..6d47d3ca4e9fc79041a6aa6de71a61c309564fb2 100644 --- a/libcpu/mips/jz47xx/exception.c +++ b/libcpu/mips/jz47xx/exception.c @@ -1,65 +1,65 @@ -/* - * File : exception.c - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include -#include -#include "../common/exception.h" -#include "../common/mipsregs.h" - -/** - * @addtogroup Jz47xx - */ -/*@{*/ - -/** - * exception handle table - */ -exception_func_t sys_exception_handlers[33]; - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > 32) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -void cache_error_handler(void) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -static void unhandled_exception_handle(pt_regs_t *regs) -{ - rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc); -} - -void install_default_execpt_handle(void) -{ - rt_int32_t i; - - for (i=0; i<33; i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; -} - -/*@}*/ - +/* + * File : exception.c + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#include +#include +#include "../common/exception.h" +#include "../common/mipsregs.h" + +/** + * @addtogroup Jz47xx + */ +/*@{*/ + +/** + * exception handle table + */ +exception_func_t sys_exception_handlers[33]; + +/** + * setup the exception handle + */ +exception_func_t rt_set_except_vector(int n, exception_func_t func) +{ + exception_func_t old_handler = sys_exception_handlers[n]; + + if ((n == 0) || (n > 32) || (!func)) + { + return 0; + } + + sys_exception_handlers[n] = func; + + return old_handler; +} + +void tlb_refill_handler(void) +{ + rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +void cache_error_handler(void) +{ + rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +static void unhandled_exception_handle(pt_regs_t *regs) +{ + rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc); +} + +void install_default_execpt_handle(void) +{ + rt_int32_t i; + + for (i=0; i<33; i++) + sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; +} + +/*@}*/ + diff --git a/libcpu/mips/jz47xx/interrupt.c b/libcpu/mips/jz47xx/interrupt.c index 78ba87c2e9ae0cfc0da0826ef615f1d4ad94583b..7d531cbd719c3683c5fdfbdeecd59b54a81f52d1 100644 --- a/libcpu/mips/jz47xx/interrupt.c +++ b/libcpu/mips/jz47xx/interrupt.c @@ -1,116 +1,116 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - */ -#include -#include "jz47xx.h" - -#define JZ47XX_MAX_INTR 32 - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static rt_isr_handler_t irq_handle_table[JZ47XX_MAX_INTR]; - -/** - * @addtogroup Jz47xx - */ -/*@{*/ - -void rt_hw_interrupt_handler(int vector) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init() -{ - rt_int32_t index; - - for (index = 0; index < JZ47XX_MAX_INTR; index ++) - { - irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - INTC_IMSR = (1 << vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - INTC_IMCR = (1 << vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) -{ - if (vector >= 0 && vector < JZ47XX_MAX_INTR) - { - if (old_handler != RT_NULL) - *old_handler = irq_handle_table[vector]; - if (new_handler != RT_NULL) - irq_handle_table[vector] = (rt_isr_handler_t)new_handler; - } -} - -void rt_interrupt_dispatch(void *ptreg) -{ - int i; - rt_isr_handler_t irq_func; - static rt_uint32_t pending = 0; - - /* the hardware interrupt */ - pending |= INTC_IPR; - if (!pending) return; - - for (i = JZ47XX_MAX_INTR; i > 0; --i) - { - if ((pending & (1< +#include "jz47xx.h" + +#define JZ47XX_MAX_INTR 32 + +extern rt_uint32_t rt_interrupt_nest; +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +static rt_isr_handler_t irq_handle_table[JZ47XX_MAX_INTR]; + +/** + * @addtogroup Jz47xx + */ +/*@{*/ + +void rt_hw_interrupt_handler(int vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init() +{ + rt_int32_t index; + + for (index = 0; index < JZ47XX_MAX_INTR; index ++) + { + irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler; + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + /* mask interrupt */ + INTC_IMSR = (1 << vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + INTC_IMCR = (1 << vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + if (vector >= 0 && vector < JZ47XX_MAX_INTR) + { + if (old_handler != RT_NULL) + *old_handler = irq_handle_table[vector]; + if (new_handler != RT_NULL) + irq_handle_table[vector] = (rt_isr_handler_t)new_handler; + } +} + +void rt_interrupt_dispatch(void *ptreg) +{ + int i; + rt_isr_handler_t irq_func; + static rt_uint32_t pending = 0; + + /* the hardware interrupt */ + pending |= INTC_IPR; + if (!pending) return; + + for (i = JZ47XX_MAX_INTR; i > 0; --i) + { + if ((pending & (1< -#include "../common/mipsregs.h" -#include "../common/mipscfg.h" - -mips32_core_cfg_t g_mips_core = -{ - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ -}; - -static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) -{ - rt_uint16_t rets = 1; - - while (n--) - rets *= b; - - return rets; -} - -static rt_uint16_t m_log2(rt_uint16_t b) -{ - rt_uint16_t rets = 0; - - while (b != 1) - { - b /= 2; - rets++; - } - - return rets; -} - -/** +/* + * File : mipscfg.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#include +#include "../common/mipsregs.h" +#include "../common/mipscfg.h" + +mips32_core_cfg_t g_mips_core = +{ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** * read core attribute - */ -void mips32_cfg_init(void) -{ - rt_uint16_t val; - rt_uint32_t cp0_config1; - - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); - - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; - - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; - - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } -} + */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/jz47xx/stack.c b/libcpu/mips/jz47xx/stack.c index 33dbaf5b64da4deda195a0d1f888cc7383ee27a5..1d408bbff16dad97103435d319cc573ddd49cad7 100644 --- a/libcpu/mips/jz47xx/stack.c +++ b/libcpu/mips/jz47xx/stack.c @@ -1,94 +1,94 @@ -/* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-07-07 Bernard porting to Jz47xx - */ -#include - -/** - * @addtogroup Jz47xx - */ -/*@{*/ - -extern rt_uint32_t cp0_get_cause(void); -extern rt_uint32_t cp0_get_status(void); -extern rt_uint32_t cp0_get_hi(void); -extern rt_uint32_t cp0_get_lo(void); - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - static rt_uint32_t g_sr = 0; - - if (g_sr == 0) - { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x0403; - } - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-07-07 Bernard porting to Jz47xx + */ +#include + +/** + * @addtogroup Jz47xx + */ +/*@{*/ + +extern rt_uint32_t cp0_get_cause(void); +extern rt_uint32_t cp0_get_status(void); +extern rt_uint32_t cp0_get_hi(void); +extern rt_uint32_t cp0_get_lo(void); + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + static rt_uint32_t g_sr = 0; + + if (g_sr == 0) + { + g_sr = cp0_get_status(); + g_sr &= 0xfffffffe; + g_sr |= 0x0403; + } + + /** Start at stack top */ + stk = (rt_uint32_t *)stack_addr; + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ + *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ + *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ + *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ + *(--stk) = (rt_uint32_t) texit; /* ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* sp */ + *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ + *(--stk) = (rt_uint32_t) parameter; /* a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/mips/jz47xx/start_gcc.S b/libcpu/mips/jz47xx/start_gcc.S index d496b54e92886cea9efa225ae4c632ccb14b75ba..162c491b1d311f397425090618b4de7741703d22 100644 --- a/libcpu/mips/jz47xx/start_gcc.S +++ b/libcpu/mips/jz47xx/start_gcc.S @@ -1,151 +1,151 @@ -/* - * File : start_gcc.S - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-04 bernard porting to Jz47xx - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "jz47xx.h" - - .section ".start", "ax" - .set noreorder - - /* the program entry */ - .globl _start -_start: - .set noreorder - la ra, _start - - /* init cp0 registers. */ - li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */ - mtc0 t0, CP0_STATUS - - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* init caches, assumes a 4way * 128set * 32byte I/D cache */ - li t0, 3 /* enable cache for kseg0 accesses */ - mtc0 t0, CP0_CONFIG /* CONFIG reg */ - la t0, 0x80000000 /* an idx op should use an unmappable address */ - ori t1, t0, 0x4000 /* 16kB cache */ - mtc0 zero, CP0_TAGLO /* TAGLO reg */ - mtc0 zero, CP0_TAGHI /* TAGHI reg */ - -_cache_loop: - cache 0x8, 0(t0) /* index store icache tag */ - cache 0x9, 0(t0) /* index store dcache tag */ - bne t0, t1, _cache_loop - addiu t0, t0, 0x20 /* 32 bytes per cache line */ - nop - - /* invalidate BTB */ - mfc0 t0, CP0_CONFIG - nop - ori t0, 2 - mtc0 t0, CP0_CONFIG - nop - - /* copy IRAM section */ - la t0, _iramcopy - la t1, _iramstart - la t2, _iramend -_iram_loop: - lw t3, 0(t0) - sw t3, 0(t1) - addiu t1, 4 - bne t1, t2, _iram_loop - addiu t0, 4 - - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - .set reorder - - .globl cp0_get_cause -cp0_get_cause: - mfc0 v0, CP0_CAUSE - jr ra - nop - - .globl cp0_get_status -cp0_get_status: - mfc0 v0, CP0_STATUS - jr ra - nop - - .globl cp0_get_hi -cp0_get_hi: - mfhi v0 - jr ra - nop - - .globl cp0_get_lo -cp0_get_lo: - mflo v0 - jr ra - nop - - .extern tlb_refill_handler - .extern cache_error_handler - - /* Exception Handler */ - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - j tlb_refill_handler - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j cache_error_handler - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - j _general_exception_handler - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - j _irq_handler - nop - - .section .vectors, "ax", %progbits - .extern mips_irq_handle - - /* general exception handler */ -_general_exception_handler: - .set noreorder - mfc0 k1, CP0_CAUSE - andi k1, k1, 0x7c - srl k1, k1, 2 - lw k0, sys_exception_handlers(k1) - jr k0 - nop - .set reorder - - /* interrupt handler */ -_irq_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder +/* + * File : start_gcc.S + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-04 bernard porting to Jz47xx + */ + +#include "../common/mips.inc" +#include "../common/stackframe.h" +#include "jz47xx.h" + + .section ".start", "ax" + .set noreorder + + /* the program entry */ + .globl _start +_start: + .set noreorder + la ra, _start + + /* init cp0 registers. */ + li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */ + mtc0 t0, CP0_STATUS + + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* setup stack pointer */ + li sp, SYSTEM_STACK + la gp, _gp + + /* init caches, assumes a 4way * 128set * 32byte I/D cache */ + li t0, 3 /* enable cache for kseg0 accesses */ + mtc0 t0, CP0_CONFIG /* CONFIG reg */ + la t0, 0x80000000 /* an idx op should use an unmappable address */ + ori t1, t0, 0x4000 /* 16kB cache */ + mtc0 zero, CP0_TAGLO /* TAGLO reg */ + mtc0 zero, CP0_TAGHI /* TAGHI reg */ + +_cache_loop: + cache 0x8, 0(t0) /* index store icache tag */ + cache 0x9, 0(t0) /* index store dcache tag */ + bne t0, t1, _cache_loop + addiu t0, t0, 0x20 /* 32 bytes per cache line */ + nop + + /* invalidate BTB */ + mfc0 t0, CP0_CONFIG + nop + ori t0, 2 + mtc0 t0, CP0_CONFIG + nop + + /* copy IRAM section */ + la t0, _iramcopy + la t1, _iramstart + la t2, _iramend +_iram_loop: + lw t3, 0(t0) + sw t3, 0(t1) + addiu t1, 4 + bne t1, t2, _iram_loop + addiu t0, 4 + + /* clear bss */ + la t0, __bss_start + la t1, __bss_end +_clr_bss_loop: + sw zero, 0(t0) + bne t0, t1, _clr_bss_loop + addiu t0, t0, 4 + + /* jump to RT-Thread RTOS */ + jal rtthread_startup + nop + + /* restart, never die */ + j _start + nop + .set reorder + + .globl cp0_get_cause +cp0_get_cause: + mfc0 v0, CP0_CAUSE + jr ra + nop + + .globl cp0_get_status +cp0_get_status: + mfc0 v0, CP0_STATUS + jr ra + nop + + .globl cp0_get_hi +cp0_get_hi: + mfhi v0 + jr ra + nop + + .globl cp0_get_lo +cp0_get_lo: + mflo v0 + jr ra + nop + + .extern tlb_refill_handler + .extern cache_error_handler + + /* Exception Handler */ + /* 0x0 - TLB refill handler */ + .section .vectors.1, "ax", %progbits + j tlb_refill_handler + nop + + /* 0x100 - Cache error handler */ + .section .vectors.2, "ax", %progbits + j cache_error_handler + nop + + /* 0x180 - Exception/Interrupt handler */ + .section .vectors.3, "ax", %progbits + j _general_exception_handler + nop + + /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ + .section .vectors.4, "ax", %progbits + j _irq_handler + nop + + .section .vectors, "ax", %progbits + .extern mips_irq_handle + + /* general exception handler */ +_general_exception_handler: + .set noreorder + mfc0 k1, CP0_CAUSE + andi k1, k1, 0x7c + srl k1, k1, 2 + lw k0, sys_exception_handlers(k1) + jr k0 + nop + .set reorder + + /* interrupt handler */ +_irq_handler: + .set noreorder + la k0, mips_irq_handle + jr k0 + nop + .set reorder diff --git a/libcpu/mips/loongson/cache.c b/libcpu/mips/loongson/cache.c index bca01a61f40404bf2ea2f146334970aedad7d6e5..6b3ad84b0e727c79c656406da47ba518e2660262 100644 --- a/libcpu/mips/loongson/cache.c +++ b/libcpu/mips/loongson/cache.c @@ -1,188 +1,188 @@ -#include "../common/mipsregs.h" -#include "cache.h" - -#define K0BASE 0x80000000 -#define PRID_3210I 0x4200 - -typedef struct cacheinfo_t { - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; -} cacheinfo_t ; - -typedef struct cacheop_t { - void (*Clear_TagLo) (void); - void (*Invalidate_Icache) (unsigned int); - void (*Invalidate_Dcache_Fill) (unsigned int); - void (*Invalidate_Dcache_ClearTag) (unsigned int); - void (*Init_Cache)(void); -} cacheop_t ; - -static cacheop_t cacheop, *pcacheop; -static cacheinfo_t cacheinfo, *pcacheinfo; - -int identify_cpu (void) -{ - unsigned int cpu_id; - void invalidate_cache (void); - - pcacheop = &cacheop; - pcacheinfo = &cacheinfo; - - rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); - cpu_id = read_c0_prid(); - switch (cpu_id) - { - case PRID_3210I: - rt_kprintf ("CPU:SoC3210\n"); - pcacheop->Clear_TagLo = Clear_TagLo; - pcacheop->Invalidate_Icache = Invalidate_Icache_Gc3210I; - pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Gc3210I; - pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Gc3210I; - break; - default: - rt_kprintf ("Unknown CPU type, system halted!\n"); - while (1) {} - break; - } - - return 0; -} - -void probe_cache(void) -{ - unsigned int config = read_c0_config (); - unsigned int icache_size, ic_lsize; - unsigned int dcache_size, dc_lsize; - - icache_size = 1 << (12 + ((config >> 9) & 7)); - dcache_size = 1 << (12 + ((config >> 6) & 7)); - ic_lsize = 16 << ((config >> 5) & 1); - dc_lsize = 16 << ((config >> 4) & 1); - - rt_kprintf("DCache %2dkb, linesize %d bytes.\n", - dcache_size >> 10, dc_lsize); - rt_kprintf("ICache %2dkb, linesize %d bytes.\n", - icache_size >> 10, ic_lsize); - - pcacheinfo->icache_size = icache_size; - pcacheinfo->dcache_size = dcache_size; - pcacheinfo->icacheline_size = ic_lsize; - pcacheinfo->dcacheline_size = dc_lsize; - - return ; -} - -void invalidate_writeback_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - start = K0BASE; - while(start < end) { - Writeback_Invalidate_Dcache(start); //hit writeback invalidate - start += pcacheinfo->dcacheline_size; - } -} - -void invalidate_writeback_dcache(unsigned long addr, int size) -{ - unsigned long start, end; - - start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); - end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); - - while(start dcacheline_size; - } -} - - -void invalidate_icache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->icache_size); - - while(start < end) { - pcacheop->Invalidate_Icache(start); - start += pcacheinfo->icacheline_size; - } -} - -void invalidate_dcache_all() -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - while(start icacheline_size; - } -} - -//with cache disabled -void init_dcache(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while(start < end){ - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - -} - -void rt_hw_cache_init(void) -{ - unsigned int start, end; - - /* 1. identify cpu and probe cache */ - identify_cpu(); - probe_cache(); - - start = K0BASE; - end = (start + pcacheinfo->icache_size); - - /* - * 2. clear CP0 taglo/taghi register; - */ - pcacheop->Clear_TagLo(); - - /* - * 3. invalidate instruction cache; - */ - while(start < end) { - pcacheop->Invalidate_Icache(start); //index invalidate icache - start += pcacheinfo->icacheline_size; - } - - /* - * 4. invalidate data cache; - */ - start = K0BASE; - end = (start + pcacheinfo->dcache_size); - while(start < end) { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) { - pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - /* enable cache */ - enable_cpu_cache(); - rt_kprintf("enable cpu cache done\n"); - - return ; -} +#include "../common/mipsregs.h" +#include "cache.h" + +#define K0BASE 0x80000000 +#define PRID_3210I 0x4200 + +typedef struct cacheinfo_t { + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; +} cacheinfo_t ; + +typedef struct cacheop_t { + void (*Clear_TagLo) (void); + void (*Invalidate_Icache) (unsigned int); + void (*Invalidate_Dcache_Fill) (unsigned int); + void (*Invalidate_Dcache_ClearTag) (unsigned int); + void (*Init_Cache)(void); +} cacheop_t ; + +static cacheop_t cacheop, *pcacheop; +static cacheinfo_t cacheinfo, *pcacheinfo; + +int identify_cpu (void) +{ + unsigned int cpu_id; + void invalidate_cache (void); + + pcacheop = &cacheop; + pcacheinfo = &cacheinfo; + + rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); + cpu_id = read_c0_prid(); + switch (cpu_id) + { + case PRID_3210I: + rt_kprintf ("CPU:SoC3210\n"); + pcacheop->Clear_TagLo = Clear_TagLo; + pcacheop->Invalidate_Icache = Invalidate_Icache_Gc3210I; + pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Gc3210I; + pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Gc3210I; + break; + default: + rt_kprintf ("Unknown CPU type, system halted!\n"); + while (1) {} + break; + } + + return 0; +} + +void probe_cache(void) +{ + unsigned int config = read_c0_config (); + unsigned int icache_size, ic_lsize; + unsigned int dcache_size, dc_lsize; + + icache_size = 1 << (12 + ((config >> 9) & 7)); + dcache_size = 1 << (12 + ((config >> 6) & 7)); + ic_lsize = 16 << ((config >> 5) & 1); + dc_lsize = 16 << ((config >> 4) & 1); + + rt_kprintf("DCache %2dkb, linesize %d bytes.\n", + dcache_size >> 10, dc_lsize); + rt_kprintf("ICache %2dkb, linesize %d bytes.\n", + icache_size >> 10, ic_lsize); + + pcacheinfo->icache_size = icache_size; + pcacheinfo->dcache_size = dcache_size; + pcacheinfo->icacheline_size = ic_lsize; + pcacheinfo->dcacheline_size = dc_lsize; + + return ; +} + +void invalidate_writeback_dcache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + start = K0BASE; + while(start < end) { + Writeback_Invalidate_Dcache(start); //hit writeback invalidate + start += pcacheinfo->dcacheline_size; + } +} + +void invalidate_writeback_dcache(unsigned long addr, int size) +{ + unsigned long start, end; + + start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); + end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); + + while(start dcacheline_size; + } +} + + +void invalidate_icache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->icache_size); + + while(start < end) { + pcacheop->Invalidate_Icache(start); + start += pcacheinfo->icacheline_size; + } +} + +void invalidate_dcache_all() +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + while(start icacheline_size; + } +} + +//with cache disabled +void init_dcache(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while(start < end){ + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + +} + +void rt_hw_cache_init(void) +{ + unsigned int start, end; + + /* 1. identify cpu and probe cache */ + identify_cpu(); + probe_cache(); + + start = K0BASE; + end = (start + pcacheinfo->icache_size); + + /* + * 2. clear CP0 taglo/taghi register; + */ + pcacheop->Clear_TagLo(); + + /* + * 3. invalidate instruction cache; + */ + while(start < end) { + pcacheop->Invalidate_Icache(start); //index invalidate icache + start += pcacheinfo->icacheline_size; + } + + /* + * 4. invalidate data cache; + */ + start = K0BASE; + end = (start + pcacheinfo->dcache_size); + while(start < end) { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) { + pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + /* enable cache */ + enable_cpu_cache(); + rt_kprintf("enable cpu cache done\n"); + + return ; +} diff --git a/libcpu/mips/loongson/cache.h b/libcpu/mips/loongson/cache.h index fb4899a6b294095e364c41a5ff4d5fcaefe3e531..26f7649b4255856987002af6a394c1ae4d978fb6 100644 --- a/libcpu/mips/loongson/cache.h +++ b/libcpu/mips/loongson/cache.h @@ -1,47 +1,47 @@ -#ifndef __CACHE_H__ -#define __CACHE_H__ - -/* - * Cache Operations - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 -/* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 -/* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b -/* 0x1c is unused */ -/* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -extern void Clear_TagLo (void); - -extern void Invalidate_Icache_Gc3210I (unsigned int); -extern void Invalidate_Dcache_ClearTag_Gc3210I (unsigned int); -extern void Invalidate_Dcache_Fill_Gc3210I(unsigned int); -extern void Writeback_Invalidate_Dcache(unsigned int); - -void rt_hw_cache_init(void); - -#endif +#ifndef __CACHE_H__ +#define __CACHE_H__ + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 +/* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 +/* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b +/* 0x1c is unused */ +/* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +extern void Clear_TagLo (void); + +extern void Invalidate_Icache_Gc3210I (unsigned int); +extern void Invalidate_Dcache_ClearTag_Gc3210I (unsigned int); +extern void Invalidate_Dcache_Fill_Gc3210I(unsigned int); +extern void Writeback_Invalidate_Dcache(unsigned int); + +void rt_hw_cache_init(void); + +#endif diff --git a/libcpu/mips/loongson/cache.inc b/libcpu/mips/loongson/cache.inc index 6adac658577155dcff43b0133334901ffc862212..815abb7f925069d943abaa5500c1d01b3bf0e62e 100644 --- a/libcpu/mips/loongson/cache.inc +++ b/libcpu/mips/loongson/cache.inc @@ -1,38 +1,38 @@ -#ifndef __CACHE_H__ -#define __CACHE_H__ - -/* - * Cache Operations - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 -/* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 -/* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b -/* 0x1c is unused */ -/* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -#endif +#ifndef __CACHE_H__ +#define __CACHE_H__ + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 +/* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 +/* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b +/* 0x1c is unused */ +/* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +#endif diff --git a/libcpu/mips/loongson/context_gcc.S b/libcpu/mips/loongson/context_gcc.S index 65cab6e1473f66923097dc45793380d76da63d71..1bb953fe8cca569e54b373ad2cad14787e3b648e 100644 --- a/libcpu/mips/loongson/context_gcc.S +++ b/libcpu/mips/loongson/context_gcc.S @@ -1,141 +1,141 @@ -/* - * File : context_gcc.S - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-11 bernard port to Loongson SoC3210 - */ -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "soc3210.h" - - .section ".text", "ax" - .set noreorder - -/* - * rt_base_t rt_hw_interrupt_disable() - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0, CP0_STATUS - and v1, v0, 0xfffffffe - mtc0 v1, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - mtc0 a0, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl mips_irq_handle -mips_irq_handle: - SAVE_ALL - - mfc0 t0, CP0_CAUSE - and t1, t0, 0xff - bnez t1, spurious_interrupt /* check exception */ - nop - - /* let k0 keep the current context sp */ - move k0, sp - /* switch to kernel stack */ - li sp, SYSTEM_STACK - - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop - -spurious_interrupt: - RESTORE_ALL_AND_RET - - .set reorder +/* + * File : context_gcc.S + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-11 bernard port to Loongson SoC3210 + */ +#include "../common/mips.inc" +#include "../common/stackframe.h" +#include "soc3210.h" + + .section ".text", "ax" + .set noreorder + +/* + * rt_base_t rt_hw_interrupt_disable() + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mfc0 v0, CP0_STATUS + and v1, v0, 0xfffffffe + mtc0 v1, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + mtc0 a0, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + mtc0 ra, CP0_EPC + SAVE_ALL + + sw sp, 0(a0) /* store sp in preempted tasks TCB */ + lw sp, 0(a1) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + lw sp, 0(a0) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + la t0, rt_thread_switch_interrupt_flag + lw t1, 0(t0) + nop + bnez t1, _reswitch + nop + li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ + sw t1, 0(t0) + la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + sw a0, 0(t0) +_reswitch: + la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + sw a1, 0(t0) + jr ra + nop + +/* + * void rt_hw_context_switch_interrupt_do(rt_base_t flag) + */ + .globl rt_interrupt_enter + .globl rt_interrupt_leave + .globl mips_irq_handle +mips_irq_handle: + SAVE_ALL + + mfc0 t0, CP0_CAUSE + and t1, t0, 0xff + bnez t1, spurious_interrupt /* check exception */ + nop + + /* let k0 keep the current context sp */ + move k0, sp + /* switch to kernel stack */ + li sp, SYSTEM_STACK + + jal rt_interrupt_enter + nop + jal rt_interrupt_dispatch + nop + jal rt_interrupt_leave + nop + + /* switch sp back to thread's context */ + move sp, k0 + + /* + * if rt_thread_switch_interrupt_flag set, jump to + * rt_hw_context_switch_interrupt_do and don't return + */ + la k0, rt_thread_switch_interrupt_flag + lw k1, 0(k0) + beqz k1, spurious_interrupt + nop + sw zero, 0(k0) /* clear flag */ + nop + + /* + * switch to the new thread + */ + la k0, rt_interrupt_from_thread + lw k1, 0(k0) + nop + sw sp, 0(k1) /* store sp in preempted tasks's TCB */ + + la k0, rt_interrupt_to_thread + lw k1, 0(k0) + nop + lw sp, 0(k1) /* get new task's stack pointer */ + j spurious_interrupt + nop + +spurious_interrupt: + RESTORE_ALL_AND_RET + + .set reorder diff --git a/libcpu/mips/loongson/cpu.c b/libcpu/mips/loongson/cpu.c index 49b310d01cc328a6dfae845d95638f08efd62852..c459061f0a247db49a3bd6711f0f9fed094209df 100644 --- a/libcpu/mips/loongson/cpu.c +++ b/libcpu/mips/loongson/cpu.c @@ -1,50 +1,50 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2010-09-11 Bernard add CPU reset implementation - */ -#include -#include - -/** - * @addtogroup Loongson SoC3210 - */ - -/*@{*/ - -/** - * this function will reset CPU - * - */ -void rt_hw_cpu_reset(void) -{ - /* open the watch-dog */ - WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WD_CTRL |= 0x01; - - rt_kprintf("reboot system...\n"); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -void rt_hw_cpu_shutdown(void) -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -/*@}*/ - +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2010-09-11 Bernard add CPU reset implementation + */ +#include +#include + +/** + * @addtogroup Loongson SoC3210 + */ + +/*@{*/ + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset(void) +{ + /* open the watch-dog */ + WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WD_CTRL |= 0x01; + + rt_kprintf("reboot system...\n"); + while (1); +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + +/*@}*/ + diff --git a/libcpu/mips/loongson/exception.c b/libcpu/mips/loongson/exception.c index 77d1414a29a79ab9f92ba39f16f63eb08a5d6396..1c6aec53ac5d99ebd778317662efb9bd0df964df 100644 --- a/libcpu/mips/loongson/exception.c +++ b/libcpu/mips/loongson/exception.c @@ -1,83 +1,83 @@ -/* - * File : exception.c - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include -#include -#include "../common/exception.h" -#include "../common/mipsregs.h" - -/** - * @addtogroup SoC3210 - */ -/*@{*/ - -/** - * exception handle table - */ -#define RT_EXCEPTION_MAX 8 -exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -void cache_error_handler(void) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -static void unhandled_exception_handle(pt_regs_t *regs) -{ - rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); -} - -void install_default_execpt_handle(void) -{ - rt_int32_t i; - - for (i=0; i> 8; - - for (index = RT_EXCEPTION_MAX; index > 0; index --) - { - if (cause & (1 << index)) - { - sys_exception_handlers[index](regs); - cause &= ~(1 << index); - } - } -} - -/*@}*/ +/* + * File : exception.c + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#include +#include +#include "../common/exception.h" +#include "../common/mipsregs.h" + +/** + * @addtogroup SoC3210 + */ +/*@{*/ + +/** + * exception handle table + */ +#define RT_EXCEPTION_MAX 8 +exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; + +/** + * setup the exception handle + */ +exception_func_t rt_set_except_vector(int n, exception_func_t func) +{ + exception_func_t old_handler = sys_exception_handlers[n]; + + if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) + { + return 0; + } + + sys_exception_handlers[n] = func; + + return old_handler; +} + +void tlb_refill_handler(void) +{ + rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +void cache_error_handler(void) +{ + rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +static void unhandled_exception_handle(pt_regs_t *regs) +{ + rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); +} + +void install_default_execpt_handle(void) +{ + rt_int32_t i; + + for (i=0; i> 8; + + for (index = RT_EXCEPTION_MAX; index > 0; index --) + { + if (cause & (1 << index)) + { + sys_exception_handlers[index](regs); + cause &= ~(1 << index); + } + } +} + +/*@}*/ diff --git a/libcpu/mips/loongson/interrupt.c b/libcpu/mips/loongson/interrupt.c index d70b58da973b70126793d9cf3445b06192134b35..4b97068a70af7e1e0cc777ac377f19fb32c02f49 100644 --- a/libcpu/mips/loongson/interrupt.c +++ b/libcpu/mips/loongson/interrupt.c @@ -1,130 +1,130 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-10-15 Bernard first version - */ -#include -#include "soc3210.h" - -#define MAX_INTR 32 - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static rt_isr_handler_t irq_handle_table[MAX_INTR]; -void rt_interrupt_dispatch(void *ptreg); -void rt_hw_timer_handler(); - -/** - * @addtogroup Loongson SoC3210 - */ - -/*@{*/ - -void rt_hw_interrupt_handler(int vector) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_int32_t index; - - for (index = 0; index < MAX_INTR; index ++) - { - irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - INT_EN &= ~(1 << vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - INT_EN |= (1 << vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) -{ - if (vector >= 0 && vector < MAX_INTR) - { - if (old_handler != RT_NULL) - *old_handler = irq_handle_table[vector]; - if (new_handler != RT_NULL) - irq_handle_table[vector] = (rt_isr_handler_t)new_handler; - } -} - -void rt_interrupt_dispatch(void *ptreg) -{ - int i; - rt_isr_handler_t irq_func; - static rt_uint32_t status = 0; - rt_uint32_t c0_status; - - /* check os timer */ - c0_status = read_c0_status(); - if (c0_status & 0x8000) - { - rt_hw_timer_handler(); - } - - if (c0_status & 0x0400) - { - /* the hardware interrupt */ - status |= INT_ISR; - if (!status) return; - - for (i = MAX_INTR; i > 0; --i) - { - if ((status & (1< +#include "soc3210.h" + +#define MAX_INTR 32 + +extern rt_uint32_t rt_interrupt_nest; +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +static rt_isr_handler_t irq_handle_table[MAX_INTR]; +void rt_interrupt_dispatch(void *ptreg); +void rt_hw_timer_handler(); + +/** + * @addtogroup Loongson SoC3210 + */ + +/*@{*/ + +void rt_hw_interrupt_handler(int vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_int32_t index; + + for (index = 0; index < MAX_INTR; index ++) + { + irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler; + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + /* mask interrupt */ + INT_EN &= ~(1 << vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + INT_EN |= (1 << vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + if (vector >= 0 && vector < MAX_INTR) + { + if (old_handler != RT_NULL) + *old_handler = irq_handle_table[vector]; + if (new_handler != RT_NULL) + irq_handle_table[vector] = (rt_isr_handler_t)new_handler; + } +} + +void rt_interrupt_dispatch(void *ptreg) +{ + int i; + rt_isr_handler_t irq_func; + static rt_uint32_t status = 0; + rt_uint32_t c0_status; + + /* check os timer */ + c0_status = read_c0_status(); + if (c0_status & 0x8000) + { + rt_hw_timer_handler(); + } + + if (c0_status & 0x0400) + { + /* the hardware interrupt */ + status |= INT_ISR; + if (!status) return; + + for (i = MAX_INTR; i > 0; --i) + { + if ((status & (1< -#include "../common/mipsregs.h" -#include "../common/mipscfg.h" - -mips32_core_cfg_t g_mips_core = -{ - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ -}; - -static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) -{ - rt_uint16_t rets = 1; - - while (n--) - rets *= b; - - return rets; -} - -static rt_uint16_t m_log2(rt_uint16_t b) -{ - rt_uint16_t rets = 0; - - while (b != 1) - { - b /= 2; - rets++; - } - - return rets; -} - -/** +/* + * File : mipscfg.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#include +#include "../common/mipsregs.h" +#include "../common/mipscfg.h" + +mips32_core_cfg_t g_mips_core = +{ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** * read core attribute - */ -void mips32_cfg_init(void) -{ - rt_uint16_t val; - rt_uint32_t cp0_config1; - - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); - - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; - - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; - - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } -} + */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/loongson/soc3210.h b/libcpu/mips/loongson/soc3210.h index fe394ce0125e4eb1983214c21224894e09e2d3be..c4d2c3926f629dd3b72c03cc6f6973e0072ee1a1 100644 --- a/libcpu/mips/loongson/soc3210.h +++ b/libcpu/mips/loongson/soc3210.h @@ -1,172 +1,172 @@ -#ifndef __SOC3210_H__ -#define __SOC3210_H__ - -#include "../common/mipsregs.h" - -/* registers */ -#define __REG8(addr) *((volatile unsigned char *)(addr)) -#define __REG16(addr) *((volatile unsigned short *)(addr)) -#define __REG32(addr) *((volatile unsigned int *)(addr)) - -#define EMI_BASE 0xBF000000 -#define NN_BASE 0xBF000040 -#define LCD_BASE 0xBF001000 -#define HSB_MISC_BASE 0xBF003200 -#define SPI_BASE 0xBF004000 -#define PS2_BASE 0xBF004040 -#define UART0_BASE 0xBF004080 -#define UART1_BASE 0xBF004090 -#define I2C_BASE 0xBF0040D0 -#define LPB_MISC_BASE 0xBF004100 -#define AC97_BASE 0xBF004200 -#define AC97_DMA_BASE 0xBF004280 -#define CAN1_BASE 0xBF004300 -#define CAN0_BASE 0xBF004400 -#define MAC0_BASE 0xBF005200 -#define MAC1_BASE 0xBF005300 - -/* LCD registers */ -#define LCD_CTRL __REG32(LCD_BASE + 0x000) -#define LCD_STAT __REG32(LCD_BASE + 0x004) -#define LCD_HTIM __REG32(LCD_BASE + 0x008) -#define LCD_VTIM __REG32(LCD_BASE + 0x00C) -#define LCD_HVLEN __REG32(LCD_BASE + 0x010) -#define LCD_VBARA __REG32(LCD_BASE + 0x014) -#define LCD_VBARB __REG32(LCD_BASE + 0x018) -#define LCD_PCLT __REG32(LCD_BASE + 0x800) - -/* HSB misc registers */ -#define HSB_MISC_REG __REG32(HSB_MISC_BASE + 0x00) -#define INT_EDGE __REG32(HSB_MISC_BASE + 0x04) -#define INT_STEER __REG32(HSB_MISC_BASE + 0x08) -#define INT_POL __REG32(HSB_MISC_BASE + 0x0C) -#define INT_SET __REG32(HSB_MISC_BASE + 0x10) -#define INT_CLR __REG32(HSB_MISC_BASE + 0x14) -#define INT_EN __REG32(HSB_MISC_BASE + 0x18) -#define INT_ISR __REG32(HSB_MISC_BASE + 0x1C) -#define GPIO_OE_60_29 __REG32(HSB_MISC_BASE + 0x20) -#define GPIO_I_60_29 __REG32(HSB_MISC_BASE + 0x24) -#define GPIO_O_60_29 __REG32(HSB_MISC_BASE + 0x28) -#define HSB_ARB_CFG __REG32(HSB_MISC_BASE + 0x2C) -#define WD_TIMER __REG32(HSB_MISC_BASE + 0x30) -#define WD_CTRL __REG32(HSB_MISC_BASE + 0x34) - -/* SPI registers */ -#define SPI_SPCR __REG8(SPI_BASE + 0x00) -#define SPI_SPSR __REG8(SPI_BASE + 0x01) -#define SPI_TX_FIFO __REG8(SPI_BASE + 0x02) -#define SPI_SPER __REG8(SPI_BASE + 0x03) - -/* PS/2 registers */ -#define PS2_RIBUF __REG8(PS2_BASE + 0x00) -#define PS2_WOBUF __REG8(PS2_BASE + 0x00) -#define PS2_RSR __REG8(PS2_BASE + 0x04) -#define PS2_WSC __REG8(PS2_BASE + 0x04) -#define PS2_DLL __REG8(PS2_BASE + 0x08) -#define PS2_DLH __REG8(PS2_BASE + 0x09) -#define PS2_DL_KBD __REG8(PS2_BASE + 0x0A) -#define PS2_DL_AUX __REG8(PS2_BASE + 0x0B) - -/* UART registers */ -#define UART_DAT(base) __REG8(base + 0x00) -#define UART_IER(base) __REG8(base + 0x01) -#define UART_IIR(base) __REG8(base + 0x02) -#define UART_FCR(base) __REG8(base + 0x02) -#define UART_LCR(base) __REG8(base + 0x03) -#define UART_MCR(base) __REG8(base + 0x04) -#define UART_LSR(base) __REG8(base + 0x05) -#define UART_MSR(base) __REG8(base + 0x06) - -#define UART_LSB(base) __REG8(base + 0x00) -#define UART_MSB(base) __REG8(base + 0x01) - -/* UART0 registers */ -#define UART0_DAT __REG8(UART0_BASE + 0x00) -#define UART0_IER __REG8(UART0_BASE + 0x01) -#define UART0_IIR __REG8(UART0_BASE + 0x02) -#define UART0_FCR __REG8(UART0_BASE + 0x02) -#define UART0_LCR __REG8(UART0_BASE + 0x03) -#define UART0_MCR __REG8(UART0_BASE + 0x04) -#define UART0_LSR __REG8(UART0_BASE + 0x05) -#define UART0_MSR __REG8(UART0_BASE + 0x06) - -#define UART0_LSB __REG8(UART0_BASE + 0x00) -#define UART0_MSB __REG8(UART0_BASE + 0x01) - -/* UART1 registers */ -#define UART1_DAT __REG8(UART1_BASE + 0x00) -#define UART1_IER __REG8(UART1_BASE + 0x01) -#define UART1_IIR __REG8(UART1_BASE + 0x02) -#define UART1_FCR __REG8(UART1_BASE + 0x02) -#define UART1_LCR __REG8(UART1_BASE + 0x03) -#define UART1_MCR __REG8(UART1_BASE + 0x04) -#define UART1_LSR __REG8(UART1_BASE + 0x05) -#define UART1_MSR __REG8(UART1_BASE + 0x06) - -#define UART1_LSB __REG8(UART1_BASE + 0x00) -#define UART1_MSB __REG8(UART1_BASE + 0x01) - -/* LPB misc registers */ -#define GPIO_OE_7_0 __REG8(LPB_MISC_BASE + 0x00) -#define GPIO_OE_15_8 __REG8(LPB_MISC_BASE + 0x01) -#define GPIO_OE_23_16 __REG8(LPB_MISC_BASE + 0x02) -#define GPIO_OE_28_24 __REG8(LPB_MISC_BASE + 0x03) -#define GPIO_I_7_0 __REG8(LPB_MISC_BASE + 0x10) -#define GPIO_I_15_8 __REG8(LPB_MISC_BASE + 0x11) -#define GPIO_I_23_16 __REG8(LPB_MISC_BASE + 0x12) -#define GPIO_I_28_24 __REG8(LPB_MISC_BASE + 0x13) -#define GPIO_O_7_0 __REG8(LPB_MISC_BASE + 0x20) -#define GPIO_O_15_8 __REG8(LPB_MISC_BASE + 0x21) -#define GPIO_O_23_16 __REG8(LPB_MISC_BASE + 0x22) -#define GPIO_O_28_24 __REG8(LPB_MISC_BASE + 0x23) -#define LPB_MISC_CFG __REG8(LPB_MISC_BASE + 0x40) - -/* MAC0 registers */ -#define MAC0_BUS_MODE __REG32(MAC0_BASE + 0x00) -#define MAC0_TX_POLL_REQ __REG32(MAC0_BASE + 0x08) -#define MAC0_RX_POLL_REQ __REG32(MAC0_BASE + 0x10) -#define MAC0_RX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x18) -#define MAC0_TX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x20) -#define MAC0_STATUS __REG32(MAC0_BASE + 0x28) -#define MAC0_OP_MODE __REG32(MAC0_BASE + 0x30) -#define MAC0_INTERRUPT_EN __REG32(MAC0_BASE + 0x38) -#define MAC0_MISSED_FRAME_STATISTIC __REG32(MAC0_BASE + 0x40) -#define MAC0_SMI_EEPROM_CTL __REG32(MAC0_BASE + 0x48) -#define MAC0_BYTE_ALIGN __REG32(MAC0_BASE + 0x50) -#define MAC0_GPT_IM_CTL __REG32(MAC0_BASE + 0x58) - -/* MAC1 registers */ -#define MAC1_BUS_MODE __REG32(MAC1_BASE + 0x00) -#define MAC1_TX_POLL_REQ __REG32(MAC1_BASE + 0x08) -#define MAC1_RX_POLL_REQ __REG32(MAC1_BASE + 0x10) -#define MAC1_RX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x18) -#define MAC1_TX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x20) -#define MAC1_STATUS __REG32(MAC1_BASE + 0x28) -#define MAC1_OP_MODE __REG32(MAC1_BASE + 0x30) -#define MAC1_INTERRUPT_EN __REG32(MAC1_BASE + 0x38) -#define MAC1_MISSED_FRAME_STATISTIC __REG32(MAC1_BASE + 0x40) -#define MAC1_SMI_EEPROM_CTL __REG32(MAC1_BASE + 0x48) -#define MAC1_BYTE_ALIGN __REG32(MAC1_BASE + 0x50) -#define MAC1_GPT_IM_CTL __REG32(MAC1_BASE + 0x58) - -/* Peripheral Interrupt Number */ -#define IRQ_LCD 0 -#define IRQ_MAC1 1 -#define IRQ_MAC2 2 -#define IRQ_AC97 3 -#define IRQ_SPI 8 -#define IRQ_KEY 9 -#define IRQ_MOUSE 10 -#define IRQ_UART0 11 -#define IRQ_UART1 12 -#define IRQ_I2C 13 -#define IRQ_CAN0 14 -#define IRQ_CAN1 15 -#define IRQ_GPIO15 20 -#define IRQ_GPIO14 21 -#define IRQ_GPIO13 22 -#define IRQ_GPIO12 23 - -#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */ - -#endif +#ifndef __SOC3210_H__ +#define __SOC3210_H__ + +#include "../common/mipsregs.h" + +/* registers */ +#define __REG8(addr) *((volatile unsigned char *)(addr)) +#define __REG16(addr) *((volatile unsigned short *)(addr)) +#define __REG32(addr) *((volatile unsigned int *)(addr)) + +#define EMI_BASE 0xBF000000 +#define NN_BASE 0xBF000040 +#define LCD_BASE 0xBF001000 +#define HSB_MISC_BASE 0xBF003200 +#define SPI_BASE 0xBF004000 +#define PS2_BASE 0xBF004040 +#define UART0_BASE 0xBF004080 +#define UART1_BASE 0xBF004090 +#define I2C_BASE 0xBF0040D0 +#define LPB_MISC_BASE 0xBF004100 +#define AC97_BASE 0xBF004200 +#define AC97_DMA_BASE 0xBF004280 +#define CAN1_BASE 0xBF004300 +#define CAN0_BASE 0xBF004400 +#define MAC0_BASE 0xBF005200 +#define MAC1_BASE 0xBF005300 + +/* LCD registers */ +#define LCD_CTRL __REG32(LCD_BASE + 0x000) +#define LCD_STAT __REG32(LCD_BASE + 0x004) +#define LCD_HTIM __REG32(LCD_BASE + 0x008) +#define LCD_VTIM __REG32(LCD_BASE + 0x00C) +#define LCD_HVLEN __REG32(LCD_BASE + 0x010) +#define LCD_VBARA __REG32(LCD_BASE + 0x014) +#define LCD_VBARB __REG32(LCD_BASE + 0x018) +#define LCD_PCLT __REG32(LCD_BASE + 0x800) + +/* HSB misc registers */ +#define HSB_MISC_REG __REG32(HSB_MISC_BASE + 0x00) +#define INT_EDGE __REG32(HSB_MISC_BASE + 0x04) +#define INT_STEER __REG32(HSB_MISC_BASE + 0x08) +#define INT_POL __REG32(HSB_MISC_BASE + 0x0C) +#define INT_SET __REG32(HSB_MISC_BASE + 0x10) +#define INT_CLR __REG32(HSB_MISC_BASE + 0x14) +#define INT_EN __REG32(HSB_MISC_BASE + 0x18) +#define INT_ISR __REG32(HSB_MISC_BASE + 0x1C) +#define GPIO_OE_60_29 __REG32(HSB_MISC_BASE + 0x20) +#define GPIO_I_60_29 __REG32(HSB_MISC_BASE + 0x24) +#define GPIO_O_60_29 __REG32(HSB_MISC_BASE + 0x28) +#define HSB_ARB_CFG __REG32(HSB_MISC_BASE + 0x2C) +#define WD_TIMER __REG32(HSB_MISC_BASE + 0x30) +#define WD_CTRL __REG32(HSB_MISC_BASE + 0x34) + +/* SPI registers */ +#define SPI_SPCR __REG8(SPI_BASE + 0x00) +#define SPI_SPSR __REG8(SPI_BASE + 0x01) +#define SPI_TX_FIFO __REG8(SPI_BASE + 0x02) +#define SPI_SPER __REG8(SPI_BASE + 0x03) + +/* PS/2 registers */ +#define PS2_RIBUF __REG8(PS2_BASE + 0x00) +#define PS2_WOBUF __REG8(PS2_BASE + 0x00) +#define PS2_RSR __REG8(PS2_BASE + 0x04) +#define PS2_WSC __REG8(PS2_BASE + 0x04) +#define PS2_DLL __REG8(PS2_BASE + 0x08) +#define PS2_DLH __REG8(PS2_BASE + 0x09) +#define PS2_DL_KBD __REG8(PS2_BASE + 0x0A) +#define PS2_DL_AUX __REG8(PS2_BASE + 0x0B) + +/* UART registers */ +#define UART_DAT(base) __REG8(base + 0x00) +#define UART_IER(base) __REG8(base + 0x01) +#define UART_IIR(base) __REG8(base + 0x02) +#define UART_FCR(base) __REG8(base + 0x02) +#define UART_LCR(base) __REG8(base + 0x03) +#define UART_MCR(base) __REG8(base + 0x04) +#define UART_LSR(base) __REG8(base + 0x05) +#define UART_MSR(base) __REG8(base + 0x06) + +#define UART_LSB(base) __REG8(base + 0x00) +#define UART_MSB(base) __REG8(base + 0x01) + +/* UART0 registers */ +#define UART0_DAT __REG8(UART0_BASE + 0x00) +#define UART0_IER __REG8(UART0_BASE + 0x01) +#define UART0_IIR __REG8(UART0_BASE + 0x02) +#define UART0_FCR __REG8(UART0_BASE + 0x02) +#define UART0_LCR __REG8(UART0_BASE + 0x03) +#define UART0_MCR __REG8(UART0_BASE + 0x04) +#define UART0_LSR __REG8(UART0_BASE + 0x05) +#define UART0_MSR __REG8(UART0_BASE + 0x06) + +#define UART0_LSB __REG8(UART0_BASE + 0x00) +#define UART0_MSB __REG8(UART0_BASE + 0x01) + +/* UART1 registers */ +#define UART1_DAT __REG8(UART1_BASE + 0x00) +#define UART1_IER __REG8(UART1_BASE + 0x01) +#define UART1_IIR __REG8(UART1_BASE + 0x02) +#define UART1_FCR __REG8(UART1_BASE + 0x02) +#define UART1_LCR __REG8(UART1_BASE + 0x03) +#define UART1_MCR __REG8(UART1_BASE + 0x04) +#define UART1_LSR __REG8(UART1_BASE + 0x05) +#define UART1_MSR __REG8(UART1_BASE + 0x06) + +#define UART1_LSB __REG8(UART1_BASE + 0x00) +#define UART1_MSB __REG8(UART1_BASE + 0x01) + +/* LPB misc registers */ +#define GPIO_OE_7_0 __REG8(LPB_MISC_BASE + 0x00) +#define GPIO_OE_15_8 __REG8(LPB_MISC_BASE + 0x01) +#define GPIO_OE_23_16 __REG8(LPB_MISC_BASE + 0x02) +#define GPIO_OE_28_24 __REG8(LPB_MISC_BASE + 0x03) +#define GPIO_I_7_0 __REG8(LPB_MISC_BASE + 0x10) +#define GPIO_I_15_8 __REG8(LPB_MISC_BASE + 0x11) +#define GPIO_I_23_16 __REG8(LPB_MISC_BASE + 0x12) +#define GPIO_I_28_24 __REG8(LPB_MISC_BASE + 0x13) +#define GPIO_O_7_0 __REG8(LPB_MISC_BASE + 0x20) +#define GPIO_O_15_8 __REG8(LPB_MISC_BASE + 0x21) +#define GPIO_O_23_16 __REG8(LPB_MISC_BASE + 0x22) +#define GPIO_O_28_24 __REG8(LPB_MISC_BASE + 0x23) +#define LPB_MISC_CFG __REG8(LPB_MISC_BASE + 0x40) + +/* MAC0 registers */ +#define MAC0_BUS_MODE __REG32(MAC0_BASE + 0x00) +#define MAC0_TX_POLL_REQ __REG32(MAC0_BASE + 0x08) +#define MAC0_RX_POLL_REQ __REG32(MAC0_BASE + 0x10) +#define MAC0_RX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x18) +#define MAC0_TX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x20) +#define MAC0_STATUS __REG32(MAC0_BASE + 0x28) +#define MAC0_OP_MODE __REG32(MAC0_BASE + 0x30) +#define MAC0_INTERRUPT_EN __REG32(MAC0_BASE + 0x38) +#define MAC0_MISSED_FRAME_STATISTIC __REG32(MAC0_BASE + 0x40) +#define MAC0_SMI_EEPROM_CTL __REG32(MAC0_BASE + 0x48) +#define MAC0_BYTE_ALIGN __REG32(MAC0_BASE + 0x50) +#define MAC0_GPT_IM_CTL __REG32(MAC0_BASE + 0x58) + +/* MAC1 registers */ +#define MAC1_BUS_MODE __REG32(MAC1_BASE + 0x00) +#define MAC1_TX_POLL_REQ __REG32(MAC1_BASE + 0x08) +#define MAC1_RX_POLL_REQ __REG32(MAC1_BASE + 0x10) +#define MAC1_RX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x18) +#define MAC1_TX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x20) +#define MAC1_STATUS __REG32(MAC1_BASE + 0x28) +#define MAC1_OP_MODE __REG32(MAC1_BASE + 0x30) +#define MAC1_INTERRUPT_EN __REG32(MAC1_BASE + 0x38) +#define MAC1_MISSED_FRAME_STATISTIC __REG32(MAC1_BASE + 0x40) +#define MAC1_SMI_EEPROM_CTL __REG32(MAC1_BASE + 0x48) +#define MAC1_BYTE_ALIGN __REG32(MAC1_BASE + 0x50) +#define MAC1_GPT_IM_CTL __REG32(MAC1_BASE + 0x58) + +/* Peripheral Interrupt Number */ +#define IRQ_LCD 0 +#define IRQ_MAC1 1 +#define IRQ_MAC2 2 +#define IRQ_AC97 3 +#define IRQ_SPI 8 +#define IRQ_KEY 9 +#define IRQ_MOUSE 10 +#define IRQ_UART0 11 +#define IRQ_UART1 12 +#define IRQ_I2C 13 +#define IRQ_CAN0 14 +#define IRQ_CAN1 15 +#define IRQ_GPIO15 20 +#define IRQ_GPIO14 21 +#define IRQ_GPIO13 22 +#define IRQ_GPIO12 23 + +#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */ + +#endif diff --git a/libcpu/mips/loongson/stack.c b/libcpu/mips/loongson/stack.c index 60e9aa4fb49492c176803d0763e15681d94ce3a1..dbfcf7ea91b8d7443d8b945ea3c4b278747d362a 100644 --- a/libcpu/mips/loongson/stack.c +++ b/libcpu/mips/loongson/stack.c @@ -1,96 +1,96 @@ -/* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-07-07 Bernard porting to Jz47xx - */ - -#include - -/** - * @addtogroup Loongson SoC3210 - */ - -/*@{*/ - -extern rt_uint32_t cp0_get_cause(void); -extern rt_uint32_t cp0_get_status(void); -extern rt_uint32_t cp0_get_hi(void); -extern rt_uint32_t cp0_get_lo(void); - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - static rt_uint32_t g_sr = 0; - - if (g_sr == 0) - { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x8401; - } - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-07-07 Bernard porting to Jz47xx + */ + +#include + +/** + * @addtogroup Loongson SoC3210 + */ + +/*@{*/ + +extern rt_uint32_t cp0_get_cause(void); +extern rt_uint32_t cp0_get_status(void); +extern rt_uint32_t cp0_get_hi(void); +extern rt_uint32_t cp0_get_lo(void); + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + static rt_uint32_t g_sr = 0; + + if (g_sr == 0) + { + g_sr = cp0_get_status(); + g_sr &= 0xfffffffe; + g_sr |= 0x8401; + } + + /** Start at stack top */ + stk = (rt_uint32_t *)stack_addr; + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ + *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ + *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ + *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ + *(--stk) = (rt_uint32_t) texit; /* ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* sp */ + *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ + *(--stk) = (rt_uint32_t) parameter; /* a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/mips/loongson/start_gcc.S b/libcpu/mips/loongson/start_gcc.S index f558622df6eb8fbf5150d046bb13ea7c902cbba0..2b0ef3a39bb97c985479c769b8f04eb133122418 100644 --- a/libcpu/mips/loongson/start_gcc.S +++ b/libcpu/mips/loongson/start_gcc.S @@ -1,130 +1,130 @@ -/* - * File : start_gcc.S - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-04 bernard porting to Jz47xx - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "soc3210.h" - - .section ".start", "ax" - .set noreorder - - /* the program entry */ - .globl _start -_start: - .set noreorder - la ra, _start - - /* disable interrupt */ - mfc0 t0, CP0_STATUS - and t0, 0xfffffffe # By default it will be disabled. - mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. - nop - - /* disable cache */ - mfc0 t0, CP0_CONFIG - and t0, 0xfffffff8 - or t0, 0x2 # disable,!default value is not it! - mtc0 t0, CP0_CONFIG # Set CPU to disable cache. - nop - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - .set reorder - - .globl cp0_get_cause -cp0_get_cause: - mfc0 v0, CP0_CAUSE - jr ra - nop - - .globl cp0_get_status -cp0_get_status: - mfc0 v0, CP0_STATUS - jr ra - nop - - .globl cp0_get_hi -cp0_get_hi: - mfhi v0 - jr ra - nop - - .globl cp0_get_lo -cp0_get_lo: - mflo v0 - jr ra - nop - - .extern tlb_refill_handler - .extern cache_error_handler - - /* Exception Handler */ - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - .global tlb_refill_exception - .type tlb_refill_exception,@function -tlb_refill_exception: - j tlb_refill_handler - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j cache_error_handler - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - .global general_exception - .type general_exception,@function -general_exception: - j _general_exception_handler - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - .global irq_exception - .type irq_exception,@function -irq_exception: - j _irq_handler - nop - - .section .vectors, "ax", %progbits - .extern mips_irq_handle - - /* general exception handler */ -_general_exception_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder - - /* interrupt handler */ -_irq_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder +/* + * File : start_gcc.S + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-04 bernard porting to Jz47xx + */ + +#include "../common/mips.inc" +#include "../common/stackframe.h" +#include "soc3210.h" + + .section ".start", "ax" + .set noreorder + + /* the program entry */ + .globl _start +_start: + .set noreorder + la ra, _start + + /* disable interrupt */ + mfc0 t0, CP0_STATUS + and t0, 0xfffffffe # By default it will be disabled. + mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. + nop + + /* disable cache */ + mfc0 t0, CP0_CONFIG + and t0, 0xfffffff8 + or t0, 0x2 # disable,!default value is not it! + mtc0 t0, CP0_CONFIG # Set CPU to disable cache. + nop + + /* setup stack pointer */ + li sp, SYSTEM_STACK + la gp, _gp + + /* clear bss */ + la t0, __bss_start + la t1, __bss_end +_clr_bss_loop: + sw zero, 0(t0) + bne t0, t1, _clr_bss_loop + addiu t0, t0, 4 + + /* jump to RT-Thread RTOS */ + jal rtthread_startup + nop + + /* restart, never die */ + j _start + nop + .set reorder + + .globl cp0_get_cause +cp0_get_cause: + mfc0 v0, CP0_CAUSE + jr ra + nop + + .globl cp0_get_status +cp0_get_status: + mfc0 v0, CP0_STATUS + jr ra + nop + + .globl cp0_get_hi +cp0_get_hi: + mfhi v0 + jr ra + nop + + .globl cp0_get_lo +cp0_get_lo: + mflo v0 + jr ra + nop + + .extern tlb_refill_handler + .extern cache_error_handler + + /* Exception Handler */ + /* 0x0 - TLB refill handler */ + .section .vectors.1, "ax", %progbits + .global tlb_refill_exception + .type tlb_refill_exception,@function +tlb_refill_exception: + j tlb_refill_handler + nop + + /* 0x100 - Cache error handler */ + .section .vectors.2, "ax", %progbits + j cache_error_handler + nop + + /* 0x180 - Exception/Interrupt handler */ + .section .vectors.3, "ax", %progbits + .global general_exception + .type general_exception,@function +general_exception: + j _general_exception_handler + nop + + /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ + .section .vectors.4, "ax", %progbits + .global irq_exception + .type irq_exception,@function +irq_exception: + j _irq_handler + nop + + .section .vectors, "ax", %progbits + .extern mips_irq_handle + + /* general exception handler */ +_general_exception_handler: + .set noreorder + la k0, mips_irq_handle + jr k0 + nop + .set reorder + + /* interrupt handler */ +_irq_handler: + .set noreorder + la k0, mips_irq_handle + jr k0 + nop + .set reorder diff --git a/libcpu/mips/loongson_1b/cache.c b/libcpu/mips/loongson_1b/cache.c index 550d4160ff14d022029aef0e9794c7f5340643e5..9b3dfde44daded4013fa5641252107aac3dcdac3 100644 --- a/libcpu/mips/loongson_1b/cache.c +++ b/libcpu/mips/loongson_1b/cache.c @@ -1,228 +1,228 @@ -/* - * File : cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2011-08-08 lgnq modified for LS1B - */ - -#include "../common/mipsregs.h" - -#define K0BASE 0x80000000 -#define PRID_LS1B 0x4220 - -extern void Clear_TagLo (void); -extern void Invalidate_Icache_Ls1b(unsigned int); -extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int); -extern void Invalidate_Dcache_Fill_Ls1b(unsigned int); -extern void Writeback_Invalidate_Dcache(unsigned int); - -typedef struct cacheinfo_t -{ - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; -} cacheinfo_t ; - -typedef struct cacheop_t -{ - void (*Clear_TagLo) (void); - void (*Invalidate_Icache) (unsigned int); - void (*Invalidate_Dcache_Fill) (unsigned int); - void (*Invalidate_Dcache_ClearTag) (unsigned int); - void (*Init_Cache)(void); -} cacheop_t ; - -static cacheop_t cacheop, *pcacheop; -static cacheinfo_t cacheinfo, *pcacheinfo; - -int identify_cpu(void) -{ - unsigned int cpu_id; - - pcacheop = &cacheop; - pcacheinfo = &cacheinfo; - - rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); - cpu_id = read_c0_prid(); - switch (cpu_id) - { - case PRID_LS1B: - rt_kprintf("CPU:LS1B\n"); - pcacheop->Clear_TagLo = Clear_TagLo; - pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b; - pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b; - pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b; - break; - default: - rt_kprintf("Unknown CPU type, system halted!\n"); - while (1) - { - ; - } - break; - } - - return 0; -} - -void probe_cache(void) -{ - unsigned int config1 = read_c0_config1(); - unsigned int icache_size, icache_line_size, icache_sets, icache_ways; - unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways; - - if ((icache_line_size = ((config1 >> 19) & 7))) - icache_line_size = 2 << icache_line_size; - else - icache_line_size = icache_line_size; - icache_sets = 64 << ((config1 >> 22) & 7); - icache_ways = 1 + ((config1 >> 16) & 7); - icache_size = icache_sets * icache_ways * icache_line_size; - - if ((dcache_line_size = ((config1 >> 10) & 7))) - dcache_line_size = 2 << dcache_line_size; - else - dcache_line_size = dcache_line_size; - dcache_sets = 64 << ((config1 >> 13) & 7); - dcache_ways = 1 + ((config1 >> 7) & 7); - dcache_size = dcache_sets * dcache_ways * dcache_line_size; - - rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); - rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); - - pcacheinfo->icache_size = icache_size; - pcacheinfo->dcache_size = dcache_size; - pcacheinfo->icacheline_size = icache_line_size; - pcacheinfo->dcacheline_size = dcache_line_size; - - return ; -} - -void invalidate_writeback_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - Writeback_Invalidate_Dcache(start); //hit writeback invalidate - start += pcacheinfo->dcacheline_size; - } -} - -void invalidate_writeback_dcache(unsigned long addr, int size) -{ - unsigned long start, end; - - start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); - end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); - - while (start dcacheline_size; - } -} - -void invalidate_icache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->icache_size); - - while (start < end) - { - pcacheop->Invalidate_Icache(start); - start += pcacheinfo->icacheline_size; - } -} - -void invalidate_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - while (start icacheline_size; - } -} - -//with cache disabled -void init_dcache(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - -} - -void rt_hw_cache_init(void) -{ - unsigned int start, end; - - /* 1. identify cpu and probe cache */ - identify_cpu(); - probe_cache(); - - start = K0BASE; - end = (start + pcacheinfo->icache_size); - - /* - * 2. clear CP0 taglo/taghi register; - */ - pcacheop->Clear_TagLo(); - - /* - * 3. invalidate instruction cache; - */ - while (start < end) - { - pcacheop->Invalidate_Icache(start); //index invalidate icache - start += pcacheinfo->icacheline_size; - } - - /* - * 4. invalidate data cache; - */ - start = K0BASE; - end = (start + pcacheinfo->dcache_size); - while(start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) - { - pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - /* enable cache */ - enable_cpu_cache(); - rt_kprintf("enable cpu cache done\n"); - - return ; -} +/* + * File : cache.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2011-08-08 lgnq modified for LS1B + */ + +#include "../common/mipsregs.h" + +#define K0BASE 0x80000000 +#define PRID_LS1B 0x4220 + +extern void Clear_TagLo (void); +extern void Invalidate_Icache_Ls1b(unsigned int); +extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int); +extern void Invalidate_Dcache_Fill_Ls1b(unsigned int); +extern void Writeback_Invalidate_Dcache(unsigned int); + +typedef struct cacheinfo_t +{ + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; +} cacheinfo_t ; + +typedef struct cacheop_t +{ + void (*Clear_TagLo) (void); + void (*Invalidate_Icache) (unsigned int); + void (*Invalidate_Dcache_Fill) (unsigned int); + void (*Invalidate_Dcache_ClearTag) (unsigned int); + void (*Init_Cache)(void); +} cacheop_t ; + +static cacheop_t cacheop, *pcacheop; +static cacheinfo_t cacheinfo, *pcacheinfo; + +int identify_cpu(void) +{ + unsigned int cpu_id; + + pcacheop = &cacheop; + pcacheinfo = &cacheinfo; + + rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); + cpu_id = read_c0_prid(); + switch (cpu_id) + { + case PRID_LS1B: + rt_kprintf("CPU:LS1B\n"); + pcacheop->Clear_TagLo = Clear_TagLo; + pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b; + pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b; + pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b; + break; + default: + rt_kprintf("Unknown CPU type, system halted!\n"); + while (1) + { + ; + } + break; + } + + return 0; +} + +void probe_cache(void) +{ + unsigned int config1 = read_c0_config1(); + unsigned int icache_size, icache_line_size, icache_sets, icache_ways; + unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways; + + if ((icache_line_size = ((config1 >> 19) & 7))) + icache_line_size = 2 << icache_line_size; + else + icache_line_size = icache_line_size; + icache_sets = 64 << ((config1 >> 22) & 7); + icache_ways = 1 + ((config1 >> 16) & 7); + icache_size = icache_sets * icache_ways * icache_line_size; + + if ((dcache_line_size = ((config1 >> 10) & 7))) + dcache_line_size = 2 << dcache_line_size; + else + dcache_line_size = dcache_line_size; + dcache_sets = 64 << ((config1 >> 13) & 7); + dcache_ways = 1 + ((config1 >> 7) & 7); + dcache_size = dcache_sets * dcache_ways * dcache_line_size; + + rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); + rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); + + pcacheinfo->icache_size = icache_size; + pcacheinfo->dcache_size = dcache_size; + pcacheinfo->icacheline_size = icache_line_size; + pcacheinfo->dcacheline_size = dcache_line_size; + + return ; +} + +void invalidate_writeback_dcache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while (start < end) + { + Writeback_Invalidate_Dcache(start); //hit writeback invalidate + start += pcacheinfo->dcacheline_size; + } +} + +void invalidate_writeback_dcache(unsigned long addr, int size) +{ + unsigned long start, end; + + start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); + end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); + + while (start dcacheline_size; + } +} + +void invalidate_icache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->icache_size); + + while (start < end) + { + pcacheop->Invalidate_Icache(start); + start += pcacheinfo->icacheline_size; + } +} + +void invalidate_dcache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + while (start icacheline_size; + } +} + +//with cache disabled +void init_dcache(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while (start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + +} + +void rt_hw_cache_init(void) +{ + unsigned int start, end; + + /* 1. identify cpu and probe cache */ + identify_cpu(); + probe_cache(); + + start = K0BASE; + end = (start + pcacheinfo->icache_size); + + /* + * 2. clear CP0 taglo/taghi register; + */ + pcacheop->Clear_TagLo(); + + /* + * 3. invalidate instruction cache; + */ + while (start < end) + { + pcacheop->Invalidate_Icache(start); //index invalidate icache + start += pcacheinfo->icacheline_size; + } + + /* + * 4. invalidate data cache; + */ + start = K0BASE; + end = (start + pcacheinfo->dcache_size); + while(start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) + { + pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + /* enable cache */ + enable_cpu_cache(); + rt_kprintf("enable cpu cache done\n"); + + return ; +} diff --git a/libcpu/mips/loongson_1b/cache.h b/libcpu/mips/loongson_1b/cache.h index b1ce6468577690f7fb4de78e5cdbc768b4763c6d..b5c2d4501e5e693d689a5a20b389ddf8b49b5edf 100644 --- a/libcpu/mips/loongson_1b/cache.h +++ b/libcpu/mips/loongson_1b/cache.h @@ -1,52 +1,52 @@ -/* - * File : cache.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2011-08-08 lgnq modified for LS1B - */ -#ifndef __CACHE_H__ -#define __CACHE_H__ - -/* - * Cache Operations - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 -/* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 -/* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b -/* 0x1c is unused */ -/* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -#endif +/* + * File : cache.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2011-08-08 lgnq modified for LS1B + */ +#ifndef __CACHE_H__ +#define __CACHE_H__ + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 +/* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 +/* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b +/* 0x1c is unused */ +/* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +#endif diff --git a/libcpu/mips/loongson_1b/context_gcc.S b/libcpu/mips/loongson_1b/context_gcc.S index ec8e0b1258ccdf39918ea6c2b9561b4a7703dfc9..ce004dc716f6daeceb88a2f53983dc0a5f02dd9d 100644 --- a/libcpu/mips/loongson_1b/context_gcc.S +++ b/libcpu/mips/loongson_1b/context_gcc.S @@ -1,149 +1,149 @@ -/* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-11 bernard port to Loongson SoC3210 - * 2011-08-08 lgnq port to Loongson LS1B - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" - - .section ".text", "ax" - .set noreorder - -/* - * rt_base_t rt_hw_interrupt_disable() - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0, CP0_STATUS - and v1, v0, 0xfffffffe - mtc0 v1, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - mtc0 a0, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl mips_irq_handle -mips_irq_handle: - SAVE_ALL - - mfc0 t0, CP0_CAUSE - and t1, t0, 0xff - bnez t1, spurious_interrupt /* check exception */ - nop - - /* let k0 keep the current context sp */ - move k0, sp - /* switch to kernel stack */ - li sp, SYSTEM_STACK - - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop - -spurious_interrupt: - RESTORE_ALL_AND_RET - - .set reorder +/* + * File : context_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-11 bernard port to Loongson SoC3210 + * 2011-08-08 lgnq port to Loongson LS1B + */ + +#include "../common/mips.inc" +#include "../common/stackframe.h" + + .section ".text", "ax" + .set noreorder + +/* + * rt_base_t rt_hw_interrupt_disable() + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mfc0 v0, CP0_STATUS + and v1, v0, 0xfffffffe + mtc0 v1, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + mtc0 a0, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + mtc0 ra, CP0_EPC + SAVE_ALL + + sw sp, 0(a0) /* store sp in preempted tasks TCB */ + lw sp, 0(a1) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + lw sp, 0(a0) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + la t0, rt_thread_switch_interrupt_flag + lw t1, 0(t0) + nop + bnez t1, _reswitch + nop + li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ + sw t1, 0(t0) + la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + sw a0, 0(t0) +_reswitch: + la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + sw a1, 0(t0) + jr ra + nop + +/* + * void rt_hw_context_switch_interrupt_do(rt_base_t flag) + */ + .globl rt_interrupt_enter + .globl rt_interrupt_leave + .globl mips_irq_handle +mips_irq_handle: + SAVE_ALL + + mfc0 t0, CP0_CAUSE + and t1, t0, 0xff + bnez t1, spurious_interrupt /* check exception */ + nop + + /* let k0 keep the current context sp */ + move k0, sp + /* switch to kernel stack */ + li sp, SYSTEM_STACK + + jal rt_interrupt_enter + nop + jal rt_interrupt_dispatch + nop + jal rt_interrupt_leave + nop + + /* switch sp back to thread's context */ + move sp, k0 + + /* + * if rt_thread_switch_interrupt_flag set, jump to + * rt_hw_context_switch_interrupt_do and don't return + */ + la k0, rt_thread_switch_interrupt_flag + lw k1, 0(k0) + beqz k1, spurious_interrupt + nop + sw zero, 0(k0) /* clear flag */ + nop + + /* + * switch to the new thread + */ + la k0, rt_interrupt_from_thread + lw k1, 0(k0) + nop + sw sp, 0(k1) /* store sp in preempted tasks's TCB */ + + la k0, rt_interrupt_to_thread + lw k1, 0(k0) + nop + lw sp, 0(k1) /* get new task's stack pointer */ + j spurious_interrupt + nop + +spurious_interrupt: + RESTORE_ALL_AND_RET + + .set reorder diff --git a/libcpu/mips/loongson_1b/cpuport.c b/libcpu/mips/loongson_1b/cpuport.c index 9917b0cce07b0bb2749f4af51d1d3498c0b4d9ba..c095c0481404f5c545055831b3fc8f3e59a923da 100644 --- a/libcpu/mips/loongson_1b/cpuport.c +++ b/libcpu/mips/loongson_1b/cpuport.c @@ -1,124 +1,124 @@ -/* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2010-09-11 Bernard add CPU reset implementation - */ - -#include -#include "ls1b.h" - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - -/** - * this function will reset CPU - * - */ -void rt_hw_cpu_reset(void) -{ - /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ - - rt_kprintf("reboot system...\n"); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -void rt_hw_cpu_shutdown(void) -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -extern rt_uint32_t cp0_get_cause(void); -extern rt_uint32_t cp0_get_status(void); -extern rt_uint32_t cp0_get_hi(void); -extern rt_uint32_t cp0_get_lo(void); - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - static rt_uint32_t g_sr = 0; - - if (g_sr == 0) - { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x8401; - } - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ - +/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2010-09-11 Bernard add CPU reset implementation + */ + +#include +#include "ls1b.h" + +/** + * @addtogroup Loongson LS1B + */ + +/*@{*/ + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset(void) +{ + /* open the watch-dog */ + WDT_EN = 0x01; /* watch dog enable */ + WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WDT_SET = 0x01; /* watch dog start */ + + rt_kprintf("reboot system...\n"); + while (1); +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + +extern rt_uint32_t cp0_get_cause(void); +extern rt_uint32_t cp0_get_status(void); +extern rt_uint32_t cp0_get_hi(void); +extern rt_uint32_t cp0_get_lo(void); + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + static rt_uint32_t g_sr = 0; + + if (g_sr == 0) + { + g_sr = cp0_get_status(); + g_sr &= 0xfffffffe; + g_sr |= 0x8401; + } + + /** Start at stack top */ + stk = (rt_uint32_t *)stack_addr; + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ + *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ + *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ + *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ + *(--stk) = (rt_uint32_t) texit; /* ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* sp */ + *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ + *(--stk) = (rt_uint32_t) parameter; /* a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ + diff --git a/libcpu/mips/loongson_1b/exception.c b/libcpu/mips/loongson_1b/exception.c index f46ddfa14a73c29588575102073ac3e34274ede7..4a3745cbc5deb3a58066fe7fa7ac86286b0678da 100644 --- a/libcpu/mips/loongson_1b/exception.c +++ b/libcpu/mips/loongson_1b/exception.c @@ -1,91 +1,91 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include -#include -#include "../common/exception.h" -#include "../common/mipsregs.h" - -/** - * @addtogroup Loongson - */ - -/*@{*/ - -/** - * exception handle table - */ -#define RT_EXCEPTION_MAX 8 -exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -void cache_error_handler(void) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -static void unhandled_exception_handle(pt_regs_t *regs) -{ - rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); -} - -void install_default_execpt_handle(void) -{ - rt_int32_t i; - - for (i=0; i> 8; - - for (index = RT_EXCEPTION_MAX; index > 0; index --) - { - if (cause & (1 << index)) - { - sys_exception_handlers[index](regs); - cause &= ~(1 << index); - } - } -} - -/*@}*/ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#include +#include +#include "../common/exception.h" +#include "../common/mipsregs.h" + +/** + * @addtogroup Loongson + */ + +/*@{*/ + +/** + * exception handle table + */ +#define RT_EXCEPTION_MAX 8 +exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; + +/** + * setup the exception handle + */ +exception_func_t rt_set_except_vector(int n, exception_func_t func) +{ + exception_func_t old_handler = sys_exception_handlers[n]; + + if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) + { + return 0; + } + + sys_exception_handlers[n] = func; + + return old_handler; +} + +void tlb_refill_handler(void) +{ + rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +void cache_error_handler(void) +{ + rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +static void unhandled_exception_handle(pt_regs_t *regs) +{ + rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); +} + +void install_default_execpt_handle(void) +{ + rt_int32_t i; + + for (i=0; i> 8; + + for (index = RT_EXCEPTION_MAX; index > 0; index --) + { + if (cause & (1 << index)) + { + sys_exception_handlers[index](regs); + cause &= ~(1 << index); + } + } +} + +/*@}*/ diff --git a/libcpu/mips/loongson_1b/interrupt.c b/libcpu/mips/loongson_1b/interrupt.c index ddba29f48952709f7043c194cec8abe0d7a82da1..63240053a872efeb200d00c0822374a0fbe3a1a1 100644 --- a/libcpu/mips/loongson_1b/interrupt.c +++ b/libcpu/mips/loongson_1b/interrupt.c @@ -1,170 +1,170 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-10-15 Bernard first version - * 2010-10-15 lgnq modified for LS1B - */ - -#include -#include "ls1b.h" - -#define MAX_INTR 32 - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static rt_isr_handler_t irq_handle_table[MAX_INTR]; -void rt_interrupt_dispatch(void *ptreg); -void rt_hw_timer_handler(); - -static struct ls1b_intc_regs volatile *ls1b_hw0_icregs - = (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE); - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - -void rt_hw_interrupt_handler(int vector) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_int32_t index; - - /* pci active low */ - ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq - /* make all interrupts level triggered */ - (ls1b_hw0_icregs+0)->int_edge = 0x0000e000; - /* mask all interrupts */ - (ls1b_hw0_icregs+0)->int_clr = 0xffffffff; - - for (index = 0; index < MAX_INTR; index ++) - { - irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - (ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f)); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - (ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f)); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) -{ - if (vector >= 0 && vector < MAX_INTR) - { - if (old_handler != RT_NULL) - *old_handler = irq_handle_table[vector]; - if (new_handler != RT_NULL) - irq_handle_table[vector] = (rt_isr_handler_t)new_handler; - } -} - -void rt_interrupt_dispatch(void *ptreg) -{ - int i; - rt_isr_handler_t irq_func; - static rt_uint32_t status = 0; - rt_uint32_t c0_status; - rt_uint32_t c0_cause; - volatile rt_uint32_t cause_im; - volatile rt_uint32_t status_im; - rt_uint32_t pending_im; - - /* check os timer */ - c0_status = read_c0_status(); - c0_cause = read_c0_cause(); - - cause_im = c0_cause & ST0_IM; - status_im = c0_status & ST0_IM; - pending_im = cause_im & status_im; - - if (pending_im & CAUSEF_IP7) - { - rt_hw_timer_handler(); - } - - if (pending_im & CAUSEF_IP2) - { - /* the hardware interrupt */ - status = ls1b_hw0_icregs->int_isr; - if (!status) - return; - - for (i = MAX_INTR; i > 0; --i) - { - if ((status & (1<int_clr |= (1 << i); - } - } - } - else if (pending_im & CAUSEF_IP3) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } - else if (pending_im & CAUSEF_IP4) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } - else if (pending_im & CAUSEF_IP5) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } - else if (pending_im & CAUSEF_IP6) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } -} - -/*@}*/ +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-10-15 Bernard first version + * 2010-10-15 lgnq modified for LS1B + */ + +#include +#include "ls1b.h" + +#define MAX_INTR 32 + +extern rt_uint32_t rt_interrupt_nest; +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +static rt_isr_handler_t irq_handle_table[MAX_INTR]; +void rt_interrupt_dispatch(void *ptreg); +void rt_hw_timer_handler(); + +static struct ls1b_intc_regs volatile *ls1b_hw0_icregs + = (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE); + +/** + * @addtogroup Loongson LS1B + */ + +/*@{*/ + +void rt_hw_interrupt_handler(int vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_int32_t index; + + /* pci active low */ + ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq + /* make all interrupts level triggered */ + (ls1b_hw0_icregs+0)->int_edge = 0x0000e000; + /* mask all interrupts */ + (ls1b_hw0_icregs+0)->int_clr = 0xffffffff; + + for (index = 0; index < MAX_INTR; index ++) + { + irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler; + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + /* mask interrupt */ + (ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f)); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + (ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f)); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + if (vector >= 0 && vector < MAX_INTR) + { + if (old_handler != RT_NULL) + *old_handler = irq_handle_table[vector]; + if (new_handler != RT_NULL) + irq_handle_table[vector] = (rt_isr_handler_t)new_handler; + } +} + +void rt_interrupt_dispatch(void *ptreg) +{ + int i; + rt_isr_handler_t irq_func; + static rt_uint32_t status = 0; + rt_uint32_t c0_status; + rt_uint32_t c0_cause; + volatile rt_uint32_t cause_im; + volatile rt_uint32_t status_im; + rt_uint32_t pending_im; + + /* check os timer */ + c0_status = read_c0_status(); + c0_cause = read_c0_cause(); + + cause_im = c0_cause & ST0_IM; + status_im = c0_status & ST0_IM; + pending_im = cause_im & status_im; + + if (pending_im & CAUSEF_IP7) + { + rt_hw_timer_handler(); + } + + if (pending_im & CAUSEF_IP2) + { + /* the hardware interrupt */ + status = ls1b_hw0_icregs->int_isr; + if (!status) + return; + + for (i = MAX_INTR; i > 0; --i) + { + if ((status & (1<int_clr |= (1 << i); + } + } + } + else if (pending_im & CAUSEF_IP3) + { + rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); + } + else if (pending_im & CAUSEF_IP4) + { + rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); + } + else if (pending_im & CAUSEF_IP5) + { + rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); + } + else if (pending_im & CAUSEF_IP6) + { + rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); + } +} + +/*@}*/ diff --git a/libcpu/mips/loongson_1b/mipscfg.c b/libcpu/mips/loongson_1b/mipscfg.c index 12907f023c27e4eaaf925f26a897e10d85ee3ac8..10dd3fee9ece100dacfca9f5d94280bf208ef4fa 100644 --- a/libcpu/mips/loongson_1b/mipscfg.c +++ b/libcpu/mips/loongson_1b/mipscfg.c @@ -1,82 +1,82 @@ -/* - * File : mipscfg.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-27 swkyer first version - */ -#include -#include "../common/mipsregs.h" -#include "../common/mipscfg.h" - -mips32_core_cfg_t g_mips_core = -{ - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ -}; - -static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) -{ - rt_uint16_t rets = 1; - - while (n--) - rets *= b; - - return rets; -} - -static rt_uint16_t m_log2(rt_uint16_t b) -{ - rt_uint16_t rets = 0; - - while (b != 1) - { - b /= 2; - rets++; - } - - return rets; -} - -/** - * read core attribute - */ -void mips32_cfg_init(void) -{ - rt_uint16_t val; - rt_uint32_t cp0_config1; - - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); - - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; - - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; - - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } -} +/* + * File : mipscfg.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#include +#include "../common/mipsregs.h" +#include "../common/mipscfg.h" + +mips32_core_cfg_t g_mips_core = +{ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** + * read core attribute + */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/loongson_1b/start_gcc.S b/libcpu/mips/loongson_1b/start_gcc.S index dc6e51849a9925dc266d95990e349e5e5a01da43..fd983356715c95f123a3b40fac7e81741432920f 100644 --- a/libcpu/mips/loongson_1b/start_gcc.S +++ b/libcpu/mips/loongson_1b/start_gcc.S @@ -1,137 +1,137 @@ -/* - * File : start_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-04 bernard porting to Jz47xx - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" - - .section ".start", "ax" - .set noreorder - - /* the program entry */ - .globl _start -_start: - .set noreorder - la ra, _start - - /* disable interrupt */ - mfc0 t0, CP0_STATUS - and t0, 0xfffffffe # By default it will be disabled. - mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. - nop - - /* disable cache */ - mfc0 t0, CP0_CONFIG - and t0, 0xfffffff8 - or t0, 0x2 # disable,!default value is not it! - mtc0 t0, CP0_CONFIG # Set CPU to disable cache. - nop - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - .set reorder - - .globl cp0_get_cause -cp0_get_cause: - mfc0 v0, CP0_CAUSE - jr ra - nop - - .globl cp0_get_status -cp0_get_status: - mfc0 v0, CP0_STATUS - jr ra - nop - - .globl cp0_get_hi -cp0_get_hi: - mfhi v0 - jr ra - nop - - .globl cp0_get_lo -cp0_get_lo: - mflo v0 - jr ra - nop - - .extern tlb_refill_handler - .extern cache_error_handler - - /* Exception Handler */ - - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - .global tlb_refill_exception - .type tlb_refill_exception,@function -tlb_refill_exception: - j tlb_refill_handler - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j cache_error_handler - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - .global general_exception - .type general_exception,@function -general_exception: - j _general_exception_handler - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - .global irq_exception - .type irq_exception,@function -irq_exception: - j _irq_handler - nop - - .section .vectors, "ax", %progbits - .extern mips_irq_handle - - /* general exception handler */ -_general_exception_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder - - /* interrupt handler */ -_irq_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder +/* + * File : start_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-04 bernard porting to Jz47xx + */ + +#include "../common/mips.inc" +#include "../common/stackframe.h" + + .section ".start", "ax" + .set noreorder + + /* the program entry */ + .globl _start +_start: + .set noreorder + la ra, _start + + /* disable interrupt */ + mfc0 t0, CP0_STATUS + and t0, 0xfffffffe # By default it will be disabled. + mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. + nop + + /* disable cache */ + mfc0 t0, CP0_CONFIG + and t0, 0xfffffff8 + or t0, 0x2 # disable,!default value is not it! + mtc0 t0, CP0_CONFIG # Set CPU to disable cache. + nop + + /* setup stack pointer */ + li sp, SYSTEM_STACK + la gp, _gp + + /* clear bss */ + la t0, __bss_start + la t1, __bss_end +_clr_bss_loop: + sw zero, 0(t0) + bne t0, t1, _clr_bss_loop + addiu t0, t0, 4 + + /* jump to RT-Thread RTOS */ + jal rtthread_startup + nop + + /* restart, never die */ + j _start + nop + .set reorder + + .globl cp0_get_cause +cp0_get_cause: + mfc0 v0, CP0_CAUSE + jr ra + nop + + .globl cp0_get_status +cp0_get_status: + mfc0 v0, CP0_STATUS + jr ra + nop + + .globl cp0_get_hi +cp0_get_hi: + mfhi v0 + jr ra + nop + + .globl cp0_get_lo +cp0_get_lo: + mflo v0 + jr ra + nop + + .extern tlb_refill_handler + .extern cache_error_handler + + /* Exception Handler */ + + /* 0x0 - TLB refill handler */ + .section .vectors.1, "ax", %progbits + .global tlb_refill_exception + .type tlb_refill_exception,@function +tlb_refill_exception: + j tlb_refill_handler + nop + + /* 0x100 - Cache error handler */ + .section .vectors.2, "ax", %progbits + j cache_error_handler + nop + + /* 0x180 - Exception/Interrupt handler */ + .section .vectors.3, "ax", %progbits + .global general_exception + .type general_exception,@function +general_exception: + j _general_exception_handler + nop + + /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ + .section .vectors.4, "ax", %progbits + .global irq_exception + .type irq_exception,@function +irq_exception: + j _irq_handler + nop + + .section .vectors, "ax", %progbits + .extern mips_irq_handle + + /* general exception handler */ +_general_exception_handler: + .set noreorder + la k0, mips_irq_handle + jr k0 + nop + .set reorder + + /* interrupt handler */ +_irq_handler: + .set noreorder + la k0, mips_irq_handle + jr k0 + nop + .set reorder diff --git a/libcpu/mips/pic32/context_gcc.S b/libcpu/mips/pic32/context_gcc.S index 924f60f910290a078eb0b9bcd93b1a304888d454..3e820fb9d89c8bb4639c8f073a10c2081352857c 100644 --- a/libcpu/mips/pic32/context_gcc.S +++ b/libcpu/mips/pic32/context_gcc.S @@ -1,121 +1,121 @@ -#include -#include "../common/mips.inc" -#include "../common/stackframe.h" - - .section ".text", "ax" - .set noat - .set noreorder - -/* - * rt_base_t rt_hw_interrupt_disable() - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0, CP0_STATUS /* v0 = status */ - addiu v1, zero, -2 /* v1 = 0-2 = 0xFFFFFFFE */ - and v1, v0, v1 /* v1 = v0 & 0xFFFFFFFE */ - mtc0 v1, CP0_STATUS /* status = v1 */ - jr ra - nop - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - mtc0 a0, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - - /* trigger the soft exception (causes context switch) */ - mfc0 t0, CP0_CAUSE /* t0 = Cause */ - ori t0, t0, (1<<8) /* t0 |= (1<<8) */ - mtc0 t0, CP0_CAUSE /* cause = t0 */ - addiu t1, zero, -257 /* t1 = ~(1<<8) */ - and t0, t0, t1 /* t0 &= t1 */ - mtc0 t0, CP0_CAUSE /* cause = t0 */ - jr ra - nop - -/* - * void __ISR(_CORE_SOFTWARE_0_VECTOR, ipl2) CoreSW0Handler(void) - */ - .section ".text", "ax" - .set noreorder - .set noat - .ent CoreSW0Handler - - .globl CoreSW0Handler -CoreSW0Handler: - SAVE_ALL - - /* mCS0ClearIntFlag(); */ - la t0, IFS0CLR /* t0 = IFS0CLR */ - addiu t1,zero,0x02 /* t1 = (1<<2) */ - sw t1, 0(t0) /* IFS0CLR = t1 */ - - la k0, rt_thread_switch_interrupt_flag - sw zero, 0(k0) /* clear flag */ - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - - RESTORE_ALL_AND_RET - - .end CoreSW0Handler +#include +#include "../common/mips.inc" +#include "../common/stackframe.h" + + .section ".text", "ax" + .set noat + .set noreorder + +/* + * rt_base_t rt_hw_interrupt_disable() + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mfc0 v0, CP0_STATUS /* v0 = status */ + addiu v1, zero, -2 /* v1 = 0-2 = 0xFFFFFFFE */ + and v1, v0, v1 /* v1 = v0 & 0xFFFFFFFE */ + mtc0 v1, CP0_STATUS /* status = v1 */ + jr ra + nop + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + mtc0 a0, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + lw sp, 0(a0) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + mtc0 ra, CP0_EPC + SAVE_ALL + + sw sp, 0(a0) /* store sp in preempted tasks TCB */ + lw sp, 0(a1) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + la t0, rt_thread_switch_interrupt_flag + lw t1, 0(t0) + nop + bnez t1, _reswitch + nop + li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ + sw t1, 0(t0) + la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + sw a0, 0(t0) +_reswitch: + la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + sw a1, 0(t0) + + /* trigger the soft exception (causes context switch) */ + mfc0 t0, CP0_CAUSE /* t0 = Cause */ + ori t0, t0, (1<<8) /* t0 |= (1<<8) */ + mtc0 t0, CP0_CAUSE /* cause = t0 */ + addiu t1, zero, -257 /* t1 = ~(1<<8) */ + and t0, t0, t1 /* t0 &= t1 */ + mtc0 t0, CP0_CAUSE /* cause = t0 */ + jr ra + nop + +/* + * void __ISR(_CORE_SOFTWARE_0_VECTOR, ipl2) CoreSW0Handler(void) + */ + .section ".text", "ax" + .set noreorder + .set noat + .ent CoreSW0Handler + + .globl CoreSW0Handler +CoreSW0Handler: + SAVE_ALL + + /* mCS0ClearIntFlag(); */ + la t0, IFS0CLR /* t0 = IFS0CLR */ + addiu t1,zero,0x02 /* t1 = (1<<2) */ + sw t1, 0(t0) /* IFS0CLR = t1 */ + + la k0, rt_thread_switch_interrupt_flag + sw zero, 0(k0) /* clear flag */ + + /* + * switch to the new thread + */ + la k0, rt_interrupt_from_thread + lw k1, 0(k0) + nop + sw sp, 0(k1) /* store sp in preempted tasks's TCB */ + + la k0, rt_interrupt_to_thread + lw k1, 0(k0) + nop + lw sp, 0(k1) /* get new task's stack pointer */ + + RESTORE_ALL_AND_RET + + .end CoreSW0Handler diff --git a/libcpu/mips/pic32/cpuport.c b/libcpu/mips/pic32/cpuport.c index 0425004de1a8b024016f33f4daa9fb644ea51342..3f08d5716756f96f36f18a0b11a79b7e45897348 100644 --- a/libcpu/mips/pic32/cpuport.c +++ b/libcpu/mips/pic32/cpuport.c @@ -1,96 +1,96 @@ -/* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 20011-05-23 aozima the first version for PIC32. - * 20011-09-05 aozima merge all of C source code into cpuport.c. - */ -#include - -/** - * @addtogroup PIC32 - */ -/*@{*/ - -/* exception and interrupt handler table */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -rt_uint32_t __attribute__((nomips16)) _get_gp(void) -{ - rt_uint32_t result; - - // get the gp reg - asm volatile("move %0, $28" : "=r"(result)); - - return result; -} - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ - *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) 0; /* lo */ - *(--stk) = (rt_uint32_t) 0; /* hi */ - *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ - *(--stk) = (rt_uint32_t) texit; /* 31 ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ - *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ - *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - - -/*@}*/ +/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 20011-05-23 aozima the first version for PIC32. + * 20011-09-05 aozima merge all of C source code into cpuport.c. + */ +#include + +/** + * @addtogroup PIC32 + */ +/*@{*/ + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +rt_uint32_t __attribute__((nomips16)) _get_gp(void) +{ + rt_uint32_t result; + + // get the gp reg + asm volatile("move %0, $28" : "=r"(result)); + + return result; +} + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + /** Start at stack top */ + stk = (rt_uint32_t *)stack_addr; + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ + *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) 0; /* lo */ + *(--stk) = (rt_uint32_t) 0; /* hi */ + *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ + *(--stk) = (rt_uint32_t) texit; /* 31 ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ + *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ + *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + + +/*@}*/ diff --git a/libcpu/mips/pic32/exceptions.c b/libcpu/mips/pic32/exceptions.c index ca3c0ae7b5cdffcc4d01d4159f002503427ed857..de5f70b7e1d16d698c432d66df68f12668915bd2 100644 --- a/libcpu/mips/pic32/exceptions.c +++ b/libcpu/mips/pic32/exceptions.c @@ -60,7 +60,7 @@ static enum { static unsigned int _epc_code; static unsigned int _excep_addr; - + #include // this function overrides the normal _weak_ generic handler void _general_exception_handler(void) @@ -68,27 +68,27 @@ void _general_exception_handler(void) asm volatile("mfc0 %0,$13" : "=r" (_excep_code)); asm volatile("mfc0 %0,$14" : "=r" (_excep_addr)); - _excep_code = (_excep_code & 0x0000007C) >> 2; - - rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code); - rt_kprintf("_excep_addr : %08X\r\n",_excep_addr); - switch(_excep_code) - { - case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break; - case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break; - case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break; - case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break; - case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break; - case EXCEP_Sys:rt_kprintf("syscall\r\n");break; - case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break; - case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break; - case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break; - case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break; - case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break; - case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break; - case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break; - case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break; - default : rt_kprintf("unkown exception\r\n");break; + _excep_code = (_excep_code & 0x0000007C) >> 2; + + rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code); + rt_kprintf("_excep_addr : %08X\r\n",_excep_addr); + switch(_excep_code) + { + case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break; + case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break; + case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break; + case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break; + case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break; + case EXCEP_Sys:rt_kprintf("syscall\r\n");break; + case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break; + case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break; + case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break; + case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break; + case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break; + case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break; + case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break; + case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break; + default : rt_kprintf("unkown exception\r\n");break; } while (1) { diff --git a/libcpu/nios/nios_ii/context_gcc.S b/libcpu/nios/nios_ii/context_gcc.S index 3ccaff3b20b5d271160f91d3da9f4f2a52ab3be9..72746f457ca72cc835624182b53e281f34308204 100644 --- a/libcpu/nios/nios_ii/context_gcc.S +++ b/libcpu/nios/nios_ii/context_gcc.S @@ -1,280 +1,280 @@ -/* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-02-14 aozima first implementation for Nios II. - * 2011-02-20 aozima fix context&switch bug. - */ - -/** - * @addtogroup NIOS_II - */ -/*@{*/ - -.text - -.set noat - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.global rt_hw_interrupt_disable -.type rt_hw_interrupt_disable, %function -rt_hw_interrupt_disable: - rdctl r2, status /* return status */ - wrctl status, zero /* disable interrupt */ - ret - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.global rt_hw_interrupt_enable -.type rt_hw_interrupt_enable, %function -rt_hw_interrupt_enable: - wrctl status, r4 /* enable interrupt by argument */ - ret - -/* void rt_hw_context_switch_interrupt_do(void) */ -.global rt_hw_context_switch_interrupt_do -.type rt_hw_context_switch_interrupt_do, %function -rt_hw_context_switch_interrupt_do: - /* save from thread */ - addi sp,sp,-72 - - /* frist save r2,so that save status */ - stw r2, 4(sp) - - /* save status */ - /* when the interrupt happen,the interrupt is enable */ - movi r2, 1 - stw r2, 68(sp) /* status */ - - stw r3, 8(sp) - stw r4, 12(sp) - - /* get & save from thread pc */ - ldw r4,%gprel(rt_current_thread_entry)(gp) - stw r4, 0(sp) /* thread pc */ - - stw r5, 16(sp) - stw r6, 20(sp) - stw r7, 24(sp) - - stw r16, 28(sp) - stw r17, 32(sp) - stw r18, 36(sp) - stw r19, 40(sp) - stw r20, 44(sp) - stw r21, 48(sp) - stw r22, 52(sp) - stw r23, 56(sp) - - stw fp, 60(sp) - stw ra, 64(sp) - - /* save from thread sp */ - /* rt_interrupt_from_thread = &from_thread->sp */ - ldw r4, %gprel(rt_interrupt_from_thread)(gp) - /* *r4(from_thread->sp) = sp */ - stw sp, (r4) - - /* clear rt_thread_switch_interrupt_flag */ - /* rt_thread_switch_interrupt_flag = 0 */ - stw zero,%gprel(rt_thread_switch_interrupt_flag)(gp) - - /* load to thread sp */ - /* r4 = rt_interrupt_to_thread(&to_thread->sp) */ - ldw r4, %gprel(rt_interrupt_to_thread)(gp) - /* sp = to_thread->sp */ - ldw sp, (r4) - - ldw r2, 68(sp) /* status */ - wrctl estatus, r2 - - ldw ea, 0(sp) /* thread pc */ - ldw r2, 4(sp) - ldw r3, 8(sp) - ldw r4, 12(sp) - ldw r5, 16(sp) - ldw r6, 20(sp) - ldw r7, 24(sp) - - ldw r16, 28(sp) - ldw r17, 32(sp) - ldw r18, 36(sp) - ldw r19, 40(sp) - ldw r20, 44(sp) - ldw r21, 48(sp) - ldw r22, 52(sp) - ldw r23, 56(sp) - - ldw fp, 60(sp) - ldw ra, 64(sp) - - addi sp, sp, 72 - - /* estatus --> status,ea --> pc */ - eret - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r4: from - * r5: to - */ -.global rt_hw_context_switch -.type rt_hw_context_switch, %function -rt_hw_context_switch: - /* save from thread */ - addi sp,sp,-72 - - /* frist save r2,so that save status */ - stw r2, 4(sp) - - /* save status */ - rdctl r2, status - stw r2, 68(sp) /* status */ - - stw ra, 0(sp) /* return from rt_hw_context_switch */ - stw r3, 8(sp) - stw r4, 12(sp) - stw r5, 16(sp) - stw r6, 20(sp) - stw r7, 24(sp) - - stw r16, 28(sp) - stw r17, 32(sp) - stw r18, 36(sp) - stw r19, 40(sp) - stw r20, 44(sp) - stw r21, 48(sp) - stw r22, 52(sp) - stw r23, 56(sp) - - stw fp, 60(sp) - stw ra, 64(sp) - - /* save form thread sp */ - /* from_thread->sp(r4) = sp */ - stw sp, (r4) - - /* update rt_interrupt_from_thread */ - /* rt_interrupt_from_thread = r4(from_thread->sp) */ - stw r4,%gprel(rt_interrupt_from_thread)(gp) - - /* update rt_interrupt_to_thread */ - /* rt_interrupt_to_thread = r5 */ - stw r5,%gprel(rt_interrupt_to_thread)(gp) - - /* get to thread sp */ - /* sp = rt_interrupt_to_thread(r5:to_thread->sp) */ - ldw sp, (r5) - - ldw r2, 68(sp) /* status */ - wrctl estatus, r2 - - ldw ea, 0(sp) /* thread pc */ - - ldw r2, 4(sp) - ldw r3, 8(sp) - ldw r4, 12(sp) - ldw r5, 16(sp) - ldw r6, 20(sp) - ldw r7, 24(sp) - - ldw r16, 28(sp) - ldw r17, 32(sp) - ldw r18, 36(sp) - ldw r19, 40(sp) - ldw r20, 44(sp) - ldw r21, 48(sp) - ldw r22, 52(sp) - ldw r23, 56(sp) - - ldw fp, 60(sp) - ldw ra, 64(sp) - - addi sp, sp, 72 - - /* estatus --> status,ea --> pc */ - eret - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - * r4: from - * r5: to - */ -.global rt_hw_context_switch_interrupt -.type rt_hw_context_switch_interrupt, %function -rt_hw_context_switch_interrupt: - /* if( rt_thread_switch_interrupt_flag != 0 ) _from_thread_not_change */ - ldw r2,%gprel(rt_thread_switch_interrupt_flag)(gp) - bne r2,zero,_from_thread_not_change - -_from_thread_change: - /* save ea -> rt_current_thread_entry */ - addi ea,ea,-4 - stw ea,%gprel(rt_current_thread_entry)(gp) - - /* set rt_thread_switch_interrupt_flag to 1 */ - movi r2, 1 - stw r2,%gprel(rt_thread_switch_interrupt_flag)(gp) - - /* update rt_interrupt_from_thread */ - stw r4,%gprel(rt_interrupt_from_thread)(gp) - -_from_thread_not_change: - /* update rt_interrupt_to_thread */ - stw r5,%gprel(rt_interrupt_to_thread)(gp) - - ret - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r4: to - */ -.global rt_hw_context_switch_to -.type rt_hw_context_switch_to, %function -rt_hw_context_switch_to: - /* save to thread */ - stw r4,%gprel(rt_interrupt_to_thread)(gp) - - /* get sp */ - ldw sp, (r4) // sp = *r4 - - ldw r2, 68(sp) /* status */ - wrctl estatus, r2 - - ldw ea, 0(sp) /* thread entry */ - - ldw r2, 4(sp) - ldw r3, 8(sp) - ldw r4, 12(sp) - ldw r5, 16(sp) - ldw r6, 20(sp) - ldw r7, 24(sp) - - ldw r16, 28(sp) - ldw r17, 32(sp) - ldw r18, 36(sp) - ldw r19, 40(sp) - ldw r20, 44(sp) - ldw r21, 48(sp) - ldw r22, 52(sp) - ldw r23, 56(sp) - - ldw fp, 60(sp) - ldw ra, 64(sp) - - addi sp, sp, 72 - - /* estatus --> status,ea --> pc */ - eret - -/*@}*/ +/* + * File : context_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-14 aozima first implementation for Nios II. + * 2011-02-20 aozima fix context&switch bug. + */ + +/** + * @addtogroup NIOS_II + */ +/*@{*/ + +.text + +.set noat + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.global rt_hw_interrupt_disable +.type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + rdctl r2, status /* return status */ + wrctl status, zero /* disable interrupt */ + ret + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.global rt_hw_interrupt_enable +.type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + wrctl status, r4 /* enable interrupt by argument */ + ret + +/* void rt_hw_context_switch_interrupt_do(void) */ +.global rt_hw_context_switch_interrupt_do +.type rt_hw_context_switch_interrupt_do, %function +rt_hw_context_switch_interrupt_do: + /* save from thread */ + addi sp,sp,-72 + + /* frist save r2,so that save status */ + stw r2, 4(sp) + + /* save status */ + /* when the interrupt happen,the interrupt is enable */ + movi r2, 1 + stw r2, 68(sp) /* status */ + + stw r3, 8(sp) + stw r4, 12(sp) + + /* get & save from thread pc */ + ldw r4,%gprel(rt_current_thread_entry)(gp) + stw r4, 0(sp) /* thread pc */ + + stw r5, 16(sp) + stw r6, 20(sp) + stw r7, 24(sp) + + stw r16, 28(sp) + stw r17, 32(sp) + stw r18, 36(sp) + stw r19, 40(sp) + stw r20, 44(sp) + stw r21, 48(sp) + stw r22, 52(sp) + stw r23, 56(sp) + + stw fp, 60(sp) + stw ra, 64(sp) + + /* save from thread sp */ + /* rt_interrupt_from_thread = &from_thread->sp */ + ldw r4, %gprel(rt_interrupt_from_thread)(gp) + /* *r4(from_thread->sp) = sp */ + stw sp, (r4) + + /* clear rt_thread_switch_interrupt_flag */ + /* rt_thread_switch_interrupt_flag = 0 */ + stw zero,%gprel(rt_thread_switch_interrupt_flag)(gp) + + /* load to thread sp */ + /* r4 = rt_interrupt_to_thread(&to_thread->sp) */ + ldw r4, %gprel(rt_interrupt_to_thread)(gp) + /* sp = to_thread->sp */ + ldw sp, (r4) + + ldw r2, 68(sp) /* status */ + wrctl estatus, r2 + + ldw ea, 0(sp) /* thread pc */ + ldw r2, 4(sp) + ldw r3, 8(sp) + ldw r4, 12(sp) + ldw r5, 16(sp) + ldw r6, 20(sp) + ldw r7, 24(sp) + + ldw r16, 28(sp) + ldw r17, 32(sp) + ldw r18, 36(sp) + ldw r19, 40(sp) + ldw r20, 44(sp) + ldw r21, 48(sp) + ldw r22, 52(sp) + ldw r23, 56(sp) + + ldw fp, 60(sp) + ldw ra, 64(sp) + + addi sp, sp, 72 + + /* estatus --> status,ea --> pc */ + eret + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r4: from + * r5: to + */ +.global rt_hw_context_switch +.type rt_hw_context_switch, %function +rt_hw_context_switch: + /* save from thread */ + addi sp,sp,-72 + + /* frist save r2,so that save status */ + stw r2, 4(sp) + + /* save status */ + rdctl r2, status + stw r2, 68(sp) /* status */ + + stw ra, 0(sp) /* return from rt_hw_context_switch */ + stw r3, 8(sp) + stw r4, 12(sp) + stw r5, 16(sp) + stw r6, 20(sp) + stw r7, 24(sp) + + stw r16, 28(sp) + stw r17, 32(sp) + stw r18, 36(sp) + stw r19, 40(sp) + stw r20, 44(sp) + stw r21, 48(sp) + stw r22, 52(sp) + stw r23, 56(sp) + + stw fp, 60(sp) + stw ra, 64(sp) + + /* save form thread sp */ + /* from_thread->sp(r4) = sp */ + stw sp, (r4) + + /* update rt_interrupt_from_thread */ + /* rt_interrupt_from_thread = r4(from_thread->sp) */ + stw r4,%gprel(rt_interrupt_from_thread)(gp) + + /* update rt_interrupt_to_thread */ + /* rt_interrupt_to_thread = r5 */ + stw r5,%gprel(rt_interrupt_to_thread)(gp) + + /* get to thread sp */ + /* sp = rt_interrupt_to_thread(r5:to_thread->sp) */ + ldw sp, (r5) + + ldw r2, 68(sp) /* status */ + wrctl estatus, r2 + + ldw ea, 0(sp) /* thread pc */ + + ldw r2, 4(sp) + ldw r3, 8(sp) + ldw r4, 12(sp) + ldw r5, 16(sp) + ldw r6, 20(sp) + ldw r7, 24(sp) + + ldw r16, 28(sp) + ldw r17, 32(sp) + ldw r18, 36(sp) + ldw r19, 40(sp) + ldw r20, 44(sp) + ldw r21, 48(sp) + ldw r22, 52(sp) + ldw r23, 56(sp) + + ldw fp, 60(sp) + ldw ra, 64(sp) + + addi sp, sp, 72 + + /* estatus --> status,ea --> pc */ + eret + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + * r4: from + * r5: to + */ +.global rt_hw_context_switch_interrupt +.type rt_hw_context_switch_interrupt, %function +rt_hw_context_switch_interrupt: + /* if( rt_thread_switch_interrupt_flag != 0 ) _from_thread_not_change */ + ldw r2,%gprel(rt_thread_switch_interrupt_flag)(gp) + bne r2,zero,_from_thread_not_change + +_from_thread_change: + /* save ea -> rt_current_thread_entry */ + addi ea,ea,-4 + stw ea,%gprel(rt_current_thread_entry)(gp) + + /* set rt_thread_switch_interrupt_flag to 1 */ + movi r2, 1 + stw r2,%gprel(rt_thread_switch_interrupt_flag)(gp) + + /* update rt_interrupt_from_thread */ + stw r4,%gprel(rt_interrupt_from_thread)(gp) + +_from_thread_not_change: + /* update rt_interrupt_to_thread */ + stw r5,%gprel(rt_interrupt_to_thread)(gp) + + ret + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r4: to + */ +.global rt_hw_context_switch_to +.type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + /* save to thread */ + stw r4,%gprel(rt_interrupt_to_thread)(gp) + + /* get sp */ + ldw sp, (r4) // sp = *r4 + + ldw r2, 68(sp) /* status */ + wrctl estatus, r2 + + ldw ea, 0(sp) /* thread entry */ + + ldw r2, 4(sp) + ldw r3, 8(sp) + ldw r4, 12(sp) + ldw r5, 16(sp) + ldw r6, 20(sp) + ldw r7, 24(sp) + + ldw r16, 28(sp) + ldw r17, 32(sp) + ldw r18, 36(sp) + ldw r19, 40(sp) + ldw r20, 44(sp) + ldw r21, 48(sp) + ldw r22, 52(sp) + ldw r23, 56(sp) + + ldw fp, 60(sp) + ldw ra, 64(sp) + + addi sp, sp, 72 + + /* estatus --> status,ea --> pc */ + eret + +/*@}*/ diff --git a/libcpu/nios/nios_ii/interrupt.c b/libcpu/nios/nios_ii/interrupt.c index 15c574901bec163f9686e71dbb101e9a511b2019..112eaa9223b76dc57d4a4a01c6f512efafcf4ea2 100644 --- a/libcpu/nios/nios_ii/interrupt.c +++ b/libcpu/nios/nios_ii/interrupt.c @@ -1,22 +1,22 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first version - */ - -#include - -/* exception and interrupt handler table */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; -rt_uint32_t rt_current_thread_entry; - -/*@}*/ +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first version + */ + +#include + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; +rt_uint32_t rt_current_thread_entry; + +/*@}*/ diff --git a/libcpu/nios/nios_ii/stack.c b/libcpu/nios/nios_ii/stack.c index 01fbb2c4688050438c0235e8416c2a83be45c5a0..125bf2c578e6d3c71c4b93c81214e9c670710a8a 100644 --- a/libcpu/nios/nios_ii/stack.c +++ b/libcpu/nios/nios_ii/stack.c @@ -1,22 +1,22 @@ -/* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-02-14 aozima first implementation for Nios II. - */ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-14 aozima first implementation for Nios II. + */ #include -/** - * @addtogroup NIOS_II - */ +/** + * @addtogroup NIOS_II + */ /*@{*/ /** @@ -34,33 +34,33 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, { unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(stk) = 0x01; /* status */ - *(--stk) = (unsigned long)texit; /* ra */ - *(--stk) = 0xdeadbeef; /* fp */ - *(--stk) = 0xdeadbeef; /* r23 */ - *(--stk) = 0xdeadbeef; /* r22 */ - *(--stk) = 0xdeadbeef; /* r21 */ - *(--stk) = 0xdeadbeef; /* r20 */ - *(--stk) = 0xdeadbeef; /* r19 */ - *(--stk) = 0xdeadbeef; /* r18 */ - *(--stk) = 0xdeadbeef; /* r17 */ - *(--stk) = 0xdeadbeef; /* r16 */ -// *(--stk) = 0xdeadbeef; /* r15 */ -// *(--stk) = 0xdeadbeef; /* r14 */ -// *(--stk) = 0xdeadbeef; /* r13 */ -// *(--stk) = 0xdeadbeef; /* r12 */ -// *(--stk) = 0xdeadbeef; /* r11 */ -// *(--stk) = 0xdeadbeef; /* r10 */ -// *(--stk) = 0xdeadbeef; /* r9 */ -// *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = (unsigned long)parameter; /* r4 argument */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = (unsigned long)tentry; /* pc */ + stk = (unsigned long *)stack_addr; + *(stk) = 0x01; /* status */ + *(--stk) = (unsigned long)texit; /* ra */ + *(--stk) = 0xdeadbeef; /* fp */ + *(--stk) = 0xdeadbeef; /* r23 */ + *(--stk) = 0xdeadbeef; /* r22 */ + *(--stk) = 0xdeadbeef; /* r21 */ + *(--stk) = 0xdeadbeef; /* r20 */ + *(--stk) = 0xdeadbeef; /* r19 */ + *(--stk) = 0xdeadbeef; /* r18 */ + *(--stk) = 0xdeadbeef; /* r17 */ + *(--stk) = 0xdeadbeef; /* r16 */ +// *(--stk) = 0xdeadbeef; /* r15 */ +// *(--stk) = 0xdeadbeef; /* r14 */ +// *(--stk) = 0xdeadbeef; /* r13 */ +// *(--stk) = 0xdeadbeef; /* r12 */ +// *(--stk) = 0xdeadbeef; /* r11 */ +// *(--stk) = 0xdeadbeef; /* r10 */ +// *(--stk) = 0xdeadbeef; /* r9 */ +// *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = (unsigned long)parameter; /* r4 argument */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = (unsigned long)tentry; /* pc */ // *(stk) = (unsigned long)tentry; /* thread entry (ra) */ // *(--stk) = (unsigned long)parameter; /* thread argument, r4 */ diff --git a/libcpu/nios/nios_ii/vector.S b/libcpu/nios/nios_ii/vector.S index f8d43425b87ab9ea6b161ec10c7571c8987b0ca9..c3ed721bef6b329a81137e295bb646c07dcb606c 100644 --- a/libcpu/nios/nios_ii/vector.S +++ b/libcpu/nios/nios_ii/vector.S @@ -1,51 +1,51 @@ -.set noat - -.globl .Lexception_exit - -.section .exceptions.exit.label -.Lexception_exit: -.section .exceptions.exit, "xa" - ldw r5, 68(sp) - - /* get exception back */ - ldw ea, 72(sp) - - /* if(rt_thread_switch_interrupt_flag == 0) goto no_need_context */ - ldw r4,%gprel(rt_thread_switch_interrupt_flag)(gp) - beq r4,zero,no_need_context - -need_context: - movia ea, rt_hw_context_switch_interrupt_do - /* disable interrupt */ - mov r5, zero - -no_need_context: - ldw ra, 0(sp) - - wrctl estatus, r5 - - /* - * Leave a gap in the stack frame at 4(sp) for the muldiv handler to - * store zero into. - */ - - ldw r1, 8(sp) - ldw r2, 12(sp) - ldw r3, 16(sp) - ldw r4, 20(sp) - ldw r5, 24(sp) - ldw r6, 28(sp) - ldw r7, 32(sp) - ldw r8, 36(sp) - ldw r9, 40(sp) - ldw r10, 44(sp) - ldw r11, 48(sp) - ldw r12, 52(sp) - ldw r13, 56(sp) - ldw r14, 60(sp) - ldw r15, 64(sp) - - addi sp, sp, 76 - - eret - +.set noat + +.globl .Lexception_exit + +.section .exceptions.exit.label +.Lexception_exit: +.section .exceptions.exit, "xa" + ldw r5, 68(sp) + + /* get exception back */ + ldw ea, 72(sp) + + /* if(rt_thread_switch_interrupt_flag == 0) goto no_need_context */ + ldw r4,%gprel(rt_thread_switch_interrupt_flag)(gp) + beq r4,zero,no_need_context + +need_context: + movia ea, rt_hw_context_switch_interrupt_do + /* disable interrupt */ + mov r5, zero + +no_need_context: + ldw ra, 0(sp) + + wrctl estatus, r5 + + /* + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + + ldw r1, 8(sp) + ldw r2, 12(sp) + ldw r3, 16(sp) + ldw r4, 20(sp) + ldw r5, 24(sp) + ldw r6, 28(sp) + ldw r7, 32(sp) + ldw r8, 36(sp) + ldw r9, 40(sp) + ldw r10, 44(sp) + ldw r11, 48(sp) + ldw r12, 52(sp) + ldw r13, 56(sp) + ldw r14, 60(sp) + ldw r15, 64(sp) + + addi sp, sp, 76 + + eret + diff --git a/libcpu/ppc/common/ptrace.h b/libcpu/ppc/common/ptrace.h index 860d1a7c601dca34951f369b2c3c2686b8f2a3f1..d60e7fdcefe178e2d6771b9ac178960f49251f1d 100644 --- a/libcpu/ppc/common/ptrace.h +++ b/libcpu/ppc/common/ptrace.h @@ -1,100 +1,100 @@ -#ifndef _PPC_PTRACE_H -#define _PPC_PTRACE_H - -/* - * This struct defines the way the registers are stored on the - * kernel stack during a system call or other kernel entry. - * - * this should only contain volatile regs - * since we can keep non-volatile in the thread_struct - * should set this up when only volatiles are saved - * by intr code. - * - * Since this is going on the stack, *CARE MUST BE TAKEN* to insure - * that the overall structure is a multiple of 16 bytes in length. - * - * Note that the offsets of the fields in this struct correspond with - * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. - */ - -#ifndef __ASSEMBLY__ -#define PPC_REG unsigned long - -struct pt_regs { - PPC_REG gpr[32]; - PPC_REG nip; - PPC_REG msr; - PPC_REG orig_gpr3; /* Used for restarting system calls */ - PPC_REG ctr; - PPC_REG link; - PPC_REG xer; - PPC_REG ccr; - PPC_REG mq; /* 601 only (not used at present) */ - /* Used on APUS to hold IPL value. */ - PPC_REG trap; /* Reason for being here */ - PPC_REG dar; /* Fault registers */ - PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ -}__attribute__((packed)) CELL_STACK_FRAME_t; -#endif - -#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ - -/* Size of stack frame allocated when calling signal handler. */ -#define __SIGNAL_FRAMESIZE 64 - -#define instruction_pointer(regs) ((regs)->nip) -#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) - -/* - * Offsets used by 'ptrace' system call interface. - * These can't be changed without breaking binary compatibility - * with MkLinux, etc. - */ -#define PT_R0 0 -#define PT_R1 1 -#define PT_R2 2 -#define PT_R3 3 -#define PT_R4 4 -#define PT_R5 5 -#define PT_R6 6 -#define PT_R7 7 -#define PT_R8 8 -#define PT_R9 9 -#define PT_R10 10 -#define PT_R11 11 -#define PT_R12 12 -#define PT_R13 13 -#define PT_R14 14 -#define PT_R15 15 -#define PT_R16 16 -#define PT_R17 17 -#define PT_R18 18 -#define PT_R19 19 -#define PT_R20 20 -#define PT_R21 21 -#define PT_R22 22 -#define PT_R23 23 -#define PT_R24 24 -#define PT_R25 25 -#define PT_R26 26 -#define PT_R27 27 -#define PT_R28 28 -#define PT_R29 29 -#define PT_R30 30 -#define PT_R31 31 - -#define PT_NIP 32 -#define PT_MSR 33 -#define PT_ORIG_R3 34 -#define PT_CTR 35 -#define PT_LNK 36 -#define PT_XER 37 -#define PT_CCR 38 -#define PT_MQ 39 - -#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ -#define PT_FPR31 (PT_FPR0 + 2*31) -#define PT_FPSCR (PT_FPR0 + 2*32 + 1) - -#endif +#ifndef _PPC_PTRACE_H +#define _PPC_PTRACE_H + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + * + * this should only contain volatile regs + * since we can keep non-volatile in the thread_struct + * should set this up when only volatiles are saved + * by intr code. + * + * Since this is going on the stack, *CARE MUST BE TAKEN* to insure + * that the overall structure is a multiple of 16 bytes in length. + * + * Note that the offsets of the fields in this struct correspond with + * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. + */ + +#ifndef __ASSEMBLY__ +#define PPC_REG unsigned long + +struct pt_regs { + PPC_REG gpr[32]; + PPC_REG nip; + PPC_REG msr; + PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG ctr; + PPC_REG link; + PPC_REG xer; + PPC_REG ccr; + PPC_REG mq; /* 601 only (not used at present) */ + /* Used on APUS to hold IPL value. */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ + PPC_REG dsisr; + PPC_REG result; /* Result of a system call */ +}__attribute__((packed)) CELL_STACK_FRAME_t; +#endif + +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ + +/* Size of stack frame allocated when calling signal handler. */ +#define __SIGNAL_FRAMESIZE 64 + +#define instruction_pointer(regs) ((regs)->nip) +#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) + +/* + * Offsets used by 'ptrace' system call interface. + * These can't be changed without breaking binary compatibility + * with MkLinux, etc. + */ +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 + +#define PT_NIP 32 +#define PT_MSR 33 +#define PT_ORIG_R3 34 +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 + +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR31 (PT_FPR0 + 2*31) +#define PT_FPSCR (PT_FPR0 + 2*32 + 1) + +#endif diff --git a/libcpu/ppc/common/stack.c b/libcpu/ppc/common/stack.c index 05ae5abb803dd6e2fb7c5e658560236998b125c3..570e9ba046b9c33b5afab262234dfc7e6232d105 100644 --- a/libcpu/ppc/common/stack.c +++ b/libcpu/ppc/common/stack.c @@ -1,88 +1,88 @@ -/* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-02-14 Fred first implementation for - */ - -#include - -/** - * @addtogroup PowerPC - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - unsigned long *stk; - rt_uint32_t msr; - - __asm__ __volatile__("mfmsr %0\n" : "=r" (msr)); - msr |= 0x00028000; - - stk = (unsigned long *)stack_addr; - --stk; - *(--stk) = msr; /* srr0: machine status register */ - *(--stk) = (rt_uint32_t)tentry; /* srr1: entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr: link register */ - *(--stk) = 0x0F0F0F0F; /* ctr: counter register */ - *(--stk) = 0x0F0F0F0F; /* xer: fixed-point exception register */ - *(--stk) = 0x0F0F0F0F; /* cr : condition register */ - *(--stk) = 0x00; /* usprg0 */ - - *(--stk) = 0x31; /* r31 */ - *(--stk) = 0x30; /* r30 */ - *(--stk) = 0x29; /* r29 */ - *(--stk) = 0x28; /* r28 */ - *(--stk) = 0x27; /* r27 */ - *(--stk) = 0x26; /* r26 */ - *(--stk) = 0x25; /* r25 */ - *(--stk) = 0x24; /* r24 */ - *(--stk) = 0x23; /* r23 */ - *(--stk) = 0x22; /* r22 */ - *(--stk) = 0x21; /* r21 */ - *(--stk) = 0x20; /* r20 */ - *(--stk) = 0x19; /* r19 */ - *(--stk) = 0x18; /* r18 */ - *(--stk) = 0x17; /* r17 */ - *(--stk) = 0x16; /* r16 */ - *(--stk) = 0x15; /* r15 */ - *(--stk) = 0x14; /* r14 */ - *(--stk) = 0x13; /* r13: thread id */ - *(--stk) = 0x12; /* r12 */ - *(--stk) = 0x11; /* r11 */ - *(--stk) = 0x10; /* r10 */ - *(--stk) = 0x09; /* r09 */ - *(--stk) = 0x08; /* r08 */ - *(--stk) = 0x07; /* r07 */ - *(--stk) = 0x06; /* r06 */ - *(--stk) = 0x05; /* r05 */ - *(--stk) = 0x04; /* r04 */ - *(--stk) = (rt_uint32_t)parameter; /* r03: parameter and return */ - *(--stk) = 0x02; /* r02: toc */ - /* r01: sp */ - *(--stk) = 0x0; /* r00 */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-14 Fred first implementation for + */ + +#include + +/** + * @addtogroup PowerPC + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + rt_uint32_t msr; + + __asm__ __volatile__("mfmsr %0\n" : "=r" (msr)); + msr |= 0x00028000; + + stk = (unsigned long *)stack_addr; + --stk; + *(--stk) = msr; /* srr0: machine status register */ + *(--stk) = (rt_uint32_t)tentry; /* srr1: entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr: link register */ + *(--stk) = 0x0F0F0F0F; /* ctr: counter register */ + *(--stk) = 0x0F0F0F0F; /* xer: fixed-point exception register */ + *(--stk) = 0x0F0F0F0F; /* cr : condition register */ + *(--stk) = 0x00; /* usprg0 */ + + *(--stk) = 0x31; /* r31 */ + *(--stk) = 0x30; /* r30 */ + *(--stk) = 0x29; /* r29 */ + *(--stk) = 0x28; /* r28 */ + *(--stk) = 0x27; /* r27 */ + *(--stk) = 0x26; /* r26 */ + *(--stk) = 0x25; /* r25 */ + *(--stk) = 0x24; /* r24 */ + *(--stk) = 0x23; /* r23 */ + *(--stk) = 0x22; /* r22 */ + *(--stk) = 0x21; /* r21 */ + *(--stk) = 0x20; /* r20 */ + *(--stk) = 0x19; /* r19 */ + *(--stk) = 0x18; /* r18 */ + *(--stk) = 0x17; /* r17 */ + *(--stk) = 0x16; /* r16 */ + *(--stk) = 0x15; /* r15 */ + *(--stk) = 0x14; /* r14 */ + *(--stk) = 0x13; /* r13: thread id */ + *(--stk) = 0x12; /* r12 */ + *(--stk) = 0x11; /* r11 */ + *(--stk) = 0x10; /* r10 */ + *(--stk) = 0x09; /* r09 */ + *(--stk) = 0x08; /* r08 */ + *(--stk) = 0x07; /* r07 */ + *(--stk) = 0x06; /* r06 */ + *(--stk) = 0x05; /* r05 */ + *(--stk) = 0x04; /* r04 */ + *(--stk) = (rt_uint32_t)parameter; /* r03: parameter and return */ + *(--stk) = 0x02; /* r02: toc */ + /* r01: sp */ + *(--stk) = 0x0; /* r00 */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/ppc/ppc405/cache.h b/libcpu/ppc/ppc405/cache.h index 81575913737deaf22f7b30ae37231f19ad67e898..930124547b05d65b47586677a37524bd44f54409 100644 --- a/libcpu/ppc/ppc405/cache.h +++ b/libcpu/ppc/ppc405/cache.h @@ -1,23 +1,23 @@ -#ifndef __CACHE_H__ -#define __CACHE_H__ - -#include - -#if !defined(__ASSEMBLY__) -void flush_dcache_range(unsigned long start, unsigned long stop); -void clean_dcache_range(unsigned long start, unsigned long stop); -void invalidate_dcache_range(unsigned long start, unsigned long stop); -void flush_dcache(void); -void invalidate_dcache(void); -void invalidate_icache(void); - -void icache_enable(void); -void icache_disable(void); -unsigned long icache_status(void); - -void dcache_enable(void); -void dcache_disable(void); -unsigned long dcache_status(void); -#endif - -#endif +#ifndef __CACHE_H__ +#define __CACHE_H__ + +#include + +#if !defined(__ASSEMBLY__) +void flush_dcache_range(unsigned long start, unsigned long stop); +void clean_dcache_range(unsigned long start, unsigned long stop); +void invalidate_dcache_range(unsigned long start, unsigned long stop); +void flush_dcache(void); +void invalidate_dcache(void); +void invalidate_icache(void); + +void icache_enable(void); +void icache_disable(void); +unsigned long icache_status(void); + +void dcache_enable(void); +void dcache_disable(void); +unsigned long dcache_status(void); +#endif + +#endif diff --git a/libcpu/ppc/ppc405/context.h b/libcpu/ppc/ppc405/context.h index 54dadbc215ae7bfff094e6bed71db65c51f0e153..8b4d55d698f9db24e5542a47588eae19a1e7931f 100644 --- a/libcpu/ppc/ppc405/context.h +++ b/libcpu/ppc/ppc405/context.h @@ -1,48 +1,48 @@ -#ifndef __CONTEXT_H__ -#define __CONTEXT_H__ - -#define MSR_ME (1<<12) /* Machine Check Enable */ -#define MSR_EE (1<<15) /* External Interrupt Enable */ -#define MSR_CE (1<<17) /* Critical Interrupt Enable */ - -#define GPR0 0 -#define GPR2 4 -#define GPR3 8 -#define GPR4 12 -#define GPR5 16 -#define GPR6 20 -#define GPR7 24 -#define GPR8 28 -#define GPR9 32 -#define GPR10 36 -#define GPR11 40 -#define GPR12 44 -#define GPR13 48 -#define GPR14 52 -#define GPR15 56 -#define GPR16 60 -#define GPR17 64 -#define GPR18 68 -#define GPR19 72 -#define GPR20 76 -#define GPR21 80 -#define GPR22 84 -#define GPR23 88 -#define GPR24 92 -#define GPR25 96 -#define GPR26 100 -#define GPR27 104 -#define GPR28 108 -#define GPR29 112 -#define GPR30 116 -#define GPR31 120 -#define USPRG0 (GPR31 + 4) -#define CR (USPRG0 + 4) -#define XER (CR + 4) -#define CTR (XER + 4) -#define LR (CTR + 4) -#define SRR0 (LR + 4) -#define SRR1 (SRR0 + 4) -#define STACK_FRAME_SIZE (SRR1 + 4) - -#endif +#ifndef __CONTEXT_H__ +#define __CONTEXT_H__ + +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ + +#define GPR0 0 +#define GPR2 4 +#define GPR3 8 +#define GPR4 12 +#define GPR5 16 +#define GPR6 20 +#define GPR7 24 +#define GPR8 28 +#define GPR9 32 +#define GPR10 36 +#define GPR11 40 +#define GPR12 44 +#define GPR13 48 +#define GPR14 52 +#define GPR15 56 +#define GPR16 60 +#define GPR17 64 +#define GPR18 68 +#define GPR19 72 +#define GPR20 76 +#define GPR21 80 +#define GPR22 84 +#define GPR23 88 +#define GPR24 92 +#define GPR25 96 +#define GPR26 100 +#define GPR27 104 +#define GPR28 108 +#define GPR29 112 +#define GPR30 116 +#define GPR31 120 +#define USPRG0 (GPR31 + 4) +#define CR (USPRG0 + 4) +#define XER (CR + 4) +#define CTR (XER + 4) +#define LR (CTR + 4) +#define SRR0 (LR + 4) +#define SRR1 (SRR0 + 4) +#define STACK_FRAME_SIZE (SRR1 + 4) + +#endif diff --git a/libcpu/ppc/ppc405/context_gcc.S b/libcpu/ppc/ppc405/context_gcc.S index e43f96d8019e2e526ffcf2588963ed4dde08e23a..f6a53dce3d6bd2b71c46d86e99f2e2ff6f6c4c5f 100644 --- a/libcpu/ppc/ppc405/context_gcc.S +++ b/libcpu/ppc/ppc405/context_gcc.S @@ -1,210 +1,210 @@ -#include "context.h" -#define SPRG0 0x110 /* Special Purpose Register General 0 */ -#define SPRG1 0x111 /* Special Purpose Register General 1 */ - - .globl rt_hw_interrupt_disable - .globl rt_hw_interrupt_enable - .globl rt_hw_context_switch - .globl rt_hw_context_switch_to - .globl rt_hw_context_switch_interrupt - .globl rt_hw_systemcall_entry - -/* - * rt_base_t rt_hw_interrupt_disable(); - * return the interrupt status and disable interrupt - */ -#if 0 -rt_hw_interrupt_disable: - mfmsr r3 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r4,r4,r3 - SYNC /* Some chip revs need this... */ - mtmsr r4 - SYNC - blr -#else -rt_hw_interrupt_disable: - addis r4, r0, 0xFFFD - ori r4, r4, 0x7FFF - mfmsr r3 - and r4, r4, 3 /* Clear bits 14 and 16, corresponding to... */ - mtmsr r4 /* ...critical and non-critical interrupts */ - blr -#endif - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - * restore interrupt - */ -rt_hw_interrupt_enable: - mtmsr r3 - SYNC - blr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r3 --> from - * r4 --> to - * - * r1: stack pointer - */ -rt_hw_systemcall_entry: - mtspr SPRG0,r3 /* save r3 to SPRG0 */ - mtspr SPRG1,r4 /* save r4 to SPRG1 */ - - lis r3,rt_thread_switch_interrput_flag@h - ori r3,r3,rt_thread_switch_interrput_flag@l - lwz r4,0(r3) - cmpi cr0,0,r4,0x0 /* whether is 0 */ - beq _no_switch /* no switch, exit */ - li r4,0x0 /* set rt_thread_switch_interrput_flag to 0 */ - stw r4,0(r3) - - /* load from thread to r3 */ - lis r3,rt_interrupt_from_thread@h /* set rt_interrupt_from_thread */ - ori r3,r3,rt_interrupt_from_thread@l - lwz r3,0(r3) - - cmpi cr0,0,r3,0x0 /* whether is 0 */ - beq _restore /* it's first switch, goto _restore */ - - /* save r1:sp to thread[from] stack pointer */ - subi r1, r1, STACK_FRAME_SIZE - stw r1, 0(r3) - - /* restore r3, r4 from SPRG */ - mfspr r3,SPRG0 - mfspr r4,SPRG0 - - /* save registers */ - stw r0,GPR0(r1) /* save general purpose registers 0 */ - stmw r2,GPR2(r1) /* save general purpose registers 2-31 */ - - mfusprg0 r0 /* save usprg0 */ - stw r0,USPRG0(r1) - mfcr r0, /* save cr */ - stw r0,CR(r1) - mfxer r0 /* save xer */ - stw r0,XER(r1) - mfctr r0 /* save ctr */ - stw r0,CTR(r1) - mflr r0 /* save lr */ - stw r0, LR(r1) - - mfsrr0 r0 /* save SRR0 and SRR1 */ - stw r0,SRR0(r1) - mfsrr1 r0 - stw r0,SRR1(r1) - -_restore: - /* get thread[to] stack pointer */ - lis r4,rt_interrupt_to_thread@h - ori r4,r4,rt_interrupt_to_thread@l - lwz r1,0(r4) - lwz r1,0(r1) - - lwz r0,SRR1(r1) /* restore SRR1 and SRR0 */ - mtsrr1 r0 - lwz r0,SRR0(r1) - mtsrr0 r0 - - lwz r0,LR(r1) /* restore lr */ - mtlr r0 - lwz r0,CTR(r1) /* restore ctr */ - mtctr r0 - lwz r0,XER(r1) /* restore xer */ - mtxer r0 - lwz r0,CR(r1) /* restore cr */ - mtcr r0 - lwz r0,USPRG0(r1) /* restore usprg0 */ - // mtusprg0 r0 - - lmw r2, GPR2(r1) /* restore general register */ - lwz r0,GPR0(r1) - addi r1, r1, STACK_FRAME_SIZE - /* RFI will restore status register and thus the correct priority*/ - rfi - -_no_switch: - /* restore r3, r4 from SPRG */ - mfspr r3,SPRG0 - mfspr r4,SPRG0 - rfi - - /* void rt_hw_context_switch_to(to); */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - /* set rt_thread_switch_interrput_flag = 1 */ - lis r5,rt_thread_switch_interrput_flag@h - ori r5,r5,rt_thread_switch_interrput_flag@l - li r6, 0x01 - stw r6,0(r5) - - /* set rt_interrupt_from_thread = 0 */ - lis r5,rt_interrupt_from_thread@h - ori r5,r5,rt_interrupt_from_thread@l - li r6, 0x00 - stw r6,0(r5) - - /* set rt_interrupt_from_thread = to */ - lis r5,rt_interrupt_to_thread@h - ori r5,r5,rt_interrupt_to_thread@l - stw r3,0(r5) - - /* trigger a system call */ - sc - - blr - - /* void rt_hw_context_switch(from, to); */ - .globl rt_hw_context_switch -rt_hw_context_switch: - /* compare rt_thread_switch_interrupt_flag and set it */ - lis r5,rt_thread_switch_interrput_flag@h - ori r5,r5,rt_thread_switch_interrput_flag@l - lwz r6,0(r5) - cmpi cr0,0,r6,0x1 /* whether is 1 */ - beq _reswitch /* set already, goto _reswitch */ - li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/ - stw r6,0(r5) - - /* set rt_interrupt_from_thread to 'from' */ - lis r5,rt_interrupt_from_thread@h - ori r5,r5,rt_interrupt_from_thread@l - stw r3,0(r5) - -_reswitch: - /* set rt_interrupt_to_thread to 'to' */ - lis r6,rt_interrupt_to_thread@h - ori r6,r6,rt_interrupt_to_thread@l - stw r4,0(r6) - - /* trigger a system call */ - sc - - blr - - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - /* compare rt_thread_switch_interrupt_flag and set it */ - lis r5,rt_thread_switch_interrput_flag@h - ori r5,r5,rt_thread_switch_interrput_flag@l - lwz r6,0(r5) - cmpi cr0,0,r6,0x1 /* whether is 1 */ - beq _int_reswitch /* set already, goto _reswitch */ - li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/ - stw r6,0(r5) - - /* set rt_interrupt_from_thread to 'from' */ - lis r5,rt_interrupt_from_thread@h - ori r5,r5,rt_interrupt_from_thread@l - stw r3,0(r5) - -_int_reswitch: - /* set rt_interrupt_to_thread to 'to' */ - lis r6,rt_interrupt_to_thread@h - ori r6,r6,rt_interrupt_to_thread@l - stw r4,0(r6) - - blr +#include "context.h" +#define SPRG0 0x110 /* Special Purpose Register General 0 */ +#define SPRG1 0x111 /* Special Purpose Register General 1 */ + + .globl rt_hw_interrupt_disable + .globl rt_hw_interrupt_enable + .globl rt_hw_context_switch + .globl rt_hw_context_switch_to + .globl rt_hw_context_switch_interrupt + .globl rt_hw_systemcall_entry + +/* + * rt_base_t rt_hw_interrupt_disable(); + * return the interrupt status and disable interrupt + */ +#if 0 +rt_hw_interrupt_disable: + mfmsr r3 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r4,r4,r3 + SYNC /* Some chip revs need this... */ + mtmsr r4 + SYNC + blr +#else +rt_hw_interrupt_disable: + addis r4, r0, 0xFFFD + ori r4, r4, 0x7FFF + mfmsr r3 + and r4, r4, 3 /* Clear bits 14 and 16, corresponding to... */ + mtmsr r4 /* ...critical and non-critical interrupts */ + blr +#endif + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + * restore interrupt + */ +rt_hw_interrupt_enable: + mtmsr r3 + SYNC + blr + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r3 --> from + * r4 --> to + * + * r1: stack pointer + */ +rt_hw_systemcall_entry: + mtspr SPRG0,r3 /* save r3 to SPRG0 */ + mtspr SPRG1,r4 /* save r4 to SPRG1 */ + + lis r3,rt_thread_switch_interrput_flag@h + ori r3,r3,rt_thread_switch_interrput_flag@l + lwz r4,0(r3) + cmpi cr0,0,r4,0x0 /* whether is 0 */ + beq _no_switch /* no switch, exit */ + li r4,0x0 /* set rt_thread_switch_interrput_flag to 0 */ + stw r4,0(r3) + + /* load from thread to r3 */ + lis r3,rt_interrupt_from_thread@h /* set rt_interrupt_from_thread */ + ori r3,r3,rt_interrupt_from_thread@l + lwz r3,0(r3) + + cmpi cr0,0,r3,0x0 /* whether is 0 */ + beq _restore /* it's first switch, goto _restore */ + + /* save r1:sp to thread[from] stack pointer */ + subi r1, r1, STACK_FRAME_SIZE + stw r1, 0(r3) + + /* restore r3, r4 from SPRG */ + mfspr r3,SPRG0 + mfspr r4,SPRG0 + + /* save registers */ + stw r0,GPR0(r1) /* save general purpose registers 0 */ + stmw r2,GPR2(r1) /* save general purpose registers 2-31 */ + + mfusprg0 r0 /* save usprg0 */ + stw r0,USPRG0(r1) + mfcr r0, /* save cr */ + stw r0,CR(r1) + mfxer r0 /* save xer */ + stw r0,XER(r1) + mfctr r0 /* save ctr */ + stw r0,CTR(r1) + mflr r0 /* save lr */ + stw r0, LR(r1) + + mfsrr0 r0 /* save SRR0 and SRR1 */ + stw r0,SRR0(r1) + mfsrr1 r0 + stw r0,SRR1(r1) + +_restore: + /* get thread[to] stack pointer */ + lis r4,rt_interrupt_to_thread@h + ori r4,r4,rt_interrupt_to_thread@l + lwz r1,0(r4) + lwz r1,0(r1) + + lwz r0,SRR1(r1) /* restore SRR1 and SRR0 */ + mtsrr1 r0 + lwz r0,SRR0(r1) + mtsrr0 r0 + + lwz r0,LR(r1) /* restore lr */ + mtlr r0 + lwz r0,CTR(r1) /* restore ctr */ + mtctr r0 + lwz r0,XER(r1) /* restore xer */ + mtxer r0 + lwz r0,CR(r1) /* restore cr */ + mtcr r0 + lwz r0,USPRG0(r1) /* restore usprg0 */ + // mtusprg0 r0 + + lmw r2, GPR2(r1) /* restore general register */ + lwz r0,GPR0(r1) + addi r1, r1, STACK_FRAME_SIZE + /* RFI will restore status register and thus the correct priority*/ + rfi + +_no_switch: + /* restore r3, r4 from SPRG */ + mfspr r3,SPRG0 + mfspr r4,SPRG0 + rfi + + /* void rt_hw_context_switch_to(to); */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + /* set rt_thread_switch_interrput_flag = 1 */ + lis r5,rt_thread_switch_interrput_flag@h + ori r5,r5,rt_thread_switch_interrput_flag@l + li r6, 0x01 + stw r6,0(r5) + + /* set rt_interrupt_from_thread = 0 */ + lis r5,rt_interrupt_from_thread@h + ori r5,r5,rt_interrupt_from_thread@l + li r6, 0x00 + stw r6,0(r5) + + /* set rt_interrupt_from_thread = to */ + lis r5,rt_interrupt_to_thread@h + ori r5,r5,rt_interrupt_to_thread@l + stw r3,0(r5) + + /* trigger a system call */ + sc + + blr + + /* void rt_hw_context_switch(from, to); */ + .globl rt_hw_context_switch +rt_hw_context_switch: + /* compare rt_thread_switch_interrupt_flag and set it */ + lis r5,rt_thread_switch_interrput_flag@h + ori r5,r5,rt_thread_switch_interrput_flag@l + lwz r6,0(r5) + cmpi cr0,0,r6,0x1 /* whether is 1 */ + beq _reswitch /* set already, goto _reswitch */ + li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/ + stw r6,0(r5) + + /* set rt_interrupt_from_thread to 'from' */ + lis r5,rt_interrupt_from_thread@h + ori r5,r5,rt_interrupt_from_thread@l + stw r3,0(r5) + +_reswitch: + /* set rt_interrupt_to_thread to 'to' */ + lis r6,rt_interrupt_to_thread@h + ori r6,r6,rt_interrupt_to_thread@l + stw r4,0(r6) + + /* trigger a system call */ + sc + + blr + + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + /* compare rt_thread_switch_interrupt_flag and set it */ + lis r5,rt_thread_switch_interrput_flag@h + ori r5,r5,rt_thread_switch_interrput_flag@l + lwz r6,0(r5) + cmpi cr0,0,r6,0x1 /* whether is 1 */ + beq _int_reswitch /* set already, goto _reswitch */ + li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/ + stw r6,0(r5) + + /* set rt_interrupt_from_thread to 'from' */ + lis r5,rt_interrupt_from_thread@h + ori r5,r5,rt_interrupt_from_thread@l + stw r3,0(r5) + +_int_reswitch: + /* set rt_interrupt_to_thread to 'to' */ + lis r6,rt_interrupt_to_thread@h + ori r6,r6,rt_interrupt_to_thread@l + stw r4,0(r6) + + blr diff --git a/libcpu/ppc/ppc405/include/asm/ppc405.h b/libcpu/ppc/ppc405/include/asm/ppc405.h index c15f2e3cf239d04e1d23f3aef3664726777596a1..c2562047cb9b40efd5c6f1f34d49b4b7084b55a6 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc405.h +++ b/libcpu/ppc/ppc405/include/asm/ppc405.h @@ -1,980 +1,980 @@ -/*----------------------------------------------------------------------------+ -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ - -#ifndef __PPC405_H__ -#define __PPC405_H__ - -/* Define bits and masks for real-mode storage attribute control registers */ -#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) -#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) - -/****************************************************************************** - * Special for PPC405GP - ******************************************************************************/ - -/****************************************************************************** - * DMA - ******************************************************************************/ -#define DMA_DCR_BASE 0x100 -#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ -#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ -#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ -#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ -#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ -#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ -#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ -#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ -#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ -#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ -#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ -#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ -#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ -#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ -#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ -#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ -#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ - -#ifndef CONFIG_405EP -/****************************************************************************** - * Decompression Controller - ******************************************************************************/ -#define DECOMP_DCR_BASE 0x14 -#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ -#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ - /* values for kiar register - indirect addressing of these regs */ - #define kitor0 0x00 /* index table origin register 0 */ - #define kitor1 0x01 /* index table origin register 1 */ - #define kitor2 0x02 /* index table origin register 2 */ - #define kitor3 0x03 /* index table origin register 3 */ - #define kaddr0 0x04 /* address decode definition regsiter 0 */ - #define kaddr1 0x05 /* address decode definition regsiter 1 */ - #define kconf 0x40 /* decompression core config register */ - #define kid 0x41 /* decompression core ID register */ - #define kver 0x42 /* decompression core version # reg */ - #define kpear 0x50 /* bus error addr reg (PLB addr) */ - #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ - #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ - #define kesr0s 0x53 /* bus error status reg 0 (set) */ - /* There are 0x400 of the following registers, from krom0 to krom3ff*/ - /* Only the first one is given here. */ - #define krom0 0x400 /* SRAM/ROM read/write */ -#endif - -/****************************************************************************** - * Power Management - ******************************************************************************/ -#ifdef CONFIG_405EX -#define POWERMAN_DCR_BASE 0xb0 -#else -#define POWERMAN_DCR_BASE 0xb8 -#endif -#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ -#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ -#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ - -/****************************************************************************** - * Extrnal Bus Controller - ******************************************************************************/ - /* values for ebccfga register - indirect addressing of these regs */ - #define pb0cr 0x00 /* periph bank 0 config reg */ - #define pb1cr 0x01 /* periph bank 1 config reg */ - #define pb2cr 0x02 /* periph bank 2 config reg */ - #define pb3cr 0x03 /* periph bank 3 config reg */ - #define pb4cr 0x04 /* periph bank 4 config reg */ -#ifndef CONFIG_405EP - #define pb5cr 0x05 /* periph bank 5 config reg */ - #define pb6cr 0x06 /* periph bank 6 config reg */ - #define pb7cr 0x07 /* periph bank 7 config reg */ -#endif - #define pb0ap 0x10 /* periph bank 0 access parameters */ - #define pb1ap 0x11 /* periph bank 1 access parameters */ - #define pb2ap 0x12 /* periph bank 2 access parameters */ - #define pb3ap 0x13 /* periph bank 3 access parameters */ - #define pb4ap 0x14 /* periph bank 4 access parameters */ -#ifndef CONFIG_405EP - #define pb5ap 0x15 /* periph bank 5 access parameters */ - #define pb6ap 0x16 /* periph bank 6 access parameters */ - #define pb7ap 0x17 /* periph bank 7 access parameters */ -#endif - #define pbear 0x20 /* periph bus error addr reg */ - #define pbesr0 0x21 /* periph bus error status reg 0 */ - #define pbesr1 0x22 /* periph bus error status reg 1 */ - #define epcr 0x23 /* external periph control reg */ -#define EBC0_CFG 0x23 /* external bus configuration reg */ - -#ifdef CONFIG_405EP -/****************************************************************************** - * Control - ******************************************************************************/ -#define CNTRL_DCR_BASE 0x0f0 -#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ - -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - -/* Bit definitions */ -#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ -#define PLLMR0_CPU_DIV_BYPASS 0x00000000 -#define PLLMR0_CPU_DIV_2 0x00100000 -#define PLLMR0_CPU_DIV_3 0x00200000 -#define PLLMR0_CPU_DIV_4 0x00300000 - -#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ -#define PLLMR0_CPU_PLB_DIV_1 0x00000000 -#define PLLMR0_CPU_PLB_DIV_2 0x00010000 -#define PLLMR0_CPU_PLB_DIV_3 0x00020000 -#define PLLMR0_CPU_PLB_DIV_4 0x00030000 - -#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ -#define PLLMR0_OPB_PLB_DIV_1 0x00000000 -#define PLLMR0_OPB_PLB_DIV_2 0x00001000 -#define PLLMR0_OPB_PLB_DIV_3 0x00002000 -#define PLLMR0_OPB_PLB_DIV_4 0x00003000 - -#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ -#define PLLMR0_EXB_PLB_DIV_2 0x00000000 -#define PLLMR0_EXB_PLB_DIV_3 0x00000100 -#define PLLMR0_EXB_PLB_DIV_4 0x00000200 -#define PLLMR0_EXB_PLB_DIV_5 0x00000300 - -#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ -#define PLLMR0_MAL_PLB_DIV_1 0x00000000 -#define PLLMR0_MAL_PLB_DIV_2 0x00000010 -#define PLLMR0_MAL_PLB_DIV_3 0x00000020 -#define PLLMR0_MAL_PLB_DIV_4 0x00000030 - -#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ -#define PLLMR0_PCI_PLB_DIV_1 0x00000000 -#define PLLMR0_PCI_PLB_DIV_2 0x00000001 -#define PLLMR0_PCI_PLB_DIV_3 0x00000002 -#define PLLMR0_PCI_PLB_DIV_4 0x00000003 - -#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ -#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ -#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ -#define PLLMR1_FBMUL_DIV_16 0x00000000 -#define PLLMR1_FBMUL_DIV_1 0x00100000 -#define PLLMR1_FBMUL_DIV_2 0x00200000 -#define PLLMR1_FBMUL_DIV_3 0x00300000 -#define PLLMR1_FBMUL_DIV_4 0x00400000 -#define PLLMR1_FBMUL_DIV_5 0x00500000 -#define PLLMR1_FBMUL_DIV_6 0x00600000 -#define PLLMR1_FBMUL_DIV_7 0x00700000 -#define PLLMR1_FBMUL_DIV_8 0x00800000 -#define PLLMR1_FBMUL_DIV_9 0x00900000 -#define PLLMR1_FBMUL_DIV_10 0x00A00000 -#define PLLMR1_FBMUL_DIV_11 0x00B00000 -#define PLLMR1_FBMUL_DIV_12 0x00C00000 -#define PLLMR1_FBMUL_DIV_13 0x00D00000 -#define PLLMR1_FBMUL_DIV_14 0x00E00000 -#define PLLMR1_FBMUL_DIV_15 0x00F00000 - -#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ -#define PLLMR1_FWDVA_DIV_8 0x00000000 -#define PLLMR1_FWDVA_DIV_7 0x00010000 -#define PLLMR1_FWDVA_DIV_6 0x00020000 -#define PLLMR1_FWDVA_DIV_5 0x00030000 -#define PLLMR1_FWDVA_DIV_4 0x00040000 -#define PLLMR1_FWDVA_DIV_3 0x00050000 -#define PLLMR1_FWDVA_DIV_2 0x00060000 -#define PLLMR1_FWDVA_DIV_1 0x00070000 -#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ -#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ - -/* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 - -/* Defines for CPC0_PCI Register */ -#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ -#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ -#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ - -/* Defines for CPC0_BOOR Register */ -#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -/* - *------------------------------------------------------------------------------- - * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, - * assuming a 33.3MHz input clock to the 405EP. - *------------------------------------------------------------------------------- - */ -#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_3) -#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) -#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_1) -#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -/* - * PLL Voltage Controlled Oscillator (VCO) definitions - * Maximum and minimum values (in MHz) for correct PLL operation. - */ -#define VCO_MIN 500 -#define VCO_MAX 1000 -#elif defined(CONFIG_405EZ) -#define sdrnand0 0x4000 -#define sdrultra0 0x4040 -#define sdrultra1 0x4050 -#define sdricintstat 0x4510 - -#define SDR_NAND0_NDEN 0x80000000 -#define SDR_NAND0_NDBTEN 0x40000000 -#define SDR_NAND0_NDBADR_MASK 0x30000000 -#define SDR_NAND0_NDBPG_MASK 0x0f000000 -#define SDR_NAND0_NDAREN 0x00800000 -#define SDR_NAND0_NDRBEN 0x00400000 - -#define SDR_ULTRA0_NDGPIOBP 0x80000000 -#define SDR_ULTRA0_CSN_MASK 0x78000000 -#define SDR_ULTRA0_CSNSEL0 0x40000000 -#define SDR_ULTRA0_CSNSEL1 0x20000000 -#define SDR_ULTRA0_CSNSEL2 0x10000000 -#define SDR_ULTRA0_CSNSEL3 0x08000000 -#define SDR_ULTRA0_EBCRDYEN 0x04000000 -#define SDR_ULTRA0_SPISSINEN 0x02000000 -#define SDR_ULTRA0_NFSRSTEN 0x01000000 - -#define SDR_ULTRA1_LEDNENABLE 0x40000000 - -#define SDR_ICRX_STAT 0x80000000 -#define SDR_ICTX0_STAT 0x40000000 -#define SDR_ICTX1_STAT 0x20000000 - -#define SDR_PINSTP 0x40 - -/****************************************************************************** - * Control - ******************************************************************************/ -/* CPR Registers */ -#define cprclkupd 0x020 /* CPR_CLKUPD */ -#define cprpllc 0x040 /* CPR_PLLC */ -#define cprplld 0x060 /* CPR_PLLD */ -#define cprprimad 0x080 /* CPR_PRIMAD */ -#define cprperd0 0x0e0 /* CPR_PERD0 */ -#define cprperd1 0x0e1 /* CPR_PERD1 */ -#define cprperc0 0x180 /* CPR_PERC0 */ -#define cprmisc0 0x181 /* CPR_MISC0 */ -#define cprmisc1 0x182 /* CPR_MISC1 */ - -#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ -#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ -#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ - -#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ - -#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ -#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ -#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ - -#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ -#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ -#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ -#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ - -#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ -#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ -#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ -#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ - -#else /* #ifdef CONFIG_405EP */ -/****************************************************************************** - * Control - ******************************************************************************/ -#define CNTRL_DCR_BASE 0x0b0 -#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ -#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ -#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ -#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ -#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ - -#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ -#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ - -/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ -#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ -#define CPC0_ECR (0xaa) /* edge conditioner register */ - -#define ecr (0xaa) /* edge conditioner register (405gpr) */ - -/* Bit definitions */ -#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ -#define PLLMR_FWD_DIV_BYPASS 0xE0000000 -#define PLLMR_FWD_DIV_3 0xA0000000 -#define PLLMR_FWD_DIV_4 0x80000000 -#define PLLMR_FWD_DIV_6 0x40000000 - -#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ -#define PLLMR_FB_DIV_1 0x02000000 -#define PLLMR_FB_DIV_2 0x04000000 -#define PLLMR_FB_DIV_3 0x06000000 -#define PLLMR_FB_DIV_4 0x08000000 - -#define PLLMR_TUNING_MASK 0x01F80000 - -#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ -#define PLLMR_CPU_PLB_DIV_1 0x00000000 -#define PLLMR_CPU_PLB_DIV_2 0x00020000 -#define PLLMR_CPU_PLB_DIV_3 0x00040000 -#define PLLMR_CPU_PLB_DIV_4 0x00060000 - -#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ -#define PLLMR_OPB_PLB_DIV_1 0x00000000 -#define PLLMR_OPB_PLB_DIV_2 0x00008000 -#define PLLMR_OPB_PLB_DIV_3 0x00010000 -#define PLLMR_OPB_PLB_DIV_4 0x00018000 - -#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ -#define PLLMR_PCI_PLB_DIV_1 0x00000000 -#define PLLMR_PCI_PLB_DIV_2 0x00002000 -#define PLLMR_PCI_PLB_DIV_3 0x00004000 -#define PLLMR_PCI_PLB_DIV_4 0x00006000 - -#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ -#define PLLMR_EXB_PLB_DIV_2 0x00000000 -#define PLLMR_EXB_PLB_DIV_3 0x00000800 -#define PLLMR_EXB_PLB_DIV_4 0x00001000 -#define PLLMR_EXB_PLB_DIV_5 0x00001800 - -/* definitions for PPC405GPr (new mode strapping) */ -#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ - -#define PSR_PLL_FWD_MASK 0xC0000000 -#define PSR_PLL_FDBACK_MASK 0x30000000 -#define PSR_PLL_TUNING_MASK 0x0E000000 -#define PSR_PLB_CPU_MASK 0x01800000 -#define PSR_OPB_PLB_MASK 0x00600000 -#define PSR_PCI_PLB_MASK 0x00180000 -#define PSR_EB_PLB_MASK 0x00060000 -#define PSR_ROM_WIDTH_MASK 0x00018000 -#define PSR_ROM_LOC 0x00004000 -#define PSR_PCI_ASYNC_EN 0x00001000 -#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ -#define PSR_PCI_ARBIT_EN 0x00000400 -#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ - -#ifndef CONFIG_IOP480 -/* - * PLL Voltage Controlled Oscillator (VCO) definitions - * Maximum and minimum values (in MHz) for correct PLL operation. - */ -#define VCO_MIN 400 -#define VCO_MAX 800 -#endif /* #ifndef CONFIG_IOP480 */ -#endif /* #ifdef CONFIG_405EP */ - -/****************************************************************************** - * Memory Access Layer - ******************************************************************************/ -#if defined(CONFIG_405EZ) -#define MAL_DCR_BASE 0x380 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -/* 0x08-0x0F Reserved */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -/* 0x14-0x1F Reserved */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ -#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ -#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ -#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ -#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ -#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ -#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ -#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ -#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ -#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ -#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ -#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ -#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ -#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ -#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ -#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ -#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ -#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ -#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ -#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ -#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ -#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ -#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ -#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ -#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ -#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ -#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ -#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ -#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ -#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ -#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ -#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ -#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ -#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ -#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ -#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ -#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ -#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ -#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ -#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ -#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ -#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ -#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ -#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ -#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ -#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ -#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ -#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ -#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ -#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ -#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ -#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ -#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ -#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ -#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ -#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ -#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ -#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ -#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ -#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ -#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ -#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ -#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ -#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ -#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ -#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ -#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ -#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ -#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ -#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ -#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ -#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ -#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ -#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ -#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ -#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ -#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ -#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ -#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ -#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ -#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ -#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ -#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ -#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ -#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ -#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ -#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ - -#else /* !defined(CONFIG_405EZ) */ - -#define MAL_DCR_BASE 0x180 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#endif /* defined(CONFIG_405EZ) */ - -/*----------------------------------------------------------------------------- -| IIC Register Offsets -'----------------------------------------------------------------------------*/ -#define IICMDBUF 0x00 -#define IICSDBUF 0x02 -#define IICLMADR 0x04 -#define IICHMADR 0x05 -#define IICCNTL 0x06 -#define IICMDCNTL 0x07 -#define IICSTS 0x08 -#define IICEXTSTS 0x09 -#define IICLSADR 0x0A -#define IICHSADR 0x0B -#define IICCLKDIV 0x0C -#define IICINTRMSK 0x0D -#define IICXFRCNT 0x0E -#define IICXTCNTLSS 0x0F -#define IICDIRECTCNTL 0x10 - -/*----------------------------------------------------------------------------- -| UART Register Offsets -'----------------------------------------------------------------------------*/ -#define DATA_REG 0x00 -#define DL_LSB 0x00 -#define DL_MSB 0x01 -#define INT_ENABLE 0x01 -#define FIFO_CONTROL 0x02 -#define LINE_CONTROL 0x03 -#define MODEM_CONTROL 0x04 -#define LINE_STATUS 0x05 -#define MODEM_STATUS 0x06 -#define SCRATCH 0x07 - -/****************************************************************************** - * On Chip Memory - ******************************************************************************/ -#if defined(CONFIG_405EZ) -#define OCM_DCR_BASE 0x020 -#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ -#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ -#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ -#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ -#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ -#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ -#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ -#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ -#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ -#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ -#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ -#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ -#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ -#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ -#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ -#else -#define OCM_DCR_BASE 0x018 -#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ -#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ -#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ -#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ -#endif /* CONFIG_405EZ */ - -/****************************************************************************** - * GPIO macro register defines - ******************************************************************************/ -#if defined(CONFIG_405EZ) -/* Only the 405EZ has 2 GPIOs */ -#define GPIO_BASE 0xEF600700 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRL (GPIO_BASE+0x8) -#define GPIO0_OSRH (GPIO_BASE+0xC) -#define GPIO0_TSRL (GPIO_BASE+0x10) -#define GPIO0_TSRH (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_RR3 (GPIO_BASE+0x28) -#define GPIO0_ISR1L (GPIO_BASE+0x30) -#define GPIO0_ISR1H (GPIO_BASE+0x34) -#define GPIO0_ISR2L (GPIO_BASE+0x38) -#define GPIO0_ISR2H (GPIO_BASE+0x3C) -#define GPIO0_ISR3L (GPIO_BASE+0x40) -#define GPIO0_ISR3H (GPIO_BASE+0x44) - -#define GPIO1_BASE 0xEF600800 -#define GPIO1_OR (GPIO1_BASE+0x0) -#define GPIO1_TCR (GPIO1_BASE+0x4) -#define GPIO1_OSRL (GPIO1_BASE+0x8) -#define GPIO1_OSRH (GPIO1_BASE+0xC) -#define GPIO1_TSRL (GPIO1_BASE+0x10) -#define GPIO1_TSRH (GPIO1_BASE+0x14) -#define GPIO1_ODR (GPIO1_BASE+0x18) -#define GPIO1_IR (GPIO1_BASE+0x1C) -#define GPIO1_RR1 (GPIO1_BASE+0x20) -#define GPIO1_RR2 (GPIO1_BASE+0x24) -#define GPIO1_RR3 (GPIO1_BASE+0x28) -#define GPIO1_ISR1L (GPIO1_BASE+0x30) -#define GPIO1_ISR1H (GPIO1_BASE+0x34) -#define GPIO1_ISR2L (GPIO1_BASE+0x38) -#define GPIO1_ISR2H (GPIO1_BASE+0x3C) -#define GPIO1_ISR3L (GPIO1_BASE+0x40) -#define GPIO1_ISR3H (GPIO1_BASE+0x44) - -#elif defined(CONFIG_405EX) -#define GPIO_BASE 0xEF600800 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRL (GPIO_BASE+0x8) -#define GPIO0_OSRH (GPIO_BASE+0xC) -#define GPIO0_TSRL (GPIO_BASE+0x10) -#define GPIO0_TSRH (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_ISR1L (GPIO_BASE+0x30) -#define GPIO0_ISR1H (GPIO_BASE+0x34) -#define GPIO0_ISR2L (GPIO_BASE+0x38) -#define GPIO0_ISR2H (GPIO_BASE+0x3C) -#define GPIO0_ISR3L (GPIO_BASE+0x40) -#define GPIO0_ISR3H (GPIO_BASE+0x44) - -#else /* !405EZ */ - -#define GPIO_BASE 0xEF600700 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRH (GPIO_BASE+0x8) -#define GPIO0_OSRL (GPIO_BASE+0xC) -#define GPIO0_TSRH (GPIO_BASE+0x10) -#define GPIO0_TSRL (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_ISR1H (GPIO_BASE+0x30) -#define GPIO0_ISR1L (GPIO_BASE+0x34) -#define GPIO0_ISR2H (GPIO_BASE+0x38) -#define GPIO0_ISR2L (GPIO_BASE+0x3C) - -#endif /* CONFIG_405EZ */ - -#define GPIO0_BASE GPIO_BASE - -#if defined(CONFIG_405EX) -#define SDR0_SRST 0x0200 - -/* - * Software Reset Register - */ -#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) -#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) -#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) -#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) -#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) -#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) -#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) -#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) -#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) -#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) -#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) -#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) -#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) -#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) -#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) -#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) -#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) -#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) -#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) -#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) -#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) -#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) -#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) -#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) -#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) -#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) -#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) -#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) -#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) -#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) -#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) -#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) - -#define sdr_uart0 0x0120 /* UART0 Config */ -#define sdr_uart1 0x0121 /* UART1 Config */ -#define sdr_mfr 0x4300 /* SDR0_MFR reg */ - -/* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 - -#define cpr0_clkupd 0x020 -#define cpr0_pllc 0x040 -#define cpr0_plld 0x060 -#define cpr0_cpud 0x080 -#define cpr0_plbd 0x0a0 -#define cpr0_opbd 0x0c0 -#define cpr0_perd 0x0e0 -#define cpr0_ahbd 0x100 -#define cpr0_icfg 0x140 - -#define SDR_PINSTP 0x0040 -#define sdr_sdcs 0x0060 - -#define SDR0_SDCS_SDD (0x80000000 >> 31) - -/* CUST0 Customer Configuration Register0 */ -#define SDR0_CUST0 0x4000 -#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ -#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ -#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ -#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ - -#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ -#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ -#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ - -#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ -#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ -#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ - -#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ -#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) -#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) - -#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ -#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) -#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) - -#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ - -#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ -#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ -#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ - -#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ -#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) -#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) - -#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ -#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ -#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ - -#define SDR0_PFC0 0x4100 -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME 0x02000000 -#define SDR0_PFC1_U0ME 0x00080000 -#define SDR0_PFC1_U0IM 0x00040000 -#define SDR0_PFC1_SIS 0x00020000 -#define SDR0_PFC1_DMAAEN 0x00010000 -#define SDR0_PFC1_DMADEN 0x00008000 -#define SDR0_PFC1_USBEN 0x00004000 -#define SDR0_PFC1_AHBSWAP 0x00000020 -#define SDR0_PFC1_USBBIGEN 0x00000010 -#define SDR0_PFC1_GPT_FREQ 0x0000000f -#endif - -/* General Purpose Timer (GPT) Register Offsets */ -#define GPT0_TBC 0x00000000 -#define GPT0_IM 0x00000018 -#define GPT0_ISS 0x0000001C -#define GPT0_ISC 0x00000020 -#define GPT0_IE 0x00000024 -#define GPT0_COMP0 0x00000080 -#define GPT0_COMP1 0x00000084 -#define GPT0_COMP2 0x00000088 -#define GPT0_COMP3 0x0000008C -#define GPT0_COMP4 0x00000090 -#define GPT0_COMP5 0x00000094 -#define GPT0_COMP6 0x00000098 -#define GPT0_MASK0 0x000000C0 -#define GPT0_MASK1 0x000000C4 -#define GPT0_MASK2 0x000000C8 -#define GPT0_MASK3 0x000000CC -#define GPT0_MASK4 0x000000D0 -#define GPT0_MASK5 0x000000D4 -#define GPT0_MASK6 0x000000D8 -#define GPT0_DCT0 0x00000110 -#define GPT0_DCIS 0x0000011C - -#endif /* __PPC405_H__ */ +/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC405_H__ +#define __PPC405_H__ + +/* Define bits and masks for real-mode storage attribute control registers */ +#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) +#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) + +/****************************************************************************** + * Special for PPC405GP + ******************************************************************************/ + +/****************************************************************************** + * DMA + ******************************************************************************/ +#define DMA_DCR_BASE 0x100 +#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ +#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ +#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ +#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ +#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ +#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ +#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ +#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ +#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ +#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ +#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ +#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ +#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ +#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ +#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ +#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ +#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ + +#ifndef CONFIG_405EP +/****************************************************************************** + * Decompression Controller + ******************************************************************************/ +#define DECOMP_DCR_BASE 0x14 +#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ +#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ + /* values for kiar register - indirect addressing of these regs */ + #define kitor0 0x00 /* index table origin register 0 */ + #define kitor1 0x01 /* index table origin register 1 */ + #define kitor2 0x02 /* index table origin register 2 */ + #define kitor3 0x03 /* index table origin register 3 */ + #define kaddr0 0x04 /* address decode definition regsiter 0 */ + #define kaddr1 0x05 /* address decode definition regsiter 1 */ + #define kconf 0x40 /* decompression core config register */ + #define kid 0x41 /* decompression core ID register */ + #define kver 0x42 /* decompression core version # reg */ + #define kpear 0x50 /* bus error addr reg (PLB addr) */ + #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ + #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ + #define kesr0s 0x53 /* bus error status reg 0 (set) */ + /* There are 0x400 of the following registers, from krom0 to krom3ff*/ + /* Only the first one is given here. */ + #define krom0 0x400 /* SRAM/ROM read/write */ +#endif + +/****************************************************************************** + * Power Management + ******************************************************************************/ +#ifdef CONFIG_405EX +#define POWERMAN_DCR_BASE 0xb0 +#else +#define POWERMAN_DCR_BASE 0xb8 +#endif +#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ +#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ +#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ + +/****************************************************************************** + * Extrnal Bus Controller + ******************************************************************************/ + /* values for ebccfga register - indirect addressing of these regs */ + #define pb0cr 0x00 /* periph bank 0 config reg */ + #define pb1cr 0x01 /* periph bank 1 config reg */ + #define pb2cr 0x02 /* periph bank 2 config reg */ + #define pb3cr 0x03 /* periph bank 3 config reg */ + #define pb4cr 0x04 /* periph bank 4 config reg */ +#ifndef CONFIG_405EP + #define pb5cr 0x05 /* periph bank 5 config reg */ + #define pb6cr 0x06 /* periph bank 6 config reg */ + #define pb7cr 0x07 /* periph bank 7 config reg */ +#endif + #define pb0ap 0x10 /* periph bank 0 access parameters */ + #define pb1ap 0x11 /* periph bank 1 access parameters */ + #define pb2ap 0x12 /* periph bank 2 access parameters */ + #define pb3ap 0x13 /* periph bank 3 access parameters */ + #define pb4ap 0x14 /* periph bank 4 access parameters */ +#ifndef CONFIG_405EP + #define pb5ap 0x15 /* periph bank 5 access parameters */ + #define pb6ap 0x16 /* periph bank 6 access parameters */ + #define pb7ap 0x17 /* periph bank 7 access parameters */ +#endif + #define pbear 0x20 /* periph bus error addr reg */ + #define pbesr0 0x21 /* periph bus error status reg 0 */ + #define pbesr1 0x22 /* periph bus error status reg 1 */ + #define epcr 0x23 /* external periph control reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ + +#ifdef CONFIG_405EP +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0f0 +#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ + +/* Bit definitions */ +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ +#define PLLMR0_CPU_DIV_BYPASS 0x00000000 +#define PLLMR0_CPU_DIV_2 0x00100000 +#define PLLMR0_CPU_DIV_3 0x00200000 +#define PLLMR0_CPU_DIV_4 0x00300000 + +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ +#define PLLMR0_CPU_PLB_DIV_1 0x00000000 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000 + +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ +#define PLLMR0_OPB_PLB_DIV_1 0x00000000 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000 + +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_PLB_DIV_2 0x00000000 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300 + +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_PLB_DIV_1 0x00000000 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030 + +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ +#define PLLMR0_PCI_PLB_DIV_1 0x00000000 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003 + +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ +#define PLLMR1_FBMUL_DIV_16 0x00000000 +#define PLLMR1_FBMUL_DIV_1 0x00100000 +#define PLLMR1_FBMUL_DIV_2 0x00200000 +#define PLLMR1_FBMUL_DIV_3 0x00300000 +#define PLLMR1_FBMUL_DIV_4 0x00400000 +#define PLLMR1_FBMUL_DIV_5 0x00500000 +#define PLLMR1_FBMUL_DIV_6 0x00600000 +#define PLLMR1_FBMUL_DIV_7 0x00700000 +#define PLLMR1_FBMUL_DIV_8 0x00800000 +#define PLLMR1_FBMUL_DIV_9 0x00900000 +#define PLLMR1_FBMUL_DIV_10 0x00A00000 +#define PLLMR1_FBMUL_DIV_11 0x00B00000 +#define PLLMR1_FBMUL_DIV_12 0x00C00000 +#define PLLMR1_FBMUL_DIV_13 0x00D00000 +#define PLLMR1_FBMUL_DIV_14 0x00E00000 +#define PLLMR1_FBMUL_DIV_15 0x00F00000 + +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVA_DIV_8 0x00000000 +#define PLLMR1_FWDVA_DIV_7 0x00010000 +#define PLLMR1_FWDVA_DIV_6 0x00020000 +#define PLLMR1_FWDVA_DIV_5 0x00030000 +#define PLLMR1_FWDVA_DIV_4 0x00040000 +#define PLLMR1_FWDVA_DIV_3 0x00050000 +#define PLLMR1_FWDVA_DIV_2 0x00060000 +#define PLLMR1_FWDVA_DIV_1 0x00070000 +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +/* Defines for CPC0_PCI Register */ +#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ +#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ +#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ + +/* Defines for CPC0_BOOR Register */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ + +/* Defines for CPC0_PLLMR1 Register fields */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 + /* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 + /* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 + /* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 + /* PLL tune bits */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ + +/* Defines for CPC0_PLLMR0 Register fields */ + /* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 + /* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 + /* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 + /* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 + /* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 + /* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +/* + *------------------------------------------------------------------------------- + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 33.3MHz input clock to the 405EP. + *------------------------------------------------------------------------------- + */ +#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 500 +#define VCO_MAX 1000 +#elif defined(CONFIG_405EZ) +#define sdrnand0 0x4000 +#define sdrultra0 0x4040 +#define sdrultra1 0x4050 +#define sdricintstat 0x4510 + +#define SDR_NAND0_NDEN 0x80000000 +#define SDR_NAND0_NDBTEN 0x40000000 +#define SDR_NAND0_NDBADR_MASK 0x30000000 +#define SDR_NAND0_NDBPG_MASK 0x0f000000 +#define SDR_NAND0_NDAREN 0x00800000 +#define SDR_NAND0_NDRBEN 0x00400000 + +#define SDR_ULTRA0_NDGPIOBP 0x80000000 +#define SDR_ULTRA0_CSN_MASK 0x78000000 +#define SDR_ULTRA0_CSNSEL0 0x40000000 +#define SDR_ULTRA0_CSNSEL1 0x20000000 +#define SDR_ULTRA0_CSNSEL2 0x10000000 +#define SDR_ULTRA0_CSNSEL3 0x08000000 +#define SDR_ULTRA0_EBCRDYEN 0x04000000 +#define SDR_ULTRA0_SPISSINEN 0x02000000 +#define SDR_ULTRA0_NFSRSTEN 0x01000000 + +#define SDR_ULTRA1_LEDNENABLE 0x40000000 + +#define SDR_ICRX_STAT 0x80000000 +#define SDR_ICTX0_STAT 0x40000000 +#define SDR_ICTX1_STAT 0x20000000 + +#define SDR_PINSTP 0x40 + +/****************************************************************************** + * Control + ******************************************************************************/ +/* CPR Registers */ +#define cprclkupd 0x020 /* CPR_CLKUPD */ +#define cprpllc 0x040 /* CPR_PLLC */ +#define cprplld 0x060 /* CPR_PLLD */ +#define cprprimad 0x080 /* CPR_PRIMAD */ +#define cprperd0 0x0e0 /* CPR_PERD0 */ +#define cprperd1 0x0e1 /* CPR_PERD1 */ +#define cprperc0 0x180 /* CPR_PERC0 */ +#define cprmisc0 0x181 /* CPR_MISC0 */ +#define cprmisc1 0x182 /* CPR_MISC1 */ + +#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ +#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ +#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ + +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ + +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ +#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ + +#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ +#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ +#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ +#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ + +#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ +#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ +#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ +#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ + +#else /* #ifdef CONFIG_405EP */ +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0b0 +#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ +#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ +#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ +#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ +#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ + +#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ +#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ + +/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ +#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ +#define CPC0_ECR (0xaa) /* edge conditioner register */ + +#define ecr (0xaa) /* edge conditioner register (405gpr) */ + +/* Bit definitions */ +#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ +#define PLLMR_FWD_DIV_BYPASS 0xE0000000 +#define PLLMR_FWD_DIV_3 0xA0000000 +#define PLLMR_FWD_DIV_4 0x80000000 +#define PLLMR_FWD_DIV_6 0x40000000 + +#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ +#define PLLMR_FB_DIV_1 0x02000000 +#define PLLMR_FB_DIV_2 0x04000000 +#define PLLMR_FB_DIV_3 0x06000000 +#define PLLMR_FB_DIV_4 0x08000000 + +#define PLLMR_TUNING_MASK 0x01F80000 + +#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ +#define PLLMR_CPU_PLB_DIV_1 0x00000000 +#define PLLMR_CPU_PLB_DIV_2 0x00020000 +#define PLLMR_CPU_PLB_DIV_3 0x00040000 +#define PLLMR_CPU_PLB_DIV_4 0x00060000 + +#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ +#define PLLMR_OPB_PLB_DIV_1 0x00000000 +#define PLLMR_OPB_PLB_DIV_2 0x00008000 +#define PLLMR_OPB_PLB_DIV_3 0x00010000 +#define PLLMR_OPB_PLB_DIV_4 0x00018000 + +#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ +#define PLLMR_PCI_PLB_DIV_1 0x00000000 +#define PLLMR_PCI_PLB_DIV_2 0x00002000 +#define PLLMR_PCI_PLB_DIV_3 0x00004000 +#define PLLMR_PCI_PLB_DIV_4 0x00006000 + +#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ +#define PLLMR_EXB_PLB_DIV_2 0x00000000 +#define PLLMR_EXB_PLB_DIV_3 0x00000800 +#define PLLMR_EXB_PLB_DIV_4 0x00001000 +#define PLLMR_EXB_PLB_DIV_5 0x00001800 + +/* definitions for PPC405GPr (new mode strapping) */ +#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ + +#define PSR_PLL_FWD_MASK 0xC0000000 +#define PSR_PLL_FDBACK_MASK 0x30000000 +#define PSR_PLL_TUNING_MASK 0x0E000000 +#define PSR_PLB_CPU_MASK 0x01800000 +#define PSR_OPB_PLB_MASK 0x00600000 +#define PSR_PCI_PLB_MASK 0x00180000 +#define PSR_EB_PLB_MASK 0x00060000 +#define PSR_ROM_WIDTH_MASK 0x00018000 +#define PSR_ROM_LOC 0x00004000 +#define PSR_PCI_ASYNC_EN 0x00001000 +#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ +#define PSR_PCI_ARBIT_EN 0x00000400 +#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ + +#ifndef CONFIG_IOP480 +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 400 +#define VCO_MAX 800 +#endif /* #ifndef CONFIG_IOP480 */ +#endif /* #ifdef CONFIG_405EP */ + +/****************************************************************************** + * Memory Access Layer + ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define MAL_DCR_BASE 0x380 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +/* 0x08-0x0F Reserved */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +/* 0x14-0x1F Reserved */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ +#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ +#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ +#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ +#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ +#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ +#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ +#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ +#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ +#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ +#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ +#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ +#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ +#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ +#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ +#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ +#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ +#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ +#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ +#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ +#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ +#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ +#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ +#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ +#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ +#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ +#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ +#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ +#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ +#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ +#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ +#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ +#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ +#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ +#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ +#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ +#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ +#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ +#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ +#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ +#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ +#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ +#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ +#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ +#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ +#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ +#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ +#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ +#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ +#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ +#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ +#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ +#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ +#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ +#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ +#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ +#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ +#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ +#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ +#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ +#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ +#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ +#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ +#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ +#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ +#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ +#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ +#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ +#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ +#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ +#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ +#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ +#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ +#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ +#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ +#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ +#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ +#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ +#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ +#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ +#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ +#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ + +#else /* !defined(CONFIG_405EZ) */ + +#define MAL_DCR_BASE 0x180 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#endif /* defined(CONFIG_405EZ) */ + +/*----------------------------------------------------------------------------- +| IIC Register Offsets +'----------------------------------------------------------------------------*/ +#define IICMDBUF 0x00 +#define IICSDBUF 0x02 +#define IICLMADR 0x04 +#define IICHMADR 0x05 +#define IICCNTL 0x06 +#define IICMDCNTL 0x07 +#define IICSTS 0x08 +#define IICEXTSTS 0x09 +#define IICLSADR 0x0A +#define IICHSADR 0x0B +#define IICCLKDIV 0x0C +#define IICINTRMSK 0x0D +#define IICXFRCNT 0x0E +#define IICXTCNTLSS 0x0F +#define IICDIRECTCNTL 0x10 + +/*----------------------------------------------------------------------------- +| UART Register Offsets +'----------------------------------------------------------------------------*/ +#define DATA_REG 0x00 +#define DL_LSB 0x00 +#define DL_MSB 0x01 +#define INT_ENABLE 0x01 +#define FIFO_CONTROL 0x02 +#define LINE_CONTROL 0x03 +#define MODEM_CONTROL 0x04 +#define LINE_STATUS 0x05 +#define MODEM_STATUS 0x06 +#define SCRATCH 0x07 + +/****************************************************************************** + * On Chip Memory + ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define OCM_DCR_BASE 0x020 +#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ +#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ +#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ +#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ +#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ +#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ +#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ +#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ +#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ +#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ +#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ +#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ +#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ +#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ +#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#else +#define OCM_DCR_BASE 0x018 +#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ +#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ +#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ +#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#endif /* CONFIG_405EZ */ + +/****************************************************************************** + * GPIO macro register defines + ******************************************************************************/ +#if defined(CONFIG_405EZ) +/* Only the 405EZ has 2 GPIOs */ +#define GPIO_BASE 0xEF600700 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_RR3 (GPIO_BASE+0x28) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + +#define GPIO1_BASE 0xEF600800 +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) + +#elif defined(CONFIG_405EX) +#define GPIO_BASE 0xEF600800 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + +#else /* !405EZ */ + +#define GPIO_BASE 0xEF600700 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRH (GPIO_BASE+0x8) +#define GPIO0_OSRL (GPIO_BASE+0xC) +#define GPIO0_TSRH (GPIO_BASE+0x10) +#define GPIO0_TSRL (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1H (GPIO_BASE+0x30) +#define GPIO0_ISR1L (GPIO_BASE+0x34) +#define GPIO0_ISR2H (GPIO_BASE+0x38) +#define GPIO0_ISR2L (GPIO_BASE+0x3C) + +#endif /* CONFIG_405EZ */ + +#define GPIO0_BASE GPIO_BASE + +#if defined(CONFIG_405EX) +#define SDR0_SRST 0x0200 + +/* + * Software Reset Register + */ +#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) +#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) +#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) +#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) +#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) +#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) +#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) +#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) +#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) +#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) +#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) +#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) +#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) +#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) +#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) +#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) +#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) +#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) +#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) +#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) +#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) +#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) +#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) +#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) +#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) +#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) +#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) +#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) +#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) +#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) +#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) +#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) + +#define sdr_uart0 0x0120 /* UART0 Config */ +#define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_mfr 0x4300 /* SDR0_MFR reg */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +#define cpr0_clkupd 0x020 +#define cpr0_pllc 0x040 +#define cpr0_plld 0x060 +#define cpr0_cpud 0x080 +#define cpr0_plbd 0x0a0 +#define cpr0_opbd 0x0c0 +#define cpr0_perd 0x0e0 +#define cpr0_ahbd 0x100 +#define cpr0_icfg 0x140 + +#define SDR_PINSTP 0x0040 +#define sdr_sdcs 0x0060 + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME 0x02000000 +#define SDR0_PFC1_U0ME 0x00080000 +#define SDR0_PFC1_U0IM 0x00040000 +#define SDR0_PFC1_SIS 0x00020000 +#define SDR0_PFC1_DMAAEN 0x00010000 +#define SDR0_PFC1_DMADEN 0x00008000 +#define SDR0_PFC1_USBEN 0x00004000 +#define SDR0_PFC1_AHBSWAP 0x00000020 +#define SDR0_PFC1_USBBIGEN 0x00000010 +#define SDR0_PFC1_GPT_FREQ 0x0000000f +#endif + +/* General Purpose Timer (GPT) Register Offsets */ +#define GPT0_TBC 0x00000000 +#define GPT0_IM 0x00000018 +#define GPT0_ISS 0x0000001C +#define GPT0_ISC 0x00000020 +#define GPT0_IE 0x00000024 +#define GPT0_COMP0 0x00000080 +#define GPT0_COMP1 0x00000084 +#define GPT0_COMP2 0x00000088 +#define GPT0_COMP3 0x0000008C +#define GPT0_COMP4 0x00000090 +#define GPT0_COMP5 0x00000094 +#define GPT0_COMP6 0x00000098 +#define GPT0_MASK0 0x000000C0 +#define GPT0_MASK1 0x000000C4 +#define GPT0_MASK2 0x000000C8 +#define GPT0_MASK3 0x000000CC +#define GPT0_MASK4 0x000000D0 +#define GPT0_MASK5 0x000000D4 +#define GPT0_MASK6 0x000000D8 +#define GPT0_DCT0 0x00000110 +#define GPT0_DCIS 0x0000011C + +#endif /* __PPC405_H__ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h index e70b99bda6bc34da6163caa7406c4920ba0864b5..cdb542c2dab861ebfd936af8fcf25a1c9e151e90 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h +++ b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h @@ -1,61 +1,61 @@ -#ifndef _PPC4xx_UIC_H_ -#define _PPC4xx_UIC_H_ - -/* - * Define the number of UIC's - */ -#define UIC_MAX 1 -#define IRQ_MAX UIC_MAX * 32 - -/* UIC0 dcr base address */ -#define UIC0_DCR_BASE 0xc0 - -/* - * UIC register - */ -#define UIC_SR 0x0 /* UIC status */ -#define UIC_ER 0x2 /* UIC enable */ -#define UIC_CR 0x3 /* UIC critical */ -#define UIC_PR 0x4 /* UIC polarity */ -#define UIC_TR 0x5 /* UIC triggering */ -#define UIC_MSR 0x6 /* UIC masked status */ -#define UIC_VR 0x7 /* UIC vector */ -#define UIC_VCR 0x8 /* UIC vector configuration */ - -#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ -#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ -#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ -#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ -#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ -#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ -#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ -#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ - -/* The following is for compatibility with 405 code */ -#define uicsr uic0sr -#define uicer uic0er -#define uiccr uic0cr -#define uicpr uic0pr -#define uictr uic0tr -#define uicmsr uic0msr -#define uicvr uic0vr -#define uicvcr uic0vcr - -/* the interrupt vector definitions */ -#define VECNUM_MAL_SERR 10 -#define VECNUM_MAL_TXEOB 11 -#define VECNUM_MAL_RXEOB 12 -#define VECNUM_MAL_TXDE 13 -#define VECNUM_MAL_RXDE 14 -#define VECNUM_ETH0 15 -#define VECNUM_ETH1_OFFS 2 -#define VECNUM_EIRQ6 29 - -/* - * Mask definitions (used for example in 4xx_enet.c) - */ -#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) -/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ -#define UIC_NR(vec) ((vec) >> 5) - -#endif /* _PPC4xx_UIC_H_ */ +#ifndef _PPC4xx_UIC_H_ +#define _PPC4xx_UIC_H_ + +/* + * Define the number of UIC's + */ +#define UIC_MAX 1 +#define IRQ_MAX UIC_MAX * 32 + +/* UIC0 dcr base address */ +#define UIC0_DCR_BASE 0xc0 + +/* + * UIC register + */ +#define UIC_SR 0x0 /* UIC status */ +#define UIC_ER 0x2 /* UIC enable */ +#define UIC_CR 0x3 /* UIC critical */ +#define UIC_PR 0x4 /* UIC polarity */ +#define UIC_TR 0x5 /* UIC triggering */ +#define UIC_MSR 0x6 /* UIC masked status */ +#define UIC_VR 0x7 /* UIC vector */ +#define UIC_VCR 0x8 /* UIC vector configuration */ + +#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ + +/* The following is for compatibility with 405 code */ +#define uicsr uic0sr +#define uicer uic0er +#define uiccr uic0cr +#define uicpr uic0pr +#define uictr uic0tr +#define uicmsr uic0msr +#define uicvr uic0vr +#define uicvcr uic0vcr + +/* the interrupt vector definitions */ +#define VECNUM_MAL_SERR 10 +#define VECNUM_MAL_TXEOB 11 +#define VECNUM_MAL_RXEOB 12 +#define VECNUM_MAL_TXDE 13 +#define VECNUM_MAL_RXDE 14 +#define VECNUM_ETH0 15 +#define VECNUM_ETH1_OFFS 2 +#define VECNUM_EIRQ6 29 + +/* + * Mask definitions (used for example in 4xx_enet.c) + */ +#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) +/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ +#define UIC_NR(vec) ((vec) >> 5) + +#endif /* _PPC4xx_UIC_H_ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx.h b/libcpu/ppc/ppc405/include/asm/ppc4xx.h index bf055f0879b212524caba76321916582bc966a60..57fe7ab2211b63faf9f8c16a81e2f2b6d4c1f520 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc4xx.h +++ b/libcpu/ppc/ppc405/include/asm/ppc4xx.h @@ -1,134 +1,134 @@ -/*----------------------------------------------------------------------------+ -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ - -#ifndef __PPC4XX_H__ -#define __PPC4XX_H__ - -/* - * Configure which SDRAM/DDR/DDR2 controller is equipped - */ -#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ - -#include -#include - -/* - * Macro for generating register field mnemonics - */ -#define PPC_REG_BITS 32 -#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) - -/* - * Elide casts when assembling register mnemonics - */ -#ifndef __ASSEMBLY__ -#define static_cast(type, val) (type)(val) -#else -#define static_cast(type, val) (val) -#endif - -/* - * Common stuff for 4xx (405 and 440) - */ - -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) - -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache - line aligned data. */ - -#define CPR0_DCR_BASE 0x0C -#define cprcfga (CPR0_DCR_BASE+0x0) -#define cprcfgd (CPR0_DCR_BASE+0x1) - -#define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) - -#define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) -#define memcfgd (SDRAM_DCR_BASE+0x1) - -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) -#define ebccfgd (EBC_DCR_BASE+0x1) - -/* - * Macros for indirect DCR access - */ -#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) -#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) - -#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) -#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) - -#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) -#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) - -#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) -#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) - -#ifndef __ASSEMBLY__ - -typedef struct -{ - unsigned long freqDDR; - unsigned long freqEBC; - unsigned long freqOPB; - unsigned long freqPCI; - unsigned long freqPLB; - unsigned long freqTmrClk; - unsigned long freqUART; - unsigned long freqProcessor; - unsigned long freqVCOHz; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long pciClkSync; /* PCI clock is synchronous */ - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pllExtBusDiv; - unsigned long pllFbkDiv; - unsigned long pllFwdDiv; - unsigned long pllFwdDivA; - unsigned long pllFwdDivB; - unsigned long pllOpbDiv; - unsigned long pllPciDiv; - unsigned long pllPlbDiv; -} PPC4xx_SYS_INFO; - -static inline rt_uint32_t get_mcsr(void) -{ - rt_uint32_t val; - - asm volatile("mfspr %0, 0x23c" : "=r" (val) :); - return val; -} - -static inline void set_mcsr(rt_uint32_t val) -{ - asm volatile("mtspr 0x23c, %0" : "=r" (val) :); -} - -#endif /* __ASSEMBLY__ */ - -/* for multi-cpu support */ -#define NA_OR_UNKNOWN_CPU -1 - -#endif /* __PPC4XX_H__ */ +/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC4XX_H__ +#define __PPC4XX_H__ + +/* + * Configure which SDRAM/DDR/DDR2 controller is equipped + */ +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ + +#include +#include + +/* + * Macro for generating register field mnemonics + */ +#define PPC_REG_BITS 32 +#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) + +/* + * Elide casts when assembling register mnemonics + */ +#ifndef __ASSEMBLY__ +#define static_cast(type, val) (type)(val) +#else +#define static_cast(type, val) (val) +#endif + +/* + * Common stuff for 4xx (405 and 440) + */ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) + +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache + line aligned data. */ + +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define SDRAM_DCR_BASE 0x10 +#define memcfga (SDRAM_DCR_BASE+0x0) +#define memcfgd (SDRAM_DCR_BASE+0x1) + +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) + +/* + * Macros for indirect DCR access + */ +#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) + +#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) +#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) + +#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) + +#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqDDR; + unsigned long freqEBC; + unsigned long freqOPB; + unsigned long freqPCI; + unsigned long freqPLB; + unsigned long freqTmrClk; + unsigned long freqUART; + unsigned long freqProcessor; + unsigned long freqVCOHz; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pllExtBusDiv; + unsigned long pllFbkDiv; + unsigned long pllFwdDiv; + unsigned long pllFwdDivA; + unsigned long pllFwdDivB; + unsigned long pllOpbDiv; + unsigned long pllPciDiv; + unsigned long pllPlbDiv; +} PPC4xx_SYS_INFO; + +static inline rt_uint32_t get_mcsr(void) +{ + rt_uint32_t val; + + asm volatile("mfspr %0, 0x23c" : "=r" (val) :); + return val; +} + +static inline void set_mcsr(rt_uint32_t val) +{ + asm volatile("mtspr 0x23c, %0" : "=r" (val) :); +} + +#endif /* __ASSEMBLY__ */ + +/* for multi-cpu support */ +#define NA_OR_UNKNOWN_CPU -1 + +#endif /* __PPC4XX_H__ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc_defs.h b/libcpu/ppc/ppc405/include/asm/ppc_defs.h index dd1e42a9259753013a974d18874a09ca5b6ef1ae..88aed2600926793a81e25d8cd345aeb3fc5f7826 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc_defs.h +++ b/libcpu/ppc/ppc405/include/asm/ppc_defs.h @@ -1,73 +1,73 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * WARNING! This file is automatically generated - DO NOT EDIT! - */ -#define STACK_FRAME_OVERHEAD 16 -#define INT_FRAME_SIZE 192 -#define GPR0 16 -#define GPR1 20 -#define GPR2 24 -#define GPR3 28 -#define GPR4 32 -#define GPR5 36 -#define GPR6 40 -#define GPR7 44 -#define GPR8 48 -#define GPR9 52 -#define GPR10 56 -#define GPR11 60 -#define GPR12 64 -#define GPR13 68 -#define GPR14 72 -#define GPR15 76 -#define GPR16 80 -#define GPR17 84 -#define GPR18 88 -#define GPR19 92 -#define GPR20 96 -#define GPR21 100 -#define GPR22 104 -#define GPR23 108 -#define GPR24 112 -#define GPR25 116 -#define GPR26 120 -#define GPR27 124 -#define GPR28 128 -#define GPR29 132 -#define GPR30 136 -#define GPR31 140 -#define _NIP 144 -#define _MSR 148 -#define ORIG_GPR3 152 -#define _CTR 156 -#define _LINK 160 -#define _XER 164 -#define _CCR 168 -#define _MQ 172 -#define TRAP 176 -#define _DAR 180 -#define _DSISR 184 -#define RESULT 188 - +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * WARNING! This file is automatically generated - DO NOT EDIT! + */ +#define STACK_FRAME_OVERHEAD 16 +#define INT_FRAME_SIZE 192 +#define GPR0 16 +#define GPR1 20 +#define GPR2 24 +#define GPR3 28 +#define GPR4 32 +#define GPR5 36 +#define GPR6 40 +#define GPR7 44 +#define GPR8 48 +#define GPR9 52 +#define GPR10 56 +#define GPR11 60 +#define GPR12 64 +#define GPR13 68 +#define GPR14 72 +#define GPR15 76 +#define GPR16 80 +#define GPR17 84 +#define GPR18 88 +#define GPR19 92 +#define GPR20 96 +#define GPR21 100 +#define GPR22 104 +#define GPR23 108 +#define GPR24 112 +#define GPR25 116 +#define GPR26 120 +#define GPR27 124 +#define GPR28 128 +#define GPR29 132 +#define GPR30 136 +#define GPR31 140 +#define _NIP 144 +#define _MSR 148 +#define ORIG_GPR3 152 +#define _CTR 156 +#define _LINK 160 +#define _XER 164 +#define _CCR 168 +#define _MQ 172 +#define TRAP 176 +#define _DAR 180 +#define _DSISR 184 +#define RESULT 188 + diff --git a/libcpu/ppc/ppc405/include/asm/processor.h b/libcpu/ppc/ppc405/include/asm/processor.h index fead8705582e175cfb7afa8100b5e14567d666d4..7aeeb01dc589270aa954538d391ad21e4f2da6b2 100644 --- a/libcpu/ppc/ppc405/include/asm/processor.h +++ b/libcpu/ppc/ppc405/include/asm/processor.h @@ -1,1238 +1,1238 @@ -#ifndef __ASM_PPC_PROCESSOR_H -#define __ASM_PPC_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#include - -#include -#include - -/* Machine State Register (MSR) Fields */ - -#ifdef CONFIG_PPC64BRIDGE -#define MSR_SF (1<<63) -#define MSR_ISF (1<<61) -#endif /* CONFIG_PPC64BRIDGE */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ -#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ -#define MSR_SPE (1<<25) /* Enable SPE(e500) */ -#define MSR_POW (1<<18) /* Enable Power Management */ -#define MSR_WE (1<<18) /* Wait State Enable */ -#define MSR_TGPR (1<<17) /* TLB Update registers in use */ -#define MSR_CE (1<<17) /* Critical Interrupt Enable */ -#define MSR_ILE (1<<16) /* Interrupt Little Endian */ -#define MSR_EE (1<<15) /* External Interrupt Enable */ -#define MSR_PR (1<<14) /* Problem State / Privilege Level */ -#define MSR_FP (1<<13) /* Floating Point enable */ -#define MSR_ME (1<<12) /* Machine Check Enable */ -#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ -#define MSR_SE (1<<10) /* Single Step */ -#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ -#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ -#define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* Debug Exception Enable */ -#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ -#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction Relocate */ -#define MSR_IS (1<<5) /* Book E Instruction space */ -#define MSR_DR (1<<4) /* Data Relocate */ -#define MSR_DS (1<<4) /* Book E Data space */ -#define MSR_PE (1<<3) /* Protection Enable */ -#define MSR_PX (1<<2) /* Protection Exclusive Mode */ -#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ -#define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little Endian */ - -#ifdef CONFIG_APUS_FAST_EXCEPT -#define MSR_ MSR_ME|MSR_IP|MSR_RI -#else -#define MSR_ MSR_ME|MSR_RI -#endif - -#ifndef CONFIG_E500 -#define MSR_KERNEL MSR_|MSR_IR|MSR_DR -#else -#define MSR_KERNEL MSR_ME -#endif - -/* Floating Point Status and Control Register (FPSCR) Fields */ - -#define FPSCR_FX 0x80000000 /* FPU exception summary */ -#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ -#define FPSCR_VX 0x20000000 /* Invalid operation summary */ -#define FPSCR_OX 0x10000000 /* Overflow exception summary */ -#define FPSCR_UX 0x08000000 /* Underflow exception summary */ -#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ -#define FPSCR_XX 0x02000000 /* Inexact exception summary */ -#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ -#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ -#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ -#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ -#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ -#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ -#define FPSCR_FR 0x00040000 /* Fraction rounded */ -#define FPSCR_FI 0x00020000 /* Fraction inexact */ -#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ -#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ -#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ -#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ -#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ -#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ -#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ -#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ -#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ -#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ -#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ -#define FPSCR_RN 0x00000003 /* FPU rounding control */ - -/* Special Purpose Registers (SPRNs)*/ - -/* PPC440 Architecture is BOOK-E */ -#ifdef CONFIG_440 -#define CONFIG_BOOKE -#endif - -#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ -#ifdef CONFIG_BOOKE -#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ -#endif -#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ -#define SPRN_CTR 0x009 /* Count Register */ -#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ -#ifndef CONFIG_BOOKE -#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ -#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ -#else -#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ -#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DAR 0x013 /* Data Address Register */ -#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ -#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ -#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ -#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ -#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ -#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ -#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ -#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ -#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ -#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ -#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ -#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ -#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ -#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ -#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ -#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ -#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ -#define DBCR_EDM 0x80000000 -#define DBCR_IDM 0x40000000 -#define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 -#define DBCR_RST_SYSTEM 3 -#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ -#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ -#define DBCR_EDE 0x02000000 /* Exception Debug Event */ -#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ -#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ -#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ -#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ -#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ -#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ -#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ -#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ -#define DAC_BYTE 0 -#define DAC_HALF 1 -#define DAC_WORD 2 -#define DAC_QUAD 3 -#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ -#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ -#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ -#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ -#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ -#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ -#define DBCR_SIA 0x00000008 /* Second IAC Enable */ -#define DBCR_SDA 0x00000004 /* Second DAC Enable */ -#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ -#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ -#ifndef CONFIG_BOOKE -#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ -#else -#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ -#endif /* CONFIG_BOOKE */ -#ifndef CONFIG_BOOKE -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ -#else -#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ -#ifdef CONFIG_BOOKE -#define SPRN_DBDR 0x3f3 /* Debug Data Register */ -#endif -#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ -#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ -#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ -#define DCCR_NOCACHE 0 /* Noncacheable */ -#define DCCR_CACHE 1 /* Cacheable */ -#ifndef CONFIG_BOOKE -#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ -#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ -#endif -#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ -#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ -#define DCWR_COPY 0 /* Copy-back */ -#define DCWR_WRITE 1 /* Write-through */ -#ifndef CONFIG_BOOKE -#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ -#else -#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DEC 0x016 /* Decrement Register */ -#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ -#ifdef CONFIG_BOOKE -#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ -#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ -#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ -#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ -#endif -#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ -#ifdef CONFIG_BOOKE -#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ -#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ -#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ -#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ -#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ -#endif -#define SPRN_EAR 0x11A /* External Address Register */ -#ifndef CONFIG_BOOKE -#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ -#else -#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ -#endif /* CONFIG_BOOKE */ -#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ -#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ -#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ -#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ -#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ -#define ESR_PTR 0x02000000 /* Program Exception - Trap */ -#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ -#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ -#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ -#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ -#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ -#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ - -#define HID0_ICE_SHIFT 15 -#define HID0_DCE_SHIFT 14 -#define HID0_DLOCK_SHIFT 12 - -#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ -#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ -#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ -#define HID0_SBCLK (1<<27) -#define HID0_EICE (1<<26) -#define HID0_ECLK (1<<25) -#define HID0_PAR (1<<24) -#define HID0_DOZE (1<<23) -#define HID0_NAP (1<<22) -#define HID0_SLEEP (1<<21) -#define HID0_DPM (1<<20) -#define HID0_ICE (1<> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ - -#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ -#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ -#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ -#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ -#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ -#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ -#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ - -/* Processor Version Register */ - -/* Processor Version Register (PVR) field extraction */ - -#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ -#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ - -/* - * AMCC has further subdivided the standard PowerPC 16-bit version and - * revision subfields of the PVR for the PowerPC 403s into the following: - */ - -#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ -#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ -#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ -#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ -#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ -#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ - -/* e600 core PVR fields */ - -#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ -#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ -#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ -#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ - -/* Processor Version Numbers */ - -#define PVR_403GA 0x00200000 -#define PVR_403GB 0x00200100 -#define PVR_403GC 0x00200200 -#define PVR_403GCX 0x00201400 -#define PVR_405GP 0x40110000 -#define PVR_405GP_RB 0x40110040 -#define PVR_405GP_RC 0x40110082 -#define PVR_405GP_RD 0x401100C4 -#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ -#define PVR_405CR_RA 0x40110041 -#define PVR_405CR_RB 0x401100C5 -#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ -#define PVR_405EP_RA 0x51210950 -#define PVR_405GPR_RB 0x50910951 -#define PVR_405EZ_RA 0x41511460 -#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */ -#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ -#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ -#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */ -#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ -#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ -#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ -#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ -#define PVR_440GP_RB 0x40120440 -#define PVR_440GP_RC 0x40120481 -#define PVR_440EP_RA 0x42221850 -#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ -#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ -#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ -#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ -#define PVR_440GX_RA 0x51B21850 -#define PVR_440GX_RB 0x51B21851 -#define PVR_440GX_RC 0x51B21892 -#define PVR_440GX_RF 0x51B21894 -#define PVR_405EP_RB 0x51210950 -#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ -#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ -#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ -#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ -#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ -#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ -#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ -#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ -#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ -#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ -#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ -#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ -#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ -#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ -#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ -#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ -#define PVR_601 0x00010000 -#define PVR_602 0x00050000 -#define PVR_603 0x00030000 -#define PVR_603e 0x00060000 -#define PVR_603ev 0x00070000 -#define PVR_603r 0x00071000 -#define PVR_604 0x00040000 -#define PVR_604e 0x00090000 -#define PVR_604r 0x000A0000 -#define PVR_620 0x00140000 -#define PVR_740 0x00080000 -#define PVR_750 PVR_740 -#define PVR_740P 0x10080000 -#define PVR_750P PVR_740P -#define PVR_7400 0x000C0000 -#define PVR_7410 0x800C0000 -#define PVR_7450 0x80000000 - -#define PVR_85xx 0x80200000 -#define PVR_85xx_REV1 (PVR_85xx | 0x0010) -#define PVR_85xx_REV2 (PVR_85xx | 0x0020) - -#define PVR_86xx 0x80040000 - -#define PVR_VIRTEX5 0x7ff21912 - -/* - * For the 8xx processors, all of them report the same PVR family for - * the PowerPC core. The various versions of these processors must be - * differentiated by the version number in the Communication Processor - * Module (CPM). - */ -#define PVR_821 0x00500000 -#define PVR_823 PVR_821 -#define PVR_850 PVR_821 -#define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 -#define PVR_8240 0x00810100 - -/* - * PowerQUICC II family processors report different PVR values depending - * on silicon process (HiP3, HiP4, HiP7, etc.) - */ -#define PVR_8260 PVR_8240 -#define PVR_8260_HIP3 0x00810101 -#define PVR_8260_HIP4 0x80811014 -#define PVR_8260_HIP7 0x80822011 -#define PVR_8260_HIP7R1 0x80822013 -#define PVR_8260_HIP7RA 0x80822014 - -/* - * MPC 52xx - */ -#define PVR_5200 0x80822011 -#define PVR_5200B 0x80822014 - -/* - * System Version Register - */ - -/* System Version Register (SVR) field extraction */ - -#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ - -#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ - -#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ -#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ - -#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ -#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ - -/* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ - -/* whether MPC8xxxE (i.e. has SEC) */ -#if defined(CONFIG_MPC85xx) -#define IS_E_PROCESSOR(svr) (svr & 0x80000) -#else -#if defined(CONFIG_MPC83xx) -#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) -#endif -#endif - -/* - * SVR_SOC_VER() Version Values - */ - -#define SVR_8533 0x803400 -#define SVR_8533_E 0x803C00 -#define SVR_8535 0x803701 -#define SVR_8535_E 0x803F01 -#define SVR_8536 0x803700 -#define SVR_8536_E 0x803F00 -#define SVR_8540 0x803000 -#define SVR_8541 0x807200 -#define SVR_8541_E 0x807A00 -#define SVR_8543 0x803200 -#define SVR_8543_E 0x803A00 -#define SVR_8544 0x803401 -#define SVR_8544_E 0x803C01 -#define SVR_8545 0x803102 -#define SVR_8545_E 0x803902 -#define SVR_8547_E 0x803901 -#define SVR_8548 0x803100 -#define SVR_8548_E 0x803900 -#define SVR_8555 0x807100 -#define SVR_8555_E 0x807900 -#define SVR_8560 0x807000 -#define SVR_8567 0x807600 -#define SVR_8567_E 0x807E00 -#define SVR_8568 0x807500 -#define SVR_8568_E 0x807D00 -#define SVR_8569 0x808000 -#define SVR_8569_E 0x808800 -#define SVR_8572 0x80E000 -#define SVR_8572_E 0x80E800 -#define SVR_P2020 0x80E200 -#define SVR_P2020_E 0x80EA00 - -#define SVR_8610 0x80A000 -#define SVR_8641 0x809000 -#define SVR_8641D 0x809001 - -#define _GLOBAL(n)\ - .globl n;\ -n: - -/* Macros for setting and retrieving special purpose registers */ - -#define stringify(s) tostring(s) -#define tostring(s) #s - -#define mfdcr(rn) ({unsigned int rval; \ - asm volatile("mfdcr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) - -#define mfmsr() ({unsigned int rval; \ - asm volatile("mfmsr %0" : "=r" (rval)); rval;}) -#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) - -#define mfspr(rn) ({unsigned int rval; \ - asm volatile("mfspr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) - -#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) - -/* Segment Registers */ - -#define SR0 0 -#define SR1 1 -#define SR2 2 -#define SR3 3 -#define SR4 4 -#define SR5 5 -#define SR6 6 -#define SR7 7 -#define SR8 8 -#define SR9 9 -#define SR10 10 -#define SR11 11 -#define SR12 12 -#define SR13 13 -#define SR14 14 -#define SR15 15 - -#ifndef __ASSEMBLY__ - -struct cpu_type { - char name[15]; - u32 soc_ver; -}; - -struct cpu_type *identify_cpu(u32 ver); - -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) -#define CPU_TYPE_ENTRY(n, v) \ - { .name = #n, .soc_ver = SVR_##v, } -#else -#if defined(CONFIG_MPC83xx) -#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} -#endif -#endif - - -#ifndef CONFIG_MACH_SPECIFIC -extern int _machine; -extern int have_of; -#endif /* CONFIG_MACH_SPECIFIC */ - -/* what kind of prep workstation we are */ -extern int _prep_type; -/* - * This is used to identify the board type from a given PReP board - * vendor. Board revision is also made available. - */ -extern unsigned char ucSystemType; -extern unsigned char ucBoardRev; -extern unsigned char ucBoardRevMaj, ucBoardRevMin; - -struct task_struct; -void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); -void release_thread(struct task_struct *); - -/* - * Create a new kernel thread. - */ -extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -/* - * Bus types - */ -#define EISA_bus 0 -#define EISA_bus__is_a_macro /* for versions in ksyms.c */ -#define MCA_bus 0 -#define MCA_bus__is_a_macro /* for versions in ksyms.c */ - -/* Lazy FPU handling on uni-processor */ -extern struct task_struct *last_task_used_math; -extern struct task_struct *last_task_used_altivec; - -/* - * this is the minimum allowable io space due to the location - * of the io areas on prep (first one at 0x80000000) but - * as soon as I get around to remapping the io areas with the BATs - * to match the mac we can raise this. -- Cort - */ -#define TASK_SIZE (0x80000000UL) - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) - -typedef struct { - unsigned long seg; -} mm_segment_t; - -struct thread_struct { - unsigned long ksp; /* Kernel stack pointer */ - unsigned long wchan; /* Event task is sleeping on */ - struct pt_regs *regs; /* Pointer to saved register state */ - mm_segment_t fs; /* for get_fs() validation */ - void *pgdir; /* root of page-table tree */ - signed long last_syscall; - double fpr[32]; /* Complete floating point set */ - unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ - unsigned long fpscr; /* Floating point status */ -#ifdef CONFIG_ALTIVEC - vector128 vr[32]; /* Complete AltiVec set */ - vector128 vscr; /* AltiVec status */ - unsigned long vrsave; -#endif /* CONFIG_ALTIVEC */ -}; - -#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) - -#define INIT_THREAD { \ - INIT_SP, /* ksp */ \ - 0, /* wchan */ \ - (struct pt_regs *)INIT_SP - 1, /* regs */ \ - KERNEL_DS, /*fs*/ \ - swapper_pg_dir, /* pgdir */ \ - 0, /* last_syscall */ \ - {0}, 0, 0 \ -} - -/* - * Note: the vm_start and vm_end fields here should *not* - * be in kernel space. (Could vm_end == vm_start perhaps?) - */ -#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ - PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ - 1, NULL, NULL } - -/* - * Return saved PC of a blocked thread. For now, this is the "user" PC - */ -static inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - return (t->regs) ? t->regs->nip : 0; -} - -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) -#define forget_segments() do { } while (0) - -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) -#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) - -/* - * NOTE! The task struct and the stack go together - */ -#define THREAD_SIZE (2*PAGE_SIZE) -#define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) - -/* in process.c - for early bootup debug -- Cort */ -int ll_printk(const char *, ...); -void ll_puts(const char *); - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -/* In misc.c */ -void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); - -#endif /* ndef ASSEMBLY*/ - -#ifdef CONFIG_MACH_SPECIFIC -#if defined(CONFIG_8xx) -#define _machine _MACH_8xx -#define have_of 0 -#elif defined(CONFIG_OAK) -#define _machine _MACH_oak -#define have_of 0 -#elif defined(CONFIG_WALNUT) -#define _machine _MACH_walnut -#define have_of 0 -#elif defined(CONFIG_APUS) -#define _machine _MACH_apus -#define have_of 0 -#elif defined(CONFIG_GEMINI) -#define _machine _MACH_gemini -#define have_of 0 -#elif defined(CONFIG_8260) -#define _machine _MACH_8260 -#define have_of 0 -#elif defined(CONFIG_SANDPOINT) -#define _machine _MACH_sandpoint -#elif defined(CONFIG_HIDDEN_DRAGON) -#define _machine _MACH_hidden_dragon -#define have_of 0 -#else -#error "Machine not defined correctly" -#endif -#endif /* CONFIG_MACH_SPECIFIC */ - -#endif /* __ASM_PPC_PROCESSOR_H */ +#ifndef __ASM_PPC_PROCESSOR_H +#define __ASM_PPC_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#include + +#include +#include + +/* Machine State Register (MSR) Fields */ + +#ifdef CONFIG_PPC64BRIDGE +#define MSR_SF (1<<63) +#define MSR_ISF (1<<61) +#endif /* CONFIG_PPC64BRIDGE */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ +#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ +#define MSR_SPE (1<<25) /* Enable SPE(e500) */ +#define MSR_POW (1<<18) /* Enable Power Management */ +#define MSR_WE (1<<18) /* Wait State Enable */ +#define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ +#define MSR_ILE (1<<16) /* Interrupt Little Endian */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_PR (1<<14) /* Problem State / Privilege Level */ +#define MSR_FP (1<<13) /* Floating Point enable */ +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ +#define MSR_SE (1<<10) /* Single Step */ +#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ +#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ +#define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ +#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ +#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IS (1<<5) /* Book E Instruction space */ +#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DS (1<<4) /* Book E Data space */ +#define MSR_PE (1<<3) /* Protection Enable */ +#define MSR_PX (1<<2) /* Protection Exclusive Mode */ +#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ +#define MSR_RI (1<<1) /* Recoverable Exception */ +#define MSR_LE (1<<0) /* Little Endian */ + +#ifdef CONFIG_APUS_FAST_EXCEPT +#define MSR_ MSR_ME|MSR_IP|MSR_RI +#else +#define MSR_ MSR_ME|MSR_RI +#endif + +#ifndef CONFIG_E500 +#define MSR_KERNEL MSR_|MSR_IR|MSR_DR +#else +#define MSR_KERNEL MSR_ME +#endif + +/* Floating Point Status and Control Register (FPSCR) Fields */ + +#define FPSCR_FX 0x80000000 /* FPU exception summary */ +#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ +#define FPSCR_VX 0x20000000 /* Invalid operation summary */ +#define FPSCR_OX 0x10000000 /* Overflow exception summary */ +#define FPSCR_UX 0x08000000 /* Underflow exception summary */ +#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ +#define FPSCR_XX 0x02000000 /* Inexact exception summary */ +#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ +#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ +#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ +#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ +#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ +#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ +#define FPSCR_FR 0x00040000 /* Fraction rounded */ +#define FPSCR_FI 0x00020000 /* Fraction inexact */ +#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ +#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ +#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ +#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ +#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ +#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ +#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ +#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ +#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ +#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ +#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ +#define FPSCR_RN 0x00000003 /* FPU rounding control */ + +/* Special Purpose Registers (SPRNs)*/ + +/* PPC440 Architecture is BOOK-E */ +#ifdef CONFIG_440 +#define CONFIG_BOOKE +#endif + +#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#ifdef CONFIG_BOOKE +#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ +#endif +#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ +#define SPRN_CTR 0x009 /* Count Register */ +#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ +#ifndef CONFIG_BOOKE +#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ +#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#else +#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ +#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DAR 0x013 /* Data Address Register */ +#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ +#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ +#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ +#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ +#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ +#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ +#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ +#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ +#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ +#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ +#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ +#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ +#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ +#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ +#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ +#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ +#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ +#define DBCR_EDM 0x80000000 +#define DBCR_IDM 0x40000000 +#define DBCR_RST(x) (((x) & 0x3) << 28) +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 +#define DBCR_RST_SYSTEM 3 +#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ +#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ +#define DBCR_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ +#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ +#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ +#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ +#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ +#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ +#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ +#define DAC_BYTE 0 +#define DAC_HALF 1 +#define DAC_WORD 2 +#define DAC_QUAD 3 +#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ +#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ +#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ +#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ +#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ +#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ +#define DBCR_SIA 0x00000008 /* Second IAC Enable */ +#define DBCR_SDA 0x00000004 /* Second DAC Enable */ +#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ +#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#ifndef CONFIG_BOOKE +#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ +#else +#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ +#endif /* CONFIG_BOOKE */ +#ifndef CONFIG_BOOKE +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#else +#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_DBDR 0x3f3 /* Debug Data Register */ +#endif +#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ +#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ +#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ +#define DCCR_NOCACHE 0 /* Noncacheable */ +#define DCCR_CACHE 1 /* Cacheable */ +#ifndef CONFIG_BOOKE +#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ +#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ +#endif +#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ +#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ +#define DCWR_COPY 0 /* Copy-back */ +#define DCWR_WRITE 1 /* Write-through */ +#ifndef CONFIG_BOOKE +#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ +#else +#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DEC 0x016 /* Decrement Register */ +#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ +#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ +#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ +#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ +#endif +#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ +#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ +#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ +#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ +#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ +#endif +#define SPRN_EAR 0x11A /* External Address Register */ +#ifndef CONFIG_BOOKE +#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#else +#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ +#endif /* CONFIG_BOOKE */ +#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ +#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ +#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ +#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ +#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ +#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PTR 0x02000000 /* Program Exception - Trap */ +#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ +#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ +#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ +#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ +#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ +#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ + +#define HID0_ICE_SHIFT 15 +#define HID0_DCE_SHIFT 14 +#define HID0_DLOCK_SHIFT 12 + +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_EICE (1<<26) +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_DOZE (1<<23) +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_ICE (1<> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ + +#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ +#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ +#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ +#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ +#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ +#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ +#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ + +/* Processor Version Register */ + +/* Processor Version Register (PVR) field extraction */ + +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ + +/* + * AMCC has further subdivided the standard PowerPC 16-bit version and + * revision subfields of the PVR for the PowerPC 403s into the following: + */ + +#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ +#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ +#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ +#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ + +/* e600 core PVR fields */ + +#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ +#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ +#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ +#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ + +/* Processor Version Numbers */ + +#define PVR_403GA 0x00200000 +#define PVR_403GB 0x00200100 +#define PVR_403GC 0x00200200 +#define PVR_403GCX 0x00201400 +#define PVR_405GP 0x40110000 +#define PVR_405GP_RB 0x40110040 +#define PVR_405GP_RC 0x40110082 +#define PVR_405GP_RD 0x401100C4 +#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ +#define PVR_405CR_RA 0x40110041 +#define PVR_405CR_RB 0x401100C5 +#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ +#define PVR_405EP_RA 0x51210950 +#define PVR_405GPR_RB 0x50910951 +#define PVR_405EZ_RA 0x41511460 +#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */ +#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ +#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ +#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */ +#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ +#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ +#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ +#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ +#define PVR_440GP_RB 0x40120440 +#define PVR_440GP_RC 0x40120481 +#define PVR_440EP_RA 0x42221850 +#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ +#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ +#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ +#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ +#define PVR_440GX_RA 0x51B21850 +#define PVR_440GX_RB 0x51B21851 +#define PVR_440GX_RC 0x51B21892 +#define PVR_440GX_RF 0x51B21894 +#define PVR_405EP_RB 0x51210950 +#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ +#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ +#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ +#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ +#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ +#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ +#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ +#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ +#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ +#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ +#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ +#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ +#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ +#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ +#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_601 0x00010000 +#define PVR_602 0x00050000 +#define PVR_603 0x00030000 +#define PVR_603e 0x00060000 +#define PVR_603ev 0x00070000 +#define PVR_603r 0x00071000 +#define PVR_604 0x00040000 +#define PVR_604e 0x00090000 +#define PVR_604r 0x000A0000 +#define PVR_620 0x00140000 +#define PVR_740 0x00080000 +#define PVR_750 PVR_740 +#define PVR_740P 0x10080000 +#define PVR_750P PVR_740P +#define PVR_7400 0x000C0000 +#define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 + +#define PVR_85xx 0x80200000 +#define PVR_85xx_REV1 (PVR_85xx | 0x0010) +#define PVR_85xx_REV2 (PVR_85xx | 0x0020) + +#define PVR_86xx 0x80040000 + +#define PVR_VIRTEX5 0x7ff21912 + +/* + * For the 8xx processors, all of them report the same PVR family for + * the PowerPC core. The various versions of these processors must be + * differentiated by the version number in the Communication Processor + * Module (CPM). + */ +#define PVR_821 0x00500000 +#define PVR_823 PVR_821 +#define PVR_850 PVR_821 +#define PVR_860 PVR_821 +#define PVR_7400 0x000C0000 +#define PVR_8240 0x00810100 + +/* + * PowerQUICC II family processors report different PVR values depending + * on silicon process (HiP3, HiP4, HiP7, etc.) + */ +#define PVR_8260 PVR_8240 +#define PVR_8260_HIP3 0x00810101 +#define PVR_8260_HIP4 0x80811014 +#define PVR_8260_HIP7 0x80822011 +#define PVR_8260_HIP7R1 0x80822013 +#define PVR_8260_HIP7RA 0x80822014 + +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + +/* + * System Version Register + */ + +/* System Version Register (SVR) field extraction */ + +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ + +#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ + +#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ +#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ + +/* Some parts define SVR[0:23] as the SOC version */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ + +/* whether MPC8xxxE (i.e. has SEC) */ +#if defined(CONFIG_MPC85xx) +#define IS_E_PROCESSOR(svr) (svr & 0x80000) +#else +#if defined(CONFIG_MPC83xx) +#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) +#endif +#endif + +/* + * SVR_SOC_VER() Version Values + */ + +#define SVR_8533 0x803400 +#define SVR_8533_E 0x803C00 +#define SVR_8535 0x803701 +#define SVR_8535_E 0x803F01 +#define SVR_8536 0x803700 +#define SVR_8536_E 0x803F00 +#define SVR_8540 0x803000 +#define SVR_8541 0x807200 +#define SVR_8541_E 0x807A00 +#define SVR_8543 0x803200 +#define SVR_8543_E 0x803A00 +#define SVR_8544 0x803401 +#define SVR_8544_E 0x803C01 +#define SVR_8545 0x803102 +#define SVR_8545_E 0x803902 +#define SVR_8547_E 0x803901 +#define SVR_8548 0x803100 +#define SVR_8548_E 0x803900 +#define SVR_8555 0x807100 +#define SVR_8555_E 0x807900 +#define SVR_8560 0x807000 +#define SVR_8567 0x807600 +#define SVR_8567_E 0x807E00 +#define SVR_8568 0x807500 +#define SVR_8568_E 0x807D00 +#define SVR_8569 0x808000 +#define SVR_8569_E 0x808800 +#define SVR_8572 0x80E000 +#define SVR_8572_E 0x80E800 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 + +#define SVR_8610 0x80A000 +#define SVR_8641 0x809000 +#define SVR_8641D 0x809001 + +#define _GLOBAL(n)\ + .globl n;\ +n: + +/* Macros for setting and retrieving special purpose registers */ + +#define stringify(s) tostring(s) +#define tostring(s) #s + +#define mfdcr(rn) ({unsigned int rval; \ + asm volatile("mfdcr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) + +#define mfmsr() ({unsigned int rval; \ + asm volatile("mfmsr %0" : "=r" (rval)); rval;}) +#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) + +#define mfspr(rn) ({unsigned int rval; \ + asm volatile("mfspr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) + +#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) + +/* Segment Registers */ + +#define SR0 0 +#define SR1 1 +#define SR2 2 +#define SR3 3 +#define SR4 4 +#define SR5 5 +#define SR6 6 +#define SR7 7 +#define SR8 8 +#define SR9 9 +#define SR10 10 +#define SR11 11 +#define SR12 12 +#define SR13 13 +#define SR14 14 +#define SR15 15 + +#ifndef __ASSEMBLY__ + +struct cpu_type { + char name[15]; + u32 soc_ver; +}; + +struct cpu_type *identify_cpu(u32 ver); + +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) +#define CPU_TYPE_ENTRY(n, v) \ + { .name = #n, .soc_ver = SVR_##v, } +#else +#if defined(CONFIG_MPC83xx) +#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} +#endif +#endif + + +#ifndef CONFIG_MACH_SPECIFIC +extern int _machine; +extern int have_of; +#endif /* CONFIG_MACH_SPECIFIC */ + +/* what kind of prep workstation we are */ +extern int _prep_type; +/* + * This is used to identify the board type from a given PReP board + * vendor. Board revision is also made available. + */ +extern unsigned char ucSystemType; +extern unsigned char ucBoardRev; +extern unsigned char ucBoardRevMaj, ucBoardRevMin; + +struct task_struct; +void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); +void release_thread(struct task_struct *); + +/* + * Create a new kernel thread. + */ +extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +/* + * Bus types + */ +#define EISA_bus 0 +#define EISA_bus__is_a_macro /* for versions in ksyms.c */ +#define MCA_bus 0 +#define MCA_bus__is_a_macro /* for versions in ksyms.c */ + +/* Lazy FPU handling on uni-processor */ +extern struct task_struct *last_task_used_math; +extern struct task_struct *last_task_used_altivec; + +/* + * this is the minimum allowable io space due to the location + * of the io areas on prep (first one at 0x80000000) but + * as soon as I get around to remapping the io areas with the BATs + * to match the mac we can raise this. -- Cort + */ +#define TASK_SIZE (0x80000000UL) + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) + +typedef struct { + unsigned long seg; +} mm_segment_t; + +struct thread_struct { + unsigned long ksp; /* Kernel stack pointer */ + unsigned long wchan; /* Event task is sleeping on */ + struct pt_regs *regs; /* Pointer to saved register state */ + mm_segment_t fs; /* for get_fs() validation */ + void *pgdir; /* root of page-table tree */ + signed long last_syscall; + double fpr[32]; /* Complete floating point set */ + unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ + unsigned long fpscr; /* Floating point status */ +#ifdef CONFIG_ALTIVEC + vector128 vr[32]; /* Complete AltiVec set */ + vector128 vscr; /* AltiVec status */ + unsigned long vrsave; +#endif /* CONFIG_ALTIVEC */ +}; + +#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) + +#define INIT_THREAD { \ + INIT_SP, /* ksp */ \ + 0, /* wchan */ \ + (struct pt_regs *)INIT_SP - 1, /* regs */ \ + KERNEL_DS, /*fs*/ \ + swapper_pg_dir, /* pgdir */ \ + 0, /* last_syscall */ \ + {0}, 0, 0 \ +} + +/* + * Note: the vm_start and vm_end fields here should *not* + * be in kernel space. (Could vm_end == vm_start perhaps?) + */ +#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ + PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ + 1, NULL, NULL } + +/* + * Return saved PC of a blocked thread. For now, this is the "user" PC + */ +static inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + return (t->regs) ? t->regs->nip : 0; +} + +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) +#define forget_segments() do { } while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) +#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) + +/* + * NOTE! The task struct and the stack go together + */ +#define THREAD_SIZE (2*PAGE_SIZE) +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) + +/* in process.c - for early bootup debug -- Cort */ +int ll_printk(const char *, ...); +void ll_puts(const char *); + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +/* In misc.c */ +void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); + +#endif /* ndef ASSEMBLY*/ + +#ifdef CONFIG_MACH_SPECIFIC +#if defined(CONFIG_8xx) +#define _machine _MACH_8xx +#define have_of 0 +#elif defined(CONFIG_OAK) +#define _machine _MACH_oak +#define have_of 0 +#elif defined(CONFIG_WALNUT) +#define _machine _MACH_walnut +#define have_of 0 +#elif defined(CONFIG_APUS) +#define _machine _MACH_apus +#define have_of 0 +#elif defined(CONFIG_GEMINI) +#define _machine _MACH_gemini +#define have_of 0 +#elif defined(CONFIG_8260) +#define _machine _MACH_8260 +#define have_of 0 +#elif defined(CONFIG_SANDPOINT) +#define _machine _MACH_sandpoint +#elif defined(CONFIG_HIDDEN_DRAGON) +#define _machine _MACH_hidden_dragon +#define have_of 0 +#else +#error "Machine not defined correctly" +#endif +#endif /* CONFIG_MACH_SPECIFIC */ + +#endif /* __ASM_PPC_PROCESSOR_H */ diff --git a/libcpu/ppc/ppc405/include/asm/ptrace.h b/libcpu/ppc/ppc405/include/asm/ptrace.h index 8019543ab11b9307ea0c6f6e5a5abdf4def4d3b5..d531de889bf42822abc156b397c447a641c04688 100644 --- a/libcpu/ppc/ppc405/include/asm/ptrace.h +++ b/libcpu/ppc/ppc405/include/asm/ptrace.h @@ -1,107 +1,107 @@ -#ifndef _PPC_PTRACE_H -#define _PPC_PTRACE_H - -/* - * This struct defines the way the registers are stored on the - * kernel stack during a system call or other kernel entry. - * - * this should only contain volatile regs - * since we can keep non-volatile in the thread_struct - * should set this up when only volatiles are saved - * by intr code. - * - * Since this is going on the stack, *CARE MUST BE TAKEN* to insure - * that the overall structure is a multiple of 16 bytes in length. - * - * Note that the offsets of the fields in this struct correspond with - * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. - */ - -#include - -#ifndef __ASSEMBLY__ -#ifdef CONFIG_PPC64BRIDGE -#define PPC_REG unsigned long /*long*/ -#else -#define PPC_REG unsigned long -#endif -struct pt_regs { - PPC_REG gpr[32]; - PPC_REG nip; - PPC_REG msr; - PPC_REG orig_gpr3; /* Used for restarting system calls */ - PPC_REG ctr; - PPC_REG link; - PPC_REG xer; - PPC_REG ccr; - PPC_REG mq; /* 601 only (not used at present) */ - /* Used on APUS to hold IPL value. */ - PPC_REG trap; /* Reason for being here */ - PPC_REG dar; /* Fault registers */ - PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ -}__attribute__((packed)) CELL_STACK_FRAME_t; -#endif - -#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ - -/* Size of stack frame allocated when calling signal handler. */ -#define __SIGNAL_FRAMESIZE 64 - -#define instruction_pointer(regs) ((regs)->nip) -#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) - -/* - * Offsets used by 'ptrace' system call interface. - * These can't be changed without breaking binary compatibility - * with MkLinux, etc. - */ -#define PT_R0 0 -#define PT_R1 1 -#define PT_R2 2 -#define PT_R3 3 -#define PT_R4 4 -#define PT_R5 5 -#define PT_R6 6 -#define PT_R7 7 -#define PT_R8 8 -#define PT_R9 9 -#define PT_R10 10 -#define PT_R11 11 -#define PT_R12 12 -#define PT_R13 13 -#define PT_R14 14 -#define PT_R15 15 -#define PT_R16 16 -#define PT_R17 17 -#define PT_R18 18 -#define PT_R19 19 -#define PT_R20 20 -#define PT_R21 21 -#define PT_R22 22 -#define PT_R23 23 -#define PT_R24 24 -#define PT_R25 25 -#define PT_R26 26 -#define PT_R27 27 -#define PT_R28 28 -#define PT_R29 29 -#define PT_R30 30 -#define PT_R31 31 - -#define PT_NIP 32 -#define PT_MSR 33 -#ifdef __KERNEL__ -#define PT_ORIG_R3 34 -#endif -#define PT_CTR 35 -#define PT_LNK 36 -#define PT_XER 37 -#define PT_CCR 38 -#define PT_MQ 39 - -#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ -#define PT_FPR31 (PT_FPR0 + 2*31) -#define PT_FPSCR (PT_FPR0 + 2*32 + 1) - -#endif +#ifndef _PPC_PTRACE_H +#define _PPC_PTRACE_H + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + * + * this should only contain volatile regs + * since we can keep non-volatile in the thread_struct + * should set this up when only volatiles are saved + * by intr code. + * + * Since this is going on the stack, *CARE MUST BE TAKEN* to insure + * that the overall structure is a multiple of 16 bytes in length. + * + * Note that the offsets of the fields in this struct correspond with + * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. + */ + +#include + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_PPC64BRIDGE +#define PPC_REG unsigned long /*long*/ +#else +#define PPC_REG unsigned long +#endif +struct pt_regs { + PPC_REG gpr[32]; + PPC_REG nip; + PPC_REG msr; + PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG ctr; + PPC_REG link; + PPC_REG xer; + PPC_REG ccr; + PPC_REG mq; /* 601 only (not used at present) */ + /* Used on APUS to hold IPL value. */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ + PPC_REG dsisr; + PPC_REG result; /* Result of a system call */ +}__attribute__((packed)) CELL_STACK_FRAME_t; +#endif + +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ + +/* Size of stack frame allocated when calling signal handler. */ +#define __SIGNAL_FRAMESIZE 64 + +#define instruction_pointer(regs) ((regs)->nip) +#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) + +/* + * Offsets used by 'ptrace' system call interface. + * These can't be changed without breaking binary compatibility + * with MkLinux, etc. + */ +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 + +#define PT_NIP 32 +#define PT_MSR 33 +#ifdef __KERNEL__ +#define PT_ORIG_R3 34 +#endif +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 + +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR31 (PT_FPR0 + 2*31) +#define PT_FPSCR (PT_FPR0 + 2*32 + 1) + +#endif diff --git a/libcpu/ppc/ppc405/include/asm/types.h b/libcpu/ppc/ppc405/include/asm/types.h index ac4133ffd4c9be40da2ea370443cd1c12970f714..6413895325e48021cd827058de89bfc7aa599b1b 100644 --- a/libcpu/ppc/ppc405/include/asm/types.h +++ b/libcpu/ppc/ppc405/include/asm/types.h @@ -1,74 +1,74 @@ -#ifndef _PPC_TYPES_H -#define _PPC_TYPES_H - - -#ifndef __ASSEMBLY__ - -typedef enum bool - { - FALSE = 0, - TRUE = 1 - }BOOL; - -typedef unsigned short umode_t; - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -typedef struct { - __u32 u[4]; -} __attribute__((aligned(16))) vector128; - -#ifdef __KERNEL__ -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -typedef char INT8; -typedef short INT16; -typedef int INT32; -typedef long long INT64; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef unsigned long long UINT64; - -#define BITS_PER_LONG 32 - -/* DMA addresses are 32-bits wide */ -typedef u32 dma_addr_t; - -#ifdef CONFIG_PHYS_64BIT -typedef unsigned long long phys_addr_t; -typedef unsigned long long phys_size_t; -#else -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; -#endif - -#endif /* __KERNEL__ */ -#endif /* __ASSEMBLY__ */ - -#endif +#ifndef _PPC_TYPES_H +#define _PPC_TYPES_H + + +#ifndef __ASSEMBLY__ + +typedef enum bool + { + FALSE = 0, + TRUE = 1 + }BOOL; + +typedef unsigned short umode_t; + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +typedef struct { + __u32 u[4]; +} __attribute__((aligned(16))) vector128; + +#ifdef __KERNEL__ +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +typedef char INT8; +typedef short INT16; +typedef int INT32; +typedef long long INT64; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; + +#define BITS_PER_LONG 32 + +/* DMA addresses are 32-bits wide */ +typedef u32 dma_addr_t; + +#ifdef CONFIG_PHYS_64BIT +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; +#else +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; +#endif + +#endif /* __KERNEL__ */ +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/libcpu/ppc/ppc405/include/config.h b/libcpu/ppc/ppc405/include/config.h index 55a930aa89367731b76ba554138add3ad708ccc6..dc01549b01e364394e67d570d1c2acebb342b078 100644 --- a/libcpu/ppc/ppc405/include/config.h +++ b/libcpu/ppc/ppc405/include/config.h @@ -1,58 +1,58 @@ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ - -#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ - -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */ -#define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */ -#define CONFIG_SYS_HZ 100 -#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -/* - * UART - */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* - * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - */ -#define CONFIG_SYS_FLASH_BASE 0xFFE00000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_ADDR0 0x555 -#define CONFIG_SYS_FLASH_ADDR1 0x2aa -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short - -#endif /* __CONFIG_H */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_405EP 1 /* this is a PPC405 CPU */ +#define CONFIG_4xx 1 /* member of PPC4xx family */ + +#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + +#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */ +#define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */ +#define CONFIG_SYS_HZ 100 +#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) + +/* + * UART + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* + * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#define CONFIG_SYS_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE 1 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + */ +#define CONFIG_SYS_FLASH_BASE 0xFFE00000 + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CONFIG_SYS_FLASH_ADDR0 0x555 +#define CONFIG_SYS_FLASH_ADDR1 0x2aa +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short + +#endif /* __CONFIG_H */ diff --git a/libcpu/ppc/ppc405/interrupt.c b/libcpu/ppc/ppc405/interrupt.c index 6edb81739f7ea71b262bacfcc406f51b9dab01aa..d0e174612cded881b32b374ef488c1a889a17cdc 100644 --- a/libcpu/ppc/ppc405/interrupt.c +++ b/libcpu/ppc/ppc405/interrupt.c @@ -1,133 +1,133 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first version - */ - -#include -#include -#include - -/* interrupt nest */ -extern volatile rt_uint8_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -#define MAX_HANDLERS 32 -rt_isr_handler_t isr_table[MAX_HANDLERS]; - -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrput_flag; - -rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; -} - -void uic_irq_ack(unsigned int vec) -{ - mtdcr(uic0sr, UIC_MASK(vec)); -} - -void uic_int_handler (unsigned int vec) -{ - rt_interrupt_enter(); - - /* Allow external interrupts to the CPU. */ - if (isr_table [vec] != 0) - { - (*isr_table[vec])(vec); - } - uic_irq_ack(vec); - - rt_interrupt_leave(); -} - -/* handler for UIC interrupt */ -void uic_interrupt(rt_uint32_t uic_base, int vec_base) -{ - int vec; - rt_uint32_t uic_msr; - rt_uint32_t msr_shift; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic_msr = get_dcr(uic_base + UIC_MSR); - msr_shift = uic_msr; - vec = vec_base; - - while (msr_shift != 0) - { - if (msr_shift & 0x80000000) - uic_int_handler(vec); - - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } -} - -void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) -{ - int intVal; - - if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS)) - { - return; /* out of range */ - } - - /* install the handler in the system interrupt table */ - intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */ - - if (*old_handler != RT_NULL) *old_handler = isr_table[vector]; - if (new_handler != RT_NULL) isr_table[vector] = new_handler; - - rt_hw_interrupt_enable (intVal); -} - -void rt_hw_interrupt_mask(int vector) -{ - mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector)); -} - -void rt_hw_interrupt_unmask(int vector) -{ - mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector)); -} - -void rt_hw_interrupt_init() -{ - int vector; - rt_uint32_t pit_value; - - pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ); - - /* enable pit */ - mtspr(SPRN_PIT, pit_value); - mtspr(SPRN_TCR, 0x4400000); - - /* set default interrupt handler */ - for (vector = 0; vector < MAX_HANDLERS; vector++) - { - isr_table [vector] = (rt_isr_handler_t)rt_hw_interrupt_handle; - } - - /* initialize interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrput_flag = 0; -} - -/*@}*/ +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first version + */ + +#include +#include +#include + +/* interrupt nest */ +extern volatile rt_uint8_t rt_interrupt_nest; + +/* exception and interrupt handler table */ +#define MAX_HANDLERS 32 +rt_isr_handler_t isr_table[MAX_HANDLERS]; + +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrput_flag; + +rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; +} + +void uic_irq_ack(unsigned int vec) +{ + mtdcr(uic0sr, UIC_MASK(vec)); +} + +void uic_int_handler (unsigned int vec) +{ + rt_interrupt_enter(); + + /* Allow external interrupts to the CPU. */ + if (isr_table [vec] != 0) + { + (*isr_table[vec])(vec); + } + uic_irq_ack(vec); + + rt_interrupt_leave(); +} + +/* handler for UIC interrupt */ +void uic_interrupt(rt_uint32_t uic_base, int vec_base) +{ + int vec; + rt_uint32_t uic_msr; + rt_uint32_t msr_shift; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = get_dcr(uic_base + UIC_MSR); + msr_shift = uic_msr; + vec = vec_base; + + while (msr_shift != 0) + { + if (msr_shift & 0x80000000) + uic_int_handler(vec); + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} + +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + int intVal; + + if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS)) + { + return; /* out of range */ + } + + /* install the handler in the system interrupt table */ + intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */ + + if (*old_handler != RT_NULL) *old_handler = isr_table[vector]; + if (new_handler != RT_NULL) isr_table[vector] = new_handler; + + rt_hw_interrupt_enable (intVal); +} + +void rt_hw_interrupt_mask(int vector) +{ + mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector)); +} + +void rt_hw_interrupt_unmask(int vector) +{ + mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector)); +} + +void rt_hw_interrupt_init() +{ + int vector; + rt_uint32_t pit_value; + + pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ); + + /* enable pit */ + mtspr(SPRN_PIT, pit_value); + mtspr(SPRN_TCR, 0x4400000); + + /* set default interrupt handler */ + for (vector = 0; vector < MAX_HANDLERS; vector++) + { + isr_table [vector] = (rt_isr_handler_t)rt_hw_interrupt_handle; + } + + /* initialize interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrput_flag = 0; +} + +/*@}*/ diff --git a/libcpu/ppc/ppc405/io.h b/libcpu/ppc/ppc405/io.h index 917cb5e3df1dc8405e550d19e3af1bf5173c3dce..32fcd5630737311898ebd344424df17938011cbb 100644 --- a/libcpu/ppc/ppc405/io.h +++ b/libcpu/ppc/ppc405/io.h @@ -1,93 +1,93 @@ -#ifndef __IO_H__ -#define __IO_H__ - -#define __iomem - -/* - * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - * - * Read operations have additional twi & isync to make sure the read - * is actually performed (i.e. the data has come back) before we start - * executing any following instructions. - */ -static inline int in_8(const volatile unsigned char __iomem *addr) -{ - int ret; - - __asm__ __volatile__( - "sync; lbz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -static inline void out_8(volatile unsigned char __iomem *addr, int val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -extern inline int in_le16(const volatile unsigned short __iomem *addr) -{ - int ret; - - __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline int in_be16(const volatile unsigned short __iomem *addr) -{ - int ret; - - __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le16(volatile unsigned short __iomem *addr, int val) -{ - __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be16(volatile unsigned short __iomem *addr, int val) -{ - __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); -} - -extern inline unsigned in_le32(const volatile unsigned __iomem *addr) -{ - unsigned ret; - - __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline unsigned in_be32(const volatile unsigned __iomem *addr) -{ - unsigned ret; - - __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le32(volatile unsigned __iomem *addr, int val) -{ - __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be32(volatile unsigned __iomem *addr, int val) -{ - __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); -} - -#endif +#ifndef __IO_H__ +#define __IO_H__ + +#define __iomem + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + * + * Read operations have additional twi & isync to make sure the read + * is actually performed (i.e. the data has come back) before we start + * executing any following instructions. + */ +static inline int in_8(const volatile unsigned char __iomem *addr) +{ + int ret; + + __asm__ __volatile__( + "sync; lbz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +static inline void out_8(volatile unsigned char __iomem *addr, int val) +{ + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +extern inline int in_le16(const volatile unsigned short __iomem *addr) +{ + int ret; + + __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline int in_be16(const volatile unsigned short __iomem *addr) +{ + int ret; + + __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le16(volatile unsigned short __iomem *addr, int val) +{ + __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be16(volatile unsigned short __iomem *addr, int val) +{ + __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); +} + +extern inline unsigned in_le32(const volatile unsigned __iomem *addr) +{ + unsigned ret; + + __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline unsigned in_be32(const volatile unsigned __iomem *addr) +{ + unsigned ret; + + __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le32(volatile unsigned __iomem *addr, int val) +{ + __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be32(volatile unsigned __iomem *addr, int val) +{ + __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); +} + +#endif diff --git a/libcpu/ppc/ppc405/serial.c b/libcpu/ppc/ppc405/serial.c index 4c1a605adc68930855d323888bd3df99ea1b2ee6..ca935fafddc0f39615cf3dc8319387a82165ca36 100644 --- a/libcpu/ppc/ppc405/serial.c +++ b/libcpu/ppc/ppc405/serial.c @@ -1,319 +1,319 @@ -#include -#include - -#include "io.h" -#include - -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 -#define UCR0_MASK 0x0000007f -#define UCR1_MASK 0x00007f00 -#define UCR0_UDIV_POS 0 -#define UCR1_UDIV_POS 8 -#define UDIV_MAX 127 - -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncLSRDataReady1 0x01 -#define asyncLSROverrunError1 0x02 -#define asyncLSRParityError1 0x04 -#define asyncLSRFramingError1 0x08 -#define asyncLSRBreakInterrupt1 0x10 -#define asyncLSRTxHoldEmpty1 0x20 -#define asyncLSRTxShiftEmpty1 0x40 -#define asyncLSRRxFifoError1 0x80 - -/* PPC405 serial device */ -struct rt_ppc405_serial -{ - /* inherit from device */ - struct rt_device parent; - - rt_uint32_t hw_base; - rt_uint32_t irqno; - rt_uint32_t baudrate; - - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; -}; -struct rt_ppc405_serial ppc405_serial; - -/* serial character device */ -static rt_err_t rt_serial_init (rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - struct rt_ppc405_serial* device; - device = (struct rt_ppc405_serial*) dev; - - RT_ASSERT(device != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Enable "RX Data Available" Interrupt on UART */ - out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01); - /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ - out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1); - - /* init UART rx interrupt */ - rt_hw_interrupt_unmask(device->irqno); - } - - return RT_EOK; -} - -static rt_err_t rt_serial_close(rt_device_t dev) -{ - struct rt_ppc405_serial* device; - device = (struct rt_ppc405_serial*) dev; - - RT_ASSERT(device != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* mask UART rx interrupt */ - rt_hw_interrupt_mask(device->irqno); - } - - return RT_EOK; -} - -static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args) -{ - return RT_EOK; -} - -static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - struct rt_ppc405_serial* device; - - device = (struct rt_ppc405_serial*) dev; - RT_ASSERT(device != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (device->read_index != device->save_index) - { - *ptr = device->rx_buffer[device->read_index]; - - device->read_index ++; - if (device->read_index >= RT_UART_RX_BUFFER_SIZE) - device->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - - /* polling mode */ - RT_ASSERT(0); - - return (rt_size_t)ptr - (rt_size_t)buffer; -} - -static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - char *ptr; - struct rt_ppc405_serial* device; - - device = (struct rt_ppc405_serial*) dev; - RT_ASSERT(device != RT_NULL); - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* not support */ - RT_ASSERT(0); - } - - /* polling write */ - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); - out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r'); - } - - while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); - out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); - - ptr ++; - size --; - } - } - else - { - while (size) - { - while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); - out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); - - ptr ++; - size --; - } - } - - return (rt_size_t) ptr - (rt_size_t) buffer; -} - -void rt_serial_set_baudrate(struct rt_ppc405_serial* device) -{ - rt_uint32_t bdiv; - - bdiv = 115200; - out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */ - out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ -} - -void rt_serial_isr(int irqno) -{ - unsigned char status; - struct rt_ppc405_serial *device; - - device = (struct rt_ppc405_serial*) &ppc405_serial; - status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); - - if (status & 0x01) - { - rt_base_t level; - - while (status & 0x01) - { - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* read character */ - device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base)); - device->save_index ++; - if (device->save_index >= RT_UART_RX_BUFFER_SIZE) - device->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (device->save_index == device->read_index) - { - device->read_index ++; - if (device->read_index >= RT_UART_RX_BUFFER_SIZE) - device->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - /* check error */ - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) - { - out_8((rt_uint8_t *)device->hw_base + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - - status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); - } - - /* invoke callback */ - if(device->parent.rx_indicate != RT_NULL) - { - device->parent.rx_indicate(&device->parent, 1); - } - } -} - -void rt_hw_serial_init(void) -{ - volatile rt_uint8_t val; - struct rt_ppc405_serial* device; - - device = (struct rt_ppc405_serial*) &ppc405_serial; - device->parent.type = RT_Device_Class_Char; - - device->hw_base = UART0_BASE; - device->baudrate = 115200; - device->irqno = VECNUM_U0; - rt_hw_interrupt_install(device->irqno, rt_serial_isr, RT_NULL); /* install isr */ - - rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer)); - device->read_index = device->save_index = 0; - - out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */ - /* setup baudrate */ - rt_serial_set_baudrate(device); - out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */ - out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */ - val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */ - out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */ - out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */ - - device->parent.type = RT_Device_Class_Char; - device->parent.init = rt_serial_init; - device->parent.open = rt_serial_open; - device->parent.close = rt_serial_close; - device->parent.read = rt_serial_read; - device->parent.write = rt_serial_write; - device->parent.control = rt_serial_control; - device->parent.user_data = RT_NULL; - - rt_device_register(&device->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); -} +#include +#include + +#include "io.h" +#include + +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define UCR0_MASK 0x0000007f +#define UCR1_MASK 0x00007f00 +#define UCR0_UDIV_POS 0 +#define UCR1_UDIV_POS 8 +#define UDIV_MAX 127 + +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncLSRDataReady1 0x01 +#define asyncLSROverrunError1 0x02 +#define asyncLSRParityError1 0x04 +#define asyncLSRFramingError1 0x08 +#define asyncLSRBreakInterrupt1 0x10 +#define asyncLSRTxHoldEmpty1 0x20 +#define asyncLSRTxShiftEmpty1 0x40 +#define asyncLSRRxFifoError1 0x80 + +/* PPC405 serial device */ +struct rt_ppc405_serial +{ + /* inherit from device */ + struct rt_device parent; + + rt_uint32_t hw_base; + rt_uint32_t irqno; + rt_uint32_t baudrate; + + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; +}; +struct rt_ppc405_serial ppc405_serial; + +/* serial character device */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_ppc405_serial* device; + device = (struct rt_ppc405_serial*) dev; + + RT_ASSERT(device != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable "RX Data Available" Interrupt on UART */ + out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01); + /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ + out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1); + + /* init UART rx interrupt */ + rt_hw_interrupt_unmask(device->irqno); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + struct rt_ppc405_serial* device; + device = (struct rt_ppc405_serial*) dev; + + RT_ASSERT(device != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* mask UART rx interrupt */ + rt_hw_interrupt_mask(device->irqno); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) dev; + RT_ASSERT(device != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (device->read_index != device->save_index) + { + *ptr = device->rx_buffer[device->read_index]; + + device->read_index ++; + if (device->read_index >= RT_UART_RX_BUFFER_SIZE) + device->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + + /* polling mode */ + RT_ASSERT(0); + + return (rt_size_t)ptr - (rt_size_t)buffer; +} + +static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + char *ptr; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) dev; + RT_ASSERT(device != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } + + /* polling write */ + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r'); + } + + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); + + ptr ++; + size --; + } + } + else + { + while (size) + { + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; +} + +void rt_serial_set_baudrate(struct rt_ppc405_serial* device) +{ + rt_uint32_t bdiv; + + bdiv = 115200; + out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */ + out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ +} + +void rt_serial_isr(int irqno) +{ + unsigned char status; + struct rt_ppc405_serial *device; + + device = (struct rt_ppc405_serial*) &ppc405_serial; + status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); + + if (status & 0x01) + { + rt_base_t level; + + while (status & 0x01) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* read character */ + device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base)); + device->save_index ++; + if (device->save_index >= RT_UART_RX_BUFFER_SIZE) + device->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (device->save_index == device->read_index) + { + device->read_index ++; + if (device->read_index >= RT_UART_RX_BUFFER_SIZE) + device->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* check error */ + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) + { + out_8((rt_uint8_t *)device->hw_base + UART_LSR, + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + + status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); + } + + /* invoke callback */ + if(device->parent.rx_indicate != RT_NULL) + { + device->parent.rx_indicate(&device->parent, 1); + } + } +} + +void rt_hw_serial_init(void) +{ + volatile rt_uint8_t val; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) &ppc405_serial; + device->parent.type = RT_Device_Class_Char; + + device->hw_base = UART0_BASE; + device->baudrate = 115200; + device->irqno = VECNUM_U0; + rt_hw_interrupt_install(device->irqno, rt_serial_isr, RT_NULL); /* install isr */ + + rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer)); + device->read_index = device->save_index = 0; + + out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */ + /* setup baudrate */ + rt_serial_set_baudrate(device); + out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */ + out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */ + val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */ + out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */ + out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */ + + device->parent.type = RT_Device_Class_Char; + device->parent.init = rt_serial_init; + device->parent.open = rt_serial_open; + device->parent.close = rt_serial_close; + device->parent.read = rt_serial_read; + device->parent.write = rt_serial_write; + device->parent.control = rt_serial_control; + device->parent.user_data = RT_NULL; + + rt_device_register(&device->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); +} diff --git a/libcpu/ppc/ppc405/traps.c b/libcpu/ppc/ppc405/traps.c index 292927b32876f08c5f5c7741ab02ccc264ed858b..1deecbc92b20eb4737d77b09956cc17786ba2283 100644 --- a/libcpu/ppc/ppc405/traps.c +++ b/libcpu/ppc/ppc405/traps.c @@ -1,208 +1,208 @@ -#include -#include -#include - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. - */ -#define END_OF_MEM 0x800000 -#define UICB0_ALL 0 - -#define ESR_MCI 0x80000000 -#define ESR_PIL 0x08000000 -#define ESR_PPR 0x04000000 -#define ESR_PTR 0x02000000 -#define ESR_DST 0x00800000 -#define ESR_DIZ 0x00400000 -#define ESR_U0F 0x00008000 - -rt_inline void set_tsr(unsigned long val) -{ - mtspr(SPRN_TSR, val); -} - -rt_inline rt_uint32_t get_esr(void) -{ - rt_uint32_t val; - - val = mfspr(SPRN_ESR); - return val; -} - -/* - * Trap & Exception support - */ - -void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - rt_kprintf("Call backtrace: "); - while (sp) { - if ((rt_uint32_t)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - rt_kprintf("\n"); - rt_kprintf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - rt_kprintf("\n"); -} - -void show_regs(struct pt_regs * regs) -{ - int i; - - rt_kprintf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - rt_kprintf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - rt_kprintf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) { - rt_kprintf("GPR%02d: ", i); - } - - rt_kprintf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) { - rt_kprintf("\n"); - } - } -} - -void panic(const char *fmt, ...) -{ - while(1); -} - -void -_exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception"); -} - -unsigned long -search_exception_table(unsigned long addr) -{ - unsigned long ret = 0; - - /* There is only the kernel to search. */ - // ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); - /* if the serial port does not hang in exception, rt_kprintf can be used */ - if (ret) return ret; - - return 0; -} - -/* - * Handle external interrupts - */ -void external_interrupt(struct pt_regs *regs) -{ - u32 uic_msr; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic_msr = mfdcr(uic0msr); - - mtdcr(uic0sr, (uic_msr & UICB0_ALL)); - - if (uic_msr & ~(UICB0_ALL)) - { - uic_interrupt(UIC0_DCR_BASE, 0); - } - - return; -} - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup, val; - - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - val = mfspr(MCSR); - /* Clear MCSR */ - mtspr(SPRN_MCSR, val); - return; - } - - rt_kprintf("Machine Check Exception.\n"); - rt_kprintf("Caused by (from msr): "); - rt_kprintf("regs %p ", regs); - - val = get_esr(); - - if (val& ESR_IMCP) { - rt_kprintf("Instruction"); - mtspr(ESR, val & ~ESR_IMCP); - } else { - rt_kprintf("Data"); - } - rt_kprintf(" machine check.\n"); - - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ - long esr_val; - - show_regs(regs); - - esr_val = get_esr(); - if( esr_val & ESR_PIL ) - rt_kprintf( "** Illegal Instruction **\n" ); - else if( esr_val & ESR_PPR ) - rt_kprintf( "** Privileged Instruction **\n" ); - else if( esr_val & ESR_PTR ) - rt_kprintf( "** Trap Instruction **\n" ); - - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void DecrementerPITException(struct pt_regs *regs) -{ - /* reset PIT interrupt */ - set_tsr(0x08000000); - - /* increase a OS Tick */ - rt_tick_increase(); -} - -void UnknownException(struct pt_regs *regs) -{ - - rt_kprintf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -void DebugException(struct pt_regs *regs) -{ - rt_kprintf("Debugger trap at @ %lx @regs %lx\n", regs->nip, (rt_uint32_t)regs ); - show_regs(regs); -} +#include +#include +#include + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. + */ +#define END_OF_MEM 0x800000 +#define UICB0_ALL 0 + +#define ESR_MCI 0x80000000 +#define ESR_PIL 0x08000000 +#define ESR_PPR 0x04000000 +#define ESR_PTR 0x02000000 +#define ESR_DST 0x00800000 +#define ESR_DIZ 0x00400000 +#define ESR_U0F 0x00008000 + +rt_inline void set_tsr(unsigned long val) +{ + mtspr(SPRN_TSR, val); +} + +rt_inline rt_uint32_t get_esr(void) +{ + rt_uint32_t val; + + val = mfspr(SPRN_ESR); + return val; +} + +/* + * Trap & Exception support + */ + +void print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + rt_kprintf("Call backtrace: "); + while (sp) { + if ((rt_uint32_t)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + rt_kprintf("\n"); + rt_kprintf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + rt_kprintf("\n"); +} + +void show_regs(struct pt_regs * regs) +{ + int i; + + rt_kprintf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + rt_kprintf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + rt_kprintf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { + rt_kprintf("GPR%02d: ", i); + } + + rt_kprintf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) { + rt_kprintf("\n"); + } + } +} + +void panic(const char *fmt, ...) +{ + while(1); +} + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception"); +} + +unsigned long +search_exception_table(unsigned long addr) +{ + unsigned long ret = 0; + + /* There is only the kernel to search. */ + // ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); + /* if the serial port does not hang in exception, rt_kprintf can be used */ + if (ret) return ret; + + return 0; +} + +/* + * Handle external interrupts + */ +void external_interrupt(struct pt_regs *regs) +{ + u32 uic_msr; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = mfdcr(uic0msr); + + mtdcr(uic0sr, (uic_msr & UICB0_ALL)); + + if (uic_msr & ~(UICB0_ALL)) + { + uic_interrupt(UIC0_DCR_BASE, 0); + } + + return; +} + +void MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup, val; + + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + val = mfspr(MCSR); + /* Clear MCSR */ + mtspr(SPRN_MCSR, val); + return; + } + + rt_kprintf("Machine Check Exception.\n"); + rt_kprintf("Caused by (from msr): "); + rt_kprintf("regs %p ", regs); + + val = get_esr(); + + if (val& ESR_IMCP) { + rt_kprintf("Instruction"); + mtspr(ESR, val & ~ESR_IMCP); + } else { + rt_kprintf("Data"); + } + rt_kprintf(" machine check.\n"); + + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void AlignmentException(struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void ProgramCheckException(struct pt_regs *regs) +{ + long esr_val; + + show_regs(regs); + + esr_val = get_esr(); + if( esr_val & ESR_PIL ) + rt_kprintf( "** Illegal Instruction **\n" ); + else if( esr_val & ESR_PPR ) + rt_kprintf( "** Privileged Instruction **\n" ); + else if( esr_val & ESR_PTR ) + rt_kprintf( "** Trap Instruction **\n" ); + + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void DecrementerPITException(struct pt_regs *regs) +{ + /* reset PIT interrupt */ + set_tsr(0x08000000); + + /* increase a OS Tick */ + rt_tick_increase(); +} + +void UnknownException(struct pt_regs *regs) +{ + + rt_kprintf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +void DebugException(struct pt_regs *regs) +{ + rt_kprintf("Debugger trap at @ %lx @regs %lx\n", regs->nip, (rt_uint32_t)regs ); + show_regs(regs); +} diff --git a/libcpu/sim/win32/cpu_port.c b/libcpu/sim/win32/cpu_port.c index 5969d2e8d1b9cb5297a0e89340fad32dd5d2dda0..38c387b196cf3f5eb54a2fbf245e52bcf9429a1e 100644 --- a/libcpu/sim/win32/cpu_port.c +++ b/libcpu/sim/win32/cpu_port.c @@ -1,677 +1,677 @@ -/* -************************************************************************************************************************ -* File : cpu_port.c -* By : xyou -* Version : V1.00.00 -* -* By : prife -* Version : V1.00.01 -************************************************************************************************************************ -*/ - -/* -********************************************************************************************************* -* INCLUDE FILES -********************************************************************************************************* -*/ -#include -#include -#include -#include -#include "cpu_port.h" - -/* -********************************************************************************************************* -* WinThread STRUCTURE -* Windows runs each task in a thread. -* The context switch is managed by the threads.So the task stack does not have to be managed directly, -* although the stack stack is still used to hold an WinThreadState structure this is the only thing it -* will be ever hold. -* the structure indirectly maps the task handle to a thread handle -********************************************************************************************************* -*/ -typedef struct -{ - void *Param; //Thread param - void (*Entry)(void *); //Thread entry - void (*Exit)(void); //Thread exit - HANDLE ThreadHandle; - DWORD ThreadID; -}win_thread_t; - -const DWORD MS_VC_EXCEPTION=0x406D1388; - -#pragma pack(push,8) -typedef struct tagTHREADNAME_INFO -{ - DWORD dwType; // Must be 0x1000. - LPCSTR szName; // Pointer to name (in user addr space). - DWORD dwThreadID; // Thread ID (-1=caller thread). - DWORD dwFlags; // Reserved for future use, must be zero. -} THREADNAME_INFO; -#pragma pack(pop) - -/* -********************************************************************************************************* -* LOCAL DEFINES -********************************************************************************************************* -*/ -#define MAX_INTERRUPT_NUM ((rt_uint32_t)sizeof(rt_uint32_t) * 8) - -/* - * Simulated interrupt waiting to be processed.this is a bit mask where each bit represent one interrupt - * so a maximum of 32 interrupts can be simulated - */ -static volatile rt_uint32_t CpuPendingInterrupts = 0; - -/* - * An event used to inform the simulated interrupt processing thread (a high priority thread - * that simulated interrupt processing) that an interrupt is pending - */ -static HANDLE hInterruptEventHandle = NULL; - -/* - * Mutex used to protect all the simulated interrupt variables that are accessed by multiple threads - */ -static HANDLE hInterruptEventMutex = NULL; - -/* - * Handler for all the simulate software interrupts. - * The first two positions are used the Yield and Tick interrupt so are handled slightly differently - * all the other interrupts can be user defined -*/ -static rt_uint32_t (*CpuIsrHandler[MAX_INTERRUPT_NUM])(void) = {0}; - -/* - * Handler for OSTick Thread - */ -static HANDLE OSTick_Thread; -static DWORD OSTick_ThreadID; -static HANDLE OSTick_SignalPtr; -static TIMECAPS OSTick_TimerCap; -static MMRESULT OSTick_TimerID; - -/* - * flag in interrupt handling - */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/* -********************************************************************************************************* -* PRIVATE FUNCTION PROTOTYPES -********************************************************************************************************* -*/ -//static void WinThreadScheduler(void); -void WinThreadScheduler(void); -rt_uint32_t YieldInterruptHandle(void); -rt_uint32_t SysTickInterruptHandle(void); -static DWORD WINAPI ThreadforSysTickTimer(LPVOID lpParam); -static DWORD WINAPI ThreadforKeyGet(LPVOID lpParam); - -static void SetThreadName(DWORD dwThreadID, char* threadName) -{ - THREADNAME_INFO info; - info.dwType = 0x1000; - info.szName = threadName; - info.dwThreadID = dwThreadID; - info.dwFlags = 0; - - __try - { - RaiseException( MS_VC_EXCEPTION, 0, sizeof(info)/sizeof(ULONG_PTR), (ULONG_PTR*)&info ); - } - __except(EXCEPTION_EXECUTE_HANDLER) - { - } -} - -/* -********************************************************************************************************* -* rt_hw_stack_init() -* Description : Initialize stack of thread -* Argument(s) : void *pvEntry,void *pvParam,rt_uint8_t *pStackAddr,void *pvExit -* Return(s) : rt_uint8_t* -* Caller(s) : rt_thread_init or rt_thread_create -* Note(s) : none -********************************************************************************************************* -*/ - -static DWORD WINAPI thread_run( LPVOID lpThreadParameter ) -{ - rt_thread_t tid = rt_thread_self(); - win_thread_t *pWinThread = (win_thread_t *)lpThreadParameter; - - SetThreadName(GetCurrentThreadId(), tid->name); - - pWinThread->Entry(pWinThread->Param); - - pWinThread->Exit(); - return 0; -} - -rt_uint8_t* rt_hw_stack_init(void *pEntry,void *pParam,rt_uint8_t *pStackAddr,void *pExit) -{ - win_thread_t *pWinThread = NULL; - - /* - * In this simulated case a stack is not initialized - * The thread handles the context switching itself. The WinThreadState object is placed onto the stack - * that was created for the task - * so the stack buffer is still used,just not in the conventional way. - */ - pWinThread = (win_thread_t *)(pStackAddr - sizeof(win_thread_t)); - - pWinThread->Entry = pEntry; - pWinThread->Param = pParam; - pWinThread->Exit = pExit; - - pWinThread->ThreadHandle = NULL; - pWinThread->ThreadID = 0; - - /* Create the winthread */ - pWinThread->ThreadHandle = CreateThread(NULL, - 0, - (LPTHREAD_START_ROUTINE) thread_run, - pWinThread, - CREATE_SUSPENDED, - &(pWinThread->ThreadID)); - SetThreadAffinityMask(pWinThread->ThreadHandle, - 0x01); - SetThreadPriorityBoost(pWinThread->ThreadHandle, - TRUE); - SetThreadPriority(pWinThread->ThreadHandle, - THREAD_PRIORITY_IDLE); - - return (rt_uint8_t*)pWinThread; -} /*** rt_hw_stack_init ***/ - -/* -********************************************************************************************************* -* rt_hw_interrupt_disable() -* Description : disable cpu interrupts -* Argument(s) : void -* Return(s) : rt_base_t -* Caller(s) : Applicatios or os_kernel -* Note(s) : none -********************************************************************************************************* -*/ -rt_base_t rt_hw_interrupt_disable(void) -{ - if(hInterruptEventMutex != NULL) - { - WaitForSingleObject(hInterruptEventMutex,INFINITE); - } - - return 0; -} /*** rt_hw_interrupt_disable ***/ - - -/* -********************************************************************************************************* -* rt_hw_interrupt_enable() -* Description : enable cpu interrupts -* Argument(s) : rt_base_t level -* Return(s) : void -* Caller(s) : Applications or os_kernel -* Note(s) : none -********************************************************************************************************* -*/ -void rt_hw_interrupt_enable(rt_base_t level) -{ - level = level; - - if (hInterruptEventMutex != NULL) - { - ReleaseMutex(hInterruptEventMutex); - } - -} /*** rt_hw_interrupt_enable ***/ - -/* -********************************************************************************************************* -* rt_hw_context_switch_interrupt() -* Description : switch thread's contex -* Argument(s) : void -* Return(s) : void -* Caller(s) : os kernel -* Note(s) : none -********************************************************************************************************* -*/ -void rt_hw_context_switch_interrupt(rt_uint32_t from, - rt_uint32_t to) -{ - if(rt_thread_switch_interrupt_flag != 1) - { - rt_thread_switch_interrupt_flag = 1; - - // set rt_interrupt_from_thread - rt_interrupt_from_thread = *((rt_uint32_t *)(from)); - } - - rt_interrupt_to_thread = *((rt_uint32_t *)(to)); - - //trigger YIELD exception(cause context switch) - TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); -} /*** rt_hw_context_switch_interrupt ***/ - - - -void rt_hw_context_switch(rt_uint32_t from, - rt_uint32_t to) -{ - if(rt_thread_switch_interrupt_flag != 1) - { - rt_thread_switch_interrupt_flag = 1; - - // set rt_interrupt_from_thread - rt_interrupt_from_thread = *((rt_uint32_t *)(from)); - - } - - // set rt_interrupt_to_thread - rt_interrupt_to_thread = *((rt_uint32_t *)(to)); - - //trigger YIELD exception(cause contex switch) - TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); - -} /*** rt_hw_context_switch ***/ - -/* -********************************************************************************************************* -* rt_hw_context_switch_to() -* Description : switch to new thread -* Argument(s) : rt_uint32_t to //the stack address of the thread which will switch to -* Return(s) : void -* Caller(s) : rt_thread schecale -* Note(s) : this function is used to perform the first thread switch -********************************************************************************************************* -*/ -void rt_hw_context_switch_to(rt_uint32_t to) -{ - //set to thread - rt_interrupt_to_thread = *((rt_uint32_t *)(to)); - - //clear from thread - rt_interrupt_from_thread = 0; - - //set interrupt to 1 - rt_thread_switch_interrupt_flag = 1; - - //start WinThreadScheduler - WinThreadScheduler(); - - //never reach here! - return; - -} /*** rt_hw_context_switch_to ***/ - - - -/* -********************************************************************************************************* -* TriggerSimulateInterrupt() -* Description : Trigger a simulated interrupts handle -* Argument(s) : t_uint32_t IntIndex -* Return(s) : void -* Caller(s) : Applications -* Note(s) : none -********************************************************************************************************* -*/ -void TriggerSimulateInterrupt(rt_uint32_t IntIndex) -{ - if((IntIndex < MAX_INTERRUPT_NUM) && (hInterruptEventMutex != NULL)) - { - /* Yield interrupts are processed even when critical nesting is non-zero */ - WaitForSingleObject(hInterruptEventMutex, - INFINITE); - - CpuPendingInterrupts |= (1 << IntIndex); - - SetEvent(hInterruptEventHandle); - - ReleaseMutex(hInterruptEventMutex); - } -} /*** TriggerSimulateInterrupt ***/ - -/* -********************************************************************************************************* -* RegisterSimulateInterrupt() -* Description : Register a interrupt handle to simulate paltform -* Argument(s) : rt_uint32_t IntIndex,rt_uint32_t (*IntHandler)(void) -* Return(s) : void -* Caller(s) : Applications -* Note(s) : none -********************************************************************************************************* -*/ -void RegisterSimulateInterrupt(rt_uint32_t IntIndex,rt_uint32_t (*IntHandler)(void)) -{ - if(IntIndex < MAX_INTERRUPT_NUM) - { - if (hInterruptEventMutex != NULL) - { - WaitForSingleObject(hInterruptEventMutex, - INFINITE); - - CpuIsrHandler[IntIndex] = IntHandler; - - ReleaseMutex(hInterruptEventMutex); - } - else - { - CpuIsrHandler[IntIndex] = IntHandler; - } - } - -} /*** RegisterSimulateInterrupt ***/ - - - -/* -********************************************************************************************************* -* PRIVATE FUNCTION -********************************************************************************************************* -*/ - -/* -********************************************************************************************************* -* WinThreadScheduler() -* Description : Handle all simulate interrupts -* Argument(s) : void -* Return(s) : static void -* Caller(s) : os scachle -* Note(s) : none -********************************************************************************************************* -*/ -#define WIN_WM_MIN_RES (1) - void WinThreadScheduler(void) -{ - HANDLE hInterruptObjectList[2]; - HANDLE hThreadHandle; - rt_uint32_t SwitchRequiredMask; - rt_uint32_t i; - - win_thread_t *WinThreadFrom; - win_thread_t *WinThreadTo; - - /* - * Install the interrupt handlers used bye scheduler itself - */ - RegisterSimulateInterrupt(CPU_INTERRUPT_YIELD, - YieldInterruptHandle); - RegisterSimulateInterrupt(CPU_INTERRUPT_TICK, - SysTickInterruptHandle); - - /* - * Create the events and mutex that are used to synchronise all the WinThreads - */ - hInterruptEventMutex = CreateMutex(NULL, - FALSE, - NULL); - hInterruptEventHandle = CreateEvent(NULL, - FALSE, - FALSE, - NULL); - - if((hInterruptEventMutex == NULL) || (hInterruptEventHandle == NULL)) - { - return; - } - - /* - * Set the priority of this WinThread such that it is above the priority of the WinThreads - * that run rt-threads. - * This is higher priority is required to ensure simulate interrupts take priority over rt-threads - */ - hThreadHandle = GetCurrentThread(); - if(hThreadHandle == NULL) - { - return; - } - - if (SetThreadPriority(hThreadHandle, - THREAD_PRIORITY_HIGHEST) == 0) - { - return; - } - SetThreadPriorityBoost(hThreadHandle, - TRUE); - SetThreadAffinityMask(hThreadHandle, - 0x01); - - /* - * Start the thread that simulates the timer peripheral to generate tick interrupts. - */ - OSTick_Thread = CreateThread(NULL, - 0, - ThreadforSysTickTimer, - 0, - CREATE_SUSPENDED, - &OSTick_ThreadID); - if(OSTick_Thread == NULL) - { - //Display Error Message - - - return; - } - SetThreadPriority(OSTick_Thread, - THREAD_PRIORITY_NORMAL); - SetThreadPriorityBoost(OSTick_Thread, - TRUE); - SetThreadAffinityMask(OSTick_Thread, - 0x01); - - /* - * Set timer Caps - */ - if (timeGetDevCaps(&OSTick_TimerCap, - sizeof(OSTick_TimerCap)) != TIMERR_NOERROR) - { - - CloseHandle(OSTick_Thread); - - return; - } - if (OSTick_TimerCap.wPeriodMin < WIN_WM_MIN_RES) - { - OSTick_TimerCap.wPeriodMin = WIN_WM_MIN_RES; - } - - if(timeBeginPeriod(OSTick_TimerCap.wPeriodMin) != TIMERR_NOERROR) - { - CloseHandle(OSTick_Thread); - - return; - } - - OSTick_SignalPtr = CreateEvent(NULL,TRUE,FALSE,NULL); - if(OSTick_SignalPtr == NULL) - { - // disp error message - - timeEndPeriod(OSTick_TimerCap.wPeriodMin); - CloseHandle(OSTick_Thread); - - return; - } - - OSTick_TimerID = timeSetEvent((UINT ) (1000 / RT_TICK_PER_SECOND) , - (UINT ) OSTick_TimerCap.wPeriodMin, - (LPTIMECALLBACK ) OSTick_SignalPtr, - (DWORD_PTR ) NULL, - (UINT ) (TIME_PERIODIC | TIME_CALLBACK_EVENT_SET)); - - if(OSTick_TimerID == 0) - { - //disp - - CloseHandle(OSTick_SignalPtr); - timeEndPeriod(OSTick_TimerCap.wPeriodMin); - CloseHandle(OSTick_Thread); - - return; - } - - /* - * Start OS Tick Thread an release Interrupt Mutex - */ - ResumeThread(OSTick_Thread); - ReleaseMutex( hInterruptEventMutex ); - - //trigger YEILD INTERRUPT - TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); - - /* - * block on the mutex that ensure exclusive access to the simulated interrupt objects - * and the events that signals that a simulated interrupt should be processed. - */ - - hInterruptObjectList[0] = hInterruptEventHandle; - hInterruptObjectList[1] = hInterruptEventMutex; - - - while (1) - { - WaitForMultipleObjects(sizeof(hInterruptObjectList) / sizeof(HANDLE), - hInterruptObjectList, - TRUE, - INFINITE); - - /* - * Used to indicate whether the simulate interrupt processing has necessitated a contex - * switch to another thread - */ - SwitchRequiredMask = 0; - - /* - * For each interrupt we are interested in processing ,each of which is represented - * by a bit in the 32bit CpuPendingInterrupts variable. - */ - for (i = 0; i < MAX_INTERRUPT_NUM; ++i) - { - /* is the simulated interrupt pending ? */ - if (CpuPendingInterrupts & (1UL << i)) - { - /* Is a handler installed ?*/ - if (CpuIsrHandler[i] != NULL) - { - /* Run the actual handler */ - if (CpuIsrHandler[i]() != 0) - { - SwitchRequiredMask |= (1UL << i); - } - } - - /* Clear the interrupt pending bit */ - CpuPendingInterrupts &= ~(1UL << i); - } - } - - if(SwitchRequiredMask != 0) - { - WinThreadFrom = (win_thread_t *)rt_interrupt_from_thread; - WinThreadTo = (win_thread_t *)rt_interrupt_to_thread; - - if ((WinThreadFrom != NULL) && (WinThreadFrom->ThreadHandle != NULL)) - { - SuspendThread(WinThreadFrom->ThreadHandle); - } - - ResumeThread(WinThreadTo->ThreadHandle); - - } - - ReleaseMutex(hInterruptEventMutex); - } -} /*** WinThreadScheduler ***/ - - - -/* -********************************************************************************************************* -* ThreadforSysTickTimer() -* Description : win thread to simulate a systick timer -* Argument(s) : LPVOID lpParam -* Return(s) : static DWORD WINAPI -* Caller(s) : none -* Note(s) : This is not a real time way of generating tick events as the next wake time should be relative -* to the previous wake time,not the time Sleep() is called. -* It is done this way to prevent overruns in this very non real time simulated/emulated environment -********************************************************************************************************* -*/ -static DWORD WINAPI ThreadforSysTickTimer(LPVOID lpParam) -{ - - (void)lpParam; //prevent compiler warnings - - for(;;) - { - /* - * Wait until the timer expires and we can access the simulated interrupt variables. - */ - WaitForSingleObject(OSTick_SignalPtr,INFINITE); - - ResetEvent(OSTick_SignalPtr); - - /* - * Trigger a systick interrupt - */ - TriggerSimulateInterrupt(CPU_INTERRUPT_TICK); - - } - - return 0; - -} /*** prvThreadforSysTickTimer ***/ - -/* -********************************************************************************************************* -* SysTickInterruptHandle() -* Description : Interrupt handle for systick -* Argument(s) : void -* Return(s) : rt_uint32_t -* Caller(s) : none -* Note(s) : none -********************************************************************************************************* -*/ -rt_uint32_t SysTickInterruptHandle(void) -{ - - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); - - return 0; -} /*** SysTickInterruptHandle ***/ - -/* -********************************************************************************************************* -* YieldInterruptHandle() -* Description : Interrupt handle for Yield -* Argument(s) : void -* Return(s) : rt_uint32_t -* Caller(s) : none -* Note(s) : none -********************************************************************************************************* -*/ -rt_uint32_t YieldInterruptHandle(void) -{ - - /* - * if rt_thread_switch_interrupt_flag = 1 yield already handled - */ - if(rt_thread_switch_interrupt_flag != 0) - { - rt_thread_switch_interrupt_flag = 0; - - /* return thread switch request = 1 */ - return 1; - } - - return 0; -} /*** YieldInterruptHandle ***/ +/* +************************************************************************************************************************ +* File : cpu_port.c +* By : xyou +* Version : V1.00.00 +* +* By : prife +* Version : V1.00.01 +************************************************************************************************************************ +*/ + +/* +********************************************************************************************************* +* INCLUDE FILES +********************************************************************************************************* +*/ +#include +#include +#include +#include +#include "cpu_port.h" + +/* +********************************************************************************************************* +* WinThread STRUCTURE +* Windows runs each task in a thread. +* The context switch is managed by the threads.So the task stack does not have to be managed directly, +* although the stack stack is still used to hold an WinThreadState structure this is the only thing it +* will be ever hold. +* the structure indirectly maps the task handle to a thread handle +********************************************************************************************************* +*/ +typedef struct +{ + void *Param; //Thread param + void (*Entry)(void *); //Thread entry + void (*Exit)(void); //Thread exit + HANDLE ThreadHandle; + DWORD ThreadID; +}win_thread_t; + +const DWORD MS_VC_EXCEPTION=0x406D1388; + +#pragma pack(push,8) +typedef struct tagTHREADNAME_INFO +{ + DWORD dwType; // Must be 0x1000. + LPCSTR szName; // Pointer to name (in user addr space). + DWORD dwThreadID; // Thread ID (-1=caller thread). + DWORD dwFlags; // Reserved for future use, must be zero. +} THREADNAME_INFO; +#pragma pack(pop) + +/* +********************************************************************************************************* +* LOCAL DEFINES +********************************************************************************************************* +*/ +#define MAX_INTERRUPT_NUM ((rt_uint32_t)sizeof(rt_uint32_t) * 8) + +/* + * Simulated interrupt waiting to be processed.this is a bit mask where each bit represent one interrupt + * so a maximum of 32 interrupts can be simulated + */ +static volatile rt_uint32_t CpuPendingInterrupts = 0; + +/* + * An event used to inform the simulated interrupt processing thread (a high priority thread + * that simulated interrupt processing) that an interrupt is pending + */ +static HANDLE hInterruptEventHandle = NULL; + +/* + * Mutex used to protect all the simulated interrupt variables that are accessed by multiple threads + */ +static HANDLE hInterruptEventMutex = NULL; + +/* + * Handler for all the simulate software interrupts. + * The first two positions are used the Yield and Tick interrupt so are handled slightly differently + * all the other interrupts can be user defined +*/ +static rt_uint32_t (*CpuIsrHandler[MAX_INTERRUPT_NUM])(void) = {0}; + +/* + * Handler for OSTick Thread + */ +static HANDLE OSTick_Thread; +static DWORD OSTick_ThreadID; +static HANDLE OSTick_SignalPtr; +static TIMECAPS OSTick_TimerCap; +static MMRESULT OSTick_TimerID; + +/* + * flag in interrupt handling + */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/* +********************************************************************************************************* +* PRIVATE FUNCTION PROTOTYPES +********************************************************************************************************* +*/ +//static void WinThreadScheduler(void); +void WinThreadScheduler(void); +rt_uint32_t YieldInterruptHandle(void); +rt_uint32_t SysTickInterruptHandle(void); +static DWORD WINAPI ThreadforSysTickTimer(LPVOID lpParam); +static DWORD WINAPI ThreadforKeyGet(LPVOID lpParam); + +static void SetThreadName(DWORD dwThreadID, char* threadName) +{ + THREADNAME_INFO info; + info.dwType = 0x1000; + info.szName = threadName; + info.dwThreadID = dwThreadID; + info.dwFlags = 0; + + __try + { + RaiseException( MS_VC_EXCEPTION, 0, sizeof(info)/sizeof(ULONG_PTR), (ULONG_PTR*)&info ); + } + __except(EXCEPTION_EXECUTE_HANDLER) + { + } +} + +/* +********************************************************************************************************* +* rt_hw_stack_init() +* Description : Initialize stack of thread +* Argument(s) : void *pvEntry,void *pvParam,rt_uint8_t *pStackAddr,void *pvExit +* Return(s) : rt_uint8_t* +* Caller(s) : rt_thread_init or rt_thread_create +* Note(s) : none +********************************************************************************************************* +*/ + +static DWORD WINAPI thread_run( LPVOID lpThreadParameter ) +{ + rt_thread_t tid = rt_thread_self(); + win_thread_t *pWinThread = (win_thread_t *)lpThreadParameter; + + SetThreadName(GetCurrentThreadId(), tid->name); + + pWinThread->Entry(pWinThread->Param); + + pWinThread->Exit(); + return 0; +} + +rt_uint8_t* rt_hw_stack_init(void *pEntry,void *pParam,rt_uint8_t *pStackAddr,void *pExit) +{ + win_thread_t *pWinThread = NULL; + + /* + * In this simulated case a stack is not initialized + * The thread handles the context switching itself. The WinThreadState object is placed onto the stack + * that was created for the task + * so the stack buffer is still used,just not in the conventional way. + */ + pWinThread = (win_thread_t *)(pStackAddr - sizeof(win_thread_t)); + + pWinThread->Entry = pEntry; + pWinThread->Param = pParam; + pWinThread->Exit = pExit; + + pWinThread->ThreadHandle = NULL; + pWinThread->ThreadID = 0; + + /* Create the winthread */ + pWinThread->ThreadHandle = CreateThread(NULL, + 0, + (LPTHREAD_START_ROUTINE) thread_run, + pWinThread, + CREATE_SUSPENDED, + &(pWinThread->ThreadID)); + SetThreadAffinityMask(pWinThread->ThreadHandle, + 0x01); + SetThreadPriorityBoost(pWinThread->ThreadHandle, + TRUE); + SetThreadPriority(pWinThread->ThreadHandle, + THREAD_PRIORITY_IDLE); + + return (rt_uint8_t*)pWinThread; +} /*** rt_hw_stack_init ***/ + +/* +********************************************************************************************************* +* rt_hw_interrupt_disable() +* Description : disable cpu interrupts +* Argument(s) : void +* Return(s) : rt_base_t +* Caller(s) : Applicatios or os_kernel +* Note(s) : none +********************************************************************************************************* +*/ +rt_base_t rt_hw_interrupt_disable(void) +{ + if(hInterruptEventMutex != NULL) + { + WaitForSingleObject(hInterruptEventMutex,INFINITE); + } + + return 0; +} /*** rt_hw_interrupt_disable ***/ + + +/* +********************************************************************************************************* +* rt_hw_interrupt_enable() +* Description : enable cpu interrupts +* Argument(s) : rt_base_t level +* Return(s) : void +* Caller(s) : Applications or os_kernel +* Note(s) : none +********************************************************************************************************* +*/ +void rt_hw_interrupt_enable(rt_base_t level) +{ + level = level; + + if (hInterruptEventMutex != NULL) + { + ReleaseMutex(hInterruptEventMutex); + } + +} /*** rt_hw_interrupt_enable ***/ + +/* +********************************************************************************************************* +* rt_hw_context_switch_interrupt() +* Description : switch thread's contex +* Argument(s) : void +* Return(s) : void +* Caller(s) : os kernel +* Note(s) : none +********************************************************************************************************* +*/ +void rt_hw_context_switch_interrupt(rt_uint32_t from, + rt_uint32_t to) +{ + if(rt_thread_switch_interrupt_flag != 1) + { + rt_thread_switch_interrupt_flag = 1; + + // set rt_interrupt_from_thread + rt_interrupt_from_thread = *((rt_uint32_t *)(from)); + } + + rt_interrupt_to_thread = *((rt_uint32_t *)(to)); + + //trigger YIELD exception(cause context switch) + TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); +} /*** rt_hw_context_switch_interrupt ***/ + + + +void rt_hw_context_switch(rt_uint32_t from, + rt_uint32_t to) +{ + if(rt_thread_switch_interrupt_flag != 1) + { + rt_thread_switch_interrupt_flag = 1; + + // set rt_interrupt_from_thread + rt_interrupt_from_thread = *((rt_uint32_t *)(from)); + + } + + // set rt_interrupt_to_thread + rt_interrupt_to_thread = *((rt_uint32_t *)(to)); + + //trigger YIELD exception(cause contex switch) + TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); + +} /*** rt_hw_context_switch ***/ + +/* +********************************************************************************************************* +* rt_hw_context_switch_to() +* Description : switch to new thread +* Argument(s) : rt_uint32_t to //the stack address of the thread which will switch to +* Return(s) : void +* Caller(s) : rt_thread schecale +* Note(s) : this function is used to perform the first thread switch +********************************************************************************************************* +*/ +void rt_hw_context_switch_to(rt_uint32_t to) +{ + //set to thread + rt_interrupt_to_thread = *((rt_uint32_t *)(to)); + + //clear from thread + rt_interrupt_from_thread = 0; + + //set interrupt to 1 + rt_thread_switch_interrupt_flag = 1; + + //start WinThreadScheduler + WinThreadScheduler(); + + //never reach here! + return; + +} /*** rt_hw_context_switch_to ***/ + + + +/* +********************************************************************************************************* +* TriggerSimulateInterrupt() +* Description : Trigger a simulated interrupts handle +* Argument(s) : t_uint32_t IntIndex +* Return(s) : void +* Caller(s) : Applications +* Note(s) : none +********************************************************************************************************* +*/ +void TriggerSimulateInterrupt(rt_uint32_t IntIndex) +{ + if((IntIndex < MAX_INTERRUPT_NUM) && (hInterruptEventMutex != NULL)) + { + /* Yield interrupts are processed even when critical nesting is non-zero */ + WaitForSingleObject(hInterruptEventMutex, + INFINITE); + + CpuPendingInterrupts |= (1 << IntIndex); + + SetEvent(hInterruptEventHandle); + + ReleaseMutex(hInterruptEventMutex); + } +} /*** TriggerSimulateInterrupt ***/ + +/* +********************************************************************************************************* +* RegisterSimulateInterrupt() +* Description : Register a interrupt handle to simulate paltform +* Argument(s) : rt_uint32_t IntIndex,rt_uint32_t (*IntHandler)(void) +* Return(s) : void +* Caller(s) : Applications +* Note(s) : none +********************************************************************************************************* +*/ +void RegisterSimulateInterrupt(rt_uint32_t IntIndex,rt_uint32_t (*IntHandler)(void)) +{ + if(IntIndex < MAX_INTERRUPT_NUM) + { + if (hInterruptEventMutex != NULL) + { + WaitForSingleObject(hInterruptEventMutex, + INFINITE); + + CpuIsrHandler[IntIndex] = IntHandler; + + ReleaseMutex(hInterruptEventMutex); + } + else + { + CpuIsrHandler[IntIndex] = IntHandler; + } + } + +} /*** RegisterSimulateInterrupt ***/ + + + +/* +********************************************************************************************************* +* PRIVATE FUNCTION +********************************************************************************************************* +*/ + +/* +********************************************************************************************************* +* WinThreadScheduler() +* Description : Handle all simulate interrupts +* Argument(s) : void +* Return(s) : static void +* Caller(s) : os scachle +* Note(s) : none +********************************************************************************************************* +*/ +#define WIN_WM_MIN_RES (1) + void WinThreadScheduler(void) +{ + HANDLE hInterruptObjectList[2]; + HANDLE hThreadHandle; + rt_uint32_t SwitchRequiredMask; + rt_uint32_t i; + + win_thread_t *WinThreadFrom; + win_thread_t *WinThreadTo; + + /* + * Install the interrupt handlers used bye scheduler itself + */ + RegisterSimulateInterrupt(CPU_INTERRUPT_YIELD, + YieldInterruptHandle); + RegisterSimulateInterrupt(CPU_INTERRUPT_TICK, + SysTickInterruptHandle); + + /* + * Create the events and mutex that are used to synchronise all the WinThreads + */ + hInterruptEventMutex = CreateMutex(NULL, + FALSE, + NULL); + hInterruptEventHandle = CreateEvent(NULL, + FALSE, + FALSE, + NULL); + + if((hInterruptEventMutex == NULL) || (hInterruptEventHandle == NULL)) + { + return; + } + + /* + * Set the priority of this WinThread such that it is above the priority of the WinThreads + * that run rt-threads. + * This is higher priority is required to ensure simulate interrupts take priority over rt-threads + */ + hThreadHandle = GetCurrentThread(); + if(hThreadHandle == NULL) + { + return; + } + + if (SetThreadPriority(hThreadHandle, + THREAD_PRIORITY_HIGHEST) == 0) + { + return; + } + SetThreadPriorityBoost(hThreadHandle, + TRUE); + SetThreadAffinityMask(hThreadHandle, + 0x01); + + /* + * Start the thread that simulates the timer peripheral to generate tick interrupts. + */ + OSTick_Thread = CreateThread(NULL, + 0, + ThreadforSysTickTimer, + 0, + CREATE_SUSPENDED, + &OSTick_ThreadID); + if(OSTick_Thread == NULL) + { + //Display Error Message + + + return; + } + SetThreadPriority(OSTick_Thread, + THREAD_PRIORITY_NORMAL); + SetThreadPriorityBoost(OSTick_Thread, + TRUE); + SetThreadAffinityMask(OSTick_Thread, + 0x01); + + /* + * Set timer Caps + */ + if (timeGetDevCaps(&OSTick_TimerCap, + sizeof(OSTick_TimerCap)) != TIMERR_NOERROR) + { + + CloseHandle(OSTick_Thread); + + return; + } + if (OSTick_TimerCap.wPeriodMin < WIN_WM_MIN_RES) + { + OSTick_TimerCap.wPeriodMin = WIN_WM_MIN_RES; + } + + if(timeBeginPeriod(OSTick_TimerCap.wPeriodMin) != TIMERR_NOERROR) + { + CloseHandle(OSTick_Thread); + + return; + } + + OSTick_SignalPtr = CreateEvent(NULL,TRUE,FALSE,NULL); + if(OSTick_SignalPtr == NULL) + { + // disp error message + + timeEndPeriod(OSTick_TimerCap.wPeriodMin); + CloseHandle(OSTick_Thread); + + return; + } + + OSTick_TimerID = timeSetEvent((UINT ) (1000 / RT_TICK_PER_SECOND) , + (UINT ) OSTick_TimerCap.wPeriodMin, + (LPTIMECALLBACK ) OSTick_SignalPtr, + (DWORD_PTR ) NULL, + (UINT ) (TIME_PERIODIC | TIME_CALLBACK_EVENT_SET)); + + if(OSTick_TimerID == 0) + { + //disp + + CloseHandle(OSTick_SignalPtr); + timeEndPeriod(OSTick_TimerCap.wPeriodMin); + CloseHandle(OSTick_Thread); + + return; + } + + /* + * Start OS Tick Thread an release Interrupt Mutex + */ + ResumeThread(OSTick_Thread); + ReleaseMutex( hInterruptEventMutex ); + + //trigger YEILD INTERRUPT + TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); + + /* + * block on the mutex that ensure exclusive access to the simulated interrupt objects + * and the events that signals that a simulated interrupt should be processed. + */ + + hInterruptObjectList[0] = hInterruptEventHandle; + hInterruptObjectList[1] = hInterruptEventMutex; + + + while (1) + { + WaitForMultipleObjects(sizeof(hInterruptObjectList) / sizeof(HANDLE), + hInterruptObjectList, + TRUE, + INFINITE); + + /* + * Used to indicate whether the simulate interrupt processing has necessitated a contex + * switch to another thread + */ + SwitchRequiredMask = 0; + + /* + * For each interrupt we are interested in processing ,each of which is represented + * by a bit in the 32bit CpuPendingInterrupts variable. + */ + for (i = 0; i < MAX_INTERRUPT_NUM; ++i) + { + /* is the simulated interrupt pending ? */ + if (CpuPendingInterrupts & (1UL << i)) + { + /* Is a handler installed ?*/ + if (CpuIsrHandler[i] != NULL) + { + /* Run the actual handler */ + if (CpuIsrHandler[i]() != 0) + { + SwitchRequiredMask |= (1UL << i); + } + } + + /* Clear the interrupt pending bit */ + CpuPendingInterrupts &= ~(1UL << i); + } + } + + if(SwitchRequiredMask != 0) + { + WinThreadFrom = (win_thread_t *)rt_interrupt_from_thread; + WinThreadTo = (win_thread_t *)rt_interrupt_to_thread; + + if ((WinThreadFrom != NULL) && (WinThreadFrom->ThreadHandle != NULL)) + { + SuspendThread(WinThreadFrom->ThreadHandle); + } + + ResumeThread(WinThreadTo->ThreadHandle); + + } + + ReleaseMutex(hInterruptEventMutex); + } +} /*** WinThreadScheduler ***/ + + + +/* +********************************************************************************************************* +* ThreadforSysTickTimer() +* Description : win thread to simulate a systick timer +* Argument(s) : LPVOID lpParam +* Return(s) : static DWORD WINAPI +* Caller(s) : none +* Note(s) : This is not a real time way of generating tick events as the next wake time should be relative +* to the previous wake time,not the time Sleep() is called. +* It is done this way to prevent overruns in this very non real time simulated/emulated environment +********************************************************************************************************* +*/ +static DWORD WINAPI ThreadforSysTickTimer(LPVOID lpParam) +{ + + (void)lpParam; //prevent compiler warnings + + for(;;) + { + /* + * Wait until the timer expires and we can access the simulated interrupt variables. + */ + WaitForSingleObject(OSTick_SignalPtr,INFINITE); + + ResetEvent(OSTick_SignalPtr); + + /* + * Trigger a systick interrupt + */ + TriggerSimulateInterrupt(CPU_INTERRUPT_TICK); + + } + + return 0; + +} /*** prvThreadforSysTickTimer ***/ + +/* +********************************************************************************************************* +* SysTickInterruptHandle() +* Description : Interrupt handle for systick +* Argument(s) : void +* Return(s) : rt_uint32_t +* Caller(s) : none +* Note(s) : none +********************************************************************************************************* +*/ +rt_uint32_t SysTickInterruptHandle(void) +{ + + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); + + return 0; +} /*** SysTickInterruptHandle ***/ + +/* +********************************************************************************************************* +* YieldInterruptHandle() +* Description : Interrupt handle for Yield +* Argument(s) : void +* Return(s) : rt_uint32_t +* Caller(s) : none +* Note(s) : none +********************************************************************************************************* +*/ +rt_uint32_t YieldInterruptHandle(void) +{ + + /* + * if rt_thread_switch_interrupt_flag = 1 yield already handled + */ + if(rt_thread_switch_interrupt_flag != 0) + { + rt_thread_switch_interrupt_flag = 0; + + /* return thread switch request = 1 */ + return 1; + } + + return 0; +} /*** YieldInterruptHandle ***/ diff --git a/libcpu/sim/win32/cpu_port.h b/libcpu/sim/win32/cpu_port.h index 9d43d61c6d4b029e770d1ad3f428efde91be29db..8ab8ae23bd872fc9b1f5f5a49383ba2ff66a961e 100644 --- a/libcpu/sim/win32/cpu_port.h +++ b/libcpu/sim/win32/cpu_port.h @@ -1,33 +1,33 @@ -/* -************************************************************************************************************************ -* File : cpu_port.h -* By : xyou -* Version : V1.00.00 -************************************************************************************************************************ -*/ - - - -#ifndef _CPU_PORT_H_ -#define _CPU_PORT_H_ - - -/* -********************************************************************************************************* -* CPU INTERRUPT PRIORITY -********************************************************************************************************* -*/ -#define CPU_INTERRUPT_YIELD 0x00 -#define CPU_INTERRUPT_TICK 0x01 - - - -/* -********************************************************************************************************* -* FUNCTION PROTOTYPES -********************************************************************************************************* -*/ -void TriggerSimulateInterrupt(rt_uint32_t IntIndex); - -void WinThreadScheduler(void); -#endif /* _CPU_PORT_H_ */ +/* +************************************************************************************************************************ +* File : cpu_port.h +* By : xyou +* Version : V1.00.00 +************************************************************************************************************************ +*/ + + + +#ifndef _CPU_PORT_H_ +#define _CPU_PORT_H_ + + +/* +********************************************************************************************************* +* CPU INTERRUPT PRIORITY +********************************************************************************************************* +*/ +#define CPU_INTERRUPT_YIELD 0x00 +#define CPU_INTERRUPT_TICK 0x01 + + + +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +********************************************************************************************************* +*/ +void TriggerSimulateInterrupt(rt_uint32_t IntIndex); + +void WinThreadScheduler(void); +#endif /* _CPU_PORT_H_ */ diff --git a/libcpu/v850/70f34/context_iar.S b/libcpu/v850/70f34/context_iar.S index a384c2f0650e0e1917cd33c44078c703c7861d12..5a8c1da41a2192f6ad015ee3607805a22a4a58aa 100644 --- a/libcpu/v850/70f34/context_iar.S +++ b/libcpu/v850/70f34/context_iar.S @@ -1,174 +1,174 @@ -#include "macdefs.inc" - - name OS_Core - - COMMON INTVEC:CODE - -;******************************************************************** -; -; function: -; description: Trap 0x10 vector used for context switch -; Right now, all TRAPs to $1x are trated the same way -; - org 50h - jr OSCtxSW - - -;******************************************************************** -; -; function: -; description: Timer 40 compare match interrupt used for system -; tick interrupt -; - org 0x220 - jr OSTickIntr - - org 0x0520 - jr uarta1_int_r - - RSEG CODE(1) - - EXTERN rt_thread_switch_interrupt_flag - EXTERN rt_interrupt_from_thread - EXTERN rt_interrupt_to_thread - - EXTERN rt_interrupt_enter - EXTERN rt_interrupt_leave - EXTERN rt_tick_increase - EXTERN uarta1_receive_handler - - PUBLIC rt_hw_interrupt_disable - PUBLIC rt_hw_interrupt_enable - PUBLIC rt_hw_context_switch_to - PUBLIC OSCtxSW - PUBLIC OS_Restore_CPU_Context - -rt_hw_interrupt_disable: - stsr psw, r1 - di - jmp [lp] - -rt_hw_interrupt_enable: - ldsr r1, psw - jmp [lp] - -OS_Restore_CPU_Context: - mov sp, ep - sld.w 4[ep], r2 - sld.w 8[ep], r5 - sld.w 12[ep],r6 - sld.w 16[ep],r7 - sld.w 20[ep],r8 - sld.w 24[ep],r9 - sld.w 28[ep],r10 - sld.w 32[ep],r11 - sld.w 36[ep],r12 - sld.w 40[ep],r13 - sld.w 44[ep],r14 - sld.w 48[ep],r15 - sld.w 52[ep],r16 - - ;See what was the latest interruption (trap or interrupt) - stsr ecr, r17 ;Move ecr to r17 - mov 0x050,r1 - cmp r1, r17 ;If latest break was due to TRAP, set EP - be _SetEP - -_ClrEP: - mov 0x20, r17 ;Set only ID - ldsr r17, psw - - ;Restore caller address - sld.w 56[ep], r1 - ldsr r1, EIPC - ;Restore PSW - sld.w 60[ep], r1 - andi 0xffdf,r1,r1 - ldsr r1, EIPSW - sld.w 0[ep], r1 - dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} - - ;Return from interrupt starts new task! - reti - -_SetEP: - mov 0x60, r17 ;Set both EIPC and ID bits - ldsr r17, psw - - ;Restore caller address - sld.w 56[ep], r1 - ldsr r1, EIPC - ;Restore PSW - sld.w 60[ep], r1 - andi 0xffdf,r1,r1 - ldsr r1, EIPSW - sld.w 0[ep], r1 - dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} - - ;Return from interrupt starts new task! - reti - -//rseg CODE:CODE -//public rt_hw_context_switch_to -rt_hw_context_switch_to: - ;Load stack pointer of the task to run - ld.w 0[r1], sp ;load sp from struct - - ;Restore all Processor registers from stack and return from interrupt - jr OS_Restore_CPU_Context - -OSCtxSW: - SAVE_CPU_CTX ;Save all CPU registers - - mov rt_interrupt_from_thread, r21 - ld.w 0[r21], r21 - st.w sp, 0[r21] - - mov rt_interrupt_to_thread, r1 - ld.w 0[r1], r1 - ld.w 0[r1], sp - - ;Restore all Processor registers from stack and return from interrupt - jr OS_Restore_CPU_Context - -rt_hw_context_switch_interrupt_do: - mov rt_thread_switch_interrupt_flag, r8 - mov 0, r9 - st.b r9, 0[r8] - - mov rt_interrupt_from_thread, r21 - ld.w 0[r21], r21 - st.w sp, 0[r21] - - mov rt_interrupt_to_thread, r1 - ld.w 0[r1], r1 - ld.w 0[r1], sp - jr OS_Restore_CPU_Context - -OSTickIntr: - SAVE_CPU_CTX ;Save current task's registers - jarl rt_interrupt_enter,lp - jarl rt_tick_increase,lp - jarl rt_interrupt_leave,lp - - mov rt_thread_switch_interrupt_flag, r8 - ld.w 0[r8],r9 - cmp 1, r9 - be rt_hw_context_switch_interrupt_do - - jr OS_Restore_CPU_Context - -uarta1_int_r: - SAVE_CPU_CTX ;Save current task's registers - jarl rt_interrupt_enter,lp - jarl uarta1_receive_handler,lp - jarl rt_interrupt_leave,lp - - mov rt_thread_switch_interrupt_flag, r8 - ld.w 0[r8],r9 - cmp 1, r9 - be rt_hw_context_switch_interrupt_do - - jr OS_Restore_CPU_Context - - END +#include "macdefs.inc" + + name OS_Core + + COMMON INTVEC:CODE + +;******************************************************************** +; +; function: +; description: Trap 0x10 vector used for context switch +; Right now, all TRAPs to $1x are trated the same way +; + org 50h + jr OSCtxSW + + +;******************************************************************** +; +; function: +; description: Timer 40 compare match interrupt used for system +; tick interrupt +; + org 0x220 + jr OSTickIntr + + org 0x0520 + jr uarta1_int_r + + RSEG CODE(1) + + EXTERN rt_thread_switch_interrupt_flag + EXTERN rt_interrupt_from_thread + EXTERN rt_interrupt_to_thread + + EXTERN rt_interrupt_enter + EXTERN rt_interrupt_leave + EXTERN rt_tick_increase + EXTERN uarta1_receive_handler + + PUBLIC rt_hw_interrupt_disable + PUBLIC rt_hw_interrupt_enable + PUBLIC rt_hw_context_switch_to + PUBLIC OSCtxSW + PUBLIC OS_Restore_CPU_Context + +rt_hw_interrupt_disable: + stsr psw, r1 + di + jmp [lp] + +rt_hw_interrupt_enable: + ldsr r1, psw + jmp [lp] + +OS_Restore_CPU_Context: + mov sp, ep + sld.w 4[ep], r2 + sld.w 8[ep], r5 + sld.w 12[ep],r6 + sld.w 16[ep],r7 + sld.w 20[ep],r8 + sld.w 24[ep],r9 + sld.w 28[ep],r10 + sld.w 32[ep],r11 + sld.w 36[ep],r12 + sld.w 40[ep],r13 + sld.w 44[ep],r14 + sld.w 48[ep],r15 + sld.w 52[ep],r16 + + ;See what was the latest interruption (trap or interrupt) + stsr ecr, r17 ;Move ecr to r17 + mov 0x050,r1 + cmp r1, r17 ;If latest break was due to TRAP, set EP + be _SetEP + +_ClrEP: + mov 0x20, r17 ;Set only ID + ldsr r17, psw + + ;Restore caller address + sld.w 56[ep], r1 + ldsr r1, EIPC + ;Restore PSW + sld.w 60[ep], r1 + andi 0xffdf,r1,r1 + ldsr r1, EIPSW + sld.w 0[ep], r1 + dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} + + ;Return from interrupt starts new task! + reti + +_SetEP: + mov 0x60, r17 ;Set both EIPC and ID bits + ldsr r17, psw + + ;Restore caller address + sld.w 56[ep], r1 + ldsr r1, EIPC + ;Restore PSW + sld.w 60[ep], r1 + andi 0xffdf,r1,r1 + ldsr r1, EIPSW + sld.w 0[ep], r1 + dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} + + ;Return from interrupt starts new task! + reti + +//rseg CODE:CODE +//public rt_hw_context_switch_to +rt_hw_context_switch_to: + ;Load stack pointer of the task to run + ld.w 0[r1], sp ;load sp from struct + + ;Restore all Processor registers from stack and return from interrupt + jr OS_Restore_CPU_Context + +OSCtxSW: + SAVE_CPU_CTX ;Save all CPU registers + + mov rt_interrupt_from_thread, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + + mov rt_interrupt_to_thread, r1 + ld.w 0[r1], r1 + ld.w 0[r1], sp + + ;Restore all Processor registers from stack and return from interrupt + jr OS_Restore_CPU_Context + +rt_hw_context_switch_interrupt_do: + mov rt_thread_switch_interrupt_flag, r8 + mov 0, r9 + st.b r9, 0[r8] + + mov rt_interrupt_from_thread, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + + mov rt_interrupt_to_thread, r1 + ld.w 0[r1], r1 + ld.w 0[r1], sp + jr OS_Restore_CPU_Context + +OSTickIntr: + SAVE_CPU_CTX ;Save current task's registers + jarl rt_interrupt_enter,lp + jarl rt_tick_increase,lp + jarl rt_interrupt_leave,lp + + mov rt_thread_switch_interrupt_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be rt_hw_context_switch_interrupt_do + + jr OS_Restore_CPU_Context + +uarta1_int_r: + SAVE_CPU_CTX ;Save current task's registers + jarl rt_interrupt_enter,lp + jarl uarta1_receive_handler,lp + jarl rt_interrupt_leave,lp + + mov rt_thread_switch_interrupt_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be rt_hw_context_switch_interrupt_do + + jr OS_Restore_CPU_Context + + END diff --git a/libcpu/v850/70f34/context_iar.asm b/libcpu/v850/70f34/context_iar.asm index a384c2f0650e0e1917cd33c44078c703c7861d12..5a8c1da41a2192f6ad015ee3607805a22a4a58aa 100644 --- a/libcpu/v850/70f34/context_iar.asm +++ b/libcpu/v850/70f34/context_iar.asm @@ -1,174 +1,174 @@ -#include "macdefs.inc" - - name OS_Core - - COMMON INTVEC:CODE - -;******************************************************************** -; -; function: -; description: Trap 0x10 vector used for context switch -; Right now, all TRAPs to $1x are trated the same way -; - org 50h - jr OSCtxSW - - -;******************************************************************** -; -; function: -; description: Timer 40 compare match interrupt used for system -; tick interrupt -; - org 0x220 - jr OSTickIntr - - org 0x0520 - jr uarta1_int_r - - RSEG CODE(1) - - EXTERN rt_thread_switch_interrupt_flag - EXTERN rt_interrupt_from_thread - EXTERN rt_interrupt_to_thread - - EXTERN rt_interrupt_enter - EXTERN rt_interrupt_leave - EXTERN rt_tick_increase - EXTERN uarta1_receive_handler - - PUBLIC rt_hw_interrupt_disable - PUBLIC rt_hw_interrupt_enable - PUBLIC rt_hw_context_switch_to - PUBLIC OSCtxSW - PUBLIC OS_Restore_CPU_Context - -rt_hw_interrupt_disable: - stsr psw, r1 - di - jmp [lp] - -rt_hw_interrupt_enable: - ldsr r1, psw - jmp [lp] - -OS_Restore_CPU_Context: - mov sp, ep - sld.w 4[ep], r2 - sld.w 8[ep], r5 - sld.w 12[ep],r6 - sld.w 16[ep],r7 - sld.w 20[ep],r8 - sld.w 24[ep],r9 - sld.w 28[ep],r10 - sld.w 32[ep],r11 - sld.w 36[ep],r12 - sld.w 40[ep],r13 - sld.w 44[ep],r14 - sld.w 48[ep],r15 - sld.w 52[ep],r16 - - ;See what was the latest interruption (trap or interrupt) - stsr ecr, r17 ;Move ecr to r17 - mov 0x050,r1 - cmp r1, r17 ;If latest break was due to TRAP, set EP - be _SetEP - -_ClrEP: - mov 0x20, r17 ;Set only ID - ldsr r17, psw - - ;Restore caller address - sld.w 56[ep], r1 - ldsr r1, EIPC - ;Restore PSW - sld.w 60[ep], r1 - andi 0xffdf,r1,r1 - ldsr r1, EIPSW - sld.w 0[ep], r1 - dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} - - ;Return from interrupt starts new task! - reti - -_SetEP: - mov 0x60, r17 ;Set both EIPC and ID bits - ldsr r17, psw - - ;Restore caller address - sld.w 56[ep], r1 - ldsr r1, EIPC - ;Restore PSW - sld.w 60[ep], r1 - andi 0xffdf,r1,r1 - ldsr r1, EIPSW - sld.w 0[ep], r1 - dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} - - ;Return from interrupt starts new task! - reti - -//rseg CODE:CODE -//public rt_hw_context_switch_to -rt_hw_context_switch_to: - ;Load stack pointer of the task to run - ld.w 0[r1], sp ;load sp from struct - - ;Restore all Processor registers from stack and return from interrupt - jr OS_Restore_CPU_Context - -OSCtxSW: - SAVE_CPU_CTX ;Save all CPU registers - - mov rt_interrupt_from_thread, r21 - ld.w 0[r21], r21 - st.w sp, 0[r21] - - mov rt_interrupt_to_thread, r1 - ld.w 0[r1], r1 - ld.w 0[r1], sp - - ;Restore all Processor registers from stack and return from interrupt - jr OS_Restore_CPU_Context - -rt_hw_context_switch_interrupt_do: - mov rt_thread_switch_interrupt_flag, r8 - mov 0, r9 - st.b r9, 0[r8] - - mov rt_interrupt_from_thread, r21 - ld.w 0[r21], r21 - st.w sp, 0[r21] - - mov rt_interrupt_to_thread, r1 - ld.w 0[r1], r1 - ld.w 0[r1], sp - jr OS_Restore_CPU_Context - -OSTickIntr: - SAVE_CPU_CTX ;Save current task's registers - jarl rt_interrupt_enter,lp - jarl rt_tick_increase,lp - jarl rt_interrupt_leave,lp - - mov rt_thread_switch_interrupt_flag, r8 - ld.w 0[r8],r9 - cmp 1, r9 - be rt_hw_context_switch_interrupt_do - - jr OS_Restore_CPU_Context - -uarta1_int_r: - SAVE_CPU_CTX ;Save current task's registers - jarl rt_interrupt_enter,lp - jarl uarta1_receive_handler,lp - jarl rt_interrupt_leave,lp - - mov rt_thread_switch_interrupt_flag, r8 - ld.w 0[r8],r9 - cmp 1, r9 - be rt_hw_context_switch_interrupt_do - - jr OS_Restore_CPU_Context - - END +#include "macdefs.inc" + + name OS_Core + + COMMON INTVEC:CODE + +;******************************************************************** +; +; function: +; description: Trap 0x10 vector used for context switch +; Right now, all TRAPs to $1x are trated the same way +; + org 50h + jr OSCtxSW + + +;******************************************************************** +; +; function: +; description: Timer 40 compare match interrupt used for system +; tick interrupt +; + org 0x220 + jr OSTickIntr + + org 0x0520 + jr uarta1_int_r + + RSEG CODE(1) + + EXTERN rt_thread_switch_interrupt_flag + EXTERN rt_interrupt_from_thread + EXTERN rt_interrupt_to_thread + + EXTERN rt_interrupt_enter + EXTERN rt_interrupt_leave + EXTERN rt_tick_increase + EXTERN uarta1_receive_handler + + PUBLIC rt_hw_interrupt_disable + PUBLIC rt_hw_interrupt_enable + PUBLIC rt_hw_context_switch_to + PUBLIC OSCtxSW + PUBLIC OS_Restore_CPU_Context + +rt_hw_interrupt_disable: + stsr psw, r1 + di + jmp [lp] + +rt_hw_interrupt_enable: + ldsr r1, psw + jmp [lp] + +OS_Restore_CPU_Context: + mov sp, ep + sld.w 4[ep], r2 + sld.w 8[ep], r5 + sld.w 12[ep],r6 + sld.w 16[ep],r7 + sld.w 20[ep],r8 + sld.w 24[ep],r9 + sld.w 28[ep],r10 + sld.w 32[ep],r11 + sld.w 36[ep],r12 + sld.w 40[ep],r13 + sld.w 44[ep],r14 + sld.w 48[ep],r15 + sld.w 52[ep],r16 + + ;See what was the latest interruption (trap or interrupt) + stsr ecr, r17 ;Move ecr to r17 + mov 0x050,r1 + cmp r1, r17 ;If latest break was due to TRAP, set EP + be _SetEP + +_ClrEP: + mov 0x20, r17 ;Set only ID + ldsr r17, psw + + ;Restore caller address + sld.w 56[ep], r1 + ldsr r1, EIPC + ;Restore PSW + sld.w 60[ep], r1 + andi 0xffdf,r1,r1 + ldsr r1, EIPSW + sld.w 0[ep], r1 + dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} + + ;Return from interrupt starts new task! + reti + +_SetEP: + mov 0x60, r17 ;Set both EIPC and ID bits + ldsr r17, psw + + ;Restore caller address + sld.w 56[ep], r1 + ldsr r1, EIPC + ;Restore PSW + sld.w 60[ep], r1 + andi 0xffdf,r1,r1 + ldsr r1, EIPSW + sld.w 0[ep], r1 + dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} + + ;Return from interrupt starts new task! + reti + +//rseg CODE:CODE +//public rt_hw_context_switch_to +rt_hw_context_switch_to: + ;Load stack pointer of the task to run + ld.w 0[r1], sp ;load sp from struct + + ;Restore all Processor registers from stack and return from interrupt + jr OS_Restore_CPU_Context + +OSCtxSW: + SAVE_CPU_CTX ;Save all CPU registers + + mov rt_interrupt_from_thread, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + + mov rt_interrupt_to_thread, r1 + ld.w 0[r1], r1 + ld.w 0[r1], sp + + ;Restore all Processor registers from stack and return from interrupt + jr OS_Restore_CPU_Context + +rt_hw_context_switch_interrupt_do: + mov rt_thread_switch_interrupt_flag, r8 + mov 0, r9 + st.b r9, 0[r8] + + mov rt_interrupt_from_thread, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + + mov rt_interrupt_to_thread, r1 + ld.w 0[r1], r1 + ld.w 0[r1], sp + jr OS_Restore_CPU_Context + +OSTickIntr: + SAVE_CPU_CTX ;Save current task's registers + jarl rt_interrupt_enter,lp + jarl rt_tick_increase,lp + jarl rt_interrupt_leave,lp + + mov rt_thread_switch_interrupt_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be rt_hw_context_switch_interrupt_do + + jr OS_Restore_CPU_Context + +uarta1_int_r: + SAVE_CPU_CTX ;Save current task's registers + jarl rt_interrupt_enter,lp + jarl uarta1_receive_handler,lp + jarl rt_interrupt_leave,lp + + mov rt_thread_switch_interrupt_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be rt_hw_context_switch_interrupt_do + + jr OS_Restore_CPU_Context + + END diff --git a/libcpu/v850/70f34/cpuport.c b/libcpu/v850/70f34/cpuport.c index 806fe6426be954122d9d49c8655af96395ee95a8..f3c7624ee57a42583cb68f1fb605715ebf20df62 100644 --- a/libcpu/v850/70f34/cpuport.c +++ b/libcpu/v850/70f34/cpuport.c @@ -1,100 +1,100 @@ -/* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-02-23 Bernard the first version - * 2012-09-23 lgnq set the texit to R31 - */ - -#include - -extern volatile rt_uint8_t rt_interrupt_nest; - -/* switch flag on interrupt and thread pointer to save switch record */ -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, - void *parameter, - rt_uint8_t *stack_addr, - void *texit) -{ - rt_uint32_t *stk; - - stk = (rt_uint32_t *)stack_addr; /* Load stack pointer */ - - *(--stk) = (rt_uint32_t)0x23232323; /* r23 */ - *(--stk) = (rt_uint32_t)0x24242424; /* r24 */ - *(--stk) = (rt_uint32_t)0x25252525; /* r25 */ - *(--stk) = (rt_uint32_t)0x26262626; /* r26 */ - *(--stk) = (rt_uint32_t)0x27272727; /* r27 */ - *(--stk) = (rt_uint32_t)0x28282828; /* r28 */ - *(--stk) = (rt_uint32_t)0x29292929; /* r29 */ - *(--stk) = (rt_uint32_t)0x30303030; /* r30 */ - *(--stk) = (rt_uint32_t)texit; /* r31 */ - *(--stk) = (rt_uint32_t)0x00000000; /* Task PSW = Interrupts enabled */ - *(--stk) = (rt_uint32_t)tentry; /* Task's PC */ - *(--stk) = (rt_uint32_t)0x16161616; /* r16 */ - *(--stk) = (rt_uint32_t)0x15151515; /* r15 */ - *(--stk) = (rt_uint32_t)0x14141414; /* r14 */ - *(--stk) = (rt_uint32_t)0x13131313; /* r13 */ - *(--stk) = (rt_uint32_t)0x12121212; /* r12 */ - *(--stk) = (rt_uint32_t)0x11111111; /* r11 */ - *(--stk) = (rt_uint32_t)0x10101010; /* r10 */ - *(--stk) = (rt_uint32_t)0x09090909; /* r9 */ - *(--stk) = (rt_uint32_t)0x08080808; /* r8 */ - *(--stk) = (rt_uint32_t)0x07070707; /* r7 */ - *(--stk) = (rt_uint32_t)0x06060606; /* r6 */ - *(--stk) = (rt_uint32_t)0x05050505; /* r5 */ - *(--stk) = (rt_uint32_t)0x02020202; /* r2 */ - *(--stk) = (rt_uint32_t)parameter; /* r1 */ - - return ((rt_uint8_t *)stk); -} - -void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) -{ - rt_interrupt_from_thread = from; - rt_interrupt_to_thread = to; - asm("trap 0x10"); -} - -void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) -{ - if (rt_thread_switch_interrupt_flag != 1) - { - rt_thread_switch_interrupt_flag = 1; - rt_interrupt_from_thread = from; - } - rt_interrupt_to_thread = to; -} +/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-23 Bernard the first version + * 2012-09-23 lgnq set the texit to R31 + */ + +#include + +extern volatile rt_uint8_t rt_interrupt_nest; + +/* switch flag on interrupt and thread pointer to save switch record */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + rt_uint32_t *stk; + + stk = (rt_uint32_t *)stack_addr; /* Load stack pointer */ + + *(--stk) = (rt_uint32_t)0x23232323; /* r23 */ + *(--stk) = (rt_uint32_t)0x24242424; /* r24 */ + *(--stk) = (rt_uint32_t)0x25252525; /* r25 */ + *(--stk) = (rt_uint32_t)0x26262626; /* r26 */ + *(--stk) = (rt_uint32_t)0x27272727; /* r27 */ + *(--stk) = (rt_uint32_t)0x28282828; /* r28 */ + *(--stk) = (rt_uint32_t)0x29292929; /* r29 */ + *(--stk) = (rt_uint32_t)0x30303030; /* r30 */ + *(--stk) = (rt_uint32_t)texit; /* r31 */ + *(--stk) = (rt_uint32_t)0x00000000; /* Task PSW = Interrupts enabled */ + *(--stk) = (rt_uint32_t)tentry; /* Task's PC */ + *(--stk) = (rt_uint32_t)0x16161616; /* r16 */ + *(--stk) = (rt_uint32_t)0x15151515; /* r15 */ + *(--stk) = (rt_uint32_t)0x14141414; /* r14 */ + *(--stk) = (rt_uint32_t)0x13131313; /* r13 */ + *(--stk) = (rt_uint32_t)0x12121212; /* r12 */ + *(--stk) = (rt_uint32_t)0x11111111; /* r11 */ + *(--stk) = (rt_uint32_t)0x10101010; /* r10 */ + *(--stk) = (rt_uint32_t)0x09090909; /* r9 */ + *(--stk) = (rt_uint32_t)0x08080808; /* r8 */ + *(--stk) = (rt_uint32_t)0x07070707; /* r7 */ + *(--stk) = (rt_uint32_t)0x06060606; /* r6 */ + *(--stk) = (rt_uint32_t)0x05050505; /* r5 */ + *(--stk) = (rt_uint32_t)0x02020202; /* r2 */ + *(--stk) = (rt_uint32_t)parameter; /* r1 */ + + return ((rt_uint8_t *)stk); +} + +void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) +{ + rt_interrupt_from_thread = from; + rt_interrupt_to_thread = to; + asm("trap 0x10"); +} + +void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) +{ + if (rt_thread_switch_interrupt_flag != 1) + { + rt_thread_switch_interrupt_flag = 1; + rt_interrupt_from_thread = from; + } + rt_interrupt_to_thread = to; +} diff --git a/libcpu/v850/70f34/macdefs.inc b/libcpu/v850/70f34/macdefs.inc index 4a0c4d4823308f811a3ae328aea226b3b42d9dd3..e42b20e3d670dd6351ab27514121be8de5faab0b 100644 --- a/libcpu/v850/70f34/macdefs.inc +++ b/libcpu/v850/70f34/macdefs.inc @@ -1,125 +1,125 @@ -; -; These are the macros used by the v850 port of the uCOS/II. -; - - - - - -;******************************************************************** -; function: -; description: -; --- Modifies ---------------------------------------------- -; IO : -; Mem: -; CPU: -; --- Uses -------------------------------------------------- -; IO : -; Mem: -; --- Input ------------------------------------------------- -; --- Output ------------------------------------------------ -; --- Notes ------------------------------------------------- -;==================================================================== - -SAVE_CPU_CTX MACRO - ;Save all registers on entry (r3 is the stack pointer) - prepare {r23,r24,r25,r26,r27,r28,r29,r30,r31},(8+(4*14)) ;Add 8 bytes for 2 more registers - mov sp, ep - sst.w r1, 0[ep] - sst.w r2, 4[ep] - sst.w r5, 8[ep] - sst.w r6, 12[ep] - sst.w r7, 16[ep] - sst.w r8, 20[ep] - sst.w r9, 24[ep] - sst.w r10, 28[ep] - sst.w r11, 32[ep] - sst.w r12, 36[ep] - sst.w r13, 40[ep] - sst.w r14, 44[ep] - sst.w r15, 48[ep] - sst.w r16, 52[ep] - ;Save caller's PC - stsr EIPC, r1 - sst.w r1, 56[ep] - ;Save caller's PSW - stsr EIPSW, r1 - sst.w r1, 60[ep] - - ENDMAC - - - - - -;******************************************************************** -; function: -; description: -; --- Modifies ---------------------------------------------- -; IO : -; Mem: -; CPU: -; --- Uses -------------------------------------------------- -; IO : -; Mem: -; --- Input ------------------------------------------------- -; --- Output ------------------------------------------------ -; --- Notes ------------------------------------------------- -;==================================================================== -SAVE_SP MACRO - ;Save stack pointer on OSTCBCur->OSTCBStkPtr (OSTCBStkPtr=0) - mov OSTCBCur, r21 - ld.w 0[r21], r21 - st.w sp, 0[r21] - ENDMAC - - - -;******************************************************************** -; function: -; description: -; --- Modifies ---------------------------------------------- -; IO : -; Mem: -; CPU: -; --- Uses -------------------------------------------------- -; IO : -; Mem: -; --- Input ------------------------------------------------- -; --- Output ------------------------------------------------ -; --- Notes ------------------------------------------------- -;==================================================================== -ISR_ENTRY MACRO - LOCAL _DontSaveSP - - ;Save all CPU registers according to the standard stack frame - SAVE_CPU_CTX - - mov OSIntNesting, r1 ;Increment OSNesting by one - LD.BU 0[r1],r2 - add 1, r2 - ST.B r2, 0[r1] - cmp 1, r2 ;If OSNesting==1 save SP in current TCB - bne _DontSaveSP - SAVE_SP -_DontSaveSP: - ENDMAC - -;******************************************************************** -; function: -; description: -; --- Modifies ---------------------------------------------- -; IO : -; Mem: -; CPU: -; --- Uses -------------------------------------------------- -; IO : -; Mem: -; --- Input ------------------------------------------------- -; --- Output ------------------------------------------------ -; --- Notes ------------------------------------------------- -;==================================================================== -ISR_EXIT MACRO - jarl OSIntExit, lp ;Call OSIntExit() - jr OS_Restore_CPU_Context ;Restore processors registers and execute RETI - ENDMAC +; +; These are the macros used by the v850 port of the uCOS/II. +; + + + + + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== + +SAVE_CPU_CTX MACRO + ;Save all registers on entry (r3 is the stack pointer) + prepare {r23,r24,r25,r26,r27,r28,r29,r30,r31},(8+(4*14)) ;Add 8 bytes for 2 more registers + mov sp, ep + sst.w r1, 0[ep] + sst.w r2, 4[ep] + sst.w r5, 8[ep] + sst.w r6, 12[ep] + sst.w r7, 16[ep] + sst.w r8, 20[ep] + sst.w r9, 24[ep] + sst.w r10, 28[ep] + sst.w r11, 32[ep] + sst.w r12, 36[ep] + sst.w r13, 40[ep] + sst.w r14, 44[ep] + sst.w r15, 48[ep] + sst.w r16, 52[ep] + ;Save caller's PC + stsr EIPC, r1 + sst.w r1, 56[ep] + ;Save caller's PSW + stsr EIPSW, r1 + sst.w r1, 60[ep] + + ENDMAC + + + + + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== +SAVE_SP MACRO + ;Save stack pointer on OSTCBCur->OSTCBStkPtr (OSTCBStkPtr=0) + mov OSTCBCur, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + ENDMAC + + + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== +ISR_ENTRY MACRO + LOCAL _DontSaveSP + + ;Save all CPU registers according to the standard stack frame + SAVE_CPU_CTX + + mov OSIntNesting, r1 ;Increment OSNesting by one + LD.BU 0[r1],r2 + add 1, r2 + ST.B r2, 0[r1] + cmp 1, r2 ;If OSNesting==1 save SP in current TCB + bne _DontSaveSP + SAVE_SP +_DontSaveSP: + ENDMAC + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== +ISR_EXIT MACRO + jarl OSIntExit, lp ;Call OSIntExit() + jr OS_Restore_CPU_Context ;Restore processors registers and execute RETI + ENDMAC diff --git a/libcpu/xilinx/microblaze/serial.h b/libcpu/xilinx/microblaze/serial.h index 090efa84e5a88b36589b4a39cd461a33f7fce43a..976138bbf828263aadaf7d466829c3e84859b598 100755 --- a/libcpu/xilinx/microblaze/serial.h +++ b/libcpu/xilinx/microblaze/serial.h @@ -1,6 +1,6 @@ -#ifndef __RT_SERIAL_H__ -#define __RT_SERIAL_H__ -#include "xuartlite_l.h" -#include "xparameters.h" - -#endif +#ifndef __RT_SERIAL_H__ +#define __RT_SERIAL_H__ +#include "xuartlite_l.h" +#include "xparameters.h" + +#endif diff --git a/src/irq.c b/src/irq.c index de36868d87f8550b40057e4cde6f0b534c8a3e4d..334b4b9e4ad0e1d88ede8714d00253f90009bf77 100644 --- a/src/irq.c +++ b/src/irq.c @@ -44,7 +44,7 @@ void rt_interrupt_enter(void) rt_interrupt_nest ++; rt_hw_interrupt_enable(level); } -RTM_EXPORT(rt_interrupt_enter); +RTM_EXPORT(rt_interrupt_enter); /** * This function will be invoked by BSP, when leave interrupt service routine @@ -64,7 +64,7 @@ void rt_interrupt_leave(void) rt_interrupt_nest --; rt_hw_interrupt_enable(level); } -RTM_EXPORT(rt_interrupt_leave); +RTM_EXPORT(rt_interrupt_leave); /** * This function will return the nest of interrupt. @@ -78,10 +78,10 @@ rt_uint8_t rt_interrupt_get_nest(void) { return rt_interrupt_nest; } -RTM_EXPORT(rt_interrupt_get_nest); - -RTM_EXPORT(rt_hw_interrupt_disable); -RTM_EXPORT(rt_hw_interrupt_enable); +RTM_EXPORT(rt_interrupt_get_nest); + +RTM_EXPORT(rt_hw_interrupt_disable); +RTM_EXPORT(rt_hw_interrupt_enable); /*@}*/ diff --git a/tools/sconsui.py b/tools/sconsui.py index eb559a9b130d8c00457bde919400fff1864f56a9..eddccb49f4c3963e1669f3510b487148f13eca9e 100644 --- a/tools/sconsui.py +++ b/tools/sconsui.py @@ -1,452 +1,452 @@ -#! /usr/bin/env python -#coding=utf-8 - -import sys - -py2 = py30 = py31 = False -version = sys.hexversion -if version >= 0x020600F0 and version < 0x03000000 : - py2 = True # Python 2.6 or 2.7 - from Tkinter import * - import ttk -elif version >= 0x03000000 and version < 0x03010000 : - py30 = True - from tkinter import * - import ttk -elif version >= 0x03010000: - py31 = True - from tkinter import * - import tkinter.ttk as ttk -else: - print (""" - You do not have a version of python supporting ttk widgets.. - You need a version >= 2.6 to execute PAGE modules. - """) - sys.exit() - -import ScrolledText -import tkFileDialog -import tkMessageBox - -import os -import threading -import platform - -builder = None -executor = None -lock = None - -class CmdExecutor(threading.Thread): - def __init__(self, cmd, output): - threading.Thread.__init__(self) - self.cmd = cmd - self.child = None - - def run(self): - global executor, builder, lock - - if platform.system() == 'Windows': - try: - from win32spawn import Win32Spawn - subprocess = Win32Spawn(self.cmd) - subprocess.start_pipe() - - builder.progressbar.start() - while not subprocess.is_terminated or subprocess.qsize() > 0: - try: - line = subprocess.get(timeout=1) - line = line.replace('\r', '') - if line: - lock.acquire() - builder.output.see(END) - builder.output.insert(END, line) - lock.release() - except: - pass - - builder.progressbar.stop() - except: - pass - - executor = None - if builder.is_makeing_project: - builder.output.insert(END, 'Done') - builder.is_makeing_project = False - -def ExecCmd(cmd): - global executor - if executor: - print 'last task does not exit' - return - - executor = CmdExecutor(cmd, builder) - executor.start() - -class DirSelectBox(ttk.Frame): - def __init__(self, master=None, **kw): - ttk.Frame.__init__(self, master, **kw) - self.dir_var = StringVar() - self.entry = ttk.Entry(self, textvariable = self.dir_var) - self.entry.pack(fill=BOTH, expand=1,side=LEFT) - self.entry.configure(width = 50) - - self.browser_button = ttk.Button(self, text="Browser", command=self.browser) - self.browser_button.pack(side=RIGHT) - - def browser(self): - dir = tkFileDialog.askdirectory(parent=self, title='Open directory', initialdir=self.dir_var.get()) - if dir != '': - self.dir_var.set(dir) - - def set_path(self, path): - path = path.replace('\\', '/') - self.dir_var.set(path) - - def get_path(self): - return self.dir_var.get() - -COMPILER = [ - ("GNU GCC", "GCC"), - ("Keil ARMCC", "ARMCC"), - ("IAR Compiler", "IAR"), - ] - -IDE = [ - ('Keil MDK4', 'mdk4'), - ('Keil MDK', 'mdk'), - ('IAR Compiler', 'iar') -] - -class SconsUI(): - def __init__(self, master=None): - style = ttk.Style() - theme = style.theme_use() - default = style.lookup(theme, 'background') - master.configure(background=default) - - notebook = ttk.Notebook(master) - notebook.pack(fill=BOTH, padx=5, pady=5) - - # building page - page_building = ttk.Frame(notebook) - notebook.add(page_building, padding=3) - notebook.tab(0, text='Build', underline="-1") - self.setup_building_ui(page_building) - self.building_page = page_building - - # make project page - page_project = ttk.Frame(notebook) - notebook.add(page_project, padding = 3) - notebook.tab(1, text = 'Project', underline = '-1') - self.setup_project_ui(page_project) - self.project_page = page_project - - # setting page - page_setting = ttk.Frame(notebook) - notebook.add(page_setting, padding = 3) - notebook.tab(2, text = 'Setting', underline = '-1') - self.setup_setting_ui(page_setting) - self.setting_page = page_setting - - padding = ttk.Frame(master) - padding.pack(fill=X) - quit = ttk.Button(padding, text='Quit', command = self.quit) - quit.pack(side=RIGHT) - - # set notebook to self - self.notebook = notebook - - # read setting - self.read_setting() - self.is_makeing_project = False - - def read_setting(self): - import platform - import os - - home = '' - if platform.system() == 'Windows': - driver = os.environ['HOMEDRIVE'] - home = os.environ['HOMEPATH'] - home = os.path.join(driver, home) - else: - home = os.environ['HOME'] - - setting_path = os.path.join(home, '.rtt_scons') - if os.path.exists(setting_path): - setting = file(os.path.join(home, '.rtt_scons')) - for line in setting: - line = line.replace('\n', '') - line = line.replace('\r', '') - if line.find('=') != -1: - items = line.split('=') - if items[0] == 'RTTRoot': - self.RTTRoot.set_path(items[1]) - elif items[0] == 'BSPRoot': - self.BSPRoot.set_path(items[1]) - elif items[0] == 'compiler': - compiler = items[1] - else: - self.CompilersPath[items[0]].set_path(items[1]) - setting.close() - - # set RT-Thread Root Directory according environ - if os.environ.has_key('RTT_ROOT'): - self.RTTRoot.set_path(os.environ['RTT_ROOT']) - - if self.RTTRoot.get_path() == '': - rtt_root = '' - # detect RT-Thread directory - if os.path.exists(os.path.join('..', 'include', 'rtthread.h')): - rtt_root = os.path.join('..') - elif os.path.exists(os.path.join('..', '..', 'include', 'rtthread.h')): - rtt_root = os.path.join('..', '..') - if rtt_root: - self.RTTRoot.set_path(os.path.abspath(rtt_root)) - - # detect compiler path - if platform.system() == 'Windows': - # Keil MDK - if not self.CompilersPath['ARMCC'].get_path(): - if os.path.exists('C:\\Keil'): - self.CompilersPath['ARMCC'].set_path('C:\\Keil') - elif os.path.exists('D:\\Keil'): - self.CompilersPath['ARMCC'].set_path('D:\\Keil') - elif os.path.exists('E:\\Keil'): - self.CompilersPath['ARMCC'].set_path('E:\\Keil') - elif os.path.exists('F:\\Keil'): - self.CompilersPath['ARMCC'].set_path('F:\\Keil') - elif os.path.exists('G:\\Keil'): - self.CompilersPath['ARMCC'].set_path('G:\\Keil') - - # GNU GCC - if not self.CompilersPath['GCC'].get_path(): - paths = os.environ['PATH'] - paths = paths.split(';') - - for path in paths: - if path.find('CodeSourcery') != -1: - self.CompilersPath['GCC'].set_path(path) - break - elif path.find('GNU Tools ARM Embedded') != -1: - self.CompilersPath['GCC'].set_path(path) - break - - def save_setting(self): - import platform - import os - - home = '' - if platform.system() == 'Windows': - driver = os.environ['HOMEDRIVE'] - home = os.environ['HOMEPATH'] - home = os.path.join(driver, home) - else: - home = os.environ['HOME'] - - setting = file(os.path.join(home, '.rtt_scons'), 'wb+') - # current comiler - # line = '%s=%s\n' % ('compiler', self.compilers.get())) - line = '%s=%s\n' % ('compiler', 'iar') - setting.write(line) - - # RTT Root Folder - if self.RTTRoot.get_path(): - line = '%s=%s\n' % ('RTTRoot', self.RTTRoot.get_path()) - setting.write(line) - - # BSP Root Folder - if self.BSPRoot.get_path(): - line = '%s=%s\n' % ('BSPRoot', self.BSPRoot.get_path()) - setting.write(line) - - for (compiler, path) in self.CompilersPath.iteritems(): - if path.get_path(): - line = '%s=%s\n' % (compiler, path.get_path()) - setting.write(line) - - setting.close() - tkMessageBox.showinfo("RT-Thread SCons UI", - "Save setting sucessfully") - - def setup_building_ui(self, frame): - padding = ttk.Frame(frame) - padding.pack(fill=X) - - button = ttk.Button(padding, text='Clean', command=self.do_clean) - button.pack(side=RIGHT) - button = ttk.Button(padding, text='Build', command=self.do_build) - button.pack(side=RIGHT) - label = ttk.Label(padding, relief = 'flat', text = 'Click Build or Clean to build or clean system -->') - label.pack(side=RIGHT, ipady = 5) - - self.progressbar = ttk.Progressbar(frame) - self.progressbar.pack(fill=X) - - separator = ttk.Separator(frame) - separator.pack(fill=X) - - self.output = ScrolledText.ScrolledText(frame) - self.output.pack(fill=X) - - def setup_project_ui(self, frame): - label = ttk.Label(frame, relief = 'flat', text = 'Choose Integrated Development Environment:') - label.pack(fill=X, pady = 5) - - separator = ttk.Separator(frame) - separator.pack(fill=X) - - self.ide = StringVar() - self.ide.set("mdk4") # initialize - - for text,mode in IDE: - radiobutton = ttk.Radiobutton(frame, text=text, variable = self.ide, value = mode) - radiobutton.pack(fill=X, padx=10) - - bottom = ttk.Frame(frame) - bottom.pack(side=BOTTOM, fill=X) - button = ttk.Button(bottom, text="Make Project", command = self.do_make_project) - button.pack(side=RIGHT, padx = 10, pady = 10) - - def setup_setting_ui(self, frame): - row = 0 - label = ttk.Label (frame, relief = 'flat', text='RT-Thread Root Folder:') - label.grid(row=row, column=0,ipadx=5, ipady=5, padx = 5) - - self.RTTRoot = DirSelectBox(frame) - self.RTTRoot.grid(row=row, column=1, sticky=E+W) - row = row + 1 - - label = ttk.Label (frame, relief = 'flat', text='Board Support Folder:') - label.grid(row=row, column=0,ipadx=5, ipady=5, padx = 5) - - self.BSPRoot = DirSelectBox(frame) - self.BSPRoot.grid(row=row, column=1, sticky=E+W) - row = row + 1 - - label = ttk.Label (frame, relief='flat', text='Toolchain:') - label.grid(row=row, column=0,ipadx=5, ipady=5, sticky=E+W) - row = row + 1 - - separator = ttk.Separator(frame) - separator.grid(row = row, column = 0, columnspan = 2, sticky = E+W) - row = row + 1 - - self.compilers = StringVar() - self.compilers.set("GCC") # initialize - - self.CompilersPath = {} - - for text,compiler in COMPILER: - radiobutton = ttk.Radiobutton(frame, text=text, variable = self.compilers, value = compiler) - radiobutton.grid(row=row, column = 0, sticky = W, ipadx = 5, ipady = 5, padx = 20) - - self.CompilersPath[compiler] = DirSelectBox(frame) - self.CompilersPath[compiler].grid(row=row, column=1, sticky=E+W) - row = row + 1 - - button = ttk.Button(frame, text='Save Setting', command = self.save_setting) - button.grid(row = row, column = 1, sticky = E) - row = row + 1 - - def prepare_build(self): - # get compiler - compiler = self.compilers.get() - if compiler == 'GCC': - compiler = 'gcc' - elif compiler == 'ARMCC': - compiler = 'keil' - elif compiler == 'IAR': - compiler = 'iar' - - # get RTT Root - rtt_root = self.RTTRoot.get_path() - # get Compiler path - exec_path = self.CompilersPath[self.compilers.get()].get_path() - - command = '' - - os.environ['RTT_ROOT'] = rtt_root - os.environ['RTT_CC'] = compiler - os.environ['RTT_EXEC_PATH'] = exec_path - - return command - - def check_path(self): - result = True - - if self.BSPRoot.get_path() == '': - result = False - - if self.RTTRoot.get_path() == '': - result = False - - if not result: - tkMessageBox.showinfo("RT-Thread SCons UI", - "Folder is empty, please choose correct directory.") - - return result - - def do_build(self): - self.prepare_build() - command = 'scons' - - if not self.check_path(): - return - - bsp = self.BSPRoot.get_path() - os.chdir(bsp) - - self.output.delete(1.0, END) - self.output.insert(END, 'building project...\n') - ExecCmd(command) - - def do_clean(self): - self.prepare_build() - command = 'scons -c' - - if not self.check_path(): - return - - bsp = self.BSPRoot.get_path() - os.chdir(bsp) - - self.output.delete(1.0, END) - self.output.insert(END, 'clean project...\n') - ExecCmd(command) - - def do_make_project(self): - ide = self.ide.get() - self.prepare_build() - command = 'scons --target=%s -s' % ide - - if not self.check_path(): - return - - # select build page - self.notebook.select(self.building_page) - - bsp = self.BSPRoot.get_path() - os.chdir(bsp) - - self.output.delete(1.0, END) - self.output.insert(END, 'Generate project ...\n') - self.is_makeing_project = True - ExecCmd(command) - - def quit(self): - exit(0) - -def StartSConsUI(path=None): - global val, root, builder, lock - root = Tk() - root.title('RT-Thread SCons UI') - #root.geometrygeometry('590x510+50+50') - lock = threading.RLock() - builder = SconsUI(root) - if path: - builder.BSPRoot.set_path(path) - root.mainloop() - -if __name__ == '__main__': - StartSConsUI() +#! /usr/bin/env python +#coding=utf-8 + +import sys + +py2 = py30 = py31 = False +version = sys.hexversion +if version >= 0x020600F0 and version < 0x03000000 : + py2 = True # Python 2.6 or 2.7 + from Tkinter import * + import ttk +elif version >= 0x03000000 and version < 0x03010000 : + py30 = True + from tkinter import * + import ttk +elif version >= 0x03010000: + py31 = True + from tkinter import * + import tkinter.ttk as ttk +else: + print (""" + You do not have a version of python supporting ttk widgets.. + You need a version >= 2.6 to execute PAGE modules. + """) + sys.exit() + +import ScrolledText +import tkFileDialog +import tkMessageBox + +import os +import threading +import platform + +builder = None +executor = None +lock = None + +class CmdExecutor(threading.Thread): + def __init__(self, cmd, output): + threading.Thread.__init__(self) + self.cmd = cmd + self.child = None + + def run(self): + global executor, builder, lock + + if platform.system() == 'Windows': + try: + from win32spawn import Win32Spawn + subprocess = Win32Spawn(self.cmd) + subprocess.start_pipe() + + builder.progressbar.start() + while not subprocess.is_terminated or subprocess.qsize() > 0: + try: + line = subprocess.get(timeout=1) + line = line.replace('\r', '') + if line: + lock.acquire() + builder.output.see(END) + builder.output.insert(END, line) + lock.release() + except: + pass + + builder.progressbar.stop() + except: + pass + + executor = None + if builder.is_makeing_project: + builder.output.insert(END, 'Done') + builder.is_makeing_project = False + +def ExecCmd(cmd): + global executor + if executor: + print 'last task does not exit' + return + + executor = CmdExecutor(cmd, builder) + executor.start() + +class DirSelectBox(ttk.Frame): + def __init__(self, master=None, **kw): + ttk.Frame.__init__(self, master, **kw) + self.dir_var = StringVar() + self.entry = ttk.Entry(self, textvariable = self.dir_var) + self.entry.pack(fill=BOTH, expand=1,side=LEFT) + self.entry.configure(width = 50) + + self.browser_button = ttk.Button(self, text="Browser", command=self.browser) + self.browser_button.pack(side=RIGHT) + + def browser(self): + dir = tkFileDialog.askdirectory(parent=self, title='Open directory', initialdir=self.dir_var.get()) + if dir != '': + self.dir_var.set(dir) + + def set_path(self, path): + path = path.replace('\\', '/') + self.dir_var.set(path) + + def get_path(self): + return self.dir_var.get() + +COMPILER = [ + ("GNU GCC", "GCC"), + ("Keil ARMCC", "ARMCC"), + ("IAR Compiler", "IAR"), + ] + +IDE = [ + ('Keil MDK4', 'mdk4'), + ('Keil MDK', 'mdk'), + ('IAR Compiler', 'iar') +] + +class SconsUI(): + def __init__(self, master=None): + style = ttk.Style() + theme = style.theme_use() + default = style.lookup(theme, 'background') + master.configure(background=default) + + notebook = ttk.Notebook(master) + notebook.pack(fill=BOTH, padx=5, pady=5) + + # building page + page_building = ttk.Frame(notebook) + notebook.add(page_building, padding=3) + notebook.tab(0, text='Build', underline="-1") + self.setup_building_ui(page_building) + self.building_page = page_building + + # make project page + page_project = ttk.Frame(notebook) + notebook.add(page_project, padding = 3) + notebook.tab(1, text = 'Project', underline = '-1') + self.setup_project_ui(page_project) + self.project_page = page_project + + # setting page + page_setting = ttk.Frame(notebook) + notebook.add(page_setting, padding = 3) + notebook.tab(2, text = 'Setting', underline = '-1') + self.setup_setting_ui(page_setting) + self.setting_page = page_setting + + padding = ttk.Frame(master) + padding.pack(fill=X) + quit = ttk.Button(padding, text='Quit', command = self.quit) + quit.pack(side=RIGHT) + + # set notebook to self + self.notebook = notebook + + # read setting + self.read_setting() + self.is_makeing_project = False + + def read_setting(self): + import platform + import os + + home = '' + if platform.system() == 'Windows': + driver = os.environ['HOMEDRIVE'] + home = os.environ['HOMEPATH'] + home = os.path.join(driver, home) + else: + home = os.environ['HOME'] + + setting_path = os.path.join(home, '.rtt_scons') + if os.path.exists(setting_path): + setting = file(os.path.join(home, '.rtt_scons')) + for line in setting: + line = line.replace('\n', '') + line = line.replace('\r', '') + if line.find('=') != -1: + items = line.split('=') + if items[0] == 'RTTRoot': + self.RTTRoot.set_path(items[1]) + elif items[0] == 'BSPRoot': + self.BSPRoot.set_path(items[1]) + elif items[0] == 'compiler': + compiler = items[1] + else: + self.CompilersPath[items[0]].set_path(items[1]) + setting.close() + + # set RT-Thread Root Directory according environ + if os.environ.has_key('RTT_ROOT'): + self.RTTRoot.set_path(os.environ['RTT_ROOT']) + + if self.RTTRoot.get_path() == '': + rtt_root = '' + # detect RT-Thread directory + if os.path.exists(os.path.join('..', 'include', 'rtthread.h')): + rtt_root = os.path.join('..') + elif os.path.exists(os.path.join('..', '..', 'include', 'rtthread.h')): + rtt_root = os.path.join('..', '..') + if rtt_root: + self.RTTRoot.set_path(os.path.abspath(rtt_root)) + + # detect compiler path + if platform.system() == 'Windows': + # Keil MDK + if not self.CompilersPath['ARMCC'].get_path(): + if os.path.exists('C:\\Keil'): + self.CompilersPath['ARMCC'].set_path('C:\\Keil') + elif os.path.exists('D:\\Keil'): + self.CompilersPath['ARMCC'].set_path('D:\\Keil') + elif os.path.exists('E:\\Keil'): + self.CompilersPath['ARMCC'].set_path('E:\\Keil') + elif os.path.exists('F:\\Keil'): + self.CompilersPath['ARMCC'].set_path('F:\\Keil') + elif os.path.exists('G:\\Keil'): + self.CompilersPath['ARMCC'].set_path('G:\\Keil') + + # GNU GCC + if not self.CompilersPath['GCC'].get_path(): + paths = os.environ['PATH'] + paths = paths.split(';') + + for path in paths: + if path.find('CodeSourcery') != -1: + self.CompilersPath['GCC'].set_path(path) + break + elif path.find('GNU Tools ARM Embedded') != -1: + self.CompilersPath['GCC'].set_path(path) + break + + def save_setting(self): + import platform + import os + + home = '' + if platform.system() == 'Windows': + driver = os.environ['HOMEDRIVE'] + home = os.environ['HOMEPATH'] + home = os.path.join(driver, home) + else: + home = os.environ['HOME'] + + setting = file(os.path.join(home, '.rtt_scons'), 'wb+') + # current comiler + # line = '%s=%s\n' % ('compiler', self.compilers.get())) + line = '%s=%s\n' % ('compiler', 'iar') + setting.write(line) + + # RTT Root Folder + if self.RTTRoot.get_path(): + line = '%s=%s\n' % ('RTTRoot', self.RTTRoot.get_path()) + setting.write(line) + + # BSP Root Folder + if self.BSPRoot.get_path(): + line = '%s=%s\n' % ('BSPRoot', self.BSPRoot.get_path()) + setting.write(line) + + for (compiler, path) in self.CompilersPath.iteritems(): + if path.get_path(): + line = '%s=%s\n' % (compiler, path.get_path()) + setting.write(line) + + setting.close() + tkMessageBox.showinfo("RT-Thread SCons UI", + "Save setting sucessfully") + + def setup_building_ui(self, frame): + padding = ttk.Frame(frame) + padding.pack(fill=X) + + button = ttk.Button(padding, text='Clean', command=self.do_clean) + button.pack(side=RIGHT) + button = ttk.Button(padding, text='Build', command=self.do_build) + button.pack(side=RIGHT) + label = ttk.Label(padding, relief = 'flat', text = 'Click Build or Clean to build or clean system -->') + label.pack(side=RIGHT, ipady = 5) + + self.progressbar = ttk.Progressbar(frame) + self.progressbar.pack(fill=X) + + separator = ttk.Separator(frame) + separator.pack(fill=X) + + self.output = ScrolledText.ScrolledText(frame) + self.output.pack(fill=X) + + def setup_project_ui(self, frame): + label = ttk.Label(frame, relief = 'flat', text = 'Choose Integrated Development Environment:') + label.pack(fill=X, pady = 5) + + separator = ttk.Separator(frame) + separator.pack(fill=X) + + self.ide = StringVar() + self.ide.set("mdk4") # initialize + + for text,mode in IDE: + radiobutton = ttk.Radiobutton(frame, text=text, variable = self.ide, value = mode) + radiobutton.pack(fill=X, padx=10) + + bottom = ttk.Frame(frame) + bottom.pack(side=BOTTOM, fill=X) + button = ttk.Button(bottom, text="Make Project", command = self.do_make_project) + button.pack(side=RIGHT, padx = 10, pady = 10) + + def setup_setting_ui(self, frame): + row = 0 + label = ttk.Label (frame, relief = 'flat', text='RT-Thread Root Folder:') + label.grid(row=row, column=0,ipadx=5, ipady=5, padx = 5) + + self.RTTRoot = DirSelectBox(frame) + self.RTTRoot.grid(row=row, column=1, sticky=E+W) + row = row + 1 + + label = ttk.Label (frame, relief = 'flat', text='Board Support Folder:') + label.grid(row=row, column=0,ipadx=5, ipady=5, padx = 5) + + self.BSPRoot = DirSelectBox(frame) + self.BSPRoot.grid(row=row, column=1, sticky=E+W) + row = row + 1 + + label = ttk.Label (frame, relief='flat', text='Toolchain:') + label.grid(row=row, column=0,ipadx=5, ipady=5, sticky=E+W) + row = row + 1 + + separator = ttk.Separator(frame) + separator.grid(row = row, column = 0, columnspan = 2, sticky = E+W) + row = row + 1 + + self.compilers = StringVar() + self.compilers.set("GCC") # initialize + + self.CompilersPath = {} + + for text,compiler in COMPILER: + radiobutton = ttk.Radiobutton(frame, text=text, variable = self.compilers, value = compiler) + radiobutton.grid(row=row, column = 0, sticky = W, ipadx = 5, ipady = 5, padx = 20) + + self.CompilersPath[compiler] = DirSelectBox(frame) + self.CompilersPath[compiler].grid(row=row, column=1, sticky=E+W) + row = row + 1 + + button = ttk.Button(frame, text='Save Setting', command = self.save_setting) + button.grid(row = row, column = 1, sticky = E) + row = row + 1 + + def prepare_build(self): + # get compiler + compiler = self.compilers.get() + if compiler == 'GCC': + compiler = 'gcc' + elif compiler == 'ARMCC': + compiler = 'keil' + elif compiler == 'IAR': + compiler = 'iar' + + # get RTT Root + rtt_root = self.RTTRoot.get_path() + # get Compiler path + exec_path = self.CompilersPath[self.compilers.get()].get_path() + + command = '' + + os.environ['RTT_ROOT'] = rtt_root + os.environ['RTT_CC'] = compiler + os.environ['RTT_EXEC_PATH'] = exec_path + + return command + + def check_path(self): + result = True + + if self.BSPRoot.get_path() == '': + result = False + + if self.RTTRoot.get_path() == '': + result = False + + if not result: + tkMessageBox.showinfo("RT-Thread SCons UI", + "Folder is empty, please choose correct directory.") + + return result + + def do_build(self): + self.prepare_build() + command = 'scons' + + if not self.check_path(): + return + + bsp = self.BSPRoot.get_path() + os.chdir(bsp) + + self.output.delete(1.0, END) + self.output.insert(END, 'building project...\n') + ExecCmd(command) + + def do_clean(self): + self.prepare_build() + command = 'scons -c' + + if not self.check_path(): + return + + bsp = self.BSPRoot.get_path() + os.chdir(bsp) + + self.output.delete(1.0, END) + self.output.insert(END, 'clean project...\n') + ExecCmd(command) + + def do_make_project(self): + ide = self.ide.get() + self.prepare_build() + command = 'scons --target=%s -s' % ide + + if not self.check_path(): + return + + # select build page + self.notebook.select(self.building_page) + + bsp = self.BSPRoot.get_path() + os.chdir(bsp) + + self.output.delete(1.0, END) + self.output.insert(END, 'Generate project ...\n') + self.is_makeing_project = True + ExecCmd(command) + + def quit(self): + exit(0) + +def StartSConsUI(path=None): + global val, root, builder, lock + root = Tk() + root.title('RT-Thread SCons UI') + #root.geometrygeometry('590x510+50+50') + lock = threading.RLock() + builder = SconsUI(root) + if path: + builder.BSPRoot.set_path(path) + root.mainloop() + +if __name__ == '__main__': + StartSConsUI() diff --git a/tools/win32spawn.py b/tools/win32spawn.py index 28a181510eaa226c7ccf5f5094743a619614af92..8adc64306b45ab6a701f03017035715514957820 100644 --- a/tools/win32spawn.py +++ b/tools/win32spawn.py @@ -1,155 +1,155 @@ -import os -import threading -import Queue - -# Windows import -import win32file -import win32pipe -import win32api -import win32con -import win32security -import win32process -import win32event - -class Win32Spawn(object): - def __init__(self, cmd, shell=False): - self.queue = Queue.Queue() - self.is_terminated = False - self.wake_up_event = win32event.CreateEvent(None, 0, 0, None) - - exec_dir = os.getcwd() - comspec = os.environ.get("COMSPEC", "cmd.exe") - cmd = comspec + ' /c ' + cmd - - win32event.ResetEvent(self.wake_up_event) - - currproc = win32api.GetCurrentProcess() - - sa = win32security.SECURITY_ATTRIBUTES() - sa.bInheritHandle = 1 - - child_stdout_rd, child_stdout_wr = win32pipe.CreatePipe(sa, 0) - child_stdout_rd_dup = win32api.DuplicateHandle(currproc, child_stdout_rd, currproc, 0, 0, win32con.DUPLICATE_SAME_ACCESS) - win32file.CloseHandle(child_stdout_rd) - - child_stderr_rd, child_stderr_wr = win32pipe.CreatePipe(sa, 0) - child_stderr_rd_dup = win32api.DuplicateHandle(currproc, child_stderr_rd, currproc, 0, 0, win32con.DUPLICATE_SAME_ACCESS) - win32file.CloseHandle(child_stderr_rd) - - child_stdin_rd, child_stdin_wr = win32pipe.CreatePipe(sa, 0) - child_stdin_wr_dup = win32api.DuplicateHandle(currproc, child_stdin_wr, currproc, 0, 0, win32con.DUPLICATE_SAME_ACCESS) - win32file.CloseHandle(child_stdin_wr) - - startup_info = win32process.STARTUPINFO() - startup_info.hStdInput = child_stdin_rd - startup_info.hStdOutput = child_stdout_wr - startup_info.hStdError = child_stderr_wr - startup_info.dwFlags = win32process.STARTF_USESTDHANDLES - - cr_flags = 0 - cr_flags = win32process.CREATE_NEW_PROCESS_GROUP - - env = os.environ.copy() - self.h_process, h_thread, dw_pid, dw_tid = win32process.CreateProcess(None, cmd, None, None, 1, - cr_flags, env, os.path.abspath(exec_dir), - startup_info) - - win32api.CloseHandle(h_thread) - - win32file.CloseHandle(child_stdin_rd) - win32file.CloseHandle(child_stdout_wr) - win32file.CloseHandle(child_stderr_wr) - - self.__child_stdout = child_stdout_rd_dup - self.__child_stderr = child_stderr_rd_dup - self.__child_stdin = child_stdin_wr_dup - - self.exit_code = -1 - - def close(self): - win32file.CloseHandle(self.__child_stdout) - win32file.CloseHandle(self.__child_stderr) - win32file.CloseHandle(self.__child_stdin) - win32api.CloseHandle(self.h_process) - win32api.CloseHandle(self.wake_up_event) - - def kill_subprocess(): - win32event.SetEvent(self.wake_up_event) - - def sleep(secs): - win32event.ResetEvent(self.wake_up_event) - timeout = int(1000 * secs) - val = win32event.WaitForSingleObject(self.wake_up_event, timeout) - if val == win32event.WAIT_TIMEOUT: - return True - else: - # The wake_up_event must have been signalled - return False - - def get(self, block=True, timeout=None): - return self.queue.get(block=block, timeout=timeout) - - def qsize(self): - return self.queue.qsize() - - def __wait_for_child(self): - # kick off threads to read from stdout and stderr of the child process - threading.Thread(target=self.__do_read, args=(self.__child_stdout, )).start() - threading.Thread(target=self.__do_read, args=(self.__child_stderr, )).start() - - while True: - # block waiting for the process to finish or the interrupt to happen - handles = (self.wake_up_event, self.h_process) - val = win32event.WaitForMultipleObjects(handles, 0, win32event.INFINITE) - - if val >= win32event.WAIT_OBJECT_0 and val < win32event.WAIT_OBJECT_0 + len(handles): - handle = handles[val - win32event.WAIT_OBJECT_0] - if handle == self.wake_up_event: - win32api.TerminateProcess(self.h_process, 1) - win32event.ResetEvent(self.wake_up_event) - return False - elif handle == self.h_process: - # the process has ended naturally - return True - else: - assert False, "Unknown handle fired" - else: - assert False, "Unexpected return from WaitForMultipleObjects" - - # Wait for job to finish. Since this method blocks, it can to be called from another thread. - # If the application wants to kill the process, it should call kill_subprocess(). - def wait(self): - if not self.__wait_for_child(): - # it's been killed - result = False - else: - # normal termination - self.exit_code = win32process.GetExitCodeProcess(self.h_process) - result = self.exit_code == 0 - self.close() - self.is_terminated = True - - return result - - # This method gets called on a worker thread to read from either a stderr - # or stdout thread from the child process. - def __do_read(self, handle): - bytesToRead = 1024 - while 1: - try: - finished = 0 - hr, data = win32file.ReadFile(handle, bytesToRead, None) - if data: - self.queue.put_nowait(data) - except win32api.error: - finished = 1 - - if finished: - return - - def start_pipe(self): - def worker(pipe): - return pipe.wait() - - thrd = threading.Thread(target=worker, args=(self, )) - thrd.start() +import os +import threading +import Queue + +# Windows import +import win32file +import win32pipe +import win32api +import win32con +import win32security +import win32process +import win32event + +class Win32Spawn(object): + def __init__(self, cmd, shell=False): + self.queue = Queue.Queue() + self.is_terminated = False + self.wake_up_event = win32event.CreateEvent(None, 0, 0, None) + + exec_dir = os.getcwd() + comspec = os.environ.get("COMSPEC", "cmd.exe") + cmd = comspec + ' /c ' + cmd + + win32event.ResetEvent(self.wake_up_event) + + currproc = win32api.GetCurrentProcess() + + sa = win32security.SECURITY_ATTRIBUTES() + sa.bInheritHandle = 1 + + child_stdout_rd, child_stdout_wr = win32pipe.CreatePipe(sa, 0) + child_stdout_rd_dup = win32api.DuplicateHandle(currproc, child_stdout_rd, currproc, 0, 0, win32con.DUPLICATE_SAME_ACCESS) + win32file.CloseHandle(child_stdout_rd) + + child_stderr_rd, child_stderr_wr = win32pipe.CreatePipe(sa, 0) + child_stderr_rd_dup = win32api.DuplicateHandle(currproc, child_stderr_rd, currproc, 0, 0, win32con.DUPLICATE_SAME_ACCESS) + win32file.CloseHandle(child_stderr_rd) + + child_stdin_rd, child_stdin_wr = win32pipe.CreatePipe(sa, 0) + child_stdin_wr_dup = win32api.DuplicateHandle(currproc, child_stdin_wr, currproc, 0, 0, win32con.DUPLICATE_SAME_ACCESS) + win32file.CloseHandle(child_stdin_wr) + + startup_info = win32process.STARTUPINFO() + startup_info.hStdInput = child_stdin_rd + startup_info.hStdOutput = child_stdout_wr + startup_info.hStdError = child_stderr_wr + startup_info.dwFlags = win32process.STARTF_USESTDHANDLES + + cr_flags = 0 + cr_flags = win32process.CREATE_NEW_PROCESS_GROUP + + env = os.environ.copy() + self.h_process, h_thread, dw_pid, dw_tid = win32process.CreateProcess(None, cmd, None, None, 1, + cr_flags, env, os.path.abspath(exec_dir), + startup_info) + + win32api.CloseHandle(h_thread) + + win32file.CloseHandle(child_stdin_rd) + win32file.CloseHandle(child_stdout_wr) + win32file.CloseHandle(child_stderr_wr) + + self.__child_stdout = child_stdout_rd_dup + self.__child_stderr = child_stderr_rd_dup + self.__child_stdin = child_stdin_wr_dup + + self.exit_code = -1 + + def close(self): + win32file.CloseHandle(self.__child_stdout) + win32file.CloseHandle(self.__child_stderr) + win32file.CloseHandle(self.__child_stdin) + win32api.CloseHandle(self.h_process) + win32api.CloseHandle(self.wake_up_event) + + def kill_subprocess(): + win32event.SetEvent(self.wake_up_event) + + def sleep(secs): + win32event.ResetEvent(self.wake_up_event) + timeout = int(1000 * secs) + val = win32event.WaitForSingleObject(self.wake_up_event, timeout) + if val == win32event.WAIT_TIMEOUT: + return True + else: + # The wake_up_event must have been signalled + return False + + def get(self, block=True, timeout=None): + return self.queue.get(block=block, timeout=timeout) + + def qsize(self): + return self.queue.qsize() + + def __wait_for_child(self): + # kick off threads to read from stdout and stderr of the child process + threading.Thread(target=self.__do_read, args=(self.__child_stdout, )).start() + threading.Thread(target=self.__do_read, args=(self.__child_stderr, )).start() + + while True: + # block waiting for the process to finish or the interrupt to happen + handles = (self.wake_up_event, self.h_process) + val = win32event.WaitForMultipleObjects(handles, 0, win32event.INFINITE) + + if val >= win32event.WAIT_OBJECT_0 and val < win32event.WAIT_OBJECT_0 + len(handles): + handle = handles[val - win32event.WAIT_OBJECT_0] + if handle == self.wake_up_event: + win32api.TerminateProcess(self.h_process, 1) + win32event.ResetEvent(self.wake_up_event) + return False + elif handle == self.h_process: + # the process has ended naturally + return True + else: + assert False, "Unknown handle fired" + else: + assert False, "Unexpected return from WaitForMultipleObjects" + + # Wait for job to finish. Since this method blocks, it can to be called from another thread. + # If the application wants to kill the process, it should call kill_subprocess(). + def wait(self): + if not self.__wait_for_child(): + # it's been killed + result = False + else: + # normal termination + self.exit_code = win32process.GetExitCodeProcess(self.h_process) + result = self.exit_code == 0 + self.close() + self.is_terminated = True + + return result + + # This method gets called on a worker thread to read from either a stderr + # or stdout thread from the child process. + def __do_read(self, handle): + bytesToRead = 1024 + while 1: + try: + finished = 0 + hr, data = win32file.ReadFile(handle, bytesToRead, None) + if data: + self.queue.put_nowait(data) + except win32api.error: + finished = 1 + + if finished: + return + + def start_pipe(self): + def worker(pipe): + return pipe.wait() + + thrd = threading.Thread(target=worker, args=(self, )) + thrd.start() diff --git a/tools/wizard.py b/tools/wizard.py index ff3eb1dac73d6afece046233d514696fbf55313a..4b2186fadbd8cf82ba2b396680a344d1e2db66be 100644 --- a/tools/wizard.py +++ b/tools/wizard.py @@ -1,71 +1,71 @@ -#! /usr/bin/env python -#coding=utf-8 - -""" -wizard.py - a script to generate SConscript in RT-Thread RTOS. - -`wizard --component name' to generate SConscript for name component. -`wizard --bridge' to generate SConscript as a bridge to connect each -SConscript script file of sub-directory. -""" - -import sys - -SConscript_com = '''# RT-Thread building script for component - -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd] - -group = DefineGroup('COMPONENT_NAME', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') -''' - -SConscript_bridge = '''# RT-Thread building script for bridge - -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') -''' - -def usage(): - print 'wizard --component name' - print 'wizard --bridge' - -def gen_component(name): - print 'generate SConscript for ' + name - text = SConscript_com.replace('COMPONENT_NAME', name) - f = file('SConscript', 'w') - f.write(text) - f.close() - -def gen_bridge(): - print 'generate SConscript for bridge' - f = file('SConscript', 'w') - f.write(SConscript_bridge) - f.close() - -if __name__ == '__main__': - if len(sys.argv) == 1: - usage() - sys.exit(2) - - if sys.argv[1] == '--component': - gen_component(sys.argv[2]) - elif sys.argv[1] == '--bridge': - gen_bridge() - else: - usage() +#! /usr/bin/env python +#coding=utf-8 + +""" +wizard.py - a script to generate SConscript in RT-Thread RTOS. + +`wizard --component name' to generate SConscript for name component. +`wizard --bridge' to generate SConscript as a bridge to connect each +SConscript script file of sub-directory. +""" + +import sys + +SConscript_com = '''# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('COMPONENT_NAME', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') +''' + +SConscript_bridge = '''# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') +''' + +def usage(): + print 'wizard --component name' + print 'wizard --bridge' + +def gen_component(name): + print 'generate SConscript for ' + name + text = SConscript_com.replace('COMPONENT_NAME', name) + f = file('SConscript', 'w') + f.write(text) + f.close() + +def gen_bridge(): + print 'generate SConscript for bridge' + f = file('SConscript', 'w') + f.write(SConscript_bridge) + f.close() + +if __name__ == '__main__': + if len(sys.argv) == 1: + usage() + sys.exit(2) + + if sys.argv[1] == '--component': + gen_component(sys.argv[2]) + elif sys.argv[1] == '--bridge': + gen_bridge() + else: + usage()