diff --git a/bsp/v85xxp/.ignore_format.yml b/bsp/v85xxp/.ignore_format.yml
new file mode 100644
index 0000000000000000000000000000000000000000..b42fb0c41a6a08e01244038edbf80c8057c922f0
--- /dev/null
+++ b/bsp/v85xxp/.ignore_format.yml
@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- Libraries/VangoV85xxP_standard_peripheral
diff --git a/bsp/v85xxp/Kconfig b/bsp/v85xxp/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..4e3f2d260d138895f419b68a03bbbb13b6e0aeab
--- /dev/null
+++ b/bsp/v85xxp/Kconfig
@@ -0,0 +1,97 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../.."
+
+# you can change the RTT_ROOT default: "rt-thread"
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_SERIES_V85XXP
+ bool
+ default y
+
+config SOC_V85XXP
+ bool
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ select SOC_SERIES_V85XXP
+ default y
+
+menu "On-chip Peripheral Drivers"
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default y
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_UART0
+ bool "using uart0"
+ default n
+ config BSP_USING_UART1
+ bool "using uart1"
+ default n
+ config BSP_USING_UART2
+ bool "using uart2"
+ default y
+ config BSP_USING_UART3
+ bool "using uart3"
+ default n
+ config BSP_USING_UART4
+ bool "using uart4"
+ default n
+ config BSP_USING_UART5
+ bool "using uart5"
+ default n
+ endif
+ menuconfig BSP_USING_ADC
+ bool "Enable ADC"
+ default n
+ select RT_USING_ADC
+ if BSP_USING_ADC
+ config BSP_USING_ADC0
+ bool "using adc0"
+ default n
+ endif
+ menuconfig BSP_USING_HWTIMER
+ bool "Enable hwtimer"
+ default n
+ select RT_USING_HWTIMER
+ if BSP_USING_HWTIMER
+ config BSP_USING_HWTIMER0
+ bool "using hwtimer0"
+ default n
+ config BSP_USING_HWTIMER1
+ bool "using hwtimer1"
+ default n
+ config BSP_USING_HWTIMER2
+ bool "using hwtimer2"
+ default n
+ config BSP_USING_HWTIMER3
+ bool "using hwtimer3"
+ default n
+ endif
+ config BSP_USING_WDT
+ bool "Enable Watchdog Timer"
+ select RT_USING_WDT
+ default n
+
+ config BSP_USING_RTC
+ bool "using internal rtc"
+ default n
+ select RT_USING_RTC
+
+endmenu
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_CodeRAM.h b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_CodeRAM.h
new file mode 100644
index 0000000000000000000000000000000000000000..cbcea56cb17755efdb01f58d425b69ab71ecb132
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_CodeRAM.h
@@ -0,0 +1,46 @@
+/**
+ ******************************************************************************
+ * @file lib_CodeRAM.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Codes executed in SRAM.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+
+#ifndef __LIB_CODERAM_H
+#define __LIB_CODERAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "target.h"
+
+#ifndef __GNUC__
+
+#ifdef __ICCARM__ /* EWARM */
+ #define __RAM_FUNC __ramfunc
+#endif
+
+#ifdef __CC_ARM /* MDK-ARM */
+ #define __RAM_FUNC __attribute__((used))
+#endif
+
+/* Exported Functions ------------------------------------------------------- */
+
+__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void);
+
+#endif /* __GNUC__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_CODERAM_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_LoadNVR.h b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_LoadNVR.h
new file mode 100644
index 0000000000000000000000000000000000000000..b429b195136adf46862b9e1d23f3d6295e462a71
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_LoadNVR.h
@@ -0,0 +1,235 @@
+/**
+ ******************************************************************************
+ * @file lib_LoadNVR.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Load information from NVR.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+
+#ifndef __LIB_LOADNVR_H
+#define __LIB_LOADNVR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "target.h"
+
+/* Power Measure Result */
+typedef struct
+{
+ uint32_t AVCCMEAResult; // LDO33 Measure Result
+ uint32_t DVCCMEAResult; // LDO15 Measure Result
+ uint32_t BGPMEAResult; // BGP Measure Result
+ uint32_t RCLMEAResult; // RCL Measure Result
+ uint32_t RCHMEAResult; // RCH Measure Result
+} NVR_MISCGain;
+
+/* Chip ID */
+typedef struct
+{
+ uint32_t ChipID0; // ID word 0
+ uint32_t ChipID1; // ID word 1
+} NVR_CHIPID;
+
+/* Temperature information */
+typedef struct
+{
+ float TempOffset;
+} NVR_TEMPINFO;
+
+/* LCD information */
+typedef struct
+{
+ uint32_t MEALCDLDO; // Measure LCD LDO pre trim value
+ uint32_t MEALCDVol; // VLCD setting
+} NVR_LCDINFO;
+
+/* RTC(temp) information */
+typedef struct
+{
+ int16_t RTCTempP0; //P0
+ int16_t RTCTempP1; //P1
+ int32_t RTCTempP2; //P2
+ int16_t RTCTempP4; //P4
+ int16_t RTCTempP5; //P5
+ int16_t RTCTempP6; //P6
+ int16_t RTCTempP7; //P7
+ int16_t RTCTempK0; //K0
+ int16_t RTCTempK1; //K1
+ int16_t RTCTempK2; //K2
+ int16_t RTCTempK3; //K3
+ int16_t RTCTempK4; //K4
+ int16_t RTCACTI; //Center temperature
+ uint32_t RTCACKTemp; //section X temperature
+ int32_t RTCTempDelta; //Temperature delta
+ uint32_t RTCACF200; //RTC_ACF200
+} NVR_RTCINFO;
+
+/* RTC(temp) information */
+typedef struct
+{
+ int16_t RTCTempP0; //P0
+ int16_t RTCTempP1; //P1
+ int32_t RTCTempP2; //P2
+} NVR_TempParams;
+
+/* ADC Voltage Parameters */
+typedef struct
+{
+ float aParameter;
+ float bParameter;
+ float OffsetParameter;
+} NVR_ADCVOLPARA;
+//Mode
+#define NVR_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None
+#define NVR_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive
+#define NVR_3V_BAT1_RESDIV (0x002UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive
+#define NVR_3V_BATRTC_RESDIV (0x003UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive
+#define NVR_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None
+#define NVR_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive
+#define NVR_5V_BAT1_RESDIV (0x102UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive
+#define NVR_5V_BATRTC_RESDIV (0x103UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive
+#define IS_NVR_ADCVOL_MODE(__MODE__) (((__MODE__) == NVR_3V_EXTERNAL_NODIV) ||\
+ ((__MODE__) == NVR_3V_EXTERNAL_RESDIV) ||\
+ ((__MODE__) == NVR_3V_BAT1_RESDIV) ||\
+ ((__MODE__) == NVR_3V_BATRTC_RESDIV) ||\
+ ((__MODE__) == NVR_5V_EXTERNAL_NODIV) ||\
+ ((__MODE__) == NVR_5V_EXTERNAL_RESDIV) ||\
+ ((__MODE__) == NVR_5V_BAT1_RESDIV) ||\
+ ((__MODE__) == NVR_5V_BATRTC_RESDIV))
+
+//VOLMode
+#define NVR_MEARES_3V 0
+#define NVR_MEARES_5V 1
+#define IS_MEARES(__VOLMODE__) (((__VOLMODE__) == NVR_MEARES_3V) ||\
+ ((__VOLMODE__) == NVR_MEARES_5V))
+/********** NVR Address **********/
+//ADC Voltage Parameters
+#define NVR_3VPARA_BASEADDR1 (__IO uint32_t *)(0x80C48)
+#define NVR_3VPARA_BASEADDR2 (__IO uint32_t *)(0x80C6C)
+#define NVR_5VPARA_BASEADDR1 (__IO uint32_t *)(0x80C00)
+#define NVR_5VPARA_BASEADDR2 (__IO uint32_t *)(0x80C24)
+//RTC DATA
+//P4
+#define NVR_RTC1_P4 (__IO uint32_t *)(0x80800)
+#define NVR_RTC1_P4_CHKSUM (__IO uint32_t *)(0x80804)
+#define NVR_RTC2_P4 (__IO uint32_t *)(0x80808)
+#define NVR_RTC2_P4_CHKSUM (__IO uint32_t *)(0x8080C)
+//ACK1~ACK5
+#define NVR_RTC1_ACK0 (__IO uint32_t *)(0x80810)
+#define NVR_RTC1_ACK1 (__IO uint32_t *)(0x80814)
+#define NVR_RTC1_ACK2 (__IO uint32_t *)(0x80818)
+#define NVR_RTC1_ACK3 (__IO uint32_t *)(0x8081C)
+#define NVR_RTC1_ACK4 (__IO uint32_t *)(0x80820)
+#define NVR_RTC1_ACK_CHKSUM (__IO uint32_t *)(0x80824)
+#define NVR_RTC2_ACK0 (__IO uint32_t *)(0x80828)
+#define NVR_RTC2_ACK1 (__IO uint32_t *)(0x8082C)
+#define NVR_RTC2_ACK2 (__IO uint32_t *)(0x80830)
+#define NVR_RTC2_ACK3 (__IO uint32_t *)(0x80834)
+#define NVR_RTC2_ACK4 (__IO uint32_t *)(0x80838)
+#define NVR_RTC2_ACK_CHKSUM (__IO uint32_t *)(0x8083C)
+//ACTI
+#define NVR_RTC1_ACTI (__IO uint32_t *)(0x80840)
+#define NVR_RTC1_ACTI_CHKSUM (__IO uint32_t *)(0x80844)
+#define NVR_RTC2_ACTI (__IO uint32_t *)(0x80848)
+#define NVR_RTC2_ACTI_CHKSUM (__IO uint32_t *)(0x8084C)
+//ACKTEMP
+#define NVR_RTC1_ACKTEMP (__IO uint32_t *)(0x80850)
+#define NVR_RTC1_ACKTEMP_CHKSUM (__IO uint32_t *)(0x80854)
+#define NVR_RTC2_ACKTEMP (__IO uint32_t *)(0x80858)
+#define NVR_RTC2_ACKTEMP_CHKSUM (__IO uint32_t *)(0x8085C)
+//Analog trim data
+#define NVR_ANA_TRIMDATA1 (__IO uint32_t *)(0x80DC0)
+#define NVR_ANA_OPREG1 (__IO uint32_t *)(0x80DC4)
+#define NVR_ANA_KEYREG1 (__IO uint32_t *)(0x80DC8)
+#define NVR_ANA_CHECKSUM1 (__IO uint32_t *)(0x80DCC)
+#define NVR_ANA_TRIMDATA2 (__IO uint32_t *)(0x80DD0)
+#define NVR_ANA_OPREG2 (__IO uint32_t *)(0x80DD4)
+#define NVR_ANA_KEYREG2 (__IO uint32_t *)(0x80DD8)
+#define NVR_ANA_CHECKSUM2 (__IO uint32_t *)(0x80DDC)
+#define NVR_ANA1_REG10 (__IO uint32_t *)(0x80DE0)
+#define NVR_ANA1_REG10_CHKSUM (__IO uint32_t *)(0x80DE4)
+#define NVR_ANA2_REG10 (__IO uint32_t *)(0x80DE8)
+#define NVR_ANA2_REG10_CHKSUM (__IO uint32_t *)(0x80DEC)
+//ADC_CHx
+#define NVR_5VADCCHx_NODIV1 (__IO uint32_t *)(0x80C90)
+#define NVR_5VADCCHx_RESDIV1 (__IO uint32_t *)(0x80C94)
+#define NVR_5VADCCHx_NODIV2 (__IO uint32_t *)(0x80CA4)
+#define NVR_5VADCCHx_RESDIV2 (__IO uint32_t *)(0x80CA8)
+#define NVR_3VADCCHx_NODIV1 (__IO uint32_t *)(0x80CB8)
+#define NVR_3VADCCHx_RESDIV1 (__IO uint32_t *)(0x80CBC)
+#define NVR_3VADCCHx_NODIV2 (__IO uint32_t *)(0x80CCC)
+#define NVR_3VADCCHx_RESDIV2 (__IO uint32_t *)(0x80CD0)
+//BAT Measure Result
+#define NVR_5VBAT1 (__IO uint32_t *)(0x80C98)
+#define NVR_5VBATRTC1 (__IO uint32_t *)(0x80C9C)
+#define NVR_5VBATCHKSUM1 (__IO uint32_t *)(0x80CA0)
+#define NVR_5VBAT2 (__IO uint32_t *)(0x80CAC)
+#define NVR_5VBATRTC2 (__IO uint32_t *)(0x80CB0)
+#define NVR_5VBATCHKSUM2 (__IO uint32_t *)(0x80CB4)
+#define NVR_3VBAT1 (__IO uint32_t *)(0x80CC0)
+#define NVR_3VBATRTC1 (__IO uint32_t *)(0x80CC4)
+#define NVR_3VBATCHKSUM1 (__IO uint32_t *)(0x80CC8)
+#define NVR_3VBAT2 (__IO uint32_t *)(0x80CD4)
+#define NVR_3VBATRTC2 (__IO uint32_t *)(0x80CD8)
+#define NVR_3VBATCHKSUM2 (__IO uint32_t *)(0x80CDC)
+//RTC AutoCal Px pramameters
+#define NVR_RTC1_P1_P0 (__IO uint32_t *)(0x80D10)
+#define NVR_RTC1_P2 (__IO uint32_t *)(0x80D14)
+#define NVR_RTC1_P5_P4 (__IO uint32_t *)(0x80D18)
+#define NVR_RTC1_P7_P6 (__IO uint32_t *)(0x80D1C)
+#define NVR_RTC1_PCHECHSUM (__IO uint32_t *)(0x80D20)
+#define NVR_RTC2_P1_P0 (__IO uint32_t *)(0x80D24)
+#define NVR_RTC2_P2 (__IO uint32_t *)(0x80D28)
+#define NVR_RTC2_P5_P4 (__IO uint32_t *)(0x80D2C)
+#define NVR_RTC2_P7_P6 (__IO uint32_t *)(0x80D30)
+#define NVR_RTC2_PCHECHSUM (__IO uint32_t *)(0x80D34)
+//Power Measure Result
+#define NVR_AVCC_MEA1 (__IO uint32_t *)(0x80D38)
+#define NVR_DVCC_MEA1 (__IO uint32_t *)(0x80D3C)
+#define NVR_BGP_MEA1 (__IO uint32_t *)(0x80D40)
+#define NVR_RCL_MEA1 (__IO uint32_t *)(0x80D44)
+#define NVR_RCH_MEA1 (__IO uint32_t *)(0x80D48)
+#define NVR_PWR_CHECKSUM1 (__IO uint32_t *)(0x80D4C)
+#define NVR_AVCC_MEA2 (__IO uint32_t *)(0x80D50)
+#define NVR_DVCC_MEA2 (__IO uint32_t *)(0x80D54)
+#define NVR_BGP_MEA2 (__IO uint32_t *)(0x80D58)
+#define NVR_RCL_MEA2 (__IO uint32_t *)(0x80D5C)
+#define NVR_RCH_MEA2 (__IO uint32_t *)(0x80D60)
+#define NVR_PWR_CHECKSUM2 (__IO uint32_t *)(0x80D64)
+//Chip ID
+#define NVR_CHIP1_ID0 (__IO uint32_t *)(0x80D68)
+#define NVR_CHIP1_ID1 (__IO uint32_t *)(0x80D6C)
+#define NVR_CHIP1_CHECKSUM (__IO uint32_t *)(0x80D70)
+#define NVR_CHIP2_ID0 (__IO uint32_t *)(0x80D74)
+#define NVR_CHIP2_ID1 (__IO uint32_t *)(0x80D78)
+#define NVR_CHIP2_CHECKSUM (__IO uint32_t *)(0x80D7C)
+//Temperature information
+#define NVR_REALTEMP1 (__IO uint32_t *)(0x80D80)
+#define NVR_MEATEMP1 (__IO uint32_t *)(0x80D84)
+#define NVR_TEMP_CHECKSUM1 (__IO uint32_t *)(0x80D88)
+#define NVR_REALTEMP2 (__IO uint32_t *)(0x80D9C)
+#define NVR_MEATEMP2 (__IO uint32_t *)(0x80D90)
+#define NVR_TEMP_CHECKSUM2 (__IO uint32_t *)(0x80D94)
+
+uint32_t NVR_LoadANADataManual(void);
+uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData, uint32_t DivCLKSource);
+uint32_t NVR_GetVoltageParameters(uint32_t Mode, NVR_ADCVOLPARA *Parameter);
+uint32_t NVR_GetTempParameters(NVR_TempParams *TempParams);
+uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult);
+uint32_t NVR_GetChipID(NVR_CHIPID *ChipID);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_LOADNVR_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_conf.h b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_conf.h
new file mode 100644
index 0000000000000000000000000000000000000000..00b29ac43cd9943cbe27351be7848ef6d1b6d520
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_conf.h
@@ -0,0 +1,62 @@
+/**
+ ******************************************************************************
+ * @file lib_conf.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Dirver configuration.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+
+#ifndef __LIB_CONF_H
+#define __LIB_CONF_H
+
+/* ########################## Assert Selection ############################## */
+
+//#define ASSERT_NDEBUG 1
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+#include "lib_ana.h"
+#include "lib_adc.h"
+#include "lib_adc_tiny.h"
+#include "lib_clk.h"
+#include "lib_cmp.h"
+#include "lib_crypt.h"
+#include "lib_dma.h"
+#include "lib_flash.h"
+#include "lib_gpio.h"
+#include "lib_i2c.h"
+#include "lib_iso7816.h"
+#include "lib_lcd.h"
+#include "lib_misc.h"
+#include "lib_pmu.h"
+#include "lib_pwm.h"
+#include "lib_rtc.h"
+#include "lib_spi.h"
+#include "lib_tmr.h"
+#include "lib_u32k.h"
+#include "lib_uart.h"
+#include "lib_version.h"
+#include "lib_wdt.h"
+#include "lib_LoadNVR.h"
+#include "lib_CodeRAM.h"
+#include "lib_cortex.h"
+
+/* Exported macro ------------------------------------------------------------*/
+#ifndef ASSERT_NDEBUG
+ #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_errhandler(uint8_t* file, uint32_t line);
+#else
+ #define assert_parameters(expr) ((void)0U)
+#endif /* ASSERT_NDEBUG */
+
+#endif
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_cortex.h b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_cortex.h
new file mode 100644
index 0000000000000000000000000000000000000000..db55de4873f5bda0d8f4808faa90789aab8b4c64
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_cortex.h
@@ -0,0 +1,49 @@
+/**
+ ******************************************************************************
+ * @file lib_Cortex.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Cortex module driver.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+
+#ifndef __LIB_CORTEX_H
+#define __LIB_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "target.h"
+
+
+#define IS_CORTEX_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
+
+#define IS_CORTEX_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
+
+/* Exported Functions ------------------------------------------------------- */
+void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority);
+
+void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn);
+void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn);
+uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn);
+void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority);
+void CORTEX_NVIC_SystemReset(void);
+uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum);
+void CORTEX_Delay_nSysClock(__IO uint32_t nClock);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_CORTEX_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/system_target.h b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/system_target.h
new file mode 100644
index 0000000000000000000000000000000000000000..ce3712bf419b2358f401c483d546833985a999d2
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/system_target.h
@@ -0,0 +1,38 @@
+/**
+ ******************************************************************************
+ * @file system_target.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief system source file.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __SYSTEM_TARGET_H
+#define __SYSTEM_TARGET_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "type_def.h"
+
+
+
+extern void SystemInit(void);
+extern void SystemUpdate(void);
+
+
+#ifdef USE_TARGET_DRIVER
+ #include "lib_conf.h"
+#endif /* USE_TARGET_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_TARGET_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/target.h b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/target.h
new file mode 100644
index 0000000000000000000000000000000000000000..50c551e0484674f7cbce43fbe8fb43c0a17733a7
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/target.h
@@ -0,0 +1,2771 @@
+/**
+********************************************************************************
+* @file target.h
+* @author Application Team
+* @version V1.1.0
+* @date 2019-10-28
+* @brief Register define
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, XXXXX SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+********************************************************************************
+*/
+
+#ifndef TARGET_H
+#define TARGET_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR, RESET = 0, SET = !RESET, DISABLE = 0, ENABLE = !DISABLE} TypeState, EventStatus, ControlStatus, FlagStatus, ErrStatus;
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+typedef enum {
+/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+/* =========================================== target Specific Interrupt Numbers =========================================== */
+ PMU_IRQn = 0, /*!< 0 PMU */
+ RTC_IRQn = 1, /*!< 1 RTC */
+ U32K0_IRQn = 2, /*!< 2 U32K0 */
+ U32K1_IRQn = 3, /*!< 3 U32K1 */
+ I2C_IRQn = 4, /*!< 4 I2C */
+ SPI1_IRQn = 5, /*!< 5 SPI1 */
+ UART0_IRQn = 6, /*!< 6 UART0 */
+ UART1_IRQn = 7, /*!< 7 UART1 */
+ UART2_IRQn = 8, /*!< 8 UART2 */
+ UART3_IRQn = 9, /*!< 9 UART3 */
+ UART4_IRQn = 10, /*!< 10 UART4 */
+ UART5_IRQn = 11, /*!< 11 UART5 */
+ ISO78160_IRQn = 12, /*!< 12 ISO78160 */
+ ISO78161_IRQn = 13, /*!< 13 ISO78161 */
+ TMR0_IRQn = 14, /*!< 14 TMR0 */
+ TMR1_IRQn = 15, /*!< 15 TMR1 */
+ TMR2_IRQn = 16, /*!< 16 TMR2 */
+ TMR3_IRQn = 17, /*!< 17 TMR3 */
+ PWM0_IRQn = 18, /*!< 18 PWM0 */
+ PWM1_IRQn = 19, /*!< 19 PWM1 */
+ PWM2_IRQn = 20, /*!< 20 PWM2 */
+ PWM3_IRQn = 21, /*!< 21 PWM3 */
+ DMA_IRQn = 22, /*!< 22 DMA */
+ FLASH_IRQn = 23, /*!< 23 FLASH */
+ ANA_IRQn = 24, /*!< 24 ANA */
+ SPI2_IRQn = 27, /*!< 27 SPI2 */
+ SPI3_IRQn = 28 /*!< 28 SPI3 */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */
+#define __CM0_REV 0x0000U /*!< CM0 Core Revision */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __FPU_PRESENT 0 /*!< FPU present or not */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */
+
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ANA ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief The Analog controller is used to control the analog function of TARGET. (ANA)
+ */
+
+typedef struct { /*!< (@ 0x40014200) ANA Structure */
+ __IOM uint32_t REG0; /*!< (@ 0x00000000) Analog register 0. */
+ __IOM uint32_t REG1; /*!< (@ 0x00000004) Analog register 1. */
+ __IOM uint32_t REG2; /*!< (@ 0x00000008) Analog register 2. */
+ __IOM uint32_t REG3; /*!< (@ 0x0000000C) Analog register 3. */
+ __IOM uint32_t REG4; /*!< (@ 0x00000010) Analog register 4. */
+ __IOM uint32_t REG5; /*!< (@ 0x00000014) Analog register 5. */
+ __IOM uint32_t REG6; /*!< (@ 0x00000018) Analog register 6. */
+ __IOM uint32_t REG7; /*!< (@ 0x0000001C) Analog register 7. */
+ __IOM uint32_t REG8; /*!< (@ 0x00000020) Analog register 8. */
+ __IOM uint32_t REG9; /*!< (@ 0x00000024) Analog register 9. */
+ __IOM uint32_t REGA; /*!< (@ 0x00000028) Analog register 10. */
+ __IOM uint32_t REGB; /*!< (@ 0x0000002C) Analog register 11. */
+ __IOM uint32_t REGC; /*!< (@ 0x00000030) Analog register 12. */
+ __IOM uint32_t REGD; /*!< (@ 0x00000034) Analog register 13. */
+ __IOM uint32_t REGE; /*!< (@ 0x00000038) Analog register 14. */
+ __IOM uint32_t REGF; /*!< (@ 0x0000003C) Analog register 15. */
+ __IOM uint32_t REG10; /*!< (@ 0x00000040) Analog register 16. */
+ __IOM uint32_t REG11; /*!< (@ 0x00000044) Analog register 17. */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CTRL; /*!< (@ 0x00000050) Analog control register. */
+ __IM uint32_t CMPOUT; /*!< (@ 0x00000054) Comparator result register. */
+ __IM uint32_t RESERVED1;
+ __IM uint32_t ADCSTATE; /*!< (@ 0x0000005C) ADC State register. */
+ __IOM uint32_t INTSTS; /*!< (@ 0x00000060) Analog interrupt status register. */
+ __IOM uint32_t INTEN; /*!< (@ 0x00000064) Analog interrupt enable register. */
+ __IOM uint32_t ADCCTRL0; /*!< (@ 0x00000068) ADC control register. */
+ __IOM uint32_t CMPCTL; /*!< (@ 0x0000006C) CMP1/CMP2 control register. */
+ __IM uint32_t ADCDATA[16]; /*!< (@ 0x00000070) ADC channel x data register. */
+ __IOM uint32_t CMPCNT1; /*!< (@ 0x000000B0) Comparator x counter. */
+ __IOM uint32_t CMPCNT2; /*!< (@ 0x000000B4) Comparator x counter. */
+ __IOM uint32_t MISC; /*!< (@ 0x000000B8) Analog MISC control register. */
+ __IM uint32_t RESERVED2;
+ __IM uint32_t ADCDOS; /*!< (@ 0x000000C0) ANA_ADCDOS. */
+ __IM uint32_t RESERVED3[7];
+ __IM uint32_t ADCDATADMA; /*!< (@ 0x000000E0) ANA_ADCDATADMA. */
+ __IOM uint32_t CMPTHR; /*!< (@ 0x000000E4) CMP1/CMP2 threshold register. */
+ __IOM uint32_t ADCCTRL1; /*!< (@ 0x000000E8) ANA_ADCCTRL1. */
+ __IOM uint32_t ADCCTRL2; /*!< (@ 0x000000EC) ANA_ADCCTRL2. */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t ADCDATATHD1_0; /*!< (@ 0x000000F4) ANA_ADCDATATHD1_0. */
+ __IOM uint32_t ADCDATATHD3_2; /*!< (@ 0x000000F8) ANA_ADCDATATHD3_2. */
+ __IOM uint32_t ADCDATATHD_CH; /*!< (@ 0x000000FC) ANA_ADCDATATHD_CH. */
+} ANA_Type; /*!< Size = 256 (0x100) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CRYPT ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CRYPT accelerate the sign and verify process speed of ECC. (CRYPT)
+ */
+
+typedef struct { /*!< (@ 0x40006000) CRYPT Structure */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000000) CRYPT control register. */
+ __IOM uint32_t PTRA; /*!< (@ 0x00000004) CRYPT pointer A. */
+ __IOM uint32_t PTRB; /*!< (@ 0x00000008) CRYPT pointer B. */
+ __IOM uint32_t PTRO; /*!< (@ 0x0000000C) CRYPT pointer O. */
+ __IM uint32_t CARRY; /*!< (@ 0x00000010) CRYPT carry/borrow bit register. */
+} CRYPT_Type; /*!< Size = 20 (0x14) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA(Direct Memory Access) (DMA)
+ */
+
+typedef struct { /*!< (@ 0x40010000) DMA Structure */
+ __IOM uint32_t IE; /*!< (@ 0x00000000) DMA interrupt enable register. */
+ __IOM uint32_t STS; /*!< (@ 0x00000004) DMA status register. */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t C0CTL; /*!< (@ 0x00000010) DMA channel x control register. */
+ __IOM uint32_t C0SRC; /*!< (@ 0x00000014) DMA source address register. */
+ __IOM uint32_t C0DST; /*!< (@ 0x00000018) DMA channel x destination register. */
+ __IOM uint32_t C0LEN; /*!< (@ 0x0000001C) DMA channel x transfer length register. */
+ __IOM uint32_t C1CTL; /*!< (@ 0x00000020) DMA channel x control register. */
+ __IOM uint32_t C1SRC; /*!< (@ 0x00000024) DMA source address register. */
+ __IOM uint32_t C1DST; /*!< (@ 0x00000028) DMA channel x destination register. */
+ __IOM uint32_t C1LEN; /*!< (@ 0x0000002C) DMA channel x transfer length register. */
+ __IOM uint32_t C2CTL; /*!< (@ 0x00000030) DMA channel x control register. */
+ __IOM uint32_t C2SRC; /*!< (@ 0x00000034) DMA source address register. */
+ __IOM uint32_t C2DST; /*!< (@ 0x00000038) DMA channel x destination register. */
+ __IOM uint32_t C2LEN; /*!< (@ 0x0000003C) DMA channel x transfer length register. */
+ __IOM uint32_t C3CTL; /*!< (@ 0x00000040) DMA channel x control register. */
+ __IOM uint32_t C3SRC; /*!< (@ 0x00000044) DMA source address register. */
+ __IOM uint32_t C3DST; /*!< (@ 0x00000048) DMA channel x destination register. */
+ __IOM uint32_t C3LEN; /*!< (@ 0x0000004C) DMA channel x transfer length register. */
+ __IOM uint32_t AESCTL; /*!< (@ 0x00000050) DMA AES control register. */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t AESKEY[8]; /*!< (@ 0x00000060) DMA AES key x register. When mode is AES128,
+ only register KEY3~KEY0 is used. When mode
+ is AES192, only register KEY5~KEY0 is used.
+ When mode is AES256, register KEY7~KEY0
+ is used. */
+} DMA_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ FLASH ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief FLASH Register (FLASH)
+ */
+
+typedef struct { /*!< (@ 0x000FFF00) FLASH Structure */
+ __IM uint32_t RESERVED[42];
+ __IOM uint32_t ICEPROT; /*!< (@ 0x000000A8) ICE protect register. */
+ __IM uint32_t RDPROT; /*!< (@ 0x000000AC) Flash read protect status register */
+ __IOM uint32_t WRPROT; /*!< (@ 0x000000B0) Flash write protect control register */
+ __IM uint32_t RESERVED1[2];
+ __IM uint32_t STS; /*!< (@ 0x000000BC) Flash programming status register. */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t INTSTS; /*!< (@ 0x000000CC) FLASH Checksum interrupt status */
+ __IOM uint32_t CSSADDR; /*!< (@ 0x000000D0) FLASH Checksum start address */
+ __IOM uint32_t CSEADDR; /*!< (@ 0x000000D4) FLASH Checksum end address. */
+ __IM uint32_t CSVALUE; /*!< (@ 0x000000D8) FLASH Checksum value register */
+ __IOM uint32_t CSCVALUE; /*!< (@ 0x000000DC) FLASH Checksum compare value register. */
+ __IOM uint32_t PASS; /*!< (@ 0x000000E0) FLASH password register */
+ __IOM uint32_t CTRL; /*!< (@ 0x000000E4) FLASH control register. */
+ __IOM uint32_t PGADDR; /*!< (@ 0x000000E8) FLASH program address register. */
+ __IOM uint32_t PGDATA; /*!< (@ 0x000000EC) FLASH program word data register. */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t SERASE; /*!< (@ 0x000000F4) FLASH sector erase control register. */
+ __IOM uint32_t CERASE; /*!< (@ 0x000000F8) FLASH chip erase control register. */
+ __IOM uint32_t DSTB; /*!< (@ 0x000000FC) FLASH deep standby control register. */
+} FLASH_Type; /*!< Size = 256 (0x100) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOA ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief The GPIO controller is used to control the GPIOs of TARGET. (GPIOA)
+ */
+
+typedef struct { /*!< (@ 0x40014010) GPIOA Structure */
+ __IOM uint32_t OEN; /*!< (@ 0x00000000) IOA output enable register */
+ __IOM uint32_t IE; /*!< (@ 0x00000004) IOA input enable register */
+ __IOM uint32_t DAT; /*!< (@ 0x00000008) IOA data register */
+ __IOM uint32_t ATT; /*!< (@ 0x0000000C) IOA attribute register */
+ __IOM uint32_t IOAWKUEN; /*!< (@ 0x00000010) IOA wake-up enable register */
+ __IM uint32_t STS; /*!< (@ 0x00000014) IOA input status register */
+ __IOM uint32_t IOAINTSTS; /*!< (@ 0x00000018) IOA interrupt status register. */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t SEL; /*!< (@ 0x00000028) IOA special function select register. */
+ __IM uint32_t RESERVED1[5];
+ __IOM uint32_t IOANODEG; /*!< (@ 0x00000040) IOA no-deglitch control register. */
+} GPIOA_Type; /*!< Size = 68 (0x44) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIO ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief The GPIO controller is used to control the GPIOs of TARGET. (GPIO)
+ */
+
+typedef struct { /*!< (@ 0x40000020) GPIO Structure */
+ __IOM uint32_t OEN; /*!< (@ 0x00000000) IO output enable register */
+ __IOM uint32_t IE; /*!< (@ 0x00000004) IO input enable register */
+ __IOM uint32_t DAT; /*!< (@ 0x00000008) IO data register */
+ __IOM uint32_t ATT; /*!< (@ 0x0000000C) IO attribute register */
+ __IM uint32_t STS; /*!< (@ 0x00000010) IO input status register */
+} GPIO_Type; /*!< Size = 20 (0x14) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOAF ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief The GPIO controller is used to control the GPIOs of TARGET. (GPIOAF)
+ */
+
+typedef struct { /*!< (@ 0x400000C0) GPIOAF Structure */
+ __IOM uint32_t IOB_SEL; /*!< (@ 0x00000000) IOB special function select register. */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t IOE_SEL; /*!< (@ 0x0000000C) IOE special function select register. */
+ __IM uint32_t RESERVED1[4];
+ __IOM uint32_t IO_MISC; /*!< (@ 0x00000020) IO misc. control register. */
+} GPIOAF_Type; /*!< Size = 36 (0x24) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2C ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C-Inter Integrated Circuit (I2C)
+ */
+
+typedef struct { /*!< (@ 0x40010800) I2C Structure */
+ __IOM uint32_t DATA; /*!< (@ 0x00000000) I2C data register. */
+ __IOM uint32_t ADDR; /*!< (@ 0x00000004) I2C address register. */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000008) I2C control/status register. */
+ __IM uint32_t STS; /*!< (@ 0x0000000C) I2C status register. */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CTRL2; /*!< (@ 0x00000018) I2C interrupt enable register. */
+} I2C_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ISO7816 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief The ISO7816 controller is an enhance UART protocol which is able to do half-duplex communication on the 2 wires bus. (ISO7816)
+ */
+
+typedef struct { /*!< (@ 0x40012000) ISO7816 Structure */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t BAUDDIVL; /*!< (@ 0x00000004) ISO7816 baud-rate low byte register */
+ __IOM uint32_t BAUDDIVH; /*!< (@ 0x00000008) ISO7816 baud-rate high byte register */
+ __IOM uint32_t DATA; /*!< (@ 0x0000000C) ISO7816 data register. */
+ __IOM uint32_t INFO; /*!< (@ 0x00000010) ISO7816 information register. */
+ __IOM uint32_t CFG; /*!< (@ 0x00000014) ISO7816 control register. */
+ __IOM uint32_t CLK; /*!< (@ 0x00000018) ISO7816 clock divider control register. */
+} ISO7816_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ LCD ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief The LCD controller is used to display content on the LCD panel. (LCD)
+ */
+
+typedef struct { /*!< (@ 0x40002000) LCD Structure */
+ __IOM uint32_t FB[40]; /*!< (@ 0x00000000) LCD Frame buffer x register */
+ __IM uint32_t RESERVED[24];
+ __IOM uint32_t CTRL; /*!< (@ 0x00000100) LCD control register. */
+ __IOM uint32_t CTRL2; /*!< (@ 0x00000104) LCD control register2. */
+ __IOM uint32_t SEGCTRL0; /*!< (@ 0x00000108) LCD segment enable control register 0 */
+ __IOM uint32_t SEGCTRL1; /*!< (@ 0x0000010C) LCD segment enable control register 1 */
+ __IOM uint32_t SEGCTRL2; /*!< (@ 0x00000110) LCD segment enable control register 2 */
+} LCD_Type; /*!< Size = 276 (0x114) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ MISC1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief The MISC controller is used to control some special function of TARGET, which will be power-off during sleep and deep-sleep mode. (MISC1)
+ */
+
+typedef struct { /*!< (@ 0x40013000) MISC1 Structure */
+ __IOM uint32_t SRAMINT; /*!< (@ 0x00000000) SRAM Parity Error Interrupt. */
+ __IOM uint32_t SRAMINIT; /*!< (@ 0x00000004) SRAM initialize register. */
+ __IM uint32_t PARERR; /*!< (@ 0x00000008) SRAM Parity Error address register. */
+ __IOM uint32_t IREN; /*!< (@ 0x0000000C) IR enable control register. */
+ __IOM uint32_t DUTYL; /*!< (@ 0x00000010) IR Duty low pulse control register. */
+ __IOM uint32_t DUTYH; /*!< (@ 0x00000014) IR Duty high pulse control register. */
+ __IOM uint32_t IRQLAT; /*!< (@ 0x00000018) Cortex M0 IRQ latency control register. */
+ __IM uint32_t RESERVED;
+ __IM uint32_t HIADDR; /*!< (@ 0x00000020) AHB invalid access address. */
+ __IM uint32_t PIADDR; /*!< (@ 0x00000024) APB invalid access address. */
+} MISC1_Type; /*!< Size = 40 (0x28) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ MISC2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief MISC2 controller is in retention domain which will be power-off at deep-sleep mode. (MISC2)
+ */
+
+typedef struct { /*!< (@ 0x40013E00) MISC2 Structure */
+ __IOM uint32_t FLASHWC; /*!< (@ 0x00000000) Flash wait cycle register. */
+ __IOM uint32_t CLKSEL; /*!< (@ 0x00000004) Clock selection register. */
+ __IOM uint32_t CLKDIVH; /*!< (@ 0x00000008) AHB clock divider control register. */
+ __IOM uint32_t CLKDIVP; /*!< (@ 0x0000000C) APB clock divider control register. */
+ __IOM uint32_t HCLKEN; /*!< (@ 0x00000010) AHB clock enable control register. */
+ __IOM uint32_t PCLKEN; /*!< (@ 0x00000014) APB clock enable control register. */
+} MISC2_Type; /*!< Size = 24 (0x18) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PMU ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Power Management Unit. (PMU)
+ */
+
+typedef struct { /*!< (@ 0x40014000) PMU Structure */
+ __IOM uint32_t DSLEEPEN; /*!< (@ 0x00000000) PMU deep sleep enable register. */
+ __IOM uint32_t DSLEEPPASS; /*!< (@ 0x00000004) PMU deep sleep password register. */
+ __IOM uint32_t CONTROL; /*!< (@ 0x00000008) PMU control register. */
+ __IOM uint32_t STS; /*!< (@ 0x0000000C) PMU Status register. */
+ __IM uint32_t RESERVED[12];
+ __IOM uint32_t WDTPASS; /*!< (@ 0x00000040) Watch dog timing unlock register. */
+ __IOM uint32_t WDTEN; /*!< (@ 0x00000044) Watch dog timer enable register. */
+ __IOM uint32_t WDTCLR; /*!< (@ 0x00000048) Watch dog timer clear register. */
+ __IM uint32_t RESERVED1[237];
+ __IOM uint32_t RAM[64]; /*!< (@ 0x00000400) PMU 32 bits Retention RAM x. */
+} PMU_Type; /*!< Size = 1280 (0x500) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PWM ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Timers are 16 bits timers with PWM and capture function. (PWM)
+ */
+
+typedef struct { /*!< (@ 0x40012900) PWM Structure */
+ __IOM uint32_t CTL; /*!< (@ 0x00000000) Control register of PWM Timer 0 */
+ __IM uint32_t TAR; /*!< (@ 0x00000004) Current count register of PWM Timer x. */
+ __IOM uint32_t CCTL[3]; /*!< (@ 0x00000008) Compare/capture control register x(x=0~3) for
+ PWM timer x. */
+ __IOM uint32_t CCR[3]; /*!< (@ 0x00000014) Compare/capture data register x for PWM timer
+ x. */
+} PWM_Type; /*!< Size = 32 (0x20) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PWM_SEL ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Timers are 16 bits timers with PWM and capture function. (PWM_SEL)
+ */
+
+typedef struct { /*!< (@ 0x400129F0) PWM_SEL Structure */
+ __IOM uint32_t O_SEL; /*!< (@ 0x00000000) PWM output selection register. */
+ __IOM uint32_t I_SEL01; /*!< (@ 0x00000004) Input of PWM0 and PWM1 selection register. */
+ __IOM uint32_t I_SEL23; /*!< (@ 0x00000008) Input of PWM2 and PWM3 selection register. */
+} PWM_SEL_Type; /*!< Size = 12 (0xc) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RTC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief The RTC controller is used to control time calculation and RTC auto calibration function. (RTC)
+ */
+
+typedef struct { /*!< (@ 0x40014800) RTC Structure */
+ __IOM uint32_t SEC; /*!< (@ 0x00000000) RTC second register */
+ __IOM uint32_t MIN; /*!< (@ 0x00000004) RTC minute register */
+ __IOM uint32_t HOUR; /*!< (@ 0x00000008) RTC hour register */
+ __IOM uint32_t DAY; /*!< (@ 0x0000000C) RTC day register */
+ __IOM uint32_t WEEK; /*!< (@ 0x00000010) RTC week register */
+ __IOM uint32_t MON; /*!< (@ 0x00000014) RTC mon register */
+ __IOM uint32_t YEAR; /*!< (@ 0x00000018) RTC year register */
+ __IOM uint32_t TIME; /*!< (@ 0x0000001C) RTC accurate second/millisecond register */
+ __IOM uint32_t WKUSEC; /*!< (@ 0x00000020) RTC wake-up second register. */
+ __IOM uint32_t WKUMIN; /*!< (@ 0x00000024) RTC wake-up minute register */
+ __IOM uint32_t WKUHOUR; /*!< (@ 0x00000028) RTC wake-up hour register */
+ __IOM uint32_t WKUCNT; /*!< (@ 0x0000002C) RTC wake-up counter register */
+ __IOM uint32_t CAL; /*!< (@ 0x00000030) RTC calibration register */
+ __IOM uint32_t DIV; /*!< (@ 0x00000034) RTC calibration register */
+ __IOM uint32_t CTL; /*!< (@ 0x00000038) RTC PLL divider control register. */
+ __IOM uint32_t ITV; /*!< (@ 0x0000003C) RTC wake-up interval control */
+ __IOM uint32_t SITV; /*!< (@ 0x00000040) RTC wake-up second interval control */
+ __IOM uint32_t PWD; /*!< (@ 0x00000044) RTC password control register. */
+ __IOM uint32_t CE; /*!< (@ 0x00000048) RTC write enable control register. */
+ __IM uint32_t LOAD; /*!< (@ 0x0000004C) RTC read enable control register */
+ __IOM uint32_t INTSTS; /*!< (@ 0x00000050) RTC interrupt status control register */
+ __IOM uint32_t INTEN; /*!< (@ 0x00000054) RTC interrupt enable control register */
+ __IOM uint32_t PSCA; /*!< (@ 0x00000058) RTC clock pre-scaler control register. */
+ __IM uint32_t RESERVED[10];
+ __IOM uint32_t ACTI; /*!< (@ 0x00000084) RTC auto-calibration center temperature control
+ register. */
+ __IOM uint32_t ACF200; /*!< (@ 0x00000088) RTC auto-calibration 200*frequency control register. */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t ACP0; /*!< (@ 0x00000090) RTC parameter P0 register. */
+ __IOM uint32_t ACP1; /*!< (@ 0x00000094) RTC parameter P1 register. */
+ __IOM uint32_t ACP2; /*!< (@ 0x00000098) RTC parameter P2 register. */
+ __IM uint32_t ACP3; /*!< (@ 0x0000009C) RTC parameter P3 register. */
+ __IOM uint32_t ACP4; /*!< (@ 0x000000A0) RTC parameter P4 register. */
+ __IOM uint32_t ACP5; /*!< (@ 0x000000A4) RTC parameter P5 register. */
+ __IOM uint32_t ACP6; /*!< (@ 0x000000A8) RTC parameter P6 register. */
+ __IOM uint32_t ACP7; /*!< (@ 0x000000AC) RTC parameter P7 register. */
+ __IOM uint32_t ACK[5]; /*!< (@ 0x000000B0) RTC auto-calibration parameter Kx control register. */
+ __IM uint32_t RESERVED2[2];
+ __IM uint32_t WKUCNTR; /*!< (@ 0x000000CC) This register is used to represent the current
+ WKUCNT value. */
+ __IOM uint32_t ACKTEMP; /*!< (@ 0x000000D0) RTC auto-calibration k temperature section control
+ register. */
+ __IOM uint32_t ALARMTIME; /*!< (@ 0x000000D4) RTC alarm accurate second/millisecond. */
+ __IOM uint32_t ALARMSEC; /*!< (@ 0x000000D8) RTC alarm inaccurate second */
+ __IOM uint32_t ALARMMIN; /*!< (@ 0x000000DC) RTC alarm minute */
+ __IOM uint32_t ALARMHOUR; /*!< (@ 0x000000E0) RTC alarm hour */
+ __IOM uint32_t ALARMCTL; /*!< (@ 0x000000E4) RTC alarm control */
+ __IOM uint32_t ADCUCALK; /*!< (@ 0x000000E8) RTC ADC Ucal K coefficients */
+ __IOM uint32_t ADCMACTL; /*!< (@ 0x000000EC) RTC ADC control */
+} RTC_Type; /*!< Size = 240 (0xf0) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI(Serial Peripheral Interface). (SPI)
+ */
+
+typedef struct { /*!< (@ 0x40011000) SPI Structure */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000000) SPI Control Register. */
+ __IOM uint32_t TXSTS; /*!< (@ 0x00000004) SPI Transmit Status Register. */
+ __IOM uint32_t TXDAT; /*!< (@ 0x00000008) SPI Transmit FIFO register. */
+ __IOM uint32_t RXSTS; /*!< (@ 0x0000000C) SPI Receive Status Register. */
+ __IM uint32_t RXDAT; /*!< (@ 0x00000010) SPI Receive FIFO Register. */
+ __IOM uint32_t MISC; /*!< (@ 0x00000014) SPI Misc. Control Register. */
+} SPI_Type; /*!< Size = 24 (0x18) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief General purpose 32 bits timer, which are used to generate regulate interrupt for CM0. (TMR)
+ */
+
+typedef struct { /*!< (@ 0x40012800) TMR Structure */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register of Timer x */
+ __IOM uint32_t VALUE; /*!< (@ 0x00000004) Current count register of Timer x */
+ __IOM uint32_t RELOAD; /*!< (@ 0x00000008) Reload register of Timer x. */
+ __IOM uint32_t INTSTS; /*!< (@ 0x0000000C) Interrupt status register of Timer x. */
+} TMR_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART(Universal Asynchronous Receiver/Transmitter). (UART)
+ */
+
+typedef struct { /*!< (@ 0x40011800) UART Structure */
+ __IOM uint32_t DATA; /*!< (@ 0x00000000) UART data register. */
+ __IOM uint32_t STATE; /*!< (@ 0x00000004) UART status register. */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000008) UART control register. */
+ __IOM uint32_t INTSTS; /*!< (@ 0x0000000C) UART interrupt status register. */
+ __IOM uint32_t BAUDDIV; /*!< (@ 0x00000010) UART baud rate divide register. */
+ __IOM uint32_t CTRL2; /*!< (@ 0x00000014) UART control register 2. */
+} UART_Type; /*!< Size = 24 (0x18) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ U32K ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief The UART 32K controller is used to receive data via UART protocol. (U32K)
+ */
+
+typedef struct { /*!< (@ 0x40014100) U32K Structure */
+ __IOM uint32_t CTRL0; /*!< (@ 0x00000000) UART 32K x control register 0. */
+ __IOM uint32_t CTRL1; /*!< (@ 0x00000004) UART 32K x control register 1. */
+ __IOM uint32_t BAUDDIV; /*!< (@ 0x00000008) UART 32K x baud rate control register. */
+ __IM uint32_t DATA; /*!< (@ 0x0000000C) UART 32K x receive data buffer. */
+ __IOM uint32_t STS; /*!< (@ 0x00000010) UART 32K x interrupt status register. */
+} U32K_Type; /*!< Size = 20 (0x14) */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+#define ANA_BASE 0x40014200UL
+#define CRYPT_BASE 0x40006000UL
+#define DMA_BASE 0x40010000UL
+#define FLASH_BASE 0x000FFF00UL
+#define GPIOA_BASE 0x40014010UL
+#define GPIOB_BASE 0x40000020UL
+#define GPIOC_BASE 0x40000040UL
+#define GPIOD_BASE 0x40000060UL
+#define GPIOE_BASE 0x40000080UL
+#define GPIOF_BASE 0x400000A0UL
+#define GPIOAF_BASE 0x400000C0UL
+#define I2C_BASE 0x40010800UL
+#define ISO78160_BASE 0x40012000UL
+#define ISO78161_BASE 0x40012040UL
+#define LCD_BASE 0x40002000UL
+#define MISC1_BASE 0x40013000UL
+#define MISC2_BASE 0x40013E00UL
+#define PMU_BASE 0x40014000UL
+#define PWM0_BASE 0x40012900UL
+#define PWM1_BASE 0x40012920UL
+#define PWM2_BASE 0x40012940UL
+#define PWM3_BASE 0x40012960UL
+#define PWM_SEL_BASE 0x400129F0UL
+#define RTC_BASE 0x40014800UL
+#define SPI1_BASE 0x40011000UL
+#define SPI2_BASE 0x40015800UL
+#define SPI3_BASE 0x40016000UL
+#define TMR0_BASE 0x40012800UL
+#define TMR1_BASE 0x40012820UL
+#define TMR2_BASE 0x40012840UL
+#define TMR3_BASE 0x40012860UL
+#define UART0_BASE 0x40011800UL
+#define UART1_BASE 0x40011820UL
+#define UART2_BASE 0x40011840UL
+#define UART3_BASE 0x40011860UL
+#define UART4_BASE 0x40011880UL
+#define UART5_BASE 0x400118A0UL
+#define U32K0_BASE 0x40014100UL
+#define U32K1_BASE 0x40014180UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+#define ANA ((ANA_Type*) ANA_BASE)
+#define CRYPT ((CRYPT_Type*) CRYPT_BASE)
+#define DMA ((DMA_Type*) DMA_BASE)
+#define FLASH ((FLASH_Type*) FLASH_BASE)
+#define GPIOA ((GPIOA_Type*) GPIOA_BASE)
+#define GPIOB ((GPIO_Type*) GPIOB_BASE)
+#define GPIOC ((GPIO_Type*) GPIOC_BASE)
+#define GPIOD ((GPIO_Type*) GPIOD_BASE)
+#define GPIOE ((GPIO_Type*) GPIOE_BASE)
+#define GPIOF ((GPIO_Type*) GPIOF_BASE)
+#define GPIOAF ((GPIOAF_Type*) GPIOAF_BASE)
+#define I2C ((I2C_Type*) I2C_BASE)
+#define ISO78160 ((ISO7816_Type*) ISO78160_BASE)
+#define ISO78161 ((ISO7816_Type*) ISO78161_BASE)
+#define LCD ((LCD_Type*) LCD_BASE)
+#define MISC1 ((MISC1_Type*) MISC1_BASE)
+#define MISC2 ((MISC2_Type*) MISC2_BASE)
+#define PMU ((PMU_Type*) PMU_BASE)
+#define PWM0 ((PWM_Type*) PWM0_BASE)
+#define PWM1 ((PWM_Type*) PWM1_BASE)
+#define PWM2 ((PWM_Type*) PWM2_BASE)
+#define PWM3 ((PWM_Type*) PWM3_BASE)
+#define PWM_SEL ((PWM_SEL_Type*) PWM_SEL_BASE)
+#define RTC ((RTC_Type*) RTC_BASE)
+#define SPI1 ((SPI_Type*) SPI1_BASE)
+#define SPI2 ((SPI_Type*) SPI2_BASE)
+#define SPI3 ((SPI_Type*) SPI3_BASE)
+#define TMR0 ((TMR_Type*) TMR0_BASE)
+#define TMR1 ((TMR_Type*) TMR1_BASE)
+#define TMR2 ((TMR_Type*) TMR2_BASE)
+#define TMR3 ((TMR_Type*) TMR3_BASE)
+#define UART0 ((UART_Type*) UART0_BASE)
+#define UART1 ((UART_Type*) UART1_BASE)
+#define UART2 ((UART_Type*) UART2_BASE)
+#define UART3 ((UART_Type*) UART3_BASE)
+#define UART4 ((UART_Type*) UART4_BASE)
+#define UART5 ((UART_Type*) UART5_BASE)
+#define U32K0 ((U32K_Type*) U32K0_BASE)
+#define U32K1 ((U32K_Type*) U32K1_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+
+/* =========================================================================================================================== */
+/* ================ Pos/Mask Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup PosMask_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ANA ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= REG0 ========================================================== */
+#define ANA_REG0_ADCFRQSEL_Pos (0UL) /*!< ANA REG0: ADCFRQSEL (Bit 0) */
+#define ANA_REG0_ADCFRQSEL_Msk (0x1UL) /*!< ANA REG0: ADCFRQSEL (Bitfield-Mask: 0x01) */
+#define ANA_REG0_ADCFRQSEL ANA_REG0_ADCFRQSEL_Msk
+/* ========================================================= REG1 ========================================================== */
+#define ANA_REG1_ADCMODESEL_Pos (7UL) /*!< ANA REG1: ADCMODESEL (Bit 7) */
+#define ANA_REG1_ADCMODESEL_Msk (0x80UL) /*!< ANA REG1: ADCMODESEL (Bitfield-Mask: 0x01) */
+#define ANA_REG1_ADCMODESEL ANA_REG1_ADCMODESEL_Msk
+/* ========================================================= REG2 ========================================================== */
+#define ANA_REG2_CMP2REFSEL_Pos (5UL) /*!< ANA REG2: CMP2REFSEL (Bit 5) */
+#define ANA_REG2_CMP2REFSEL_Msk (0x20UL) /*!< ANA REG2: CMP2REFSEL (Bitfield-Mask: 0x01) */
+#define ANA_REG2_CMP2REFSEL ANA_REG2_CMP2REFSEL_Msk
+#define ANA_REG2_CMP1REFSEL_Pos (4UL) /*!< ANA REG2: CMP1REFSEL (Bit 4) */
+#define ANA_REG2_CMP1REFSEL_Msk (0x10UL) /*!< ANA REG2: CMP1REFSEL (Bitfield-Mask: 0x01) */
+#define ANA_REG2_CMP1REFSEL ANA_REG2_CMP1REFSEL_Msk
+#define ANA_REG2_CMP2SEL_Pos (2UL) /*!< ANA REG2: CMP2SEL (Bit 2) */
+#define ANA_REG2_CMP2SEL_Msk (0xcUL) /*!< ANA REG2: CMP2SEL (Bitfield-Mask: 0x03) */
+#define ANA_REG2_CMP2SEL ANA_REG2_CMP2SEL_Msk
+#define ANA_REG2_CMP1SEL_Pos (0UL) /*!< ANA REG2: CMP1SEL (Bit 0) */
+#define ANA_REG2_CMP1SEL_Msk (0x3UL) /*!< ANA REG2: CMP1SEL (Bitfield-Mask: 0x03) */
+#define ANA_REG2_CMP1SEL ANA_REG2_CMP1SEL_Msk
+/* ========================================================= REG3 ========================================================== */
+#define ANA_REG3_XOHPDN_Pos (7UL) /*!< ANA REG3: XOHPDN (Bit 7) */
+#define ANA_REG3_XOHPDN_Msk (0x80UL) /*!< ANA REG3: XOHPDN (Bitfield-Mask: 0x01) */
+#define ANA_REG3_XOHPDN ANA_REG3_XOHPDN_Msk
+#define ANA_REG3_PLLHPDN_Pos (6UL) /*!< ANA REG3: PLLHPDN (Bit 6) */
+#define ANA_REG3_PLLHPDN_Msk (0x40UL) /*!< ANA REG3: PLLHPDN (Bitfield-Mask: 0x01) */
+#define ANA_REG3_PLLHPDN ANA_REG3_PLLHPDN_Msk
+#define ANA_REG3_PLLLPDN_Pos (5UL) /*!< ANA REG3: PLLLPDN (Bit 5) */
+#define ANA_REG3_PLLLPDN_Msk (0x20UL) /*!< ANA REG3: PLLLPDN (Bitfield-Mask: 0x01) */
+#define ANA_REG3_PLLLPDN ANA_REG3_PLLLPDN_Msk
+#define ANA_REG3_RCHPD_Pos (4UL) /*!< ANA REG3: RCHPD (Bit 4) */
+#define ANA_REG3_RCHPD_Msk (0x10UL) /*!< ANA REG3: RCHPD (Bitfield-Mask: 0x01) */
+#define ANA_REG3_RCHPD ANA_REG3_RCHPD_Msk
+#define ANA_REG3_BGPPD_Pos (3UL) /*!< ANA REG3: BGPPD (Bit 3) */
+#define ANA_REG3_BGPPD_Msk (0x8UL) /*!< ANA REG3: BGPPD (Bitfield-Mask: 0x01) */
+#define ANA_REG3_BGPPD ANA_REG3_BGPPD_Msk
+#define ANA_REG3_CMP2PDN_Pos (2UL) /*!< ANA REG3: CMP2PDN (Bit 2) */
+#define ANA_REG3_CMP2PDN_Msk (0x4UL) /*!< ANA REG3: CMP2PDN (Bitfield-Mask: 0x01) */
+#define ANA_REG3_CMP2PDN ANA_REG3_CMP2PDN_Msk
+#define ANA_REG3_CMP1PDN_Pos (1UL) /*!< ANA REG3: CMP1PDN (Bit 1) */
+#define ANA_REG3_CMP1PDN_Msk (0x2UL) /*!< ANA REG3: CMP1PDN (Bitfield-Mask: 0x01) */
+#define ANA_REG3_CMP1PDN ANA_REG3_CMP1PDN_Msk
+/* ========================================================= REG4 ========================================================== */
+/* ========================================================= REG5 ========================================================== */
+#define ANA_REG5_AVCCLVDETPD_Pos (6UL) /*!< ANA REG5: AVCCLVDETPD (Bit 6) */
+#define ANA_REG5_AVCCLVDETPD_Msk (0x40UL) /*!< ANA REG5: AVCCLVDETPD (Bitfield-Mask: 0x01) */
+#define ANA_REG5_AVCCLVDETPD ANA_REG5_AVCCLVDETPD_Msk
+#define ANA_REG5_CMP2IT_Pos (2UL) /*!< ANA REG5: CMP2IT (Bit 2) */
+#define ANA_REG5_CMP2IT_Msk (0xcUL) /*!< ANA REG5: CMP2IT (Bitfield-Mask: 0x03) */
+#define ANA_REG5_CMP2IT ANA_REG5_CMP2IT_Msk
+#define ANA_REG5_CMP1IT_Pos (0UL) /*!< ANA REG5: CMP1IT (Bit 0) */
+#define ANA_REG5_CMP1IT_Msk (0x3UL) /*!< ANA REG5: CMP1IT (Bitfield-Mask: 0x03) */
+#define ANA_REG5_CMP1IT ANA_REG5_CMP1IT_Msk
+/* ========================================================= REG6 ========================================================== */
+#define ANA_REG6_BATRTCDISC_Pos (7UL) /*!< ANA REG6: BATRTCDISC (Bit 7) */
+#define ANA_REG6_BATRTCDISC_Msk (0x80UL) /*!< ANA REG6: BATRTCDISC (Bitfield-Mask: 0x01) */
+#define ANA_REG6_BATRTCDISC ANA_REG6_BATRTCDISC_Msk
+#define ANA_REG6_BAT1DISC_Pos (6UL) /*!< ANA REG6: BAT1DISC (Bit 6) */
+#define ANA_REG6_BAT1DISC_Msk (0x40UL) /*!< ANA REG6: BAT1DISC (Bitfield-Mask: 0x01) */
+#define ANA_REG6_BAT1DISC ANA_REG6_BAT1DISC_Msk
+#define ANA_REG6_LCDBMODE_Pos (0UL) /*!< ANA REG6: LCDBMODE (Bit 0) */
+#define ANA_REG6_LCDBMODE_Msk (0x1UL) /*!< ANA REG6: LCDBMODE (Bitfield-Mask: 0x01) */
+#define ANA_REG6_LCDBMODE ANA_REG6_LCDBMODE_Msk
+/* ========================================================= REG7 ========================================================== */
+/* ========================================================= REG8 ========================================================== */
+#define ANA_REG8_AVCCLDOPD_Pos (7UL) /*!< ANA REG8: AVCCLDOPD (Bit 7) */
+#define ANA_REG8_AVCCLDOPD_Msk (0x80UL) /*!< ANA REG8: AVCCLDOPD (Bitfield-Mask: 0x01) */
+#define ANA_REG8_AVCCLDOPD ANA_REG8_AVCCLDOPD_Msk
+#define ANA_REG8_VDDPVDSEL_Pos (4UL) /*!< ANA REG8: VDDPVDSEL (Bit 4) */
+#define ANA_REG8_VDDPVDSEL_Msk (0x70UL) /*!< ANA REG8: VDDPVDSEL (Bitfield-Mask: 0x07) */
+#define ANA_REG8_VDDPVDSEL ANA_REG8_VDDPVDSEL_Msk
+#define ANA_REG8_DVCCSEL_Pos (0UL) /*!< ANA REG8: DVCCSEL (Bit 0) */
+#define ANA_REG8_DVCCSEL_Msk (0x3UL) /*!< ANA REG8: DVCCSEL (Bitfield-Mask: 0x03) */
+#define ANA_REG8_DVCCSEL ANA_REG8_DVCCSEL_Msk
+/* ========================================================= REG9 ========================================================== */
+#define ANA_REG9_VDDDETPD_Pos (7UL) /*!< ANA REG9: VDDDETPD (Bit 7) */
+#define ANA_REG9_VDDDETPD_Msk (0x80UL) /*!< ANA REG9: VDDDETPD (Bitfield-Mask: 0x01) */
+#define ANA_REG9_VDDDETPD ANA_REG9_VDDDETPD_Msk
+#define ANA_REG9_PLLHSEL_Pos (3UL) /*!< ANA REG9: PLLHSEL (Bit 3) */
+#define ANA_REG9_PLLHSEL_Msk (0x78UL) /*!< ANA REG9: PLLHSEL (Bitfield-Mask: 0x0f) */
+#define ANA_REG9_PLLHSEL ANA_REG9_PLLHSEL_Msk
+#define ANA_REG9_PLLLSEL_Pos (0UL) /*!< ANA REG9: PLLLSEL (Bit 0) */
+#define ANA_REG9_PLLLSEL_Msk (0x7UL) /*!< ANA REG9: PLLLSEL (Bitfield-Mask: 0x07) */
+#define ANA_REG9_PLLLSEL ANA_REG9_PLLLSEL_Msk
+/* ========================================================= REGA ========================================================== */
+#define ANA_REGA_VDCINDETPD_Pos (7UL) /*!< ANA REGA: VDCINDETPD (Bit 7) */
+#define ANA_REGA_VDCINDETPD_Msk (0x80UL) /*!< ANA REGA: VDCINDETPD (Bitfield-Mask: 0x01) */
+#define ANA_REGA_VDCINDETPD ANA_REGA_VDCINDETPD_Msk
+/* ========================================================= REGB ========================================================== */
+#define ANA_REGB_RCLTRIM_Pos (0UL) /*!< ANA REGB: RCLTRIM (Bit 0) */
+#define ANA_REGB_RCLTRIM_Msk (0x1fUL) /*!< ANA REGB: RCLTRIM (Bitfield-Mask: 0x1f) */
+#define ANA_REGB_RCLTRIM ANA_REGB_RCLTRIM_Msk
+/* ========================================================= REGC ========================================================== */
+#define ANA_REGC_RCHTRIM_Pos (0UL) /*!< ANA REGC: RCHTRIM (Bit 0) */
+#define ANA_REGC_RCHTRIM_Msk (0x3fUL) /*!< ANA REGC: RCHTRIM (Bitfield-Mask: 0x3f) */
+#define ANA_REGC_RCHTRIM ANA_REGC_RCHTRIM_Msk
+/* ========================================================= REGD ========================================================== */
+/* ========================================================= REGE ========================================================== */
+#define ANA_REGE_BKPWREN_Pos (7UL) /*!< ANA REGE: BKPWREN (Bit 7) */
+#define ANA_REGE_BKPWREN_Msk (0x80UL) /*!< ANA REGE: BKPWREN (Bitfield-Mask: 0x01) */
+#define ANA_REGE_BKPWREN ANA_REGE_BKPWREN_Msk
+/* ========================================================= REGF ========================================================== */
+#define ANA_REGF_ADTREF3SEL_Pos (7UL) /*!< ANA REGF: ADTREF3SEL (Bit 7) */
+#define ANA_REGF_ADTREF3SEL_Msk (0x80UL) /*!< ANA REGF: ADTREF3SEL (Bitfield-Mask: 0x01) */
+#define ANA_REGF_ADTREF3SEL ANA_REGF_ADTREF3SEL_Msk
+#define ANA_REGF_ADTREF2SEL_Pos (6UL) /*!< ANA REGF: ADTREF2SEL (Bit 6) */
+#define ANA_REGF_ADTREF2SEL_Msk (0x40UL) /*!< ANA REGF: ADTREF2SEL (Bitfield-Mask: 0x01) */
+#define ANA_REGF_ADTREF2SEL ANA_REGF_ADTREF2SEL_Msk
+#define ANA_REGF_ADTREF1SEL_Pos (5UL) /*!< ANA REGF: ADTREF1SEL (Bit 5) */
+#define ANA_REGF_ADTREF1SEL_Msk (0x20UL) /*!< ANA REGF: ADTREF1SEL (Bitfield-Mask: 0x01) */
+#define ANA_REGF_ADTREF1SEL ANA_REGF_ADTREF1SEL_Msk
+#define ANA_REGF_ADTSEL_Pos (4UL) /*!< ANA REGF: ADTSEL (Bit 4) */
+#define ANA_REGF_ADTSEL_Msk (0x10UL) /*!< ANA REGF: ADTSEL (Bitfield-Mask: 0x01) */
+#define ANA_REGF_ADTSEL ANA_REGF_ADTSEL_Msk
+#define ANA_REGF_ADTPDN_Pos (3UL) /*!< ANA REGF: ADTPDN (Bit 3) */
+#define ANA_REGF_ADTPDN_Msk (0x8UL) /*!< ANA REGF: ADTPDN (Bitfield-Mask: 0x01) */
+#define ANA_REGF_ADTPDN ANA_REGF_ADTPDN_Msk
+#define ANA_REGF_AVCCOEN_Pos (2UL) /*!< ANA REGF: AVCCOEN (Bit 2) */
+#define ANA_REGF_AVCCOEN_Msk (0x4UL) /*!< ANA REGF: AVCCOEN (Bitfield-Mask: 0x01) */
+#define ANA_REGF_AVCCOEN ANA_REGF_AVCCOEN_Msk
+#define ANA_REGF_BATRTCDETEN_Pos (1UL) /*!< ANA REGF: BATRTCDETEN (Bit 1) */
+#define ANA_REGF_BATRTCDETEN_Msk (0x2UL) /*!< ANA REGF: BATRTCDETEN (Bitfield-Mask: 0x01) */
+#define ANA_REGF_BATRTCDETEN ANA_REGF_BATRTCDETEN_Msk
+#define ANA_REGF_BAT1DETEN_Pos (0UL) /*!< ANA REGF: BAT1DETEN (Bit 0) */
+#define ANA_REGF_BAT1DETEN_Msk (0x1UL) /*!< ANA REGF: BAT1DETEN (Bitfield-Mask: 0x01) */
+#define ANA_REGF_BAT1DETEN ANA_REGF_BAT1DETEN_Msk
+/* ========================================================= REG10 ========================================================= */
+/* ========================================================= REG11 ========================================================= */
+#define ANA_REG11_VINBUFPD_Pos (7UL) /*!< ANA REG11: VINBUFPD (Bit 7) */
+#define ANA_REG11_VINBUFPD_Msk (0x80UL) /*!< ANA REG11: VINBUFPD (Bitfield-Mask: 0x01) */
+#define ANA_REG11_VINBUFPD ANA_REG11_VINBUFPD_Msk
+#define ANA_REG11_REFBUFPD_Pos (6UL) /*!< ANA REG11: REFBUFPD (Bit 6) */
+#define ANA_REG11_REFBUFPD_Msk (0x40UL) /*!< ANA REG11: REFBUFPD (Bitfield-Mask: 0x01) */
+#define ANA_REG11_REFBUFPD ANA_REG11_REFBUFPD_Msk
+/* ========================================================= CTRL ========================================================== */
+#define ANA_CTRL_PDNS2_Pos (26UL) /*!< ANA CTRL: PDNS2 (Bit 26) */
+#define ANA_CTRL_PDNS2_Msk (0x4000000UL) /*!< ANA CTRL: PDNS2 (Bitfield-Mask: 0x01) */
+#define ANA_CTRL_PDNS2 ANA_CTRL_PDNS2_Msk
+#define ANA_CTRL_CMP2DEB_Pos (22UL) /*!< ANA CTRL: CMP2DEB (Bit 22) */
+#define ANA_CTRL_CMP2DEB_Msk (0xc00000UL) /*!< ANA CTRL: CMP2DEB (Bitfield-Mask: 0x03) */
+#define ANA_CTRL_CMP2DEB ANA_CTRL_CMP2DEB_Msk
+#define ANA_CTRL_CMP1DEB_Pos (20UL) /*!< ANA CTRL: CMP1DEB (Bit 20) */
+#define ANA_CTRL_CMP1DEB_Msk (0x300000UL) /*!< ANA CTRL: CMP1DEB (Bitfield-Mask: 0x03) */
+#define ANA_CTRL_CMP1DEB ANA_CTRL_CMP1DEB_Msk
+#define ANA_CTRL_RCHTGT_Pos (8UL) /*!< ANA CTRL: RCHTGT (Bit 8) */
+#define ANA_CTRL_RCHTGT_Msk (0xff00UL) /*!< ANA CTRL: RCHTGT (Bitfield-Mask: 0xff) */
+#define ANA_CTRL_RCHTGT ANA_CTRL_RCHTGT_Msk
+#define ANA_CTRL_PDNS_Pos (6UL) /*!< ANA CTRL: PDNS (Bit 6) */
+#define ANA_CTRL_PDNS_Msk (0x40UL) /*!< ANA CTRL: PDNS (Bitfield-Mask: 0x01) */
+#define ANA_CTRL_PDNS ANA_CTRL_PDNS_Msk
+#define ANA_CTRL_CMP2SEL_Pos (2UL) /*!< ANA CTRL: CMP2SEL (Bit 2) */
+#define ANA_CTRL_CMP2SEL_Msk (0xcUL) /*!< ANA CTRL: CMP2SEL (Bitfield-Mask: 0x03) */
+#define ANA_CTRL_CMP2SEL ANA_CTRL_CMP2SEL_Msk
+#define ANA_CTRL_CMP1SEL_Pos (0UL) /*!< ANA CTRL: CMP1SEL (Bit 0) */
+#define ANA_CTRL_CMP1SEL_Msk (0x3UL) /*!< ANA CTRL: CMP1SEL (Bitfield-Mask: 0x03) */
+#define ANA_CTRL_CMP1SEL ANA_CTRL_CMP1SEL_Msk
+/* ======================================================== CMPOUT ========================================================= */
+#define ANA_CMPOUT_TADCO_Pos (14UL) /*!< ANA CMPOUT: TADCO (Bit 14) */
+#define ANA_CMPOUT_TADCO_Msk (0xc000UL) /*!< ANA CMPOUT: TADCO (Bitfield-Mask: 0x03) */
+#define ANA_CMPOUT_TADCO ANA_CMPOUT_TADCO_Msk
+#define ANA_CMPOUT_AVCCLV_Pos (10UL) /*!< ANA CMPOUT: AVCCLV (Bit 10) */
+#define ANA_CMPOUT_AVCCLV_Msk (0x400UL) /*!< ANA CMPOUT: AVCCLV (Bitfield-Mask: 0x01) */
+#define ANA_CMPOUT_AVCCLV ANA_CMPOUT_AVCCLV_Msk
+#define ANA_CMPOUT_VDCINDROP_Pos (8UL) /*!< ANA CMPOUT: VDCINDROP (Bit 8) */
+#define ANA_CMPOUT_VDCINDROP_Msk (0x100UL) /*!< ANA CMPOUT: VDCINDROP (Bitfield-Mask: 0x01) */
+#define ANA_CMPOUT_VDCINDROP ANA_CMPOUT_VDCINDROP_Msk
+#define ANA_CMPOUT_VDDALARM_Pos (7UL) /*!< ANA CMPOUT: VDDALARM (Bit 7) */
+#define ANA_CMPOUT_VDDALARM_Msk (0x80UL) /*!< ANA CMPOUT: VDDALARM (Bitfield-Mask: 0x01) */
+#define ANA_CMPOUT_VDDALARM ANA_CMPOUT_VDDALARM_Msk
+#define ANA_CMPOUT_CMP2_Pos (3UL) /*!< ANA CMPOUT: CMP2 (Bit 3) */
+#define ANA_CMPOUT_CMP2_Msk (0x8UL) /*!< ANA CMPOUT: CMP2 (Bitfield-Mask: 0x01) */
+#define ANA_CMPOUT_CMP2 ANA_CMPOUT_CMP2_Msk
+#define ANA_CMPOUT_CMP1_Pos (2UL) /*!< ANA CMPOUT: CMP1 (Bit 2) */
+#define ANA_CMPOUT_CMP1_Msk (0x4UL) /*!< ANA CMPOUT: CMP1 (Bitfield-Mask: 0x01) */
+#define ANA_CMPOUT_CMP1 ANA_CMPOUT_CMP1_Msk
+#define ANA_CMPOUT_LOCKL_Pos (1UL) /*!< ANA CMPOUT: LOCKL (Bit 1) */
+#define ANA_CMPOUT_LOCKL_Msk (0x2UL) /*!< ANA CMPOUT: LOCKL (Bitfield-Mask: 0x01) */
+#define ANA_CMPOUT_LOCKL ANA_CMPOUT_LOCKL_Msk
+#define ANA_CMPOUT_LOCKH_Pos (0UL) /*!< ANA CMPOUT: LOCKH (Bit 0) */
+#define ANA_CMPOUT_LOCKH_Msk (0x1UL) /*!< ANA CMPOUT: LOCKH (Bitfield-Mask: 0x01) */
+#define ANA_CMPOUT_LOCKH ANA_CMPOUT_LOCKH_Msk
+/* ======================================================= ADCSTATE ======================================================== */
+#define ANA_ADCSTATE_CAL_EN_Pos (5UL) /*!< ANA ADCSTATE: CAL_EN (Bit 5) */
+#define ANA_ADCSTATE_CAL_EN_Msk (0x20UL) /*!< ANA ADCSTATE: CAL_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCSTATE_CAL_EN ANA_ADCSTATE_CAL_EN_Msk
+#define ANA_ADCSTATE_RESET_Pos (4UL) /*!< ANA ADCSTATE: RESET (Bit 4) */
+#define ANA_ADCSTATE_RESET_Msk (0x10UL) /*!< ANA ADCSTATE: RESET (Bitfield-Mask: 0x01) */
+#define ANA_ADCSTATE_RESET ANA_ADCSTATE_RESET_Msk
+#define ANA_ADCSTATE_ADC_EN_Pos (3UL) /*!< ANA ADCSTATE: ADC_EN (Bit 3) */
+#define ANA_ADCSTATE_ADC_EN_Msk (0x8UL) /*!< ANA ADCSTATE: ADC_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCSTATE_ADC_EN ANA_ADCSTATE_ADC_EN_Msk
+#define ANA_ADCSTATE_ADCSTATE_Pos (0UL) /*!< ANA ADCSTATE: ADCSTATE (Bit 0) */
+#define ANA_ADCSTATE_ADCSTATE_Msk (0x7UL) /*!< ANA ADCSTATE: ADCSTATE (Bitfield-Mask: 0x07) */
+#define ANA_ADCSTATE_ADCSTATE ANA_ADCSTATE_ADCSTATE_Msk
+/* ======================================================== INTSTS ========================================================= */
+#define ANA_INTSTS_INTSTS21_Pos (21UL) /*!< ANA INTSTS: INTSTS21 (Bit 21) */
+#define ANA_INTSTS_INTSTS21_Msk (0x200000UL) /*!< ANA INTSTS: INTSTS21 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS21 ANA_INTSTS_INTSTS21_Msk
+#define ANA_INTSTS_INTSTS20_Pos (20UL) /*!< ANA INTSTS: INTSTS20 (Bit 20) */
+#define ANA_INTSTS_INTSTS20_Msk (0x100000UL) /*!< ANA INTSTS: INTSTS20 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS20 ANA_INTSTS_INTSTS20_Msk
+#define ANA_INTSTS_INTSTS19_Pos (19UL) /*!< ANA INTSTS: INTSTS19 (Bit 19) */
+#define ANA_INTSTS_INTSTS19_Msk (0x80000UL) /*!< ANA INTSTS: INTSTS19 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS19 ANA_INTSTS_INTSTS19_Msk
+#define ANA_INTSTS_INTSTS18_Pos (18UL) /*!< ANA INTSTS: INTSTS18 (Bit 18) */
+#define ANA_INTSTS_INTSTS18_Msk (0x40000UL) /*!< ANA INTSTS: INTSTS18 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS18 ANA_INTSTS_INTSTS18_Msk
+#define ANA_INTSTS_INTSTS17_Pos (17UL) /*!< ANA INTSTS: INTSTS17 (Bit 17) */
+#define ANA_INTSTS_INTSTS17_Msk (0x20000UL) /*!< ANA INTSTS: INTSTS17 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS17 ANA_INTSTS_INTSTS17_Msk
+#define ANA_INTSTS_INTSTS16_Pos (16UL) /*!< ANA INTSTS: INTSTS16 (Bit 16) */
+#define ANA_INTSTS_INTSTS16_Msk (0x10000UL) /*!< ANA INTSTS: INTSTS16 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS16 ANA_INTSTS_INTSTS16_Msk
+#define ANA_INTSTS_INTSTS15_Pos (15UL) /*!< ANA INTSTS: INTSTS15 (Bit 15) */
+#define ANA_INTSTS_INTSTS15_Msk (0x8000UL) /*!< ANA INTSTS: INTSTS15 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS15 ANA_INTSTS_INTSTS15_Msk
+#define ANA_INTSTS_INTSTS14_Pos (14UL) /*!< ANA INTSTS: INTSTS14 (Bit 14) */
+#define ANA_INTSTS_INTSTS14_Msk (0x4000UL) /*!< ANA INTSTS: INTSTS14 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS14 ANA_INTSTS_INTSTS14_Msk
+#define ANA_INTSTS_INTSTS13_Pos (13UL) /*!< ANA INTSTS: INTSTS13 (Bit 13) */
+#define ANA_INTSTS_INTSTS13_Msk (0x2000UL) /*!< ANA INTSTS: INTSTS13 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS13 ANA_INTSTS_INTSTS13_Msk
+#define ANA_INTSTS_INTSTS12_Pos (12UL) /*!< ANA INTSTS: INTSTS12 (Bit 12) */
+#define ANA_INTSTS_INTSTS12_Msk (0x1000UL) /*!< ANA INTSTS: INTSTS12 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS12 ANA_INTSTS_INTSTS12_Msk
+#define ANA_INTSTS_INTSTS11_Pos (11UL) /*!< ANA INTSTS: INTSTS11 (Bit 11) */
+#define ANA_INTSTS_INTSTS11_Msk (0x800UL) /*!< ANA INTSTS: INTSTS11 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS11 ANA_INTSTS_INTSTS11_Msk
+#define ANA_INTSTS_INTSTS10_Pos (10UL) /*!< ANA INTSTS: INTSTS10 (Bit 10) */
+#define ANA_INTSTS_INTSTS10_Msk (0x400UL) /*!< ANA INTSTS: INTSTS10 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS10 ANA_INTSTS_INTSTS10_Msk
+#define ANA_INTSTS_INTSTS8_Pos (8UL) /*!< ANA INTSTS: INTSTS8 (Bit 8) */
+#define ANA_INTSTS_INTSTS8_Msk (0x100UL) /*!< ANA INTSTS: INTSTS8 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS8 ANA_INTSTS_INTSTS8_Msk
+#define ANA_INTSTS_INTSTS7_Pos (7UL) /*!< ANA INTSTS: INTSTS7 (Bit 7) */
+#define ANA_INTSTS_INTSTS7_Msk (0x80UL) /*!< ANA INTSTS: INTSTS7 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS7 ANA_INTSTS_INTSTS7_Msk
+#define ANA_INTSTS_INTSTS3_Pos (3UL) /*!< ANA INTSTS: INTSTS3 (Bit 3) */
+#define ANA_INTSTS_INTSTS3_Msk (0x8UL) /*!< ANA INTSTS: INTSTS3 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS3 ANA_INTSTS_INTSTS3_Msk
+#define ANA_INTSTS_INTSTS2_Pos (2UL) /*!< ANA INTSTS: INTSTS2 (Bit 2) */
+#define ANA_INTSTS_INTSTS2_Msk (0x4UL) /*!< ANA INTSTS: INTSTS2 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS2 ANA_INTSTS_INTSTS2_Msk
+#define ANA_INTSTS_INTSTS1_Pos (1UL) /*!< ANA INTSTS: INTSTS1 (Bit 1) */
+#define ANA_INTSTS_INTSTS1_Msk (0x2UL) /*!< ANA INTSTS: INTSTS1 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS1 ANA_INTSTS_INTSTS1_Msk
+#define ANA_INTSTS_INTSTS0_Pos (0UL) /*!< ANA INTSTS: INTSTS0 (Bit 0) */
+#define ANA_INTSTS_INTSTS0_Msk (0x1UL) /*!< ANA INTSTS: INTSTS0 (Bitfield-Mask: 0x01) */
+#define ANA_INTSTS_INTSTS0 ANA_INTSTS_INTSTS0_Msk
+/* ========================================================= INTEN ========================================================= */
+#define ANA_INTEN_INTEN21_Pos (21UL) /*!< ANA INTEN: INTEN21 (Bit 21) */
+#define ANA_INTEN_INTEN21_Msk (0x200000UL) /*!< ANA INTEN: INTEN21 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN21 ANA_INTEN_INTEN21_Msk
+#define ANA_INTEN_INTEN20_Pos (20UL) /*!< ANA INTEN: INTEN20 (Bit 20) */
+#define ANA_INTEN_INTEN20_Msk (0x100000UL) /*!< ANA INTEN: INTEN20 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN20 ANA_INTEN_INTEN20_Msk
+#define ANA_INTEN_INTEN19_Pos (19UL) /*!< ANA INTEN: INTEN19 (Bit 19) */
+#define ANA_INTEN_INTEN19_Msk (0x80000UL) /*!< ANA INTEN: INTEN19 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN19 ANA_INTEN_INTEN19_Msk
+#define ANA_INTEN_INTEN18_Pos (18UL) /*!< ANA INTEN: INTEN18 (Bit 18) */
+#define ANA_INTEN_INTEN18_Msk (0x40000UL) /*!< ANA INTEN: INTEN18 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN18 ANA_INTEN_INTEN18_Msk
+#define ANA_INTEN_INTEN17_Pos (17UL) /*!< ANA INTEN: INTEN17 (Bit 17) */
+#define ANA_INTEN_INTEN17_Msk (0x20000UL) /*!< ANA INTEN: INTEN17 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN17 ANA_INTEN_INTEN17_Msk
+#define ANA_INTEN_INTEN16_Pos (16UL) /*!< ANA INTEN: INTEN16 (Bit 16) */
+#define ANA_INTEN_INTEN16_Msk (0x10000UL) /*!< ANA INTEN: INTEN16 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN16 ANA_INTEN_INTEN16_Msk
+#define ANA_INTEN_INTEN15_Pos (15UL) /*!< ANA INTEN: INTEN15 (Bit 15) */
+#define ANA_INTEN_INTEN15_Msk (0x8000UL) /*!< ANA INTEN: INTEN15 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN15 ANA_INTEN_INTEN15_Msk
+#define ANA_INTEN_INTEN14_Pos (14UL) /*!< ANA INTEN: INTEN14 (Bit 14) */
+#define ANA_INTEN_INTEN14_Msk (0x4000UL) /*!< ANA INTEN: INTEN14 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN14 ANA_INTEN_INTEN14_Msk
+#define ANA_INTEN_INTEN13_Pos (13UL) /*!< ANA INTEN: INTEN13 (Bit 13) */
+#define ANA_INTEN_INTEN13_Msk (0x2000UL) /*!< ANA INTEN: INTEN13 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN13 ANA_INTEN_INTEN13_Msk
+#define ANA_INTEN_INTEN12_Pos (12UL) /*!< ANA INTEN: INTEN12 (Bit 12) */
+#define ANA_INTEN_INTEN12_Msk (0x1000UL) /*!< ANA INTEN: INTEN12 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN12 ANA_INTEN_INTEN12_Msk
+#define ANA_INTEN_INTEN11_Pos (11UL) /*!< ANA INTEN: INTEN11 (Bit 11) */
+#define ANA_INTEN_INTEN11_Msk (0x800UL) /*!< ANA INTEN: INTEN11 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN11 ANA_INTEN_INTEN11_Msk
+#define ANA_INTEN_INTEN10_Pos (10UL) /*!< ANA INTEN: INTEN10 (Bit 10) */
+#define ANA_INTEN_INTEN10_Msk (0x400UL) /*!< ANA INTEN: INTEN10 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN10 ANA_INTEN_INTEN10_Msk
+#define ANA_INTEN_INTEN8_Pos (8UL) /*!< ANA INTEN: INTEN8 (Bit 8) */
+#define ANA_INTEN_INTEN8_Msk (0x100UL) /*!< ANA INTEN: INTEN8 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN8 ANA_INTEN_INTEN8_Msk
+#define ANA_INTEN_INTEN7_Pos (7UL) /*!< ANA INTEN: INTEN7 (Bit 7) */
+#define ANA_INTEN_INTEN7_Msk (0x80UL) /*!< ANA INTEN: INTEN7 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN7 ANA_INTEN_INTEN7_Msk
+#define ANA_INTEN_INTEN3_Pos (3UL) /*!< ANA INTEN: INTEN3 (Bit 3) */
+#define ANA_INTEN_INTEN3_Msk (0x8UL) /*!< ANA INTEN: INTEN3 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN3 ANA_INTEN_INTEN3_Msk
+#define ANA_INTEN_INTEN2_Pos (2UL) /*!< ANA INTEN: INTEN2 (Bit 2) */
+#define ANA_INTEN_INTEN2_Msk (0x4UL) /*!< ANA INTEN: INTEN2 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN2 ANA_INTEN_INTEN2_Msk
+#define ANA_INTEN_INTEN1_Pos (1UL) /*!< ANA INTEN: INTEN1 (Bit 1) */
+#define ANA_INTEN_INTEN1_Msk (0x2UL) /*!< ANA INTEN: INTEN1 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN1 ANA_INTEN_INTEN1_Msk
+#define ANA_INTEN_INTEN0_Pos (0UL) /*!< ANA INTEN: INTEN0 (Bit 0) */
+#define ANA_INTEN_INTEN0_Msk (0x1UL) /*!< ANA INTEN: INTEN0 (Bitfield-Mask: 0x01) */
+#define ANA_INTEN_INTEN0 ANA_INTEN_INTEN0_Msk
+/* ======================================================= ADCCTRL0 ======================================================== */
+#define ANA_ADCCTRL0_MTRIG_Pos (31UL) /*!< ANA ADCCTRL0: MTRIG (Bit 31) */
+#define ANA_ADCCTRL0_MTRIG_Msk (0x80000000UL) /*!< ANA ADCCTRL0: MTRIG (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL0_MTRIG ANA_ADCCTRL0_MTRIG_Msk
+#define ANA_ADCCTRL0_STOP_Pos (19UL) /*!< ANA ADCCTRL0: STOP (Bit 19) */
+#define ANA_ADCCTRL0_STOP_Msk (0x80000UL) /*!< ANA ADCCTRL0: STOP (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL0_STOP ANA_ADCCTRL0_STOP_Msk
+#define ANA_ADCCTRL0_AEN_Pos (16UL) /*!< ANA ADCCTRL0: AEN (Bit 16) */
+#define ANA_ADCCTRL0_AEN_Msk (0x70000UL) /*!< ANA ADCCTRL0: AEN (Bitfield-Mask: 0x07) */
+#define ANA_ADCCTRL0_AEN ANA_ADCCTRL0_AEN_Msk
+#define ANA_ADCCTRL0_CLKSRCSEL_Pos (12UL) /*!< ANA ADCCTRL0: CLKSRCSEL (Bit 12) */
+#define ANA_ADCCTRL0_CLKSRCSEL_Msk (0x1000UL) /*!< ANA ADCCTRL0: CLKSRCSEL (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL0_CLKSRCSEL ANA_ADCCTRL0_CLKSRCSEL_Msk
+/* ======================================================== CMPCTL ========================================================= */
+#define ANA_CMPCTL_PWR_DEB_SEL_Pos (24UL) /*!< ANA CMPCTL: PWR_DEB_SEL (Bit 24) */
+#define ANA_CMPCTL_PWR_DEB_SEL_Msk (0xff000000UL) /*!< ANA CMPCTL: PWR_DEB_SEL (Bitfield-Mask: 0xff) */
+#define ANA_CMPCTL_PWR_DEB_SEL ANA_CMPCTL_PWR_DEB_SEL_Msk
+#define ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Pos (22UL) /*!< ANA CMPCTL: VDDALARM_CHK_FRQ_SEL (Bit 22) */
+#define ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Msk (0xc00000UL) /*!< ANA CMPCTL: VDDALARM_CHK_FRQ_SEL (Bitfield-Mask: 0x03) */
+#define ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Msk
+#define ANA_CMPCTL_CMP2_IO_NODEB_Pos (21UL) /*!< ANA CMPCTL: CMP2_IO_NODEB (Bit 21) */
+#define ANA_CMPCTL_CMP2_IO_NODEB_Msk (0x200000UL) /*!< ANA CMPCTL: CMP2_IO_NODEB (Bitfield-Mask: 0x01) */
+#define ANA_CMPCTL_CMP2_IO_NODEB ANA_CMPCTL_CMP2_IO_NODEB_Msk
+#define ANA_CMPCTL_CMP2_INT_MASK_EN_Pos (20UL) /*!< ANA CMPCTL: CMP2_INT_MASK_EN (Bit 20) */
+#define ANA_CMPCTL_CMP2_INT_MASK_EN_Msk (0x100000UL) /*!< ANA CMPCTL: CMP2_INT_MASK_EN (Bitfield-Mask: 0x01) */
+#define ANA_CMPCTL_CMP2_INT_MASK_EN ANA_CMPCTL_CMP2_INT_MASK_EN_Msk
+#define ANA_CMPCTL_CMP1_IO_NODEB_Pos (17UL) /*!< ANA CMPCTL: CMP1_IO_NODEB (Bit 17) */
+#define ANA_CMPCTL_CMP1_IO_NODEB_Msk (0x20000UL) /*!< ANA CMPCTL: CMP1_IO_NODEB (Bitfield-Mask: 0x01) */
+#define ANA_CMPCTL_CMP1_IO_NODEB ANA_CMPCTL_CMP1_IO_NODEB_Msk
+#define ANA_CMPCTL_CMP1_INT_MASK_EN_Pos (16UL) /*!< ANA CMPCTL: CMP1_INT_MASK_EN (Bit 16) */
+#define ANA_CMPCTL_CMP1_INT_MASK_EN_Msk (0x10000UL) /*!< ANA CMPCTL: CMP1_INT_MASK_EN (Bitfield-Mask: 0x01) */
+#define ANA_CMPCTL_CMP1_INT_MASK_EN ANA_CMPCTL_CMP1_INT_MASK_EN_Msk
+#define ANA_CMPCTL_CMP2_CHK_NUM_Pos (12UL) /*!< ANA CMPCTL: CMP2_CHK_NUM (Bit 12) */
+#define ANA_CMPCTL_CMP2_CHK_NUM_Msk (0xf000UL) /*!< ANA CMPCTL: CMP2_CHK_NUM (Bitfield-Mask: 0x0f) */
+#define ANA_CMPCTL_CMP2_CHK_NUM ANA_CMPCTL_CMP2_CHK_NUM_Msk
+#define ANA_CMPCTL_CMP2_THR_EN_Pos (11UL) /*!< ANA CMPCTL: CMP2_THR_EN (Bit 11) */
+#define ANA_CMPCTL_CMP2_THR_EN_Msk (0x800UL) /*!< ANA CMPCTL: CMP2_THR_EN (Bitfield-Mask: 0x01) */
+#define ANA_CMPCTL_CMP2_THR_EN ANA_CMPCTL_CMP2_THR_EN_Msk
+#define ANA_CMPCTL_CMP2_CHK_FRQ_Pos (8UL) /*!< ANA CMPCTL: CMP2_CHK_FRQ (Bit 8) */
+#define ANA_CMPCTL_CMP2_CHK_FRQ_Msk (0x700UL) /*!< ANA CMPCTL: CMP2_CHK_FRQ (Bitfield-Mask: 0x07) */
+#define ANA_CMPCTL_CMP2_CHK_FRQ ANA_CMPCTL_CMP2_CHK_FRQ_Msk
+#define ANA_CMPCTL_CMP1_CHK_NUM_Pos (4UL) /*!< ANA CMPCTL: CMP1_CHK_NUM (Bit 4) */
+#define ANA_CMPCTL_CMP1_CHK_NUM_Msk (0xf0UL) /*!< ANA CMPCTL: CMP1_CHK_NUM (Bitfield-Mask: 0x0f) */
+#define ANA_CMPCTL_CMP1_CHK_NUM ANA_CMPCTL_CMP1_CHK_NUM_Msk
+#define ANA_CMPCTL_CMP1_THR_EN_Pos (3UL) /*!< ANA CMPCTL: CMP1_THR_EN (Bit 3) */
+#define ANA_CMPCTL_CMP1_THR_EN_Msk (0x8UL) /*!< ANA CMPCTL: CMP1_THR_EN (Bitfield-Mask: 0x01) */
+#define ANA_CMPCTL_CMP1_THR_EN ANA_CMPCTL_CMP1_THR_EN_Msk
+#define ANA_CMPCTL_CMP1_CHK_FRQ_Pos (0UL) /*!< ANA CMPCTL: CMP1_CHK_FRQ (Bit 0) */
+#define ANA_CMPCTL_CMP1_CHK_FRQ_Msk (0x7UL) /*!< ANA CMPCTL: CMP1_CHK_FRQ (Bitfield-Mask: 0x07) */
+#define ANA_CMPCTL_CMP1_CHK_FRQ ANA_CMPCTL_CMP1_CHK_FRQ_Msk
+/* ======================================================== ADCDATA ======================================================== */
+#define ANA_ADCDATA_ADCDATA_Pos (0UL) /*!< ANA ADCDATA: ADCDATA (Bit 0) */
+#define ANA_ADCDATA_ADCDATA_Msk (0xffffUL) /*!< ANA ADCDATA: ADCDATA (Bitfield-Mask: 0xffff) */
+#define ANA_ADCDATA_ADCDATA ANA_ADCDATA_ADCDATA_Msk
+/* ======================================================== CMPCNT ========================================================= */
+#define ANA_CMPCNT_CNT_Pos (0UL) /*!< ANA CMPCNT: CNT (Bit 0) */
+#define ANA_CMPCNT_CNT_Msk (0xffffffffUL) /*!< ANA CMPCNT: CNT (Bitfield-Mask: 0xffffffff) */
+#define ANA_CMPCNT_CNT ANA_CMPCNT_CNT_Msk
+/* ========================================================= MISC ========================================================== */
+#define ANA_MISC_TADCTH_Pos (4UL) /*!< ANA MISC: TADCTH (Bit 4) */
+#define ANA_MISC_TADCTH_Msk (0x30UL) /*!< ANA MISC: TADCTH (Bitfield-Mask: 0x03) */
+#define ANA_MISC_TADCTH ANA_MISC_TADCTH_Msk
+/* ======================================================== ADCDOS ========================================================= */
+#define ANA_ADCDOS_DOS_Pos (0UL) /*!< ANA ADCDOS: DOS (Bit 0) */
+#define ANA_ADCDOS_DOS_Msk (0xffUL) /*!< ANA ADCDOS: DOS (Bitfield-Mask: 0xff) */
+#define ANA_ADCDOS_DOS ANA_ADCDOS_DOS_Msk
+/* ====================================================== ADCDATADMA ======================================================= */
+#define ANA_ADCDATADMA_ADCDATA_DMA_Pos (0UL) /*!< ANA ADCDATADMA: ADCDATA_DMA (Bit 0) */
+#define ANA_ADCDATADMA_ADCDATA_DMA_Msk (0xffffUL) /*!< ANA ADCDATADMA: ADCDATA_DMA (Bitfield-Mask: 0xffff) */
+#define ANA_ADCDATADMA_ADCDATA_DMA ANA_ADCDATADMA_ADCDATA_DMA_Msk
+/* ======================================================== CMPTHR ========================================================= */
+#define ANA_CMPTHR_CMP2_THR_Pos (16UL) /*!< ANA CMPTHR: CMP2_THR (Bit 16) */
+#define ANA_CMPTHR_CMP2_THR_Msk (0xffff0000UL) /*!< ANA CMPTHR: CMP2_THR (Bitfield-Mask: 0xffff) */
+#define ANA_CMPTHR_CMP2_THR ANA_CMPTHR_CMP2_THR_Msk
+#define ANA_CMPTHR_CMP1_THR_Pos (0UL) /*!< ANA CMPTHR: CMP1_THR (Bit 0) */
+#define ANA_CMPTHR_CMP1_THR_Msk (0xffffUL) /*!< ANA CMPTHR: CMP1_THR (Bitfield-Mask: 0xffff) */
+#define ANA_CMPTHR_CMP1_THR ANA_CMPTHR_CMP1_THR_Msk
+/* ======================================================= ADCCTRL1 ======================================================== */
+#define ANA_ADCCTRL1_RESDIV_CHx_Pos (16UL) /*!< ANA ADCCTRL1: RESDIV_CHx (Bit 16) */
+#define ANA_ADCCTRL1_RESDIV_CHx_Msk (0xffff0000UL) /*!< ANA ADCCTRL1: RESDIV_CHx (Bitfield-Mask: 0xffff) */
+#define ANA_ADCCTRL1_RESDIV_CHx ANA_ADCCTRL1_RESDIV_CHx_Msk
+#define ANA_ADCCTRL1_UPPER_THD3_EN_Pos (15UL) /*!< ANA ADCCTRL1: UPPER_THD3_EN (Bit 15) */
+#define ANA_ADCCTRL1_UPPER_THD3_EN_Msk (0x8000UL) /*!< ANA ADCCTRL1: UPPER_THD3_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL1_UPPER_THD3_EN ANA_ADCCTRL1_UPPER_THD3_EN_Msk
+#define ANA_ADCCTRL1_LOWER_THD3_EN_Pos (14UL) /*!< ANA ADCCTRL1: LOWER_THD3_EN (Bit 14) */
+#define ANA_ADCCTRL1_LOWER_THD3_EN_Msk (0x4000UL) /*!< ANA ADCCTRL1: LOWER_THD3_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL1_LOWER_THD3_EN ANA_ADCCTRL1_LOWER_THD3_EN_Msk
+#define ANA_ADCCTRL1_UPPER_THD2_EN_Pos (13UL) /*!< ANA ADCCTRL1: UPPER_THD2_EN (Bit 13) */
+#define ANA_ADCCTRL1_UPPER_THD2_EN_Msk (0x2000UL) /*!< ANA ADCCTRL1: UPPER_THD2_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL1_UPPER_THD2_EN ANA_ADCCTRL1_UPPER_THD2_EN_Msk
+#define ANA_ADCCTRL1_LOWER_THD2_EN_Pos (12UL) /*!< ANA ADCCTRL1: LOWER_THD2_EN (Bit 12) */
+#define ANA_ADCCTRL1_LOWER_THD2_EN_Msk (0x1000UL) /*!< ANA ADCCTRL1: LOWER_THD2_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL1_LOWER_THD2_EN ANA_ADCCTRL1_LOWER_THD2_EN_Msk
+#define ANA_ADCCTRL1_UPPER_THD1_EN_Pos (11UL) /*!< ANA ADCCTRL1: UPPER_THD1_EN (Bit 11) */
+#define ANA_ADCCTRL1_UPPER_THD1_EN_Msk (0x800UL) /*!< ANA ADCCTRL1: UPPER_THD1_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL1_UPPER_THD1_EN ANA_ADCCTRL1_UPPER_THD1_EN_Msk
+#define ANA_ADCCTRL1_LOWER_THD1_EN_Pos (10UL) /*!< ANA ADCCTRL1: LOWER_THD1_EN (Bit 10) */
+#define ANA_ADCCTRL1_LOWER_THD1_EN_Msk (0x400UL) /*!< ANA ADCCTRL1: LOWER_THD1_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL1_LOWER_THD1_EN ANA_ADCCTRL1_LOWER_THD1_EN_Msk
+#define ANA_ADCCTRL1_UPPER_THD0_EN_Pos (9UL) /*!< ANA ADCCTRL1: UPPER_THD0_EN (Bit 9) */
+#define ANA_ADCCTRL1_UPPER_THD0_EN_Msk (0x200UL) /*!< ANA ADCCTRL1: UPPER_THD0_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL1_UPPER_THD0_EN ANA_ADCCTRL1_UPPER_THD0_EN_Msk
+#define ANA_ADCCTRL1_LOWER_THD0_EN_Pos (8UL) /*!< ANA ADCCTRL1: LOWER_THD0_EN (Bit 8) */
+#define ANA_ADCCTRL1_LOWER_THD0_EN_Msk (0x100UL) /*!< ANA ADCCTRL1: LOWER_THD0_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL1_LOWER_THD0_EN ANA_ADCCTRL1_LOWER_THD0_EN_Msk
+/* ======================================================= ADCCTRL2 ======================================================== */
+#define ANA_ADCCTRL2_SCAN_CHx_Pos (16UL) /*!< ANA ADCCTRL2: SCAN_CHx (Bit 16) */
+#define ANA_ADCCTRL2_SCAN_CHx_Msk (0xffff0000UL) /*!< ANA ADCCTRL2: SCAN_CHx (Bitfield-Mask: 0xffff) */
+#define ANA_ADCCTRL2_SCAN_CHx ANA_ADCCTRL2_SCAN_CHx_Msk
+#define ANA_ADCCTRL2_CONV_ERR_Pos (11UL) /*!< ANA ADCCTRL2: CONV_ERR (Bit 11) */
+#define ANA_ADCCTRL2_CONV_ERR_Msk (0x800UL) /*!< ANA ADCCTRL2: CONV_ERR (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL2_CONV_ERR ANA_ADCCTRL2_CONV_ERR_Msk
+#define ANA_ADCCTRL2_CAL_ERR_Pos (10UL) /*!< ANA ADCCTRL2: CAL_ERR (Bit 10) */
+#define ANA_ADCCTRL2_CAL_ERR_Msk (0x400UL) /*!< ANA ADCCTRL2: CAL_ERR (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL2_CAL_ERR ANA_ADCCTRL2_CAL_ERR_Msk
+#define ANA_ADCCTRL2_CONV_ERR_CLR_Pos (9UL) /*!< ANA ADCCTRL2: CONV_ERR_CLR (Bit 9) */
+#define ANA_ADCCTRL2_CONV_ERR_CLR_Msk (0x200UL) /*!< ANA ADCCTRL2: CONV_ERR_CLR (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL2_CONV_ERR_CLR ANA_ADCCTRL2_CONV_ERR_CLR_Msk
+#define ANA_ADCCTRL2_CAL_ERR_CLR_Pos (8UL) /*!< ANA ADCCTRL2: CAL_ERR_CLR (Bit 8) */
+#define ANA_ADCCTRL2_CAL_ERR_CLR_Msk (0x100UL) /*!< ANA ADCCTRL2: CAL_ERR_CLR (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL2_CAL_ERR_CLR ANA_ADCCTRL2_CAL_ERR_CLR_Msk
+#define ANA_ADCCTRL2_RTC_CAL_DONE_Pos (7UL) /*!< ANA ADCCTRL2: RTC_CAL_DONE (Bit 7) */
+#define ANA_ADCCTRL2_RTC_CAL_DONE_Msk (0x80UL) /*!< ANA ADCCTRL2: RTC_CAL_DONE (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL2_RTC_CAL_DONE ANA_ADCCTRL2_RTC_CAL_DONE_Msk
+#define ANA_ADCCTRL2_ADC_EN_TRG_CAL_Pos (6UL) /*!< ANA ADCCTRL2: ADC_EN_TRG_CAL (Bit 6) */
+#define ANA_ADCCTRL2_ADC_EN_TRG_CAL_Msk (0x40UL) /*!< ANA ADCCTRL2: ADC_EN_TRG_CAL (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL2_ADC_EN_TRG_CAL ANA_ADCCTRL2_ADC_EN_TRG_CAL_Msk
+#define ANA_ADCCTRL2_BUSY_Pos (5UL) /*!< ANA ADCCTRL2: BUSY (Bit 5) */
+#define ANA_ADCCTRL2_BUSY_Msk (0x20UL) /*!< ANA ADCCTRL2: BUSY (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL2_BUSY ANA_ADCCTRL2_BUSY_Msk
+#define ANA_ADCCTRL2_ADCCR_Pos (3UL) /*!< ANA ADCCTRL2: ADCCR (Bit 3) */
+#define ANA_ADCCTRL2_ADCCR_Msk (0x8UL) /*!< ANA ADCCTRL2: ADCCR (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL2_ADCCR ANA_ADCCTRL2_ADCCR_Msk
+#define ANA_ADCCTRL2_RESET_Pos (1UL) /*!< ANA ADCCTRL2: RESET (Bit 1) */
+#define ANA_ADCCTRL2_RESET_Msk (0x2UL) /*!< ANA ADCCTRL2: RESET (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL2_RESET ANA_ADCCTRL2_RESET_Msk
+#define ANA_ADCCTRL2_ADC_EN_Pos (0UL) /*!< ANA ADCCTRL2: ADC_EN (Bit 0) */
+#define ANA_ADCCTRL2_ADC_EN_Msk (0x1UL) /*!< ANA ADCCTRL2: ADC_EN (Bitfield-Mask: 0x01) */
+#define ANA_ADCCTRL2_ADC_EN ANA_ADCCTRL2_ADC_EN_Msk
+/* ===================================================== ADCDATATHD1_0 ===================================================== */
+#define ANA_ADCDATATHD1_0_UPPER_THD1_Pos (24UL) /*!< ANA ADCDATATHD1_0: UPPER_THD1 (Bit 24) */
+#define ANA_ADCDATATHD1_0_UPPER_THD1_Msk (0xff000000UL) /*!< ANA ADCDATATHD1_0: UPPER_THD1 (Bitfield-Mask: 0xff) */
+#define ANA_ADCDATATHD1_0_UPPER_THD1 ANA_ADCDATATHD1_0_UPPER_THD1_Msk
+#define ANA_ADCDATATHD1_0_LOWER_THD1_Pos (16UL) /*!< ANA ADCDATATHD1_0: LOWER_THD1 (Bit 16) */
+#define ANA_ADCDATATHD1_0_LOWER_THD1_Msk (0xff0000UL) /*!< ANA ADCDATATHD1_0: LOWER_THD1 (Bitfield-Mask: 0xff) */
+#define ANA_ADCDATATHD1_0_LOWER_THD1 ANA_ADCDATATHD1_0_LOWER_THD1_Msk
+#define ANA_ADCDATATHD1_0_UPPER_THD0_Pos (8UL) /*!< ANA ADCDATATHD1_0: UPPER_THD0 (Bit 8) */
+#define ANA_ADCDATATHD1_0_UPPER_THD0_Msk (0xff00UL) /*!< ANA ADCDATATHD1_0: UPPER_THD0 (Bitfield-Mask: 0xff) */
+#define ANA_ADCDATATHD1_0_UPPER_THD0 ANA_ADCDATATHD1_0_UPPER_THD0_Msk
+#define ANA_ADCDATATHD1_0_LOWER_THD0_Pos (0UL) /*!< ANA ADCDATATHD1_0: LOWER_THD0 (Bit 0) */
+#define ANA_ADCDATATHD1_0_LOWER_THD0_Msk (0xffUL) /*!< ANA ADCDATATHD1_0: LOWER_THD0 (Bitfield-Mask: 0xff) */
+#define ANA_ADCDATATHD1_0_LOWER_THD0 ANA_ADCDATATHD1_0_LOWER_THD0_Msk
+/* ===================================================== ADCDATATHD3_2 ===================================================== */
+#define ANA_ADCDATATHD3_2_UPPER_THD3_Pos (24UL) /*!< ANA ADCDATATHD3_2: UPPER_THD3 (Bit 24) */
+#define ANA_ADCDATATHD3_2_UPPER_THD3_Msk (0xff000000UL) /*!< ANA ADCDATATHD3_2: UPPER_THD3 (Bitfield-Mask: 0xff) */
+#define ANA_ADCDATATHD3_2_UPPER_THD3 ANA_ADCDATATHD3_2_UPPER_THD3_Msk
+#define ANA_ADCDATATHD3_2_LOWER_THD3_Pos (16UL) /*!< ANA ADCDATATHD3_2: LOWER_THD3 (Bit 16) */
+#define ANA_ADCDATATHD3_2_LOWER_THD3_Msk (0xff0000UL) /*!< ANA ADCDATATHD3_2: LOWER_THD3 (Bitfield-Mask: 0xff) */
+#define ANA_ADCDATATHD3_2_LOWER_THD3 ANA_ADCDATATHD3_2_LOWER_THD3_Msk
+#define ANA_ADCDATATHD3_2_UPPER_THD2_Pos (8UL) /*!< ANA ADCDATATHD3_2: UPPER_THD2 (Bit 8) */
+#define ANA_ADCDATATHD3_2_UPPER_THD2_Msk (0xff00UL) /*!< ANA ADCDATATHD3_2: UPPER_THD2 (Bitfield-Mask: 0xff) */
+#define ANA_ADCDATATHD3_2_UPPER_THD2 ANA_ADCDATATHD3_2_UPPER_THD2_Msk
+#define ANA_ADCDATATHD3_2_LOWER_THD2_Pos (0UL) /*!< ANA ADCDATATHD3_2: LOWER_THD2 (Bit 0) */
+#define ANA_ADCDATATHD3_2_LOWER_THD2_Msk (0xffUL) /*!< ANA ADCDATATHD3_2: LOWER_THD2 (Bitfield-Mask: 0xff) */
+#define ANA_ADCDATATHD3_2_LOWER_THD2 ANA_ADCDATATHD3_2_LOWER_THD2_Msk
+/* ===================================================== ADCDATATHD_CH ===================================================== */
+#define ANA_ADCDATATHD_CH_UPPER_THD3_TRGED_Pos (31UL) /*!< ANA ADCDATATHD_CH: UPPER_THD3_TRGED (Bit 31) */
+#define ANA_ADCDATATHD_CH_UPPER_THD3_TRGED_Msk (0x80000000UL) /*!< ANA ADCDATATHD_CH: UPPER_THD3_TRGED (Bitfield-Mask: 0x01) */
+#define ANA_ADCDATATHD_CH_UPPER_THD3_TRGED ANA_ADCDATATHD_CH_UPPER_THD3_TRGED_Msk
+#define ANA_ADCDATATHD_CH_LOWER_THD3_TRGED_Pos (30UL) /*!< ANA ADCDATATHD_CH: LOWER_THD3_TRGED (Bit 30) */
+#define ANA_ADCDATATHD_CH_LOWER_THD3_TRGED_Msk (0x40000000UL) /*!< ANA ADCDATATHD_CH: LOWER_THD3_TRGED (Bitfield-Mask: 0x01) */
+#define ANA_ADCDATATHD_CH_LOWER_THD3_TRGED ANA_ADCDATATHD_CH_LOWER_THD3_TRGED_Msk
+#define ANA_ADCDATATHD_CH_UPPER_THD2_TRGED_Pos (29UL) /*!< ANA ADCDATATHD_CH: UPPER_THD2_TRGED (Bit 29) */
+#define ANA_ADCDATATHD_CH_UPPER_THD2_TRGED_Msk (0x20000000UL) /*!< ANA ADCDATATHD_CH: UPPER_THD2_TRGED (Bitfield-Mask: 0x01) */
+#define ANA_ADCDATATHD_CH_UPPER_THD2_TRGED ANA_ADCDATATHD_CH_UPPER_THD2_TRGED_Msk
+#define ANA_ADCDATATHD_CH_LOWER_THD2_TRGED_Pos (28UL) /*!< ANA ADCDATATHD_CH: LOWER_THD2_TRGED (Bit 28) */
+#define ANA_ADCDATATHD_CH_LOWER_THD2_TRGED_Msk (0x10000000UL) /*!< ANA ADCDATATHD_CH: LOWER_THD2_TRGED (Bitfield-Mask: 0x01) */
+#define ANA_ADCDATATHD_CH_LOWER_THD2_TRGED ANA_ADCDATATHD_CH_LOWER_THD2_TRGED_Msk
+#define ANA_ADCDATATHD_CH_UPPER_THD1_TRGED_Pos (27UL) /*!< ANA ADCDATATHD_CH: UPPER_THD1_TRGED (Bit 27) */
+#define ANA_ADCDATATHD_CH_UPPER_THD1_TRGED_Msk (0x8000000UL) /*!< ANA ADCDATATHD_CH: UPPER_THD1_TRGED (Bitfield-Mask: 0x01) */
+#define ANA_ADCDATATHD_CH_UPPER_THD1_TRGED ANA_ADCDATATHD_CH_UPPER_THD1_TRGED_Msk
+#define ANA_ADCDATATHD_CH_LOWER_THD1_TRGED_Pos (26UL) /*!< ANA ADCDATATHD_CH: LOWER_THD1_TRGED (Bit 26) */
+#define ANA_ADCDATATHD_CH_LOWER_THD1_TRGED_Msk (0x4000000UL) /*!< ANA ADCDATATHD_CH: LOWER_THD1_TRGED (Bitfield-Mask: 0x01) */
+#define ANA_ADCDATATHD_CH_LOWER_THD1_TRGED ANA_ADCDATATHD_CH_LOWER_THD1_TRGED_Msk
+#define ANA_ADCDATATHD_CH_UPPER_THD0_TRGED_Pos (25UL) /*!< ANA ADCDATATHD_CH: UPPER_THD0_TRGED (Bit 25) */
+#define ANA_ADCDATATHD_CH_UPPER_THD0_TRGED_Msk (0x2000000UL) /*!< ANA ADCDATATHD_CH: UPPER_THD0_TRGED (Bitfield-Mask: 0x01) */
+#define ANA_ADCDATATHD_CH_UPPER_THD0_TRGED ANA_ADCDATATHD_CH_UPPER_THD0_TRGED_Msk
+#define ANA_ADCDATATHD_CH_LOWER_THD0_TRGED_Pos (24UL) /*!< ANA ADCDATATHD_CH: LOWER_THD0_TRGED (Bit 24) */
+#define ANA_ADCDATATHD_CH_LOWER_THD0_TRGED_Msk (0x1000000UL) /*!< ANA ADCDATATHD_CH: LOWER_THD0_TRGED (Bitfield-Mask: 0x01) */
+#define ANA_ADCDATATHD_CH_LOWER_THD0_TRGED ANA_ADCDATATHD_CH_LOWER_THD0_TRGED_Msk
+#define ANA_ADCDATATHD_CH_THD3_SEL_Pos (22UL) /*!< ANA ADCDATATHD_CH: THD3_SEL (Bit 22) */
+#define ANA_ADCDATATHD_CH_THD3_SEL_Msk (0xc00000UL) /*!< ANA ADCDATATHD_CH: THD3_SEL (Bitfield-Mask: 0x03) */
+#define ANA_ADCDATATHD_CH_THD3_SEL ANA_ADCDATATHD_CH_THD3_SEL_Msk
+#define ANA_ADCDATATHD_CH_THD2_SEL_Pos (20UL) /*!< ANA ADCDATATHD_CH: THD2_SEL (Bit 20) */
+#define ANA_ADCDATATHD_CH_THD2_SEL_Msk (0x300000UL) /*!< ANA ADCDATATHD_CH: THD2_SEL (Bitfield-Mask: 0x03) */
+#define ANA_ADCDATATHD_CH_THD2_SEL ANA_ADCDATATHD_CH_THD2_SEL_Msk
+#define ANA_ADCDATATHD_CH_THD1_SEL_Pos (18UL) /*!< ANA ADCDATATHD_CH: THD1_SEL (Bit 18) */
+#define ANA_ADCDATATHD_CH_THD1_SEL_Msk (0xc0000UL) /*!< ANA ADCDATATHD_CH: THD1_SEL (Bitfield-Mask: 0x03) */
+#define ANA_ADCDATATHD_CH_THD1_SEL ANA_ADCDATATHD_CH_THD1_SEL_Msk
+#define ANA_ADCDATATHD_CH_THD0_SEL_Pos (16UL) /*!< ANA ADCDATATHD_CH: THD0_SEL (Bit 16) */
+#define ANA_ADCDATATHD_CH_THD0_SEL_Msk (0x30000UL) /*!< ANA ADCDATATHD_CH: THD0_SEL (Bitfield-Mask: 0x03) */
+#define ANA_ADCDATATHD_CH_THD0_SEL ANA_ADCDATATHD_CH_THD0_SEL_Msk
+#define ANA_ADCDATATHD_CH_THD3_CH_Pos (12UL) /*!< ANA ADCDATATHD_CH: THD3_CH (Bit 12) */
+#define ANA_ADCDATATHD_CH_THD3_CH_Msk (0xf000UL) /*!< ANA ADCDATATHD_CH: THD3_CH (Bitfield-Mask: 0x0f) */
+#define ANA_ADCDATATHD_CH_THD3_CH ANA_ADCDATATHD_CH_THD3_CH_Msk
+#define ANA_ADCDATATHD_CH_THD2_CH_Pos (8UL) /*!< ANA ADCDATATHD_CH: THD2_CH (Bit 8) */
+#define ANA_ADCDATATHD_CH_THD2_CH_Msk (0xf00UL) /*!< ANA ADCDATATHD_CH: THD2_CH (Bitfield-Mask: 0x0f) */
+#define ANA_ADCDATATHD_CH_THD2_CH ANA_ADCDATATHD_CH_THD2_CH_Msk
+#define ANA_ADCDATATHD_CH_THD1_CH_Pos (4UL) /*!< ANA ADCDATATHD_CH: THD1_CH (Bit 4) */
+#define ANA_ADCDATATHD_CH_THD1_CH_Msk (0xf0UL) /*!< ANA ADCDATATHD_CH: THD1_CH (Bitfield-Mask: 0x0f) */
+#define ANA_ADCDATATHD_CH_THD1_CH ANA_ADCDATATHD_CH_THD1_CH_Msk
+#define ANA_ADCDATATHD_CH_THD0_CH_Pos (0UL) /*!< ANA ADCDATATHD_CH: THD0_CH (Bit 0) */
+#define ANA_ADCDATATHD_CH_THD0_CH_Msk (0xfUL) /*!< ANA ADCDATATHD_CH: THD0_CH (Bitfield-Mask: 0x0f) */
+#define ANA_ADCDATATHD_CH_THD0_CH ANA_ADCDATATHD_CH_THD0_CH_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ CRYPT ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CTRL ========================================================== */
+#define CRYPT_CTRL_NOSTOP_Pos (15UL) /*!< CRYPT CTRL: NOSTOP (Bit 15) */
+#define CRYPT_CTRL_NOSTOP_Msk (0x8000UL) /*!< CRYPT CTRL: NOSTOP (Bitfield-Mask: 0x01) */
+#define CRYPT_CTRL_NOSTOP CRYPT_CTRL_NOSTOP_Msk
+#define CRYPT_CTRL_LENGTH_Pos (8UL) /*!< CRYPT CTRL: LENGTH (Bit 8) */
+#define CRYPT_CTRL_LENGTH_Msk (0xf00UL) /*!< CRYPT CTRL: LENGTH (Bitfield-Mask: 0x0f) */
+#define CRYPT_CTRL_LENGTH CRYPT_CTRL_LENGTH_Msk
+#define CRYPT_CTRL_MODE_Pos (4UL) /*!< CRYPT CTRL: MODE (Bit 4) */
+#define CRYPT_CTRL_MODE_Msk (0x70UL) /*!< CRYPT CTRL: MODE (Bitfield-Mask: 0x07) */
+#define CRYPT_CTRL_MODE CRYPT_CTRL_MODE_Msk
+#define CRYPT_CTRL_ACT_Pos (0UL) /*!< CRYPT CTRL: ACT (Bit 0) */
+#define CRYPT_CTRL_ACT_Msk (0x1UL) /*!< CRYPT CTRL: ACT (Bitfield-Mask: 0x01) */
+#define CRYPT_CTRL_ACT CRYPT_CTRL_ACT_Msk
+/* ========================================================= PTRA ========================================================== */
+#define CRYPT_PTRA_PTRA_Pos (0UL) /*!< CRYPT PTRA: PTRA (Bit 0) */
+#define CRYPT_PTRA_PTRA_Msk (0xffffUL) /*!< CRYPT PTRA: PTRA (Bitfield-Mask: 0xffff) */
+#define CRYPT_PTRA_PTRA CRYPT_PTRA_PTRA_Msk
+/* ========================================================= PTRB ========================================================== */
+#define CRYPT_PTRB_PTRB_Pos (0UL) /*!< CRYPT PTRB: PTRB (Bit 0) */
+#define CRYPT_PTRB_PTRB_Msk (0xffffUL) /*!< CRYPT PTRB: PTRB (Bitfield-Mask: 0xffff) */
+#define CRYPT_PTRB_PTRB CRYPT_PTRB_PTRB_Msk
+/* ========================================================= PTRO ========================================================== */
+#define CRYPT_PTRO_PTRO_Pos (0UL) /*!< CRYPT PTRO: PTRO (Bit 0) */
+#define CRYPT_PTRO_PTRO_Msk (0xffffUL) /*!< CRYPT PTRO: PTRO (Bitfield-Mask: 0xffff) */
+#define CRYPT_PTRO_PTRO CRYPT_PTRO_PTRO_Msk
+/* ========================================================= CARRY ========================================================= */
+#define CRYPT_CARRY_CARRY_Pos (0UL) /*!< CRYPT CARRY: CARRY (Bit 0) */
+#define CRYPT_CARRY_CARRY_Msk (0x1UL) /*!< CRYPT CARRY: CARRY (Bitfield-Mask: 0x01) */
+#define CRYPT_CARRY_CARRY CRYPT_CARRY_CARRY_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ DMA ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== IE =========================================================== */
+#define DMA_IE_C3DAIE_Pos (11UL) /*!< DMA IE: C3DAIE (Bit 11) */
+#define DMA_IE_C3DAIE_Msk (0x800UL) /*!< DMA IE: C3DAIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C3DAIE DMA_IE_C3DAIE_Msk
+#define DMA_IE_C2DAIE_Pos (10UL) /*!< DMA IE: C2DAIE (Bit 10) */
+#define DMA_IE_C2DAIE_Msk (0x400UL) /*!< DMA IE: C2DAIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C2DAIE DMA_IE_C2DAIE_Msk
+#define DMA_IE_C1DAIE_Pos (9UL) /*!< DMA IE: C1DAIE (Bit 9) */
+#define DMA_IE_C1DAIE_Msk (0x200UL) /*!< DMA IE: C1DAIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C1DAIE DMA_IE_C1DAIE_Msk
+#define DMA_IE_C0DAIE_Pos (8UL) /*!< DMA IE: C0DAIE (Bit 8) */
+#define DMA_IE_C0DAIE_Msk (0x100UL) /*!< DMA IE: C0DAIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C0DAIE DMA_IE_C0DAIE_Msk
+#define DMA_IE_C3FEIE_Pos (7UL) /*!< DMA IE: C3FEIE (Bit 7) */
+#define DMA_IE_C3FEIE_Msk (0x80UL) /*!< DMA IE: C3FEIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C3FEIE DMA_IE_C3FEIE_Msk
+#define DMA_IE_C2FEIE_Pos (6UL) /*!< DMA IE: C2FEIE (Bit 6) */
+#define DMA_IE_C2FEIE_Msk (0x40UL) /*!< DMA IE: C2FEIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C2FEIE DMA_IE_C2FEIE_Msk
+#define DMA_IE_C1FEIE_Pos (5UL) /*!< DMA IE: C1FEIE (Bit 5) */
+#define DMA_IE_C1FEIE_Msk (0x20UL) /*!< DMA IE: C1FEIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C1FEIE DMA_IE_C1FEIE_Msk
+#define DMA_IE_C0FEIE_Pos (4UL) /*!< DMA IE: C0FEIE (Bit 4) */
+#define DMA_IE_C0FEIE_Msk (0x10UL) /*!< DMA IE: C0FEIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C0FEIE DMA_IE_C0FEIE_Msk
+#define DMA_IE_C3PEIE_Pos (3UL) /*!< DMA IE: C3PEIE (Bit 3) */
+#define DMA_IE_C3PEIE_Msk (0x8UL) /*!< DMA IE: C3PEIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C3PEIE DMA_IE_C3PEIE_Msk
+#define DMA_IE_C2PEIE_Pos (2UL) /*!< DMA IE: C2PEIE (Bit 2) */
+#define DMA_IE_C2PEIE_Msk (0x4UL) /*!< DMA IE: C2PEIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C2PEIE DMA_IE_C2PEIE_Msk
+#define DMA_IE_C1PEIE_Pos (1UL) /*!< DMA IE: C1PEIE (Bit 1) */
+#define DMA_IE_C1PEIE_Msk (0x2UL) /*!< DMA IE: C1PEIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C1PEIE DMA_IE_C1PEIE_Msk
+#define DMA_IE_C0PEIE_Pos (0UL) /*!< DMA IE: C0PEIE (Bit 0) */
+#define DMA_IE_C0PEIE_Msk (0x1UL) /*!< DMA IE: C0PEIE (Bitfield-Mask: 0x01) */
+#define DMA_IE_C0PEIE DMA_IE_C0PEIE_Msk
+/* ========================================================== STS ========================================================== */
+#define DMA_STS_C3DA_Pos (15UL) /*!< DMA STS: C3DA (Bit 15) */
+#define DMA_STS_C3DA_Msk (0x8000UL) /*!< DMA STS: C3DA (Bitfield-Mask: 0x01) */
+#define DMA_STS_C3DA DMA_STS_C3DA_Msk
+#define DMA_STS_C2DA_Pos (14UL) /*!< DMA STS: C2DA (Bit 14) */
+#define DMA_STS_C2DA_Msk (0x4000UL) /*!< DMA STS: C2DA (Bitfield-Mask: 0x01) */
+#define DMA_STS_C2DA DMA_STS_C2DA_Msk
+#define DMA_STS_C1DA_Pos (13UL) /*!< DMA STS: C1DA (Bit 13) */
+#define DMA_STS_C1DA_Msk (0x2000UL) /*!< DMA STS: C1DA (Bitfield-Mask: 0x01) */
+#define DMA_STS_C1DA DMA_STS_C1DA_Msk
+#define DMA_STS_C0DA_Pos (12UL) /*!< DMA STS: C0DA (Bit 12) */
+#define DMA_STS_C0DA_Msk (0x1000UL) /*!< DMA STS: C0DA (Bitfield-Mask: 0x01) */
+#define DMA_STS_C0DA DMA_STS_C0DA_Msk
+#define DMA_STS_C3FE_Pos (11UL) /*!< DMA STS: C3FE (Bit 11) */
+#define DMA_STS_C3FE_Msk (0x800UL) /*!< DMA STS: C3FE (Bitfield-Mask: 0x01) */
+#define DMA_STS_C3FE DMA_STS_C3FE_Msk
+#define DMA_STS_C2FE_Pos (10UL) /*!< DMA STS: C2FE (Bit 10) */
+#define DMA_STS_C2FE_Msk (0x400UL) /*!< DMA STS: C2FE (Bitfield-Mask: 0x01) */
+#define DMA_STS_C2FE DMA_STS_C2FE_Msk
+#define DMA_STS_C1FE_Pos (9UL) /*!< DMA STS: C1FE (Bit 9) */
+#define DMA_STS_C1FE_Msk (0x200UL) /*!< DMA STS: C1FE (Bitfield-Mask: 0x01) */
+#define DMA_STS_C1FE DMA_STS_C1FE_Msk
+#define DMA_STS_C0FE_Pos (8UL) /*!< DMA STS: C0FE (Bit 8) */
+#define DMA_STS_C0FE_Msk (0x100UL) /*!< DMA STS: C0FE (Bitfield-Mask: 0x01) */
+#define DMA_STS_C0FE DMA_STS_C0FE_Msk
+#define DMA_STS_C3PE_Pos (7UL) /*!< DMA STS: C3PE (Bit 7) */
+#define DMA_STS_C3PE_Msk (0x80UL) /*!< DMA STS: C3PE (Bitfield-Mask: 0x01) */
+#define DMA_STS_C3PE DMA_STS_C3PE_Msk
+#define DMA_STS_C2PE_Pos (6UL) /*!< DMA STS: C2PE (Bit 6) */
+#define DMA_STS_C2PE_Msk (0x40UL) /*!< DMA STS: C2PE (Bitfield-Mask: 0x01) */
+#define DMA_STS_C2PE DMA_STS_C2PE_Msk
+#define DMA_STS_C1PE_Pos (5UL) /*!< DMA STS: C1PE (Bit 5) */
+#define DMA_STS_C1PE_Msk (0x20UL) /*!< DMA STS: C1PE (Bitfield-Mask: 0x01) */
+#define DMA_STS_C1PE DMA_STS_C1PE_Msk
+#define DMA_STS_C0PE_Pos (4UL) /*!< DMA STS: C0PE (Bit 4) */
+#define DMA_STS_C0PE_Msk (0x10UL) /*!< DMA STS: C0PE (Bitfield-Mask: 0x01) */
+#define DMA_STS_C0PE DMA_STS_C0PE_Msk
+#define DMA_STS_C3BUSY_Pos (3UL) /*!< DMA STS: C3BUSY (Bit 3) */
+#define DMA_STS_C3BUSY_Msk (0x8UL) /*!< DMA STS: C3BUSY (Bitfield-Mask: 0x01) */
+#define DMA_STS_C3BUSY DMA_STS_C3BUSY_Msk
+#define DMA_STS_C2BUSY_Pos (2UL) /*!< DMA STS: C2BUSY (Bit 2) */
+#define DMA_STS_C2BUSY_Msk (0x4UL) /*!< DMA STS: C2BUSY (Bitfield-Mask: 0x01) */
+#define DMA_STS_C2BUSY DMA_STS_C2BUSY_Msk
+#define DMA_STS_C1BUSY_Pos (1UL) /*!< DMA STS: C1BUSY (Bit 1) */
+#define DMA_STS_C1BUSY_Msk (0x2UL) /*!< DMA STS: C1BUSY (Bitfield-Mask: 0x01) */
+#define DMA_STS_C1BUSY DMA_STS_C1BUSY_Msk
+#define DMA_STS_C0BUSY_Pos (0UL) /*!< DMA STS: C0BUSY (Bit 0) */
+#define DMA_STS_C0BUSY_Msk (0x1UL) /*!< DMA STS: C0BUSY (Bitfield-Mask: 0x01) */
+#define DMA_STS_C0BUSY DMA_STS_C0BUSY_Msk
+/* ========================================================= CCTL ========================================================== */
+#define DMA_CCTL_FLEN_Pos (24UL) /*!< DMA CCTL: FLEN (Bit 24) */
+#define DMA_CCTL_FLEN_Msk (0xff000000UL) /*!< DMA CCTL: FLEN (Bitfield-Mask: 0xff) */
+#define DMA_CCTL_FLEN DMA_CCTL_FLEN_Msk
+#define DMA_CCTL_PLEN_Pos (16UL) /*!< DMA CCTL: PLEN (Bit 16) */
+#define DMA_CCTL_PLEN_Msk (0xff0000UL) /*!< DMA CCTL: PLEN (Bitfield-Mask: 0xff) */
+#define DMA_CCTL_PLEN DMA_CCTL_PLEN_Msk
+#define DMA_CCTL_STOP_Pos (15UL) /*!< DMA CCTL: STOP (Bit 15) */
+#define DMA_CCTL_STOP_Msk (0x8000UL) /*!< DMA CCTL: STOP (Bitfield-Mask: 0x01) */
+#define DMA_CCTL_STOP DMA_CCTL_STOP_Msk
+#define DMA_CCTL_AESEN_Pos (14UL) /*!< DMA CCTL: AESEN (Bit 14) */
+#define DMA_CCTL_AESEN_Msk (0x4000UL) /*!< DMA CCTL: AESEN (Bitfield-Mask: 0x01) */
+#define DMA_CCTL_AESEN DMA_CCTL_AESEN_Msk
+#define DMA_CCTL_CONT_Pos (13UL) /*!< DMA CCTL: CONT (Bit 13) */
+#define DMA_CCTL_CONT_Msk (0x2000UL) /*!< DMA CCTL: CONT (Bitfield-Mask: 0x01) */
+#define DMA_CCTL_CONT DMA_CCTL_CONT_Msk
+#define DMA_CCTL_TMODE_Pos (12UL) /*!< DMA CCTL: TMODE (Bit 12) */
+#define DMA_CCTL_TMODE_Msk (0x1000UL) /*!< DMA CCTL: TMODE (Bitfield-Mask: 0x01) */
+#define DMA_CCTL_TMODE DMA_CCTL_TMODE_Msk
+#define DMA_CCTL_DMASEL_Pos (7UL) /*!< DMA CCTL: DMASEL (Bit 7) */
+#define DMA_CCTL_DMASEL_Msk (0xf80UL) /*!< DMA CCTL: DMASEL (Bitfield-Mask: 0x1f) */
+#define DMA_CCTL_DMASEL DMA_CCTL_DMASEL_Msk
+#define DMA_CCTL_DMODE_Pos (5UL) /*!< DMA CCTL: DMODE (Bit 5) */
+#define DMA_CCTL_DMODE_Msk (0x60UL) /*!< DMA CCTL: DMODE (Bitfield-Mask: 0x03) */
+#define DMA_CCTL_DMODE DMA_CCTL_DMODE_Msk
+#define DMA_CCTL_SMODE_Pos (3UL) /*!< DMA CCTL: SMODE (Bit 3) */
+#define DMA_CCTL_SMODE_Msk (0x18UL) /*!< DMA CCTL: SMODE (Bitfield-Mask: 0x03) */
+#define DMA_CCTL_SMODE DMA_CCTL_SMODE_Msk
+#define DMA_CCTL_SIZE_Pos (1UL) /*!< DMA CCTL: SIZE (Bit 1) */
+#define DMA_CCTL_SIZE_Msk (0x6UL) /*!< DMA CCTL: SIZE (Bitfield-Mask: 0x03) */
+#define DMA_CCTL_SIZE DMA_CCTL_SIZE_Msk
+#define DMA_CCTL_EN_Pos (0UL) /*!< DMA CCTL: EN (Bit 0) */
+#define DMA_CCTL_EN_Msk (0x1UL) /*!< DMA CCTL: EN (Bitfield-Mask: 0x01) */
+#define DMA_CCTL_EN DMA_CCTL_EN_Msk
+/* ========================================================= CSRC ========================================================== */
+#define DMA_CSRC_SRC_Pos (0UL) /*!< DMA CSRC: SRC (Bit 0) */
+#define DMA_CSRC_SRC_Msk (0xffffffffUL) /*!< DMA CSRC: SRC (Bitfield-Mask: 0xffffffff) */
+#define DMA_CSRC_SRC DMA_CSRC_SRC_Msk
+/* ========================================================= CDST ========================================================== */
+#define DMA_CDST_DST_Pos (0UL) /*!< DMA CDST: DST (Bit 0) */
+#define DMA_CDST_DST_Msk (0xffffffffUL) /*!< DMA CDST: DST (Bitfield-Mask: 0xffffffff) */
+#define DMA_CDST_DST DMA_CDST_DST_Msk
+/* ========================================================= CLEN ========================================================== */
+#define DMA_CLEN_CFLEN_Pos (8UL) /*!< DMA CLEN: CFLEN (Bit 8) */
+#define DMA_CLEN_CFLEN_Msk (0xff00UL) /*!< DMA CLEN: CFLEN (Bitfield-Mask: 0xff) */
+#define DMA_CLEN_CFLEN DMA_CLEN_CFLEN_Msk
+#define DMA_CLEN_CPLEN_Pos (0UL) /*!< DMA CLEN: CPLEN (Bit 0) */
+#define DMA_CLEN_CPLEN_Msk (0xffUL) /*!< DMA CLEN: CPLEN (Bitfield-Mask: 0xff) */
+#define DMA_CLEN_CPLEN DMA_CLEN_CPLEN_Msk
+/* ======================================================== AESCTL ========================================================= */
+#define DMA_AESCTL_MODE_Pos (2UL) /*!< DMA AESCTL: MODE (Bit 2) */
+#define DMA_AESCTL_MODE_Msk (0xcUL) /*!< DMA AESCTL: MODE (Bitfield-Mask: 0x03) */
+#define DMA_AESCTL_MODE DMA_AESCTL_MODE_Msk
+#define DMA_AESCTL_ENC_Pos (0UL) /*!< DMA AESCTL: ENC (Bit 0) */
+#define DMA_AESCTL_ENC_Msk (0x1UL) /*!< DMA AESCTL: ENC (Bitfield-Mask: 0x01) */
+#define DMA_AESCTL_ENC DMA_AESCTL_ENC_Msk
+/* ======================================================== AESKEY ========================================================= */
+#define DMA_AESKEY_KEY_Pos (0UL) /*!< DMA AESKEY: KEY (Bit 0) */
+#define DMA_AESKEY_KEY_Msk (0xffffffffUL) /*!< DMA AESKEY: KEY (Bitfield-Mask: 0xffffffff) */
+#define DMA_AESKEY_KEY DMA_AESKEY_KEY_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ FLASH ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ICEPROT ======================================================== */
+#define FLASH_ICEPROT_ICEPROT_Pos (0UL) /*!< FLASH ICEPROT: ICEPROT (Bit 0) */
+#define FLASH_ICEPROT_ICEPROT_Msk (0xffffffffUL) /*!< FLASH ICEPROT: ICEPROT (Bitfield-Mask: 0xffffffff) */
+#define FLASH_ICEPROT_ICEPROT FLASH_ICEPROT_ICEPROT_Msk
+/* ======================================================== RDPROT ========================================================= */
+#define FLASH_RDPROT_RDPORT_Pos (0UL) /*!< FLASH RDPROT: RDPORT (Bit 0) */
+#define FLASH_RDPROT_RDPORT_Msk (0xffffffffUL) /*!< FLASH RDPROT: RDPORT (Bitfield-Mask: 0xffffffff) */
+#define FLASH_RDPROT_RDPORT FLASH_RDPROT_RDPORT_Msk
+/* ======================================================== WRPROT ========================================================= */
+#define FLASH_WRPROT_WRPORT_Pos (0UL) /*!< FLASH WRPROT: WRPORT (Bit 0) */
+#define FLASH_WRPROT_WRPORT_Msk (0xffffffffUL) /*!< FLASH WRPROT: WRPORT (Bitfield-Mask: 0xffffffff) */
+#define FLASH_WRPROT_WRPORT FLASH_WRPROT_WRPORT_Msk
+/* ========================================================== STS ========================================================== */
+#define FLASH_STS_STS_Pos (0UL) /*!< FLASH STS: STS (Bit 0) */
+#define FLASH_STS_STS_Msk (0x1fUL) /*!< FLASH STS: STS (Bitfield-Mask: 0x1f) */
+#define FLASH_STS_STS FLASH_STS_STS_Msk
+/* ======================================================== INTSTS ========================================================= */
+#define FLASH_INTSTS_CSERR_Pos (0UL) /*!< FLASH INTSTS: CSERR (Bit 0) */
+#define FLASH_INTSTS_CSERR_Msk (0x1UL) /*!< FLASH INTSTS: CSERR (Bitfield-Mask: 0x01) */
+#define FLASH_INTSTS_CSERR FLASH_INTSTS_CSERR_Msk
+/* ======================================================== CSSADDR ======================================================== */
+#define FLASH_CSSADDR_CSSADDR_Pos (0UL) /*!< FLASH CSSADDR: CSSADDR (Bit 0) */
+#define FLASH_CSSADDR_CSSADDR_Msk (0x7ffffUL) /*!< FLASH CSSADDR: CSSADDR (Bitfield-Mask: 0x7ffff) */
+#define FLASH_CSSADDR_CSSADDR FLASH_CSSADDR_CSSADDR_Msk
+/* ======================================================== CSEADDR ======================================================== */
+#define FLASH_CSEADDR_CSEADDR_Pos (0UL) /*!< FLASH CSEADDR: CSEADDR (Bit 0) */
+#define FLASH_CSEADDR_CSEADDR_Msk (0x7ffffUL) /*!< FLASH CSEADDR: CSEADDR (Bitfield-Mask: 0x7ffff) */
+#define FLASH_CSEADDR_CSEADDR FLASH_CSEADDR_CSEADDR_Msk
+/* ======================================================== CSVALUE ======================================================== */
+#define FLASH_CSVALUE_CSVALUE_Pos (0UL) /*!< FLASH CSVALUE: CSVALUE (Bit 0) */
+#define FLASH_CSVALUE_CSVALUE_Msk (0xffffffffUL) /*!< FLASH CSVALUE: CSVALUE (Bitfield-Mask: 0xffffffff) */
+#define FLASH_CSVALUE_CSVALUE FLASH_CSVALUE_CSVALUE_Msk
+/* ======================================================= CSCVALUE ======================================================== */
+#define FLASH_CSCVALUE_CSCVALUE_Pos (0UL) /*!< FLASH CSCVALUE: CSCVALUE (Bit 0) */
+#define FLASH_CSCVALUE_CSCVALUE_Msk (0xffffffffUL) /*!< FLASH CSCVALUE: CSCVALUE (Bitfield-Mask: 0xffffffff) */
+#define FLASH_CSCVALUE_CSCVALUE FLASH_CSCVALUE_CSCVALUE_Msk
+/* ========================================================= PASS ========================================================== */
+#define FLASH_PASS_UNLOCK_Pos (0UL) /*!< FLASH PASS: UNLOCK (Bit 0) */
+#define FLASH_PASS_UNLOCK_Msk (0x1UL) /*!< FLASH PASS: UNLOCK (Bitfield-Mask: 0x01) */
+#define FLASH_PASS_UNLOCK FLASH_PASS_UNLOCK_Msk
+/* ========================================================= CTRL ========================================================== */
+#define FLASH_CTRL_CSINTEN_Pos (2UL) /*!< FLASH CTRL: CSINTEN (Bit 2) */
+#define FLASH_CTRL_CSINTEN_Msk (0x4UL) /*!< FLASH CTRL: CSINTEN (Bitfield-Mask: 0x01) */
+#define FLASH_CTRL_CSINTEN FLASH_CTRL_CSINTEN_Msk
+#define FLASH_CTRL_CSMODE_Pos (0UL) /*!< FLASH CTRL: CSMODE (Bit 0) */
+#define FLASH_CTRL_CSMODE_Msk (0x3UL) /*!< FLASH CTRL: CSMODE (Bitfield-Mask: 0x03) */
+#define FLASH_CTRL_CSMODE FLASH_CTRL_CSMODE_Msk
+/* ======================================================== PGADDR ========================================================= */
+#define FLASH_PGADDR_PGADDR_Pos (0UL) /*!< FLASH PGADDR: PGADDR (Bit 0) */
+#define FLASH_PGADDR_PGADDR_Msk (0x3ffffUL) /*!< FLASH PGADDR: PGADDR (Bitfield-Mask: 0x3ffff) */
+#define FLASH_PGADDR_PGADDR FLASH_PGADDR_PGADDR_Msk
+/* ======================================================== PGDATA ========================================================= */
+#define FLASH_PGDATA_PGDATA_Pos (0UL) /*!< FLASH PGDATA: PGDATA (Bit 0) */
+#define FLASH_PGDATA_PGDATA_Msk (0xffffffffUL) /*!< FLASH PGDATA: PGDATA (Bitfield-Mask: 0xffffffff) */
+#define FLASH_PGDATA_PGDATA FLASH_PGDATA_PGDATA_Msk
+/* ======================================================== SERASE ========================================================= */
+#define FLASH_SERASE_SERASE_Pos (0UL) /*!< FLASH SERASE: SERASE (Bit 0) */
+#define FLASH_SERASE_SERASE_Msk (0x1UL) /*!< FLASH SERASE: SERASE (Bitfield-Mask: 0x01) */
+#define FLASH_SERASE_SERASE FLASH_SERASE_SERASE_Msk
+/* ======================================================== CERASE ========================================================= */
+#define FLASH_CERASE_CERASE_Pos (0UL) /*!< FLASH CERASE: CERASE (Bit 0) */
+#define FLASH_CERASE_CERASE_Msk (0x1UL) /*!< FLASH CERASE: CERASE (Bitfield-Mask: 0x01) */
+#define FLASH_CERASE_CERASE FLASH_CERASE_CERASE_Msk
+/* ========================================================= DSTB ========================================================== */
+#define FLASH_DSTB_DSTB_Pos (0UL) /*!< FLASH DSTB: DSTB (Bit 0) */
+#define FLASH_DSTB_DSTB_Msk (0x1UL) /*!< FLASH DSTB: DSTB (Bitfield-Mask: 0x01) */
+#define FLASH_DSTB_DSTB FLASH_DSTB_DSTB_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOA ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== OEN ========================================================== */
+#define GPIOA_OEN_IOAOEN_Pos (0UL) /*!< GPIOA OEN: IOAOEN (Bit 0) */
+#define GPIOA_OEN_IOAOEN_Msk (0xffffUL) /*!< GPIOA OEN: IOAOEN (Bitfield-Mask: 0xffff) */
+#define GPIOA_OEN_IOAOEN GPIOA_OEN_IOAOEN_Msk
+/* ========================================================== IE =========================================================== */
+#define GPIOA_IE_IOAIE_Pos (0UL) /*!< GPIOA IE: IOAIE (Bit 0) */
+#define GPIOA_IE_IOAIE_Msk (0xffffUL) /*!< GPIOA IE: IOAIE (Bitfield-Mask: 0xffff) */
+#define GPIOA_IE_IOAIE GPIOA_IE_IOAIE_Msk
+/* ========================================================== DAT ========================================================== */
+#define GPIOA_DAT_IOADAT_Pos (0UL) /*!< GPIOA DAT: IOADAT (Bit 0) */
+#define GPIOA_DAT_IOADAT_Msk (0xffffUL) /*!< GPIOA DAT: IOADAT (Bitfield-Mask: 0xffff) */
+#define GPIOA_DAT_IOADAT GPIOA_DAT_IOADAT_Msk
+/* ========================================================== ATT ========================================================== */
+#define GPIOA_ATT_IOAATT_Pos (0UL) /*!< GPIOA ATT: IOAATT (Bit 0) */
+#define GPIOA_ATT_IOAATT_Msk (0xffffUL) /*!< GPIOA ATT: IOAATT (Bitfield-Mask: 0xffff) */
+#define GPIOA_ATT_IOAATT GPIOA_ATT_IOAATT_Msk
+/* ======================================================= IOAWKUEN ======================================================== */
+#define GPIOA_IOAWKUEN_WKUEN_Pos (0UL) /*!< GPIOA IOAWKUEN: WKUEN (Bit 0) */
+#define GPIOA_IOAWKUEN_WKUEN_Msk (0xffffffffUL) /*!< GPIOA IOAWKUEN: WKUEN (Bitfield-Mask: 0xffffffff) */
+#define GPIOA_IOAWKUEN_WKUEN GPIOA_IOAWKUEN_WKUEN_Msk
+/* ========================================================== STS ========================================================== */
+#define GPIOA_STS_IOASTS_Pos (0UL) /*!< GPIOA STS: IOASTS (Bit 0) */
+#define GPIOA_STS_IOASTS_Msk (0xffffUL) /*!< GPIOA STS: IOASTS (Bitfield-Mask: 0xffff) */
+#define GPIOA_STS_IOASTS GPIOA_STS_IOASTS_Msk
+/* ======================================================= IOAINTSTS ======================================================= */
+#define GPIOA_IOAINTSTS_INTSTS_Pos (0UL) /*!< GPIOA IOAINTSTS: INTSTS (Bit 0) */
+#define GPIOA_IOAINTSTS_INTSTS_Msk (0xffffUL) /*!< GPIOA IOAINTSTS: INTSTS (Bitfield-Mask: 0xffff) */
+#define GPIOA_IOAINTSTS_INTSTS GPIOA_IOAINTSTS_INTSTS_Msk
+/* ========================================================== SEL ========================================================== */
+#define GPIOA_SEL_SEL7_Pos (7UL) /*!< GPIOA SEL: SEL7 (Bit 7) */
+#define GPIOA_SEL_SEL7_Msk (0x80UL) /*!< GPIOA SEL: SEL7 (Bitfield-Mask: 0x01) */
+#define GPIOA_SEL_SEL7 GPIOA_SEL_SEL7_Msk
+#define GPIOA_SEL_SEL6_Pos (6UL) /*!< GPIOA SEL: SEL6 (Bit 6) */
+#define GPIOA_SEL_SEL6_Msk (0x40UL) /*!< GPIOA SEL: SEL6 (Bitfield-Mask: 0x01) */
+#define GPIOA_SEL_SEL6 GPIOA_SEL_SEL6_Msk
+#define GPIOA_SEL_SEL3_Pos (3UL) /*!< GPIOA SEL: SEL3 (Bit 3) */
+#define GPIOA_SEL_SEL3_Msk (0x8UL) /*!< GPIOA SEL: SEL3 (Bitfield-Mask: 0x01) */
+#define GPIOA_SEL_SEL3 GPIOA_SEL_SEL3_Msk
+/* ======================================================= IOANODEG ======================================================== */
+#define GPIOA_IOANODEG_NODEG_Pos (0UL) /*!< GPIOA IOANODEG: NODEG (Bit 0) */
+#define GPIOA_IOANODEG_NODEG_Msk (0xffffUL) /*!< GPIOA IOANODEG: NODEG (Bitfield-Mask: 0xffff) */
+#define GPIOA_IOANODEG_NODEG GPIOA_IOANODEG_NODEG_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ GPIO ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== OEN ========================================================== */
+#define GPIO_OEN_IOXOEN_Pos (0UL) /*!< GPIO OEN: IOXOEN (Bit 0) */
+#define GPIO_OEN_IOXOEN_Msk (0xffffUL) /*!< GPIO OEN: IOXOEN (Bitfield-Mask: 0xffff) */
+#define GPIO_OEN_IOXOEN GPIO_OEN_IOXOEN_Msk
+/* ========================================================== IE =========================================================== */
+#define GPIO_IE_IOXIE_Pos (0UL) /*!< GPIO IE: IOXIE (Bit 0) */
+#define GPIO_IE_IOXIE_Msk (0xffffUL) /*!< GPIO IE: IOXIE (Bitfield-Mask: 0xffff) */
+#define GPIO_IE_IOXIE GPIO_IE_IOXIE_Msk
+/* ========================================================== DAT ========================================================== */
+#define GPIO_DAT_IOXDAT_Pos (0UL) /*!< GPIO DAT: IOXDAT (Bit 0) */
+#define GPIO_DAT_IOXDAT_Msk (0xffffUL) /*!< GPIO DAT: IOXDAT (Bitfield-Mask: 0xffff) */
+#define GPIO_DAT_IOXDAT GPIO_DAT_IOXDAT_Msk
+/* ========================================================== ATT ========================================================== */
+#define GPIO_ATT_IOXATT_Pos (0UL) /*!< GPIO ATT: IOXATT (Bit 0) */
+#define GPIO_ATT_IOXATT_Msk (0xffffUL) /*!< GPIO ATT: IOXATT (Bitfield-Mask: 0xffff) */
+#define GPIO_ATT_IOXATT GPIO_ATT_IOXATT_Msk
+/* ========================================================== STS ========================================================== */
+#define GPIO_STS_IOXSTS_Pos (0UL) /*!< GPIO STS: IOXSTS (Bit 0) */
+#define GPIO_STS_IOXSTS_Msk (0xffffUL) /*!< GPIO STS: IOXSTS (Bitfield-Mask: 0xffff) */
+#define GPIO_STS_IOXSTS GPIO_STS_IOXSTS_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOAF ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== IOB_SEL ======================================================== */
+#define GPIOAF_IOB_SEL_SEL6_Pos (6UL) /*!< GPIOAF IOB_SEL: SEL6 (Bit 6) */
+#define GPIOAF_IOB_SEL_SEL6_Msk (0x40UL) /*!< GPIOAF IOB_SEL: SEL6 (Bitfield-Mask: 0x01) */
+#define GPIOAF_IOB_SEL_SEL6 GPIOAF_IOB_SEL_SEL6_Msk
+#define GPIOAF_IOB_SEL_SEL2_Pos (2UL) /*!< GPIOAF IOB_SEL: SEL2 (Bit 2) */
+#define GPIOAF_IOB_SEL_SEL2_Msk (0x4UL) /*!< GPIOAF IOB_SEL: SEL2 (Bitfield-Mask: 0x01) */
+#define GPIOAF_IOB_SEL_SEL2 GPIOAF_IOB_SEL_SEL2_Msk
+#define GPIOAF_IOB_SEL_SEL1_Pos (1UL) /*!< GPIOAF IOB_SEL: SEL1 (Bit 1) */
+#define GPIOAF_IOB_SEL_SEL1_Msk (0x2UL) /*!< GPIOAF IOB_SEL: SEL1 (Bitfield-Mask: 0x01) */
+#define GPIOAF_IOB_SEL_SEL1 GPIOAF_IOB_SEL_SEL1_Msk
+/* ======================================================== IOE_SEL ======================================================== */
+#define GPIOAF_IOE_SEL_SEL7_Pos (7UL) /*!< GPIOAF IOE_SEL: SEL7 (Bit 7) */
+#define GPIOAF_IOE_SEL_SEL7_Msk (0x80UL) /*!< GPIOAF IOE_SEL: SEL7 (Bitfield-Mask: 0x01) */
+#define GPIOAF_IOE_SEL_SEL7 GPIOAF_IOE_SEL_SEL7_Msk
+/* ======================================================== IO_MISC ======================================================== */
+#define GPIOAF_IO_MISC_I2CIOC_Pos (5UL) /*!< GPIOAF IO_MISC: I2CIOC (Bit 5) */
+#define GPIOAF_IO_MISC_I2CIOC_Msk (0x20UL) /*!< GPIOAF IO_MISC: I2CIOC (Bitfield-Mask: 0x01) */
+#define GPIOAF_IO_MISC_I2CIOC GPIOAF_IO_MISC_I2CIOC_Msk
+#define GPIOAF_IO_MISC_PLLHDIV_Pos (0UL) /*!< GPIOAF IO_MISC: PLLHDIV (Bit 0) */
+#define GPIOAF_IO_MISC_PLLHDIV_Msk (0x7UL) /*!< GPIOAF IO_MISC: PLLHDIV (Bitfield-Mask: 0x07) */
+#define GPIOAF_IO_MISC_PLLHDIV GPIOAF_IO_MISC_PLLHDIV_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ I2C ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= DATA ========================================================== */
+#define I2C_DATA_DATA_Pos (0UL) /*!< I2C DATA: DATA (Bit 0) */
+#define I2C_DATA_DATA_Msk (0xffUL) /*!< I2C DATA: DATA (Bitfield-Mask: 0xff) */
+#define I2C_DATA_DATA I2C_DATA_DATA_Msk
+/* ========================================================= ADDR ========================================================== */
+#define I2C_ADDR_SLA_Pos (1UL) /*!< I2C ADDR: SLA (Bit 1) */
+#define I2C_ADDR_SLA_Msk (0xfeUL) /*!< I2C ADDR: SLA (Bitfield-Mask: 0x7f) */
+#define I2C_ADDR_SLA I2C_ADDR_SLA_Msk
+#define I2C_ADDR_GC_Pos (0UL) /*!< I2C ADDR: GC (Bit 0) */
+#define I2C_ADDR_GC_Msk (0x1UL) /*!< I2C ADDR: GC (Bitfield-Mask: 0x01) */
+#define I2C_ADDR_GC I2C_ADDR_GC_Msk
+/* ========================================================= CTRL ========================================================== */
+#define I2C_CTRL_CR2_Pos (7UL) /*!< I2C CTRL: CR2 (Bit 7) */
+#define I2C_CTRL_CR2_Msk (0x80UL) /*!< I2C CTRL: CR2 (Bitfield-Mask: 0x01) */
+#define I2C_CTRL_CR2 I2C_CTRL_CR2_Msk
+#define I2C_CTRL_EN_Pos (6UL) /*!< I2C CTRL: EN (Bit 6) */
+#define I2C_CTRL_EN_Msk (0x40UL) /*!< I2C CTRL: EN (Bitfield-Mask: 0x01) */
+#define I2C_CTRL_EN I2C_CTRL_EN_Msk
+#define I2C_CTRL_STA_Pos (5UL) /*!< I2C CTRL: STA (Bit 5) */
+#define I2C_CTRL_STA_Msk (0x20UL) /*!< I2C CTRL: STA (Bitfield-Mask: 0x01) */
+#define I2C_CTRL_STA I2C_CTRL_STA_Msk
+#define I2C_CTRL_STO_Pos (4UL) /*!< I2C CTRL: STO (Bit 4) */
+#define I2C_CTRL_STO_Msk (0x10UL) /*!< I2C CTRL: STO (Bitfield-Mask: 0x01) */
+#define I2C_CTRL_STO I2C_CTRL_STO_Msk
+#define I2C_CTRL_SI_Pos (3UL) /*!< I2C CTRL: SI (Bit 3) */
+#define I2C_CTRL_SI_Msk (0x8UL) /*!< I2C CTRL: SI (Bitfield-Mask: 0x01) */
+#define I2C_CTRL_SI I2C_CTRL_SI_Msk
+#define I2C_CTRL_AA_Pos (2UL) /*!< I2C CTRL: AA (Bit 2) */
+#define I2C_CTRL_AA_Msk (0x4UL) /*!< I2C CTRL: AA (Bitfield-Mask: 0x01) */
+#define I2C_CTRL_AA I2C_CTRL_AA_Msk
+#define I2C_CTRL_CR1_Pos (1UL) /*!< I2C CTRL: CR1 (Bit 1) */
+#define I2C_CTRL_CR1_Msk (0x2UL) /*!< I2C CTRL: CR1 (Bitfield-Mask: 0x01) */
+#define I2C_CTRL_CR1 I2C_CTRL_CR1_Msk
+#define I2C_CTRL_CR0_Pos (0UL) /*!< I2C CTRL: CR0 (Bit 0) */
+#define I2C_CTRL_CR0_Msk (0x1UL) /*!< I2C CTRL: CR0 (Bitfield-Mask: 0x01) */
+#define I2C_CTRL_CR0 I2C_CTRL_CR0_Msk
+/* ========================================================== STS ========================================================== */
+#define I2C_STS_STS_Pos (3UL) /*!< I2C STS: STS (Bit 3) */
+#define I2C_STS_STS_Msk (0xf8UL) /*!< I2C STS: STS (Bitfield-Mask: 0x1f) */
+#define I2C_STS_STS I2C_STS_STS_Msk
+/* ========================================================= CTRL2 ========================================================= */
+#define I2C_CTRL2_INTEN_Pos (0UL) /*!< I2C CTRL2: INTEN (Bit 0) */
+#define I2C_CTRL2_INTEN_Msk (0x1UL) /*!< I2C CTRL2: INTEN (Bitfield-Mask: 0x01) */
+#define I2C_CTRL2_INTEN I2C_CTRL2_INTEN_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ ISO7816 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================= BAUDDIVL ======================================================== */
+#define ISO7816_BAUDDIVL_BAUDDIVL_Pos (0UL) /*!< ISO7816 BAUDDIVL: BAUDDIVL (Bit 0) */
+#define ISO7816_BAUDDIVL_BAUDDIVL_Msk (0xffUL) /*!< ISO7816 BAUDDIVL: BAUDDIVL (Bitfield-Mask: 0xff) */
+#define ISO7816_BAUDDIVL_BAUDDIVL ISO7816_BAUDDIVL_BAUDDIVL_Msk
+/* ======================================================= BAUDDIVH ======================================================== */
+#define ISO7816_BAUDDIVH_BAUDDIVH_Pos (0UL) /*!< ISO7816 BAUDDIVH: BAUDDIVH (Bit 0) */
+#define ISO7816_BAUDDIVH_BAUDDIVH_Msk (0xffUL) /*!< ISO7816 BAUDDIVH: BAUDDIVH (Bitfield-Mask: 0xff) */
+#define ISO7816_BAUDDIVH_BAUDDIVH ISO7816_BAUDDIVH_BAUDDIVH_Msk
+/* ========================================================= DATA ========================================================== */
+#define ISO7816_DATA_DATA_Pos (0UL) /*!< ISO7816 DATA: DATA (Bit 0) */
+#define ISO7816_DATA_DATA_Msk (0xffUL) /*!< ISO7816 DATA: DATA (Bitfield-Mask: 0xff) */
+#define ISO7816_DATA_DATA ISO7816_DATA_DATA_Msk
+/* ========================================================= INFO ========================================================== */
+#define ISO7816_INFO_DMATXDONE_Pos (9UL) /*!< ISO7816 INFO: DMATXDONE (Bit 9) */
+#define ISO7816_INFO_DMATXDONE_Msk (0x200UL) /*!< ISO7816 INFO: DMATXDONE (Bitfield-Mask: 0x01) */
+#define ISO7816_INFO_DMATXDONE ISO7816_INFO_DMATXDONE_Msk
+#define ISO7816_INFO_TXRTYERRIF_Pos (8UL) /*!< ISO7816 INFO: TXRTYERRIF (Bit 8) */
+#define ISO7816_INFO_TXRTYERRIF_Msk (0x100UL) /*!< ISO7816 INFO: TXRTYERRIF (Bitfield-Mask: 0x01) */
+#define ISO7816_INFO_TXRTYERRIF ISO7816_INFO_TXRTYERRIF_Msk
+#define ISO7816_INFO_RXOVIF_Pos (7UL) /*!< ISO7816 INFO: RXOVIF (Bit 7) */
+#define ISO7816_INFO_RXOVIF_Msk (0x80UL) /*!< ISO7816 INFO: RXOVIF (Bitfield-Mask: 0x01) */
+#define ISO7816_INFO_RXOVIF ISO7816_INFO_RXOVIF_Msk
+#define ISO7816_INFO_TXDONEIF_Pos (6UL) /*!< ISO7816 INFO: TXDONEIF (Bit 6) */
+#define ISO7816_INFO_TXDONEIF_Msk (0x40UL) /*!< ISO7816 INFO: TXDONEIF (Bitfield-Mask: 0x01) */
+#define ISO7816_INFO_TXDONEIF ISO7816_INFO_TXDONEIF_Msk
+#define ISO7816_INFO_RXIF_Pos (5UL) /*!< ISO7816 INFO: RXIF (Bit 5) */
+#define ISO7816_INFO_RXIF_Msk (0x20UL) /*!< ISO7816 INFO: RXIF (Bitfield-Mask: 0x01) */
+#define ISO7816_INFO_RXIF ISO7816_INFO_RXIF_Msk
+#define ISO7816_INFO_RXERRIF_Pos (2UL) /*!< ISO7816 INFO: RXERRIF (Bit 2) */
+#define ISO7816_INFO_RXERRIF_Msk (0x4UL) /*!< ISO7816 INFO: RXERRIF (Bitfield-Mask: 0x01) */
+#define ISO7816_INFO_RXERRIF ISO7816_INFO_RXERRIF_Msk
+#define ISO7816_INFO_CHKSUM_Pos (1UL) /*!< ISO7816 INFO: CHKSUM (Bit 1) */
+#define ISO7816_INFO_CHKSUM_Msk (0x2UL) /*!< ISO7816 INFO: CHKSUM (Bitfield-Mask: 0x01) */
+#define ISO7816_INFO_CHKSUM ISO7816_INFO_CHKSUM_Msk
+#define ISO7816_INFO_RXACK_Pos (0UL) /*!< ISO7816 INFO: RXACK (Bit 0) */
+#define ISO7816_INFO_RXACK_Msk (0x1UL) /*!< ISO7816 INFO: RXACK (Bitfield-Mask: 0x01) */
+#define ISO7816_INFO_RXACK ISO7816_INFO_RXACK_Msk
+/* ========================================================== CFG ========================================================== */
+#define ISO7816_CFG_RXACKSET_Pos (16UL) /*!< ISO7816 CFG: RXACKSET (Bit 16) */
+#define ISO7816_CFG_RXACKSET_Msk (0x10000UL) /*!< ISO7816 CFG: RXACKSET (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_RXACKSET ISO7816_CFG_RXACKSET_Msk
+#define ISO7816_CFG_TXRTYCNT_Pos (12UL) /*!< ISO7816 CFG: TXRTYCNT (Bit 12) */
+#define ISO7816_CFG_TXRTYCNT_Msk (0xf000UL) /*!< ISO7816 CFG: TXRTYCNT (Bitfield-Mask: 0x0f) */
+#define ISO7816_CFG_TXRTYCNT ISO7816_CFG_TXRTYCNT_Msk
+#define ISO7816_CFG_LSB_Pos (11UL) /*!< ISO7816 CFG: LSB (Bit 11) */
+#define ISO7816_CFG_LSB_Msk (0x800UL) /*!< ISO7816 CFG: LSB (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_LSB ISO7816_CFG_LSB_Msk
+#define ISO7816_CFG_AUTORXACK_Pos (9UL) /*!< ISO7816 CFG: AUTORXACK (Bit 9) */
+#define ISO7816_CFG_AUTORXACK_Msk (0x200UL) /*!< ISO7816 CFG: AUTORXACK (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_AUTORXACK ISO7816_CFG_AUTORXACK_Msk
+#define ISO7816_CFG_TXRTYERRIE_Pos (8UL) /*!< ISO7816 CFG: TXRTYERRIE (Bit 8) */
+#define ISO7816_CFG_TXRTYERRIE_Msk (0x100UL) /*!< ISO7816 CFG: TXRTYERRIE (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_TXRTYERRIE ISO7816_CFG_TXRTYERRIE_Msk
+#define ISO7816_CFG_RXOVIE_Pos (7UL) /*!< ISO7816 CFG: RXOVIE (Bit 7) */
+#define ISO7816_CFG_RXOVIE_Msk (0x80UL) /*!< ISO7816 CFG: RXOVIE (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_RXOVIE ISO7816_CFG_RXOVIE_Msk
+#define ISO7816_CFG_TXDONEIE_Pos (6UL) /*!< ISO7816 CFG: TXDONEIE (Bit 6) */
+#define ISO7816_CFG_TXDONEIE_Msk (0x40UL) /*!< ISO7816 CFG: TXDONEIE (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_TXDONEIE ISO7816_CFG_TXDONEIE_Msk
+#define ISO7816_CFG_RXIE_Pos (5UL) /*!< ISO7816 CFG: RXIE (Bit 5) */
+#define ISO7816_CFG_RXIE_Msk (0x20UL) /*!< ISO7816 CFG: RXIE (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_RXIE ISO7816_CFG_RXIE_Msk
+#define ISO7816_CFG_ACKLEN_Pos (4UL) /*!< ISO7816 CFG: ACKLEN (Bit 4) */
+#define ISO7816_CFG_ACKLEN_Msk (0x10UL) /*!< ISO7816 CFG: ACKLEN (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_ACKLEN ISO7816_CFG_ACKLEN_Msk
+#define ISO7816_CFG_RXERRIE_Pos (2UL) /*!< ISO7816 CFG: RXERRIE (Bit 2) */
+#define ISO7816_CFG_RXERRIE_Msk (0x4UL) /*!< ISO7816 CFG: RXERRIE (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_RXERRIE ISO7816_CFG_RXERRIE_Msk
+#define ISO7816_CFG_CHKP_Pos (1UL) /*!< ISO7816 CFG: CHKP (Bit 1) */
+#define ISO7816_CFG_CHKP_Msk (0x2UL) /*!< ISO7816 CFG: CHKP (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_CHKP ISO7816_CFG_CHKP_Msk
+#define ISO7816_CFG_EN_Pos (0UL) /*!< ISO7816 CFG: EN (Bit 0) */
+#define ISO7816_CFG_EN_Msk (0x1UL) /*!< ISO7816 CFG: EN (Bitfield-Mask: 0x01) */
+#define ISO7816_CFG_EN ISO7816_CFG_EN_Msk
+/* ========================================================== CLK ========================================================== */
+#define ISO7816_CLK_CLKEN_Pos (7UL) /*!< ISO7816 CLK: CLKEN (Bit 7) */
+#define ISO7816_CLK_CLKEN_Msk (0x80UL) /*!< ISO7816 CLK: CLKEN (Bitfield-Mask: 0x01) */
+#define ISO7816_CLK_CLKEN ISO7816_CLK_CLKEN_Msk
+#define ISO7816_CLK_CLKDIV_Pos (0UL) /*!< ISO7816 CLK: CLKDIV (Bit 0) */
+#define ISO7816_CLK_CLKDIV_Msk (0x7fUL) /*!< ISO7816 CLK: CLKDIV (Bitfield-Mask: 0x7f) */
+#define ISO7816_CLK_CLKDIV ISO7816_CLK_CLKDIV_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ LCD ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== FB =========================================================== */
+#define LCD_FB_DATA_Pos (0UL) /*!< LCD FB: DATA (Bit 0) */
+#define LCD_FB_DATA_Msk (0xffffffffUL) /*!< LCD FB: DATA (Bitfield-Mask: 0xffffffff) */
+#define LCD_FB_DATA LCD_FB_DATA_Msk
+/* ========================================================= CTRL ========================================================== */
+#define LCD_CTRL_EN_Pos (7UL) /*!< LCD CTRL: EN (Bit 7) */
+#define LCD_CTRL_EN_Msk (0x80UL) /*!< LCD CTRL: EN (Bitfield-Mask: 0x01) */
+#define LCD_CTRL_EN LCD_CTRL_EN_Msk
+#define LCD_CTRL_TYPE_Pos (4UL) /*!< LCD CTRL: TYPE (Bit 4) */
+#define LCD_CTRL_TYPE_Msk (0x30UL) /*!< LCD CTRL: TYPE (Bitfield-Mask: 0x03) */
+#define LCD_CTRL_TYPE LCD_CTRL_TYPE_Msk
+#define LCD_CTRL_DRV_Pos (2UL) /*!< LCD CTRL: DRV (Bit 2) */
+#define LCD_CTRL_DRV_Msk (0xcUL) /*!< LCD CTRL: DRV (Bitfield-Mask: 0x03) */
+#define LCD_CTRL_DRV LCD_CTRL_DRV_Msk
+#define LCD_CTRL_FRQ_Pos (0UL) /*!< LCD CTRL: FRQ (Bit 0) */
+#define LCD_CTRL_FRQ_Msk (0x3UL) /*!< LCD CTRL: FRQ (Bitfield-Mask: 0x03) */
+#define LCD_CTRL_FRQ LCD_CTRL_FRQ_Msk
+/* ========================================================= CTRL2 ========================================================= */
+#define LCD_CTRL2_SWPR_Pos (8UL) /*!< LCD CTRL2: SWPR (Bit 8) */
+#define LCD_CTRL2_SWPR_Msk (0xff00UL) /*!< LCD CTRL2: SWPR (Bitfield-Mask: 0xff) */
+#define LCD_CTRL2_SWPR LCD_CTRL2_SWPR_Msk
+#define LCD_CTRL2_FBMODE_Pos (6UL) /*!< LCD CTRL2: FBMODE (Bit 6) */
+#define LCD_CTRL2_FBMODE_Msk (0xc0UL) /*!< LCD CTRL2: FBMODE (Bitfield-Mask: 0x03) */
+#define LCD_CTRL2_FBMODE LCD_CTRL2_FBMODE_Msk
+#define LCD_CTRL2_BKFILL_Pos (4UL) /*!< LCD CTRL2: BKFILL (Bit 4) */
+#define LCD_CTRL2_BKFILL_Msk (0x10UL) /*!< LCD CTRL2: BKFILL (Bitfield-Mask: 0x01) */
+#define LCD_CTRL2_BKFILL LCD_CTRL2_BKFILL_Msk
+/* ======================================================= SEGCTRL0 ======================================================== */
+#define LCD_SEGCTRL0_SEGCTRL_Pos (0UL) /*!< LCD SEGCTRL0: SEGCTRL (Bit 0) */
+#define LCD_SEGCTRL0_SEGCTRL_Msk (0xffffffffUL) /*!< LCD SEGCTRL0: SEGCTRL (Bitfield-Mask: 0xffffffff) */
+#define LCD_SEGCTRL0_SEGCTRL LCD_SEGCTRL0_SEGCTRL_Msk
+/* ======================================================= SEGCTRL1 ======================================================== */
+#define LCD_SEGCTRL1_SEGCTRL_Pos (0UL) /*!< LCD SEGCTRL1: SEGCTRL (Bit 0) */
+#define LCD_SEGCTRL1_SEGCTRL_Msk (0xffffffffUL) /*!< LCD SEGCTRL1: SEGCTRL (Bitfield-Mask: 0xffffffff) */
+#define LCD_SEGCTRL1_SEGCTRL LCD_SEGCTRL1_SEGCTRL_Msk
+/* ======================================================= SEGCTRL2 ======================================================== */
+#define LCD_SEGCTRL2_SEGCTRL_Pos (0UL) /*!< LCD SEGCTRL2: SEGCTRL (Bit 0) */
+#define LCD_SEGCTRL2_SEGCTRL_Msk (0xffffUL) /*!< LCD SEGCTRL2: SEGCTRL (Bitfield-Mask: 0xffff) */
+#define LCD_SEGCTRL2_SEGCTRL LCD_SEGCTRL2_SEGCTRL_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ MISC1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== SRAMINT ======================================================== */
+#define MISC1_SRAMINT_LOCKUP_Pos (4UL) /*!< MISC1 SRAMINT: LOCKUP (Bit 4) */
+#define MISC1_SRAMINT_LOCKUP_Msk (0x10UL) /*!< MISC1 SRAMINT: LOCKUP (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINT_LOCKUP MISC1_SRAMINT_LOCKUP_Msk
+#define MISC1_SRAMINT_PIAC_Pos (3UL) /*!< MISC1 SRAMINT: PIAC (Bit 3) */
+#define MISC1_SRAMINT_PIAC_Msk (0x8UL) /*!< MISC1 SRAMINT: PIAC (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINT_PIAC MISC1_SRAMINT_PIAC_Msk
+#define MISC1_SRAMINT_HIAC_Pos (2UL) /*!< MISC1 SRAMINT: HIAC (Bit 2) */
+#define MISC1_SRAMINT_HIAC_Msk (0x4UL) /*!< MISC1 SRAMINT: HIAC (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINT_HIAC MISC1_SRAMINT_HIAC_Msk
+#define MISC1_SRAMINT_HIAL_Pos (1UL) /*!< MISC1 SRAMINT: HIAL (Bit 1) */
+#define MISC1_SRAMINT_HIAL_Msk (0x2UL) /*!< MISC1 SRAMINT: HIAL (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINT_HIAL MISC1_SRAMINT_HIAL_Msk
+#define MISC1_SRAMINT_PERR_Pos (0UL) /*!< MISC1 SRAMINT: PERR (Bit 0) */
+#define MISC1_SRAMINT_PERR_Msk (0x1UL) /*!< MISC1 SRAMINT: PERR (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINT_PERR MISC1_SRAMINT_PERR_Msk
+/* ======================================================= SRAMINIT ======================================================== */
+#define MISC1_SRAMINIT_LOCKIE_Pos (7UL) /*!< MISC1 SRAMINIT: LOCKIE (Bit 7) */
+#define MISC1_SRAMINIT_LOCKIE_Msk (0x80UL) /*!< MISC1 SRAMINIT: LOCKIE (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINIT_LOCKIE MISC1_SRAMINIT_LOCKIE_Msk
+#define MISC1_SRAMINIT_PIACIE_Pos (6UL) /*!< MISC1 SRAMINIT: PIACIE (Bit 6) */
+#define MISC1_SRAMINIT_PIACIE_Msk (0x40UL) /*!< MISC1 SRAMINIT: PIACIE (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINIT_PIACIE MISC1_SRAMINIT_PIACIE_Msk
+#define MISC1_SRAMINIT_HIACIE_Pos (5UL) /*!< MISC1 SRAMINIT: HIACIE (Bit 5) */
+#define MISC1_SRAMINIT_HIACIE_Msk (0x20UL) /*!< MISC1 SRAMINIT: HIACIE (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINIT_HIACIE MISC1_SRAMINIT_HIACIE_Msk
+#define MISC1_SRAMINIT_INIT_Pos (2UL) /*!< MISC1 SRAMINIT: INIT (Bit 2) */
+#define MISC1_SRAMINIT_INIT_Msk (0x4UL) /*!< MISC1 SRAMINIT: INIT (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINIT_INIT MISC1_SRAMINIT_INIT_Msk
+#define MISC1_SRAMINIT_PERRIE_Pos (1UL) /*!< MISC1 SRAMINIT: PERRIE (Bit 1) */
+#define MISC1_SRAMINIT_PERRIE_Msk (0x2UL) /*!< MISC1 SRAMINIT: PERRIE (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINIT_PERRIE MISC1_SRAMINIT_PERRIE_Msk
+#define MISC1_SRAMINIT_PEN_Pos (0UL) /*!< MISC1 SRAMINIT: PEN (Bit 0) */
+#define MISC1_SRAMINIT_PEN_Msk (0x1UL) /*!< MISC1 SRAMINIT: PEN (Bitfield-Mask: 0x01) */
+#define MISC1_SRAMINIT_PEN MISC1_SRAMINIT_PEN_Msk
+/* ======================================================== PARERR ========================================================= */
+#define MISC1_PARERR_PEADDR_Pos (0UL) /*!< MISC1 PARERR: PEADDR (Bit 0) */
+#define MISC1_PARERR_PEADDR_Msk (0x3fffUL) /*!< MISC1 PARERR: PEADDR (Bitfield-Mask: 0x3fff) */
+#define MISC1_PARERR_PEADDR MISC1_PARERR_PEADDR_Msk
+/* ========================================================= IREN ========================================================== */
+#define MISC1_IREN_IREN_Pos (0UL) /*!< MISC1 IREN: IREN (Bit 0) */
+#define MISC1_IREN_IREN_Msk (0x3fUL) /*!< MISC1 IREN: IREN (Bitfield-Mask: 0x3f) */
+#define MISC1_IREN_IREN MISC1_IREN_IREN_Msk
+/* ========================================================= DUTYL ========================================================= */
+#define MISC1_DUTYL_DUTYL_Pos (0UL) /*!< MISC1 DUTYL: DUTYL (Bit 0) */
+#define MISC1_DUTYL_DUTYL_Msk (0xffffUL) /*!< MISC1 DUTYL: DUTYL (Bitfield-Mask: 0xffff) */
+#define MISC1_DUTYL_DUTYL MISC1_DUTYL_DUTYL_Msk
+/* ========================================================= DUTYH ========================================================= */
+#define MISC1_DUTYH_DUTYH_Pos (0UL) /*!< MISC1 DUTYH: DUTYH (Bit 0) */
+#define MISC1_DUTYH_DUTYH_Msk (0xffffUL) /*!< MISC1 DUTYH: DUTYH (Bitfield-Mask: 0xffff) */
+#define MISC1_DUTYH_DUTYH MISC1_DUTYH_DUTYH_Msk
+/* ======================================================== IRQLAT ========================================================= */
+#define MISC1_IRQLAT_NOHARDFAULT_Pos (9UL) /*!< MISC1 IRQLAT: NOHARDFAULT (Bit 9) */
+#define MISC1_IRQLAT_NOHARDFAULT_Msk (0x200UL) /*!< MISC1 IRQLAT: NOHARDFAULT (Bitfield-Mask: 0x01) */
+#define MISC1_IRQLAT_NOHARDFAULT MISC1_IRQLAT_NOHARDFAULT_Msk
+#define MISC1_IRQLAT_LOCKRESET_Pos (8UL) /*!< MISC1 IRQLAT: LOCKRESET (Bit 8) */
+#define MISC1_IRQLAT_LOCKRESET_Msk (0x100UL) /*!< MISC1 IRQLAT: LOCKRESET (Bitfield-Mask: 0x01) */
+#define MISC1_IRQLAT_LOCKRESET MISC1_IRQLAT_LOCKRESET_Msk
+#define MISC1_IRQLAT_IRQLAT_Pos (0UL) /*!< MISC1 IRQLAT: IRQLAT (Bit 0) */
+#define MISC1_IRQLAT_IRQLAT_Msk (0xffUL) /*!< MISC1 IRQLAT: IRQLAT (Bitfield-Mask: 0xff) */
+#define MISC1_IRQLAT_IRQLAT MISC1_IRQLAT_IRQLAT_Msk
+/* ======================================================== HIADDR ========================================================= */
+#define MISC1_HIADDR_HIADDR_Pos (0UL) /*!< MISC1 HIADDR: HIADDR (Bit 0) */
+#define MISC1_HIADDR_HIADDR_Msk (0xffffffffUL) /*!< MISC1 HIADDR: HIADDR (Bitfield-Mask: 0xffffffff) */
+#define MISC1_HIADDR_HIADDR MISC1_HIADDR_HIADDR_Msk
+/* ======================================================== PIADDR ========================================================= */
+#define MISC1_PIADDR_PIADDR_Pos (0UL) /*!< MISC1 PIADDR: PIADDR (Bit 0) */
+#define MISC1_PIADDR_PIADDR_Msk (0xffffffffUL) /*!< MISC1 PIADDR: PIADDR (Bitfield-Mask: 0xffffffff) */
+#define MISC1_PIADDR_PIADDR MISC1_PIADDR_PIADDR_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ MISC2 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== FLASHWC ======================================================== */
+#define MISC2_FLASHWC_CYCLE_1US_Pos (8UL) /*!< MISC2 FLASHWC: CYCLE_1US (Bit 8) */
+#define MISC2_FLASHWC_CYCLE_1US_Msk (0x3f00UL) /*!< MISC2 FLASHWC: CYCLE_1US (Bitfield-Mask: 0x3f) */
+#define MISC2_FLASHWC_CYCLE_1US MISC2_FLASHWC_CYCLE_1US_Msk
+/* ======================================================== CLKSEL ========================================================= */
+#define MISC2_CLKSEL_CLKSEL_Pos (0UL) /*!< MISC2 CLKSEL: CLKSEL (Bit 0) */
+#define MISC2_CLKSEL_CLKSEL_Msk (0x7UL) /*!< MISC2 CLKSEL: CLKSEL (Bitfield-Mask: 0x07) */
+#define MISC2_CLKSEL_CLKSEL MISC2_CLKSEL_CLKSEL_Msk
+/* ======================================================== CLKDIVH ======================================================== */
+#define MISC2_CLKDIVH_CLKDIVH_Pos (0UL) /*!< MISC2 CLKDIVH: CLKDIVH (Bit 0) */
+#define MISC2_CLKDIVH_CLKDIVH_Msk (0xffUL) /*!< MISC2 CLKDIVH: CLKDIVH (Bitfield-Mask: 0xff) */
+#define MISC2_CLKDIVH_CLKDIVH MISC2_CLKDIVH_CLKDIVH_Msk
+/* ======================================================== CLKDIVP ======================================================== */
+#define MISC2_CLKDIVP_CLKDIVP_Pos (0UL) /*!< MISC2 CLKDIVP: CLKDIVP (Bit 0) */
+#define MISC2_CLKDIVP_CLKDIVP_Msk (0xffUL) /*!< MISC2 CLKDIVP: CLKDIVP (Bitfield-Mask: 0xff) */
+#define MISC2_CLKDIVP_CLKDIVP MISC2_CLKDIVP_CLKDIVP_Msk
+/* ======================================================== HCLKEN ========================================================= */
+#define MISC2_HCLKEN_CRYPT_Pos (8UL) /*!< MISC2 HCLKEN: CRYPT (Bit 8) */
+#define MISC2_HCLKEN_CRYPT_Msk (0x100UL) /*!< MISC2 HCLKEN: CRYPT (Bitfield-Mask: 0x01) */
+#define MISC2_HCLKEN_CRYPT MISC2_HCLKEN_CRYPT_Msk
+#define MISC2_HCLKEN_LCD_Pos (6UL) /*!< MISC2 HCLKEN: LCD (Bit 6) */
+#define MISC2_HCLKEN_LCD_Msk (0x40UL) /*!< MISC2 HCLKEN: LCD (Bitfield-Mask: 0x01) */
+#define MISC2_HCLKEN_LCD MISC2_HCLKEN_LCD_Msk
+#define MISC2_HCLKEN_GPIO_Pos (5UL) /*!< MISC2 HCLKEN: GPIO (Bit 5) */
+#define MISC2_HCLKEN_GPIO_Msk (0x20UL) /*!< MISC2 HCLKEN: GPIO (Bitfield-Mask: 0x01) */
+#define MISC2_HCLKEN_GPIO MISC2_HCLKEN_GPIO_Msk
+#define MISC2_HCLKEN_DMA_Pos (4UL) /*!< MISC2 HCLKEN: DMA (Bit 4) */
+#define MISC2_HCLKEN_DMA_Msk (0x10UL) /*!< MISC2 HCLKEN: DMA (Bitfield-Mask: 0x01) */
+#define MISC2_HCLKEN_DMA MISC2_HCLKEN_DMA_Msk
+/* ======================================================== PCLKEN ========================================================= */
+#define MISC2_PCLKEN_SPI3_Pos (22UL) /*!< MISC2 PCLKEN: SPI3 (Bit 22) */
+#define MISC2_PCLKEN_SPI3_Msk (0x400000UL) /*!< MISC2 PCLKEN: SPI3 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_SPI3 MISC2_PCLKEN_SPI3_Msk
+#define MISC2_PCLKEN_SPI2_Pos (21UL) /*!< MISC2 PCLKEN: SPI2 (Bit 21) */
+#define MISC2_PCLKEN_SPI2_Msk (0x200000UL) /*!< MISC2 PCLKEN: SPI2 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_SPI2 MISC2_PCLKEN_SPI2_Msk
+#define MISC2_PCLKEN_U32K1_Pos (19UL) /*!< MISC2 PCLKEN: U32K1 (Bit 19) */
+#define MISC2_PCLKEN_U32K1_Msk (0x80000UL) /*!< MISC2 PCLKEN: U32K1 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_U32K1 MISC2_PCLKEN_U32K1_Msk
+#define MISC2_PCLKEN_U32K0_Pos (18UL) /*!< MISC2 PCLKEN: U32K0 (Bit 18) */
+#define MISC2_PCLKEN_U32K0_Msk (0x40000UL) /*!< MISC2 PCLKEN: U32K0 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_U32K0 MISC2_PCLKEN_U32K0_Msk
+#define MISC2_PCLKEN_ANA_Pos (17UL) /*!< MISC2 PCLKEN: ANA (Bit 17) */
+#define MISC2_PCLKEN_ANA_Msk (0x20000UL) /*!< MISC2 PCLKEN: ANA (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_ANA MISC2_PCLKEN_ANA_Msk
+#define MISC2_PCLKEN_RTC_Pos (16UL) /*!< MISC2 PCLKEN: RTC (Bit 16) */
+#define MISC2_PCLKEN_RTC_Msk (0x10000UL) /*!< MISC2 PCLKEN: RTC (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_RTC MISC2_PCLKEN_RTC_Msk
+#define MISC2_PCLKEN_PMU_Pos (15UL) /*!< MISC2 PCLKEN: PMU (Bit 15) */
+#define MISC2_PCLKEN_PMU_Msk (0x8000UL) /*!< MISC2 PCLKEN: PMU (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_PMU MISC2_PCLKEN_PMU_Msk
+#define MISC2_PCLKEN_MISC2_Pos (14UL) /*!< MISC2 PCLKEN: MISC2 (Bit 14) */
+#define MISC2_PCLKEN_MISC2_Msk (0x4000UL) /*!< MISC2 PCLKEN: MISC2 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_MISC2 MISC2_PCLKEN_MISC2_Msk
+#define MISC2_PCLKEN_MISC1_Pos (13UL) /*!< MISC2 PCLKEN: MISC1 (Bit 13) */
+#define MISC2_PCLKEN_MISC1_Msk (0x2000UL) /*!< MISC2 PCLKEN: MISC1 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_MISC1 MISC2_PCLKEN_MISC1_Msk
+#define MISC2_PCLKEN_TIMER_Pos (12UL) /*!< MISC2 PCLKEN: TIMER (Bit 12) */
+#define MISC2_PCLKEN_TIMER_Msk (0x1000UL) /*!< MISC2 PCLKEN: TIMER (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_TIMER MISC2_PCLKEN_TIMER_Msk
+#define MISC2_PCLKEN_ISO78161_Pos (11UL) /*!< MISC2 PCLKEN: ISO78161 (Bit 11) */
+#define MISC2_PCLKEN_ISO78161_Msk (0x800UL) /*!< MISC2 PCLKEN: ISO78161 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_ISO78161 MISC2_PCLKEN_ISO78161_Msk
+#define MISC2_PCLKEN_ISO78160_Pos (10UL) /*!< MISC2 PCLKEN: ISO78160 (Bit 10) */
+#define MISC2_PCLKEN_ISO78160_Msk (0x400UL) /*!< MISC2 PCLKEN: ISO78160 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_ISO78160 MISC2_PCLKEN_ISO78160_Msk
+#define MISC2_PCLKEN_UART5_Pos (9UL) /*!< MISC2 PCLKEN: UART5 (Bit 9) */
+#define MISC2_PCLKEN_UART5_Msk (0x200UL) /*!< MISC2 PCLKEN: UART5 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_UART5 MISC2_PCLKEN_UART5_Msk
+#define MISC2_PCLKEN_UART4_Pos (8UL) /*!< MISC2 PCLKEN: UART4 (Bit 8) */
+#define MISC2_PCLKEN_UART4_Msk (0x100UL) /*!< MISC2 PCLKEN: UART4 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_UART4 MISC2_PCLKEN_UART4_Msk
+#define MISC2_PCLKEN_UART3_Pos (7UL) /*!< MISC2 PCLKEN: UART3 (Bit 7) */
+#define MISC2_PCLKEN_UART3_Msk (0x80UL) /*!< MISC2 PCLKEN: UART3 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_UART3 MISC2_PCLKEN_UART3_Msk
+#define MISC2_PCLKEN_UART2_Pos (6UL) /*!< MISC2 PCLKEN: UART2 (Bit 6) */
+#define MISC2_PCLKEN_UART2_Msk (0x40UL) /*!< MISC2 PCLKEN: UART2 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_UART2 MISC2_PCLKEN_UART2_Msk
+#define MISC2_PCLKEN_UART1_Pos (5UL) /*!< MISC2 PCLKEN: UART1 (Bit 5) */
+#define MISC2_PCLKEN_UART1_Msk (0x20UL) /*!< MISC2 PCLKEN: UART1 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_UART1 MISC2_PCLKEN_UART1_Msk
+#define MISC2_PCLKEN_UART0_Pos (4UL) /*!< MISC2 PCLKEN: UART0 (Bit 4) */
+#define MISC2_PCLKEN_UART0_Msk (0x10UL) /*!< MISC2 PCLKEN: UART0 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_UART0 MISC2_PCLKEN_UART0_Msk
+#define MISC2_PCLKEN_SPI1_Pos (3UL) /*!< MISC2 PCLKEN: SPI1 (Bit 3) */
+#define MISC2_PCLKEN_SPI1_Msk (0x8UL) /*!< MISC2 PCLKEN: SPI1 (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_SPI1 MISC2_PCLKEN_SPI1_Msk
+#define MISC2_PCLKEN_I2C_Pos (2UL) /*!< MISC2 PCLKEN: I2C (Bit 2) */
+#define MISC2_PCLKEN_I2C_Msk (0x4UL) /*!< MISC2 PCLKEN: I2C (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_I2C MISC2_PCLKEN_I2C_Msk
+#define MISC2_PCLKEN_DMA_Pos (1UL) /*!< MISC2 PCLKEN: DMA (Bit 1) */
+#define MISC2_PCLKEN_DMA_Msk (0x2UL) /*!< MISC2 PCLKEN: DMA (Bitfield-Mask: 0x01) */
+#define MISC2_PCLKEN_DMA MISC2_PCLKEN_DMA_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ PMU ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================= DSLEEPEN ======================================================== */
+#define PMU_DSLEEPEN_WKU_Pos (31UL) /*!< PMU DSLEEPEN: WKU (Bit 31) */
+#define PMU_DSLEEPEN_WKU_Msk (0x80000000UL) /*!< PMU DSLEEPEN: WKU (Bitfield-Mask: 0x01) */
+#define PMU_DSLEEPEN_WKU PMU_DSLEEPEN_WKU_Msk
+/* ====================================================== DSLEEPPASS ======================================================= */
+#define PMU_DSLEEPPASS_UNLOCK_Pos (0UL) /*!< PMU DSLEEPPASS: UNLOCK (Bit 0) */
+#define PMU_DSLEEPPASS_UNLOCK_Msk (0x1UL) /*!< PMU DSLEEPPASS: UNLOCK (Bitfield-Mask: 0x01) */
+#define PMU_DSLEEPPASS_UNLOCK PMU_DSLEEPPASS_UNLOCK_Msk
+/* ======================================================== CONTROL ======================================================== */
+#define PMU_CONTROL_FORCE_CLKSEL_RCH_Pos (20UL) /*!< PMU CONTROL: FORCE_CLKSEL_RCH (Bit 20) */
+#define PMU_CONTROL_FORCE_CLKSEL_RCH_Msk (0x100000UL) /*!< PMU CONTROL: FORCE_CLKSEL_RCH (Bitfield-Mask: 0x01) */
+#define PMU_CONTROL_FORCE_CLKSEL_RCH PMU_CONTROL_FORCE_CLKSEL_RCH_Msk
+#define PMU_CONTROL_PWUPCYC_Pos (8UL) /*!< PMU CONTROL: PWUPCYC (Bit 8) */
+#define PMU_CONTROL_PWUPCYC_Msk (0xff00UL) /*!< PMU CONTROL: PWUPCYC (Bitfield-Mask: 0xff) */
+#define PMU_CONTROL_PWUPCYC PMU_CONTROL_PWUPCYC_Msk
+#define PMU_CONTROL_PLLL_SEL_Pos (5UL) /*!< PMU CONTROL: PLLL_SEL (Bit 5) */
+#define PMU_CONTROL_PLLL_SEL_Msk (0x20UL) /*!< PMU CONTROL: PLLL_SEL (Bitfield-Mask: 0x01) */
+#define PMU_CONTROL_PLLL_SEL PMU_CONTROL_PLLL_SEL_Msk
+#define PMU_CONTROL_PLLH_SEL_Pos (4UL) /*!< PMU CONTROL: PLLH_SEL (Bit 4) */
+#define PMU_CONTROL_PLLH_SEL_Msk (0x10UL) /*!< PMU CONTROL: PLLH_SEL (Bitfield-Mask: 0x01) */
+#define PMU_CONTROL_PLLH_SEL PMU_CONTROL_PLLH_SEL_Msk
+#define PMU_CONTROL_INT_6M_EN_Pos (3UL) /*!< PMU CONTROL: INT_6M_EN (Bit 3) */
+#define PMU_CONTROL_INT_6M_EN_Msk (0x8UL) /*!< PMU CONTROL: INT_6M_EN (Bitfield-Mask: 0x01) */
+#define PMU_CONTROL_INT_6M_EN PMU_CONTROL_INT_6M_EN_Msk
+#define PMU_CONTROL_INT_32K_EN_Pos (2UL) /*!< PMU CONTROL: INT_32K_EN (Bit 2) */
+#define PMU_CONTROL_INT_32K_EN_Msk (0x4UL) /*!< PMU CONTROL: INT_32K_EN (Bitfield-Mask: 0x01) */
+#define PMU_CONTROL_INT_32K_EN PMU_CONTROL_INT_32K_EN_Msk
+#define PMU_CONTROL_RTCCLK_SEL_Pos (1UL) /*!< PMU CONTROL: RTCCLK_SEL (Bit 1) */
+#define PMU_CONTROL_RTCCLK_SEL_Msk (0x2UL) /*!< PMU CONTROL: RTCCLK_SEL (Bitfield-Mask: 0x01) */
+#define PMU_CONTROL_RTCCLK_SEL PMU_CONTROL_RTCCLK_SEL_Msk
+#define PMU_CONTROL_INT_IOA_EN_Pos (0UL) /*!< PMU CONTROL: INT_IOA_EN (Bit 0) */
+#define PMU_CONTROL_INT_IOA_EN_Msk (0x1UL) /*!< PMU CONTROL: INT_IOA_EN (Bitfield-Mask: 0x01) */
+#define PMU_CONTROL_INT_IOA_EN PMU_CONTROL_INT_IOA_EN_Msk
+/* ========================================================== STS ========================================================== */
+#define PMU_STS_MODE_Pos (24UL) /*!< PMU STS: MODE (Bit 24) */
+#define PMU_STS_MODE_Msk (0x1000000UL) /*!< PMU STS: MODE (Bitfield-Mask: 0x01) */
+#define PMU_STS_MODE PMU_STS_MODE_Msk
+#define PMU_STS_WKUMODE_Pos (22UL) /*!< PMU STS: WKUMODE (Bit 22) */
+#define PMU_STS_WKUMODE_Msk (0x400000UL) /*!< PMU STS: WKUMODE (Bitfield-Mask: 0x01) */
+#define PMU_STS_WKUMODE PMU_STS_WKUMODE_Msk
+#define PMU_STS_WKUXTAL_Pos (20UL) /*!< PMU STS: WKUXTAL (Bit 20) */
+#define PMU_STS_WKUXTAL_Msk (0x100000UL) /*!< PMU STS: WKUXTAL (Bitfield-Mask: 0x01) */
+#define PMU_STS_WKUXTAL PMU_STS_WKUXTAL_Msk
+#define PMU_STS_WKUU32K_Pos (19UL) /*!< PMU STS: WKUU32K (Bit 19) */
+#define PMU_STS_WKUU32K_Msk (0x80000UL) /*!< PMU STS: WKUU32K (Bitfield-Mask: 0x01) */
+#define PMU_STS_WKUU32K PMU_STS_WKUU32K_Msk
+#define PMU_STS_WKUANA_Pos (18UL) /*!< PMU STS: WKUANA (Bit 18) */
+#define PMU_STS_WKUANA_Msk (0x40000UL) /*!< PMU STS: WKUANA (Bitfield-Mask: 0x01) */
+#define PMU_STS_WKUANA PMU_STS_WKUANA_Msk
+#define PMU_STS_WKURTC_Pos (17UL) /*!< PMU STS: WKURTC (Bit 17) */
+#define PMU_STS_WKURTC_Msk (0x20000UL) /*!< PMU STS: WKURTC (Bitfield-Mask: 0x01) */
+#define PMU_STS_WKURTC PMU_STS_WKURTC_Msk
+#define PMU_STS_WKUIOA_Pos (16UL) /*!< PMU STS: WKUIOA (Bit 16) */
+#define PMU_STS_WKUIOA_Msk (0x10000UL) /*!< PMU STS: WKUIOA (Bitfield-Mask: 0x01) */
+#define PMU_STS_WKUIOA PMU_STS_WKUIOA_Msk
+#define PMU_STS_MODERST_Pos (10UL) /*!< PMU STS: MODERST (Bit 10) */
+#define PMU_STS_MODERST_Msk (0x400UL) /*!< PMU STS: MODERST (Bitfield-Mask: 0x01) */
+#define PMU_STS_MODERST PMU_STS_MODERST_Msk
+#define PMU_STS_SFTRST_Pos (8UL) /*!< PMU STS: SFTRST (Bit 8) */
+#define PMU_STS_SFTRST_Msk (0x100UL) /*!< PMU STS: SFTRST (Bitfield-Mask: 0x01) */
+#define PMU_STS_SFTRST PMU_STS_SFTRST_Msk
+#define PMU_STS_WDTRST_Pos (7UL) /*!< PMU STS: WDTRST (Bit 7) */
+#define PMU_STS_WDTRST_Msk (0x80UL) /*!< PMU STS: WDTRST (Bitfield-Mask: 0x01) */
+#define PMU_STS_WDTRST PMU_STS_WDTRST_Msk
+#define PMU_STS_DPORST_Pos (6UL) /*!< PMU STS: DPORST (Bit 6) */
+#define PMU_STS_DPORST_Msk (0x40UL) /*!< PMU STS: DPORST (Bitfield-Mask: 0x01) */
+#define PMU_STS_DPORST PMU_STS_DPORST_Msk
+#define PMU_STS_PORST_Pos (5UL) /*!< PMU STS: PORST (Bit 5) */
+#define PMU_STS_PORST_Msk (0x20UL) /*!< PMU STS: PORST (Bitfield-Mask: 0x01) */
+#define PMU_STS_PORST PMU_STS_PORST_Msk
+#define PMU_STS_EXTRST_Pos (4UL) /*!< PMU STS: EXTRST (Bit 4) */
+#define PMU_STS_EXTRST_Msk (0x10UL) /*!< PMU STS: EXTRST (Bitfield-Mask: 0x01) */
+#define PMU_STS_EXTRST PMU_STS_EXTRST_Msk
+#define PMU_STS_EXIST_6M_Pos (3UL) /*!< PMU STS: EXIST_6M (Bit 3) */
+#define PMU_STS_EXIST_6M_Msk (0x8UL) /*!< PMU STS: EXIST_6M (Bitfield-Mask: 0x01) */
+#define PMU_STS_EXIST_6M PMU_STS_EXIST_6M_Msk
+#define PMU_STS_EXIST_32K_Pos (2UL) /*!< PMU STS: EXIST_32K (Bit 2) */
+#define PMU_STS_EXIST_32K_Msk (0x4UL) /*!< PMU STS: EXIST_32K (Bitfield-Mask: 0x01) */
+#define PMU_STS_EXIST_32K PMU_STS_EXIST_32K_Msk
+#define PMU_STS_INT_6M_Pos (1UL) /*!< PMU STS: INT_6M (Bit 1) */
+#define PMU_STS_INT_6M_Msk (0x2UL) /*!< PMU STS: INT_6M (Bitfield-Mask: 0x01) */
+#define PMU_STS_INT_6M PMU_STS_INT_6M_Msk
+#define PMU_STS_INT_32K_Pos (0UL) /*!< PMU STS: INT_32K (Bit 0) */
+#define PMU_STS_INT_32K_Msk (0x1UL) /*!< PMU STS: INT_32K (Bitfield-Mask: 0x01) */
+#define PMU_STS_INT_32K PMU_STS_INT_32K_Msk
+/* ======================================================== WDTPASS ======================================================== */
+#define PMU_WDTPASS_UNLOCK_Pos (0UL) /*!< PMU WDTPASS: UNLOCK (Bit 0) */
+#define PMU_WDTPASS_UNLOCK_Msk (0x1UL) /*!< PMU WDTPASS: UNLOCK (Bitfield-Mask: 0x01) */
+#define PMU_WDTPASS_UNLOCK PMU_WDTPASS_UNLOCK_Msk
+/* ========================================================= WDTEN ========================================================= */
+#define PMU_WDTEN_WDTSEL_Pos (2UL) /*!< PMU WDTEN: WDTSEL (Bit 2) */
+#define PMU_WDTEN_WDTSEL_Msk (0xcUL) /*!< PMU WDTEN: WDTSEL (Bitfield-Mask: 0x03) */
+#define PMU_WDTEN_WDTSEL PMU_WDTEN_WDTSEL_Msk
+#define PMU_WDTEN_WDTEN_Pos (0UL) /*!< PMU WDTEN: WDTEN (Bit 0) */
+#define PMU_WDTEN_WDTEN_Msk (0x1UL) /*!< PMU WDTEN: WDTEN (Bitfield-Mask: 0x01) */
+#define PMU_WDTEN_WDTEN PMU_WDTEN_WDTEN_Msk
+/* ======================================================== WDTCLR ========================================================= */
+#define PMU_WDTCLR_WDTCNT_Pos (0UL) /*!< PMU WDTCLR: WDTCNT (Bit 0) */
+#define PMU_WDTCLR_WDTCNT_Msk (0xffffUL) /*!< PMU WDTCLR: WDTCNT (Bitfield-Mask: 0xffff) */
+#define PMU_WDTCLR_WDTCNT PMU_WDTCLR_WDTCNT_Msk
+/* ========================================================== RAM ========================================================== */
+#define PMU_RAM_RAM_Pos (0UL) /*!< PMU RAM: RAM (Bit 0) */
+#define PMU_RAM_RAM_Msk (0xffffffffUL) /*!< PMU RAM: RAM (Bitfield-Mask: 0xffffffff) */
+#define PMU_RAM_RAM PMU_RAM_RAM_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ PWM ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CTL ========================================================== */
+#define PWM_CTL_ID_Pos (6UL) /*!< PWM CTL: ID (Bit 6) */
+#define PWM_CTL_ID_Msk (0xc0UL) /*!< PWM CTL: ID (Bitfield-Mask: 0x03) */
+#define PWM_CTL_ID PWM_CTL_ID_Msk
+#define PWM_CTL_MC_Pos (4UL) /*!< PWM CTL: MC (Bit 4) */
+#define PWM_CTL_MC_Msk (0x30UL) /*!< PWM CTL: MC (Bitfield-Mask: 0x03) */
+#define PWM_CTL_MC PWM_CTL_MC_Msk
+#define PWM_CTL_TSEL_Pos (3UL) /*!< PWM CTL: TSEL (Bit 3) */
+#define PWM_CTL_TSEL_Msk (0x8UL) /*!< PWM CTL: TSEL (Bitfield-Mask: 0x01) */
+#define PWM_CTL_TSEL PWM_CTL_TSEL_Msk
+#define PWM_CTL_CLR_Pos (2UL) /*!< PWM CTL: CLR (Bit 2) */
+#define PWM_CTL_CLR_Msk (0x4UL) /*!< PWM CTL: CLR (Bitfield-Mask: 0x01) */
+#define PWM_CTL_CLR PWM_CTL_CLR_Msk
+#define PWM_CTL_IE_Pos (1UL) /*!< PWM CTL: IE (Bit 1) */
+#define PWM_CTL_IE_Msk (0x2UL) /*!< PWM CTL: IE (Bitfield-Mask: 0x01) */
+#define PWM_CTL_IE PWM_CTL_IE_Msk
+#define PWM_CTL_IFG_Pos (0UL) /*!< PWM CTL: IFG (Bit 0) */
+#define PWM_CTL_IFG_Msk (0x1UL) /*!< PWM CTL: IFG (Bitfield-Mask: 0x01) */
+#define PWM_CTL_IFG PWM_CTL_IFG_Msk
+/* ========================================================== TAR ========================================================== */
+#define PWM_TAR_TAR_Pos (0UL) /*!< PWM TAR: TAR (Bit 0) */
+#define PWM_TAR_TAR_Msk (0xffffUL) /*!< PWM TAR: TAR (Bitfield-Mask: 0xffff) */
+#define PWM_TAR_TAR PWM_TAR_TAR_Msk
+/* ========================================================= CCTL ========================================================== */
+#define PWM_CCTL_CM_Pos (14UL) /*!< PWM CCTL: CM (Bit 14) */
+#define PWM_CCTL_CM_Msk (0xc000UL) /*!< PWM CCTL: CM (Bitfield-Mask: 0x03) */
+#define PWM_CCTL_CM PWM_CCTL_CM_Msk
+#define PWM_CCTL_SCCI_Pos (10UL) /*!< PWM CCTL: SCCI (Bit 10) */
+#define PWM_CCTL_SCCI_Msk (0x400UL) /*!< PWM CCTL: SCCI (Bitfield-Mask: 0x01) */
+#define PWM_CCTL_SCCI PWM_CCTL_SCCI_Msk
+#define PWM_CCTL_OUTEN_Pos (9UL) /*!< PWM CCTL: OUTEN (Bit 9) */
+#define PWM_CCTL_OUTEN_Msk (0x200UL) /*!< PWM CCTL: OUTEN (Bitfield-Mask: 0x01) */
+#define PWM_CCTL_OUTEN PWM_CCTL_OUTEN_Msk
+#define PWM_CCTL_CAP_Pos (8UL) /*!< PWM CCTL: CAP (Bit 8) */
+#define PWM_CCTL_CAP_Msk (0x100UL) /*!< PWM CCTL: CAP (Bitfield-Mask: 0x01) */
+#define PWM_CCTL_CAP PWM_CCTL_CAP_Msk
+#define PWM_CCTL_OUTMOD_Pos (5UL) /*!< PWM CCTL: OUTMOD (Bit 5) */
+#define PWM_CCTL_OUTMOD_Msk (0xe0UL) /*!< PWM CCTL: OUTMOD (Bitfield-Mask: 0x07) */
+#define PWM_CCTL_OUTMOD PWM_CCTL_OUTMOD_Msk
+#define PWM_CCTL_CCIE_Pos (4UL) /*!< PWM CCTL: CCIE (Bit 4) */
+#define PWM_CCTL_CCIE_Msk (0x10UL) /*!< PWM CCTL: CCIE (Bitfield-Mask: 0x01) */
+#define PWM_CCTL_CCIE PWM_CCTL_CCIE_Msk
+#define PWM_CCTL_OUT_Pos (2UL) /*!< PWM CCTL: OUT (Bit 2) */
+#define PWM_CCTL_OUT_Msk (0x4UL) /*!< PWM CCTL: OUT (Bitfield-Mask: 0x01) */
+#define PWM_CCTL_OUT PWM_CCTL_OUT_Msk
+#define PWM_CCTL_COV_Pos (1UL) /*!< PWM CCTL: COV (Bit 1) */
+#define PWM_CCTL_COV_Msk (0x2UL) /*!< PWM CCTL: COV (Bitfield-Mask: 0x01) */
+#define PWM_CCTL_COV PWM_CCTL_COV_Msk
+#define PWM_CCTL_CCIFG_Pos (0UL) /*!< PWM CCTL: CCIFG (Bit 0) */
+#define PWM_CCTL_CCIFG_Msk (0x1UL) /*!< PWM CCTL: CCIFG (Bitfield-Mask: 0x01) */
+#define PWM_CCTL_CCIFG PWM_CCTL_CCIFG_Msk
+/* ========================================================== CCR ========================================================== */
+#define PWM_CCR_CCRx_Pos (0UL) /*!< PWM CCR: CCRx (Bit 0) */
+#define PWM_CCR_CCRx_Msk (0xffffUL) /*!< PWM CCR: CCRx (Bitfield-Mask: 0xffff) */
+#define PWM_CCR_CCRx PWM_CCR_CCRx_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ PWM_SEL ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= O_SEL ========================================================= */
+#define PWM_SEL_O_SEL_SEL3_Pos (12UL) /*!< PWM_SEL O_SEL: SEL3 (Bit 12) */
+#define PWM_SEL_O_SEL_SEL3_Msk (0xf000UL) /*!< PWM_SEL O_SEL: SEL3 (Bitfield-Mask: 0x0f) */
+#define PWM_SEL_O_SEL_SEL3 PWM_SEL_O_SEL_SEL3_Msk
+#define PWM_SEL_O_SEL_SEL2_Pos (8UL) /*!< PWM_SEL O_SEL: SEL2 (Bit 8) */
+#define PWM_SEL_O_SEL_SEL2_Msk (0xf00UL) /*!< PWM_SEL O_SEL: SEL2 (Bitfield-Mask: 0x0f) */
+#define PWM_SEL_O_SEL_SEL2 PWM_SEL_O_SEL_SEL2_Msk
+#define PWM_SEL_O_SEL_SEL1_Pos (4UL) /*!< PWM_SEL O_SEL: SEL1 (Bit 4) */
+#define PWM_SEL_O_SEL_SEL1_Msk (0xf0UL) /*!< PWM_SEL O_SEL: SEL1 (Bitfield-Mask: 0x0f) */
+#define PWM_SEL_O_SEL_SEL1 PWM_SEL_O_SEL_SEL1_Msk
+#define PWM_SEL_O_SEL_SEL0_Pos (0UL) /*!< PWM_SEL O_SEL: SEL0 (Bit 0) */
+#define PWM_SEL_O_SEL_SEL0_Msk (0xfUL) /*!< PWM_SEL O_SEL: SEL0 (Bitfield-Mask: 0x0f) */
+#define PWM_SEL_O_SEL_SEL0 PWM_SEL_O_SEL_SEL0_Msk
+/* ======================================================== I_SEL01 ======================================================== */
+#define PWM_SEL_I_SEL01_SEL12_Pos (20UL) /*!< PWM_SEL I_SEL01: SEL12 (Bit 20) */
+#define PWM_SEL_I_SEL01_SEL12_Msk (0x300000UL) /*!< PWM_SEL I_SEL01: SEL12 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL01_SEL12 PWM_SEL_I_SEL01_SEL12_Msk
+#define PWM_SEL_I_SEL01_SEL11_Pos (18UL) /*!< PWM_SEL I_SEL01: SEL11 (Bit 18) */
+#define PWM_SEL_I_SEL01_SEL11_Msk (0xc0000UL) /*!< PWM_SEL I_SEL01: SEL11 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL01_SEL11 PWM_SEL_I_SEL01_SEL11_Msk
+#define PWM_SEL_I_SEL01_SEL10_Pos (16UL) /*!< PWM_SEL I_SEL01: SEL10 (Bit 16) */
+#define PWM_SEL_I_SEL01_SEL10_Msk (0x30000UL) /*!< PWM_SEL I_SEL01: SEL10 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL01_SEL10 PWM_SEL_I_SEL01_SEL10_Msk
+#define PWM_SEL_I_SEL01_SEL02_Pos (4UL) /*!< PWM_SEL I_SEL01: SEL02 (Bit 4) */
+#define PWM_SEL_I_SEL01_SEL02_Msk (0x30UL) /*!< PWM_SEL I_SEL01: SEL02 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL01_SEL02 PWM_SEL_I_SEL01_SEL02_Msk
+#define PWM_SEL_I_SEL01_SEL01_Pos (2UL) /*!< PWM_SEL I_SEL01: SEL01 (Bit 2) */
+#define PWM_SEL_I_SEL01_SEL01_Msk (0xcUL) /*!< PWM_SEL I_SEL01: SEL01 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL01_SEL01 PWM_SEL_I_SEL01_SEL01_Msk
+#define PWM_SEL_I_SEL01_SEL00_Pos (0UL) /*!< PWM_SEL I_SEL01: SEL00 (Bit 0) */
+#define PWM_SEL_I_SEL01_SEL00_Msk (0x3UL) /*!< PWM_SEL I_SEL01: SEL00 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL01_SEL00 PWM_SEL_I_SEL01_SEL00_Msk
+/* ======================================================== I_SEL23 ======================================================== */
+#define PWM_SEL_I_SEL23_SEL32_Pos (20UL) /*!< PWM_SEL I_SEL23: SEL32 (Bit 20) */
+#define PWM_SEL_I_SEL23_SEL32_Msk (0x300000UL) /*!< PWM_SEL I_SEL23: SEL32 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL23_SEL32 PWM_SEL_I_SEL23_SEL32_Msk
+#define PWM_SEL_I_SEL23_SEL31_Pos (18UL) /*!< PWM_SEL I_SEL23: SEL31 (Bit 18) */
+#define PWM_SEL_I_SEL23_SEL31_Msk (0xc0000UL) /*!< PWM_SEL I_SEL23: SEL31 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL23_SEL31 PWM_SEL_I_SEL23_SEL31_Msk
+#define PWM_SEL_I_SEL23_SEL30_Pos (16UL) /*!< PWM_SEL I_SEL23: SEL30 (Bit 16) */
+#define PWM_SEL_I_SEL23_SEL30_Msk (0x30000UL) /*!< PWM_SEL I_SEL23: SEL30 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL23_SEL30 PWM_SEL_I_SEL23_SEL30_Msk
+#define PWM_SEL_I_SEL23_SEL22_Pos (4UL) /*!< PWM_SEL I_SEL23: SEL22 (Bit 4) */
+#define PWM_SEL_I_SEL23_SEL22_Msk (0x30UL) /*!< PWM_SEL I_SEL23: SEL22 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL23_SEL22 PWM_SEL_I_SEL23_SEL22_Msk
+#define PWM_SEL_I_SEL23_SEL21_Pos (2UL) /*!< PWM_SEL I_SEL23: SEL21 (Bit 2) */
+#define PWM_SEL_I_SEL23_SEL21_Msk (0xcUL) /*!< PWM_SEL I_SEL23: SEL21 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL23_SEL21 PWM_SEL_I_SEL23_SEL21_Msk
+#define PWM_SEL_I_SEL23_SEL20_Pos (0UL) /*!< PWM_SEL I_SEL23: SEL20 (Bit 0) */
+#define PWM_SEL_I_SEL23_SEL20_Msk (0x3UL) /*!< PWM_SEL I_SEL23: SEL20 (Bitfield-Mask: 0x03) */
+#define PWM_SEL_I_SEL23_SEL20 PWM_SEL_I_SEL23_SEL20_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ RTC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SEC ========================================================== */
+#define RTC_SEC_SEC_Pos (0UL) /*!< RTC SEC: SEC (Bit 0) */
+#define RTC_SEC_SEC_Msk (0x7fUL) /*!< RTC SEC: SEC (Bitfield-Mask: 0x7f) */
+#define RTC_SEC_SEC RTC_SEC_SEC_Msk
+/* ========================================================== MIN ========================================================== */
+#define RTC_MIN_MIN_Pos (0UL) /*!< RTC MIN: MIN (Bit 0) */
+#define RTC_MIN_MIN_Msk (0x7fUL) /*!< RTC MIN: MIN (Bitfield-Mask: 0x7f) */
+#define RTC_MIN_MIN RTC_MIN_MIN_Msk
+/* ========================================================= HOUR ========================================================== */
+#define RTC_HOUR_HOUR_Pos (0UL) /*!< RTC HOUR: HOUR (Bit 0) */
+#define RTC_HOUR_HOUR_Msk (0x3fUL) /*!< RTC HOUR: HOUR (Bitfield-Mask: 0x3f) */
+#define RTC_HOUR_HOUR RTC_HOUR_HOUR_Msk
+/* ========================================================== DAY ========================================================== */
+#define RTC_DAY_DAY_Pos (0UL) /*!< RTC DAY: DAY (Bit 0) */
+#define RTC_DAY_DAY_Msk (0x3fUL) /*!< RTC DAY: DAY (Bitfield-Mask: 0x3f) */
+#define RTC_DAY_DAY RTC_DAY_DAY_Msk
+/* ========================================================= WEEK ========================================================== */
+#define RTC_WEEK_WEEK_Pos (0UL) /*!< RTC WEEK: WEEK (Bit 0) */
+#define RTC_WEEK_WEEK_Msk (0x7UL) /*!< RTC WEEK: WEEK (Bitfield-Mask: 0x07) */
+#define RTC_WEEK_WEEK RTC_WEEK_WEEK_Msk
+/* ========================================================== MON ========================================================== */
+#define RTC_MON_MON_Pos (0UL) /*!< RTC MON: MON (Bit 0) */
+#define RTC_MON_MON_Msk (0x1fUL) /*!< RTC MON: MON (Bitfield-Mask: 0x1f) */
+#define RTC_MON_MON RTC_MON_MON_Msk
+/* ========================================================= YEAR ========================================================== */
+#define RTC_YEAR_YEAR_Pos (0UL) /*!< RTC YEAR: YEAR (Bit 0) */
+#define RTC_YEAR_YEAR_Msk (0xffUL) /*!< RTC YEAR: YEAR (Bitfield-Mask: 0xff) */
+#define RTC_YEAR_YEAR RTC_YEAR_YEAR_Msk
+/* ========================================================= TIME ========================================================== */
+#define RTC_TIME_TIME_Pos (0UL) /*!< RTC TIME: TIME (Bit 0) */
+#define RTC_TIME_TIME_Msk (0x3fffffUL) /*!< RTC TIME: TIME (Bitfield-Mask: 0x3fffff) */
+#define RTC_TIME_TIME RTC_TIME_TIME_Msk
+/* ======================================================== WKUSEC ========================================================= */
+#define RTC_WKUSEC_WKUSEC_Pos (0UL) /*!< RTC WKUSEC: WKUSEC (Bit 0) */
+#define RTC_WKUSEC_WKUSEC_Msk (0x3fUL) /*!< RTC WKUSEC: WKUSEC (Bitfield-Mask: 0x3f) */
+#define RTC_WKUSEC_WKUSEC RTC_WKUSEC_WKUSEC_Msk
+/* ======================================================== WKUMIN ========================================================= */
+#define RTC_WKUMIN_WKUMIN_Pos (0UL) /*!< RTC WKUMIN: WKUMIN (Bit 0) */
+#define RTC_WKUMIN_WKUMIN_Msk (0x3fUL) /*!< RTC WKUMIN: WKUMIN (Bitfield-Mask: 0x3f) */
+#define RTC_WKUMIN_WKUMIN RTC_WKUMIN_WKUMIN_Msk
+/* ======================================================== WKUHOUR ======================================================== */
+#define RTC_WKUHOUR_WKUHOUR_Pos (0UL) /*!< RTC WKUHOUR: WKUHOUR (Bit 0) */
+#define RTC_WKUHOUR_WKUHOUR_Msk (0x1fUL) /*!< RTC WKUHOUR: WKUHOUR (Bitfield-Mask: 0x1f) */
+#define RTC_WKUHOUR_WKUHOUR RTC_WKUHOUR_WKUHOUR_Msk
+/* ======================================================== WKUCNT ========================================================= */
+#define RTC_WKUCNT_CNTSEL_Pos (24UL) /*!< RTC WKUCNT: CNTSEL (Bit 24) */
+#define RTC_WKUCNT_CNTSEL_Msk (0x3000000UL) /*!< RTC WKUCNT: CNTSEL (Bitfield-Mask: 0x03) */
+#define RTC_WKUCNT_CNTSEL RTC_WKUCNT_CNTSEL_Msk
+#define RTC_WKUCNT_WKUCNT_Pos (0UL) /*!< RTC WKUCNT: WKUCNT (Bit 0) */
+#define RTC_WKUCNT_WKUCNT_Msk (0xffffffUL) /*!< RTC WKUCNT: WKUCNT (Bitfield-Mask: 0xffffff) */
+#define RTC_WKUCNT_WKUCNT RTC_WKUCNT_WKUCNT_Msk
+/* ========================================================== CAL ========================================================== */
+#define RTC_CAL_CAL_Pos (0UL) /*!< RTC CAL: CAL (Bit 0) */
+#define RTC_CAL_CAL_Msk (0x3fffUL) /*!< RTC CAL: CAL (Bitfield-Mask: 0x3fff) */
+#define RTC_CAL_CAL RTC_CAL_CAL_Msk
+/* ========================================================== DIV ========================================================== */
+#define RTC_DIV_RTCDIV_Pos (0UL) /*!< RTC DIV: RTCDIV (Bit 0) */
+#define RTC_DIV_RTCDIV_Msk (0x3ffffffUL) /*!< RTC DIV: RTCDIV (Bitfield-Mask: 0x3ffffff) */
+#define RTC_DIV_RTCDIV RTC_DIV_RTCDIV_Msk
+/* ========================================================== CTL ========================================================== */
+#define RTC_CTL_RTCPLLCLKSEL_Pos (4UL) /*!< RTC CTL: RTCPLLCLKSEL (Bit 4) */
+#define RTC_CTL_RTCPLLCLKSEL_Msk (0x10UL) /*!< RTC CTL: RTCPLLCLKSEL (Bitfield-Mask: 0x01) */
+#define RTC_CTL_RTCPLLCLKSEL RTC_CTL_RTCPLLCLKSEL_Msk
+#define RTC_CTL_RTCPLLOE_Pos (2UL) /*!< RTC CTL: RTCPLLOE (Bit 2) */
+#define RTC_CTL_RTCPLLOE_Msk (0x4UL) /*!< RTC CTL: RTCPLLOE (Bitfield-Mask: 0x01) */
+#define RTC_CTL_RTCPLLOE RTC_CTL_RTCPLLOE_Msk
+/* ========================================================== ITV ========================================================== */
+#define RTC_ITV_ITV_Pos (0UL) /*!< RTC ITV: ITV (Bit 0) */
+#define RTC_ITV_ITV_Msk (0x7UL) /*!< RTC ITV: ITV (Bitfield-Mask: 0x07) */
+#define RTC_ITV_ITV RTC_ITV_ITV_Msk
+/* ========================================================= SITV ========================================================== */
+#define RTC_SITV_SITVEN_Pos (6UL) /*!< RTC SITV: SITVEN (Bit 6) */
+#define RTC_SITV_SITVEN_Msk (0x40UL) /*!< RTC SITV: SITVEN (Bitfield-Mask: 0x01) */
+#define RTC_SITV_SITVEN RTC_SITV_SITVEN_Msk
+#define RTC_SITV_SITV_Pos (0UL) /*!< RTC SITV: SITV (Bit 0) */
+#define RTC_SITV_SITV_Msk (0x3fUL) /*!< RTC SITV: SITV (Bitfield-Mask: 0x3f) */
+#define RTC_SITV_SITV RTC_SITV_SITV_Msk
+/* ========================================================== PWD ========================================================== */
+#define RTC_PWD_PWDEN_Pos (0UL) /*!< RTC PWD: PWDEN (Bit 0) */
+#define RTC_PWD_PWDEN_Msk (0x1UL) /*!< RTC PWD: PWDEN (Bitfield-Mask: 0x01) */
+#define RTC_PWD_PWDEN RTC_PWD_PWDEN_Msk
+/* ========================================================== CE =========================================================== */
+#define RTC_CE_BSY_Pos (1UL) /*!< RTC CE: BSY (Bit 1) */
+#define RTC_CE_BSY_Msk (0x2UL) /*!< RTC CE: BSY (Bitfield-Mask: 0x01) */
+#define RTC_CE_BSY RTC_CE_BSY_Msk
+#define RTC_CE_CE_Pos (0UL) /*!< RTC CE: CE (Bit 0) */
+#define RTC_CE_CE_Msk (0x1UL) /*!< RTC CE: CE (Bitfield-Mask: 0x01) */
+#define RTC_CE_CE RTC_CE_CE_Msk
+/* ========================================================= LOAD ========================================================== */
+#define RTC_LOAD_LOAD_Pos (0UL) /*!< RTC LOAD: LOAD (Bit 0) */
+#define RTC_LOAD_LOAD_Msk (0xffffffffUL) /*!< RTC LOAD: LOAD (Bitfield-Mask: 0xffffffff) */
+#define RTC_LOAD_LOAD RTC_LOAD_LOAD_Msk
+/* ======================================================== INTSTS ========================================================= */
+#define RTC_INTSTS_INTSTS10_Pos (10UL) /*!< RTC INTSTS: INTSTS10 (Bit 10) */
+#define RTC_INTSTS_INTSTS10_Msk (0x400UL) /*!< RTC INTSTS: INTSTS10 (Bitfield-Mask: 0x01) */
+#define RTC_INTSTS_INTSTS10 RTC_INTSTS_INTSTS10_Msk
+#define RTC_INTSTS_INTSTS8_Pos (8UL) /*!< RTC INTSTS: INTSTS8 (Bit 8) */
+#define RTC_INTSTS_INTSTS8_Msk (0x100UL) /*!< RTC INTSTS: INTSTS8 (Bitfield-Mask: 0x01) */
+#define RTC_INTSTS_INTSTS8 RTC_INTSTS_INTSTS8_Msk
+#define RTC_INTSTS_INTSTS6_Pos (6UL) /*!< RTC INTSTS: INTSTS6 (Bit 6) */
+#define RTC_INTSTS_INTSTS6_Msk (0x40UL) /*!< RTC INTSTS: INTSTS6 (Bitfield-Mask: 0x01) */
+#define RTC_INTSTS_INTSTS6 RTC_INTSTS_INTSTS6_Msk
+#define RTC_INTSTS_INTSTS5_Pos (5UL) /*!< RTC INTSTS: INTSTS5 (Bit 5) */
+#define RTC_INTSTS_INTSTS5_Msk (0x20UL) /*!< RTC INTSTS: INTSTS5 (Bitfield-Mask: 0x01) */
+#define RTC_INTSTS_INTSTS5 RTC_INTSTS_INTSTS5_Msk
+#define RTC_INTSTS_INTSTS4_Pos (4UL) /*!< RTC INTSTS: INTSTS4 (Bit 4) */
+#define RTC_INTSTS_INTSTS4_Msk (0x10UL) /*!< RTC INTSTS: INTSTS4 (Bitfield-Mask: 0x01) */
+#define RTC_INTSTS_INTSTS4 RTC_INTSTS_INTSTS4_Msk
+#define RTC_INTSTS_INTSTS3_Pos (3UL) /*!< RTC INTSTS: INTSTS3 (Bit 3) */
+#define RTC_INTSTS_INTSTS3_Msk (0x8UL) /*!< RTC INTSTS: INTSTS3 (Bitfield-Mask: 0x01) */
+#define RTC_INTSTS_INTSTS3 RTC_INTSTS_INTSTS3_Msk
+#define RTC_INTSTS_INTSTS2_Pos (2UL) /*!< RTC INTSTS: INTSTS2 (Bit 2) */
+#define RTC_INTSTS_INTSTS2_Msk (0x4UL) /*!< RTC INTSTS: INTSTS2 (Bitfield-Mask: 0x01) */
+#define RTC_INTSTS_INTSTS2 RTC_INTSTS_INTSTS2_Msk
+#define RTC_INTSTS_INTSTS1_Pos (1UL) /*!< RTC INTSTS: INTSTS1 (Bit 1) */
+#define RTC_INTSTS_INTSTS1_Msk (0x2UL) /*!< RTC INTSTS: INTSTS1 (Bitfield-Mask: 0x01) */
+#define RTC_INTSTS_INTSTS1 RTC_INTSTS_INTSTS1_Msk
+#define RTC_INTSTS_INTSTS0_Pos (0UL) /*!< RTC INTSTS: INTSTS0 (Bit 0) */
+#define RTC_INTSTS_INTSTS0_Msk (0x1UL) /*!< RTC INTSTS: INTSTS0 (Bitfield-Mask: 0x01) */
+#define RTC_INTSTS_INTSTS0 RTC_INTSTS_INTSTS0_Msk
+/* ========================================================= INTEN ========================================================= */
+#define RTC_INTEN_INTEN10_Pos (10UL) /*!< RTC INTEN: INTEN10 (Bit 10) */
+#define RTC_INTEN_INTEN10_Msk (0x400UL) /*!< RTC INTEN: INTEN10 (Bitfield-Mask: 0x01) */
+#define RTC_INTEN_INTEN10 RTC_INTEN_INTEN10_Msk
+#define RTC_INTEN_INTEN8_Pos (8UL) /*!< RTC INTEN: INTEN8 (Bit 8) */
+#define RTC_INTEN_INTEN8_Msk (0x100UL) /*!< RTC INTEN: INTEN8 (Bitfield-Mask: 0x01) */
+#define RTC_INTEN_INTEN8 RTC_INTEN_INTEN8_Msk
+#define RTC_INTEN_INTEN6_Pos (6UL) /*!< RTC INTEN: INTEN6 (Bit 6) */
+#define RTC_INTEN_INTEN6_Msk (0x40UL) /*!< RTC INTEN: INTEN6 (Bitfield-Mask: 0x01) */
+#define RTC_INTEN_INTEN6 RTC_INTEN_INTEN6_Msk
+#define RTC_INTEN_INTEN5_Pos (5UL) /*!< RTC INTEN: INTEN5 (Bit 5) */
+#define RTC_INTEN_INTEN5_Msk (0x20UL) /*!< RTC INTEN: INTEN5 (Bitfield-Mask: 0x01) */
+#define RTC_INTEN_INTEN5 RTC_INTEN_INTEN5_Msk
+#define RTC_INTEN_INTEN4_Pos (4UL) /*!< RTC INTEN: INTEN4 (Bit 4) */
+#define RTC_INTEN_INTEN4_Msk (0x10UL) /*!< RTC INTEN: INTEN4 (Bitfield-Mask: 0x01) */
+#define RTC_INTEN_INTEN4 RTC_INTEN_INTEN4_Msk
+#define RTC_INTEN_INTRN3_Pos (3UL) /*!< RTC INTEN: INTRN3 (Bit 3) */
+#define RTC_INTEN_INTRN3_Msk (0x8UL) /*!< RTC INTEN: INTRN3 (Bitfield-Mask: 0x01) */
+#define RTC_INTEN_INTRN3 RTC_INTEN_INTRN3_Msk
+#define RTC_INTEN_INTEN2_Pos (2UL) /*!< RTC INTEN: INTEN2 (Bit 2) */
+#define RTC_INTEN_INTEN2_Msk (0x4UL) /*!< RTC INTEN: INTEN2 (Bitfield-Mask: 0x01) */
+#define RTC_INTEN_INTEN2 RTC_INTEN_INTEN2_Msk
+#define RTC_INTEN_INTEN1_Pos (1UL) /*!< RTC INTEN: INTEN1 (Bit 1) */
+#define RTC_INTEN_INTEN1_Msk (0x2UL) /*!< RTC INTEN: INTEN1 (Bitfield-Mask: 0x01) */
+#define RTC_INTEN_INTEN1 RTC_INTEN_INTEN1_Msk
+#define RTC_INTEN_INTEN0_Pos (0UL) /*!< RTC INTEN: INTEN0 (Bit 0) */
+#define RTC_INTEN_INTEN0_Msk (0x1UL) /*!< RTC INTEN: INTEN0 (Bitfield-Mask: 0x01) */
+#define RTC_INTEN_INTEN0 RTC_INTEN_INTEN0_Msk
+/* ========================================================= PSCA ========================================================== */
+#define RTC_PSCA_PSCA_Pos (0UL) /*!< RTC PSCA: PSCA (Bit 0) */
+#define RTC_PSCA_PSCA_Msk (0x3UL) /*!< RTC PSCA: PSCA (Bitfield-Mask: 0x03) */
+#define RTC_PSCA_PSCA RTC_PSCA_PSCA_Msk
+/* ========================================================= ACTI ========================================================== */
+#define RTC_ACTI_ACTI_Pos (0UL) /*!< RTC ACTI: ACTI (Bit 0) */
+#define RTC_ACTI_ACTI_Msk (0x3fffUL) /*!< RTC ACTI: ACTI (Bitfield-Mask: 0x3fff) */
+#define RTC_ACTI_ACTI RTC_ACTI_ACTI_Msk
+/* ======================================================== ACF200 ========================================================= */
+#define RTC_ACF200_F200_Pos (0UL) /*!< RTC ACF200: F200 (Bit 0) */
+#define RTC_ACF200_F200_Msk (0x3ffffffUL) /*!< RTC ACF200: F200 (Bitfield-Mask: 0x3ffffff) */
+#define RTC_ACF200_F200 RTC_ACF200_F200_Msk
+/* ========================================================= ACP0 ========================================================== */
+#define RTC_ACP0_P0_Pos (0UL) /*!< RTC ACP0: P0 (Bit 0) */
+#define RTC_ACP0_P0_Msk (0xffffUL) /*!< RTC ACP0: P0 (Bitfield-Mask: 0xffff) */
+#define RTC_ACP0_P0 RTC_ACP0_P0_Msk
+/* ========================================================= ACP1 ========================================================== */
+#define RTC_ACP1_P1_Pos (0UL) /*!< RTC ACP1: P1 (Bit 0) */
+#define RTC_ACP1_P1_Msk (0xffffUL) /*!< RTC ACP1: P1 (Bitfield-Mask: 0xffff) */
+#define RTC_ACP1_P1 RTC_ACP1_P1_Msk
+/* ========================================================= ACP2 ========================================================== */
+#define RTC_ACP2_P2_Pos (0UL) /*!< RTC ACP2: P2 (Bit 0) */
+#define RTC_ACP2_P2_Msk (0xffffffffUL) /*!< RTC ACP2: P2 (Bitfield-Mask: 0xffffffff) */
+#define RTC_ACP2_P2 RTC_ACP2_P2_Msk
+/* ========================================================= ACP3 ========================================================== */
+#define RTC_ACP3_P3_Pos (0UL) /*!< RTC ACP3: P3 (Bit 0) */
+#define RTC_ACP3_P3_Msk (0xffffffffUL) /*!< RTC ACP3: P3 (Bitfield-Mask: 0xffffffff) */
+#define RTC_ACP3_P3 RTC_ACP3_P3_Msk
+/* ========================================================= ACP4 ========================================================== */
+#define RTC_ACP4_P4_Pos (0UL) /*!< RTC ACP4: P4 (Bit 0) */
+#define RTC_ACP4_P4_Msk (0xffffUL) /*!< RTC ACP4: P4 (Bitfield-Mask: 0xffff) */
+#define RTC_ACP4_P4 RTC_ACP4_P4_Msk
+/* ========================================================= ACP5 ========================================================== */
+#define RTC_ACP5_P5_Pos (0UL) /*!< RTC ACP5: P5 (Bit 0) */
+#define RTC_ACP5_P5_Msk (0xffffUL) /*!< RTC ACP5: P5 (Bitfield-Mask: 0xffff) */
+#define RTC_ACP5_P5 RTC_ACP5_P5_Msk
+/* ========================================================= ACP6 ========================================================== */
+#define RTC_ACP6_P6_Pos (0UL) /*!< RTC ACP6: P6 (Bit 0) */
+#define RTC_ACP6_P6_Msk (0xffffUL) /*!< RTC ACP6: P6 (Bitfield-Mask: 0xffff) */
+#define RTC_ACP6_P6 RTC_ACP6_P6_Msk
+/* ========================================================= ACP7 ========================================================== */
+#define RTC_ACP7_P7_Pos (0UL) /*!< RTC ACP7: P7 (Bit 0) */
+#define RTC_ACP7_P7_Msk (0xffffUL) /*!< RTC ACP7: P7 (Bitfield-Mask: 0xffff) */
+#define RTC_ACP7_P7 RTC_ACP7_P7_Msk
+/* ========================================================== ACK ========================================================== */
+#define RTC_ACK_K_Pos (0UL) /*!< RTC ACK: K (Bit 0) */
+#define RTC_ACK_K_Msk (0xffffUL) /*!< RTC ACK: K (Bitfield-Mask: 0xffff) */
+#define RTC_ACK_K RTC_ACK_K_Msk
+/* ======================================================== WKUCNTR ======================================================== */
+#define RTC_WKUCNTR_WKUCNTR_Pos (0UL) /*!< RTC WKUCNTR: WKUCNTR (Bit 0) */
+#define RTC_WKUCNTR_WKUCNTR_Msk (0xffffffUL) /*!< RTC WKUCNTR: WKUCNTR (Bitfield-Mask: 0xffffff) */
+#define RTC_WKUCNTR_WKUCNTR RTC_WKUCNTR_WKUCNTR_Msk
+/* ======================================================== ACKTEMP ======================================================== */
+#define RTC_ACKTEMP_KTEMP4_Pos (24UL) /*!< RTC ACKTEMP: KTEMP4 (Bit 24) */
+#define RTC_ACKTEMP_KTEMP4_Msk (0xff000000UL) /*!< RTC ACKTEMP: KTEMP4 (Bitfield-Mask: 0xff) */
+#define RTC_ACKTEMP_KTEMP4 RTC_ACKTEMP_KTEMP4_Msk
+#define RTC_ACKTEMP_KTEMP3_Pos (16UL) /*!< RTC ACKTEMP: KTEMP3 (Bit 16) */
+#define RTC_ACKTEMP_KTEMP3_Msk (0xff0000UL) /*!< RTC ACKTEMP: KTEMP3 (Bitfield-Mask: 0xff) */
+#define RTC_ACKTEMP_KTEMP3 RTC_ACKTEMP_KTEMP3_Msk
+#define RTC_ACKTEMP_KTEMP2_Pos (8UL) /*!< RTC ACKTEMP: KTEMP2 (Bit 8) */
+#define RTC_ACKTEMP_KTEMP2_Msk (0xff00UL) /*!< RTC ACKTEMP: KTEMP2 (Bitfield-Mask: 0xff) */
+#define RTC_ACKTEMP_KTEMP2 RTC_ACKTEMP_KTEMP2_Msk
+#define RTC_ACKTEMP_KTEMP1_Pos (0UL) /*!< RTC ACKTEMP: KTEMP1 (Bit 0) */
+#define RTC_ACKTEMP_KTEMP1_Msk (0xffUL) /*!< RTC ACKTEMP: KTEMP1 (Bitfield-Mask: 0xff) */
+#define RTC_ACKTEMP_KTEMP1 RTC_ACKTEMP_KTEMP1_Msk
+/* ======================================================= ALARMTIME ======================================================= */
+#define RTC_ALARMTIME_ALARMTIME_Pos (0UL) /*!< RTC ALARMTIME: ALARMTIME (Bit 0) */
+#define RTC_ALARMTIME_ALARMTIME_Msk (0x3fffffUL) /*!< RTC ALARMTIME: ALARMTIME (Bitfield-Mask: 0x3fffff) */
+#define RTC_ALARMTIME_ALARMTIME RTC_ALARMTIME_ALARMTIME_Msk
+/* ======================================================= ALARMSEC ======================================================== */
+#define RTC_ALARMSEC_ALARMSEC_Pos (0UL) /*!< RTC ALARMSEC: ALARMSEC (Bit 0) */
+#define RTC_ALARMSEC_ALARMSEC_Msk (0x7fUL) /*!< RTC ALARMSEC: ALARMSEC (Bitfield-Mask: 0x7f) */
+#define RTC_ALARMSEC_ALARMSEC RTC_ALARMSEC_ALARMSEC_Msk
+/* ======================================================= ALARMMIN ======================================================== */
+#define RTC_ALARMMIN_ALARMMIN_Pos (0UL) /*!< RTC ALARMMIN: ALARMMIN (Bit 0) */
+#define RTC_ALARMMIN_ALARMMIN_Msk (0x7fUL) /*!< RTC ALARMMIN: ALARMMIN (Bitfield-Mask: 0x7f) */
+#define RTC_ALARMMIN_ALARMMIN RTC_ALARMMIN_ALARMMIN_Msk
+/* ======================================================= ALARMHOUR ======================================================= */
+#define RTC_ALARMHOUR_ALARMHOUR_Pos (0UL) /*!< RTC ALARMHOUR: ALARMHOUR (Bit 0) */
+#define RTC_ALARMHOUR_ALARMHOUR_Msk (0x3fUL) /*!< RTC ALARMHOUR: ALARMHOUR (Bitfield-Mask: 0x3f) */
+#define RTC_ALARMHOUR_ALARMHOUR RTC_ALARMHOUR_ALARMHOUR_Msk
+/* ======================================================= ALARMCTL ======================================================== */
+#define RTC_ALARMCTL_TIME_CNT_EN_Pos (2UL) /*!< RTC ALARMCTL: TIME_CNT_EN (Bit 2) */
+#define RTC_ALARMCTL_TIME_CNT_EN_Msk (0x4UL) /*!< RTC ALARMCTL: TIME_CNT_EN (Bitfield-Mask: 0x01) */
+#define RTC_ALARMCTL_TIME_CNT_EN RTC_ALARMCTL_TIME_CNT_EN_Msk
+#define RTC_ALARMCTL_ALARM_INACCURATE_Pos (1UL) /*!< RTC ALARMCTL: ALARM_INACCURATE (Bit 1) */
+#define RTC_ALARMCTL_ALARM_INACCURATE_Msk (0x2UL) /*!< RTC ALARMCTL: ALARM_INACCURATE (Bitfield-Mask: 0x01) */
+#define RTC_ALARMCTL_ALARM_INACCURATE RTC_ALARMCTL_ALARM_INACCURATE_Msk
+#define RTC_ALARMCTL_ALARM_EN_Pos (0UL) /*!< RTC ALARMCTL: ALARM_EN (Bit 0) */
+#define RTC_ALARMCTL_ALARM_EN_Msk (0x1UL) /*!< RTC ALARMCTL: ALARM_EN (Bitfield-Mask: 0x01) */
+#define RTC_ALARMCTL_ALARM_EN RTC_ALARMCTL_ALARM_EN_Msk
+/* ======================================================= ADCUCALK ======================================================== */
+#define RTC_ADCUCALK_UCAL_K3_Pos (16UL) /*!< RTC ADCUCALK: UCAL_K3 (Bit 16) */
+#define RTC_ADCUCALK_UCAL_K3_Msk (0xffff0000UL) /*!< RTC ADCUCALK: UCAL_K3 (Bitfield-Mask: 0xffff) */
+#define RTC_ADCUCALK_UCAL_K3 RTC_ADCUCALK_UCAL_K3_Msk
+#define RTC_ADCUCALK_UCAL_K1_Pos (0UL) /*!< RTC ADCUCALK: UCAL_K1 (Bit 0) */
+#define RTC_ADCUCALK_UCAL_K1_Msk (0xffffUL) /*!< RTC ADCUCALK: UCAL_K1 (Bitfield-Mask: 0xffff) */
+#define RTC_ADCUCALK_UCAL_K1 RTC_ADCUCALK_UCAL_K1_Msk
+/* ======================================================= ADCMACTL ======================================================== */
+#define RTC_ADCMACTL_ADCSREF_CAL_Pos (24UL) /*!< RTC ADCMACTL: ADCSREF_CAL (Bit 24) */
+#define RTC_ADCMACTL_ADCSREF_CAL_Msk (0x7000000UL) /*!< RTC ADCMACTL: ADCSREF_CAL (Bitfield-Mask: 0x07) */
+#define RTC_ADCMACTL_ADCSREF_CAL RTC_ADCMACTL_ADCSREF_CAL_Msk
+#define RTC_ADCMACTL_SKIP_SAMPLE_Pos (20UL) /*!< RTC ADCMACTL: SKIP_SAMPLE (Bit 20) */
+#define RTC_ADCMACTL_SKIP_SAMPLE_Msk (0xf00000UL) /*!< RTC ADCMACTL: SKIP_SAMPLE (Bitfield-Mask: 0x0f) */
+#define RTC_ADCMACTL_SKIP_SAMPLE RTC_ADCMACTL_SKIP_SAMPLE_Msk
+#define RTC_ADCMACTL_AVERAGE_SAMPLE_Pos (16UL) /*!< RTC ADCMACTL: AVERAGE_SAMPLE (Bit 16) */
+#define RTC_ADCMACTL_AVERAGE_SAMPLE_Msk (0x70000UL) /*!< RTC ADCMACTL: AVERAGE_SAMPLE (Bitfield-Mask: 0x07) */
+#define RTC_ADCMACTL_AVERAGE_SAMPLE RTC_ADCMACTL_AVERAGE_SAMPLE_Msk
+#define RTC_ADCMACTL_AVERAGE_CHx_Pos (0UL) /*!< RTC ADCMACTL: AVERAGE_CHx (Bit 0) */
+#define RTC_ADCMACTL_AVERAGE_CHx_Msk (0xffffUL) /*!< RTC ADCMACTL: AVERAGE_CHx (Bitfield-Mask: 0xffff) */
+#define RTC_ADCMACTL_AVERAGE_CHx RTC_ADCMACTL_AVERAGE_CHx_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ SPI ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CTRL ========================================================== */
+#define SPI_CTRL_EN_Pos (15UL) /*!< SPI CTRL: EN (Bit 15) */
+#define SPI_CTRL_EN_Msk (0x8000UL) /*!< SPI CTRL: EN (Bitfield-Mask: 0x01) */
+#define SPI_CTRL_EN SPI_CTRL_EN_Msk
+#define SPI_CTRL_LSBF_Pos (12UL) /*!< SPI CTRL: LSBF (Bit 12) */
+#define SPI_CTRL_LSBF_Msk (0x1000UL) /*!< SPI CTRL: LSBF (Bitfield-Mask: 0x01) */
+#define SPI_CTRL_LSBF SPI_CTRL_LSBF_Msk
+#define SPI_CTRL_RST_Pos (11UL) /*!< SPI CTRL: RST (Bit 11) */
+#define SPI_CTRL_RST_Msk (0x800UL) /*!< SPI CTRL: RST (Bitfield-Mask: 0x01) */
+#define SPI_CTRL_RST SPI_CTRL_RST_Msk
+#define SPI_CTRL_CSGPIO_Pos (10UL) /*!< SPI CTRL: CSGPIO (Bit 10) */
+#define SPI_CTRL_CSGPIO_Msk (0x400UL) /*!< SPI CTRL: CSGPIO (Bitfield-Mask: 0x01) */
+#define SPI_CTRL_CSGPIO SPI_CTRL_CSGPIO_Msk
+#define SPI_CTRL_SWAP_Pos (9UL) /*!< SPI CTRL: SWAP (Bit 9) */
+#define SPI_CTRL_SWAP_Msk (0x200UL) /*!< SPI CTRL: SWAP (Bitfield-Mask: 0x01) */
+#define SPI_CTRL_SWAP SPI_CTRL_SWAP_Msk
+#define SPI_CTRL_MOD_Pos (8UL) /*!< SPI CTRL: MOD (Bit 8) */
+#define SPI_CTRL_MOD_Msk (0x100UL) /*!< SPI CTRL: MOD (Bitfield-Mask: 0x01) */
+#define SPI_CTRL_MOD SPI_CTRL_MOD_Msk
+#define SPI_CTRL_SCKPHA_Pos (5UL) /*!< SPI CTRL: SCKPHA (Bit 5) */
+#define SPI_CTRL_SCKPHA_Msk (0x20UL) /*!< SPI CTRL: SCKPHA (Bitfield-Mask: 0x01) */
+#define SPI_CTRL_SCKPHA SPI_CTRL_SCKPHA_Msk
+#define SPI_CTRL_SCKPOL_Pos (4UL) /*!< SPI CTRL: SCKPOL (Bit 4) */
+#define SPI_CTRL_SCKPOL_Msk (0x10UL) /*!< SPI CTRL: SCKPOL (Bitfield-Mask: 0x01) */
+#define SPI_CTRL_SCKPOL SPI_CTRL_SCKPOL_Msk
+#define SPI_CTRL_SCKSEL_Pos (0UL) /*!< SPI CTRL: SCKSEL (Bit 0) */
+#define SPI_CTRL_SCKSEL_Msk (0x7UL) /*!< SPI CTRL: SCKSEL (Bitfield-Mask: 0x07) */
+#define SPI_CTRL_SCKSEL SPI_CTRL_SCKSEL_Msk
+/* ========================================================= TXSTS ========================================================= */
+#define SPI_TXSTS_TXIF_Pos (15UL) /*!< SPI TXSTS: TXIF (Bit 15) */
+#define SPI_TXSTS_TXIF_Msk (0x8000UL) /*!< SPI TXSTS: TXIF (Bitfield-Mask: 0x01) */
+#define SPI_TXSTS_TXIF SPI_TXSTS_TXIF_Msk
+#define SPI_TXSTS_TXIEN_Pos (14UL) /*!< SPI TXSTS: TXIEN (Bit 14) */
+#define SPI_TXSTS_TXIEN_Msk (0x4000UL) /*!< SPI TXSTS: TXIEN (Bitfield-Mask: 0x01) */
+#define SPI_TXSTS_TXIEN SPI_TXSTS_TXIEN_Msk
+#define SPI_TXSTS_TXEMPTY_Pos (9UL) /*!< SPI TXSTS: TXEMPTY (Bit 9) */
+#define SPI_TXSTS_TXEMPTY_Msk (0x200UL) /*!< SPI TXSTS: TXEMPTY (Bitfield-Mask: 0x01) */
+#define SPI_TXSTS_TXEMPTY SPI_TXSTS_TXEMPTY_Msk
+#define SPI_TXSTS_TXFUR_Pos (8UL) /*!< SPI TXSTS: TXFUR (Bit 8) */
+#define SPI_TXSTS_TXFUR_Msk (0x100UL) /*!< SPI TXSTS: TXFUR (Bitfield-Mask: 0x01) */
+#define SPI_TXSTS_TXFUR SPI_TXSTS_TXFUR_Msk
+#define SPI_TXSTS_TXFLEV_Pos (4UL) /*!< SPI TXSTS: TXFLEV (Bit 4) */
+#define SPI_TXSTS_TXFLEV_Msk (0x70UL) /*!< SPI TXSTS: TXFLEV (Bitfield-Mask: 0x07) */
+#define SPI_TXSTS_TXFLEV SPI_TXSTS_TXFLEV_Msk
+#define SPI_TXSTS_DMATXDONE_Pos (3UL) /*!< SPI TXSTS: DMATXDONE (Bit 3) */
+#define SPI_TXSTS_DMATXDONE_Msk (0x8UL) /*!< SPI TXSTS: DMATXDONE (Bitfield-Mask: 0x01) */
+#define SPI_TXSTS_DMATXDONE SPI_TXSTS_DMATXDONE_Msk
+#define SPI_TXSTS_TXFFLAG_Pos (0UL) /*!< SPI TXSTS: TXFFLAG (Bit 0) */
+#define SPI_TXSTS_TXFFLAG_Msk (0x7UL) /*!< SPI TXSTS: TXFFLAG (Bitfield-Mask: 0x07) */
+#define SPI_TXSTS_TXFFLAG SPI_TXSTS_TXFFLAG_Msk
+/* ========================================================= TXDAT ========================================================= */
+#define SPI_TXDAT_TXD_Pos (0UL) /*!< SPI TXDAT: TXD (Bit 0) */
+#define SPI_TXDAT_TXD_Msk (0xffUL) /*!< SPI TXDAT: TXD (Bitfield-Mask: 0xff) */
+#define SPI_TXDAT_TXD SPI_TXDAT_TXD_Msk
+/* ========================================================= RXSTS ========================================================= */
+#define SPI_RXSTS_RXIF_Pos (15UL) /*!< SPI RXSTS: RXIF (Bit 15) */
+#define SPI_RXSTS_RXIF_Msk (0x8000UL) /*!< SPI RXSTS: RXIF (Bitfield-Mask: 0x01) */
+#define SPI_RXSTS_RXIF SPI_RXSTS_RXIF_Msk
+#define SPI_RXSTS_RXIEN_Pos (14UL) /*!< SPI RXSTS: RXIEN (Bit 14) */
+#define SPI_RXSTS_RXIEN_Msk (0x4000UL) /*!< SPI RXSTS: RXIEN (Bitfield-Mask: 0x01) */
+#define SPI_RXSTS_RXIEN SPI_RXSTS_RXIEN_Msk
+#define SPI_RXSTS_RXFULL_Pos (9UL) /*!< SPI RXSTS: RXFULL (Bit 9) */
+#define SPI_RXSTS_RXFULL_Msk (0x200UL) /*!< SPI RXSTS: RXFULL (Bitfield-Mask: 0x01) */
+#define SPI_RXSTS_RXFULL SPI_RXSTS_RXFULL_Msk
+#define SPI_RXSTS_RXFOV_Pos (8UL) /*!< SPI RXSTS: RXFOV (Bit 8) */
+#define SPI_RXSTS_RXFOV_Msk (0x100UL) /*!< SPI RXSTS: RXFOV (Bitfield-Mask: 0x01) */
+#define SPI_RXSTS_RXFOV SPI_RXSTS_RXFOV_Msk
+#define SPI_RXSTS_RXFLEV_Pos (4UL) /*!< SPI RXSTS: RXFLEV (Bit 4) */
+#define SPI_RXSTS_RXFLEV_Msk (0x70UL) /*!< SPI RXSTS: RXFLEV (Bitfield-Mask: 0x07) */
+#define SPI_RXSTS_RXFLEV SPI_RXSTS_RXFLEV_Msk
+#define SPI_RXSTS_RXFFLAG_Pos (0UL) /*!< SPI RXSTS: RXFFLAG (Bit 0) */
+#define SPI_RXSTS_RXFFLAG_Msk (0x7UL) /*!< SPI RXSTS: RXFFLAG (Bitfield-Mask: 0x07) */
+#define SPI_RXSTS_RXFFLAG SPI_RXSTS_RXFFLAG_Msk
+/* ========================================================= RXDAT ========================================================= */
+#define SPI_RXDAT_RXD_Pos (0UL) /*!< SPI RXDAT: RXD (Bit 0) */
+#define SPI_RXDAT_RXD_Msk (0xffUL) /*!< SPI RXDAT: RXD (Bitfield-Mask: 0xff) */
+#define SPI_RXDAT_RXD SPI_RXDAT_RXD_Msk
+/* ========================================================= MISC ========================================================== */
+#define SPI_MISC_OVER_Pos (9UL) /*!< SPI MISC: OVER (Bit 9) */
+#define SPI_MISC_OVER_Msk (0x200UL) /*!< SPI MISC: OVER (Bitfield-Mask: 0x01) */
+#define SPI_MISC_OVER SPI_MISC_OVER_Msk
+#define SPI_MISC_SMART_Pos (8UL) /*!< SPI MISC: SMART (Bit 8) */
+#define SPI_MISC_SMART_Msk (0x100UL) /*!< SPI MISC: SMART (Bitfield-Mask: 0x01) */
+#define SPI_MISC_SMART SPI_MISC_SMART_Msk
+#define SPI_MISC_BSY_Pos (4UL) /*!< SPI MISC: BSY (Bit 4) */
+#define SPI_MISC_BSY_Msk (0x10UL) /*!< SPI MISC: BSY (Bitfield-Mask: 0x01) */
+#define SPI_MISC_BSY SPI_MISC_BSY_Msk
+#define SPI_MISC_RFF_Pos (3UL) /*!< SPI MISC: RFF (Bit 3) */
+#define SPI_MISC_RFF_Msk (0x8UL) /*!< SPI MISC: RFF (Bitfield-Mask: 0x01) */
+#define SPI_MISC_RFF SPI_MISC_RFF_Msk
+#define SPI_MISC_RNE_Pos (2UL) /*!< SPI MISC: RNE (Bit 2) */
+#define SPI_MISC_RNE_Msk (0x4UL) /*!< SPI MISC: RNE (Bitfield-Mask: 0x01) */
+#define SPI_MISC_RNE SPI_MISC_RNE_Msk
+#define SPI_MISC_TNF_Pos (1UL) /*!< SPI MISC: TNF (Bit 1) */
+#define SPI_MISC_TNF_Msk (0x2UL) /*!< SPI MISC: TNF (Bitfield-Mask: 0x01) */
+#define SPI_MISC_TNF SPI_MISC_TNF_Msk
+#define SPI_MISC_TFE_Pos (0UL) /*!< SPI MISC: TFE (Bit 0) */
+#define SPI_MISC_TFE_Msk (0x1UL) /*!< SPI MISC: TFE (Bitfield-Mask: 0x01) */
+#define SPI_MISC_TFE SPI_MISC_TFE_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ TMR ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CTRL ========================================================== */
+#define TMR_CTRL_INTEN_Pos (3UL) /*!< TMR CTRL: INTEN (Bit 3) */
+#define TMR_CTRL_INTEN_Msk (0x8UL) /*!< TMR CTRL: INTEN (Bitfield-Mask: 0x01) */
+#define TMR_CTRL_INTEN TMR_CTRL_INTEN_Msk
+#define TMR_CTRL_EXTCLK_Pos (2UL) /*!< TMR CTRL: EXTCLK (Bit 2) */
+#define TMR_CTRL_EXTCLK_Msk (0x4UL) /*!< TMR CTRL: EXTCLK (Bitfield-Mask: 0x01) */
+#define TMR_CTRL_EXTCLK TMR_CTRL_EXTCLK_Msk
+#define TMR_CTRL_EXTEN_Pos (1UL) /*!< TMR CTRL: EXTEN (Bit 1) */
+#define TMR_CTRL_EXTEN_Msk (0x2UL) /*!< TMR CTRL: EXTEN (Bitfield-Mask: 0x01) */
+#define TMR_CTRL_EXTEN TMR_CTRL_EXTEN_Msk
+#define TMR_CTRL_EN_Pos (0UL) /*!< TMR CTRL: EN (Bit 0) */
+#define TMR_CTRL_EN_Msk (0x1UL) /*!< TMR CTRL: EN (Bitfield-Mask: 0x01) */
+#define TMR_CTRL_EN TMR_CTRL_EN_Msk
+/* ========================================================= VALUE ========================================================= */
+#define TMR_VALUE_VALUE_Pos (0UL) /*!< TMR VALUE: VALUE (Bit 0) */
+#define TMR_VALUE_VALUE_Msk (0xffffffffUL) /*!< TMR VALUE: VALUE (Bitfield-Mask: 0xffffffff) */
+#define TMR_VALUE_VALUE TMR_VALUE_VALUE_Msk
+/* ======================================================== RELOAD ========================================================= */
+#define TMR_RELOAD_RELOAD_Pos (0UL) /*!< TMR RELOAD: RELOAD (Bit 0) */
+#define TMR_RELOAD_RELOAD_Msk (0xffffffffUL) /*!< TMR RELOAD: RELOAD (Bitfield-Mask: 0xffffffff) */
+#define TMR_RELOAD_RELOAD TMR_RELOAD_RELOAD_Msk
+/* ======================================================== INTSTS ========================================================= */
+#define TMR_INTSTS_INTSTS_Pos (0UL) /*!< TMR INTSTS: INTSTS (Bit 0) */
+#define TMR_INTSTS_INTSTS_Msk (0x1UL) /*!< TMR INTSTS: INTSTS (Bitfield-Mask: 0x01) */
+#define TMR_INTSTS_INTSTS TMR_INTSTS_INTSTS_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ UART ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= DATA ========================================================== */
+#define UART_DATA_DATA_Pos (0UL) /*!< UART DATA: DATA (Bit 0) */
+#define UART_DATA_DATA_Msk (0xffUL) /*!< UART DATA: DATA (Bitfield-Mask: 0xff) */
+#define UART_DATA_DATA UART_DATA_DATA_Msk
+/* ========================================================= STATE ========================================================= */
+#define UART_STATE_DMATXDONE_Pos (7UL) /*!< UART STATE: DMATXDONE (Bit 7) */
+#define UART_STATE_DMATXDONE_Msk (0x80UL) /*!< UART STATE: DMATXDONE (Bitfield-Mask: 0x01) */
+#define UART_STATE_DMATXDONE UART_STATE_DMATXDONE_Msk
+#define UART_STATE_RXPSTS_Pos (6UL) /*!< UART STATE: RXPSTS (Bit 6) */
+#define UART_STATE_RXPSTS_Msk (0x40UL) /*!< UART STATE: RXPSTS (Bitfield-Mask: 0x01) */
+#define UART_STATE_RXPSTS UART_STATE_RXPSTS_Msk
+#define UART_STATE_TXDONE_Pos (5UL) /*!< UART STATE: TXDONE (Bit 5) */
+#define UART_STATE_TXDONE_Msk (0x20UL) /*!< UART STATE: TXDONE (Bitfield-Mask: 0x01) */
+#define UART_STATE_TXDONE UART_STATE_TXDONE_Msk
+#define UART_STATE_RXPE_Pos (4UL) /*!< UART STATE: RXPE (Bit 4) */
+#define UART_STATE_RXPE_Msk (0x10UL) /*!< UART STATE: RXPE (Bitfield-Mask: 0x01) */
+#define UART_STATE_RXPE UART_STATE_RXPE_Msk
+#define UART_STATE_RXOV_Pos (3UL) /*!< UART STATE: RXOV (Bit 3) */
+#define UART_STATE_RXOV_Msk (0x8UL) /*!< UART STATE: RXOV (Bitfield-Mask: 0x01) */
+#define UART_STATE_RXOV UART_STATE_RXOV_Msk
+#define UART_STATE_TXOV_Pos (2UL) /*!< UART STATE: TXOV (Bit 2) */
+#define UART_STATE_TXOV_Msk (0x4UL) /*!< UART STATE: TXOV (Bitfield-Mask: 0x01) */
+#define UART_STATE_TXOV UART_STATE_TXOV_Msk
+#define UART_STATE_RXFULL_Pos (1UL) /*!< UART STATE: RXFULL (Bit 1) */
+#define UART_STATE_RXFULL_Msk (0x2UL) /*!< UART STATE: RXFULL (Bitfield-Mask: 0x01) */
+#define UART_STATE_RXFULL UART_STATE_RXFULL_Msk
+/* ========================================================= CTRL ========================================================== */
+#define UART_CTRL_TXDONEIE_Pos (8UL) /*!< UART CTRL: TXDONEIE (Bit 8) */
+#define UART_CTRL_TXDONEIE_Msk (0x100UL) /*!< UART CTRL: TXDONEIE (Bitfield-Mask: 0x01) */
+#define UART_CTRL_TXDONEIE UART_CTRL_TXDONEIE_Msk
+#define UART_CTRL_RXPEIE_Pos (7UL) /*!< UART CTRL: RXPEIE (Bit 7) */
+#define UART_CTRL_RXPEIE_Msk (0x80UL) /*!< UART CTRL: RXPEIE (Bitfield-Mask: 0x01) */
+#define UART_CTRL_RXPEIE UART_CTRL_RXPEIE_Msk
+#define UART_CTRL_RXOVIE_Pos (5UL) /*!< UART CTRL: RXOVIE (Bit 5) */
+#define UART_CTRL_RXOVIE_Msk (0x20UL) /*!< UART CTRL: RXOVIE (Bitfield-Mask: 0x01) */
+#define UART_CTRL_RXOVIE UART_CTRL_RXOVIE_Msk
+#define UART_CTRL_TXOVIE_Pos (4UL) /*!< UART CTRL: TXOVIE (Bit 4) */
+#define UART_CTRL_TXOVIE_Msk (0x10UL) /*!< UART CTRL: TXOVIE (Bitfield-Mask: 0x01) */
+#define UART_CTRL_TXOVIE UART_CTRL_TXOVIE_Msk
+#define UART_CTRL_RXIE_Pos (3UL) /*!< UART CTRL: RXIE (Bit 3) */
+#define UART_CTRL_RXIE_Msk (0x8UL) /*!< UART CTRL: RXIE (Bitfield-Mask: 0x01) */
+#define UART_CTRL_RXIE UART_CTRL_RXIE_Msk
+#define UART_CTRL_RXEN_Pos (1UL) /*!< UART CTRL: RXEN (Bit 1) */
+#define UART_CTRL_RXEN_Msk (0x2UL) /*!< UART CTRL: RXEN (Bitfield-Mask: 0x01) */
+#define UART_CTRL_RXEN UART_CTRL_RXEN_Msk
+#define UART_CTRL_TXEN_Pos (0UL) /*!< UART CTRL: TXEN (Bit 0) */
+#define UART_CTRL_TXEN_Msk (0x1UL) /*!< UART CTRL: TXEN (Bitfield-Mask: 0x01) */
+#define UART_CTRL_TXEN UART_CTRL_TXEN_Msk
+/* ======================================================== INTSTS ========================================================= */
+#define UART_INTSTS_TXDONEIF_Pos (5UL) /*!< UART INTSTS: TXDONEIF (Bit 5) */
+#define UART_INTSTS_TXDONEIF_Msk (0x20UL) /*!< UART INTSTS: TXDONEIF (Bitfield-Mask: 0x01) */
+#define UART_INTSTS_TXDONEIF UART_INTSTS_TXDONEIF_Msk
+#define UART_INTSTS_RXPEIF_Pos (4UL) /*!< UART INTSTS: RXPEIF (Bit 4) */
+#define UART_INTSTS_RXPEIF_Msk (0x10UL) /*!< UART INTSTS: RXPEIF (Bitfield-Mask: 0x01) */
+#define UART_INTSTS_RXPEIF UART_INTSTS_RXPEIF_Msk
+#define UART_INTSTS_RXOVIF_Pos (3UL) /*!< UART INTSTS: RXOVIF (Bit 3) */
+#define UART_INTSTS_RXOVIF_Msk (0x8UL) /*!< UART INTSTS: RXOVIF (Bitfield-Mask: 0x01) */
+#define UART_INTSTS_RXOVIF UART_INTSTS_RXOVIF_Msk
+#define UART_INTSTS_TXOVIF_Pos (2UL) /*!< UART INTSTS: TXOVIF (Bit 2) */
+#define UART_INTSTS_TXOVIF_Msk (0x4UL) /*!< UART INTSTS: TXOVIF (Bitfield-Mask: 0x01) */
+#define UART_INTSTS_TXOVIF UART_INTSTS_TXOVIF_Msk
+#define UART_INTSTS_RXIF_Pos (1UL) /*!< UART INTSTS: RXIF (Bit 1) */
+#define UART_INTSTS_RXIF_Msk (0x2UL) /*!< UART INTSTS: RXIF (Bitfield-Mask: 0x01) */
+#define UART_INTSTS_RXIF UART_INTSTS_RXIF_Msk
+/* ======================================================== BAUDDIV ======================================================== */
+#define UART_BAUDDIV_BAUDDIV_Pos (0UL) /*!< UART BAUDDIV: BAUDDIV (Bit 0) */
+#define UART_BAUDDIV_BAUDDIV_Msk (0xfffffUL) /*!< UART BAUDDIV: BAUDDIV (Bitfield-Mask: 0xfffff) */
+#define UART_BAUDDIV_BAUDDIV UART_BAUDDIV_BAUDDIV_Msk
+/* ========================================================= CTRL2 ========================================================= */
+#define UART_CTRL2_PMODE_Pos (1UL) /*!< UART CTRL2: PMODE (Bit 1) */
+#define UART_CTRL2_PMODE_Msk (0xeUL) /*!< UART CTRL2: PMODE (Bitfield-Mask: 0x07) */
+#define UART_CTRL2_PMODE UART_CTRL2_PMODE_Msk
+#define UART_CTRL2_MSB_Pos (0UL) /*!< UART CTRL2: MSB (Bit 0) */
+#define UART_CTRL2_MSB_Msk (0x1UL) /*!< UART CTRL2: MSB (Bitfield-Mask: 0x01) */
+#define UART_CTRL2_MSB UART_CTRL2_MSB_Msk
+
+
+/* =========================================================================================================================== */
+/* ================ U32K ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CTRL0 ========================================================= */
+#define U32K_CTRL0_WKUMODE_Pos (8UL) /*!< U32K CTRL0: WKUMODE (Bit 8) */
+#define U32K_CTRL0_WKUMODE_Msk (0x100UL) /*!< U32K CTRL0: WKUMODE (Bitfield-Mask: 0x01) */
+#define U32K_CTRL0_WKUMODE U32K_CTRL0_WKUMODE_Msk
+#define U32K_CTRL0_DEBSEL_Pos (6UL) /*!< U32K CTRL0: DEBSEL (Bit 6) */
+#define U32K_CTRL0_DEBSEL_Msk (0xc0UL) /*!< U32K CTRL0: DEBSEL (Bitfield-Mask: 0x03) */
+#define U32K_CTRL0_DEBSEL U32K_CTRL0_DEBSEL_Msk
+#define U32K_CTRL0_PMODE_Pos (3UL) /*!< U32K CTRL0: PMODE (Bit 3) */
+#define U32K_CTRL0_PMODE_Msk (0x38UL) /*!< U32K CTRL0: PMODE (Bitfield-Mask: 0x07) */
+#define U32K_CTRL0_PMODE U32K_CTRL0_PMODE_Msk
+#define U32K_CTRL0_MSB_Pos (2UL) /*!< U32K CTRL0: MSB (Bit 2) */
+#define U32K_CTRL0_MSB_Msk (0x4UL) /*!< U32K CTRL0: MSB (Bitfield-Mask: 0x01) */
+#define U32K_CTRL0_MSB U32K_CTRL0_MSB_Msk
+#define U32K_CTRL0_ACOFF_Pos (1UL) /*!< U32K CTRL0: ACOFF (Bit 1) */
+#define U32K_CTRL0_ACOFF_Msk (0x2UL) /*!< U32K CTRL0: ACOFF (Bitfield-Mask: 0x01) */
+#define U32K_CTRL0_ACOFF U32K_CTRL0_ACOFF_Msk
+#define U32K_CTRL0_EN_Pos (0UL) /*!< U32K CTRL0: EN (Bit 0) */
+#define U32K_CTRL0_EN_Msk (0x1UL) /*!< U32K CTRL0: EN (Bitfield-Mask: 0x01) */
+#define U32K_CTRL0_EN U32K_CTRL0_EN_Msk
+/* ========================================================= CTRL1 ========================================================= */
+#define U32K_CTRL1_RXSEL_Pos (4UL) /*!< U32K CTRL1: RXSEL (Bit 4) */
+#define U32K_CTRL1_RXSEL_Msk (0x30UL) /*!< U32K CTRL1: RXSEL (Bitfield-Mask: 0x03) */
+#define U32K_CTRL1_RXSEL U32K_CTRL1_RXSEL_Msk
+#define U32K_CTRL1_RXOVIE_Pos (2UL) /*!< U32K CTRL1: RXOVIE (Bit 2) */
+#define U32K_CTRL1_RXOVIE_Msk (0x4UL) /*!< U32K CTRL1: RXOVIE (Bitfield-Mask: 0x01) */
+#define U32K_CTRL1_RXOVIE U32K_CTRL1_RXOVIE_Msk
+#define U32K_CTRL1_RXPEIE_Pos (1UL) /*!< U32K CTRL1: RXPEIE (Bit 1) */
+#define U32K_CTRL1_RXPEIE_Msk (0x2UL) /*!< U32K CTRL1: RXPEIE (Bitfield-Mask: 0x01) */
+#define U32K_CTRL1_RXPEIE U32K_CTRL1_RXPEIE_Msk
+#define U32K_CTRL1_RXIE_Pos (0UL) /*!< U32K CTRL1: RXIE (Bit 0) */
+#define U32K_CTRL1_RXIE_Msk (0x1UL) /*!< U32K CTRL1: RXIE (Bitfield-Mask: 0x01) */
+#define U32K_CTRL1_RXIE U32K_CTRL1_RXIE_Msk
+/* ======================================================== BAUDDIV ======================================================== */
+#define U32K_BAUDDIV_BAUDDIV_Pos (0UL) /*!< U32K BAUDDIV: BAUDDIV (Bit 0) */
+#define U32K_BAUDDIV_BAUDDIV_Msk (0xffffUL) /*!< U32K BAUDDIV: BAUDDIV (Bitfield-Mask: 0xffff) */
+#define U32K_BAUDDIV_BAUDDIV U32K_BAUDDIV_BAUDDIV_Msk
+/* ========================================================= DATA ========================================================== */
+#define U32K_DATA_DATA_Pos (0UL) /*!< U32K DATA: DATA (Bit 0) */
+#define U32K_DATA_DATA_Msk (0xffUL) /*!< U32K DATA: DATA (Bitfield-Mask: 0xff) */
+#define U32K_DATA_DATA U32K_DATA_DATA_Msk
+/* ========================================================== STS ========================================================== */
+#define U32K_STS_RXOV_Pos (2UL) /*!< U32K STS: RXOV (Bit 2) */
+#define U32K_STS_RXOV_Msk (0x4UL) /*!< U32K STS: RXOV (Bitfield-Mask: 0x01) */
+#define U32K_STS_RXOV U32K_STS_RXOV_Msk
+#define U32K_STS_RXPE_Pos (1UL) /*!< U32K STS: RXPE (Bit 1) */
+#define U32K_STS_RXPE_Msk (0x2UL) /*!< U32K STS: RXPE (Bitfield-Mask: 0x01) */
+#define U32K_STS_RXPE U32K_STS_RXPE_Msk
+#define U32K_STS_RXIF_Pos (0UL) /*!< U32K STS: RXIF (Bit 0) */
+#define U32K_STS_RXIF_Msk (0x1UL) /*!< U32K STS: RXIF (Bitfield-Mask: 0x01) */
+#define U32K_STS_RXIF U32K_STS_RXIF_Msk
+
+/** @} */ /* End of group PosMask_peripherals */
+#include "system_target.h" /*!< target System */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TARGET_H */
+
+
+/** @} */ /* End of group target */
+
+/** @} */ /* End of group Vango */
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/type_def.h b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/type_def.h
new file mode 100644
index 0000000000000000000000000000000000000000..0a17a8b5c4630647a7207f3832591a040fac56d8
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/type_def.h
@@ -0,0 +1,107 @@
+/**
+ ******************************************************************************
+ * @file type_def.h
+ * @author Application Team
+ * @version V4.4.0
+ * @date 2018-09-27
+ * @brief Typedef file
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+
+#ifndef __TYPE_DEF_H
+#define __TYPE_DEF_H
+
+#define ENABLE 1
+#define DISABLE 0
+#define IS_FUNCTIONAL_STATE(__STATE__) (((__STATE__) == DISABLE) || ((__STATE__) == ENABLE))
+
+#define BIT_BAND(addr, bitnum) *((volatile unsigned long *)((((uint32_t)addr) & 0xF0000000) + \
+ 0x2000000 + ((((uint32_t)addr) & 0xFFFFF) << 5) + (bitnum << 2)))
+
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+#if defined ( __GNUC__ )
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__GNUC__) /* GNU Compiler */
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif /* __ALIGN_BEGIN */
+#else
+ #ifndef __ALIGN_END
+ #define __ALIGN_END
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #if defined (__CC_ARM) /* ARM Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #elif defined (__ICCARM__) /* IAR Compiler */
+ #define __ALIGN_BEGIN
+ #endif /* __CC_ARM */
+ #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#endif /* __TYPE_DEF_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/GCC/startup_target.S b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/GCC/startup_target.S
new file mode 100644
index 0000000000000000000000000000000000000000..b77a821a44318eb4fd7092c7f860f4c5ca8d2abd
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/GCC/startup_target.S
@@ -0,0 +1,478 @@
+;/**
+;* @file startup_target.s
+;* @author Application Team
+;* @version V1.1.0
+;* @date 2019-10-28
+;* @brief Target Devices vector table.
+;******************************************************************************/
+
+ .syntax unified
+ .cpu cortex-m0
+ .fpu softvfp
+ .thumb
+
+.equ __CHIPINITIAL, 1
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/*************************************************************************
+* Chip init.
+* 1. Load flash configuration
+* 2. Load ANA_REG(B/C/D/E) information
+* 3. Load ANA_REG10 information
+
+**************************************************************************/
+.if (__CHIPINITIAL != 0)
+ .section .chipinit_section.__CHIP_INIT
+__CHIP_INIT:
+CONFIG1_START:
+ /*-------------------------------*/
+ /* 1. Load flash configuration */
+ /* Unlock flash */
+ LDR R0, =0x000FFFE0
+ LDR R1, =0x55AAAA55
+ STR R1, [R0]
+ /* Load configure word 0 to 7
+ Compare bit[7:0] */
+ LDR R0, =0x00080E00
+ LDR R1, =0x20
+ LDR R2, =0x000FFFE8
+ LDR R3, =0x000FFFF0
+ LDR R4, =0x0
+ LDR R7, =0x0FF
+FLASH_CONF_START_1:
+ LDR R5, [R0]
+ STR R4, [R2]
+ STR R5, [R3]
+ LDR R6, [R3]
+ ANDS R5, R7
+ ANDS R6, R7
+ CMP R5, R6
+ BNE FLASH_CONF_AGAIN_1
+ ADDS R4, #4
+ ADDS R0, #4
+ CMP R1, R4
+ BEQ FLASH_CONF_END_1
+ B FLASH_CONF_START_1
+FLASH_CONF_AGAIN_1:
+ LDR R5, [R0]
+ STR R4, [R2]
+ STR R5, [R3]
+ LDR R6, [R3]
+ ANDS R5, R7
+ ANDS R6, R7
+ CMP R5, R6
+FLASH_CONF_WHILELOOP_1:
+ BNE FLASH_CONF_WHILELOOP_1
+ ADDS R4, #4
+ ADDS R0, #4
+ CMP R1, R4
+ BEQ FLASH_CONF_END_1
+ B FLASH_CONF_START_1
+FLASH_CONF_END_1:
+ /* Load configure word 8 to 11
+ Compare bit 31,24,23:16,8,7:0 */
+ LDR R1, =0x30
+ LDR R7, =0x81FF81FF
+FLASH_CONF_START_2:
+ LDR R5, [R0]
+ STR R4, [R2]
+ STR R5, [R3]
+ LDR R6, [R3]
+ ANDS R5, R7
+ ANDS R6, R7
+ CMP R5, R6
+ BNE FLASH_CONF_AGAIN_1
+ ADDS R4, #4
+ ADDS R0, #4
+ CMP R1, R4
+ BEQ FLASH_CONF_END_2
+ B FLASH_CONF_START_2
+FLASH_CONF_AGAIN_2:
+ LDR R5, [R0]
+ STR R4, [R2]
+ STR R5, [R3]
+ LDR R6, [R3]
+ ANDS R5, R7
+ ANDS R6, R7
+ CMP R5, R6
+FLASH_CONF_WHILELOOP_2:
+ BNE FLASH_CONF_WHILELOOP_2
+ ADDS R4, #4
+ ADDS R0, #4
+ CMP R1, R4
+ BEQ FLASH_CONF_END_2
+ B FLASH_CONF_START_2
+FLASH_CONF_END_2:
+ /* Lock flash */
+ LDR R0, =0x000FFFE0
+ LDR R1, =0x0
+ STR R1, [R0]
+ /*-------------------------------*/
+ /* 2. Load ANA_REG(B/C/D/E) information */
+CONFIG2_START:
+ LDR R4, =0x4001422C
+ LDR R5, =0x40014230
+ LDR R6, =0x40014234
+ LDR R7, =0x40014238
+ LDR R0, =0x80DC0
+ LDR R0, [R0]
+ LDR R1, =0x80DC4
+ LDR R1, [R1]
+ ADDS R2, R0, R1
+ ADDS R2, #0x0FFFFFFFF
+ MVNS R2, R2
+ LDR R3, =0x80DCC
+ LDR R3, [R3]
+ CMP R3, R2
+ BEQ ANADAT_CHECKSUM1_OK
+ B ANADAT_CHECKSUM1_ERR
+ANADAT_CHECKSUM1_OK:
+ /* ANA_REGB */
+ LDR R1, =0x0FF
+ ANDS R1, R0
+ STR R1, [R4]
+ /* ANA_REGC */
+ LDR R1, =0x0FF00
+ ANDS R1, R0
+ LSRS R1, R1, #8
+ STR R1, [R5]
+ /* ANA_REGD */
+ LDR R1, =0x0FF0000
+ ANDS R1, R0
+ LSRS R1, R1, #16
+ STR R1, [R6]
+ /* ANA_REGE */
+ LDR R1, =0x0FF000000
+ ANDS R1, R0
+ LSRS R1, R1, #24
+ STR R1, [R7]
+ B CONFIG3_START
+ANADAT_CHECKSUM1_ERR:
+ LDR R0, =0x80DD0
+ LDR R0, [R0]
+ LDR R1, =0x80DD4
+ LDR R1, [R1]
+ ADDS R2, R0, R1
+ ADDS R2, #0x0FFFFFFFF
+ MVNS R2, R2
+ LDR R3, =0x80DDC
+ LDR R3, [R3]
+ CMP R3, R2
+ BEQ ANADAT_CHECKSUM2_OK
+ B ANADAT_CHECKSUM2_ERR
+ANADAT_CHECKSUM2_OK:
+ /* ANA_REGB */
+ LDR R1, =0x0FF
+ ANDS R1, R0
+ STR R1, [R4]
+ /* ANA_REGC */
+ LDR R1, =0x0FF00
+ ANDS R1, R0
+ LSRS R1, R1, #8
+ STR R1, [R5]
+ /* ANA_REGD */
+ LDR R1, =0x0FF0000
+ ANDS R1, R0
+ LSRS R1, R1, #16
+ STR R1, [R6]
+ /* ANA_REGE */
+ LDR R1, =0x0FF000000
+ ANDS R1, R0
+ LSRS R1, R1, #24
+ STR R1, [R7]
+ B CONFIG3_START
+ANADAT_CHECKSUM2_ERR:
+ B ANADAT_CHECKSUM2_ERR
+ /*-------------------------------*/
+ /* 3. Load ANA_REG10 information */
+CONFIG3_START:
+ LDR R7, =0x40014240
+ LDR R0, =0x80DE0
+ LDR R0, [R0]
+ LDR R1, =0x80DE4
+ LDR R1, [R1]
+ MVNS R1, R1
+ CMP R1, R0
+ BEQ ANADAT10_CHECKSUM1_OK
+ B ANADAT10_CHECKSUM1_ERR
+ANADAT10_CHECKSUM1_OK:
+ /* ANA_REG10 */
+ LDR R1, =0x0FF
+ ANDS R1, R0
+ STR R1, [R7]
+ BX LR
+ANADAT10_CHECKSUM1_ERR:
+ LDR R0, =0x80DE8
+ LDR R0, [R0]
+ LDR R1, =0x80DEC
+ LDR R1, [R1]
+ MVNS R1, R1
+ CMP R1, R0
+ BEQ ANADAT10_CHECKSUM2_OK
+ B ANADAT10_CHECKSUM2_ERR
+ANADAT10_CHECKSUM2_OK:
+ /* ANA_REG10 */
+ LDR R1, =0x0FF
+ ANDS R1, R0
+ STR R1, [R7]
+ BX LR
+ANADAT10_CHECKSUM2_ERR:
+ B ANADAT10_CHECKSUM2_ERR
+.size __CHIP_INIT, .-__CHIP_INIT
+.endif
+
+
+.if (__CHIPINITIAL != 0)
+ .global __CHIP_INIT
+ .section .chipinit_section.Reset_Handler
+.else
+ .section .text.Reset_Handler
+.endif
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+.if (__CHIPINITIAL != 0)
+/* Chip Initiliazation */
+ bl __CHIP_INIT
+/* System Initiliazation */
+ bl SystemInit
+.endif
+
+/* set stack pointer */
+ ldr r0, =_estack
+ mov sp, r0
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word 0
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word PMU_IRQHandler /* 0: PMU */
+ .word RTC_IRQHandler /* 1: RTC */
+ .word U32K0_IRQHandler /* 2: U32K0 */
+ .word U32K1_IRQHandler /* 3: U32K1 */
+ .word I2C_IRQHandler /* 4: I2C */
+ .word SPI1_IRQHandler /* 5: SPI1 */
+ .word UART0_IRQHandler /* 6: UART0 */
+ .word UART1_IRQHandler /* 7: UART1 */
+ .word UART2_IRQHandler /* 8: UART2 */
+ .word UART3_IRQHandler /* 9: UART3 */
+ .word UART4_IRQHandler /* 10: UART4 */
+ .word UART5_IRQHandler /* 11: UART5 */
+ .word ISO78160_IRQHandler /* 12: ISO78160 */
+ .word ISO78161_IRQHandler /* 13: ISO78161 */
+ .word TMR0_IRQHandler /* 14: TMR0 */
+ .word TMR1_IRQHandler /* 15: TMR1 */
+ .word TMR2_IRQHandler /* 16: TMR2 */
+ .word TMR3_IRQHandler /* 17: TMR3 */
+ .word PWM0_IRQHandler /* 18: PWM0 */
+ .word PWM1_IRQHandler /* 19: PWM1 */
+ .word PWM2_IRQHandler /* 20: PWM2 */
+ .word PWM3_IRQHandler /* 21: PWM3 */
+ .word DMA_IRQHandler /* 22: DMA */
+ .word FLASH_IRQHandler /* 23: FLASH */
+ .word ANA_IRQHandler /* 24: ANA */
+ .word 0 /* 25: Reserved */
+ .word 0 /* 26: Reserved */
+ .word SPI2_IRQHandler /* 27: SPI2 */
+ .word SPI3_IRQHandler /* 28: SPI3 */
+ .word 0 /* 29: Reserved */
+ .word 0 /* 30: Reserved */
+ .word 0 /* 31: Reserved */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak PMU_IRQHandler
+ .thumb_set PMU_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak U32K0_IRQHandler
+ .thumb_set U32K0_IRQHandler,Default_Handler
+
+ .weak U32K1_IRQHandler
+ .thumb_set U32K1_IRQHandler,Default_Handler
+
+ .weak I2C_IRQHandler
+ .thumb_set I2C_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak UART0_IRQHandler
+ .thumb_set UART0_IRQHandler,Default_Handler
+
+ .weak UART1_IRQHandler
+ .thumb_set UART1_IRQHandler,Default_Handler
+
+ .weak UART2_IRQHandler
+ .thumb_set UART2_IRQHandler,Default_Handler
+
+ .weak UART3_IRQHandler
+ .thumb_set UART3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak ISO78160_IRQHandler
+ .thumb_set ISO78160_IRQHandler,Default_Handler
+
+ .weak ISO78161_IRQHandler
+ .thumb_set ISO78161_IRQHandler,Default_Handler
+
+ .weak TMR0_IRQHandler
+ .thumb_set TMR0_IRQHandler,Default_Handler
+
+ .weak TMR1_IRQHandler
+ .thumb_set TMR1_IRQHandler,Default_Handler
+
+ .weak TMR2_IRQHandler
+ .thumb_set TMR2_IRQHandler,Default_Handler
+
+ .weak TMR3_IRQHandler
+ .thumb_set TMR3_IRQHandler,Default_Handler
+
+ .weak PWM0_IRQHandler
+ .thumb_set PWM0_IRQHandler,Default_Handler
+
+ .weak PWM1_IRQHandler
+ .thumb_set PWM1_IRQHandler,Default_Handler
+
+ .weak PWM2_IRQHandler
+ .thumb_set PWM2_IRQHandler,Default_Handler
+
+ .weak PWM3_IRQHandler
+ .thumb_set PWM3_IRQHandler,Default_Handler
+
+ .weak DMA_IRQHandler
+ .thumb_set DMA_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak ANA_IRQHandler
+ .thumb_set ANA_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/Keil5/startup_target.S b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/Keil5/startup_target.S
new file mode 100644
index 0000000000000000000000000000000000000000..90fd31b143ccb0d21161b308bcd0802630f8d663
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/Keil5/startup_target.S
@@ -0,0 +1,450 @@
+;/**
+;* @file startup_target.s
+;* @author Application Team
+;* @version V1.1.0
+;* @date 2019-10-28
+;* @brief Target Devices vector table.
+;******************************************************************************/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+__CHIPINITIAL EQU 1
+
+Stack_Size EQU 0x000001000
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD PMU_IRQHandler ; 0: PMU
+ DCD RTC_IRQHandler ; 1: RTC
+ DCD U32K0_IRQHandler ; 2: U32K0
+ DCD U32K1_IRQHandler ; 3: U32K1
+ DCD I2C_IRQHandler ; 4: I2C
+ DCD SPI1_IRQHandler ; 5: SPI1
+ DCD UART0_IRQHandler ; 6: UART0
+ DCD UART1_IRQHandler ; 7: UART1
+ DCD UART2_IRQHandler ; 8: UART2
+ DCD UART3_IRQHandler ; 9: UART3
+ DCD UART4_IRQHandler ; 10: UART4
+ DCD UART5_IRQHandler ; 11: UART5
+ DCD ISO78160_IRQHandler ; 12: ISO78160
+ DCD ISO78161_IRQHandler ; 13: ISO78161
+ DCD TMR0_IRQHandler ; 14: TMR0
+ DCD TMR1_IRQHandler ; 15: TMR1
+ DCD TMR2_IRQHandler ; 16: TMR2
+ DCD TMR3_IRQHandler ; 17: TMR3
+ DCD PWM0_IRQHandler ; 18: PWM0
+ DCD PWM1_IRQHandler ; 19: PWM1
+ DCD PWM2_IRQHandler ; 20: PWM2
+ DCD PWM3_IRQHandler ; 21: PWM3
+ DCD DMA_IRQHandler ; 22: DMA
+ DCD FLASH_IRQHandler ; 23: FLASH
+ DCD ANA_IRQHandler ; 24: ANA
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD SPI2_IRQHandler ; 27: SPI2
+ DCD SPI3_IRQHandler ; 28: SPI3
+ DCD 0 ; 29: Reserved
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ IF (__CHIPINITIAL != 0)
+ AREA |.ARM.__AT_0xC0|, CODE, READONLY
+ ELSE
+ AREA |.text|, CODE, READONLY
+ ENDIF
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ IF (__CHIPINITIAL != 0)
+ LDR R0, =__CHIP_INIT
+ BLX R0
+ ENDIF
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+ AREA |.text|, CODE, READONLY
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT PMU_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT U32K0_IRQHandler [WEAK]
+ EXPORT U32K1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT ISO78160_IRQHandler [WEAK]
+ EXPORT ISO78161_IRQHandler [WEAK]
+ EXPORT TMR0_IRQHandler [WEAK]
+ EXPORT TMR1_IRQHandler [WEAK]
+ EXPORT TMR2_IRQHandler [WEAK]
+ EXPORT TMR3_IRQHandler [WEAK]
+ EXPORT PWM0_IRQHandler [WEAK]
+ EXPORT PWM1_IRQHandler [WEAK]
+ EXPORT PWM2_IRQHandler [WEAK]
+ EXPORT PWM3_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT ANA_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+
+PMU_IRQHandler
+RTC_IRQHandler
+U32K0_IRQHandler
+U32K1_IRQHandler
+I2C_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+ISO78160_IRQHandler
+ISO78161_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+PWM0_IRQHandler
+PWM1_IRQHandler
+PWM2_IRQHandler
+PWM3_IRQHandler
+DMA_IRQHandler
+FLASH_IRQHandler
+ANA_IRQHandler
+SPI2_IRQHandler
+SPI3_IRQHandler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Chip init.
+;; 1. Load flash configuration
+;; 2. Load ANA_REG(B/C/D/E) information
+;; 3. Load ANA_REG10 information
+ IF (__CHIPINITIAL != 0)
+ AREA |.ARM.__AT_0xC0|, CODE, READONLY
+
+__CHIP_INIT PROC
+CONFIG1_START
+ ;-------------------------------;
+ ;; 1. Load flash configuration
+ ; Unlock flash
+ LDR R0, =0x000FFFE0
+ LDR R1, =0x55AAAA55
+ STR R1, [R0]
+ ; Load configure word 0 to 7
+ ; Compare bit[7:0]
+ LDR R0, =0x00080E00
+ LDR R1, =0x20
+ LDR R2, =0x000FFFE8
+ LDR R3, =0x000FFFF0
+ LDR R4, =0x0
+ LDR R7, =0x0FF
+FLASH_CONF_START_1
+ LDR R5, [R0]
+ STR R4, [R2]
+ STR R5, [R3]
+ LDR R6, [R3]
+ ANDS R5, R7
+ ANDS R6, R7
+ CMP R5, R6
+ BNE FLASH_CONF_AGAIN_1
+ ADDS R4, #4
+ ADDS R0, #4
+ CMP R1, R4
+ BEQ FLASH_CONF_END_1
+ B FLASH_CONF_START_1
+FLASH_CONF_AGAIN_1
+ LDR R5, [R0]
+ STR R4, [R2]
+ STR R5, [R3]
+ LDR R6, [R3]
+ ANDS R5, R7
+ ANDS R6, R7
+ CMP R5, R6
+FLASH_CONF_WHILELOOP_1
+ BNE FLASH_CONF_WHILELOOP_1
+ ADDS R4, #4
+ ADDS R0, #4
+ CMP R1, R4
+ BEQ FLASH_CONF_END_1
+ B FLASH_CONF_START_1
+FLASH_CONF_END_1
+ ; Load configure word 8 to 11
+ ; Compare bit 31,24,23:16,8,7:0
+ LDR R1, =0x30
+ LDR R7, =0x81FF81FF
+FLASH_CONF_START_2
+ LDR R5, [R0]
+ STR R4, [R2]
+ STR R5, [R3]
+ LDR R6, [R3]
+ ANDS R5, R7
+ ANDS R6, R7
+ CMP R5, R6
+ BNE FLASH_CONF_AGAIN_1
+ ADDS R4, #4
+ ADDS R0, #4
+ CMP R1, R4
+ BEQ FLASH_CONF_END_2
+ B FLASH_CONF_START_2
+FLASH_CONF_AGAIN_2
+ LDR R5, [R0]
+ STR R4, [R2]
+ STR R5, [R3]
+ LDR R6, [R3]
+ ANDS R5, R7
+ ANDS R6, R7
+ CMP R5, R6
+FLASH_CONF_WHILELOOP_2
+ BNE FLASH_CONF_WHILELOOP_2
+ ADDS R4, #4
+ ADDS R0, #4
+ CMP R1, R4
+ BEQ FLASH_CONF_END_2
+ B FLASH_CONF_START_2
+FLASH_CONF_END_2
+ ; Lock flash
+ LDR R0, =0x000FFFE0
+ LDR R1, =0x0
+ STR R1, [R0]
+ ;-------------------------------;
+ ;; 2. Load ANA_REG(B/C/D/E) information
+CONFIG2_START
+ LDR R4, =0x4001422C
+ LDR R5, =0x40014230
+ LDR R6, =0x40014234
+ LDR R7, =0x40014238
+ LDR R0, =0x80DC0
+ LDR R0, [R0]
+ LDR R1, =0x80DC4
+ LDR R1, [R1]
+ ADDS R2, R0, R1
+ ADDS R2, #0x0FFFFFFFF
+ MVNS R2, R2
+ LDR R3, =0x80DCC
+ LDR R3, [R3]
+ CMP R3, R2
+ BEQ ANADAT_CHECKSUM1_OK
+ B ANADAT_CHECKSUM1_ERR
+ANADAT_CHECKSUM1_OK
+ ; ANA_REGB
+ LDR R1, =0x0FF
+ ANDS R1, R0
+ STR R1, [R4]
+ ; ANA_REGC
+ LDR R1, =0x0FF00
+ ANDS R1, R0
+ LSRS R1, R1, #8
+ STR R1, [R5]
+ ; ANA_REGD
+ LDR R1, =0x0FF0000
+ ANDS R1, R0
+ LSRS R1, R1, #16
+ STR R1, [R6]
+ ; ANA_REGE
+ LDR R1, =0x0FF000000
+ ANDS R1, R0
+ LSRS R1, R1, #24
+ STR R1, [R7]
+ B CONFIG3_START
+ANADAT_CHECKSUM1_ERR
+ LDR R0, =0x80DD0
+ LDR R0, [R0]
+ LDR R1, =0x80DD4
+ LDR R1, [R1]
+ ADDS R2, R0, R1
+ ADDS R2, #0x0FFFFFFFF
+ MVNS R2, R2
+ LDR R3, =0x80DDC
+ LDR R3, [R3]
+ CMP R3, R2
+ BEQ ANADAT_CHECKSUM2_OK
+ B ANADAT_CHECKSUM2_ERR
+ANADAT_CHECKSUM2_OK
+ ; ANA_REGB
+ LDR R1, =0x0FF
+ ANDS R1, R0
+ STR R1, [R4]
+ ; ANA_REGC
+ LDR R1, =0x0FF00
+ ANDS R1, R0
+ LSRS R1, R1, #8
+ STR R1, [R5]
+ ; ANA_REGD
+ LDR R1, =0x0FF0000
+ ANDS R1, R0
+ LSRS R1, R1, #16
+ STR R1, [R6]
+ ; ANA_REGE
+ LDR R1, =0x0FF000000
+ ANDS R1, R0
+ LSRS R1, R1, #24
+ STR R1, [R7]
+ B CONFIG3_START
+ANADAT_CHECKSUM2_ERR
+ B ANADAT_CHECKSUM2_ERR
+ ;-------------------------------;
+ ;; 2. Load ANA_REG10 information
+CONFIG3_START
+ LDR R7, =0x40014240
+ LDR R0, =0x80DE0
+ LDR R0, [R0]
+ LDR R1, =0x80DE4
+ LDR R1, [R1]
+ MVNS R1, R1
+ CMP R1, R0
+ BEQ ANADAT10_CHECKSUM1_OK
+ B ANADAT10_CHECKSUM1_ERR
+ANADAT10_CHECKSUM1_OK
+ ; ANA_REG10
+ LDR R1, =0x0FF
+ ANDS R1, R0
+ STR R1, [R7]
+ BX LR
+ANADAT10_CHECKSUM1_ERR
+ LDR R0, =0x80DE8
+ LDR R0, [R0]
+ LDR R1, =0x80DEC
+ LDR R1, [R1]
+ MVNS R1, R1
+ CMP R1, R0
+ BEQ ANADAT10_CHECKSUM2_OK
+ B ANADAT10_CHECKSUM2_ERR
+ANADAT10_CHECKSUM2_OK
+ ; ANA_REG10
+ LDR R1, =0x0FF
+ ANDS R1, R0
+ STR R1, [R7]
+ BX LR
+ANADAT10_CHECKSUM2_ERR
+ B ANADAT10_CHECKSUM2_ERR
+
+ NOP
+ ENDP
+ ENDIF
+
+ END
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_CodeRAM.c b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_CodeRAM.c
new file mode 100644
index 0000000000000000000000000000000000000000..363f49a86ddcc2163792b0d109996e6eb9514ebb
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_CodeRAM.c
@@ -0,0 +1,35 @@
+/**
+ ******************************************************************************
+ * @file lib_CodeRAM.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Codes executed in SRAM.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "lib_CodeRAM.h"
+
+#ifndef __GNUC__
+/**
+ * @brief Enter idle mode with flash deep standby.
+ * @note This function is executed in RAM.
+ * @param None
+ * @retval None
+ */
+__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void)
+{
+ /* Flash deep standby */
+ FLASH->PASS = 0x55AAAA55;
+ FLASH->DSTB = 0xAA5555AA;
+ /* Enter Idle mode */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+ __WFI();
+}
+#endif
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_LoadNVR.c b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_LoadNVR.c
new file mode 100644
index 0000000000000000000000000000000000000000..e3fbc7c00e4aa725e739afa325095866a4032ee3
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_LoadNVR.c
@@ -0,0 +1,700 @@
+/**
+ ******************************************************************************
+ * @file lib_LoadNVR.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Load information from NVR.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "lib_LoadNVR.h"
+
+
+/**
+ * @breif Loads Analog trim data from NVR manually.
+ * @note Successful Operation:
+ * - Load [0x80DC0] or [0x80DD0] to ANA registers(B C D E)
+ * - Load [0x80DE0] or [0x80DE8] to ANA registers(10)
+ * @param None
+ * @retval 0: Function succeeded.
+ !0: Function failed.
+ bit[0]=1: Function failed(ANA registers(B C D E) Checksum error).
+ bit[1]=1: Function failed(ANA registers(10) Checksum error).
+ */
+uint32_t NVR_LoadANADataManual(void)
+{
+ uint32_t checksum;
+ uint32_t op_reg;
+ uint32_t ana_data;
+ uint32_t key_reg = 0xFFFFFFFF;
+ uint32_t ret = 0;
+
+ /* Get Analog data1 */
+ ana_data = *NVR_ANA_TRIMDATA1;
+ op_reg = *NVR_ANA_OPREG1;
+ /* Calculate checksum1 */
+ checksum = ~(ana_data + op_reg + key_reg);
+ /* Compare checksum1 */
+ if (checksum == (*NVR_ANA_CHECKSUM1))
+ {
+ ANA->REGB = (uint8_t)(ana_data);
+ ANA->REGC = (uint8_t)(ana_data >> 8);
+ ANA->REGD = (uint8_t)(ana_data >> 16);
+ ANA->REGE = (uint8_t)(ana_data >> 24);
+ }
+ else
+ {
+ /* Get Analog data2 */
+ ana_data = *NVR_ANA_TRIMDATA2;
+ op_reg = *NVR_ANA_OPREG2;
+ /* Calculate checksum2 */
+ checksum = ~(ana_data + op_reg + key_reg);
+ /* Compare checksum2 */
+ if (checksum == (*NVR_ANA_CHECKSUM2))
+ {
+ ANA->REGB = (uint8_t)(ana_data);
+ ANA->REGC = (uint8_t)(ana_data >> 8);
+ ANA->REGD = (uint8_t)(ana_data >> 16);
+ ANA->REGE = (uint8_t)(ana_data >> 24);
+ }
+ else
+ {
+ ret |= BIT0;
+ }
+ }
+
+ /* Get Analog data1 */
+ ana_data = *NVR_ANA1_REG10;
+ /* Calculate checksum1 */
+ checksum = ~ana_data;
+ /* Compare checksum1 */
+ if (checksum == (*NVR_ANA1_REG10_CHKSUM))
+ {
+ ANA->REG10 = (uint8_t)(ana_data);
+ }
+ else
+ {
+ /* Get Analog data2 */
+ ana_data = *NVR_ANA2_REG10;
+ /* Calculate checksum2 */
+ checksum = ~ana_data;
+ /* Compare checksum2 */
+ if (checksum == (*NVR_ANA2_REG10_CHKSUM))
+ {
+ ANA->REG10 = (uint8_t)(ana_data);
+ }
+ else
+ {
+ ret |= BIT1;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @breif Gets the parameters of ADC voltage measuring.
+ * @note Voltage(unit:V) = aParameter*ADC_DATA + bParameter + OffsetParameter
+ * ADC_DATA: ADC channel original data
+ * aParameter/bParameter/OffsetParameter: Get from this function
+ * @param [in]Mode:
+ * NVR_3V_EXTERNAL_NODIV
+ * NVR_3V_EXTERNAL_RESDIV
+ * NVR_3V_BAT1_RESDIV
+ * NVR_3V_BATRTC_RESDIV
+ * NVR_5V_EXTERNAL_NODIV
+ * NVR_5V_EXTERNAL_RESDIV
+ * NVR_5V_BAT1_RESDIV
+ * NVR_5V_BATRTC_RESDIV
+ * @param [out]Parameter: The parameters get from NVR
+ * @retval 0: Function succeeded.
+ 1: Function failed(Checksum error).
+ */
+uint32_t NVR_GetVoltageParameters(uint32_t Mode, NVR_ADCVOLPARA *Parameter)
+{
+ uint32_t checksum;
+ uint32_t i;
+ int32_t tmp_int;
+
+ /* Check the parameters */
+ assert_parameters(IS_NVR_ADCVOL_MODE(Mode));
+
+ /*----- Power supply: 5V -----*/
+ if (0x100UL & Mode)
+ {
+ /* Parameter */
+ checksum = 0UL;
+ for (i=0; i<8; i++)
+ checksum += *(NVR_5VPARA_BASEADDR1+i);
+ checksum = ~(checksum);
+ if (checksum != *(NVR_5VPARA_BASEADDR1+i)) /* Checksum1 error */
+ {
+ checksum = 0UL;
+ for (i=0; i<8; i++)
+ checksum += *(NVR_5VPARA_BASEADDR2+i);
+ checksum = ~(checksum);
+ if (checksum != *(NVR_5VPARA_BASEADDR2+i)) /* Checksum2 error */
+ {
+ return 1;
+ }
+ else
+ {
+ tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL));
+ Parameter->aParameter = (float)(tmp_int / 100000.0);
+ tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL)+1);
+ Parameter->bParameter = (float)(tmp_int / 100000.0);
+ }
+ }
+ else
+ {
+ tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL));
+ Parameter->aParameter = (float)(tmp_int / 100000.0);
+ tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL)+1);
+ Parameter->bParameter = (float)(tmp_int / 100000.0);
+ }
+ /* Offset */
+ /* Calculate checksum1 */
+ checksum = 0UL;
+ for (i = 0; i < 4; i++)
+ checksum += *(NVR_5VADCCHx_NODIV1 + i);
+ checksum = ~(checksum);
+ if (checksum != *(NVR_5VADCCHx_NODIV1 + i))
+ {
+ /* Calculate checksum2 */
+ checksum = 0UL;
+ for (i = 0; i < 4; i++)
+ checksum += *(NVR_5VADCCHx_NODIV2+i);
+ checksum = ~(checksum);
+ if (checksum != *(NVR_5VADCCHx_NODIV2 + i))
+ {
+ return 1;
+ }
+ else
+ {
+ Parameter->OffsetParameter = (float)((int32_t)*(NVR_5VADCCHx_NODIV2 + (Mode-0x100UL)));
+ return 0;
+ }
+ }
+ else
+ {
+ Parameter->OffsetParameter = (float)((int32_t)*(NVR_5VADCCHx_NODIV1 + (Mode-0x100UL)));
+ return 0;
+ }
+ }
+ /*----- Power supply: 3.3V -----*/
+ else
+ {
+ checksum = 0UL;
+ for (i=0; i<8; i++)
+ checksum += *(NVR_3VPARA_BASEADDR1+i);
+ checksum = ~(checksum);
+ if (checksum != *(NVR_3VPARA_BASEADDR1+i)) /* Checksum1 error */
+ {
+ checksum = 0UL;
+ for (i=0; i<8; i++)
+ checksum += *(NVR_3VPARA_BASEADDR2+i);
+ checksum = ~(checksum);
+ if (checksum != *(NVR_3VPARA_BASEADDR2+i)) /* Checksum2 error */
+ {
+ return 1;
+ }
+ else
+ {
+ tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode));
+ Parameter->aParameter = (float)(tmp_int / 100000.0);
+ tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode)+1);
+ Parameter->bParameter = (float)(tmp_int / 100000.0);
+ }
+ }
+ else
+ {
+ tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode));
+ Parameter->aParameter = (float)(tmp_int / 100000.0);
+ tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode)+1);
+ Parameter->bParameter = (float)(tmp_int / 100000.0);
+ }
+ /* Calculate checksum1 */
+ checksum = 0UL;
+ for (i = 0; i < 4; i++)
+ checksum += *(NVR_3VADCCHx_NODIV1 + i);
+ checksum = ~(checksum);
+ if (checksum != *(NVR_3VADCCHx_NODIV1 + i))
+ {
+ /* Calculate checksum2 */
+ checksum = 0UL;
+ for (i = 0; i < 4; i++)
+ checksum += *(NVR_3VADCCHx_NODIV2+i);
+ checksum = ~(checksum);
+ if (checksum != *(NVR_3VADCCHx_NODIV2 + i))
+ {
+ return 1;
+ }
+ else
+ {
+ Parameter->OffsetParameter = (float)((int32_t)*(NVR_3VADCCHx_NODIV2 + (Mode)));
+ return 0;
+ }
+ }
+ else
+ {
+ Parameter->OffsetParameter = (float)((int32_t)*(NVR_3VADCCHx_NODIV1 + (Mode)));
+ return 0;
+ }
+ }
+}
+
+/**
+ * @breif Gets RTC parameters(P0 P1 P2).
+ * @param [out]TempParams The pointer to struct NVR_TempParams.
+ * @retval 0: Function succeeded.
+ !0: Function failed.
+ bit[0]=1: Temperature Measure delta information checksum error, default value 0.
+ bit[1]=1: P0/P1/P2 paramters checksum error, default value 0
+ */
+uint32_t NVR_GetTempParameters(NVR_TempParams *TempParams)
+{
+ uint32_t checksum;
+ uint32_t data_u32[4];
+ int32_t TempDelta;
+ uint32_t retval = 0;
+
+/*------------------------ Temperature Measure delta -------------------------*/
+ data_u32[0] = *NVR_REALTEMP1;
+ data_u32[1] = *NVR_MEATEMP1;
+ /* Calculate checksum1 */
+ checksum = ~(data_u32[0] + data_u32[1]);
+ if (checksum == (*NVR_TEMP_CHECKSUM1)) //checksum1 true
+ {
+ TempDelta = (int32_t)data_u32[0] - (int32_t)data_u32[1];
+ }
+ else
+ {
+ data_u32[0] = *NVR_REALTEMP2;
+ data_u32[1] = *NVR_MEATEMP2;
+ /* Calculate checksum2 */
+ checksum = ~(data_u32[0] + data_u32[1]);
+ if (checksum == (*NVR_TEMP_CHECKSUM2)) //checksum2 true
+ {
+ TempDelta = (int32_t)data_u32[0] - (int32_t)data_u32[1];
+ }
+ else
+ {
+ TempDelta = 0;
+ retval |= BIT0;
+ }
+ }
+/*------------------------------ P parameters --------------------------------*/
+
+ data_u32[0] = *NVR_RTC1_P1_P0;
+ data_u32[1] = *NVR_RTC1_P2;
+ data_u32[2] = *NVR_RTC1_P5_P4;
+ data_u32[3] = *NVR_RTC1_P7_P6;
+
+ /* Calculate checksum1 */
+ checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3]);
+ if (checksum == (*NVR_RTC1_PCHECHSUM)) //checksum1 true
+ {
+ /* Get information */
+ TempParams->RTCTempP0 = (int16_t)(data_u32[0]);
+ TempParams->RTCTempP1 = (int16_t)(data_u32[0] >> 16);
+ TempParams->RTCTempP2 = (int32_t)((int32_t)(data_u32[1]) + (TempDelta*256));
+ }
+ else
+ {
+ data_u32[0] = *NVR_RTC2_P1_P0;
+ data_u32[1] = *NVR_RTC2_P2;
+ data_u32[2] = *NVR_RTC2_P5_P4;
+ data_u32[3] = *NVR_RTC2_P7_P6;
+ /* Calculate checksum2 */
+ checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3]);
+ if (checksum == (*NVR_RTC2_PCHECHSUM)) //checksum2 true
+ {
+ /* Get information */
+ TempParams->RTCTempP0 = (int16_t)(data_u32[0]);
+ TempParams->RTCTempP1 = (int16_t)(data_u32[0] >> 16);
+ TempParams->RTCTempP2 = (int32_t)((int32_t)(data_u32[1]) + (TempDelta*256));
+ }
+ else
+ {
+ /* Get information */
+ TempParams->RTCTempP0 = 0;
+ TempParams->RTCTempP1 = 0;
+ TempParams->RTCTempP2 = 0;
+ retval |= BIT1;
+ }
+ }
+ return retval;
+}
+
+/**
+ * @breif Loads RTC ACPx pramameters from NVR to RTC registers.
+ Get RTC pramameters.
+ * @param [out]RTCTempData The pointer to struct NVR_RTCINFO.
+ [in]DivCLKSource The RTC division output clock source frequency
+ * @retval 0: Function succeeded.
+ !0: Function not succeeded, load default value to registers.
+ bit[0]=1: Temperature Measure delta information checksum error, default value 0.
+ bit[1]=1: P paramters checksum error, default value 0
+ bit[2]=1: P4 checksum error, default value is 0
+ bit[3]=1: ACKx checksum error, default value 0
+ bit[4]=1: ACTI checksum error, default value is 0
+ bit[5]=1: ACKTEMP checksum error, defalut value is 0
+ */
+uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData, uint32_t DivCLKSource)
+{
+ uint32_t data_u32[5];
+ uint32_t checksum;
+ float pclk_mul;
+ uint32_t retval = 0;
+
+/*------------------------ Temperature Measure delta -------------------------*/
+ data_u32[0] = *NVR_REALTEMP1;
+ data_u32[1] = *NVR_MEATEMP1;
+ /* Calculate checksum1 */
+ checksum = ~(data_u32[0] + data_u32[1]);
+ if (checksum == (*NVR_TEMP_CHECKSUM1)) //checksum1 true
+ {
+ RTCTempData->RTCTempDelta = (int32_t)data_u32[0] - (int32_t)data_u32[1];
+ }
+ else
+ {
+ data_u32[0] = *NVR_REALTEMP2;
+ data_u32[1] = *NVR_MEATEMP2;
+ /* Calculate checksum2 */
+ checksum = ~(data_u32[0] + data_u32[1]);
+ if (checksum == (*NVR_TEMP_CHECKSUM2)) //checksum2 true
+ {
+ RTCTempData->RTCTempDelta = (int32_t)data_u32[0] - (int32_t)data_u32[1];
+ }
+ else
+ {
+ RTCTempData->RTCTempDelta = 0;
+ retval |= BIT0;
+ }
+ }
+
+/*------------------------------ P parameters --------------------------------*/
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ /* RTC div output clock source */
+ pclk_mul = DivCLKSource / 6553600.0;
+
+ data_u32[0] = *NVR_RTC1_P1_P0;
+ data_u32[1] = *NVR_RTC1_P2;
+ data_u32[2] = *NVR_RTC1_P5_P4;
+ data_u32[3] = *NVR_RTC1_P7_P6;
+ /* Calculate checksum1 */
+ checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3]);
+ if (checksum == (*NVR_RTC1_PCHECHSUM)) //checksum1 true
+ {
+ /* Get information */
+ RTCTempData->RTCTempP0 = (int16_t)(data_u32[0]);
+ RTCTempData->RTCTempP1 = (int16_t)(data_u32[0] >> 16);
+ RTCTempData->RTCTempP2 = (int32_t)((int32_t)(data_u32[1]) + (RTCTempData->RTCTempDelta*256));
+ RTCTempData->RTCTempP5 = (int16_t)(data_u32[2] >> 16);
+ RTCTempData->RTCTempP6 = (int16_t)(data_u32[3] * pclk_mul);
+ RTCTempData->RTCTempP7 = (int16_t)(data_u32[3] >> 16);
+
+ /* Load data to ACPx register */
+ RTC->ACP0 = (uint16_t)(data_u32[0] & 0xFFFF);
+ RTC->ACP1 = (uint16_t)((data_u32[0] >> 16) & 0xFFFF);
+ RTC->ACP2 = (uint32_t)((int32_t)(data_u32[1]) + (RTCTempData->RTCTempDelta*256));
+ RTC->ACP5 = (uint16_t)((data_u32[2] >> 16) & 0xFFFF);
+ RTC->ACP6 = ((uint16_t)((int16_t)(data_u32[3] * pclk_mul)));
+ RTC->ACP7 = (uint16_t)((data_u32[3] >> 16) & 0xFFFF);
+ }
+ else
+ {
+ data_u32[0] = *NVR_RTC2_P1_P0;
+ data_u32[1] = *NVR_RTC2_P2;
+ data_u32[2] = *NVR_RTC2_P5_P4;
+ data_u32[3] = *NVR_RTC2_P7_P6;
+ /* Calculate checksum2 */
+ checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3]);
+ if (checksum == (*NVR_RTC2_PCHECHSUM)) //checksum2 true
+ {
+ /* Get information */
+ RTCTempData->RTCTempP0 = (int16_t)(data_u32[0]);
+ RTCTempData->RTCTempP1 = (int16_t)(data_u32[0] >> 16);
+ RTCTempData->RTCTempP2 = (int32_t)((int32_t)(data_u32[1]) + (RTCTempData->RTCTempDelta*256));
+ RTCTempData->RTCTempP5 = (int16_t)(data_u32[2] >> 16);
+ RTCTempData->RTCTempP6 = (int16_t)(data_u32[3] * pclk_mul);
+ RTCTempData->RTCTempP7 = (int16_t)(data_u32[3] >> 16);
+
+ /* Load data to ACPx register */
+ RTC->ACP0 = (uint16_t)(data_u32[0] & 0xFFFF);
+ RTC->ACP1 = (uint16_t)((data_u32[0] >> 16) & 0xFFFF);
+ RTC->ACP2 = (uint32_t)((int32_t)(data_u32[1]) + (RTCTempData->RTCTempDelta*256));
+ RTC->ACP5 = (uint16_t)((data_u32[2] >> 16) & 0xFFFF);
+ RTC->ACP6 = (uint16_t)((int16_t)(data_u32[3] * pclk_mul));
+ RTC->ACP7 = (uint16_t)((data_u32[3] >> 16) & 0xFFFF);
+ }
+ else
+ {
+ /* Get information */
+ RTCTempData->RTCTempP0 = 0;
+ RTCTempData->RTCTempP1 = 0;
+ RTCTempData->RTCTempP2 = 0;
+ RTCTempData->RTCTempP5 = 0;
+ RTCTempData->RTCTempP6 = 0;
+ RTCTempData->RTCTempP7 = 0;
+ retval |= BIT1;
+ }
+ }
+
+/*----------------------------------- P4 -------------------------------------*/
+ /* Calculate checksum1 */
+ data_u32[0] = *NVR_RTC1_P4;
+ checksum = ~data_u32[0];
+ if (checksum == (*NVR_RTC1_P4_CHKSUM))//checksum1 true
+ {
+ /* Get information */
+ RTCTempData->RTCTempP4 = (int16_t)data_u32[0];
+ RTC->ACP4 = data_u32[0];
+ }
+ else
+ {
+ data_u32[0] = *NVR_RTC2_P4;
+ checksum = ~data_u32[0];
+ if (checksum == (*NVR_RTC2_P4_CHKSUM))//checksum2 true
+ {
+ /* Get information */
+ RTCTempData->RTCTempP4 = (int16_t)data_u32[0];
+ RTC->ACP4 = data_u32[0];
+ }
+ else
+ {
+ RTCTempData->RTCTempP4 = 0;
+
+ retval |= BIT2;
+ }
+ }
+
+/*-------------------------- RTC ACKx parameters -----------------------------*/
+ data_u32[0] = *NVR_RTC1_ACK0;
+ data_u32[1] = *NVR_RTC1_ACK1;
+ data_u32[2] = *NVR_RTC1_ACK2;
+ data_u32[3] = *NVR_RTC1_ACK3;
+ data_u32[4] = *NVR_RTC1_ACK4;
+ checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3] + data_u32[4]);
+ if (checksum == (*NVR_RTC1_ACK_CHKSUM))//checksum1 true
+ {
+ /* Get information */
+ RTCTempData->RTCTempK0 = data_u32[0];
+ RTCTempData->RTCTempK1 = data_u32[1];
+ RTCTempData->RTCTempK2 = data_u32[2];
+ RTCTempData->RTCTempK3 = data_u32[3];
+ RTCTempData->RTCTempK4 = data_u32[4];
+
+ /* Load data to ACKx register */
+ RTC->ACK[0] = data_u32[0];
+ RTC->ACK[1] = data_u32[1];
+ RTC->ACK[2] = data_u32[2];
+ RTC->ACK[3] = data_u32[3];
+ RTC->ACK[4] = data_u32[4];
+ }
+ else
+ {
+ data_u32[0] = *NVR_RTC2_ACK0;
+ data_u32[1] = *NVR_RTC2_ACK1;
+ data_u32[2] = *NVR_RTC2_ACK2;
+ data_u32[3] = *NVR_RTC2_ACK3;
+ data_u32[4] = *NVR_RTC2_ACK4;
+ checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3] + data_u32[4]);
+ if (checksum == (*NVR_RTC2_ACK_CHKSUM))//checksum2 true
+ {
+ /* Get information */
+ RTCTempData->RTCTempK0 = data_u32[0];
+ RTCTempData->RTCTempK1 = data_u32[1];
+ RTCTempData->RTCTempK2 = data_u32[2];
+ RTCTempData->RTCTempK3 = data_u32[3];
+ RTCTempData->RTCTempK4 = data_u32[4];
+
+ /* Load data to ACKx register */
+ RTC->ACK[0] = data_u32[0];
+ RTC->ACK[1] = data_u32[1];
+ RTC->ACK[2] = data_u32[2];
+ RTC->ACK[3] = data_u32[3];
+ RTC->ACK[4] = data_u32[4];
+ }
+ else
+ {
+ /* Get information */
+ RTCTempData->RTCTempK0 = 0;
+ RTCTempData->RTCTempK1 = 0;
+ RTCTempData->RTCTempK2 = 0;
+ RTCTempData->RTCTempK3 = 0;
+ RTCTempData->RTCTempK4 = 0;
+
+ retval |= BIT3;
+ }
+ }
+
+/*-------------------------- RTC ACTI parameters -----------------------------*/
+ data_u32[0] = *NVR_RTC1_ACTI;
+ checksum = ~data_u32[0];
+ if (checksum == (*NVR_RTC1_ACTI_CHKSUM))
+ {
+ /* Get information */
+ RTCTempData->RTCACTI = data_u32[0];
+ /* Load data to ACKx register */
+ RTC->ACTI = data_u32[0];
+ }
+ else
+ {
+ data_u32[0] = *NVR_RTC2_ACTI;
+ checksum = ~data_u32[0];
+ if (checksum == (*NVR_RTC2_ACTI_CHKSUM))
+ {
+ /* Get information */
+ RTCTempData->RTCACTI = data_u32[0];
+ /* Load data to ACKx register */
+ RTC->ACTI = data_u32[0];
+ }
+ else
+ {
+ /* Get information */
+ RTCTempData->RTCACTI = 0;
+
+ retval |= BIT4;
+ }
+ }
+
+/*------------------------- RTC ACKTemp parameters ---------------------------*/
+ data_u32[0] = *NVR_RTC1_ACKTEMP;
+ checksum = ~data_u32[0];
+ if (checksum == (*NVR_RTC1_ACKTEMP_CHKSUM))
+ {
+ /* Get information */
+ RTCTempData->RTCACKTemp = data_u32[0];
+ /* Load data to ACKx register */
+ RTC->ACKTEMP = data_u32[0];
+ }
+ else
+ {
+ data_u32[0] = *NVR_RTC2_ACKTEMP;
+ checksum = ~data_u32[0];
+ if (checksum == (*NVR_RTC2_ACKTEMP_CHKSUM))
+ {
+ /* Get information */
+ RTCTempData->RTCACKTemp = data_u32[0];
+ /* Load data to ACKx register */
+ RTC->ACKTEMP = data_u32[0];
+ }
+ else
+ {
+ /* Get information */
+ RTCTempData->RTCACKTemp = 0;
+
+ retval |= BIT5;
+ }
+ }
+/*--------------------------------- ACF200 -----------------------------------*/
+ RTCTempData->RTCACF200 = (uint32_t)(int32_t)((pclk_mul * 0x320000));
+ RTC->ACF200 = (uint32_t)(int32_t)((pclk_mul * 0x320000));
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+
+ return retval;
+}
+
+/**
+ * @breif Gets Power/Clock Measure result.
+ * @param [out]MEAResult The pointer to struct NVR_PWRMEARES.
+ * @retval 0: Function succeeded.
+ 1: Function failed(Checksum error).
+ */
+uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult)
+{
+ uint32_t avcc_data, dvcc_data, bgp_data, rcl_data, rch_data;
+ uint32_t checksum;
+
+ avcc_data = *NVR_AVCC_MEA1;
+ dvcc_data = *NVR_DVCC_MEA1;
+ bgp_data = *NVR_BGP_MEA1;
+ rcl_data = *NVR_RCL_MEA1;
+ rch_data = *NVR_RCH_MEA1;
+ /* Calculate checksum1 */
+ checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data);
+ if (checksum == (*NVR_PWR_CHECKSUM1))
+ {
+ MEAResult->AVCCMEAResult = avcc_data;
+ MEAResult->DVCCMEAResult = dvcc_data;
+ MEAResult->BGPMEAResult = bgp_data;
+ MEAResult->RCLMEAResult = rcl_data;
+ MEAResult->RCHMEAResult = rch_data;
+ return 0;
+ }
+
+ avcc_data = *NVR_AVCC_MEA2;
+ dvcc_data = *NVR_DVCC_MEA2;
+ bgp_data = *NVR_BGP_MEA2;
+ rcl_data = *NVR_RCL_MEA2;
+ rch_data = *NVR_RCH_MEA2;
+ /* Calculate checksum2 */
+ checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data);
+ if (checksum == (*NVR_PWR_CHECKSUM2))
+ {
+ MEAResult->AVCCMEAResult = avcc_data;
+ MEAResult->DVCCMEAResult = dvcc_data;
+ MEAResult->BGPMEAResult = bgp_data;
+ MEAResult->RCLMEAResult = rcl_data;
+ MEAResult->RCHMEAResult = rch_data;
+ return 0;
+ }
+ else
+ {
+ return 1;
+ }
+}
+
+/**
+ * @breif Gets Chip ID.
+ * @param [out]ChipID The pointer to struct NVR_CHIPID.
+ * @retval 0: Function succeeded.
+ 1: Function failed(Checksum error).
+ */
+uint32_t NVR_GetChipID(NVR_CHIPID *ChipID)
+{
+ uint32_t id0, id1;
+ uint32_t checksum;
+
+ id0 = *NVR_CHIP1_ID0;
+ id1 = *NVR_CHIP1_ID1;
+ /* Calculate checksum1 */
+ checksum = ~(id0 + id1);
+ if (checksum == (*NVR_CHIP1_CHECKSUM))
+ {
+ ChipID->ChipID0 = id0;
+ ChipID->ChipID1 = id1;
+ return 0;
+ }
+
+ id0 = *NVR_CHIP2_ID0;
+ id1 = *NVR_CHIP2_ID1;
+ /* Calculate checksum2 */
+ checksum = ~(id0 + id1);
+ if (checksum == (*NVR_CHIP2_CHECKSUM))
+ {
+ ChipID->ChipID0 = id0;
+ ChipID->ChipID1 = id1;
+ return 0;
+ }
+ else
+ {
+ return 1;
+ }
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_cortex.c b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_cortex.c
new file mode 100644
index 0000000000000000000000000000000000000000..968d5a9df961205e50f39e08bffc99fe1e788ead
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_cortex.c
@@ -0,0 +1,198 @@
+/**
+ ******************************************************************************
+ * @file lib_cortex.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Cortex module driver.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "lib_cortex.h"
+#include "core_cm0.h"
+
+/**
+ * @brief 1. Clears Pending of a device specific External Interrupt.
+ * 2. Sets Priority of a device specific External Interrupt.
+ * 3. Enables a device specific External Interrupt.
+ * @param IRQn: External interrupt number .
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete target Devices IRQ Channels list, please refer to target.h file)
+ * @param Priority: The preemption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 3.
+ * A lower priority value indicates a higher priority
+ * @retval None
+ */
+void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority)
+{
+ /* Check parameters */
+ assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+ assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
+
+ /* Clear Pending Interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+ /* Set Interrupt Priority */
+ NVIC_SetPriority(IRQn, Priority);
+ /* Enable Interrupt in NVIC */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly before calling it.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+ * @retval None
+ */
+void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Check parameters */
+ assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+ /* Enable interrupt in NVIC */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+ * @retval None
+ */
+void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Check parameters */
+ assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+ /* Disable interrupt in NVIC */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiates a system reset request to reset the MCU.
+ * @retval None
+ */
+void CORTEX_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Gets the Pending bit of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+ * @retval 0 Interrupt status is not pending.
+ 1 Interrupt status is pending.
+ */
+uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check parameters */
+ assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+ /* Get priority for Cortex-M0 system or device specific interrupts */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Sets Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+ * @retval None
+ */
+void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check parameters */
+ assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+ * @retval None
+ */
+void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check parameters */
+ assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+ /* Clear interrupt pending */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets the priority of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+ * @retval Interrupt Priority. Value is aligned automatically to the implemented
+ * priority bits of the microcontroller.
+ */
+uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn)
+{
+ /* Get priority for Cortex-M0 system or device specific interrupts */
+ return NVIC_GetPriority(IRQn);
+}
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn: External interrupt number .
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete target Devices IRQ Channels list, please refer to target.h file)
+ * @param Priority: The preemption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 3.
+ * A lower priority value indicates a higher priority
+ * @retval None
+ */
+void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority)
+{
+ /* Check parameters */
+ assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
+ /* Get priority for Cortex-M0 system or device specific interrupts */
+ NVIC_SetPriority(IRQn, Priority);
+}
+
+/**
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum)
+{
+ return SysTick_Config(TicksNum);
+}
+
+/**
+ * @brief Delay N system-clock cycle.
+ * @param nClock < 0x1000000
+ * @retval None
+ */
+void CORTEX_Delay_nSysClock(__IO uint32_t nClock)
+{
+ uint32_t tmp;
+
+ SysTick->LOAD = nClock - 1;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \
+ |SysTick_CTRL_ENABLE_Msk;
+
+ do
+ {
+ tmp = SysTick->CTRL;
+ }
+ while (!(tmp & SysTick_CTRL_COUNTFLAG_Msk));
+
+ SysTick->CTRL = 0;
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/system_target.c b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/system_target.c
new file mode 100644
index 0000000000000000000000000000000000000000..67edacf3102a387e5b27cd3249c6a242727ffd7c
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/system_target.c
@@ -0,0 +1,76 @@
+/**
+ ******************************************************************************
+ * @file system_target.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief system source file.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "target.h"
+
+
+
+/**
+ * @brief Setup the microcontroller system
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ volatile uint32_t i;
+ uint32_t tmp[3];
+
+ ANA->REG0 = 0x30;
+ ANA->REG4 = 0x04;
+ ANA->REG7 = 0x84;
+ ANA->REGA = 0x02;
+ while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
+ ANA->ADCCTRL0 = 0x300000;
+ ANA->ADCCTRL1 = 0xC2;
+ ANA->ADCCTRL2 = 0x8014;
+ LCD->CTRL = 0x84;
+
+ tmp[0] = 0x599A599A;
+ tmp[1] = 0x78000000;
+ tmp[2] = 0x80000000;
+ RTC_WriteRegisters((uint32_t)&RTC->ADCUCALK, tmp, 3);
+}
+
+/**
+ * @brief Initializes registers.
+ * @param None
+ * @retval None
+ */
+void SystemUpdate(void)
+{
+ uint32_t tmp[3];
+
+ ANA->REG0 &= ~0xCE;
+ ANA->REG0 |= 0x30;
+ ANA->REG1 &= ~0x7F;
+ ANA->REG2 &= ~0xC0;
+ ANA->REG3 &= ~0x01;
+ ANA->REG4 |= 0x04;
+ ANA->REG4 &= ~0xFB;
+ ANA->REG5 &= ~0xB0;
+ ANA->REG6 &= ~0x3E;
+ ANA->REG7 |= 0x84;
+ ANA->REG7 &= ~0x7B;
+ ANA->REG8 &= ~0x0C;
+ ANA->REGA |= 0x02;
+ ANA->REGA &= ~0x7D;
+
+ tmp[0] = 0x599A599A;
+ tmp[1] = RTC->ADCMACTL;
+ tmp[1] &= ~0XFF080000;
+ tmp[1] |= 0x78000000;
+ tmp[2] = 0x80000000;
+ RTC_WriteRegisters((uint32_t)&RTC->ADCUCALK, tmp, 3);
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/CMSIS/cmsis_armcc.h b/bsp/v85xxp/Libraries/CMSIS/cmsis_armcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..59f173ac71b996c8615e3c1804963c8b4c311cde
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/cmsis_armcc.h
@@ -0,0 +1,894 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.1.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/bsp/v85xxp/Libraries/CMSIS/cmsis_compiler.h b/bsp/v85xxp/Libraries/CMSIS/cmsis_compiler.h
new file mode 100644
index 0000000000000000000000000000000000000000..94212eb87a94d11bb8346c6fff99d5fbf838c0ac
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/bsp/v85xxp/Libraries/CMSIS/cmsis_gcc.h b/bsp/v85xxp/Libraries/CMSIS/cmsis_gcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..2d9db15a5def3461f91ec54855611284379cde32
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.0.4
+ * @date 09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/v85xxp/Libraries/CMSIS/cmsis_version.h b/bsp/v85xxp/Libraries/CMSIS/cmsis_version.h
new file mode 100644
index 0000000000000000000000000000000000000000..660f612aa31fe2a71cc786af5cac407e41fdd144
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/bsp/v85xxp/Libraries/CMSIS/core_cm0.h b/bsp/v85xxp/Libraries/CMSIS/core_cm0.h
new file mode 100644
index 0000000000000000000000000000000000000000..f929bba07b76a21370be6d560ac5cd9512647bd2
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/core_cm0.h
@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V5.0.5
+ * @date 28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/v85xxp/Libraries/CMSIS/core_cmFunc.h b/bsp/v85xxp/Libraries/CMSIS/core_cmFunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..4a6b5d668379c20236434b18d1bf0d13344986e4
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/core_cmFunc.h
@@ -0,0 +1,616 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return (__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return (__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return (__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return (__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return (__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return (__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return (__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return (__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return (__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return (__regfpscr);
+#else
+ return (0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile("MRS %0, control" : "=r"(result));
+ return (result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile("MSR control, %0" : : "r"(control));
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile("MRS %0, ipsr" : "=r"(result));
+ return (result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile("MRS %0, apsr" : "=r"(result));
+ return (result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile("MRS %0, xpsr" : "=r"(result));
+ return (result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile("MRS %0, psp\n" : "=r"(result));
+ return (result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack));
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile("MRS %0, msp\n" : "=r"(result));
+ return (result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack));
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile("MRS %0, primask" : "=r"(result));
+ return (result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile("MSR primask, %0" : : "r"(priMask));
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile("MRS %0, basepri_max" : "=r"(result));
+ return (result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile("MSR basepri, %0" : : "r"(value));
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile("MRS %0, faultmask" : "=r"(result));
+ return (result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile("MSR faultmask, %0" : : "r"(faultMask));
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile("VMRS %0, fpscr" : "=r"(result));
+ return (result);
+#else
+ return (0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr));
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/v85xxp/Libraries/CMSIS/core_cmInstr.h b/bsp/v85xxp/Libraries/CMSIS/core_cmInstr.h
new file mode 100644
index 0000000000000000000000000000000000000000..1c0b6f6b973386bee578048f37de0c9c41ef494b
--- /dev/null
+++ b/bsp/v85xxp/Libraries/CMSIS/core_cmInstr.h
@@ -0,0 +1,618 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+#if (__CORTEX_M >= 0x03)
+
+ /** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ #define __RBIT __rbit
+
+
+ /** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+ /** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+ /** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+ /** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+ #define __STREXB(value, ptr) __strex(value, ptr)
+
+
+ /** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+ #define __STREXH(value, ptr) __strex(value, ptr)
+
+
+ /** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+ #define __STREXW(value, ptr) __strex(value, ptr)
+
+
+ /** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+ #define __CLREX __clrex
+
+
+ /** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+ #define __SSAT __ssat
+
+
+ /** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+ #define __USAT __usat
+
+
+ /** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+ #define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile("rev %0, %1" : "=r"(result) : "r"(value));
+ return (result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value));
+ return (result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value));
+ return (result);
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+ __ASM volatile("ror %0, %0, %1" : "+r"(op1) : "r"(op2));
+ return (op1);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
+ return (result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr));
+ return (result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr));
+ return (result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr));
+ return (result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile("strexb %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
+ return (result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile("strexh %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
+ return (result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile("strex %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
+ return (result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile("clz %0, %1" : "=r"(result) : "r"(value));
+ return (result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/v85xxp/Libraries/SConscript b/bsp/v85xxp/Libraries/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..acb3ae6670501d234b79dc255681d5149ef842b3
--- /dev/null
+++ b/bsp/v85xxp/Libraries/SConscript
@@ -0,0 +1,30 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Glob('VangoV85xxP_standard_peripheral/Source/*.c')
+src += [cwd + '/CMSIS/Vango/V85xxP/Source/system_target.c']
+src += [cwd + '/CMSIS/Vango/V85xxP/Source/lib_CodeRAM.c']
+src += [cwd + '/CMSIS/Vango/V85xxP/Source/lib_cortex.c']
+src += [cwd + '/CMSIS/Vango/V85xxP/Source/lib_LoadNVR.c']
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += [cwd + '/CMSIS/Vango/V85xxP/Source/GCC/startup_target.S']
+if rtconfig.CROSS_TOOL == 'keil':
+ src += [cwd + '/CMSIS/Vango/V85xxP/Source/Keil5/startup_target.S']
+
+path = [
+ cwd + '/CMSIS/Vango/V85xxP/Include',
+ cwd + '/CMSIS',
+ cwd + '/VangoV85xxP_standard_peripheral/Include',]
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'V85XXP','USE_TARGET_DRIVER']
+
+group = DefineGroup('Vango_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_adc.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_adc.h
new file mode 100644
index 0000000000000000000000000000000000000000..3099c7d289ac0381e7de1770101797935997437c
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_adc.h
@@ -0,0 +1,308 @@
+/**
+ ******************************************************************************
+ * @file lib_adc.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief ADC library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_ADC_H
+#define __LIB_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+ uint32_t Mode;
+ uint32_t ClockSource;
+ uint32_t ClockFrq;
+ uint32_t SkipSample;
+ uint32_t AverageSample;
+ uint32_t TriggerSource;
+ uint32_t Channel;
+ uint32_t ResDivEnable;
+ uint32_t AverageEnable;
+} ADC_InitType;
+
+typedef struct
+{
+ uint32_t THDChannel;
+ uint8_t UpperTHD;
+ uint8_t LowerTHD;
+ uint32_t TriggerSel;
+ uint32_t THDSource;
+} ADCTHD_InitType;
+
+/* Exported constants --------------------------------------------------------*/
+//Mode
+#define ADC_MODE_DC (0UL)
+#define ADC_MODE_AC (1UL)
+#define ADC_MODE_TEMP (2UL)
+#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_DC) ||\
+ ((__MODE__) == ADC_MODE_AC) ||\
+ ((__MODE__) == ADC_MODE_TEMP))
+//ClockSource
+#define ADC_CLKSRC_RCH (0)
+#define ADC_CLKSRC_PLLL ANA_ADCCTRL0_CLKSRCSEL
+#define IS_ADC_CLKSRC(__CLKSRC__) (((__CLKSRC__) == ADC_CLKSRC_RCH) ||\
+ ((__CLKSRC__) == ADC_CLKSRC_PLLL))
+//ClockFrq
+#define ADC_CLKFRQ_HIGH (0UL)
+#define ADC_CLKFRQ_LOW (1UL)
+#define IS_ADC_CLKFRQ(__CLKFRQ__) (((__CLKFRQ__) == ADC_CLKFRQ_HIGH) ||\
+ ((__CLKFRQ__) == ADC_CLKFRQ_LOW))
+//SkipSample
+#define ADC_SKIP_0 (0x0UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos)
+#define ADC_SKIP_4 (0x4UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos)
+#define ADC_SKIP_8 (0x7UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos)
+#define ADC_SKIP_12 (0x12UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos)
+#define IS_ADC_SKIP(__SKIP__) (((__SKIP__) == ADC_SKIP_0) ||\
+ ((__SKIP__) == ADC_SKIP_4) ||\
+ ((__SKIP__) == ADC_SKIP_8) ||\
+ ((__SKIP__) == ADC_SKIP_12))
+//AverageSample
+#define ADC_AVERAGE_2 (0x0UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
+#define ADC_AVERAGE_4 (0x1UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
+#define ADC_AVERAGE_8 (0x2UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
+#define ADC_AVERAGE_16 (0x3UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
+#define ADC_AVERAGE_32 (0x4UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
+#define ADC_AVERAGE_64 (0x5UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
+#define IS_ADC_AVERAG(__AVERAG__) (((__AVERAG__) == ADC_AVERAGE_2) ||\
+ ((__AVERAG__) == ADC_AVERAGE_4) ||\
+ ((__AVERAG__) == ADC_AVERAGE_8) ||\
+ ((__AVERAG__) == ADC_AVERAGE_16) ||\
+ ((__AVERAG__) == ADC_AVERAGE_32) ||\
+ ((__AVERAG__) == ADC_AVERAGE_64))
+//TriggerSource
+#define ADC_TRIGSOURCE_OFF (0x0UL << ANA_ADCCTRL0_AEN_Pos)
+#define ADC_TRIGSOURCE_ITVSITV (0x1UL << ANA_ADCCTRL0_AEN_Pos)
+#define ADC_TRIGSOURCE_WKUSEC (0x2UL << ANA_ADCCTRL0_AEN_Pos)
+#define ADC_TRIGSOURCE_ALARM (0x3UL << ANA_ADCCTRL0_AEN_Pos)
+#define ADC_TRIGSOURCE_TMR0 (0x4UL << ANA_ADCCTRL0_AEN_Pos)
+#define ADC_TRIGSOURCE_TMR1 (0x5UL << ANA_ADCCTRL0_AEN_Pos)
+#define ADC_TRIGSOURCE_TMR2 (0x6UL << ANA_ADCCTRL0_AEN_Pos)
+#define ADC_TRIGSOURCE_TMR3 (0x7UL << ANA_ADCCTRL0_AEN_Pos)
+#define IS_ADC_TRIGSOURCE(__TRIGSOURCE__) (((__TRIGSOURCE__) == ADC_TRIGSOURCE_OFF) ||\
+ ((__TRIGSOURCE__) == ADC_TRIGSOURCE_ITVSITV) ||\
+ ((__TRIGSOURCE__) == ADC_TRIGSOURCE_WKUSEC) ||\
+ ((__TRIGSOURCE__) == ADC_TRIGSOURCE_ALARM) ||\
+ ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR0) ||\
+ ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR1) ||\
+ ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR2) ||\
+ ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR3))
+//Channel
+#define ADC_CHANNEL_NONE (0 << 0UL)
+#define ADC_CHANNEL_GND0 (1 << 0UL)
+#define ADC_CHANNEL_BAT1 (1 << 1UL)
+#define ADC_CHANNEL_BATRTC (1 << 2UL)
+#define ADC_CHANNEL_CH3 (1 << 3UL)
+#define ADC_CHANNEL_CH4 (1 << 4UL)
+#define ADC_CHANNEL_CH5 (1 << 5UL)
+#define ADC_CHANNEL_CH6 (1 << 6UL)
+#define ADC_CHANNEL_CH7 (1 << 7UL)
+#define ADC_CHANNEL_CH8 (1 << 8UL)
+#define ADC_CHANNEL_CH9 (1 << 9UL)
+#define ADC_CHANNEL_TEMP (1 << 10UL)
+#define ADC_CHANNEL_CH11 (1 << 11UL)
+#define ADC_CHANNEL_DVCC (1 << 12UL)
+#define ADC_CHANNEL_GND13 (1 << 13UL)
+#define ADC_CHANNEL_GND14 (1 << 14UL)
+#define ADC_CHANNEL_GND15 (1 << 15UL)
+#define ADC_CHANNEL_DC_Msk (0xFBFFUL)
+#define ADC_CHANNEL_DC_ALL ADC_CHANNEL_DC_Msk
+#define ADC_CHANNEL_AC_Msk (0x0BF8UL)
+#define ADC_CHANNEL_AC_ALL ADC_CHANNEL_AC_Msk
+#define IS_ADC_CHANNEL_GETDATA(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_GND0) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_BAT1) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_BATRTC) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_CH3) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_CH4) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_CH5) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_CH6) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_CH7) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_CH8) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_CH9) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_TEMP) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_CH11) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_DVCC) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_GND13) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_GND14) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_GND15))
+#define IS_ADC_CHANNEL_AC(__CHANNEL__) ((((__CHANNEL__) & ADC_CHANNEL_AC_Msk) != 0UL) &&\
+ (((__CHANNEL__) & ~ADC_CHANNEL_AC_Msk) == 0UL))
+#define IS_ADC_CHANNEL_DC(__CHANNEL__) ((((__CHANNEL__) & ADC_CHANNEL_DC_Msk) != 0UL) &&\
+ (((__CHANNEL__) & ~ADC_CHANNEL_DC_Msk) == 0UL))
+#define IS_ADC_CHANNEL_TEMP(__CHANNEL__) ((__CHANNEL__) == ADC_CHANNEL_TEMP)
+#define IS_ADC_CHANNEL_EN_DC(__CHANNEL__) (((((__CHANNEL__) & ADC_CHANNEL_DC_Msk) != 0UL) && (((__CHANNEL__) & ~ADC_CHANNEL_DC_Msk) == 0UL)) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_NONE))
+#define IS_ADC_CHANNEL_EN_AC(__CHANNEL__) (((((__CHANNEL__) & ADC_CHANNEL_AC_Msk) != 0UL) && (((__CHANNEL__) & ~ADC_CHANNEL_AC_Msk) == 0UL)) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_NONE))
+
+#define ADC_CHANNEL_Pos (0UL)
+#define ADC_CHANNEL_SHIFT (ANA_ADCCTRL2_SCAN_CHx_Pos - ADC_CHANNEL_Pos)
+#define ADC_AVERAGECH_SHIFT (RTC_ADCMACTL_AVERAGE_CHx_Pos - ADC_CHANNEL_Pos)
+#define ADC_RESDIVCH_SHIFT (ANA_ADCCTRL1_RESDIV_CHx_Pos - ADC_CHANNEL_Pos)
+
+//THDChannel
+#define ADC_THDCHANNEL0 (0UL)
+#define ADC_THDCHANNEL1 (1UL)
+#define ADC_THDCHANNEL2 (2UL)
+#define ADC_THDCHANNEL3 (3UL)
+#define IS_ADC_THDCHANNEL(THDCHANNEL) (((THDCHANNEL) == ADC_THDCHANNEL0) ||\
+ ((THDCHANNEL) == ADC_THDCHANNEL1) ||\
+ ((THDCHANNEL) == ADC_THDCHANNEL2) ||\
+ ((THDCHANNEL) == ADC_THDCHANNEL3))
+
+//TriggerSel
+#define ADC_THDSEL_HIGH (0UL)
+#define ADC_THDSEL_RISING (1UL)
+#define ADC_THDSEL_FALLING (2UL)
+#define ADC_THDSEL_BOTH (3UL)
+#define IS_ADC_THDSEL(__THDSEL__) (((__THDSEL__) == ADC_THDSEL_HIGH) ||\
+ ((__THDSEL__) == ADC_THDSEL_RISING) ||\
+ ((__THDSEL__) == ADC_THDSEL_FALLING) ||\
+ ((__THDSEL__) == ADC_THDSEL_BOTH))
+
+//INTMask
+#define ADC_INT_UPPER_TH3 ANA_INTEN_INTEN21
+#define ADC_INT_LOWER_TH3 ANA_INTEN_INTEN20
+#define ADC_INT_UPPER_TH2 ANA_INTEN_INTEN19
+#define ADC_INT_LOWER_TH2 ANA_INTEN_INTEN18
+#define ADC_INT_UPPER_TH1 ANA_INTEN_INTEN17
+#define ADC_INT_LOWER_TH1 ANA_INTEN_INTEN16
+#define ADC_INT_UPPER_TH0 ANA_INTEN_INTEN15
+#define ADC_INT_LOWER_TH0 ANA_INTEN_INTEN14
+#define ADC_INT_AUTODONE ANA_INTEN_INTEN1
+#define ADC_INT_MANUALDONE ANA_INTEN_INTEN0
+#define ADC_INT_Msk (0x3FC003UL)
+#define IS_ADC_INT(__INT__) ((((__INT__) & ADC_INT_Msk) != 0UL) &&\
+ (((__INT__) & ~ADC_INT_Msk) == 0UL))
+
+//INTSTS
+#define ADC_INTSTS_UPPER_TH3 ANA_INTSTS_INTSTS21
+#define ADC_INTSTS_LOWER_TH3 ANA_INTSTS_INTSTS20
+#define ADC_INTSTS_UPPER_TH2 ANA_INTSTS_INTSTS19
+#define ADC_INTSTS_LOWER_TH2 ANA_INTSTS_INTSTS18
+#define ADC_INTSTS_UPPER_TH1 ANA_INTSTS_INTSTS17
+#define ADC_INTSTS_LOWER_TH1 ANA_INTSTS_INTSTS16
+#define ADC_INTSTS_UPPER_TH0 ANA_INTSTS_INTSTS15
+#define ADC_INTSTS_LOWER_TH0 ANA_INTSTS_INTSTS14
+#define ADC_INTSTS_AUTODONE ANA_INTSTS_INTSTS1
+#define ADC_INTSTS_MANUALDONE ANA_INTSTS_INTSTS0
+#define ADC_INTSTS_Msk (0x3FC003UL)
+#define IS_ADC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & ADC_INTSTS_Msk) != 0U) &&\
+ (((__INTFLAGC__) & ~ADC_INTSTS_Msk) == 0U))
+
+#define IS_ADC_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == ADC_INTSTS_UPPER_TH3) ||\
+ ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH3) ||\
+ ((__INTFLAGR__) == ADC_INTSTS_UPPER_TH2) ||\
+ ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH2) ||\
+ ((__INTFLAGR__) == ADC_INTSTS_UPPER_TH1) ||\
+ ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH1) ||\
+ ((__INTFLAGR__) == ADC_INTSTS_UPPER_TH0) ||\
+ ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH0) ||\
+ ((__INTFLAGR__) == ADC_INTSTS_AUTODONE) ||\
+ ((__INTFLAGR__) == ADC_INTSTS_MANUALDONE))
+
+#define ADC_FLAG_CONV_ERR (0x1U << ANA_ADCCTRL2_CONV_ERR_Pos)
+#define ADC_FLAG_CAL_ERR (0x1U << ANA_ADCCTRL2_CAL_ERR_Pos)
+#define ADC_FLAG_CAL_DONE (0x1U << ANA_ADCCTRL2_RTC_CAL_DONE_Pos)
+#define ADC_FLAG_BUSY (0x1U << ANA_ADCCTRL2_BUSY_Pos)
+#define IS_ADC_ADCFLAG(__ADCFLAG__) (((__ADCFLAG__) == ADC_FLAG_CONV_ERR) ||\
+ ((__ADCFLAG__) == ADC_FLAG_CAL_ERR) ||\
+ ((__ADCFLAG__) == ADC_FLAG_CAL_DONE) ||\
+ ((__ADCFLAG__) == ADC_FLAG_BUSY))
+
+#define ADC_FLAG_RCMsk (ADC_FLAG_CONV_ERR|ADC_FLAG_CAL_ERR)
+#define IS_ADC_ADCFLAGC(__ADCFLAG__) ((((__ADCFLAG__) & ADC_FLAG_RCMsk) != 0U) &&\
+ (((__ADCFLAG__) & ~ADC_FLAG_RCMsk) == 0U))
+
+//THDFlag
+#define ADC_THDFLAG_UPPER3 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD3_TRGED_Pos)
+#define ADC_THDFLAG_LOWER3 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD3_TRGED_Pos)
+#define ADC_THDFLAG_UPPER2 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD2_TRGED_Pos)
+#define ADC_THDFLAG_LOWER2 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD2_TRGED_Pos)
+#define ADC_THDFLAG_UPPER1 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD1_TRGED_Pos)
+#define ADC_THDFLAG_LOWER1 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD1_TRGED_Pos)
+#define ADC_THDFLAG_UPPER0 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD0_TRGED_Pos)
+#define ADC_THDFLAG_LOWER0 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD0_TRGED_Pos)
+#define IS_ADC_THDFLAG(__THDFLAG__) (((__THDFLAG__) == ADC_THDFLAG_UPPER3) ||\
+ ((__THDFLAG__) == ADC_THDFLAG_LOWER3) ||\
+ ((__THDFLAG__) == ADC_THDFLAG_UPPER2) ||\
+ ((__THDFLAG__) == ADC_THDFLAG_LOWER2) ||\
+ ((__THDFLAG__) == ADC_THDFLAG_UPPER1) ||\
+ ((__THDFLAG__) == ADC_THDFLAG_LOWER1) ||\
+ ((__THDFLAG__) == ADC_THDFLAG_UPPER0) ||\
+ ((__THDFLAG__) == ADC_THDFLAG_LOWER0))
+
+#define IS_ADC_BATDIV(__BATDIV__) (((__BATDIV__) == ADC_BAT_CAPDIV) ||\
+ ((__BATDIV__) == ADC_BAT_RESDIV))
+
+/* ADC_GetVoltage */
+//Mode
+#define ADC_3V_ADCCHx_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None
+#define ADC_3V_ADCCHx_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive
+#define ADC_3V_BAT1_RESDIV (0x002UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive
+#define ADC_3V_BATRTC_RESDIV (0x003UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive
+#define ADC_5V_ADCCHx_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None
+#define ADC_5V_ADCCHx_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive
+#define ADC_5V_BAT1_RESDIV (0x102UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive
+#define ADC_5V_BATRTC_RESDIV (0x103UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive
+#define ADC_TEMP (0x1000UL) // Temperature ; Channel: ADC_CHANNEL_TEMP
+#define IS_ADCVOL_MODE(__MODE__) (((__MODE__) == ADC_3V_ADCCHx_NODIV) ||\
+ ((__MODE__) == ADC_3V_ADCCHx_RESDIV) ||\
+ ((__MODE__) == ADC_3V_BAT1_RESDIV) ||\
+ ((__MODE__) == ADC_3V_BATRTC_RESDIV) ||\
+ ((__MODE__) == ADC_5V_ADCCHx_NODIV) ||\
+ ((__MODE__) == ADC_5V_ADCCHx_RESDIV) ||\
+ ((__MODE__) == ADC_5V_BAT1_RESDIV) ||\
+ ((__MODE__) == ADC_5V_BATRTC_RESDIV) ||\
+ ((__MODE__) == ADC_TEMP))
+
+/* Exported Functions ------------------------------------------------------- */
+/* ADC Exported Functions Group1:
+ (De)Initialization -------------------------*/
+void ADC_DeInit(void);
+void ADC_StructInit(ADC_InitType* ADC_InitStruct);
+void ADC_Init(ADC_InitType* ADC_InitStruct);
+/* ADC Exported Functions Group2:
+ ADC Configuration --------------*/
+void ADC_THDInit(ADCTHD_InitType* ADC_THDStruct);
+void ADC_THDStructInit(ADCTHD_InitType* ADC_THDStruct);
+void ADC_Calibration(void);
+/* ADC Exported Functions Group3:
+ Get NVR Info, Calculate datas --------------*/
+uint32_t ADC_CalculateValue(uint32_t Mode, int16_t adc_data, int16_t *value);
+/* ADC Exported Functions Group4:
+ Interrupt (flag) ---------------------------*/
+int16_t ADC_GetADCConversionValue(uint32_t Channel);
+void ADC_INTConfig(uint32_t INTMask, uint32_t NewState);
+uint8_t ADC_GetFlag(uint32_t FlagMask);
+void ADC_ClearFlag(uint32_t FlagMask);
+uint8_t ADC_GetINTStatus(uint32_t INTMask);
+void ADC_ClearINTStatus(uint32_t INTMask);
+uint8_t ADC_GetTHDFlag(uint32_t THDFlagMask);
+
+/* ADC Exported Functions Group5:
+ MISC Configuration -------------------------*/
+void ADC_Cmd(uint32_t NewState);
+void ADC_LowerTHDCmd(uint32_t THDChannel,uint32_t NewState);
+void ADC_UpperTHDCmd(uint32_t THDChannel,uint32_t NewState);
+void ADC_StartManual(void);
+void ADC_WaitForManual(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_ADC_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_adc_tiny.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_adc_tiny.h
new file mode 100644
index 0000000000000000000000000000000000000000..7988ffb96f0843c2e109cc4eaf70f0578aec65b3
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_adc_tiny.h
@@ -0,0 +1,81 @@
+/**
+ ******************************************************************************
+ * @file lib_adc_tiny.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief ADC_TINY library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_ADC_TINY_H
+#define __LIB_ADC_TINY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+ uint32_t SignalSel;
+ uint32_t ADTREF1;
+ uint32_t ADTREF2;
+ uint32_t ADTREF3;
+} TADCInitType;
+
+//SelADT
+#define ADCTINY_SIGNALSEL_IOE6 0
+#define ADCTINY_SIGNALSEL_IOE7 ANA_REGF_ADTSEL
+#define IS_ADCTINY_SELADT(__SELADT__) (((__SELADT__) == ADCTINY_SIGNALSEL_IOE6) ||\
+ ((__SELADT__) == ADCTINY_SIGNALSEL_IOE7))
+
+//ADTREF1
+#define ADCTINY_REF1_0_9 0
+#define ADCTINY_REF1_0_7 ANA_REGF_ADTREF1SEL
+#define IS_ADCTINY_ADTREF1(__ADTREF1__) (((__ADTREF1__) == ADCTINY_REF1_0_9) ||\
+ ((__ADTREF1__) == ADCTINY_REF1_0_7))
+
+//ADTREF2
+#define ADCTINY_REF2_1_8 0
+#define ADCTINY_REF2_1_6 ANA_REGF_ADTREF2SEL
+#define IS_ADCTINY_ADTREF2(__ADTREF2__) (((__ADTREF2__) == ADCTINY_REF2_1_8) ||\
+ ((__ADTREF2__) == ADCTINY_REF2_1_6))
+
+//ADTREF3
+#define ADCTINY_REF3_2_7 0
+#define ADCTINY_REF3_2_5 ANA_REGF_ADTREF3SEL
+#define IS_ADCTINY_ADTREF3(__ADTREF3__) (((__ADTREF3__) == ADCTINY_REF3_2_7) ||\
+ ((__ADTREF3__) == ADCTINY_REF3_2_5))
+
+//THSel
+#define ADCTINY_THSEL_0 (0x00UL << ANA_MISC_TADCTH_Pos)
+#define ADCTINY_THSEL_1 (0x01UL << ANA_MISC_TADCTH_Pos)
+#define ADCTINY_THSEL_2 (0x02UL << ANA_MISC_TADCTH_Pos)
+#define ADCTINY_THSEL_3 (0x03UL << ANA_MISC_TADCTH_Pos)
+#define IS_ADCTINY_THSEL(__THSEL__) (((__THSEL__) == ADCTINY_THSEL_0) ||\
+ ((__THSEL__) == ADCTINY_THSEL_1) ||\
+ ((__THSEL__) == ADCTINY_THSEL_2) ||\
+ ((__THSEL__) == ADCTINY_THSEL_3))
+
+/* Exported Functions ------------------------------------------------------- */
+void TADC_DeInit(void);
+void TADC_StructInit(TADCInitType* TADC_InitStruct);
+void TADC_Init(TADCInitType* TADC_InitStruct);
+void TADC_Cmd(uint32_t NewState);
+uint8_t TADC_GetOutput(void);
+void TADC_IntTHConfig(uint32_t THSel);
+void TADC_INTConfig(uint32_t NewState);
+uint8_t TADC_GetINTStatus(void);
+void TADC_ClearINTStatus(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_ADC_TINY_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_ana.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_ana.h
new file mode 100644
index 0000000000000000000000000000000000000000..104dc2c870b54340da0ba81923926c2d4befb268
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_ana.h
@@ -0,0 +1,118 @@
+/**
+ ******************************************************************************
+ * @file lib_ana.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Analog library.
+ ******************************************************************************
+ * @attention
+ *
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_ANA_H
+#define __LIB_ANA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+/***** StatusMask (ANA_GetStatus) *****/
+#define ANA_STATUS_AVCCLV ANA_CMPOUT_AVCCLV
+#define ANA_STATUS_VDCINDROP ANA_CMPOUT_VDCINDROP
+#define ANA_STATUS_VDDALARM ANA_CMPOUT_VDDALARM
+#define ANA_STATUS_COMP2 ANA_CMPOUT_CMP2
+#define ANA_STATUS_COMP1 ANA_CMPOUT_CMP1
+#define ANA_STATUS_LOCKL ANA_CMPOUT_LOCKL
+#define ANA_STATUS_LOCKH ANA_CMPOUT_LOCKH
+
+/***** IntMask (ANA_GetINTStatus / ANA_ClearINTStatus / ANA_INTConfig) *****/
+#define ANA_INT_UPPER_TH3 ANA_INTEN_INTEN21
+#define ANA_INT_LOWER_TH3 ANA_INTEN_INTEN20
+#define ANA_INT_UPPER_TH2 ANA_INTEN_INTEN19
+#define ANA_INT_LOWER_TH2 ANA_INTEN_INTEN18
+#define ANA_INT_UPPER_TH1 ANA_INTEN_INTEN17
+#define ANA_INT_LOWER_TH1 ANA_INTEN_INTEN16
+#define ANA_INT_UPPER_TH0 ANA_INTEN_INTEN15
+#define ANA_INT_LOWER_TH0 ANA_INTEN_INTEN14
+#define ANA_INT_TADC_OVER ANA_INTEN_INTEN13
+#define ANA_INT_REGERR ANA_INTEN_INTEN12
+#define ANA_INT_SLPFAIL_VDCIN ANA_INTEN_INTEN11
+#define ANA_INT_AVCCLV ANA_INTEN_INTEN10
+#define ANA_INT_VDCINDROP ANA_INTEN_INTEN8
+#define ANA_INT_VDDALARM ANA_INTEN_INTEN7
+#define ANA_INT_COMP2 ANA_INTEN_INTEN3
+#define ANA_INT_COMP1 ANA_INTEN_INTEN2
+#define ANA_INT_ADCA ANA_INTEN_INTEN1
+#define ANA_INT_ADCM ANA_INTEN_INTEN0
+#define ANA_INT_Msk (ANA_INTSTS_INTSTS21 \
+ |ANA_INTSTS_INTSTS20 \
+ |ANA_INTSTS_INTSTS19 \
+ |ANA_INTSTS_INTSTS18 \
+ |ANA_INTSTS_INTSTS17 \
+ |ANA_INTSTS_INTSTS16 \
+ |ANA_INTSTS_INTSTS15 \
+ |ANA_INTSTS_INTSTS14 \
+ |ANA_INTSTS_INTSTS13 \
+ |ANA_INTSTS_INTSTS12 \
+ |ANA_INTSTS_INTSTS11 \
+ |ANA_INTSTS_INTSTS10 \
+ |ANA_INTSTS_INTSTS8 \
+ |ANA_INTSTS_INTSTS7 \
+ |ANA_INTSTS_INTSTS3 \
+ |ANA_INTSTS_INTSTS2 \
+ |ANA_INTSTS_INTSTS1 \
+ |ANA_INTSTS_INTSTS0)
+
+/****************************** ANA Instances *********************************/
+#define IS_ANA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ANA)
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_ANA_STATUS(__STATUS__) (((__STATUS__) == ANA_STATUS_AVCCLV) ||\
+ ((__STATUS__) == ANA_STATUS_VDCINDROP) ||\
+ ((__STATUS__) == ANA_STATUS_VDDALARM) ||\
+ ((__STATUS__) == ANA_STATUS_COMP2) ||\
+ ((__STATUS__) == ANA_STATUS_COMP1) ||\
+ ((__STATUS__) == ANA_STATUS_LOCKL) ||\
+ ((__STATUS__) == ANA_STATUS_LOCKH))
+
+#define IS_ANA_INTSTSR(__INTSTSR__) (((__INTSTSR__) == ANA_INT_UPPER_TH3) ||\
+ ((__INTSTSR__) == ANA_INT_LOWER_TH3) ||\
+ ((__INTSTSR__) == ANA_INT_UPPER_TH2) ||\
+ ((__INTSTSR__) == ANA_INT_LOWER_TH2) ||\
+ ((__INTSTSR__) == ANA_INT_UPPER_TH1) ||\
+ ((__INTSTSR__) == ANA_INT_LOWER_TH1) ||\
+ ((__INTSTSR__) == ANA_INT_UPPER_TH0) ||\
+ ((__INTSTSR__) == ANA_INT_LOWER_TH0) ||\
+ ((__INTSTSR__) == ANA_INT_TADC_OVER) ||\
+ ((__INTSTSR__) == ANA_INT_REGERR) ||\
+ ((__INTSTSR__) == ANA_INT_SLPFAIL_VDCIN) ||\
+ ((__INTSTSR__) == ANA_INT_AVCCLV) ||\
+ ((__INTSTSR__) == ANA_INT_VDCINDROP) ||\
+ ((__INTSTSR__) == ANA_INT_VDDALARM) ||\
+ ((__INTSTSR__) == ANA_INT_COMP2) ||\
+ ((__INTSTSR__) == ANA_INT_COMP1) ||\
+ ((__INTSTSR__) == ANA_INT_ADCA) ||\
+ ((__INTSTSR__) == ANA_INT_ADCM))
+
+#define IS_ANA_INTSTSC(__INTSTSC__) ((((__INTSTSC__) & ANA_INT_Msk) != 0U) &&\
+ (((__INTSTSC__) & ~ANA_INT_Msk) == 0U))
+
+#define IS_ANA_INT(__INT__) IS_ANA_INTSTSC(__INT__)
+
+/* Exported Functions ------------------------------------------------------- */
+uint8_t ANA_GetStatus(uint32_t StatusMask);
+uint8_t ANA_GetINTStatus(uint32_t IntMask);
+void ANA_ClearINTStatus(uint32_t IntMask);
+void ANA_INTConfig(uint32_t IntMask, uint32_t NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_ANA_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_clk.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..b7b11c75229afb879b4f7f22c7bcde4a16ba0fba
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_clk.h
@@ -0,0 +1,338 @@
+/**
+ ******************************************************************************
+ * @file lib_clk.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Clock library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_CLK_H
+#define __LIB_CLK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+/* PLLL Configure */
+typedef struct
+{
+ uint32_t Source;
+ uint32_t State;
+ uint32_t Frequency;
+} PLLL_ConfTypeDef;
+
+/* PLLH Configure */
+typedef struct
+{
+ uint32_t Source;
+ uint32_t State;
+ uint32_t Frequency;
+} PLLH_ConfTypeDef;
+
+/* RCH Configure */
+typedef struct
+{
+ uint32_t State;
+} RCH_ConfTypeDef;
+
+/* XTALH Configure */
+typedef struct
+{
+ uint32_t State;
+} XTALH_ConfTypeDef;
+
+/* RTCCLK Configure */
+typedef struct
+{
+ uint32_t Source;
+ uint32_t Divider;
+} RTCCLK_ConfTypeDef;
+
+/* HCLK Configure */
+typedef struct
+{
+ uint32_t Divider; /* 1 ~ 256 */
+} HCLK_ConfTypeDef;
+
+/* PCLK Configure */
+typedef struct
+{
+ uint32_t Divider; /* 1 ~ 256 */
+} PCLK_ConfTypeDef;
+
+/* Clock Configure */
+typedef struct
+{
+ uint32_t ClockType; /* The clock to be configured */
+
+ uint32_t AHBSource;
+
+ PLLL_ConfTypeDef PLLL;
+
+ PLLH_ConfTypeDef PLLH;
+
+ XTALH_ConfTypeDef XTALH;
+
+ RTCCLK_ConfTypeDef RTCCLK;
+
+ HCLK_ConfTypeDef HCLK;
+
+ PCLK_ConfTypeDef PCLK;
+
+} CLK_InitTypeDef;
+
+/************** Bits definition for ANA_REG9 register ******************/
+#define ANA_REG9_PLLLSEL_26M (0x0U << ANA_REG9_PLLLSEL_Pos)
+#define ANA_REG9_PLLLSEL_13M (0x1U << ANA_REG9_PLLLSEL_Pos)
+#define ANA_REG9_PLLLSEL_6_5M (0x2U << ANA_REG9_PLLLSEL_Pos)
+#define ANA_REG9_PLLLSEL_3_2M (0x3U << ANA_REG9_PLLLSEL_Pos)
+#define ANA_REG9_PLLLSEL_1_6M (0x4U << ANA_REG9_PLLLSEL_Pos)
+#define ANA_REG9_PLLLSEL_800K (0x5U << ANA_REG9_PLLLSEL_Pos)
+#define ANA_REG9_PLLLSEL_400K (0x6U << ANA_REG9_PLLLSEL_Pos)
+#define ANA_REG9_PLLLSEL_200K (0x7U << ANA_REG9_PLLLSEL_Pos)
+#define ANA_REG9_PLLHSEL_X2 (0xCU << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X2_5 (0xDU << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X3 (0xEU << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X3_5 (0xFU << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X4 (0x0U << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X4_5 (0x1U << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X5 (0x2U << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X5_5 (0x3U << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X6 (0x4U << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X6_5 (0x5U << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X7 (0x6U << ANA_REG9_PLLHSEL_Pos)
+#define ANA_REG9_PLLHSEL_X7_5 (0x7U << ANA_REG9_PLLHSEL_Pos)
+
+/************** Bits definition for MISC2_CLKSEL register ******************/
+#define MISC2_CLKSEL_CLKSEL_RCOH (0x0U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000000 */
+#define MISC2_CLKSEL_CLKSEL_XOH (0x1U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000001 */
+#define MISC2_CLKSEL_CLKSEL_PLLH (0x2U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000002 */
+#define MISC2_CLKSEL_CLKSEL_RTCCLK (0x3U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000003 */
+#define MISC2_CLKSEL_CLKSEL_PLLL (0x4U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000004 */
+
+/***** ClockType *****/
+#define CLK_TYPE_MSk (0xFFUL)
+#define CLK_TYPE_ALL CLK_TYPE_MSk
+#define CLK_TYPE_AHBSRC (0x01UL) /* AHB Clock source to configure */
+#define CLK_TYPE_PLLL (0x02UL) /* PLLL to configure */
+#define CLK_TYPE_PLLH (0x04UL) /* PLLH to configure */
+#define CLK_TYPE_XTALH (0x08UL) /* XTALH to configure */
+#define CLK_TYPE_RTCCLK (0x20UL) /* RTCCLK to configure */
+#define CLK_TYPE_HCLK (0x40UL) /* AHB Clock to configure */
+#define CLK_TYPE_PCLK (0x80UL) /* APB Clock to configure */
+
+/***** AHBSource *****/
+#define CLK_AHBSEL_6_5MRC (0x0U << MISC2_CLKSEL_CLKSEL_Pos)
+#define CLK_AHBSEL_6_5MXTAL (0x1U << MISC2_CLKSEL_CLKSEL_Pos)
+#define CLK_AHBSEL_HSPLL (0x2U << MISC2_CLKSEL_CLKSEL_Pos)
+#define CLK_AHBSEL_RTCCLK (0x3U << MISC2_CLKSEL_CLKSEL_Pos)
+#define CLK_AHBSEL_LSPLL (0x4U << MISC2_CLKSEL_CLKSEL_Pos)
+
+/***** PLLL_ConfTypeDef PLLL *****/
+/* PLLL.Source */
+#define CLK_PLLLSRC_RCL PMU_CONTROL_PLLL_SEL
+#define CLK_PLLLSRC_XTALL (0)
+/* PLLL.State */
+#define CLK_PLLL_ON ANA_REG3_PLLLPDN
+#define CLK_PLLL_OFF (0)
+/* PLLL.Frequency */
+#define CLK_PLLL_26_2144MHz ANA_REG9_PLLLSEL_26M
+#define CLK_PLLL_13_1072MHz ANA_REG9_PLLLSEL_13M
+#define CLK_PLLL_6_5536MHz ANA_REG9_PLLLSEL_6_5M
+#define CLK_PLLL_3_2768MHz ANA_REG9_PLLLSEL_3_2M
+#define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M
+#define CLK_PLLL_0_8192MHz ANA_REG9_PLLLSEL_800K
+#define CLK_PLLL_0_4096MHz ANA_REG9_PLLLSEL_400K
+#define CLK_PLLL_0_2048MHz ANA_REG9_PLLLSEL_200K
+
+/***** PLLH_ConfTypeDef PLLH *****/
+/* PLLH.Source */
+#define CLK_PLLHSRC_RCH (0)
+#define CLK_PLLHSRC_XTALH PMU_CONTROL_PLLH_SEL
+/* PLLH.State */
+#define CLK_PLLH_ON ANA_REG3_PLLHPDN
+#define CLK_PLLH_OFF (0)
+/* PLLH.Frequency */
+#define CLK_PLLH_13_1072MHz ANA_REG9_PLLHSEL_X2
+#define CLK_PLLH_16_384MHz ANA_REG9_PLLHSEL_X2_5
+#define CLK_PLLH_19_6608MHz ANA_REG9_PLLHSEL_X3
+#define CLK_PLLH_22_9376MHz ANA_REG9_PLLHSEL_X3_5
+#define CLK_PLLH_26_2144MHz ANA_REG9_PLLHSEL_X4
+#define CLK_PLLH_29_4912MHz ANA_REG9_PLLHSEL_X4_5
+#define CLK_PLLH_32_768MHz ANA_REG9_PLLHSEL_X5
+#define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5
+#define CLK_PLLH_39_3216MHz ANA_REG9_PLLHSEL_X6
+#define CLK_PLLH_42_5984MHz ANA_REG9_PLLHSEL_X6_5
+#define CLK_PLLH_45_8752MHz ANA_REG9_PLLHSEL_X7
+#define CLK_PLLH_49_152MHz ANA_REG9_PLLHSEL_X7_5
+
+/* XTALH_ConfTypeDef XTALH */
+/* XTALH.State */
+#define CLK_XTALH_ON ANA_REG3_XOHPDN
+#define CLK_XTALH_OFF (0)
+
+/* RTCCLK Configure */
+/* RTCCLK.Source */
+#define CLK_RTCCLKSRC_XTALL (0)
+#define CLK_RTCCLKSRC_RCL (PMU_CONTROL_RTCCLK_SEL)
+/* RTCCLK.Divider */
+#define CLK_RTCCLKDIV_1 (RTC_PSCA_PSCA_0)
+#define CLK_RTCCLKDIV_4 (RTC_PSCA_PSCA_1)
+
+//AHB Periphral
+#define CLK_AHBPERIPHRAL_DMA MISC2_HCLKEN_DMA
+#define CLK_AHBPERIPHRAL_GPIO MISC2_HCLKEN_GPIO
+#define CLK_AHBPERIPHRAL_LCD MISC2_HCLKEN_LCD
+#define CLK_AHBPERIPHRAL_CRYPT MISC2_HCLKEN_CRYPT
+#define CLK_AHBPERIPHRAL_ALL (MISC2_HCLKEN_DMA \
+ |MISC2_HCLKEN_GPIO \
+ |MISC2_HCLKEN_LCD \
+ |MISC2_HCLKEN_CRYPT)
+
+//APB Periphral
+#define CLK_APBPERIPHRAL_DMA MISC2_PCLKEN_DMA
+#define CLK_APBPERIPHRAL_I2C MISC2_PCLKEN_I2C
+#define CLK_APBPERIPHRAL_SPI1 MISC2_PCLKEN_SPI1
+#define CLK_APBPERIPHRAL_UART0 MISC2_PCLKEN_UART0
+#define CLK_APBPERIPHRAL_UART1 MISC2_PCLKEN_UART1
+#define CLK_APBPERIPHRAL_UART2 MISC2_PCLKEN_UART2
+#define CLK_APBPERIPHRAL_UART3 MISC2_PCLKEN_UART3
+#define CLK_APBPERIPHRAL_UART4 MISC2_PCLKEN_UART4
+#define CLK_APBPERIPHRAL_UART5 MISC2_PCLKEN_UART5
+#define CLK_APBPERIPHRAL_ISO78160 MISC2_PCLKEN_ISO78160
+#define CLK_APBPERIPHRAL_ISO78161 MISC2_PCLKEN_ISO78161
+#define CLK_APBPERIPHRAL_TIMER MISC2_PCLKEN_TIMER
+#define CLK_APBPERIPHRAL_MISC MISC2_PCLKEN_MISC
+#define CLK_APBPERIPHRAL_MISC2 MISC2_PCLKEN_MISC2
+#define CLK_APBPERIPHRAL_PMU MISC2_PCLKEN_PMU
+#define CLK_APBPERIPHRAL_RTC MISC2_PCLKEN_RTC
+#define CLK_APBPERIPHRAL_ANA MISC2_PCLKEN_ANA
+#define CLK_APBPERIPHRAL_U32K0 MISC2_PCLKEN_U32K0
+#define CLK_APBPERIPHRAL_U32K1 MISC2_PCLKEN_U32K1
+#define CLK_APBPERIPHRAL_SPI2 MISC2_PCLKEN_SPI2
+#define CLK_APBPERIPHRAL_ALL (MISC2_PCLKEN_DMA \
+ |MISC2_PCLKEN_I2C \
+ |MISC2_PCLKEN_SPI1 \
+ |MISC2_PCLKEN_UART0 \
+ |MISC2_PCLKEN_UART1 \
+ |MISC2_PCLKEN_UART2 \
+ |MISC2_PCLKEN_UART3 \
+ |MISC2_PCLKEN_UART4 \
+ |MISC2_PCLKEN_UART5 \
+ |MISC2_PCLKEN_ISO78160 \
+ |MISC2_PCLKEN_ISO78161 \
+ |MISC2_PCLKEN_TIMER \
+ |MISC2_PCLKEN_MISC1 \
+ |MISC2_PCLKEN_MISC2 \
+ |MISC2_PCLKEN_PMU \
+ |MISC2_PCLKEN_RTC \
+ |MISC2_PCLKEN_ANA \
+ |MISC2_PCLKEN_U32K0 \
+ |MISC2_PCLKEN_U32K1 \
+ |MISC2_PCLKEN_SPI2 \
+ |MISC2_PCLKEN_SPI3)
+
+/***** PLLStatus (CLK_GetPLLLockStatus) *****/
+#define CLK_STATUS_LOCKL ANA_CMPOUT_LOCKL
+#define CLK_STATUS_LOCKH ANA_CMPOUT_LOCKH
+
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_CLK_TYPE(__TYPE__) ((((__TYPE__) & CLK_TYPE_MSk) != 0UL) &&\
+ (((__TYPE__) & ~CLK_TYPE_MSk) == 0UL))
+
+#define IS_CLK_AHBSRC(__AHBSRC__) (((__AHBSRC__) == CLK_AHBSEL_6_5MRC) ||\
+ ((__AHBSRC__) == CLK_AHBSEL_6_5MXTAL) ||\
+ ((__AHBSRC__) == CLK_AHBSEL_HSPLL) ||\
+ ((__AHBSRC__) == CLK_AHBSEL_RTCCLK) ||\
+ ((__AHBSRC__) == CLK_AHBSEL_LSPLL))
+
+#define IS_CLK_PLLLSRC(__PLLLSRC__) (((__PLLLSRC__) == CLK_PLLLSRC_RCL) ||\
+ ((__PLLLSRC__) == CLK_PLLLSRC_XTALL))
+
+#define IS_CLK_PLLLSTA(__PLLLSTA__) (((__PLLLSTA__) == CLK_PLLL_ON) ||\
+ ((__PLLLSTA__) == CLK_PLLL_OFF))
+
+#define IS_CLK_PLLLFRQ(__PLLLFRQ__) (((__PLLLFRQ__) == CLK_PLLL_26_2144MHz) ||\
+ ((__PLLLFRQ__) == CLK_PLLL_13_1072MHz) ||\
+ ((__PLLLFRQ__) == CLK_PLLL_6_5536MHz) ||\
+ ((__PLLLFRQ__) == CLK_PLLL_3_2768MHz) ||\
+ ((__PLLLFRQ__) == CLK_PLLL_1_6384MHz) ||\
+ ((__PLLLFRQ__) == CLK_PLLL_0_8192MHz) ||\
+ ((__PLLLFRQ__) == CLK_PLLL_0_4096MHz) ||\
+ ((__PLLLFRQ__) == CLK_PLLL_0_2048MHz))
+
+#define IS_CLK_PLLHSRC(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLHSRC_RCH) ||\
+ ((__PLLHSRC__) == CLK_PLLHSRC_XTALH))
+
+#define IS_CLK_PLLHSTA(__PLLHSTA__) (((__PLLHSTA__) == CLK_PLLH_ON) ||\
+ ((__PLLHSTA__) == CLK_PLLH_OFF))
+
+#define IS_CLK_PLLHFRQ(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLH_13_1072MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_16_384MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_19_6608MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_22_9376MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_26_2144MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_29_4912MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_32_768MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_36_0448MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_39_3216MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_42_5984MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_45_8752MHz) ||\
+ ((__PLLHSRC__) == CLK_PLLH_49_152MHz))
+
+#define IS_CLK_XTALHSTA(__XTALHSTA__) (((__XTALHSTA__) == CLK_XTALH_ON) ||\
+ ((__XTALHSTA__) == CLK_XTALH_OFF))
+
+#define IS_CLK_RTCSRC(__RTCSRC__) (((__RTCSRC__) == CLK_RTCCLKSRC_XTALL) ||\
+ ((__RTCSRC__) == CLK_RTCCLKSRC_RCL))
+
+#define IS_CLK_RTCDIV(__RTCDIV__) (((__RTCDIV__) == CLK_RTCCLKDIV_1) ||\
+ ((__RTCDIV__) == CLK_RTCCLKDIV_4))
+
+#define IS_CLK_HCLKDIV(__HCLKDIV__) (((__HCLKDIV__) > 0UL) &&\
+ ((__HCLKDIV__) < 257UL))
+
+#define IS_CLK_PCLKDIV(__PCLKDIV__) (((__PCLKDIV__) > 0UL) &&\
+ ((__PCLKDIV__) < 257UL))
+
+#define IS_CLK_AHBPERIPHRAL(__AHBPERIPHRAL__) ((((__AHBPERIPHRAL__) & CLK_AHBPERIPHRAL_ALL) != 0UL) &&\
+ (((__AHBPERIPHRAL__) & ~CLK_AHBPERIPHRAL_ALL) == 0UL))
+
+#define IS_CLK_APBPERIPHRAL(__APBPERIPHRAL__) ((((__APBPERIPHRAL__) & CLK_APBPERIPHRAL_ALL) != 0UL) &&\
+ (((__APBPERIPHRAL__) & ~CLK_APBPERIPHRAL_ALL) == 0UL))
+
+#define IS_CLK_PLLLOCK(__PLLLOCK__) (((__PLLLOCK__) == ANA_CMPOUT_LOCKL) ||\
+ ((__PLLLOCK__) == ANA_CMPOUT_LOCKH))
+/* Exported Functions ------------------------------------------------------- */
+/* CLK Exported Functions Group1:
+ Initialization and functions ---------------*/
+void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct);
+
+/* CLK Exported Functions Group2:
+ Peripheral Control -------------------------*/
+void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState);
+void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState);
+/* CLK Exported Functions Group3:
+ Get clock/configuration information --------*/
+uint32_t CLK_GetHCLKFreq(void);
+uint32_t CLK_GetPCLKFreq(void);
+uint32_t CLK_GetPLLLFreq(void);
+void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct);
+uint8_t CLK_GetXTALHStatus(void);
+uint8_t CLK_GetXTALLStatus(void);
+uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_CLK_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_cmp.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_cmp.h
new file mode 100644
index 0000000000000000000000000000000000000000..252aa2ef6642acf7661f7ccaab31320fc3d3ea43
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_cmp.h
@@ -0,0 +1,205 @@
+/**
+ ******************************************************************************
+ * @file lib_cmp.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief CMP library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_CMP_H
+#define __LIB_CMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+/* CMP Time struct */
+typedef struct
+{
+ uint32_t DebSel;
+ uint32_t SignalSourceSel;
+ uint32_t BiasSel;
+} CMP_TypeDef;
+
+typedef struct
+{
+ uint32_t ModeSel;
+ uint32_t CheckPeriod;
+ uint32_t CheckNum;
+} CMP_CountTypeDef;
+
+typedef struct
+{
+ uint32_t DebSel;
+ uint32_t OutputSel;
+} CMP_OutputTypeDef;
+
+typedef struct
+{
+ uint32_t INTNumSel;
+ uint32_t SubSel;
+ uint32_t THRNum;
+} CMP_INTTypeDef;
+
+/* Macros --------------------------------------------------------------------*/
+
+/***** CMP_DEBConfig *****/
+//CMPx
+#define CMP_1 (0x00U)
+#define CMP_2 (0x02U)
+#define IS_CMP(__CMP__) (((__CMP__) == CMP_1) || ((__CMP__) == CMP_2))
+/************** Bits definition for ANA_REG2 register ******************/
+#define ANA_REG2_CMP1SEL_0 (0x0U << ANA_REG2_CMP1SEL_Pos)
+#define ANA_REG2_CMP1SEL_1 (0x1U << ANA_REG2_CMP1SEL_Pos)
+#define ANA_REG2_CMP1SEL_2 (0x2U << ANA_REG2_CMP1SEL_Pos)
+#define ANA_REG2_CMP1SEL_3 (0x3U << ANA_REG2_CMP1SEL_Pos)
+#define ANA_REG2_CMP2SEL_0 (0x0U << ANA_REG2_CMP2SEL_Pos)
+#define ANA_REG2_CMP2SEL_1 (0x1U << ANA_REG2_CMP2SEL_Pos)
+#define ANA_REG2_CMP2SEL_2 (0x2U << ANA_REG2_CMP2SEL_Pos)
+#define ANA_REG2_CMP2SEL_3 (0x3U << ANA_REG2_CMP2SEL_Pos)
+/************** Bits definition for ANA_REG5 register ******************/
+#define ANA_REG5_CMP1IT_0 (0x0U << ANA_REG5_CMP1IT_Pos)
+#define ANA_REG5_CMP1IT_1 (0x1U << ANA_REG5_CMP1IT_Pos)
+#define ANA_REG5_CMP1IT_2 (0x2U << ANA_REG5_CMP1IT_Pos)
+#define ANA_REG5_CMP1IT_3 (0x3U << ANA_REG5_CMP1IT_Pos)
+#define ANA_REG5_CMP2IT_0 (0x0U << ANA_REG5_CMP2IT_Pos)
+#define ANA_REG5_CMP2IT_1 (0x1U << ANA_REG5_CMP2IT_Pos)
+#define ANA_REG5_CMP2IT_2 (0x2U << ANA_REG5_CMP2IT_Pos)
+#define ANA_REG5_CMP2IT_3 (0x3U << ANA_REG5_CMP2IT_Pos)
+/************** Bits definition for ANA_CTRL register ******************/
+//Debounce
+#define CMP_DEB_NONE (0x0U)
+#define CMP_DEB_RTCCLK_2 (0x1U)
+#define CMP_DEB_RTCCLK_3 (0x2U)
+#define CMP_DEB_RTCCLK_4 (0x3U)
+#define IS_CMP_DEB(__DEB__) (((__DEB__) == CMP_DEB_NONE) ||\
+ ((__DEB__) == CMP_DEB_RTCCLK_2) ||\
+ ((__DEB__) == CMP_DEB_RTCCLK_3) ||\
+ ((__DEB__) == CMP_DEB_RTCCLK_4))
+
+/***** SourceSelect (CMP_ConfigSignalSource) *****/
+#define CMP_SIGNALSRC_PPIN_TO_VREF 0x00
+#define CMP_SIGNALSRC_PPIN_TO_BGPREF 0x01
+#define CMP_SIGNALSRC_PBAT_TO_VREF 0x80
+#define CMP_SIGNALSRC_PBAT_TO_BGPREF 0x81
+#define CMP_SIGNALSRC_NPIN_TO_VREF 0x10
+#define CMP_SIGNALSRC_NPIN_TO_BGPREF 0x11
+#define CMP_SIGNALSRC_PPIN_TO_NPIN 0x20
+#define CMP_SIGNALSRC_PBAT_TO_NPIN 0xA0
+
+#define IS_CMP_SIGNALSRC(__SIGNALSRC__) (((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_VREF) ||\
+ ((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_BGPREF) ||\
+ ((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_NPIN) ||\
+ ((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_NPIN) ||\
+ ((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_VREF) ||\
+ ((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_BGPREF) ||\
+ ((__SIGNALSRC__) == CMP_SIGNALSRC_NPIN_TO_VREF) ||\
+ ((__SIGNALSRC__) == CMP_SIGNALSRC_NPIN_TO_BGPREF))
+
+/***** BiasSel (CMP_BiasConfig) *****/
+#define CMP_BIAS_20nA (0x0U)
+#define CMP_BIAS_100nA (0x1U)
+#define CMP_BIAS_500nA (0x2U)
+#define IS_CMP_BIAS(__BIAS__) (((__BIAS__) == CMP_BIAS_20nA) ||\
+ ((__BIAS__) == CMP_BIAS_100nA) ||\
+ ((__BIAS__) == CMP_BIAS_500nA))
+
+/***** CheckPeriod (CMP_CheckFrequecnyConfig) *****/
+#define CMP_PERIOD_30US 0
+#define CMP_PERIOD_7_8125MS 1
+#define CMP_PERIOD_125MS 2
+#define CMP_PERIOD_250MS 3
+#define CMP_PERIOD_500MS 4
+#define IS_CMP_CHECKPERIOD(__CHECKPERIOD__) (((__CHECKPERIOD__) == CMP_PERIOD_30US) ||\
+ ((__CHECKPERIOD__) == CMP_PERIOD_7_8125MS)||\
+ ((__CHECKPERIOD__) == CMP_PERIOD_125MS) ||\
+ ((__CHECKPERIOD__) == CMP_PERIOD_250MS) ||\
+ ((__CHECKPERIOD__) == CMP_PERIOD_500MS))
+
+/***** Mode (CMP_ModeConfig) *****/
+#define CMP_MODE_OFF (0x0U)
+#define CMP_MODE_RISING (0x1U)
+#define CMP_MODE_FALLING (0x2U)
+#define CMP_MODE_BOTH (0x3U)
+#define IS_CMP_MODE(__MODE__) (((__MODE__) == CMP_MODE_OFF) ||\
+ ((__MODE__) == CMP_MODE_RISING) ||\
+ ((__MODE__) == CMP_MODE_FALLING) ||\
+ ((__MODE__) == CMP_MODE_BOTH))
+
+//CountSel
+#define CMP_COUNT_NOSUB 0
+#define CMP_COUNT_SUB 1
+#define IS_CMP_COUNT(__COUNT__) (((__COUNT__) == CMP_COUNT_NOSUB) ||\
+ ((__COUNT__) == CMP_COUNT_SUB))
+
+//SubSel
+#define CMP_INTNUM_EVERY 0
+#define CMP_INTNUM_1 1
+#define IS_CMP_INTNUM(__INTNUM__) (((__INTNUM__) == CMP_INTNUM_EVERY) ||\
+ ((__INTNUM__) == CMP_INTNUM_1))
+
+//THRNum
+#define IS_CMP_THRNUM(__THRNUM__) ((__THRNUM__) < 65536UL)
+
+#define CMP_CHKNUM_1 0
+#define CMP_CHKNUM_2 1
+#define CMP_CHKNUM_3 2
+#define CMP_CHKNUM_4 3
+#define CMP_CHKNUM_5 4
+#define CMP_CHKNUM_6 5
+#define CMP_CHKNUM_7 6
+#define CMP_CHKNUM_8 7
+#define CMP_CHKNUM_9 8
+#define CMP_CHKNUM_10 9
+#define CMP_CHKNUM_11 10
+#define CMP_CHKNUM_12 11
+#define CMP_CHKNUM_13 12
+#define CMP_CHKNUM_14 13
+#define CMP_CHKNUM_15 14
+#define CMP_CHKNUM_16 15
+#define IS_CMP_CHKNUM(__CHKNUM__) (__CHKNUM__ < 16)
+
+//DebSel
+//SubSel
+#define CMP_OUTPUT_DEB 0
+#define CMP_OUTPUT_NODEB 1
+#define IS_CMP_OUTPUTDEB(__OUTPUTDEB__) (((__OUTPUTDEB__) == CMP_OUTPUT_DEB) ||\
+ ((__OUTPUTDEB__) == CMP_OUTPUT_NODEB))
+
+/* Exported Functions ------------------------------------------------------- */
+/* CMP Exported Functions Group1:
+ (De)Initialization ------------------------*/
+void CMP_DeInit(uint32_t CMPx);
+void CMP_Init(uint32_t CMPx, CMP_TypeDef *InitStruct);
+void CMP_StructInit(CMP_TypeDef *InitStruct);
+void CMP_CountStructInit(CMP_CountTypeDef *InitStruct);
+void CMP_CountInit(uint32_t CMPx, CMP_CountTypeDef *InitStruct);
+void CMP_INTStructInit(CMP_INTTypeDef *InitStruct);
+void CMP_INTInit(uint32_t CMPx, CMP_INTTypeDef *InitStruct);
+void CMP_OutputStructInit(CMP_OutputTypeDef *InitStruct);
+void CMP_OutputInit(uint32_t CMPx, CMP_OutputTypeDef *InitStruct);
+/* CMP Exported Functions Group2:
+ Interrupt (flag) --------------------------*/
+void CMP_INTConfig(uint32_t CMPx, uint32_t NewState);
+uint8_t CMP_GetINTStatus(uint32_t CMPx);
+void CMP_ClearINTStatus(uint32_t CMPx);
+/* CMP Exported Functions Group3:
+ MISC Configuration ------------------------*/
+void CMP_Cmd(uint32_t CMPx, uint32_t NewState);
+uint32_t CMP_GetCNTValue(uint32_t CMPx);
+void CMP_ClearCNTValue(uint32_t CMPx);
+uint8_t CMP_GetOutputValue(uint32_t CMPx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_CMP_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_crypt.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_crypt.h
new file mode 100644
index 0000000000000000000000000000000000000000..295fe3c2db9fe3aebb9f3cb4b1db4254a2f775b5
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_crypt.h
@@ -0,0 +1,107 @@
+/**
+ ******************************************************************************
+ * @file lib_crypt.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief CRYPT library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_CRYPT_H
+#define __LIB_CRYPT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+/************** Bits definition for CRYPT_CTRL register ******************/
+#define CRYPT_CTRL_MODE_MULTIPLY (0x0U << CRYPT_CTRL_MODE_Pos)
+#define CRYPT_CTRL_MODE_ADD (0x1U << CRYPT_CTRL_MODE_Pos)
+#define CRYPT_CTRL_MODE_SUB (0x2U << CRYPT_CTRL_MODE_Pos)
+#define CRYPT_CTRL_MODE_RSHIFT1 (0x3U << CRYPT_CTRL_MODE_Pos)
+#define CRYPT_CTRL_LENGTH_32 (0x0U << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_64 (0x1U << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_96 (0x2U << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_128 (0x3U << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_160 (0x4U << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_192 (0x5U << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_224 (0x6U << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_256 (0x7U << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_288 (0x8U << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_320 (0x9U << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_352 (0xAU << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_384 (0xBU << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_416 (0xCU << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_448 (0xDU << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_480 (0xEU << CRYPT_CTRL_LENGTH_Pos)
+#define CRYPT_CTRL_LENGTH_512 (0xFU << CRYPT_CTRL_LENGTH_Pos)
+//Length
+#define CRYPT_LENGTH_32 CRYPT_CTRL_LENGTH_32
+#define CRYPT_LENGTH_64 CRYPT_CTRL_LENGTH_64
+#define CRYPT_LENGTH_96 CRYPT_CTRL_LENGTH_96
+#define CRYPT_LENGTH_128 CRYPT_CTRL_LENGTH_128
+#define CRYPT_LENGTH_160 CRYPT_CTRL_LENGTH_160
+#define CRYPT_LENGTH_192 CRYPT_CTRL_LENGTH_192
+#define CRYPT_LENGTH_224 CRYPT_CTRL_LENGTH_224
+#define CRYPT_LENGTH_256 CRYPT_CTRL_LENGTH_256
+#define CRYPT_LENGTH_288 CRYPT_CTRL_LENGTH_288
+#define CRYPT_LENGTH_320 CRYPT_CTRL_LENGTH_320
+#define CRYPT_LENGTH_352 CRYPT_CTRL_LENGTH_352
+#define CRYPT_LENGTH_384 CRYPT_CTRL_LENGTH_384
+#define CRYPT_LENGTH_416 CRYPT_CTRL_LENGTH_416
+#define CRYPT_LENGTH_448 CRYPT_CTRL_LENGTH_448
+#define CRYPT_LENGTH_480 CRYPT_CTRL_LENGTH_480
+#define CRYPT_LENGTH_512 CRYPT_CTRL_LENGTH_512
+//Nostop
+#define CRYPT_STOPCPU (0)
+#define CRYPT_NOSTOPCPU CRYPT_CTRL_NOSTOP
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_CRYPT_ADDR(__ADDR__) (((__ADDR__) & 0x3U) == 0U)
+
+#define IS_CRYPT_LENGTH(__LENGTH__) (((__LENGTH__) == CRYPT_LENGTH_32) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_64) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_32) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_96) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_128) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_160) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_192) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_224) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_256) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_288) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_320) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_352) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_384) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_416) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_448) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_480) ||\
+ ((__LENGTH__) == CRYPT_LENGTH_512))
+
+#define IS_CRYPT_NOSTOP(__NOSTOP__) (((__NOSTOP__) == CRYPT_STOPCPU) || ((__NOSTOP__) == CRYPT_NOSTOPCPU))
+
+/****************************** CRYPT Instances *******************************/
+#define IS_CRYPT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRYPT)
+
+/* Exported Functions ------------------------------------------------------- */
+void CRYPT_AddressAConfig(uint16_t AddrA);
+void CRYPT_AddressBConfig(uint16_t AddrB);
+void CRYPT_AddressOConfig(uint16_t AddrO);
+uint8_t CRYPT_GetCarryBorrowBit(void);
+void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop);
+void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop);
+void CRYPT_StartSub(uint32_t Length, uint32_t Nostop);
+void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop);
+void CRYPT_WaitForLastOperation(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_CRYPT_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_dma.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_dma.h
new file mode 100644
index 0000000000000000000000000000000000000000..02038a2bd17d33fb986382650e40b182a12c8c68
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_dma.h
@@ -0,0 +1,267 @@
+/**
+ ******************************************************************************
+ * @file lib_dma.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief DMA library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_DMA_H
+#define __LIB_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+//Channel
+#define DMA_CHANNEL_0 (0)
+#define DMA_CHANNEL_1 (1)
+#define DMA_CHANNEL_2 (2)
+#define DMA_CHANNEL_3 (3)
+
+typedef struct
+{
+ uint32_t DestAddr; /* destination address */
+ uint32_t SrcAddr; /* source address */
+ uint8_t FrameLen; /* Frame length */
+ uint8_t PackLen; /* Package length */
+ uint32_t ContMode; /* Continuous mode */
+ uint32_t TransMode; /* Transfer mode */
+ uint32_t ReqSrc; /* DMA request source */
+ uint32_t DestAddrMode; /* Destination address mode */
+ uint32_t SrcAddrMode; /* Source address mode */
+ uint32_t TransSize; /* Transfer size mode */
+} DMA_InitType;
+
+/************** Bits definition for DMA_CxCTL register ******************/
+
+
+
+/************** Bits definition for DMA_AESCTL register ******************/
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA)
+
+//ContMode
+#define DMA_CONTMODE_ENABLE DMA_CCTL_CONT
+#define DMA_CONTMODE_DISABLE 0
+#define IS_DMA_CONTMOD(__CONTMOD__) (((__CONTMOD__) == DMA_CONTMODE_ENABLE) ||\
+ ((__CONTMOD__) == DMA_CONTMODE_DISABLE))
+
+//TransMode
+#define DMA_TRANSMODE_SINGLE 0
+#define DMA_TRANSMODE_PACK DMA_CCTL_TMODE
+#define IS_DMA_TRANSMOD(__TRANSMOD__) (((__TRANSMOD__) == DMA_TRANSMODE_SINGLE) ||\
+ ((__TRANSMOD__) == DMA_TRANSMODE_PACK))
+
+//ReqSrc
+#define DMA_REQSRC_SOFT (0x0U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000000 */
+#define DMA_REQSRC_ADC (0x1U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000080 */
+#define DMA_REQSRC_UART0TX (0x2U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000100 */
+#define DMA_REQSRC_UART0RX (0x3U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000180 */
+#define DMA_REQSRC_UART1TX (0x4U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000200 */
+#define DMA_REQSRC_UART1RX (0x5U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000280 */
+#define DMA_REQSRC_UART2TX (0x6U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000300 */
+#define DMA_REQSRC_UART2RX (0x7U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000380 */
+#define DMA_REQSRC_UART3TX (0x8U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000400 */
+#define DMA_REQSRC_UART3RX (0x9U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000480 */
+#define DMA_REQSRC_UART4TX (0xAU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000500 */
+#define DMA_REQSRC_UART4RX (0xBU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000580 */
+#define DMA_REQSRC_UART5TX (0xCU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000600 */
+#define DMA_REQSRC_UART5RX (0xDU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000680 */
+#define DMA_REQSRC_ISO78160TX (0xEU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000700 */
+#define DMA_REQSRC_ISO78160RX (0xFU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000780 */
+#define DMA_REQSRC_ISO78161TX (0x10U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000800 */
+#define DMA_REQSRC_ISO78161RX (0x11U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000880 */
+#define DMA_REQSRC_TIMER0 (0x12U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000900 */
+#define DMA_REQSRC_TIMER1 (0x13U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000980 */
+#define DMA_REQSRC_TIMER2 (0x14U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000A00 */
+#define DMA_REQSRC_TIMER3 (0x15U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000A80 */
+#define DMA_REQSRC_SPI1TX (0x16U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000B00 */
+#define DMA_REQSRC_SPI1RX (0x17U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000B80 */
+#define DMA_REQSRC_U32K0 (0x18U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000C00 */
+#define DMA_REQSRC_U32K1 (0x19U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000C80 */
+#define DMA_REQSRC_CMP1 (0x1AU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000D00 */
+#define DMA_REQSRC_CMP2 (0x1BU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000D80 */
+#define DMA_REQSRC_SPI3TX (0x1CU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000E00 */
+#define DMA_REQSRC_SPI3RX (0x1DU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000E80 */
+#define DMA_REQSRC_SPI2TX (0x1EU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000F00 */
+#define DMA_REQSRC_SPI2RX (0x1FU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000F80 */
+
+#define IS_DMA_REQSRC(__REQSRC__) (((__REQSRC__) == DMA_REQSRC_SOFT) ||\
+ ((__REQSRC__) == DMA_REQSRC_ADC) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART0TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART0RX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART1TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART1RX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART2TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART2RX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART3TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART3RX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART4TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART4RX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART5TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_UART5RX) ||\
+ ((__REQSRC__) == DMA_REQSRC_ISO78160TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_ISO78160RX) ||\
+ ((__REQSRC__) == DMA_REQSRC_ISO78161TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_ISO78161RX) ||\
+ ((__REQSRC__) == DMA_REQSRC_TIMER0) ||\
+ ((__REQSRC__) == DMA_REQSRC_TIMER1) ||\
+ ((__REQSRC__) == DMA_REQSRC_TIMER2) ||\
+ ((__REQSRC__) == DMA_REQSRC_TIMER3) ||\
+ ((__REQSRC__) == DMA_REQSRC_SPI1TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_SPI1RX) ||\
+ ((__REQSRC__) == DMA_REQSRC_U32K0) ||\
+ ((__REQSRC__) == DMA_REQSRC_U32K1) ||\
+ ((__REQSRC__) == DMA_REQSRC_CMP1) ||\
+ ((__REQSRC__) == DMA_REQSRC_CMP2) ||\
+ ((__REQSRC__) == DMA_REQSRC_SPI3TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_SPI3RX) ||\
+ ((__REQSRC__) == DMA_REQSRC_SPI2TX) ||\
+ ((__REQSRC__) == DMA_REQSRC_SPI2RX))
+
+
+//DestAddrMode
+#define DMA_DESTADDRMODE_FIX (0x0U << DMA_CCTL_DMODE_Pos) /*!< 0x00000000 */
+#define DMA_DESTADDRMODE_PEND (0x1U << DMA_CCTL_DMODE_Pos) /*!< 0x00000020 */
+#define DMA_DESTADDRMODE_FEND (0x2U << DMA_CCTL_DMODE_Pos) /*!< 0x00000040 */
+#define IS_DMA_DESTADDRMOD(__DAM__) (((__DAM__) == DMA_DESTADDRMODE_FIX) ||\
+ ((__DAM__) == DMA_DESTADDRMODE_PEND) ||\
+ ((__DAM__) == DMA_DESTADDRMODE_FEND))
+
+//SrcAddrMode
+#define DMA_SRCADDRMODE_FIX (0x0U << DMA_CCTL_SMODE_Pos) /*!< 0x00000000 */
+#define DMA_SRCADDRMODE_PEND (0x1U << DMA_CCTL_SMODE_Pos) /*!< 0x00000008 */
+#define DMA_SRCADDRMODE_FEND (0x2U << DMA_CCTL_SMODE_Pos) /*!< 0x00000010 */
+#define IS_DMA_SRCADDRMOD(__SAM__) (((__SAM__) == DMA_SRCADDRMODE_FIX) ||\
+ ((__SAM__) == DMA_SRCADDRMODE_PEND) ||\
+ ((__SAM__) == DMA_SRCADDRMODE_FEND))
+
+//TransSize
+#define DMA_TRANSSIZE_BYTE (0x0U << DMA_CCTL_SIZE_Pos)
+#define DMA_TRANSSIZE_HWORD (0x1U << DMA_CCTL_SIZE_Pos)
+#define DMA_TRANSSIZE_WORD (0x2U << DMA_CCTL_SIZE_Pos)
+#define IS_DMA_TRANSSIZE(__TSIZE__) (((__TSIZE__) == DMA_TRANSSIZE_BYTE) ||\
+ ((__TSIZE__) == DMA_TRANSSIZE_HWORD) ||\
+ ((__TSIZE__) == DMA_TRANSSIZE_WORD))
+
+#define IS_DMA_ALIGNEDADDR_WORD(__ADDRW__) (((__ADDRW__) & 0x3U) == 0U)
+#define IS_DMA_ALIGNEDADDR_HWORD(__ADDRHW__) (((__ADDRHW__) & 0x1U) == 0U)
+
+typedef struct
+{
+ uint32_t Mode; /* AES mode */
+ uint32_t Direction; /* Direction */
+ uint32_t *KeyStr; /* AES key */
+} DMA_AESInitType;
+
+//AES MODE
+#define DMA_AESMODE_128 (0x0U << DMA_AESCTL_MODE_Pos) /*!< 0x00000000 */
+#define DMA_AESMODE_192 (0x1U << DMA_AESCTL_MODE_Pos) /*!< 0x00000004 */
+#define DMA_AESMODE_256 (0x2U << DMA_AESCTL_MODE_Pos) /*!< 0x00000008 */
+#define IS_DMA_AESMOD(__AESMOD__) (((__AESMOD__) == DMA_AESMODE_128) ||\
+ ((__AESMOD__) == DMA_AESMODE_192) ||\
+ ((__AESMOD__) == DMA_AESMODE_256))
+
+//AES Direction
+#define DMA_AESDIRECTION_ENCODE DMA_AESCTL_ENC
+#define DMA_AESDIRECTION_DECODE 0
+#define IS_DMA_AESDIR(__AESDIR__) (((__AESDIR__) == DMA_AESDIRECTION_ENCODE) ||\
+ ((__AESDIR__) == DMA_AESDIRECTION_DECODE))
+
+//INT
+#define DMA_INT_C3DA DMA_IE_C3DAIE
+#define DMA_INT_C2DA DMA_IE_C2DAIE
+#define DMA_INT_C1DA DMA_IE_C1DAIE
+#define DMA_INT_C0DA DMA_IE_C0DAIE
+#define DMA_INT_C3FE DMA_IE_C3FEIE
+#define DMA_INT_C2FE DMA_IE_C2FEIE
+#define DMA_INT_C1FE DMA_IE_C1FEIE
+#define DMA_INT_C0FE DMA_IE_C0FEIE
+#define DMA_INT_C3PE DMA_IE_C3PEIE
+#define DMA_INT_C2PE DMA_IE_C2PEIE
+#define DMA_INT_C1PE DMA_IE_C1PEIE
+#define DMA_INT_C0PE DMA_IE_C0PEIE
+#define DMA_INT_Msk (0xFFFUL)
+#define IS_DMA_INT(__INT__) ((((__INT__) & DMA_INT_Msk) != 0U) &&\
+ (((__INT__) & ~DMA_INT_Msk) == 0U))
+
+//INTSTS
+#define DMA_INTSTS_C3DA DMA_STS_C3DA
+#define DMA_INTSTS_C2DA DMA_STS_C2DA
+#define DMA_INTSTS_C1DA DMA_STS_C1DA
+#define DMA_INTSTS_C0DA DMA_STS_C0DA
+#define DMA_INTSTS_C3FE DMA_STS_C3FE
+#define DMA_INTSTS_C2FE DMA_STS_C2FE
+#define DMA_INTSTS_C1FE DMA_STS_C1FE
+#define DMA_INTSTS_C0FE DMA_STS_C0FE
+#define DMA_INTSTS_C3PE DMA_STS_C3PE
+#define DMA_INTSTS_C2PE DMA_STS_C2PE
+#define DMA_INTSTS_C1PE DMA_STS_C1PE
+#define DMA_INTSTS_C0PE DMA_STS_C0PE
+#define DMA_INTSTS_C3BUSY DMA_STS_C3BUSY
+#define DMA_INTSTS_C2BUSY DMA_STS_C2BUSY
+#define DMA_INTSTS_C1BUSY DMA_STS_C1BUSY
+#define DMA_INTSTS_C0BUSY DMA_STS_C0BUSY
+#define DMA_INTSTS_Msk (0xFFF0UL)
+
+#define IS_DMA_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == DMA_INTSTS_C3DA) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C2DA) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C1DA) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C0DA) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C3FE) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C2FE) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C1FE) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C0FE) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C3PE) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C2PE) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C1PE) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C0PE) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C3BUSY) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C2BUSY) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C1BUSY) ||\
+ ((__INTFLAGR__) == DMA_INTSTS_C0BUSY))
+
+#define IS_DMA_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & DMA_INTSTS_Msk) != 0U) &&\
+ (((__INTFLAGC__) & ~DMA_INTSTS_Msk) == 0U))
+
+#define IS_DMA_CHANNEL(__CH__) (((__CH__) == DMA_CHANNEL_0) ||\
+ ((__CH__) == DMA_CHANNEL_1) ||\
+ ((__CH__) == DMA_CHANNEL_2) ||\
+ ((__CH__) == DMA_CHANNEL_3))
+
+/* Exported Functions ------------------------------------------------------- */
+/* DMA Exported Functions Group1:
+ (De)Initialization ------------------------*/
+void DMA_DeInit(uint32_t Channel);
+void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel);
+void DMA_StructInit(DMA_InitType *InitStruct);
+void DMA_ASEDeInit(void);
+void DMA_AESInit(DMA_AESInitType *InitStruct);
+/* DMA Exported Functions Group2:
+ Interrupt (flag) --------------------------*/
+void DMA_INTConfig(uint32_t INTMask, uint32_t NewState);
+uint8_t DMA_GetINTStatus(uint32_t INTMask);
+void DMA_ClearINTStatus(uint32_t INTMask);
+/* DMA Exported Functions Group3:
+ MISC Configuration ------------------------*/
+void DMA_Cmd(uint32_t Channel, uint32_t NewState);
+void DMA_AESCmd(uint32_t NewState);
+void DMA_StopTransmit(uint32_t Channel, uint32_t NewState);
+uint8_t DMA_GetFrameLenTransferred(uint32_t Channel);
+uint8_t DMA_GetPackLenTransferred(uint32_t Channel);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_DMA_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_flash.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_flash.h
new file mode 100644
index 0000000000000000000000000000000000000000..c22a1f9c54185e2c426d55bed4055b243db70c41
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_flash.h
@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file lib_flash.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief FLASH library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_FLASH_H
+#define __LIB_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+#define FLASH_BLOCK_0 (0x00000001UL)
+#define FLASH_BLOCK_1 (0x00000002UL)
+#define FLASH_BLOCK_2 (0x00000004UL)
+#define FLASH_BLOCK_3 (0x00000008UL)
+#define FLASH_BLOCK_4 (0x00000010UL)
+#define FLASH_BLOCK_5 (0x00000020UL)
+#define FLASH_BLOCK_6 (0x00000040UL)
+#define FLASH_BLOCK_7 (0x00000080UL)
+#define FLASH_BLOCK_8 (0x00000100UL)
+#define FLASH_BLOCK_9 (0x00000200UL)
+#define FLASH_BLOCK_10 (0x00000400UL)
+#define FLASH_BLOCK_11 (0x00000800UL)
+#define FLASH_BLOCK_12 (0x00001000UL)
+#define FLASH_BLOCK_13 (0x00002000UL)
+#define FLASH_BLOCK_14 (0x00004000UL)
+#define FLASH_BLOCK_15 (0x00008000UL)
+#define FLASH_BLOCK_16 (0x00010000UL)
+#define FLASH_BLOCK_17 (0x00020000UL)
+#define FLASH_BLOCK_18 (0x00040000UL)
+#define FLASH_BLOCK_19 (0x00080000UL)
+#define FLASH_BLOCK_20 (0x00100000UL)
+#define FLASH_BLOCK_21 (0x00200000UL)
+#define FLASH_BLOCK_22 (0x00400000UL)
+#define FLASH_BLOCK_23 (0x00800000UL)
+#define FLASH_BLOCK_24 (0x01000000UL)
+#define FLASH_BLOCK_25 (0x02000000UL)
+#define FLASH_BLOCK_26 (0x04000000UL)
+#define FLASH_BLOCK_27 (0x08000000UL)
+#define FLASH_BLOCK_28 (0x10000000UL)
+#define FLASH_BLOCK_29 (0x20000000UL)
+#define FLASH_BLOCK_30 (0x40000000UL)
+#define FLASH_BLOCK_31 (0x80000000UL)
+#define FLASH_BLOCK_Msk (0xFFFFFFFFUL)
+#define FLASH_BLOCK_ALL FLASH_BLOCK_Msk
+#define IS_FLASH_RWBLOCK(__BLOCK__) ((((__BLOCK__) & FLASH_BLOCK_Msk) != 0UL) &&\
+ (((__BLOCK__) & ~FLASH_BLOCK_Msk) == 0UL))
+
+#define IS_FLASH_BLOCK(__BLOCK__) (((__BLOCK__) == FLASH_BLOCK_0) ||\
+ ((__BLOCK__) == FLASH_BLOCK_1) ||\
+ ((__BLOCK__) == FLASH_BLOCK_2) ||\
+ ((__BLOCK__) == FLASH_BLOCK_3) ||\
+ ((__BLOCK__) == FLASH_BLOCK_4) ||\
+ ((__BLOCK__) == FLASH_BLOCK_5) ||\
+ ((__BLOCK__) == FLASH_BLOCK_6) ||\
+ ((__BLOCK__) == FLASH_BLOCK_7) ||\
+ ((__BLOCK__) == FLASH_BLOCK_8) ||\
+ ((__BLOCK__) == FLASH_BLOCK_9) ||\
+ ((__BLOCK__) == FLASH_BLOCK_10) ||\
+ ((__BLOCK__) == FLASH_BLOCK_11) ||\
+ ((__BLOCK__) == FLASH_BLOCK_12) ||\
+ ((__BLOCK__) == FLASH_BLOCK_13) ||\
+ ((__BLOCK__) == FLASH_BLOCK_14) ||\
+ ((__BLOCK__) == FLASH_BLOCK_15) ||\
+ ((__BLOCK__) == FLASH_BLOCK_16) ||\
+ ((__BLOCK__) == FLASH_BLOCK_17) ||\
+ ((__BLOCK__) == FLASH_BLOCK_18) ||\
+ ((__BLOCK__) == FLASH_BLOCK_19) ||\
+ ((__BLOCK__) == FLASH_BLOCK_20) ||\
+ ((__BLOCK__) == FLASH_BLOCK_21) ||\
+ ((__BLOCK__) == FLASH_BLOCK_22) ||\
+ ((__BLOCK__) == FLASH_BLOCK_23) ||\
+ ((__BLOCK__) == FLASH_BLOCK_24) ||\
+ ((__BLOCK__) == FLASH_BLOCK_25) ||\
+ ((__BLOCK__) == FLASH_BLOCK_26) ||\
+ ((__BLOCK__) == FLASH_BLOCK_27) ||\
+ ((__BLOCK__) == FLASH_BLOCK_28) ||\
+ ((__BLOCK__) == FLASH_BLOCK_29) ||\
+ ((__BLOCK__) == FLASH_BLOCK_30) ||\
+ ((__BLOCK__) == FLASH_BLOCK_31))
+
+#define FLASH_READ (0)
+#define FLASH_WRITE (1)
+#define IS_FLASH_OPERATION(__OPERATION__) (((__OPERATION__) == FLASH_READ) ||\
+ ((__OPERATION__) == FLASH_WRITE))
+
+/************** Bits definition for FLASH_CTRL register ******************/
+#define FLASH_CTRL_CSMODE_DISABLE (0x0U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000000 */
+#define FLASH_CTRL_CSMODE_ALWAYSON (0x1U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000001 */
+#define FLASH_CTRL_CSMODE_TIM2OV (0x2U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000002 */
+#define FLASH_CTRL_CSMODE_RTC (0x3U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000003 */
+
+//CSMode
+#define FLASH_CSMODE_DISABLE FLASH_CTRL_CSMODE_DISABLE
+#define FLASH_CSMODE_ALWAYSON FLASH_CTRL_CSMODE_ALWAYSON
+#define FLASH_CSMODE_TMR2OF FLASH_CTRL_CSMODE_TIM2OV
+#define FLASH_CSMODE_RTC FLASH_CTRL_CSMODE_RTC
+#define IS_FLASH_CSMODE(__CSMODE__) (((__CSMODE__) == FLASH_CSMODE_DISABLE) ||\
+ ((__CSMODE__) == FLASH_CSMODE_ALWAYSON) ||\
+ ((__CSMODE__) == FLASH_CSMODE_TMR2OF) ||\
+ ((__CSMODE__) == FLASH_CSMODE_RTC))
+
+//INT
+#define FLASH_INT_CS FLASH_CTRL_CSINTEN
+#define IS_FLASH_INT(__INT__) ((__INT__) == FLASH_INT_CS)
+
+//WriteStatus
+#define FLASH_WSTA_BUSY 0
+#define FLASH_WRITE_FINISH 1
+#define FLASH_WSTA_FINISH FLASH_WRITE_FINISH
+
+#define IS_FLASH_ADDRESS(__ADDRESS__) ((__ADDRESS__) < 0x80000UL)
+
+#define IS_FLASH_ADRRW(__ADDRW__) (((__ADDRW__) < 0x80000UL) &&\
+ (((__ADDRW__) & 0x3U) == 0U))
+
+#define IS_FLASH_ADRRHW(__ADDRHW__) (((__ADDRHW__) < 0x80000UL) &&\
+ (((__ADDRHW__) & 0x1U) == 0U))
+
+#define IS_FLASH_CHECKSUMADDR(__ADDRESS1__,__ADDRESS2__) (((__ADDRESS1__) < 0x80000) && ((__ADDRESS2__) < 0x80000) && ((__ADDRESS1__) < (__ADDRESS2__)))
+
+/* Exported Functions ------------------------------------------------------- */
+
+void FLASH_Init(uint32_t CSMode);
+void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState);
+void FLASH_CycleInit(void);
+void FLASH_SectorErase(uint32_t SectorAddr);
+void FLASH_ChipErase(void);
+void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length);
+void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length);
+void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length);
+void FLASH_SetReadProtection(uint32_t Block);
+void FLASH_WriteProtection(uint32_t Block, uint32_t NewState);
+void FLASH_ICEProtection(uint32_t NewState);
+uint8_t FLASH_GetProtectionStatus(uint32_t Block, uint32_t Operation);
+uint32_t FLASH_GetAllProtectionStatus(uint32_t Operation);
+void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd);
+void FLASH_SetCheckSumCompValue(uint32_t Checksum);
+uint32_t FLASH_GetCheckSum(void);
+uint8_t FLASH_GetINTStatus(uint32_t IntMask);
+void FLASH_ClearINTStatus(uint32_t IntMask);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_FLASH_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_gpio.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_gpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..53c9a40037d2fe20135d71483c2db108153e11b0
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_gpio.h
@@ -0,0 +1,225 @@
+/**
+ ******************************************************************************
+ * @file lib_gpio.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief GPIO library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_GPIO_H
+#define __LIB_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+#define GET_BITBAND_ADDR(addr, bitnum) ((((uint32_t)addr) & 0xF0000000) + \
+ 0x2000000 + ((((uint32_t)addr) & 0xFFFFF) << 5) + (bitnum << 2))
+
+typedef struct
+{
+ uint32_t GPIO_Pin;
+ uint32_t GPIO_Mode;
+} GPIO_InitType;
+
+typedef struct
+{
+ __IO uint32_t DATBitBand[16];
+} GPIO_DATInitType;
+
+/**
+ * @brief Bit_State_enumeration
+ */
+typedef enum {
+ Bit_RESET = 0,
+ Bit_SET
+} BitState;
+
+#define GPIO_A ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40014018,0)))
+#define GPIO_B ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000028,0)))
+#define GPIO_C ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000048,0)))
+#define GPIO_D ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000068,0)))
+#define GPIO_E ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000088,0)))
+#define GPIO_F ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x400000A8,0)))
+#define IS_GPIO_DAT(__GPIODAT__) (((__GPIODAT__) == GPIO_A) ||\
+ ((__GPIODAT__) == GPIO_B) ||\
+ ((__GPIODAT__) == GPIO_C) ||\
+ ((__GPIODAT__) == GPIO_D) ||\
+ ((__GPIODAT__) == GPIO_E) ||\
+ ((__GPIODAT__) == GPIO_F))
+
+#define IS_GPIO_PINNUM(__PINNUM__) ((__PINNUM__) < 16U)
+
+#define IS_GPIO_BITVAL(__BITVAL__) (((__BITVAL__) == 1U) || ((__BITVAL__) == 0U))
+
+//GPIO_Pin
+#define GPIO_Pin_0 ((uint16_t)0x0001)
+#define GPIO_Pin_1 ((uint16_t)0x0002)
+#define GPIO_Pin_2 ((uint16_t)0x0004)
+#define GPIO_Pin_3 ((uint16_t)0x0008)
+#define GPIO_Pin_4 ((uint16_t)0x0010)
+#define GPIO_Pin_5 ((uint16_t)0x0020)
+#define GPIO_Pin_6 ((uint16_t)0x0040)
+#define GPIO_Pin_7 ((uint16_t)0x0080)
+#define GPIO_Pin_8 ((uint16_t)0x0100)
+#define GPIO_Pin_9 ((uint16_t)0x0200)
+#define GPIO_Pin_10 ((uint16_t)0x0400)
+#define GPIO_Pin_11 ((uint16_t)0x0800)
+#define GPIO_Pin_12 ((uint16_t)0x1000)
+#define GPIO_Pin_13 ((uint16_t)0x2000)
+#define GPIO_Pin_14 ((uint16_t)0x4000)
+#define GPIO_Pin_15 ((uint16_t)0x8000)
+#define GPIO_Pin_All ((uint16_t)0xFFFF)
+#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_Pin_All) != 0UL) &&\
+ (((__PIN__) & ~GPIO_Pin_All) == 0UL))
+#define IS_GPIO_PINR(__PINR__) (((__PINR__) == GPIO_Pin_0) ||\
+ ((__PINR__) == GPIO_Pin_1) ||\
+ ((__PINR__) == GPIO_Pin_2) ||\
+ ((__PINR__) == GPIO_Pin_3) ||\
+ ((__PINR__) == GPIO_Pin_4) ||\
+ ((__PINR__) == GPIO_Pin_5) ||\
+ ((__PINR__) == GPIO_Pin_6) ||\
+ ((__PINR__) == GPIO_Pin_7) ||\
+ ((__PINR__) == GPIO_Pin_8) ||\
+ ((__PINR__) == GPIO_Pin_9) ||\
+ ((__PINR__) == GPIO_Pin_10) ||\
+ ((__PINR__) == GPIO_Pin_11) ||\
+ ((__PINR__) == GPIO_Pin_12) ||\
+ ((__PINR__) == GPIO_Pin_13) ||\
+ ((__PINR__) == GPIO_Pin_14) ||\
+ ((__PINR__) == GPIO_Pin_15))
+
+//GPIO_Mode
+#define GPIO_MODE_INPUT (0xCU)
+#define GPIO_MODE_OUTPUT_CMOS (0x2U)
+#define GPIO_MODE_OUTPUT_OD (0x3U)
+#define GPIO_MODE_INOUT_OD (0xBU)
+#define GPIO_MODE_INOUT_CMOS (0xAU)
+#define GPIO_MODE_FORBIDDEN (0x4U)
+#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
+ ((__MODE__) == GPIO_MODE_OUTPUT_CMOS) ||\
+ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
+ ((__MODE__) == GPIO_MODE_INOUT_OD) ||\
+ ((__MODE__) == GPIO_MODE_INOUT_CMOS) ||\
+ ((__MODE__) == GPIO_MODE_FORBIDDEN))
+
+/************** Bits definition for IO_MISC register ******************/
+#define IO_MISC_PLLHDIV_1 (0x0U << GPIOAF_IO_MISC_PLLHDIV_Pos)
+#define IO_MISC_PLLHDIV_2 (0x1U << GPIOAF_IO_MISC_PLLHDIV_Pos)
+#define IO_MISC_PLLHDIV_4 (0x2U << GPIOAF_IO_MISC_PLLHDIV_Pos)
+#define IO_MISC_PLLHDIV_8 (0x3U << GPIOAF_IO_MISC_PLLHDIV_Pos)
+#define IO_MISC_PLLHDIV_16 (0x4U << GPIOAF_IO_MISC_PLLHDIV_Pos)
+
+//GPIO AF
+#define GPIOB_AF_PLLHDIV GPIOAF_IOB_SEL_SEL1
+#define GPIOB_AF_PLLLOUT GPIOAF_IOB_SEL_SEL2
+#define GPIOB_AF_OSC GPIOAF_IOB_SEL_SEL6
+#define GPIOE_AF_CMP1O GPIOAF_IOE_SEL_SEL7
+#define IS_GPIO_GPIOAF(__GPIOAF__) (((__GPIOAF__) == GPIOB_AF_PLLHDIV) ||\
+ ((__GPIOAF__) == GPIOB_AF_PLLLOUT) ||\
+ ((__GPIOAF__) == GPIOB_AF_OSC) ||\
+ ((__GPIOAF__) == GPIOE_AF_CMP1O))
+
+#define IS_GPIOB_GPIOAF(__GPIOAF__) (((__GPIOAF__) == GPIOB_AF_PLLHDIV) ||\
+ ((__GPIOAF__) == GPIOB_AF_PLLLOUT) ||\
+ ((__GPIOAF__) == GPIOB_AF_OSC))
+
+#define IS_GPIOE_GPIOAF(__GPIOAF__) ((__GPIOAF__) == GPIOE_AF_CMP1O)
+
+
+//PMUIO AF
+#define PMUIO7_AF_PLLDIV GPIOA_SEL_SEL7
+#define PMUIO6_AF_CMP2O GPIOA_SEL_SEL6
+#define PMUIO3_AF_PLLDIV GPIOA_SEL_SEL3
+#define PMUIO_AF_Msk (PMUIO7_AF_PLLDIV | PMUIO6_AF_CMP2O | PMUIO3_AF_PLLDIV)
+
+//GPIO pin remap
+#define GPIO_REMAP_I2C GPIOAF_IO_MISC_I2CIOC
+#define IS_GPIO_REMAP(__REMAP__) ((__REMAP__) == GPIO_REMAP_I2C)
+
+//PLLDIV
+#define GPIO_PLLDIV_1 IO_MISC_PLLHDIV_1
+#define GPIO_PLLDIV_2 IO_MISC_PLLHDIV_2
+#define GPIO_PLLDIV_4 IO_MISC_PLLHDIV_4
+#define GPIO_PLLDIV_8 IO_MISC_PLLHDIV_8
+#define GPIO_PLLDIV_16 IO_MISC_PLLHDIV_16
+#define IS_GPIO_PLLDIV(__PLLDIV__) (((__PLLDIV__) == GPIO_PLLDIV_1) ||\
+ ((__PLLDIV__) == GPIO_PLLDIV_2) ||\
+ ((__PLLDIV__) == GPIO_PLLDIV_4) ||\
+ ((__PLLDIV__) == GPIO_PLLDIV_8) ||\
+ ((__PLLDIV__) == GPIO_PLLDIV_16))
+
+
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_PMUIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPIOA)
+
+#define IS_GPIOAF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOE))
+
+#define IS_GPIOE_GPIOAF(__GPIOAF__) ((__GPIOAF__) == GPIOE_AF_CMP1O)
+
+#define IS_GPIO_PMUIOAF(__PMUIOAF__) ((((__PMUIOAF__) & PMUIO_AF_Msk) != 0U) &&\
+ (((__PMUIOAF__) & ~PMUIO_AF_Msk) == 0U))
+
+#define IS_GPIO_REMAP(__REMAP__) ((__REMAP__) == GPIO_REMAP_I2C)
+
+#define IS_GPIO_PLLDIV(__PLLDIV__) (((__PLLDIV__) == GPIO_PLLDIV_1) ||\
+ ((__PLLDIV__) == GPIO_PLLDIV_2) ||\
+ ((__PLLDIV__) == GPIO_PLLDIV_4) ||\
+ ((__PLLDIV__) == GPIO_PLLDIV_8) ||\
+ ((__PLLDIV__) == GPIO_PLLDIV_16))
+
+/* Exported Functions ------------------------------------------------------- */
+/* GPIO Exported Functions Group1:
+ Initialization and functions --------------*/
+void GPIOBToF_Init(GPIO_Type *GPIOx, GPIO_InitType *InitStruct);
+void GPIOA_Init(GPIOA_Type *GPIOx, GPIO_InitType *InitStruct);
+/* GPIO Exported Functions Group2:
+ Read input data ---------------------------*/
+uint8_t GPIOBToF_ReadInputDataBit(GPIO_Type *GPIOx, uint16_t GPIO_Pin);
+uint8_t GPIOA_ReadInputDataBit(GPIOA_Type *GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIOBToF_ReadInputData(GPIO_Type* GPIOx);
+uint16_t GPIOA_ReadInputData(GPIOA_Type* GPIOx);
+/* GPIO Exported Functions Group3:
+ Read output data --------------------------*/
+uint8_t GPIOBToF_ReadOutputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+uint8_t GPIOA_ReadOutputDataBit(GPIOA_Type* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIOBToF_ReadOutputData(GPIO_Type* GPIOx);
+uint16_t GPIOA_ReadOutputData(GPIOA_Type* GPIOx);
+/* GPIO Exported Functions Group4:
+ Write output data -------------------------*/
+void GPIO_WriteBit(GPIO_DATInitType* DATx, uint8_t PinNum, uint8_t val);
+void GPIOBToF_WriteBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin, uint8_t val);
+void GPIOA_WriteBit(GPIOA_Type* GPIOx, uint16_t GPIO_Pin, uint8_t val);
+void GPIOBToF_Write(GPIO_Type* GPIOx, uint16_t val);
+void GPIOA_Write(GPIOA_Type* GPIOx, uint16_t val);
+/* GPIO Exported Functions Group5:
+ IO AF configure ---------------------------*/
+void GPIOBToF_AFConfig(GPIO_Type* GPIOx, uint32_t GPIO_AFx, uint8_t NewState);
+void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState);
+/* GPIO Exported Functions Group6:
+ IO Remap configure ------------------------*/
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState);
+/* GPIO Exported Functions Group7:
+ Others ------------------------------------*/
+void GPIO_PLLDIVConfig(uint32_t Divider);
+void GPIOA_DeGlitchCmd( uint16_t GPIO_Pin, uint8_t NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_GPIO_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_i2c.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_i2c.h
new file mode 100644
index 0000000000000000000000000000000000000000..280e36ba963856cde6a3a2758008fc80073fcc38
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_i2c.h
@@ -0,0 +1,164 @@
+/**
+ ******************************************************************************
+ * @file lib_i2c.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief IIC library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_I2C_H
+#define __LIB_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+ uint32_t SlaveAddr;
+ uint32_t GeneralCallAck;
+ uint32_t AssertAcknowledge;
+ uint32_t ClockSource;
+} I2C_InitType;
+
+/************** Bits definition for I2C_CTRL register ******************/
+#define I2C_CTRL_CR_0 (0x0U << I2C_CTRL_CR0_Pos) /*!< 0x0000000 */
+#define I2C_CTRL_CR_1 (0x1U << I2C_CTRL_CR0_Pos) /*!< 0x0000001 */
+#define I2C_CTRL_CR_2 (0x2U << I2C_CTRL_CR0_Pos) /*!< 0x0000002 */
+#define I2C_CTRL_CR_3 (0x3U << I2C_CTRL_CR0_Pos) /*!< 0x0000003 */
+#define I2C_CTRL_CR_4 (0x80U << I2C_CTRL_CR0_Pos) /*!< 0x0000080 */
+#define I2C_CTRL_CR_5 (0x81U << I2C_CTRL_CR0_Pos) /*!< 0x0000081 */
+#define I2C_CTRL_CR_6 (0x82U << I2C_CTRL_CR0_Pos) /*!< 0x0000082 */
+#define I2C_CTRL_CR_7 (0x83U << I2C_CTRL_CR0_Pos) /*!< 0x0000083 */
+
+/************** Bits definition for I2C_STS register ******************/
+#define I2C_STS_STS_0x00 (0x0U << I2C_STS_STS_Pos) /*!< 0x0000000 */
+#define I2C_STS_STS_0x08 (0x1U << I2C_STS_STS_Pos) /*!< 0x0000008 */
+#define I2C_STS_STS_0x10 (0x2U << I2C_STS_STS_Pos) /*!< 0x0000010 */
+#define I2C_STS_STS_0x18 (0x3U << I2C_STS_STS_Pos) /*!< 0x0000018 */
+#define I2C_STS_STS_0x20 (0x4U << I2C_STS_STS_Pos) /*!< 0x0000020 */
+#define I2C_STS_STS_0x28 (0x5U << I2C_STS_STS_Pos) /*!< 0x0000028 */
+#define I2C_STS_STS_0x30 (0x6U << I2C_STS_STS_Pos) /*!< 0x0000030 */
+#define I2C_STS_STS_0x38 (0x7U << I2C_STS_STS_Pos) /*!< 0x0000038 */
+#define I2C_STS_STS_0x40 (0x8U << I2C_STS_STS_Pos) /*!< 0x0000040 */
+#define I2C_STS_STS_0x48 (0x9U << I2C_STS_STS_Pos) /*!< 0x0000048 */
+#define I2C_STS_STS_0x50 (0xAU << I2C_STS_STS_Pos) /*!< 0x0000050 */
+#define I2C_STS_STS_0x58 (0xBU << I2C_STS_STS_Pos) /*!< 0x0000058 */
+#define I2C_STS_STS_0x60 (0xCU << I2C_STS_STS_Pos) /*!< 0x0000060 */
+#define I2C_STS_STS_0x68 (0xDU << I2C_STS_STS_Pos) /*!< 0x0000068 */
+#define I2C_STS_STS_0x70 (0xEU << I2C_STS_STS_Pos) /*!< 0x0000070 */
+#define I2C_STS_STS_0x78 (0xFU << I2C_STS_STS_Pos) /*!< 0x0000078 */
+#define I2C_STS_STS_0x80 (0x10U << I2C_STS_STS_Pos) /*!< 0x0000080 */
+#define I2C_STS_STS_0x88 (0x11U << I2C_STS_STS_Pos) /*!< 0x0000088 */
+#define I2C_STS_STS_0x90 (0x12U << I2C_STS_STS_Pos) /*!< 0x0000090 */
+#define I2C_STS_STS_0x98 (0x13U << I2C_STS_STS_Pos) /*!< 0x0000098 */
+#define I2C_STS_STS_0xA0 (0x14U << I2C_STS_STS_Pos) /*!< 0x00000A0 */
+#define I2C_STS_STS_0xA8 (0x15U << I2C_STS_STS_Pos) /*!< 0x00000A8 */
+#define I2C_STS_STS_0xB0 (0x16U << I2C_STS_STS_Pos) /*!< 0x00000B0 */
+#define I2C_STS_STS_0xB8 (0x17U << I2C_STS_STS_Pos) /*!< 0x00000B8 */
+#define I2C_STS_STS_0xC0 (0x18U << I2C_STS_STS_Pos) /*!< 0x00000C0 */
+#define I2C_STS_STS_0xC8 (0x19U << I2C_STS_STS_Pos) /*!< 0x00000C8 */
+#define I2C_STS_STS_0xF8 (0x1FU << I2C_STS_STS_Pos) /*!< 0x00000F8 */
+
+//GeneralCallAck
+#define I2C_GENERALCALLACK_ENABLE I2C_ADDR_GC
+#define I2C_GENERALCALLACK_DISABLE 0
+//AssertAcknowledge
+#define I2C_ASSERTACKNOWLEDGE_ENABLE I2C_CTRL_AA
+#define I2C_ASSERTACKNOWLEDGE_DISABLE 0
+//ClockSource
+#define I2C_CLOCKSOURCE_APBD256 I2C_CTRL_CR_0
+#define I2C_CLOCKSOURCE_APBD224 I2C_CTRL_CR_1
+#define I2C_CLOCKSOURCE_APBD192 I2C_CTRL_CR_2
+#define I2C_CLOCKSOURCE_APBD160 I2C_CTRL_CR_3
+#define I2C_CLOCKSOURCE_APBD960 I2C_CTRL_CR_4
+#define I2C_CLOCKSOURCE_APBD120 I2C_CTRL_CR_5
+#define I2C_CLOCKSOURCE_APBD60 I2C_CTRL_CR_6
+#define I2C_CLOCKSOURCE_TIM3OFD8 I2C_CTRL_CR_7
+
+#define I2C_CTRL_CR (0x83)
+typedef struct
+{
+ uint16_t SlaveAddr;
+ uint8_t SubAddrType;
+ uint32_t PageRange;
+ uint32_t SubAddress;
+ uint8_t *pBuffer;
+ uint32_t Length;
+} I2C_WRType;
+//SubAddrType
+#define I2C_SUBADDR_1BYTE (1)
+#define I2C_SUBADDR_2BYTE (2)
+#define I2C_SUBADDR_OTHER (3)
+
+//remap
+#define I2C_REMAP_ENABLE (1)
+#define I2C_REMAP_DISABLE (0)
+
+/* Private macros ------------------------------------------------------------*/
+
+#define IS_I2C_GC(__GC__) (((__GC__) == I2C_GENERALCALLACK_ENABLE) ||\
+ ((__GC__) == I2C_GENERALCALLACK_DISABLE))
+
+#define IS_I2C_AA(__AA__) (((__AA__) == I2C_ASSERTACKNOWLEDGE_ENABLE) ||\
+ ((__AA__) == I2C_ASSERTACKNOWLEDGE_DISABLE))
+
+#define IS_I2C_CLKSRC(__CLKSRC__) (((__CLKSRC__) == I2C_CLOCKSOURCE_APBD256) ||\
+ ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD224) ||\
+ ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD192) ||\
+ ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD160) ||\
+ ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD960) ||\
+ ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD120) ||\
+ ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD60) ||\
+ ((__CLKSRC__) == I2C_CLOCKSOURCE_TIM3OFD8))
+
+#define I2C_SUBADDR_TYPE(__TYPE__) (((__TYPE__) == I2C_SUBADDR_1BYTE) ||\
+ ((__TYPE__) == I2C_SUBADDR_2BYTE) ||\
+ ((__TYPE__) == I2C_SUBADDR_OTHER))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C)
+
+
+/* Exported Functions ------------------------------------------------------- */
+/* I2C Exported Functions Group1:
+ (De)Initialization ------------------------*/
+void I2C_DeInit(uint32_t remap);
+void I2C_StructInit(I2C_InitType *InitStruct);
+void I2C_Init(I2C_InitType *InitStruct);
+/* I2C Exported Functions Group2:
+ Interrupt ---------------------------------*/
+void I2C_INTConfig(uint32_t NewState);
+uint8_t I2C_GetINTStatus(void);
+void I2C_ClearINTStatus(void);
+/* I2C Exported Functions Group3:
+ Transfer datas ----------------------------*/
+uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct);
+uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct);
+/* I2C Exported Functions Group4:
+ MISC Configuration ------------------------*/
+void I2C_Cmd(uint32_t NewState);
+
+/* I2C Exported Functions Group5:
+ Others ------------------------------------*/
+void I2C_AssertAcknowledgeConfig(uint32_t NewState);
+uint8_t I2C_ReceiveData(void);
+void I2C_SendData(uint8_t Dat);
+void I2C_GenerateSTART(uint32_t NewState);
+void I2C_GenerateSTOP(uint32_t NewState);
+uint8_t I2C_GetStatusCode(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_I2C_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_iso7816.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_iso7816.h
new file mode 100644
index 0000000000000000000000000000000000000000..2c2cf10ba00051cca1a0077fac23b406e3cab245
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_iso7816.h
@@ -0,0 +1,174 @@
+/**
+ ******************************************************************************
+ * @file lib_iso7816.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief ISO7816 library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_ISO7816_H
+#define __LIB_ISO7816_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+ uint32_t FirstBit;
+ uint32_t Parity;
+ uint32_t Baudrate;
+ uint32_t TXRetry;
+ uint32_t RXACKLength;
+ uint32_t TXNACKLength;
+} ISO7816_InitType;
+//FirstBit
+#define ISO7816_FIRSTBIT_MSB (0UL)
+#define ISO7816_FIRSTBIT_LSB ISO7816_CFG_LSB
+#define IS_ISO7816_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == ISO7816_FIRSTBIT_MSB) ||\
+ ((__FIRSTBIT__) == ISO7816_FIRSTBIT_LSB))
+//Parity
+#define ISO7816_PARITY_EVEN (0UL)
+#define ISO7816_PARITY_ODD ISO7816_CFG_CHKP
+#define IS_ISO7816_PARITY(__PARITY__) (((__PARITY__) == ISO7816_PARITY_EVEN) ||\
+ ((__PARITY__) == ISO7816_PARITY_ODD))
+//Baudrate
+#define IS_ISO7816_BAUDRATE(__BAUDRATE__) ((200UL <= (__BAUDRATE__)) &&\
+ ((__BAUDRATE__) <= 2625000UL))
+//TXRetry
+#define ISO7816_TXRTY_0 ((0x00U << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_1 ((0x01U << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_2 ((0x02U << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_3 ((0x03U << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_4 ((0x04U << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_5 ((0x05U << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_6 ((0x06U << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_7 ((0x07U << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_8 ((0x08U << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_9 ((0x09U << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_10 ((0x0AU << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_11 ((0x0BU << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_12 ((0x0CU << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_13 ((0x0DU << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_14 ((0x0EU << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define ISO7816_TXRTY_15 ((0x0FU << ISO7816_CFG_TXRTYCNT_Pos) \
+ | (1U << 10))
+#define IS_ISO7816_TXRTY(__TXRTY__) (((__TXRTY__) == ISO7816_TXRTY_0) || \
+ ((__TXRTY__) == ISO7816_TXRTY_1) || \
+ ((__TXRTY__) == ISO7816_TXRTY_2) || \
+ ((__TXRTY__) == ISO7816_TXRTY_3) || \
+ ((__TXRTY__) == ISO7816_TXRTY_4) || \
+ ((__TXRTY__) == ISO7816_TXRTY_5) || \
+ ((__TXRTY__) == ISO7816_TXRTY_6) || \
+ ((__TXRTY__) == ISO7816_TXRTY_7) || \
+ ((__TXRTY__) == ISO7816_TXRTY_8) || \
+ ((__TXRTY__) == ISO7816_TXRTY_9) || \
+ ((__TXRTY__) == ISO7816_TXRTY_10) || \
+ ((__TXRTY__) == ISO7816_TXRTY_11) || \
+ ((__TXRTY__) == ISO7816_TXRTY_12) || \
+ ((__TXRTY__) == ISO7816_TXRTY_13) || \
+ ((__TXRTY__) == ISO7816_TXRTY_14) || \
+ ((__TXRTY__) == ISO7816_TXRTY_15))
+//RXACKLength
+#define ISO7816_RXACKLEN_2 (0UL)
+#define ISO7816_RXACKLEN_1 (ISO7816_CFG_RXACKSET)
+#define IS_ISO7816_RXACKLEN(__RXACKLEN__) (((__RXACKLEN__) == ISO7816_RXACKLEN_2) ||\
+ ((__RXACKLEN__) == ISO7816_RXACKLEN_1))
+//TXNACKLength
+#define ISO7816_TXNACKLEN_0 (0UL)
+#define ISO7816_TXNACKLEN_1 (ISO7816_CFG_AUTORXACK)
+#define ISO7816_TXNACKLEN_2 (ISO7816_CFG_AUTORXACK | ISO7816_CFG_ACKLEN)
+#define IS_ISO7816_TXNACKLEN(__TXNACKLEN__) (((__TXNACKLEN__) == ISO7816_TXNACKLEN_0) ||\
+ ((__TXNACKLEN__) == ISO7816_TXNACKLEN_1) ||\
+ ((__TXNACKLEN__) == ISO7816_TXNACKLEN_2))
+
+#define IS_ISO7816_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x80)
+
+//interrupt
+#define ISO7816_INT_TXRTYERR ISO7816_CFG_TXRTYERRIE
+#define ISO7816_INT_RXOV ISO7816_CFG_RXOVIE
+#define ISO7816_INT_TXDONE ISO7816_CFG_TXDONEIE
+#define ISO7816_INT_RX ISO7816_CFG_RXIE
+#define ISO7816_INT_RXERR ISO7816_CFG_RXERRIE
+#define ISO7816_INT_Msk (ISO7816_INT_TXRTYERR \
+ |ISO7816_INT_RXOV \
+ |ISO7816_INT_TXDONE \
+ |ISO7816_INT_RX \
+ |ISO7816_INT_RXERR)
+#define IS_ISO7816_INT(__INT__) ((((__INT__) & ISO7816_INT_Msk) != 0U) &&\
+ (((__INT__) & ~ISO7816_INT_Msk) == 0U))
+
+//INTStatus
+#define ISO7816_INTSTS_TXRTYERR ISO7816_INFO_TXRTYERRIF
+#define ISO7816_INTSTS_RXOV ISO7816_INFO_RXOVIF
+#define ISO7816_INTSTS_TXDONE ISO7816_INFO_TXDONEIF
+#define ISO7816_INTSTS_RX ISO7816_INFO_RXIF
+#define ISO7816_INTSTS_RXERR ISO7816_INFO_RXERRIF
+#define ISO7816_INTSTS_Msk (ISO7816_INTSTS_TXRTYERR \
+ |ISO7816_INTSTS_RXOV \
+ |ISO7816_INTSTS_TXDONE \
+ |ISO7816_INTSTS_RX \
+ |ISO7816_INTSTS_RXERR)
+#define IS_ISO7816_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == ISO7816_INTSTS_TXRTYERR) ||\
+ ((__INTFLAG__) == ISO7816_INTSTS_RXOV) ||\
+ ((__INTFLAG__) == ISO7816_INTSTS_TXDONE) ||\
+ ((__INTFLAG__) == ISO7816_INTSTS_RX) ||\
+ ((__INTFLAG__) == ISO7816_INTSTS_RXERR))
+
+#define IS_ISO7816_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&ISO7816_INTSTS_Msk) != 0U) &&\
+ (((__INTFLAG__)&(~ISO7816_INTSTS_Msk)) == 0U))
+//status
+#define ISO7816_FLAG_DMATXDONE ISO7816_INFO_DMATXDONE
+#define IS_ISO7816_FLAGR(__FLAG__) ((__FLAG__) == ISO7816_FLAG_DMATXDONE)
+#define IS_ISO7816_FLAGC(__FLAG__) ((__FLAG__) == ISO7816_FLAG_DMATXDONE)
+
+/****************************** ISO7816 Instances *****************************/
+#define IS_ISO7816_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ISO78160) || \
+ ((INSTANCE) == ISO78161))
+
+/* Exported Functions ------------------------------------------------------- */
+void ISO7816_DeInit(ISO7816_Type *ISO7816x);
+void ISO7816_StructInit(ISO7816_InitType *InitStruct);
+void ISO7816_Init(ISO7816_Type *ISO7816x, ISO7816_InitType *Init_Struct);
+void ISO7816_Cmd(ISO7816_Type *ISO7816x, uint32_t NewState);
+void ISO7816_BaudrateConfig(ISO7816_Type *ISO7816x, uint32_t BaudRate);
+void ISO7816_CLKDIVConfig(ISO7816_Type *ISO7816x, uint32_t Prescaler);
+void ISO7816_CLKOutputCmd(ISO7816_Type *ISO7816x, uint32_t NewState);
+void ISO7816_SendData(ISO7816_Type *ISO7816x, uint8_t ch);
+uint8_t ISO7816_ReceiveData(ISO7816_Type *ISO7816x);
+void ISO7816_INTConfig(ISO7816_Type *ISO7816x, uint32_t INTMask, uint8_t NewState);
+uint8_t ISO7816_GetINTStatus(ISO7816_Type *ISO7816x, uint32_t INTMask);
+void ISO7816_ClearINTStatus(ISO7816_Type *ISO7816x, uint32_t INTMask);
+uint8_t ISO7816_GetFlag(ISO7816_Type *ISO7816x, uint32_t FlagMask);
+void ISO7816_ClearFlag(ISO7816_Type *ISO7816x, uint32_t FlagMask);
+uint8_t ISO7816_GetLastTransmitACK(ISO7816_Type *ISO7816x);
+uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_Type *ISO7816x);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_ISO7816_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_lcd.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_lcd.h
new file mode 100644
index 0000000000000000000000000000000000000000..d9bc415477418108a593f0f5552eac721f8925f5
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_lcd.h
@@ -0,0 +1,147 @@
+/**
+ ******************************************************************************
+ * @file lib_lcd.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief LCD library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_LCD_H
+#define __LIB_LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+/* LCD COMx IO typedef */
+typedef struct
+{
+ __IO uint32_t *GPIO;
+ uint16_t Pin;
+}LCD_COMIO;
+
+typedef struct
+{
+ uint32_t Type;
+ uint32_t Drv;
+ uint32_t FRQ;
+ uint32_t SWPR;
+ uint32_t FBMODE;
+ uint32_t BKFILL;
+} LCD_InitType;
+
+typedef struct
+{
+ uint32_t SegCtrl0;
+ uint32_t SegCtrl1;
+ uint16_t SegCtrl2;
+ uint32_t COMMode;
+} LCD_IOInitType;
+
+/************** Bits definition for ANA_REG6 register ******************/
+#define ANA_REG6_VLCD_0 (0x0U << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_1 (0x1U << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_2 (0x2U << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_3 (0x3U << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_4 (0x4U << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_5 (0x5U << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_6 (0x6U << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_7 (0x7U << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_8 (0x8U << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_9 (0x9U << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_A (0xAU << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_B (0xBU << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_C (0xCU << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_D (0xDU << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_E (0xEU << ANA_REG6_VLCD_Pos)
+#define ANA_REG6_VLCD_F (0xFU << ANA_REG6_VLCD_Pos)
+
+/************** Bits definition for LCD_CTRL register ******************/
+
+/************** Bits definition for LCD_CTRL2 register ******************/
+
+//Type
+#define LCD_TYPE_4COM (0x0U << LCD_CTRL_TYPE_Pos) /*!< 0x00000000 */
+#define LCD_TYPE_6COM (0x1U << LCD_CTRL_TYPE_Pos) /*!< 0x00000010 */
+#define LCD_TYPE_8COM (0x2U << LCD_CTRL_TYPE_Pos) /*!< 0x00000020 */
+#define IS_LCD_TYPE(__TYPE__) (((__TYPE__) == LCD_TYPE_4COM) ||\
+ ((__TYPE__) == LCD_TYPE_6COM) ||\
+ ((__TYPE__) == LCD_TYPE_8COM))
+
+//DrivingRes
+#define LCD_DRV_300 (0x0U << LCD_CTRL_DRV_Pos) /*!< 0x00000000 */
+#define LCD_DRV_600 (0x1U << LCD_CTRL_DRV_Pos) /*!< 0x00000004 */
+#define LCD_DRV_150 (0x2U << LCD_CTRL_DRV_Pos) /*!< 0x00000008 */
+#define LCD_DRV_200 (0x3U << LCD_CTRL_DRV_Pos) /*!< 0x0000000C */
+#define IS_LCD_DRV(__DRV__) (((__DRV__) == LCD_DRV_300) ||\
+ ((__DRV__) == LCD_DRV_600) ||\
+ ((__DRV__) == LCD_DRV_150) ||\
+ ((__DRV__) == LCD_DRV_200))
+
+//ScanFRQ
+#define LCD_FRQ_64H (0x0U << LCD_CTRL_FRQ_Pos) /*!< 0x00000000 */
+#define LCD_FRQ_128H (0x1U << LCD_CTRL_FRQ_Pos) /*!< 0x00000001 */
+#define LCD_FRQ_256H (0x2U << LCD_CTRL_FRQ_Pos) /*!< 0x00000002 */
+#define LCD_FRQ_512H (0x3U << LCD_CTRL_FRQ_Pos) /*!< 0x00000003 */
+#define IS_LCD_FRQ(__FRQ__) (((__FRQ__) == LCD_FRQ_64H) ||\
+ ((__FRQ__) == LCD_FRQ_128H) ||\
+ ((__FRQ__) == LCD_FRQ_256H) ||\
+ ((__FRQ__) == LCD_FRQ_512H))
+
+#define IS_LCD_SWPR(__SWPR__) ((__SWPR__) <= 0xFFUL)
+
+//SwitchMode
+#define LCD_FBMODE_BUFA (0x0U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000000 */
+#define LCD_FBMODE_BUFAB (0x1U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000040 */
+#define LCD_FBMODE_BUFABLANK (0x2U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000080 */
+#define IS_LCD_FBMODE(__FBMODE__) (((__FBMODE__) == LCD_FBMODE_BUFA) ||\
+ ((__FBMODE__) == LCD_FBMODE_BUFAB) ||\
+ ((__FBMODE__) == LCD_FBMODE_BUFABLANK))
+
+//BlankFill
+#define LCD_BKFILL_1 LCD_CTRL2_BKFILL
+#define LCD_BKFILL_0 0
+#define IS_LCD_BKFILL(__BKFILL__) (((__BKFILL__) == LCD_BKFILL_1) || ((__BKFILL__) == LCD_BKFILL_0))
+
+//ComMode
+#define LCD_COMMOD_4COM 1
+#define LCD_COMMOD_6COM 3
+#define LCD_COMMOD_8COM 7
+#define IS_LCD_COMMOD(__COMMOD__) (((__COMMOD__) == LCD_COMMOD_4COM) ||\
+ ((__COMMOD__) == LCD_COMMOD_6COM) ||\
+ ((__COMMOD__) == LCD_COMMOD_8COM))
+
+//BiasSelection
+#define LCD_BMODE_DIV3 0
+#define LCD_BMODE_DIV4 ANA_REG6_LCDBMODE
+#define IS_LCD_BMODE(__BMODE__) (((__BMODE__) == LCD_BMODE_DIV3) ||\
+ ((__BMODE__) == LCD_BMODE_DIV4))
+
+/****************************** LCD Instances *********************************/
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
+
+/* Exported Functions ------------------------------------------------------- */
+/* LCD Exported Functions Group1:
+ (De)Initialization -------------------------*/
+void LCD_DeInit(void);
+void LCD_StructInit(LCD_InitType *LCD_InitStruct);
+void LCD_Init(LCD_InitType *InitStruct);
+/* LCD Exported Functions Group1:
+ MISC Configuration -------------------------*/
+void LCD_Cmd(LCD_IOInitType *IOInitType, uint32_t NewState);
+void LCD_BiasModeConfig(uint32_t BiasSelection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_LCD_H */
+
+/*********************************** END OF FILE ******************************/
+
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_misc.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_misc.h
new file mode 100644
index 0000000000000000000000000000000000000000..b5d23f37e6ee7cacdbfe2c1f18507781c870c96c
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_misc.h
@@ -0,0 +1,85 @@
+/**
+ ******************************************************************************
+ * @file lib_misc.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief MISC library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_MISC_H
+#define __LIB_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+//FlagMask
+#define MISC_FLAG_LOCKUP MISC1_SRAMINT_LOCKUP
+#define MISC_FLAG_PIAC MISC1_SRAMINT_PIAC
+#define MISC_FLAG_HIAC MISC1_SRAMINT_HIAC
+#define MISC_FLAG_PERR MISC1_SRAMINT_PERR
+#define MISC_FLAG_Msk (MISC_FLAG_LOCKUP | MISC_FLAG_PIAC | MISC_FLAG_HIAC | MISC_FLAG_PERR)
+
+//MISC interrupt
+#define MISC_INT_LOCK MISC1_SRAMINIT_LOCKIE
+#define MISC_INT_PIAC MISC1_SRAMINIT_PIACIE
+#define MISC_INT_HIAC MISC1_SRAMINIT_HIACIE
+#define MISC_INT_PERR MISC1_SRAMINIT_PERRIE
+#define MISC_INT_Msk (MISC_INT_LOCK | MISC_INT_PIAC | MISC_INT_HIAC | MISC_INT_PERR)
+
+//IR
+#define MISC_IREN_TX0 (0x1U << MISC1_IREN_IREN_Pos)
+#define MISC_IREN_TX1 (0x1U << MISC1_IREN_IREN_Pos)
+#define MISC_IREN_TX2 (0x1U << MISC1_IREN_IREN_Pos)
+#define MISC_IREN_TX3 (0x1U << MISC1_IREN_IREN_Pos)
+#define MISC_IREN_TX4 (0x1U << MISC1_IREN_IREN_Pos)
+#define MISC_IREN_TX5 (0x1U << MISC1_IREN_IREN_Pos)
+#define MISC_IREN_Msk (0x3FUL)
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_MISC_FLAGR(__FLAGR__) (((__FLAGR__) == MISC_FLAG_LOCKUP) ||\
+ ((__FLAGR__) == MISC_FLAG_PIAC) ||\
+ ((__FLAGR__) == MISC_FLAG_HIAC) ||\
+ ((__FLAGR__) == MISC_FLAG_PERR))
+
+#define IS_MISC_FLAGC(__FLAGC__) ((((__FLAGC__) & MISC_FLAG_Msk) != 0U) &&\
+ (((__FLAGC__) & ~MISC_FLAG_Msk) == 0U))
+
+#define IS_MISC_INT(__INT__) ((((__INT__) & MISC_INT_Msk) != 0U) &&\
+ (((__INT__) &~MISC_INT_Msk) == 0U))
+
+#define IS_MISC_IREN(__IREN__) ((((__IREN__) & MISC_IREN_Msk) != 0U) &&\
+ (((__IREN__) & ~MISC_IREN_Msk) == 0U))
+
+/****************************** MISC Instances ********************************/
+#define IS_MISC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MISC1)
+
+#define IS_MISC2_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MISC2)
+
+/* Exported Functions ------------------------------------------------------- */
+uint8_t MISC_GetFlag(uint32_t FlagMask);
+void MISC_ClearFlag(uint32_t FlagMask);
+void MISC_INTConfig(uint32_t INTMask, uint32_t NewState);
+void MISC_SRAMParityCmd(uint32_t NewState);
+uint32_t MISC_GetSRAMPEAddr(void);
+uint32_t MISC_GetAPBErrAddr(void);
+uint32_t MISC_GetAHBErrAddr(void);
+void MISC_IRCmd(uint32_t IRx, uint32_t NewState);
+void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow);
+void MISC_HardFaultCmd(uint32_t NewState);
+void MISC_LockResetCmd(uint32_t NewState);
+void MISC_IRQLATConfig(uint8_t Latency);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_MISC_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_pmu.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_pmu.h
new file mode 100644
index 0000000000000000000000000000000000000000..401aa777a32705ac2f0fd7ee3bfa6b46e5810322
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_pmu.h
@@ -0,0 +1,362 @@
+/**
+ ******************************************************************************
+ * @file lib_pmu.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief PMU library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_PMU_H
+#define __LIB_PMU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+/**
+ * Deep-sleep low-power configuration
+*/
+typedef struct
+{
+ uint32_t COMP1Power; /* Comparator 1 power control */
+ uint32_t COMP2Power; /* Comparator 2 power control */
+ uint32_t TADCPower; /* Tiny ADC power control */
+ uint32_t BGPPower; /* BGP power control */
+ uint32_t AVCCPower; /* AVCC power control */
+// uint32_t LCDPower; /* LCD controller power control */
+ uint32_t VDCINDetector; /* VDCIN detector control */
+ uint32_t VDDDetector; /* VDD detector control */
+ uint32_t AHBPeriphralDisable; /* AHB Periphral clock disable selection */
+ uint32_t APBPeriphralDisable; /* APB Periphral clock disable selection */
+} PMU_LowPWRTypeDef;
+
+/************** Bits definition for ANA_REG8 register ******************/
+#define ANA_REG8_VDDPVDSEL_0 (0x0UL << ANA_REG8_VDDPVDSEL_Pos)
+#define ANA_REG8_VDDPVDSEL_1 (0x1UL << ANA_REG8_VDDPVDSEL_Pos)
+#define ANA_REG8_VDDPVDSEL_2 (0x2UL << ANA_REG8_VDDPVDSEL_Pos)
+#define ANA_REG8_VDDPVDSEL_3 (0x3UL << ANA_REG8_VDDPVDSEL_Pos)
+#define ANA_REG8_VDDPVDSEL_4 (0x4UL << ANA_REG8_VDDPVDSEL_Pos)
+#define ANA_REG8_VDDPVDSEL_5 (0x5UL << ANA_REG8_VDDPVDSEL_Pos)
+#define ANA_REG8_VDDPVDSEL_6 (0x6UL << ANA_REG8_VDDPVDSEL_Pos)
+#define ANA_REG8_VDDPVDSEL_7 (0x7UL << ANA_REG8_VDDPVDSEL_Pos)
+
+/****************************** PMU Instances *********************************/
+#define IS_PMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU)
+
+/****************************** PMU_RETRAM Instances **************************/
+#define IS_PMU_RETRAM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU_RETRAM)
+
+/* COMP1Power */
+#define PMU_COMP1PWR_ON (ANA_REG3_CMP1PDN)
+#define PMU_COMP1PWR_OFF (0UL)
+#define IS_PMU_COMP1PWR(__COMP1PWR__) (((__COMP1PWR__) == PMU_COMP1PWR_ON) ||\
+ ((__COMP1PWR__) == PMU_COMP1PWR_OFF))
+/* COMP2Power */
+#define PMU_COMP2PWR_ON (ANA_REG3_CMP2PDN)
+#define PMU_COMP2PWR_OFF (0UL)
+#define IS_PMU_COMP2PWR(__COMP2PWR__) (((__COMP2PWR__) == PMU_COMP2PWR_ON) ||\
+ ((__COMP2PWR__) == PMU_COMP2PWR_OFF))
+/* TADCPower */
+#define PMU_TADCPWR_ON (ANA_REGF_ADTPDN)
+#define PMU_TADCPWR_OFF (0UL)
+#define IS_PMU_TADCPWR(__TADCPWR__) (((__TADCPWR__) == PMU_TADCPWR_ON) ||\
+ ((__TADCPWR__) == PMU_TADCPWR_OFF))
+/* BGPPower */
+#define PMU_BGPPWR_ON (0UL)
+#define PMU_BGPPWR_OFF (ANA_REG3_BGPPD)
+#define IS_PMU_BGPPWR(__BGPPWR__) (((__BGPPWR__) == PMU_BGPPWR_ON) ||\
+ ((__BGPPWR__) == PMU_BGPPWR_OFF))
+/* AVCCPower */
+#define PMU_AVCCPWR_ON (0UL)
+#define PMU_AVCCPWR_OFF (ANA_REG8_AVCCLDOPD)
+#define IS_PMU_AVCCPWR(__AVCCPWR__) (((__AVCCPWR__) == PMU_AVCCPWR_ON) ||\
+ ((__AVCCPWR__) == PMU_AVCCPWR_OFF))
+
+/* VDCINDetector */
+#define PMU_VDCINDET_ENABLE (0UL)
+#define PMU_VDCINDET_DISABLE (ANA_REGA_VDCINDETPD)
+#define IS_PMU_VDCINDET(__VDCINDET__) (((__VDCINDET__) == PMU_VDCINDET_ENABLE) ||\
+ ((__VDCINDET__) == PMU_VDCINDET_DISABLE))
+
+/* VDDDetector */
+#define PMU_VDDDET_ENABLE (0UL)
+#define PMU_VDDDET_DISABLE (ANA_REG9_VDDDETPD)
+#define IS_PMU_VDDDET(__VDDDET__) (((__VDDDET__) == PMU_VDDDET_ENABLE) ||\
+ ((__VDDDET__) == PMU_VDDDET_DISABLE))
+
+#define PMU_APB_ALL (MISC2_PCLKEN_DMA \
+ |MISC2_PCLKEN_I2C \
+ |MISC2_PCLKEN_SPI1 \
+ |MISC2_PCLKEN_UART0 \
+ |MISC2_PCLKEN_UART1 \
+ |MISC2_PCLKEN_UART2 \
+ |MISC2_PCLKEN_UART3 \
+ |MISC2_PCLKEN_UART4 \
+ |MISC2_PCLKEN_UART5 \
+ |MISC2_PCLKEN_ISO78160 \
+ |MISC2_PCLKEN_ISO78161 \
+ |MISC2_PCLKEN_TIMER \
+ |MISC2_PCLKEN_MISC1 \
+ |MISC2_PCLKEN_MISC2 \
+ |MISC2_PCLKEN_U32K0 \
+ |MISC2_PCLKEN_U32K1 \
+ |MISC2_PCLKEN_SPI2 \
+ |MISC2_PCLKEN_SPI3)
+#define PMU_APB_DMA MISC2_PCLKEN_DMA
+#define PMU_APB_I2C MISC2_PCLKEN_I2C
+#define PMU_APB_SPI1 MISC2_PCLKEN_SPI1
+#define PMU_APB_UART0 MISC2_PCLKEN_UART0
+#define PMU_APB_UART1 MISC2_PCLKEN_UART1
+#define PMU_APB_UART2 MISC2_PCLKEN_UART2
+#define PMU_APB_UART3 MISC2_PCLKEN_UART3
+#define PMU_APB_UART4 MISC2_PCLKEN_UART4
+#define PMU_APB_UART5 MISC2_PCLKEN_UART5
+#define PMU_APB_ISO78160 MISC2_PCLKEN_ISO78160
+#define PMU_APB_ISO78161 MISC2_PCLKEN_ISO78161
+#define PMU_APB_TIMER MISC2_PCLKEN_TIMER
+#define PMU_APB_MISC1 MISC2_PCLKEN_MISC1
+#define PMU_APB_U32K0 MISC2_PCLKEN_U32K0
+#define PMU_APB_U32K1 MISC2_PCLKEN_U32K1
+#define PMU_APB_SPI2 MISC2_PCLKEN_SPI2
+#define PMU_APB_SPI3 MISC2_PCLKEN_SPI3
+
+#define PMU_AHB_ALL (MISC2_HCLKEN_DMA \
+ |MISC2_HCLKEN_GPIO \
+ |MISC2_HCLKEN_CRYPT)
+// |MISC2_HCLKEN_LCD
+#define PMU_AHB_DMA MISC2_HCLKEN_DMA
+#define PMU_AHB_GPIO MISC2_HCLKEN_GPIO
+//#define PMU_AHB_LCD MISC2_HCLKEN_LCD
+#define PMU_AHB_CRYPT MISC2_HCLKEN_CRYPT
+
+//PMU interrupt
+#define PMU_INT_IOAEN PMU_CONTROL_INT_IOA_EN
+#define PMU_INT_32K PMU_CONTROL_INT_32K_EN
+#define PMU_INT_6M PMU_CONTROL_INT_6M_EN
+#define PMU_INT_Msk (PMU_INT_IOAEN \
+ |PMU_INT_32K \
+ |PMU_INT_6M)
+#define IS_PMU_INT(__INT__) ((((__INT__)&PMU_INT_Msk) != 0UL) &&\
+ (((__INT__)&(~PMU_INT_Msk)) == 0UL))
+
+//INTStatus
+#define PMU_INTSTS_32K PMU_STS_INT_32K
+#define PMU_INTSTS_6M PMU_STS_INT_6M
+#define PMU_INTSTS_Msk (PMU_INTSTS_32K \
+ |PMU_INTSTS_6M)
+#define IS_PMU_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == PMU_INTSTS_32K) ||\
+ ((__INTFLAG__) == PMU_INTSTS_6M))
+
+#define IS_PMU_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&PMU_INTSTS_Msk) != 0UL) &&\
+ (((__INTFLAG__)&(~PMU_INTSTS_Msk)) == 0UL))
+
+/***** Reset Source Status *****/
+#define PMU_RSTSRC_EXTRST PMU_STS_EXTRST
+#define PMU_RSTSRC_PORST PMU_STS_PORST
+#define PMU_RSTSRC_DPORST PMU_STS_DPORST
+#define PMU_RSTSRC_WDTRST PMU_STS_WDTRST
+#define PMU_RSTSRC_SFTRST PMU_STS_SFTRST
+#define PMU_RSTSRC_MODERST PMU_STS_MODERST
+#define PMU_RSTSRC_Msk (PMU_RSTSRC_EXTRST |\
+ PMU_RSTSRC_PORST |\
+ PMU_RSTSRC_DPORST |\
+ PMU_RSTSRC_WDTRST |\
+ PMU_RSTSRC_SFTRST |\
+ PMU_RSTSRC_MODERST)
+#define PMU_RSTSRC_ALL PMU_RSTSRC_Msk
+#define PMU_RESETSRC(__RSTSRC__) (((__RSTSRC__) == PMU_RSTSRC_EXTRST) ||\
+ ((__RSTSRC__) == PMU_RSTSRC_PORST) ||\
+ ((__RSTSRC__) == PMU_RSTSRC_DPORST) ||\
+ ((__RSTSRC__) == PMU_RSTSRC_WDTRST) ||\
+ ((__RSTSRC__) == PMU_RSTSRC_SFTRST) ||\
+ ((__RSTSRC__) == PMU_RSTSRC_MODERST))
+#define PMU_RESETSRC_CLR(__RSTSRC__) ((((__RSTSRC__) & PMU_RSTSRC_Msk) != 0UL) &&\
+ (((__RSTSRC__) & (~PMU_RSTSRC_Msk)) == 0UL))
+
+/***** DeepSleep wakeup Source Status *****/
+#define PMU_DSLEEPWKUSRC_MODE PMU_STS_WKUMODE
+#define PMU_DSLEEPWKUSRC_XTAL PMU_STS_WKUXTAL
+#define PMU_DSLEEPWKUSRC_U32K PMU_STS_WKUU32K
+#define PMU_DSLEEPWKUSRC_ANA PMU_STS_WKUANA
+#define PMU_DSLEEPWKUSRC_RTC PMU_STS_WKURTC
+#define PMU_DSLEEPWKUSRC_IOA PMU_STS_WKUIOA
+#define PMU_DSLEEPWKUSRC_Msk (PMU_DSLEEPWKUSRC_MODE |\
+ PMU_DSLEEPWKUSRC_XTAL |\
+ PMU_DSLEEPWKUSRC_U32K |\
+ PMU_DSLEEPWKUSRC_ANA |\
+ PMU_DSLEEPWKUSRC_RTC |\
+ PMU_DSLEEPWKUSRC_IOA)
+#define IS_PMU_DSLEEPWKUSRC(__SRC__) (((__SRC__) == PMU_DSLEEPWKUSRC_MODE) ||\
+ ((__SRC__) == PMU_DSLEEPWKUSRC_XTAL) ||\
+ ((__SRC__) == PMU_DSLEEPWKUSRC_U32K) ||\
+ ((__SRC__) == PMU_DSLEEPWKUSRC_ANA) ||\
+ ((__SRC__) == PMU_DSLEEPWKUSRC_RTC) ||\
+ ((__SRC__) == PMU_DSLEEPWKUSRC_IOA))
+
+
+//Status
+#define PMU_STS_32K PMU_STS_EXIST_32K
+#define PMU_STS_6M PMU_STS_EXIST_6M
+#define IS_PMU_FLAG(__FLAG__) (((__FLAG__) == PMU_STS_32K) || ((__FLAG__) == PMU_STS_6M))
+
+//Wakeup_Event
+#define IOA_DISABLE (0UL)
+#define IOA_RISING (1UL)
+#define IOA_FALLING (2UL)
+#define IOA_HIGH (3UL)
+#define IOA_LOW (4UL)
+#define IOA_EDGEBOTH (5UL)
+#define IS_PMU_WAKEUP(__WAKEUP__) (((__WAKEUP__) == IOA_DISABLE) ||\
+ ((__WAKEUP__) == IOA_RISING) ||\
+ ((__WAKEUP__) == IOA_FALLING) ||\
+ ((__WAKEUP__) == IOA_HIGH) ||\
+ ((__WAKEUP__) == IOA_LOW) ||\
+ ((__WAKEUP__) == IOA_EDGEBOTH))
+
+/***** Wakeup_Event (PMU_SleepWKUSRCConfig_RTC) *****/
+#define PMU_RTCEVT_ALARM RTC_INTSTS_INTSTS10
+#define PMU_RTCEVT_WKUCNT RTC_INTSTS_INTSTS6
+#define PMU_RTCEVT_MIDNIGHT RTC_INTSTS_INTSTS5
+#define PMU_RTCEVT_WKUHOUR RTC_INTSTS_INTSTS4
+#define PMU_RTCEVT_WKUMIN RTC_INTSTS_INTSTS3
+#define PMU_RTCEVT_WKUSEC RTC_INTSTS_INTSTS2
+#define PMU_RTCEVT_TIMEILLE RTC_INTSTS_INTSTS1
+#define PMU_RTCEVT_ITVSITV RTC_INTSTS_INTSTS0
+#define PMU_RTCEVT_Msk (PMU_RTCEVT_WKUCNT \
+ |PMU_RTCEVT_MIDNIGHT \
+ |PMU_RTCEVT_WKUHOUR \
+ |PMU_RTCEVT_WKUMIN \
+ |PMU_RTCEVT_WKUSEC \
+ |PMU_RTCEVT_TIMEILLE \
+ |PMU_RTCEVT_ITVSITV \
+ |PMU_RTCEVT_ALARM)
+#define IS_PMU_RTCEVT(__RTCEVT__) ((((__RTCEVT__)&PMU_RTCEVT_Msk) != 0UL) &&\
+ (((__RTCEVT__)&(~PMU_RTCEVT_Msk)) == 0UL))
+
+
+/***** BATRTCDisc (PMU_BATDischargeConfig) *****/
+#define PMU_BAT1 ANA_REG6_BAT1DISC
+#define PMU_BATRTC ANA_REG6_BATRTCDISC
+#define IS_PMU_BATRTCDISC(__BATRTCDISC__) (((__BATRTCDISC__) == PMU_BAT1) || ((__BATRTCDISC__) == PMU_BATRTC))
+
+/***** PowerThreshold (PMU_PowerAlarmTHConfig) *****/
+#define PMU_VDDALARM_4_5V ANA_REG8_VDDPVDSEL_0
+#define PMU_VDDALARM_4_2V ANA_REG8_VDDPVDSEL_1
+#define PMU_VDDALARM_3_9V ANA_REG8_VDDPVDSEL_2
+#define PMU_VDDALARM_3_6V ANA_REG8_VDDPVDSEL_3
+#define PMU_VDDALARM_3_2V ANA_REG8_VDDPVDSEL_4
+#define PMU_VDDALARM_2_9V ANA_REG8_VDDPVDSEL_5
+#define PMU_VDDALARM_2_6V ANA_REG8_VDDPVDSEL_6
+#define PMU_VDDALARM_2_3V ANA_REG8_VDDPVDSEL_7
+
+#define IS_PMU_VDDALARM_THR(__VDDALARM__) (((__VDDALARM__) == PMU_VDDALARM_4_5V) ||\
+ ((__VDDALARM__) == PMU_VDDALARM_4_2V) ||\
+ ((__VDDALARM__) == PMU_VDDALARM_3_9V) ||\
+ ((__VDDALARM__) == PMU_VDDALARM_3_6V) ||\
+ ((__VDDALARM__) == PMU_VDDALARM_3_2V) ||\
+ ((__VDDALARM__) == PMU_VDDALARM_2_9V) ||\
+ ((__VDDALARM__) == PMU_VDDALARM_2_6V) ||\
+ ((__VDDALARM__) == PMU_VDDALARM_2_3V))
+
+/***** RTCLDOSel (PMU_RTCLDOConfig) *****/
+#define PMU_RTCLDO_1_5 (0UL)
+#define PMU_RTCLDO_1_2 ANA_REGA_RTCVSEL
+
+/***** StatusMask (PMU_GetPowerStatus) *****/
+#define PMU_PWRSTS_AVCCLV ANA_COMPOUT_AVCCLV
+#define PMU_PWRSTS_VDCINDROP ANA_CMPOUT_VDCINDROP
+#define PMU_PWRSTS_VDDALARM ANA_CMPOUT_VDDALARM
+
+/***** PMU_PDNDSleepConfig *****/
+//VDCIN_PDNS
+#define PMU_VDCINPDNS_0 (0UL)
+#define PMU_VDCINPDNS_1 (ANA_CTRL_PDNS)
+#define IS_PMU_VDCINPDNS(__VDCINPDNS__) (((__VDCINPDNS__) == PMU_VDCINPDNS_0) ||\
+ ((__VDCINPDNS__) == PMU_VDCINPDNS_1))
+//VDD_PDNS
+#define PMU_VDDPDNS_0 (0UL)
+#define PMU_VDDPDNS_1 (ANA_CTRL_PDNS2)
+#define IS_PMU_VDDPDNS(__VDDPDNS__) (((__VDDPDNS__) == PMU_VDDPDNS_0) ||\
+ ((__VDDPDNS__) == PMU_VDDPDNS_1))
+
+#define PMU_VDDALARM_CHKFRE_NOCHECK (0x0UL << ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Pos)
+#define PMU_VDDALARM_CHKFRE_30US (0x1UL << ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Pos)
+#define IS_PMU_VDDALARM_CHKFRE(__CHKFRE__) (((__CHKFRE__) == PMU_VDDALARM_CHKFRE_NOCHECK) ||\
+ ((__CHKFRE__) == PMU_VDDALARM_CHKFRE_30US))
+
+#define IS_PMU_PWR_DEBSEL(__DEBSEL__) ((__DEBSEL__) < 256UL)
+
+/* Exported Functions ------------------------------------------------------- */
+
+uint32_t PMU_EnterDSleepMode(void);
+void PMU_EnterIdleMode(void);
+uint32_t PMU_EnterSleepMode(void);
+
+void PMU_INTConfig(uint32_t INTMask, uint32_t NewState);
+uint8_t PMU_GetINTStatus(uint32_t INTMask);
+void PMU_ClearINTStatus(uint32_t INTMask);
+
+uint8_t PMU_GetCrystalStatus(uint32_t Mask);
+uint16_t PMU_GetIOAAllINTStatus(void);
+uint8_t PMU_GetIOAINTStatus(uint16_t INTMask);
+void PMU_ClearIOAINTStatus(uint16_t INTMask);
+
+void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event);
+
+uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct);
+uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct);
+#ifndef __GNUC__
+void PMU_EnterIdle_LowPower(void);
+#endif
+void PMU_SleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority);
+void PMU_SleepWKUSRCConfig_RTC(uint32_t Wakeup_Event, uint32_t Priority);
+void PMU_DeepSleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event);
+void PMU_DeepSleepWKUSRCConfig_RTC(uint32_t Wakeup_Event);
+void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS);
+
+/***** BGP functions *****/
+void PMU_BGPCmd(uint32_t NewState);
+
+/***** VDD functions *****/
+void PMU_VDDAlarmConfig(uint32_t CheckTHR, uint32_t CheckFrequency);
+uint8_t PMU_GetVDDAlarmStatus(void);
+
+/***** AVCC functions *****/
+void PMU_AVCCCmd(uint32_t NewState);
+void PMU_AVCCOutputCmd(uint32_t NewState);
+void PMU_AVCCLVDetectorCmd(uint32_t NewState);
+uint8_t PMU_GetAVCCLVStatus(void);
+
+/***** VDCIN functions *****/
+void PMU_VDCINDetectorCmd(uint32_t NewState);
+uint8_t PMU_GetVDCINDropStatus(void);
+
+void PMU_PWRDEBSel(uint32_t DEBSel);
+
+/***** BAT functions *****/
+void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState);
+
+/***** Other functions *****/
+uint8_t PMU_GetModeStatus(void);
+uint8_t PMU_GetPowerStatus(uint32_t StatusMask);
+
+uint8_t PMU_GetResetSource(uint32_t Mask);
+void PMU_ClearResetSource(uint32_t Mask);
+uint32_t PMU_GetAllResetSource(void);
+
+uint8_t PMU_GetDSleepWKUSource(uint32_t Mask);
+uint32_t PMU_GetAllDSleepWKUSource(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_PMU_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_pwm.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_pwm.h
new file mode 100644
index 0000000000000000000000000000000000000000..1b194514bb5c7024d66a2edd42f853e0eb612cbe
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_pwm.h
@@ -0,0 +1,258 @@
+/**
+ ******************************************************************************
+ * @file lib_pwm.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief PWM library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_PWM_H
+#define __LIB_PWM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+ uint32_t ClockDivision;
+ uint32_t Mode;
+ uint32_t ClockSource;
+} PWM_BaseInitType;
+
+/************** Bits definition for PWMx_CTL register ******************/
+#define PWM_CTL_TESL_APBDIV128 (0x0U << PWM_CTL_TSEL_Pos) /*!< 0x00000000 */
+#define PWM_CTL_TESL_APBDIV1 (0x1U << PWM_CTL_TSEL_Pos) /*!< 0x00000008 */
+#define PWM_CTL_MC_STOP (0x0U << PWM_CTL_MC_Pos) /*!< 0x00000000 */
+#define PWM_CTL_MC_UP (0x1U << PWM_CTL_MC_Pos) /*!< 0x00000010 */
+#define PWM_CTL_MC_CONTINUE (0x2U << PWM_CTL_MC_Pos) /*!< 0x00000020 */
+#define PWM_CTL_MC_UPDOWN (0x3U << PWM_CTL_MC_Pos) /*!< 0x00000030 */
+#define PWM_CTL_ID_DIV2 (0x0U << PWM_CTL_ID_Pos) /*!< 0x00000000 */
+#define PWM_CTL_ID_DIV4 (0x1U << PWM_CTL_ID_Pos) /*!< 0x00000040 */
+#define PWM_CTL_ID_DIV8 (0x2U << PWM_CTL_ID_Pos) /*!< 0x00000080 */
+#define PWM_CTL_ID_DIV16 (0x3U << PWM_CTL_ID_Pos) /*!< 0x000000C0 */
+
+/************** Bits definition for PWMx_TAR register ******************/
+
+/************** Bits definition for PWMx_CCTLy register ******************/
+////////////#define PWM_CCTL_OUTMOD_CONST (0x00UL << PWM_CCTL_OUTMOD_Pos)
+#define PWM_CCTL_OUTMOD_SET (0x01UL << PWM_CCTL_OUTMOD_Pos)
+#define PWM_CCTL_OUTMOD_TOGGLE_RESET (0x02UL << PWM_CCTL_OUTMOD_Pos)
+#define PWM_CCTL_OUTMOD_SET_RESET (0x03UL << PWM_CCTL_OUTMOD_Pos)
+#define PWM_CCTL_OUTMOD_TOGGLE (0x04UL << PWM_CCTL_OUTMOD_Pos)
+#define PWM_CCTL_OUTMOD_RESET (0x05UL << PWM_CCTL_OUTMOD_Pos)
+#define PWM_CCTL_OUTMOD_TOGGLE_SET (0x06UL << PWM_CCTL_OUTMOD_Pos)
+#define PWM_CCTL_OUTMOD_RESET_SET (0x07UL << PWM_CCTL_OUTMOD_Pos)
+////////////////////
+
+//ClockDivision
+#define PWM_CLKDIV_2 (0x0U << PWM_CTL_ID_Pos)
+#define PWM_CLKDIV_4 (0x1U << PWM_CTL_ID_Pos)
+#define PWM_CLKDIV_8 (0x2U << PWM_CTL_ID_Pos)
+#define PWM_CLKDIV_16 (0x3U << PWM_CTL_ID_Pos)
+#define IS_PWM_CLKDIV(__CLKDIV__) (((__CLKDIV__) == PWM_CLKDIV_2) ||\
+ ((__CLKDIV__) == PWM_CLKDIV_4) ||\
+ ((__CLKDIV__) == PWM_CLKDIV_8) ||\
+ ((__CLKDIV__) == PWM_CLKDIV_16))
+
+//Mode
+#define PWM_MODE_STOP (0x0U << PWM_CTL_MC_Pos)
+#define PWM_MODE_UPCOUNT (0x1U << PWM_CTL_MC_Pos)
+#define PWM_MODE_CONTINUOUS (0x2U << PWM_CTL_MC_Pos)
+#define PWM_MODE_UPDOWN (0x3U << PWM_CTL_MC_Pos)
+#define IS_PWM_CNTMODE(__CNTMODE__) (((__CNTMODE__) == PWM_MODE_STOP) ||\
+ ((__CNTMODE__) == PWM_MODE_UPCOUNT) ||\
+ ((__CNTMODE__) == PWM_MODE_CONTINUOUS) ||\
+ ((__CNTMODE__) == PWM_MODE_UPDOWN))
+
+//ClockSource
+#define PWM_CLKSRC_APB (0x1U << PWM_CTL_TSEL_Pos)
+#define PWM_CLKSRC_APBD128 (0x0U << PWM_CTL_TSEL_Pos)
+#define IS_PWM_CLKSRC(__CLKSRC__) (((__CLKSRC__) == PWM_CLKSRC_APB) ||\
+ ((__CLKSRC__) == PWM_CLKSRC_APBD128))
+
+typedef struct
+{
+ uint32_t Channel;
+ uint32_t Period;
+ uint32_t OutMode;
+} PWM_OCInitType;
+typedef struct
+{
+ uint32_t Channel;
+ uint32_t CaptureMode;
+} PWM_ICInitType;
+//Channel
+#define PWM_CHANNEL_0 (0UL)
+#define PWM_CHANNEL_1 (1UL)
+#define PWM_CHANNEL_2 (2UL)
+#define IS_PWM_CHANNEL(__CHANNEL__) (((__CHANNEL__) == PWM_CHANNEL_0) ||\
+ ((__CHANNEL__) == PWM_CHANNEL_1) ||\
+ ((__CHANNEL__) == PWM_CHANNEL_2))
+//OutMode
+#define PWM_OUTMOD_CONST (0x0U << PWM_CCTL_OUTMOD_Pos)
+#define PWM_OUTMOD_SET (0x1U << PWM_CCTL_OUTMOD_Pos)
+#define PWM_OUTMOD_TOGGLE_RESET (0x2U << PWM_CCTL_OUTMOD_Pos)
+#define PWM_OUTMOD_SET_RESET (0x3U << PWM_CCTL_OUTMOD_Pos)
+#define PWM_OUTMOD_TOGGLE (0x4U << PWM_CCTL_OUTMOD_Pos)
+#define PWM_OUTMOD_RESET (0x5U << PWM_CCTL_OUTMOD_Pos)
+#define PWM_OUTMOD_TOGGLE_SET (0x6U << PWM_CCTL_OUTMOD_Pos)
+#define PWM_OUTMOD_RESET_SET (0x7U << PWM_CCTL_OUTMOD_Pos)
+#define IS_PWM_OUTMODE(__OUTMODE__) (((__OUTMODE__) == PWM_OUTMOD_CONST) ||\
+ ((__OUTMODE__) == PWM_OUTMOD_SET) ||\
+ ((__OUTMODE__) == PWM_OUTMOD_TOGGLE_RESET) ||\
+ ((__OUTMODE__) == PWM_OUTMOD_SET_RESET) ||\
+ ((__OUTMODE__) == PWM_OUTMOD_TOGGLE) ||\
+ ((__OUTMODE__) == PWM_OUTMOD_RESET) ||\
+ ((__OUTMODE__) == PWM_OUTMOD_TOGGLE_SET) ||\
+ ((__OUTMODE__) == PWM_OUTMOD_RESET_SET))
+
+//CaptureMode
+#define PWM_CM_DISABLE (0x0U << PWM_CCTL_CM_Pos)
+#define PWM_CM_RISING (0x1U << PWM_CCTL_CM_Pos)
+#define PWM_CM_FALLING (0x2U << PWM_CCTL_CM_Pos)
+#define PWM_CM_BOTH (0x3U << PWM_CCTL_CM_Pos)
+#define IS_PWM_CAPMODE(__CAPMODE__) (((__CAPMODE__) == PWM_CM_DISABLE) ||\
+ ((__CAPMODE__) == PWM_CM_RISING) ||\
+ ((__CAPMODE__) == PWM_CM_FALLING) ||\
+ ((__CAPMODE__) == PWM_CM_BOTH))
+
+//Interrupt
+#define PWM_INT_CCIFG PWM_CCTL_CCIFG
+#define PWM_INT_COV PWM_CCTL_COV
+#define PWM_INT_Msk (PWM_INT_CCIFG | PWM_INT_COV)
+#define IS_PWM_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == PWM_INT_CCIFG) ||\
+ ((__INTFLAGR__) == PWM_INT_COV))
+#define IS_PWM_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & PWM_INT_Msk) != 0U) &&\
+ (((__INTFLAGC__) & ~PWM_INT_Msk) == 0U))
+
+//PWM output selection
+#define PWM0_OUT0 0
+#define PWM0_OUT1 1
+#define PWM0_OUT2 2
+#define PWM1_OUT0 4
+#define PWM1_OUT1 5
+#define PWM1_OUT2 6
+#define PWM2_OUT0 8
+#define PWM2_OUT1 9
+#define PWM2_OUT2 10
+#define PWM3_OUT0 12
+#define PWM3_OUT1 13
+#define PWM3_OUT2 14
+#define IS_PWM_OUTSEL(__OUTSEL__) (((__OUTSEL__) == PWM0_OUT0) ||\
+ ((__OUTSEL__) == PWM0_OUT1) ||\
+ ((__OUTSEL__) == PWM0_OUT2) ||\
+ ((__OUTSEL__) == PWM1_OUT0) ||\
+ ((__OUTSEL__) == PWM1_OUT1) ||\
+ ((__OUTSEL__) == PWM1_OUT2) ||\
+ ((__OUTSEL__) == PWM2_OUT0) ||\
+ ((__OUTSEL__) == PWM2_OUT1) ||\
+ ((__OUTSEL__) == PWM2_OUT2) ||\
+ ((__OUTSEL__) == PWM3_OUT0) ||\
+ ((__OUTSEL__) == PWM3_OUT1) ||\
+ ((__OUTSEL__) == PWM3_OUT2))
+
+//outline
+#define PWM_OLINE_0 1
+#define PWM_OLINE_1 2
+#define PWM_OLINE_2 4
+#define PWM_OLINE_3 8
+#define PWM_OLINE_Msk 0xF
+#define IS_PWM_OUTLINE(__OUTLINE__) ((((__OUTLINE__) & PWM_OLINE_Msk) != 0U) &&\
+ (((__OUTLINE__) & ~PWM_OLINE_Msk) == 0U))
+
+//inline
+#define PWM_ILINE_0 0
+#define PWM_ILINE_1 1
+#define PWM_ILINE_2 2
+#define PWM_ILINE_3 3
+#define IS_PWM_INLINE(__INLINE__) (((__INLINE__) == PWM_ILINE_0) ||\
+ ((__INLINE__) == PWM_ILINE_1) ||\
+ ((__INLINE__) == PWM_ILINE_2) ||\
+ ((__INLINE__) == PWM_ILINE_3))
+
+//PWM input selection
+#define PWM1_IN2 0x014
+#define PWM1_IN1 0x012
+#define PWM1_IN0 0x010
+#define PWM0_IN2 0x004
+#define PWM0_IN1 0x002
+#define PWM0_IN0 0x000
+#define PWM3_IN2 0x114
+#define PWM3_IN1 0x112
+#define PWM3_IN0 0x110
+#define PWM2_IN2 0x104
+#define PWM2_IN1 0x102
+#define PWM2_IN0 0x100
+#define IS_PWM_INSEL(__INSEL__) (((__INSEL__) == PWM1_IN2) ||\
+ ((__INSEL__) == PWM1_IN1) ||\
+ ((__INSEL__) == PWM1_IN0) ||\
+ ((__INSEL__) == PWM0_IN2) ||\
+ ((__INSEL__) == PWM0_IN1) ||\
+ ((__INSEL__) == PWM0_IN0) ||\
+ ((__INSEL__) == PWM3_IN2) ||\
+ ((__INSEL__) == PWM3_IN1) ||\
+ ((__INSEL__) == PWM3_IN0) ||\
+ ((__INSEL__) == PWM2_IN2) ||\
+ ((__INSEL__) == PWM2_IN1) ||\
+ ((__INSEL__) == PWM2_IN0))
+
+//Level
+#define PWM_LEVEL_HIGH (0x1U << PWM_CCTL_OUT_Pos)
+#define PWM_LEVEL_LOW 0
+#define IS_PWM_OUTLVL(__OUTLVL__) (((__OUTLVL__) == PWM_LEVEL_HIGH) ||\
+ ((__OUTLVL__) == PWM_LEVEL_LOW))
+
+#define IS_PWM_CCR(__CCR__) ((__CCR__) < 0x10000U)
+
+
+/****************************** PWM Instances *********************************/
+#define IS_PWM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PWM0) || \
+ ((INSTANCE) == PWM1) || \
+ ((INSTANCE) == PWM2) || \
+ ((INSTANCE) == PWM3))
+
+#define IS_PWMMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PWMMUX)
+
+/* Exported Functions ------------------------------------------------------- */
+/* PWM Exported Functions Group1:
+ Initialization ----------------------------*/
+void PWM_BaseInit(PWM_Type *PWMx, PWM_BaseInitType *InitStruct);
+void PWM_BaseStructInit(PWM_BaseInitType *InitStruct);
+void PWM_OCStructInit(PWM_OCInitType *OCInitType);
+void PWM_OCInit(PWM_Type *PWMx, PWM_OCInitType *OCInitType);
+void PWM_ICStructInit(PWM_ICInitType *ICInitType);
+void PWM_ICInit(PWM_Type *PWMx, PWM_ICInitType *ICInitType);
+/* PWM Exported Functions Group2:
+ Interrupt ---------------------------------*/
+void PWM_BaseINTConfig(PWM_Type *PWMx, uint32_t NewState);
+uint8_t PWM_GetBaseINTStatus(PWM_Type *PWMx);
+void PWM_ClearBaseINTStatus(PWM_Type *PWMx);
+void PWM_ChannelINTConfig(PWM_Type *PWMx, uint32_t Channel, uint32_t NewState);
+uint8_t PWM_GetChannelINTStatus(PWM_Type *PWMx, uint32_t Channel, uint32_t IntMask);
+void PWM_ClearChannelINTStatus(PWM_Type *PWMx, uint32_t Channel, uint32_t IntMask);
+/* PWM Exported Functions Group3:
+ MISC --------------------------------------*/
+void PWM_ClearCounter(PWM_Type *PWMx);
+void PWM_CCRConfig(PWM_Type *PWMx, uint32_t Channel, uint16_t Period);
+//Compare output
+void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine);
+void PWM_OutputCmd(PWM_Type *PWMx, uint32_t Channel, uint32_t NewState);
+void PWM_SetOutLevel(PWM_Type *PWMx, uint32_t Channel, uint32_t Level);
+void PWM_ILineConfig(uint32_t InSelection, uint32_t ILine);
+uint8_t PWM_GetSCCI(PWM_Type *PWMx, uint32_t Channel);
+uint32_t PWM_GetCapture(PWM_Type *PWMx, uint32_t Channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_PWM_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_rtc.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_rtc.h
new file mode 100644
index 0000000000000000000000000000000000000000..74ad131b335829f1b4d2227bb6a58114ce2f5452
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_rtc.h
@@ -0,0 +1,229 @@
+/**
+ ******************************************************************************
+ * @file lib_rtc.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief RTC library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_RTC_H
+#define __LIB_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+/* RTC Time struct */
+typedef struct
+{
+ uint32_t Year;
+ uint32_t Month;
+ uint32_t Date;
+ uint32_t WeekDay;
+ uint32_t Hours;
+ uint32_t Minutes;
+ uint32_t Seconds;
+ uint32_t SubSeconds;
+} RTC_TimeTypeDef;
+
+/* RTC Alarm Time struct */
+typedef struct
+{
+ uint32_t AlarmHours;
+ uint32_t AlarmMinutes;
+ uint32_t AlarmSeconds;
+ uint32_t AlarmSubSeconds;
+}RTC_AlarmTypeDef;
+
+#define RTC_ACCURATE 0
+#define RTC_INACCURATE 1
+#define IS_RTC_ACCURATESEL(__ACCURATESEL__) (((__ACCURATESEL__) == RTC_ACCURATE) ||\
+ ((__ACCURATESEL__) == RTC_INACCURATE))
+
+/************** Bits definition for RTC_WKUCNT register ******************/
+#define RTC_WKUCNT_CNTSEL_0 (0x0U << RTC_WKUCNT_CNTSEL_Pos)
+#define RTC_WKUCNT_CNTSEL_1 (0x1U << RTC_WKUCNT_CNTSEL_Pos)
+#define RTC_WKUCNT_CNTSEL_2 (0x2U << RTC_WKUCNT_CNTSEL_Pos)
+#define RTC_WKUCNT_CNTSEL_3 (0x3U << RTC_WKUCNT_CNTSEL_Pos)
+
+/************** Bits definition for RTC_PSCA register ******************/
+#define RTC_PSCA_PSCA_0 (0x0U << RTC_PSCA_PSCA_Pos)
+#define RTC_PSCA_PSCA_1 (0x1U << RTC_PSCA_PSCA_Pos)
+//#define RTC_PSCA_PSCA_2 (0x2U << RTC_PSCA_PSCA_Pos)
+//#define RTC_PSCA_PSCA_3 (0x3U << RTC_PSCA_PSCA_Pos)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+//INT
+#define RTC_INT_ALARM RTC_INTSTS_INTSTS10
+#define RTC_INT_CEILLE RTC_INTSTS_INTSTS8
+#define RTC_INT_WKUCNT RTC_INTSTS_INTSTS6
+#define RTC_INT_MIDNIGHT RTC_INTSTS_INTSTS5
+#define RTC_INT_WKUHOUR RTC_INTSTS_INTSTS4
+#define RTC_INT_WKUMIN RTC_INTSTS_INTSTS3
+#define RTC_INT_WKUSEC RTC_INTSTS_INTSTS2
+#define RTC_INT_TIMEILLE RTC_INTSTS_INTSTS1
+#define RTC_INT_ITVSITV RTC_INTSTS_INTSTS0
+#define RTC_INT_Msk (0x57FUL)
+
+//INTSTS
+#define RTC_INTSTS_ALARM RTC_INTSTS_INTSTS10
+#define RTC_INTSTS_CEILLE RTC_INTSTS_INTSTS8
+#define RTC_INTSTS_WKUCNT RTC_INTSTS_INTSTS6
+#define RTC_INTSTS_MIDNIGHT RTC_INTSTS_INTSTS5
+#define RTC_INTSTS_WKUHOUR RTC_INTSTS_INTSTS4
+#define RTC_INTSTS_WKUMIN RTC_INTSTS_INTSTS3
+#define RTC_INTSTS_WKUSEC RTC_INTSTS_INTSTS2
+#define RTC_INTSTS_TIMEILLE RTC_INTSTS_INTSTS1
+#define RTC_INTSTS_ITVSITV RTC_INTSTS_INTSTS0
+#define RTC_INTSTS_Msk (0x57FUL)
+
+//CNTCLK
+#define RTC_WKUCNT_RTCCLK RTC_WKUCNT_CNTSEL_0
+#define RTC_WKUCNT_2048 RTC_WKUCNT_CNTSEL_1
+#define RTC_WKUCNT_512 RTC_WKUCNT_CNTSEL_2
+#define RTC_WKUCNT_128 RTC_WKUCNT_CNTSEL_3
+
+//Prescaler
+#define RTC_CLKDIV_1 RTC_PSCA_PSCA_0
+#define RTC_CLKDIV_4 RTC_PSCA_PSCA_1
+
+//PLLDIVSOUCE
+#define RTC_PLLDIVSOURCE_PCLK 0
+#define RTC_PLLDIVSOURCE_PLLL (0x1U << RTC_CTL_RTCPLLCLKSEL_Pos)
+
+//RTC_ITV
+#define RTC_ITV_SEC (0x80)
+#define RTC_ITV_MIN (1 << RTC_ITV_ITV_Pos)
+#define RTC_ITV_HOUR (2 << RTC_ITV_ITV_Pos)
+#define RTC_ITV_DAY (3 << RTC_ITV_ITV_Pos)
+#define RTC_ITV_500MS (4 << RTC_ITV_ITV_Pos)
+#define RTC_ITV_250MS (5 << RTC_ITV_ITV_Pos)
+#define RTC_ITV_125MS (6 << RTC_ITV_ITV_Pos)
+#define RTC_ITV_62MS (7 << RTC_ITV_ITV_Pos)
+#define RTC_ITV_SITVSEC (7 << RTC_ITV_ITV_Pos)
+//RTC_SITV
+#define RTC_SITV_EN (1 << RTC_SITV_SITVEN_Pos) //Control Multi Second interval.1:enable; 0:disable.
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_RTC_REGOP_STARTADDR(__STARTADDR__) (((__STARTADDR__) & 0x3U) == 0U)
+/* Year 0 ~ 99 */
+#define IS_RTC_TIME_YEAR(__YEAR__) ((__YEAR__) < 0x9AU)
+/* Month 1 ~ 12 */
+#define IS_RTC_TIME_MONTH(__MONTH__) (((__MONTH__) > 0x0U) && ((__MONTH__) < 0x13U))
+/* Date 1 ~ 31 */
+#define IS_RTC_TIME_DATE(__DATE__) (((__DATE__) > 0x0U) && ((__DATE__) < 0x32U))
+/* Weekday 0 ~ 6 */
+#define IS_RTC_TIME_WEEKDAY(__WEEKDAY__) ((__WEEKDAY__) < 0x7U)
+/* Hours 0 ~ 23 */
+#define IS_RTC_TIME_HOURS(__HOURS__) ((__HOURS__) < 0x24U)
+/* Minutes 0 ~ 59 */
+#define IS_RTC_TIME_MINS(__MINS__) ((__MINS__) < 0x5AU)
+/* Seconds 0 ~ 59 */
+#define IS_RTC_TIME_SECS(__SECS__) ((__SECS__) < 0x5AU)
+/* SubSeconds 0 ~ 0x999 */
+#define IS_RTC_TIME_SubSECS(__SubSECS__) ((__SubSECS__) < 0x1000U)
+
+/* Alarm time 0 ~ 0x999 */
+#define IS_RTC_ALARMTIME(__ALARMTIME__) ((__ALARMTIME__) < 0x1E0000U)
+
+#define IS_RTC_INT(__INT__) ((((__INT__) & RTC_INT_Msk) != 0U) &&\
+ (((__INT__) & ~RTC_INT_Msk) == 0U))
+
+#define IS_RTC_INTFLAGR(__INTFLAGR_) (((__INTFLAGR_) == RTC_INTSTS_CEILLE) ||\
+ ((__INTFLAGR_) == RTC_INTSTS_WKUCNT) ||\
+ ((__INTFLAGR_) == RTC_INTSTS_MIDNIGHT) ||\
+ ((__INTFLAGR_) == RTC_INTSTS_WKUHOUR) ||\
+ ((__INTFLAGR_) == RTC_INTSTS_WKUMIN) ||\
+ ((__INTFLAGR_) == RTC_INTSTS_WKUSEC) ||\
+ ((__INTFLAGR_) == RTC_INTSTS_ALARM) ||\
+ ((__INTFLAGR_) == RTC_INTSTS_TIMEILLE) ||\
+ ((__INTFLAGR_) == RTC_INTSTS_ITVSITV))
+
+#define IS_RTC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & RTC_INTSTS_Msk) != 0U) &&\
+ (((__INTFLAGC__) & ~RTC_INTSTS_Msk) == 0U))
+
+#define IS_RTC_WKUSEC_PERIOD(__PERIOD__) ((__PERIOD__) < 0x41U)
+
+#define IS_RTC_WKUMIN_PERIOD(__PERIOD__) ((__PERIOD__) < 0x41U)
+
+#define IS_RTC_WKUHOUR_PERIOD(__PERIOD__) ((__PERIOD__) < 0x21U)
+
+#define IS_RTC_WKUCNT_PERIOD(__PERIOD__) ((__PERIOD__) < 0x1000001U)
+
+#define IS_RTC_WKUCNT_CNTSEL(__CNTSEL__) (((__CNTSEL__) == RTC_WKUCNT_RTCCLK) ||\
+ ((__CNTSEL__) == RTC_WKUCNT_2048) ||\
+ ((__CNTSEL__) == RTC_WKUCNT_512) ||\
+ ((__CNTSEL__) == RTC_WKUCNT_128))
+
+#define IS_RTC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == RTC_CLKDIV_1) ||\
+ ((__CLKDIV__) == RTC_CLKDIV_4))
+
+#define IS_RTC_PLLDIVSOURCE(__PLLDIVSOURCE__) (((__PLLDIVSOURCE__) == RTC_PLLDIVSOURCE_PCLK) ||\
+ ((__PLLDIVSOURCE__) == RTC_PLLDIVSOURCE_PLLL))
+
+#define IS_RTC_ITV(__ITV__) (((__ITV__) == RTC_ITV_SEC) ||\
+ ((__ITV__) == RTC_ITV_MIN) ||\
+ ((__ITV__) == RTC_ITV_HOUR) ||\
+ ((__ITV__) == RTC_ITV_DAY) ||\
+ ((__ITV__) == RTC_ITV_500MS) ||\
+ ((__ITV__) == RTC_ITV_250MS) ||\
+ ((__ITV__) == RTC_ITV_125MS) ||\
+ ((__ITV__) == RTC_ITV_62MS) ||\
+ ((__ITV__) == RTC_ITV_SITVSEC))
+
+#define IS_RTC_SITV(__SITV__) ((__SITV__) < 64U)
+
+/* Exported Functions ------------------------------------------------------- */
+/* RTC Exported Functions Group1:
+ Time functions -----------------------------*/
+void RTC_SetTime(RTC_TimeTypeDef *sTime, uint32_t AccurateSel);
+void RTC_GetTime(RTC_TimeTypeDef *gTime, uint32_t AccurateSel);
+void RTC_SubSecondCmd(uint32_t NewState);
+/* RTC Exported Functions Group2:
+ Alarms configuration functions -------------*/
+void RTC_SetAlarm(RTC_AlarmTypeDef *RTC_AlarmStruct, uint32_t AccurateSel);
+void RTC_GetAlarm(RTC_AlarmTypeDef *RTC_AlarmStruct, uint32_t AccurateSel);
+void RTC_AlarmCmd(uint32_t NewState);
+void RTC_AlarmAccurateCmd(uint32_t NewState);
+/* RTC Exported Functions Group3:
+ Registers operation functions --------------*/
+void RTC_WriteProtection(uint32_t NewState);
+void RTC_WaitForSynchro(void);
+void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len);
+void RTC_ReadRegisters(uint32_t StartAddr, uint32_t *rBuffer, uint8_t Len);
+/* RTC Exported Functions Group4:
+ Interrupt functions ------------------------*/
+void RTC_INTConfig(uint32_t INTMask, uint32_t NewState);
+uint8_t RTC_GetINTStatus(uint32_t FlagMask);
+void RTC_ClearINTStatus(uint32_t FlagMask);
+
+/* RTC Exported Functions Group5:
+ Wake-up functions --------------------------*/
+void RTC_WKUSecondsConfig(uint8_t nPeriod);
+void RTC_WKUMinutesConfig(uint8_t nPeriod);
+void RTC_WKUHoursConfig(uint8_t nPeriod);
+void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK);
+void RTC_WAKE_ITV(uint8_t nType);
+void RTC_WAKE_SITV(uint8_t nPeriod);
+uint32_t RTC_GetWKUCounterValue(void);
+/* RTC Exported Functions Group6:
+ MISC functions -----------------------------*/
+void RTC_PrescalerConfig(uint32_t Prescaler);
+void RTC_PLLDIVConfig(uint32_t DIVSource,uint32_t nfrequency);
+void RTC_PLLDIVOutputCmd(uint8_t NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_RTC_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_spi.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_spi.h
new file mode 100644
index 0000000000000000000000000000000000000000..59681ad12c643bcc73ed168517a665620204e744
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_spi.h
@@ -0,0 +1,212 @@
+/**
+ ******************************************************************************
+ * @file lib_spi.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief SPI library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_SPI_H
+#define __LIB_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+ uint32_t Mode;
+ uint32_t SPH;
+ uint32_t SPO;
+ uint32_t ClockDivision;
+ uint32_t CSNSoft;
+ uint32_t SWAP;
+} SPI_InitType;
+
+/************** Bits definition for SPIx_CTRL register ******************/
+#define SPI_CTRL_SCKSEL_0 (0x1U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000001 */
+#define SPI_CTRL_SCKSEL_1 (0x2U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000002 */
+#define SPI_CTRL_SCKSEL_2 (0x4U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000004 */
+
+/************** Bits definition for SPIx_TXSTS register ******************/
+#define SPI_TXSTS_TXFFLAG_0 (0x1U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000001 */
+#define SPI_TXSTS_TXFFLAG_1 (0x2U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000002 */
+#define SPI_TXSTS_TXFFLAG_2 (0x4U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000004 */
+#define SPI_TXSTS_TXFFLAG_3 (0x8U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000008 */
+#define SPI_TXSTS_TXFLEV_0 (0x1U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000010 */
+#define SPI_TXSTS_TXFLEV_1 (0x2U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000020 */
+#define SPI_TXSTS_TXFLEV_2 (0x4U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000040 */
+
+/************** Bits definition for SPIx_TXDAT register ******************/
+
+/************** Bits definition for SPIx_RXSTS register ******************/
+#define SPI_RXSTS_RXFFLAG_0 (0x1U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000001 */
+#define SPI_RXSTS_RXFFLAG_1 (0x2U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000002 */
+#define SPI_RXSTS_RXFFLAG_2 (0x4U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000004 */
+#define SPI_RXSTS_RXFFLAG_3 (0x8U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000008 */
+#define SPI_RXSTS_RXFLEV_0 (0x1U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000010 */
+#define SPI_RXSTS_RXFLEV_1 (0x2U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000020 */
+#define SPI_RXSTS_RXFLEV_2 (0x4U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000040 */
+//Mode
+#define SPI_MODE_MASTER 0
+#define SPI_MODE_SLAVE SPI_CTRL_MOD
+//SPH
+#define SPI_SPH_0 0
+#define SPI_SPH_1 SPI_CTRL_SCKPHA
+//SPO
+#define SPI_SPO_0 0
+#define SPI_SPO_1 SPI_CTRL_SCKPOL
+//ClockDivision
+#define SPI_CLKDIV_2 (0)
+#define SPI_CLKDIV_4 (SPI_CTRL_SCKSEL_0)
+#define SPI_CLKDIV_8 (SPI_CTRL_SCKSEL_1)
+#define SPI_CLKDIV_16 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_1)
+#define SPI_CLKDIV_32 (SPI_CTRL_SCKSEL_2)
+#define SPI_CLKDIV_64 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_2)
+#define SPI_CLKDIV_128 (SPI_CTRL_SCKSEL_1 | SPI_CTRL_SCKSEL_2)
+//CSNSoft
+#define SPI_CSNSOFT_ENABLE SPI_CTRL_CSGPIO
+#define SPI_CSNSOFT_DISABLE 0
+//SWAP
+#define SPI_SWAP_ENABLE SPI_CTRL_SWAP
+#define SPI_SWAP_DISABLE 0
+
+//INT
+#define SPI_INT_TX (0x80000000|SPI_TXSTS_TXIEN)
+#define SPI_INT_RX (0x40000000|SPI_RXSTS_RXIEN)
+
+//status
+#define SPI_STS_TXIF (0x80000000|SPI_TXSTS_TXIF)
+#define SPI_STS_TXEMPTY (0x80000000|SPI_TXSTS_TXEMPTY)
+#define SPI_STS_TXFUR (0x80000000|SPI_TXSTS_TXFUR)
+#define SPI_STS_DMATXDONE (0x80000000|SPI_TXSTS_DMATXDONE)
+#define SPI_STS_RXIF (0x40000000|SPI_RXSTS_RXIF)
+#define SPI_STS_RXFULL (0x40000000|SPI_RXSTS_RXFULL)
+#define SPI_STS_RXFOV (0x40000000|SPI_RXSTS_RXFOV)
+#define SPI_STS_BSY (0x20000000|SPI_MISC_BSY)
+#define SPI_STS_RFF (0x20000000|SPI_MISC_RFF)
+#define SPI_STS_RNE (0x20000000|SPI_MISC_RNE)
+#define SPI_STS_TNF (0x20000000|SPI_MISC_TNF)
+#define SPI_STS_TFE (0x20000000|SPI_MISC_TFE)
+
+//TXFLEV
+#define SPI_TXFLEV_0 (0)
+#define SPI_TXFLEV_1 (SPI_TXSTS_TXFLEV_0)
+#define SPI_TXFLEV_2 (SPI_TXSTS_TXFLEV_1)
+#define SPI_TXFLEV_3 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1)
+#define SPI_TXFLEV_4 (SPI_TXSTS_TXFLEV_2)
+#define SPI_TXFLEV_5 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_2)
+#define SPI_TXFLEV_6 (SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2)
+#define SPI_TXFLEV_7 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2)
+
+//RXFLEV
+#define SPI_RXFLEV_0 (0)
+#define SPI_RXFLEV_1 (SPI_RXSTS_RXFLEV_0)
+#define SPI_RXFLEV_2 (SPI_RXSTS_RXFLEV_1)
+#define SPI_RXFLEV_3 (SPI_RXSTS_RXFLEV_0 | SPI_RXSTS_RXFLEV_1)
+#define SPI_RXFLEV_4 (SPI_RXSTS_RXFLEV_2)
+#define SPI_RXFLEV_5 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_0)
+#define SPI_RXFLEV_6 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1)
+#define SPI_RXFLEV_7 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1 | SPI_RXSTS_RXFLEV_0)
+
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_MASTER) || ((__MODE__) == SPI_MODE_SLAVE))
+
+#define IS_SPI_SPH(__SPH__) (((__SPH__) == SPI_SPH_0) || ((__SPH__) == SPI_SPH_1))
+
+#define IS_SPI_SPO(__SPO__) (((__SPO__) == SPI_SPO_0) || ((__SPO__) == SPI_SPO_1))
+
+#define IS_SPI_CLKDIV(__CLKDIV__) (((__CLKDIV__) == SPI_CLKDIV_2) ||\
+ ((__CLKDIV__) == SPI_CLKDIV_4) ||\
+ ((__CLKDIV__) == SPI_CLKDIV_8) ||\
+ ((__CLKDIV__) == SPI_CLKDIV_16) ||\
+ ((__CLKDIV__) == SPI_CLKDIV_32) ||\
+ ((__CLKDIV__) == SPI_CLKDIV_64) ||\
+ ((__CLKDIV__) == SPI_CLKDIV_128))
+
+#define IS_SPI_CSN(__CSN__) (((__CSN__) == SPI_CSNSOFT_ENABLE) || ((__CSN__) == SPI_CSNSOFT_DISABLE))
+
+#define IS_SPI_SWAP(__SWAP__) (((__SWAP__) == SPI_SWAP_ENABLE) || ((__SWAP__) == SPI_SWAP_DISABLE))
+
+#define IS_SPI_INT(__INT__) ((((__INT__) & (SPI_INT_TX | SPI_INT_RX)) != 0U) &&\
+ (((__INT__) & ~(SPI_INT_TX | SPI_INT_RX)) == 0U))
+
+#define IS_SPI_STSR(__STSR__) (((__STSR__) == SPI_STS_TXIF) ||\
+ ((__STSR__) == SPI_STS_TXEMPTY) ||\
+ ((__STSR__) == SPI_STS_TXFUR) ||\
+ ((__STSR__) == SPI_STS_DMATXDONE) ||\
+ ((__STSR__) == SPI_STS_RXFULL) ||\
+ ((__STSR__) == SPI_STS_RXFOV) ||\
+ ((__STSR__) == SPI_STS_BSY) ||\
+ ((__STSR__) == SPI_STS_RFF) ||\
+ ((__STSR__) == SPI_STS_RNE) ||\
+ ((__STSR__) == SPI_STS_TNF) ||\
+ ((__STSR__) == SPI_STS_TFE) ||\
+ ((__STSR__) == SPI_STS_RXIF))
+
+#define IS_SPI_STSC(__STSC__) ((((__STSC__) & (SPI_STS_TXIF | SPI_STS_RXIF | SPI_STS_DMATXDONE)) != 0U) &&\
+ (((__STSC__) & ~(SPI_STS_TXIF | SPI_STS_RXIF | SPI_STS_DMATXDONE)) == 0U))
+
+#define IS_SPI_TXFLEV(__TXFLEV__) (((__TXFLEV__) == SPI_TXFLEV_0) ||\
+ ((__TXFLEV__) == SPI_TXFLEV_1) ||\
+ ((__TXFLEV__) == SPI_TXFLEV_2) ||\
+ ((__TXFLEV__) == SPI_TXFLEV_3) ||\
+ ((__TXFLEV__) == SPI_TXFLEV_4) ||\
+ ((__TXFLEV__) == SPI_TXFLEV_5) ||\
+ ((__TXFLEV__) == SPI_TXFLEV_6) ||\
+ ((__TXFLEV__) == SPI_TXFLEV_7))
+
+#define IS_SPI_RXFLEV(__RXFLEV__) (((__RXFLEV__) == SPI_RXFLEV_0) ||\
+ ((__RXFLEV__) == SPI_RXFLEV_1) ||\
+ ((__RXFLEV__) == SPI_RXFLEV_2) ||\
+ ((__RXFLEV__) == SPI_RXFLEV_3) ||\
+ ((__RXFLEV__) == SPI_RXFLEV_4) ||\
+ ((__RXFLEV__) == SPI_RXFLEV_5) ||\
+ ((__RXFLEV__) == SPI_RXFLEV_6) ||\
+ ((__RXFLEV__) == SPI_RXFLEV_7))
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/* Exported Functions ------------------------------------------------------- */
+/* SPI Exported Functions Group1:
+ (De)Initialization -------------------------*/
+void SPI_DeviceInit(SPI_Type *SPIx);
+void SPI_Init(SPI_Type *SPIx, SPI_InitType *InitStruct);
+void SPI_StructInit(SPI_InitType *InitStruct);
+/* SPI Exported Functions Group2:
+ Interrupt (flag) ---------------------------*/
+void SPI_INTConfig(SPI_Type *SPIx, uint32_t INTMask, uint32_t NewState);
+uint8_t SPI_GetStatus(SPI_Type *SPIx, uint32_t Status);
+void SPI_ClearStatus(SPI_Type *SPIx, uint32_t Status);
+/* SPI Exported Functions Group3:
+ Transfer datas -----------------------------*/
+void SPI_SendData(SPI_Type *SPIx, uint8_t ch);
+uint8_t SPI_ReceiveData(SPI_Type *SPIx);
+/* SPI Exported Functions Group4:
+ MISC Configuration -------------------------*/
+void SPI_Cmd(SPI_Type *SPIx, uint32_t NewState);
+void SPI_TransmitFIFOLevelConfig(SPI_Type *SPIx, uint32_t FIFOLevel);
+void SPI_ReceiveFIFOLevelConfig(SPI_Type *SPIx, uint32_t FIFOLevel);
+uint8_t SPI_GetTransmitFIFOLevel(SPI_Type *SPIx);
+uint8_t SPI_GetReceiveFIFOLevel(SPI_Type *SPIx);
+void SPI_SmartModeCmd(SPI_Type *SPIx, uint32_t NewState);
+void SPI_OverWriteModeCmd(SPI_Type *SPIx, uint32_t NewState);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_SPI_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_tmr.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_tmr.h
new file mode 100644
index 0000000000000000000000000000000000000000..9a5a2969e98d28892856cee629f8f535d71fc454
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_tmr.h
@@ -0,0 +1,68 @@
+/**
+ ******************************************************************************
+ * @file lib_tmr.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Timer library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_TMR_H
+#define __LIB_TMR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+ uint32_t Period;
+ uint32_t ClockSource;
+ uint32_t EXTGT;
+} TMR_InitType;
+//ClockSource
+#define TMR_CLKSRC_INTERNAL 0
+#define TMR_CLKSRC_EXTERNAL TMR_CTRL_EXTCLK
+//ClockGate
+#define TMR_EXTGT_DISABLE 0
+#define TMR_EXTGT_ENABLE TMR_CTRL_EXTEN
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_TMR_CLKSRC(__CLKSRC__) (((__CLKSRC__) == TMR_CLKSRC_INTERNAL) || ((__CLKSRC__) == TMR_CLKSRC_EXTERNAL))
+
+#define IS_TMR_EXTGT(__EXTGT__) (((__EXTGT__) == TMR_EXTGT_DISABLE) || ((__EXTGT__) == TMR_EXTGT_ENABLE))
+
+/****************************** TMR Instances *********************************/
+#define IS_TMR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TMR0) || \
+ ((INSTANCE) == TMR1) || \
+ ((INSTANCE) == TMR2) || \
+ ((INSTANCE) == TMR3))
+
+/* Exported Functions ------------------------------------------------------- */
+/* Timer Exported Functions Group1:
+ (De)Initialization ----------------------*/
+void TMR_DeInit(TMR_Type *TMRx);
+void TMR_Init(TMR_Type *TMRx, TMR_InitType *InitStruct);
+void TMR_StructInit(TMR_InitType *InitStruct);
+/* Timer Exported Functions Group2:
+ Interrupt (flag) -------------------------*/
+void TMR_INTConfig(TMR_Type *TMRx, uint32_t NewState);
+uint8_t TMR_GetINTStatus(TMR_Type *TMRx);
+void TMR_ClearINTStatus(TMR_Type *TMRx);
+/* Timer Exported Functions Group3:
+ MISC Configuration -----------------------*/
+void TMR_Cmd(TMR_Type *TMRx, uint32_t NewState);
+uint32_t TMR_GetCurrentValue(TMR_Type *TMRx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_TMR_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_u32k.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_u32k.h
new file mode 100644
index 0000000000000000000000000000000000000000..546d390a861dcde4f37b169ad182dec12c1d471f
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_u32k.h
@@ -0,0 +1,160 @@
+/**
+ ******************************************************************************
+ * @file lib_u32k.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief UART 32K library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_U32K_H
+#define __LIB_U32K_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+ uint32_t Debsel;
+ uint32_t Parity;
+ uint32_t FirstBit;
+ uint32_t AutoCal;
+ uint32_t Baudrate;
+ uint32_t LineSel;
+} U32K_InitType;
+
+/************** Bits definition for U32Kx_CTRL0 register ******************/
+#define U32K_CTRL0_PMODE_EVEN (0x0U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000000 */
+#define U32K_CTRL0_PMODE_ODD (0x1U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000010 */
+#define U32K_CTRL0_PMODE_0 (0x2U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000020 */
+#define U32K_CTRL0_PMODE_1 (0x3U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000030 */
+#define U32K_CTRL0_DEBSEL_0 (0x0U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000000 */
+#define U32K_CTRL0_DEBSEL_1 (0x1U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000040 */
+#define U32K_CTRL0_DEBSEL_2 (0x2U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000080 */
+#define U32K_CTRL0_DEBSEL_3 (0x3U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x000000C0 */
+
+/************** Bits definition for U32Kx_CTRL1 register ******************/
+#define U32K_CTRL1_RXSEL_RX0 (0x0U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000000 */
+#define U32K_CTRL1_RXSEL_RX1 (0x1U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000010 */
+#define U32K_CTRL1_RXSEL_RX2 (0x2U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000020 */
+#define U32K_CTRL1_RXSEL_RX3 (0x3U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000030 */
+//Debsel
+#define U32K_DEBSEL_0 (0x0U << U32K_CTRL0_DEBSEL_Pos)
+#define U32K_DEBSEL_1 (0x1U << U32K_CTRL0_DEBSEL_Pos)
+#define U32K_DEBSEL_2 (0x2U << U32K_CTRL0_DEBSEL_Pos)
+#define U32K_DEBSEL_3 (0x3U << U32K_CTRL0_DEBSEL_Pos)
+//Parity
+#define U32K_PARITY_EVEN (0x1U << U32K_CTRL0_PMODE_Pos)
+#define U32K_PARITY_ODD (0x3U << U32K_CTRL0_PMODE_Pos)
+#define U32K_PARITY_0 (0x5U << U32K_CTRL0_PMODE_Pos)
+#define U32K_PARITY_1 (0x7U << U32K_CTRL0_PMODE_Pos)
+#define U32K_PARITY_NONE (0x0U << U32K_CTRL0_PMODE_Pos)
+//FirstBit
+#define U32K_FIRSTBIT_LSB 0
+#define U32K_FIRSTBIT_MSB (0x1U << U32K_CTRL0_MSB_Pos)
+//AutoCal
+#define U32K_AUTOCAL_ON 0
+#define U32K_AUTOCAL_OFF (0x1U << U32K_CTRL0_ACOFF_Pos)
+//Line
+#define U32K_LINE_RX0 (0x0U << U32K_CTRL1_RXSEL_Pos)
+#define U32K_LINE_RX1 (0x1U << U32K_CTRL1_RXSEL_Pos)
+#define U32K_LINE_RX2 (0x2U << U32K_CTRL1_RXSEL_Pos)
+#define U32K_LINE_RX3 (0x3U << U32K_CTRL1_RXSEL_Pos)
+
+//INT
+#define U32K_INT_RXOV (0x1U << U32K_CTRL1_RXOVIE_Pos)
+#define U32K_INT_RXPE (0x1U << U32K_CTRL1_RXPEIE_Pos)
+#define U32K_INT_RX (0x1U << U32K_CTRL1_RXIE_Pos)
+#define U32K_INT_Msk (U32K_INT_RXOV \
+ |U32K_INT_RXPE \
+ |U32K_INT_RX)
+
+//INT Status
+#define U32K_INTSTS_RXOV (0x1U << U32K_STS_RXOV_Pos)
+#define U32K_INTSTS_RXPE (0x1U << U32K_STS_RXPE_Pos)
+#define U32K_INTSTS_RX (0x1U << U32K_STS_RXIF_Pos)
+#define U32K_INTSTS_Msk (U32K_INTSTS_RXOV \
+ |U32K_INTSTS_RXPE \
+ |U32K_INTSTS_RX)
+
+//WKUMode
+#define U32K_WKUMOD_RX 0 // Wake-up when receive data
+#define U32K_WKUMOD_PC (0x1U << U32K_CTRL0_WKUMODE_Pos) // Wake-up when receive data and parity/stop bit correct
+
+
+/****************************** U32K Instances ********************************/
+#define IS_U32K_ALL_INSTANCE(INSTANCE) (((INSTANCE) == U32K0) || \
+ ((INSTANCE) == U32K1))
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_U32K_DEBSEL(__DEBSEL__) (((__DEBSEL__) == U32K_DEBSEL_0) ||\
+ ((__DEBSEL__) == U32K_DEBSEL_1) ||\
+ ((__DEBSEL__) == U32K_DEBSEL_2) ||\
+ ((__DEBSEL__) == U32K_DEBSEL_3))
+
+#define IS_U32K_PARITY(__PARITY__) (((__PARITY__) == U32K_PARITY_EVEN) ||\
+ ((__PARITY__) == U32K_PARITY_ODD) ||\
+ ((__PARITY__) == U32K_PARITY_0) ||\
+ ((__PARITY__) == U32K_PARITY_1) ||\
+ ((__PARITY__) == U32K_PARITY_NONE))
+
+#define IS_U32K_WORDLEN(__WORDLEN__) (((__WORDLEN__) == U32K_WORDLEN_8B) || ((__WORDLEN__) == U32K_WORDLEN_9B))
+
+#define IS_U32K_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == U32K_FIRSTBIT_LSB) || ((__FIRSTBIT__) == U32K_FIRSTBIT_MSB))
+
+#define IS_U32K_AUTOCAL(__AUTOCAL__) (((__AUTOCAL__) == U32K_AUTOCAL_ON) || ((__AUTOCAL__) == U32K_AUTOCAL_OFF))
+
+#define IS_U32K_LINE(__LINE__) (((__LINE__) == U32K_LINE_RX0) ||\
+ ((__LINE__) == U32K_LINE_RX1) ||\
+ ((__LINE__) == U32K_LINE_RX2) ||\
+ ((__LINE__) == U32K_LINE_RX3))
+
+#define IS_U32K_BAUDRATE(__BAUDRATE__) ((300UL <= (__BAUDRATE__)) &&\
+ ((__BAUDRATE__) <= 14400UL))
+
+#define IS_U32K_INT(__INT__) ((((__INT__) & U32K_INT_Msk) != 0U) &&\
+ (((__INT__) & ~U32K_INT_Msk) == 0U))
+
+#define IS_U32K_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == U32K_INTSTS_RXOV) ||\
+ ((__INTFLAGR__) == U32K_INTSTS_RXPE) ||\
+ ((__INTFLAGR__) == U32K_INTSTS_RX))
+
+#define IS_U32K_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & U32K_INTSTS_Msk) != 0U) &&\
+ (((__INTFLAGC__) & ~U32K_INTSTS_Msk) == 0U))
+
+#define IS_U32K_WKUMODE(__WKUMODE__) (((__WKUMODE__) == U32K_WKUMOD_RX) || ((__WKUMODE__) == U32K_WKUMOD_PC))
+
+/* Exported Functions ------------------------------------------------------- */
+/* U32K Exported Functions Group1:
+ (De)Initialization -----------------------*/
+void U32K_DeInit(U32K_Type *U32Kx);
+void U32K_Init(U32K_Type *U32Kx, U32K_InitType *InitStruct);
+void U32K_StructInit(U32K_InitType *InitStruct);
+/* U32K Exported Functions Group2:
+ Interrupt (flag) configure ---------------*/
+void U32K_INTConfig(U32K_Type *U32Kx, uint32_t INTMask, uint8_t NewState);
+uint8_t U32K_GetINTStatus(U32K_Type *U32Kx, uint32_t INTMask);
+void U32K_ClearINTStatus(U32K_Type *U32Kx, uint32_t INTMask);
+/* U32K Exported Functions Group3:
+ Receive datas -----------------------------*/
+uint8_t U32K_ReceiveData(U32K_Type *U32Kx);
+/* U32K Exported Functions Group4:
+ MISC Configuration -------- ---------------*/
+void U32K_BaudrateConfig(U32K_Type *U32Kx, uint32_t BaudRate);
+void U32K_Cmd(U32K_Type *U32Kx, uint32_t NewState);
+void U32K_LineConfig(U32K_Type *U32Kx, uint32_t Line);
+void U32K_WKUModeConfig(U32K_Type *U32Kx, uint32_t WKUMode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_U32K_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_uart.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_uart.h
new file mode 100644
index 0000000000000000000000000000000000000000..b91f85288939da388f2d6d4d373e9ffd1b9d957c
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_uart.h
@@ -0,0 +1,172 @@
+/**
+ ******************************************************************************
+ * @file lib_uart.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief UART library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_UART_H
+#define __LIB_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+//UART Init struct
+typedef struct
+{
+ uint32_t Mode;
+ uint32_t Parity;
+ uint32_t FirstBit;
+ uint32_t Baudrate;
+} UART_InitType;
+
+//Mode
+#define UART_MODE_RX (0x1U << UART_CTRL_RXEN_Pos)
+#define UART_MODE_TX (0x1U << UART_CTRL_TXEN_Pos)
+#define UART_MODE_OFF 0
+#define UART_MODE_Msk (UART_MODE_RX | UART_MODE_TX)
+//Parity
+#define UART_PARITY_EVEN (0x1U << UART_CTRL2_PMODE_Pos)
+#define UART_PARITY_ODD (0x3U << UART_CTRL2_PMODE_Pos)
+#define UART_PARITY_0 (0x5U << UART_CTRL2_PMODE_Pos)
+#define UART_PARITY_1 (0x7U << UART_CTRL2_PMODE_Pos)
+#define UART_PARITY_NONE (0x0U << UART_CTRL2_PMODE_Pos)
+
+//FirstBit
+#define UART_FIRSTBIT_LSB 0
+#define UART_FIRSTBIT_MSB (0x1U << UART_CTRL2_MSB_Pos)
+
+//UART Configration Information struct
+typedef struct
+{
+ uint32_t Mode_Transmit :1; //1: TX Enable; 0: TX Disable
+ uint32_t Mode_Receive :1; //1: RX Enable; 0: RX Disable
+ uint32_t Baudrate; //The value of current budrate
+ uint8_t Parity; //0:1+8+1 mode; 1: Even parity; 3:Odd parity; 5: parity bit=0; 7: parity bit=1;
+ uint8_t FirstBit; //0: LSB transmit first; 1: MSB transmit first
+} UART_ConfigINFOType;
+
+//status
+#define UART_FLAG_DMATXDONE (0x1U << UART_STATE_DMATXDONE_Pos)
+#define UART_FLAG_RXPARITY (0x1U << UART_STATE_RXPSTS_Pos)
+#define UART_FLAG_TXDONE (0x1U << UART_STATE_TXDONE_Pos)
+#define UART_FLAG_RXPE (0x1U << UART_STATE_RXPE_Pos)
+#define UART_FLAG_RXOV (0x1U << UART_STATE_RXOV_Pos)
+#define UART_FLAG_TXOV (0x1U << UART_STATE_TXOV_Pos)
+#define UART_FLAG_RXFULL (0x1U << UART_STATE_RXFULL_Pos)
+#define UART_FLAG_RCMsk (UART_FLAG_DMATXDONE \
+ |UART_FLAG_TXDONE \
+ |UART_FLAG_RXPE \
+ |UART_FLAG_RXOV \
+ |UART_FLAG_RXFULL \
+ |UART_FLAG_TXOV)
+
+//interrupt
+#define UART_INT_TXDONE (0x1U << UART_CTRL_TXDONEIE_Pos)
+#define UART_INT_RXPE (0x1U << UART_CTRL_RXPEIE_Pos)
+#define UART_INT_RXOV (0x1U << UART_CTRL_RXOVIE_Pos)
+#define UART_INT_TXOV (0x1U << UART_CTRL_TXOVIE_Pos)
+#define UART_INT_RX (0x1U << UART_CTRL_RXIE_Pos)
+#define UART_INT_Msk (UART_INT_TXDONE \
+ |UART_INT_RXPE \
+ |UART_INT_RXOV \
+ |UART_INT_TXOV \
+ |UART_INT_RX)
+
+//INTStatus
+#define UART_INTSTS_TXDONE (0x1U << UART_INTSTS_TXDONEIF_Pos)
+#define UART_INTSTS_RXPE (0x1U << UART_INTSTS_RXPEIF_Pos)
+#define UART_INTSTS_RXOV (0x1U << UART_INTSTS_RXOVIF_Pos)
+#define UART_INTSTS_TXOV (0x1U << UART_INTSTS_TXOVIF_Pos)
+#define UART_INTSTS_RX (0x1U << UART_INTSTS_RXIF_Pos)
+#define UART_INTSTS_Msk (UART_INTSTS_TXDONE \
+ |UART_INTSTS_RXPE \
+ |UART_INTSTS_RXOV \
+ |UART_INTSTS_TXOV \
+ |UART_INTSTS_RX)
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_UART_MODE(__MODE__) (((((__MODE__) & UART_MODE_Msk) != 0U) && (((__MODE__) & ~UART_MODE_Msk) == 0U)))
+
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_EVEN) ||\
+ ((__PARITY__) == UART_PARITY_ODD) ||\
+ ((__PARITY__) == UART_PARITY_0) ||\
+ ((__PARITY__) == UART_PARITY_1) ||\
+ ((__PARITY__) == UART_PARITY_NONE))
+
+#define IS_UART_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == UART_FIRSTBIT_LSB) ||\
+ ((__FIRSTBIT__) == UART_FIRSTBIT_MSB))
+
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((300UL <= (__BAUDRATE__)) &&\
+ ((__BAUDRATE__) <= 819200UL))
+
+#define IS_UART_FLAGR(__FLAGR__) (((__FLAGR__) == UART_FLAG_DMATXDONE) ||\
+ ((__FLAGR__) == UART_FLAG_RXPARITY) ||\
+ ((__FLAGR__) == UART_FLAG_TXDONE) ||\
+ ((__FLAGR__) == UART_FLAG_RXPE) ||\
+ ((__FLAGR__) == UART_FLAG_RXOV) ||\
+ ((__FLAGR__) == UART_FLAG_TXOV) ||\
+ ((__FLAGR__) == UART_FLAG_RXFULL))
+
+#define IS_UART_FLAGC(__FLAGC__) ((((__FLAGC__) & UART_FLAG_RCMsk) != 0U) &&\
+ (((__FLAGC__) & ~UART_FLAG_RCMsk) == 0U))
+
+#define IS_UART_INT(__INT__) ((((__INT__) & UART_INT_Msk) != 0U) &&\
+ (((__INT__) & ~UART_INT_Msk) == 0U))
+
+#define IS_UART_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == UART_INTSTS_TXDONE) ||\
+ ((__INTFLAGR__) == UART_INTSTS_RXPE) ||\
+ ((__INTFLAGR__) == UART_INTSTS_RXOV) ||\
+ ((__INTFLAGR__) == UART_INTSTS_TXOV) ||\
+ ((__INTFLAGR__) == UART_INTSTS_RX))
+
+#define IS_UART_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & UART_INTSTS_Msk) != 0U) &&\
+ (((__INTFLAGC__) & ~UART_INTSTS_Msk) == 0U))
+
+/****************************** UART Instances ********************************/
+#define IS_UART_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UART0) || \
+ ((INSTANCE) == UART1) || \
+ ((INSTANCE) == UART2) || \
+ ((INSTANCE) == UART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/* Exported Functions ------------------------------------------------------- */
+/* UART Exported Functions Group1:
+ Initialization and functions --------------*/
+void UART_DeInit(UART_Type *UARTx);
+void UART_Init(UART_Type *UARTx, UART_InitType *InitStruct);
+void UART_StructInit(UART_InitType *InitStruct);
+/* UART Exported Functions Group2:
+ (Interrupt) Flag --------------------------*/
+uint8_t UART_GetFlag(UART_Type *UARTx, uint32_t FlagMask);
+void UART_ClearFlag(UART_Type *UARTx, uint32_t FlagMask);
+void UART_INTConfig(UART_Type *UARTx, uint32_t INTMask, uint8_t NewState);
+uint8_t UART_GetINTStatus(UART_Type *UARTx, uint32_t INTMask);
+void UART_ClearINTStatus(UART_Type *UARTx, uint32_t INTMask);
+/* UART Exported Functions Group3:
+ Transfer datas ----------------------------*/
+void UART_SendData(UART_Type *UARTx, uint8_t ch);
+uint8_t UART_ReceiveData(UART_Type *UARTx);
+/* UART Exported Functions Group4:
+ MISC Configuration ------------------------*/
+void UART_BaudrateConfig(UART_Type *UARTx, uint32_t BaudRate);
+void UART_Cmd(UART_Type *UARTx, uint32_t Mode, uint32_t NewState);
+void UART_GetConfigINFO(UART_Type *UARTx, UART_ConfigINFOType *ConfigInfo);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_UART_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_version.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_version.h
new file mode 100644
index 0000000000000000000000000000000000000000..542d05e1e291ae72ef5e430e5672952d8d62425f
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_version.h
@@ -0,0 +1,36 @@
+/**
+*******************************************************************************
+ * @file lib_version.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Version library.
+*******************************************************************************/
+
+#ifndef __LIB_VERSION_H
+#define __LIB_VERSION_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+#define DRIVER_VERSION(major,minor) (((major) << 8) | (minor))
+
+/* Exported Functions ------------------------------------------------------- */
+
+/**
+ * @brief Read receive data register.
+ * @param None
+ * @retval Version value
+ */
+uint16_t Target_GetDriveVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_VERSION_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_wdt.h b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_wdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..300884dc26a5790346067bbe4e59090356ebd1b4
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_wdt.h
@@ -0,0 +1,47 @@
+/**
+ ******************************************************************************
+ * @file lib_wdt.h
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief WDT library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#ifndef __LIB_WDT_H
+#define __LIB_WDT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+
+#define WDT_2_SECS (0x0U << PMU_WDTEN_WDTSEL_Pos)
+#define WDT_4_SECS (0x1U << PMU_WDTEN_WDTSEL_Pos)
+#define WDT_8_SECS (0x2U << PMU_WDTEN_WDTSEL_Pos)
+#define WDT_16_SECS (0x3U << PMU_WDTEN_WDTSEL_Pos)
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_WDT_PERIOD(__PERIOD__) (((__PERIOD__) == WDT_2_SECS) ||\
+ ((__PERIOD__) == WDT_4_SECS) ||\
+ ((__PERIOD__) == WDT_8_SECS) ||\
+ ((__PERIOD__) == WDT_16_SECS))
+
+/* Exported Functions ------------------------------------------------------- */
+void WDT_Enable(void);
+void WDT_Disable(void);
+void WDT_Clear(void);
+void WDT_SetPeriod(uint32_t period);
+uint16_t WDT_GetCounterValue(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_WDT_H */
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_adc.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_adc.c
new file mode 100644
index 0000000000000000000000000000000000000000..769422032b2e021ac6fe62fb2bf333d6b23e69d9
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_adc.c
@@ -0,0 +1,799 @@
+/**
+ ******************************************************************************
+ * @file lib_adc.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief ADC library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_adc.h"
+
+#define ANA_INTEN_ADCMsk (0x3FC003U)
+#define ANA_INTSTS_ADCMsk (0x3FC003U)
+#define ANA_ADCCTRL0_RSTValue (0x300000U)
+#define ANA_ADCCTRL1_RSTValue (0xC2U)
+#define ANA_ADCCTRL2_RSTValue (0x8014U)
+#define ANA_ADCDATATHD1_0_RSTValue (0U)
+#define ANA_ADCDATATHD3_2_RSTValue (0U)
+#define ANA_ADCDATATHD_CH_RSTValue (0U)
+#define RTC_ADCUCALK_RSTValue (0x599A599AU)
+#define RTC_ADCMACTL_RSTValue (0x78000000U)
+#define RTC_ADCDTCTL_RSTValue (0x80000000)
+
+#define ADC_SYNC_WR(); {__NOP(); __NOP(); __NOP(); __NOP();}
+/**
+ * @brief Initializes ADC peripheral registers to their default reset values.
+ * @note 1. Disable ADC
+ 2. Disable resistor division.
+ 3. Disable ADC auto/manual done interrupt.
+ 4. The ADC correlation (register) is written to the default value.
+ * @param None
+ * @retval None
+ */
+void ADC_DeInit(void)
+{
+ uint32_t tmp[3];
+
+ if((ANA->ADCSTATE&0x07)!=0)
+ {
+ ADC_Cmd(DISABLE);
+ }
+
+ /* 6.5MHz clock. */
+ ANA->REG0 &= ~ANA_REG0_ADCFRQSEL;
+ /* ADC mode */
+ ANA->REG1 &= ~ANA_REG1_ADCMODESEL;
+ /* Power up VINBUF and REFBUF. */
+ ANA->REG11 &= ~(ANA_REG11_REFBUFPD|ANA_REG11_VINBUFPD);
+ /* Power down ADC */
+ ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
+ /* Disable interrupt, Clear interrupt flag */
+ ANA->INTEN &= ~ANA_INTEN_ADCMsk;
+ ANA->INTSTS = ANA_INTSTS_ADCMsk;
+ while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
+ ANA->ADCCTRL0 = ANA_ADCCTRL0_RSTValue;
+ while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
+ ANA->ADCCTRL1 = ANA_ADCCTRL1_RSTValue;
+ ANA->ADCCTRL2 = ANA_ADCCTRL2_RSTValue|ANA_ADCCTRL2_CONV_ERR_CLR|ANA_ADCCTRL2_CAL_ERR_CLR;
+
+ ANA->ADCDATATHD1_0= ANA_ADCDATATHD1_0_RSTValue;
+ ANA->ADCDATATHD3_2 = ANA_ADCDATATHD3_2_RSTValue;
+ ANA->ADCDATATHD_CH = ANA_ADCDATATHD_CH_RSTValue;
+ tmp[0] = RTC_ADCUCALK_RSTValue;
+ tmp[1] = RTC_ADCMACTL_RSTValue;
+ tmp[2] = RTC_ADCDTCTL_RSTValue;
+ RTC_WriteRegisters((uint32_t)&RTC->ADCUCALK, tmp, 3);
+
+ ANA->ADCCTRL2 = ANA_ADCCTRL2_RSTValue;
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct: pointer to an ADC_InitType structure which will be initialized.
+ * @retval None
+ */
+void ADC_StructInit(ADC_InitType* ADC_InitStruct)
+{
+ /*------ Reset ADC init structure parameters values ------*/
+ ADC_InitStruct->Mode = ADC_MODE_DC;
+ ADC_InitStruct->ClockSource = ADC_CLKSRC_RCH;
+ ADC_InitStruct->ClockFrq = ADC_CLKFRQ_HIGH;
+ ADC_InitStruct->SkipSample = ADC_SKIP_0;
+ ADC_InitStruct->AverageSample = ADC_AVERAGE_2;
+ ADC_InitStruct->TriggerSource = ADC_TRIGSOURCE_OFF;
+ ADC_InitStruct->Channel = ADC_CHANNEL_GND0;
+ ADC_InitStruct->ResDivEnable = 0;
+ ADC_InitStruct->AverageEnable = 0;
+}
+
+/**
+ * @brief Initializes ADC.
+ * @param ADC_InitStruct: pointer to an ADC_InitType structure which will be initialized.
+ Mode:
+ ADC_MODE_DC (Not include ADC_CHANNEL_TEMP)
+ ADC_MODE_AC (Only ADC_CHANNEL_CHx be valid)
+ ADC_MODE_TEMP (Only ADC_CHANNEL_TEMP be valid)
+ ClockSource: \n
+ ADC_CLKSRC_RCH \n
+ ADC_CLKSRC_PLLL \n
+ ClockFrq: \n
+ ADC_CLKFRQ_HIGH \n
+ ADC_CLKFRQ_LOW \n
+ SkipSample: \n
+ ADC_SKIP_0 \n
+ ADC_SKIP_4 \n
+ ADC_SKIP_8 \n
+ ADC_SKIP_12 \n
+ AverageSample: \n
+ ADC_AVERAGE_2 \n
+ ADC_AVERAGE_4 \n
+ ADC_AVERAGE_8 \n
+ ADC_AVERAGE_16 \n
+ ADC_AVERAGE_32 \n
+ ADC_AVERAGE_64 \n
+ TriggerSource: \n
+ ADC_TRIGSOURCE_OFF \n
+ ADC_TRIGSOURCE_ITVSITV \n
+ ADC_TRIGSOURCE_WKUSEC \n
+ ADC_TRIGSOURCE_ALARM \n
+ ADC_TRIGSOURCE_TMR0 \n
+ ADC_TRIGSOURCE_TMR1 \n
+ ADC_TRIGSOURCE_TMR2 \n
+ ADC_TRIGSOURCE_TMR3 \n
+ Channel:
+ ResDivEnable: (also can be ADC_CHANNEL_NONE)
+ AverageEnable: (also can be ADC_CHANNEL_NONE)
+ ADC_CHANNEL_GND0
+ ADC_CHANNEL_BAT1
+ ADC_CHANNEL_BATRTC
+ ADC_CHANNEL_CH3
+ ADC_CHANNEL_CH4
+ ADC_CHANNEL_CH5
+ ADC_CHANNEL_CH6
+ ADC_CHANNEL_CH7
+ ADC_CHANNEL_CH8
+ ADC_CHANNEL_CH9
+ ADC_CHANNEL_TEMP
+ ADC_CHANNEL_CH11
+ ADC_CHANNEL_DVCC
+ ADC_CHANNEL_GND13
+ ADC_CHANNEL_GND14
+ ADC_CHANNEL_GND15
+ ADC_CHANNEL_DC_ALL
+ ADC_CHANNEL_AC_ALL
+ * @retval None
+ */
+void ADC_Init(ADC_InitType *ADC_InitStruct)
+{
+ uint32_t tmp_anareg0, tmp_anareg1, tmp_anareg3, tmp_anareg11;
+ uint32_t tmp_adcctrl0, tmp_adcctrl1, tmp_adcctrl2;
+ uint32_t tmp_rtcadcmactl;
+
+ /* Check parameters */
+ assert_parameters(IS_ADC_MODE(ADC_InitStruct->Mode));
+ assert_parameters(IS_ADC_CLKSRC(ADC_InitStruct->ClockSource));
+ assert_parameters(IS_ADC_CLKFRQ(ADC_InitStruct->ClockFrq));
+ assert_parameters(IS_ADC_SKIP(ADC_InitStruct->SkipSample));
+ assert_parameters(IS_ADC_AVERAG(ADC_InitStruct->AverageSample));
+ assert_parameters(IS_ADC_TRIGSOURCE(ADC_InitStruct->TriggerSource));
+
+ while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
+ ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
+
+ tmp_adcctrl0 = ANA->ADCCTRL0;
+ tmp_adcctrl1 = ANA->ADCCTRL1;
+ tmp_adcctrl2 = ANA->ADCCTRL2;
+ tmp_anareg0 = ANA->REG0;
+ tmp_anareg1 = ANA->REG1;
+ tmp_anareg3 = ANA->REG3;
+ tmp_anareg11 = 0;
+ tmp_rtcadcmactl = RTC->ADCMACTL;
+
+ /* Configure clock source and trigger source */
+ tmp_adcctrl0 &= ~(ANA_ADCCTRL0_AEN | ANA_ADCCTRL0_CLKSRCSEL);
+ tmp_adcctrl0 |= (ADC_InitStruct->TriggerSource | ADC_InitStruct->ClockSource);
+
+ /* Configure ClockFrq */
+ if (ADC_InitStruct->ClockFrq == ADC_CLKFRQ_HIGH)
+ {
+ tmp_anareg0 &= ~ANA_REG0_ADCFRQSEL;
+ tmp_adcctrl2 &= ~ANA_ADCCTRL2_ADCCR;
+ }
+ else
+ {
+ tmp_anareg0 |= ANA_REG0_ADCFRQSEL;
+ tmp_adcctrl2 |= ANA_ADCCTRL2_ADCCR;
+ }
+
+ /* Configure skip samples and average samples */
+ tmp_rtcadcmactl &= ~(RTC_ADCMACTL_SKIP_SAMPLE | RTC_ADCMACTL_AVERAGE_SAMPLE);
+ tmp_rtcadcmactl |= (ADC_InitStruct->SkipSample | ADC_InitStruct->AverageSample);
+
+ /* Mode: DC */
+ if (ADC_InitStruct->Mode == ADC_MODE_DC)
+ {
+ /* Check parameters */
+ assert_parameters(IS_ADC_CHANNEL_DC(ADC_InitStruct->Channel));
+ assert_parameters(IS_ADC_CHANNEL_EN_DC(ADC_InitStruct->AverageEnable));
+ assert_parameters(IS_ADC_CHANNEL_EN_DC(ADC_InitStruct->ResDivEnable));
+
+ /* Enable or disable Channels */
+ tmp_adcctrl2 &= ~ANA_ADCCTRL2_SCAN_CHx;
+ tmp_adcctrl2 |= (ADC_InitStruct->Channel << ADC_CHANNEL_SHIFT);
+ /* Enable or disable average */
+ tmp_rtcadcmactl &= ~RTC_ADCMACTL_AVERAGE_CHx;
+ tmp_rtcadcmactl |= (ADC_InitStruct->AverageEnable << ADC_AVERAGECH_SHIFT);
+ /* Enable or disable RESDIV */
+ tmp_adcctrl1 &= ~ANA_ADCCTRL1_RESDIV_CHx;
+ tmp_adcctrl1 |= (ADC_InitStruct->ResDivEnable << ADC_RESDIVCH_SHIFT);
+ /* Others */
+ tmp_anareg1 &= ~ANA_REG1_ADCMODESEL;
+ }
+ /* Mode: AC */
+ else if (ADC_InitStruct->Mode == ADC_MODE_AC)
+ {
+ /* Check parameters */
+ assert_parameters(IS_ADC_CHANNEL_AC(ADC_InitStruct->Channel));
+ assert_parameters(IS_ADC_CHANNEL_EN_AC(ADC_InitStruct->AverageEnable));
+
+ /* Enable or disable Channels */
+ tmp_adcctrl2 &= ~ANA_ADCCTRL2_SCAN_CHx;
+ tmp_adcctrl2 |= (ADC_InitStruct->Channel << ADC_CHANNEL_SHIFT);
+ /* Enable or disable average */
+ tmp_rtcadcmactl &= ~RTC_ADCMACTL_AVERAGE_CHx;
+ tmp_rtcadcmactl |= (ADC_InitStruct->AverageEnable << ADC_AVERAGECH_SHIFT);
+ /* Enable or disable RESDIV */
+ tmp_adcctrl1 &= ~ANA_ADCCTRL1_RESDIV_CHx;
+ tmp_adcctrl1 |= (ADC_InitStruct->Channel << ADC_RESDIVCH_SHIFT);
+ /* Others */
+ tmp_anareg1 |= ANA_REG1_ADCMODESEL;
+ }
+ /* Mode: TEMP */
+ else
+ {
+ /* Check parameters */
+ assert_parameters(IS_ADC_CHANNEL_TEMP(ADC_InitStruct->Channel));
+
+ /* Enable ADC_CHANNEL_TEMP */
+ tmp_adcctrl2 &= ~ANA_ADCCTRL2_SCAN_CHx;
+ tmp_adcctrl2 |= (ADC_CHANNEL_TEMP << ADC_CHANNEL_SHIFT);
+ /* Enable average */
+ tmp_rtcadcmactl &= ~RTC_ADCMACTL_AVERAGE_CHx;
+ tmp_rtcadcmactl |= (ADC_CHANNEL_TEMP << ADC_AVERAGECH_SHIFT);
+ /* Disable RESDIV */
+ tmp_adcctrl1 &= ~ANA_ADCCTRL1_RESDIV_CHx;
+ /* Others */
+ tmp_anareg1 &= ~ANA_REG1_ADCMODESEL;
+ if(ADC_InitStruct->ClockFrq == ADC_CLKFRQ_LOW)
+ {
+ /* It can improve the accuracy of temperature measurement */
+ tmp_anareg11 |= (ANA_REG11_VINBUFPD | ANA_REG11_REFBUFPD);
+ }
+ }
+
+ ANA->ADCCTRL0 = tmp_adcctrl0&(~ANA_ADCCTRL0_MTRIG);
+ ANA->ADCCTRL1 = tmp_adcctrl1;
+ ANA->ADCCTRL2 = tmp_adcctrl2;
+ ANA->REG0 = tmp_anareg0;
+ ANA->REG1 = tmp_anareg1;
+ ANA->REG3 = tmp_anareg3;
+ ANA->REG11 = tmp_anareg11;
+ RTC_WriteRegisters((uint32_t)&RTC->ADCMACTL, &tmp_rtcadcmactl, 1);
+}
+
+/**
+ * @brief Fills each ADCTHD_InitType member with its default value.
+ * @param ADC_THDStruct: pointer to an ADC_THDStruct structure which will be initialized.
+ * @retval None
+ */
+void ADC_THDStructInit(ADCTHD_InitType* ADC_THDStruct)
+{
+ ADC_THDStruct->THDChannel = ADC_THDCHANNEL0;
+ ADC_THDStruct->UpperTHD = 0x0000;
+ ADC_THDStruct->LowerTHD = 0x0000;
+ ADC_THDStruct->TriggerSel = ADC_THDSEL_HIGH;
+ ADC_THDStruct->THDSource = ADC_CHANNEL_GND0;
+}
+
+/**
+ * @brief Initializes ADC threshold.
+ * @param ADC_THDStruct:
+ * THDChannel:
+ * ADC_THDCHANNEL0
+ * ADC_THDCHANNEL1
+ * ADC_THDCHANNEL2
+ * ADC_THDCHANNEL3
+ * UpperTHD:
+ * 0~0xFF
+ * LowerTHD:
+ * 0~0xFF
+ * TriggerSel:
+ * ADC_THDSEL_HIGH
+ * ADC_THDSEL_RISING
+ * ADC_THDSEL_FALLING
+ * ADC_THDSEL_BOTH
+ * THDSource:
+ * ADC_CHANNEL_GND0
+ * ADC_CHANNEL_BAT1
+ * ADC_CHANNEL_BATRTC
+ * ADC_CHANNEL_CH3
+ * ADC_CHANNEL_CH4
+ * ADC_CHANNEL_CH5
+ * ADC_CHANNEL_CH6
+ * ADC_CHANNEL_CH7
+ * ADC_CHANNEL_CH8
+ * ADC_CHANNEL_CH9
+ * ADC_CHANNEL_TEMP
+ * ADC_CHANNEL_CH11
+ * ADC_CHANNEL_DVCC
+ * ADC_CHANNEL_GND13
+ * ADC_CHANNEL_GND14
+ * ADC_CHANNEL_GND15
+ * @retval None
+ */
+void ADC_THDInit(ADCTHD_InitType* ADC_THDStruct)
+{
+ uint32_t tmp = 0;
+ uint32_t position = 0x00U;
+ uint32_t currentch = 0x00U;
+
+ /* Check parameters */
+ assert_parameters(IS_ADC_THDCHANNEL(ADC_THDStruct->THDChannel));
+ assert_parameters(IS_ADC_THDSEL(ADC_THDStruct->TriggerSel));
+ assert_parameters(IS_ADC_CHANNEL_GETDATA(ADC_THDStruct->THDSource));
+
+ while ((ADC_THDStruct->THDSource >> position) != 0U)
+ {
+ /* Get current ch position */
+ currentch = ADC_THDStruct->THDSource & (0x01U << position);
+
+ if (currentch)
+ {
+ break;
+ }
+ position++;
+ }
+
+ if ((ADC_THDStruct->THDChannel == ADC_THDCHANNEL0) || (ADC_THDStruct->THDChannel == ADC_THDCHANNEL1))
+ {
+ ANA->ADCDATATHD1_0 &= ~((ANA_ADCDATATHD1_0_LOWER_THD0|ANA_ADCDATATHD1_0_UPPER_THD0) << (16*ADC_THDStruct->THDChannel));
+ ANA->ADCDATATHD1_0 |= (((ADC_THDStruct->UpperTHD<<8)|ADC_THDStruct->LowerTHD) << (16*ADC_THDStruct->THDChannel));
+ }
+ else
+ {
+ ANA->ADCDATATHD3_2 &= ~((ANA_ADCDATATHD3_2_LOWER_THD2|ANA_ADCDATATHD3_2_UPPER_THD2) << (16*(ADC_THDStruct->THDChannel - 2)));
+ ANA->ADCDATATHD3_2 |= (((ADC_THDStruct->UpperTHD<<8)|ADC_THDStruct->LowerTHD) << (16*(ADC_THDStruct->THDChannel - 2)));
+ }
+
+ tmp = ANA->ADCDATATHD_CH;
+ tmp &= ~(ANA_ADCDATATHD_CH_THD0_SEL << (ADC_THDStruct->THDChannel*2));
+ tmp |= (ADC_THDStruct->TriggerSel << (ADC_THDStruct->THDChannel*2 + ANA_ADCDATATHD_CH_THD0_SEL_Pos));
+
+ tmp &= ~(ANA_ADCDATATHD_CH_THD0_CH << (ADC_THDStruct->THDChannel*4));
+ tmp |= (position << (ADC_THDStruct->THDChannel*4+ANA_ADCDATATHD_CH_THD0_CH_Pos));
+
+ ANA->ADCDATATHD_CH = tmp;
+}
+
+/**
+ * @brief Starts a ADC calibration (ADC calibration is implemented when DPORST or ADC RESET happened).
+ * @param None
+ * @retval None
+ */
+void ADC_Calibration(void)
+{
+ volatile uint32_t i;
+
+// if ((ANA->ADCCTRL2 & ANA_ADCCTRL2_RTC_CAL_DONE) && (ANA->ADCDOS != 0))
+// return;
+ //Disable ADC
+ADCCALSTART:
+ ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
+ ANA->ADCCTRL2 |= ANA_ADCCTRL2_CAL_ERR_CLR;
+ ADC_SYNC_WR();
+ //Set 6.5M ADC clock
+ ANA->REG0 &= ~ANA_REG0_ADCFRQSEL;
+ ADC_SYNC_WR();
+ while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
+ //ADC STOP
+ ANA->ADCCTRL0 = ANA_ADCCTRL0_RSTValue|ANA_ADCCTRL0_STOP;
+ ADC_SYNC_WR();
+ ANA->ADCCTRL0 = ANA_ADCCTRL0_RSTValue;
+ ADC_SYNC_WR();
+ //Reset ADC
+ ANA->ADCCTRL2 = ANA_ADCCTRL2_RSTValue | ANA_ADCCTRL2_RESET;
+ ADC_SYNC_WR();
+ ANA->ADCCTRL2 = ANA_ADCCTRL2_RSTValue;
+ ADC_SYNC_WR();
+ //Enable ADC TRG_CAL
+ ANA->ADCCTRL2 |= ANA_ADCCTRL2_ADC_EN_TRG_CAL;
+ ADC_SYNC_WR();
+ ANA->ADCCTRL2 |= ANA_ADCCTRL2_ADC_EN;
+ ADC_SYNC_WR();
+ /* while loop until ADC calibration is done */
+ ADC_SYNC_WR();
+ while (!(ANA->ADCCTRL2 & ANA_ADCCTRL2_RTC_CAL_DONE))
+ {
+ }
+ if(ANA->ADCCTRL2 & ANA_ADCCTRL2_CAL_ERR)
+ {
+ goto ADCCALSTART;
+ }
+ ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN_TRG_CAL;
+ ADC_SYNC_WR();
+ ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
+ ADC_SYNC_WR();
+
+}
+
+/**
+ * @brief Calculates ADC value via ADC original data.
+ * @param [in]Mode:
+ ADC_3V_ADCCHx_NODIV
+ ADC_3V_ADCCHx_RESDIV
+ ADC_3V_BAT1_RESDIV
+ ADC_3V_BATRTC_RESDIV
+ ADC_5V_ADCCHx_NODIV
+ ADC_5V_ADCCHx_RESDIV
+ ADC_5V_BAT1_RESDIV
+ ADC_5V_BATRTC_RESDIV
+ ADC_TEMP
+ * @param [in]adc_data: The ADC original data
+ * @param [out]value: The pointer of value calculated by this function
+ * @retval 1 NVR checksum error.
+ 0 Function successed.
+ */
+uint32_t ADC_CalculateValue(uint32_t Mode, int16_t adc_data, int16_t *value)
+{
+ NVR_ADCVOLPARA parameter;
+ NVR_TempParams TempParams;
+
+ /* Check parameters */
+ assert_parameters(IS_ADCVOL_MODE(Mode));
+
+ if (Mode == ADC_TEMP)
+ {
+ if (NVR_GetTempParameters(&TempParams))
+ {
+ return 1;
+ }
+ else
+ {
+ /* Calculate temperature */
+ *value = ((TempParams.RTCTempP0 * ((adc_data*adc_data)>>16)) + TempParams.RTCTempP1*adc_data + TempParams.RTCTempP2) >> 8;
+ }
+ }
+ else
+ {
+ if (NVR_GetVoltageParameters(Mode, ¶meter))
+ {
+ return 1;
+ }
+ else
+ {
+ *value = (int16_t)((parameter.aParameter*(float)adc_data + parameter.bParameter) + parameter.OffsetParameter);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * @brief Enables or disables ADC.
+ * @note None
+ * @param NewState
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void ADC_Cmd(uint32_t NewState)
+{
+ __IO uint32_t dly = 400UL;
+
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+ while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
+ if (NewState == DISABLE)
+ {
+ if(ANA->ADCSTATE & ANA_ADCSTATE_ADCSTATE)
+ {
+ ANA->ADCCTRL0 |= ANA_ADCCTRL0_STOP;
+ if ((MISC2->CLKSEL&MISC2_CLKSEL_CLKSEL) == MISC2_CLKSEL_CLKSEL_RTCCLK)
+ {
+ __NOP();
+ __NOP();
+ }
+ else
+ {
+ while (dly--)
+ __NOP();
+ }
+ ANA->ADCCTRL0 &= ~ANA_ADCCTRL0_STOP;
+ }
+ ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
+ }
+ else
+ {
+ ANA->ADCCTRL0 &= ~ANA_ADCCTRL0_STOP;
+ ANA->ADCCTRL2 |= ANA_ADCCTRL2_ADC_EN;
+
+ if ((MISC2->CLKSEL&MISC2_CLKSEL_CLKSEL) == MISC2_CLKSEL_CLKSEL_RTCCLK)
+ {
+ __NOP();
+ __NOP();
+ }
+ else
+ {
+ while (dly--)
+ __NOP();
+ }
+ /* Start Manual ADC conversion */
+ ADC_StartManual();
+ /* Waiting Manual ADC conversion done */
+ ADC_WaitForManual();
+ }
+}
+
+/**
+ * @brief Enables or disables ADC lower threshold detect function.
+ * @note None
+ * @param THDChannel:
+ ADC_THDCHANNEL0~ADC_THDCHANNEL3
+ NewState
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void ADC_LowerTHDCmd(uint32_t THDChannel,uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_ADC_THDCHANNEL(THDChannel));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == DISABLE)
+ {
+ ANA->ADCCTRL1 &= ~(ANA_ADCCTRL1_LOWER_THD0_EN << (THDChannel*2));
+ }
+ else
+ {
+ ANA->ADCCTRL1 |= (ANA_ADCCTRL1_LOWER_THD0_EN << (THDChannel*2));
+ }
+}
+
+/**
+ * @brief Enables or disables ADC upper threshold detect function.
+ * @note None
+ * @param THDChannel:
+ IS_ADC_THDCHANNEL0~IS_ADC_THDCHANNEL3
+ NewState
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void ADC_UpperTHDCmd(uint32_t THDChannel,uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_ADC_THDCHANNEL(THDChannel));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == DISABLE)
+ {
+ ANA->ADCCTRL1 &= ~(ANA_ADCCTRL1_UPPER_THD0_EN << (THDChannel*2));
+ }
+ else
+ {
+ ANA->ADCCTRL1 |= (ANA_ADCCTRL1_UPPER_THD0_EN << (THDChannel*2));
+ }
+}
+
+/**
+ * @brief Starts a ADC manual-trigger.
+ * @param None
+ * @retval None
+ */
+void ADC_StartManual(void)
+{
+ while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
+ ANA->ADCCTRL0 |= ANA_ADCCTRL0_MTRIG;
+}
+
+/**
+ * @brief Waits until the last Manual ADC conversion done.
+ * @param None
+ * @retval None
+ */
+void ADC_WaitForManual(void)
+{
+ while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG)
+ {
+ }
+}
+
+/**
+ * @brief Gets ADC vonversion value.
+ * @param Channel:
+ * ADC_CHANNEL_GND0
+ * ADC_CHANNEL_BAT1
+ * ADC_CHANNEL_BATRTC
+ * ADC_CHANNEL_CH3
+ * ADC_CHANNEL_CH4
+ * ADC_CHANNEL_CH5
+ * ADC_CHANNEL_CH6
+ * ADC_CHANNEL_CH7
+ * ADC_CHANNEL_CH8
+ * ADC_CHANNEL_CH9
+ * ADC_CHANNEL_TEMP
+ * ADC_CHANNEL_CH11
+ * ADC_CHANNEL_DVCC
+ * ADC_CHANNEL_GND13
+ * ADC_CHANNEL_GND14
+ * ADC_CHANNEL_GND15
+ * @retval ADC conversion value.
+ */
+int16_t ADC_GetADCConversionValue(uint32_t Channel)
+{
+ uint32_t position = 0x0000UL;
+ uint32_t chcurrent = 0x0000UL;
+
+ /* Check parameters */
+ assert_parameters(IS_ADC_CHANNEL_GETDATA(Channel));
+
+ while ((Channel >> position) != 0UL)
+ {
+ chcurrent = Channel & (0x01U << position);
+ if (chcurrent)
+ break;
+ position++;
+ }
+ return (ANA->ADCDATA[position]);
+}
+
+/**
+ * @brief Enables or disables ADC interrupt.
+ * @param INTMask: can use the '|' operator
+ ADC_INT_UPPER_TH3
+ ADC_INT_LOWER_TH3
+ ADC_INT_UPPER_TH2
+ ADC_INT_LOWER_TH2
+ ADC_INT_UPPER_TH1
+ ADC_INT_LOWER_TH1
+ ADC_INT_UPPER_TH0
+ ADC_INT_LOWER_TH0
+ ADC_INT_AUTODONE
+ ADC_INT_MANUALDONE
+ NewState
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void ADC_INTConfig(uint32_t INTMask, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+ assert_parameters(IS_ADC_INT(INTMask));
+
+ if (NewState == ENABLE)
+ ANA->INTEN |= INTMask;
+ else
+ ANA->INTEN &= ~INTMask;
+}
+
+/**
+ * @brief Clears ADC interrupt status.
+ * @param INTMask: can use the '|' operator
+ ADC_INTSTS_UPPER_TH3
+ ADC_INTSTS_LOWER_TH3
+ ADC_INTSTS_UPPER_TH2
+ ADC_INTSTS_LOWER_TH2
+ ADC_INTSTS_UPPER_TH1
+ ADC_INTSTS_LOWER_TH1
+ ADC_INTSTS_UPPER_TH0
+ ADC_INTSTS_LOWER_TH0
+ ADC_INTSTS_AUTODONE
+ ADC_INTSTS_MANUALDONE
+ * @retval None
+ */
+void ADC_ClearINTStatus(uint32_t INTMask)
+{
+ /* Parameter check */
+ assert_parameters(IS_ADC_INTFLAGC(INTMask));
+
+ ANA->INTSTS = INTMask;
+}
+
+/**
+ * @brief Gets ADC interrupt status.
+ * @param INTMask:
+ ADC_INTSTS_UPPER_TH3
+ ADC_INTSTS_LOWER_TH3
+ ADC_INTSTS_UPPER_TH2
+ ADC_INTSTS_LOWER_TH2
+ ADC_INTSTS_UPPER_TH1
+ ADC_INTSTS_LOWER_TH1
+ ADC_INTSTS_UPPER_TH0
+ ADC_INTSTS_LOWER_TH0
+ ADC_INTSTS_AUTODONE
+ ADC_INTSTS_MANUALDONE
+ * @retval 1: status set
+ 0: status reset.
+ */
+uint8_t ADC_GetINTStatus(uint32_t INTMask)
+{
+ /* Parameter check */
+ assert_parameters(IS_ADC_INTFLAGR(INTMask));
+
+ if (ANA->INTSTS & INTMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Gets ADC flag
+ * @param FlagMask
+ ADC_FLAG_CONV_ERR
+ ADC_FLAG_CAL_ERR
+ ADC_FLAG_CAL_DONE
+ ADC_FLAG_BUSY
+ * @retval 1 flag set
+ * 0 flag reset.
+ */
+uint8_t ADC_GetFlag(uint32_t FlagMask)
+{
+ /* Parameter check */
+ assert_parameters(IS_ADC_ADCFLAG(FlagMask));
+
+ if (ANA->ADCCTRL2 & FlagMask)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Clears ADC flag
+ * @param FlagMask: status to clear, can use the '|' operator.
+ ADC_FLAG_CONV_ERR
+ ADC_FLAG_CAL_ERR
+ * @retval None
+ */
+void ADC_ClearFlag(uint32_t FlagMask)
+{
+ uint32_t tmp;
+
+ /* Parameter check */
+ assert_parameters(IS_ADC_ADCFLAGC(FlagMask));
+
+ if (FlagMask == ADC_FLAG_CONV_ERR)
+ {
+ tmp = ANA->ADCCTRL2;
+ tmp &= ~ANA_ADCCTRL2_CAL_ERR_CLR;
+ tmp |= ANA_ADCCTRL2_CONV_ERR_CLR;
+ }
+ else if (FlagMask == ADC_FLAG_CAL_ERR)
+ {
+ tmp = ANA->ADCCTRL2;
+ tmp &= ~ANA_ADCCTRL2_CONV_ERR_CLR;
+ tmp |= ANA_ADCCTRL2_CAL_ERR_CLR;
+ }
+ else
+ {
+ tmp = ANA->ADCCTRL2;
+ tmp |= (ANA_ADCCTRL2_CAL_ERR_CLR | ANA_ADCCTRL2_CONV_ERR_CLR);
+ }
+ ANA->ADCCTRL2 = tmp;
+}
+
+/**
+ * @brief Gets threshold flag
+ * @param THDFlagMask
+ ADC_THDFLAG_UPPER3
+ ADC_THDFLAG_LOWER3
+ ADC_THDFLAG_UPPER2
+ ADC_THDFLAG_LOWER2
+ ADC_THDFLAG_UPPER1
+ ADC_THDFLAG_LOWER1
+ ADC_THDFLAG_UPPER0
+ ADC_THDFLAG_LOWER0
+ * @retval 1 flag set
+ * 0 flag reset.
+ */
+uint8_t ADC_GetTHDFlag(uint32_t THDFlagMask)
+{
+ /* Parameter check */
+ assert_parameters(IS_ADC_THDFLAG(THDFlagMask));
+
+ if(ANA->ADCDATATHD_CH & THDFlagMask)
+ return 1;
+ else
+ return 0;
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_adc_tiny.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_adc_tiny.c
new file mode 100644
index 0000000000000000000000000000000000000000..b24a8863e73d3498418b78a2bf883e2b0c9eb376
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_adc_tiny.c
@@ -0,0 +1,176 @@
+/**
+ ******************************************************************************
+ * @file lib_adc_tiny.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief ADC_TINY library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_adc_tiny.h"
+
+#define ANA_REGF_RSTValue (0U)
+
+/**
+ * @brief Initializes the Tiny ADC peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void TADC_DeInit(void)
+{
+ ANA->REGF = ANA_REGF_RSTValue;
+ ANA->INTSTS = ANA_INTSTS_INTSTS13;
+ ANA->INTEN &= ~ANA_INTEN_INTEN13;
+ ANA->MISC &= ~ANA_MISC_TADCTH;
+}
+
+/**
+ * @brief Fills each TADC_InitStruct member with its default value.
+ * @param TADC_InitStruct: pointer to an TADCInitType structure which will be initialized.
+ * @retval None
+ */
+void TADC_StructInit(TADCInitType* TADC_InitStruct)
+{
+ /*--------------- Reset TADC init structure parameters values ---------------*/
+ /* Initialize the SignalSel member */
+ TADC_InitStruct->SignalSel = ADCTINY_SIGNALSEL_IOE6;
+ /* Initialize the ADTREF1 member */
+ TADC_InitStruct->ADTREF1 = ADCTINY_REF1_0_9;
+ /* Initialize the ADTREF2 member */
+ TADC_InitStruct->ADTREF2 = ADCTINY_REF2_1_8;
+ /* Initialize the ADTREF3 member */
+ TADC_InitStruct->ADTREF3 = ADCTINY_REF3_2_7;
+}
+
+/**
+ * @brief Initializes Tiny ADC.
+ * @param TADC_InitStruct
+ SelADT:
+ ADCTINY_SIGNALSEL_IOE6
+ ADCTINY_SIGNALSEL_IOE7
+ ADTREF1:
+ ADCTINY_REF1_0_9
+ ADCTINY_REF1_0_7
+ ADTREF2:
+ ADCTINY_REF2_1_8
+ ADCTINY_REF2_1_6
+ ADTREF3:
+ ADCTINY_REF3_2_7
+ ADCTINY_REF3_2_5
+ * @retval None
+ */
+void TADC_Init(TADCInitType* TADC_InitStruct)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_ADCTINY_SELADT(TADC_InitStruct->SignalSel));
+ assert_parameters(IS_ADCTINY_ADTREF1(TADC_InitStruct->ADTREF1));
+ assert_parameters(IS_ADCTINY_ADTREF2(TADC_InitStruct->ADTREF2));
+ assert_parameters(IS_ADCTINY_ADTREF3(TADC_InitStruct->ADTREF3));
+
+ tmp = ANA->REGF;
+ tmp &= ~(ANA_REGF_ADTSEL \
+ |ANA_REGF_ADTREF1SEL\
+ |ANA_REGF_ADTREF2SEL\
+ |ANA_REGF_ADTREF3SEL);
+ tmp |= (TADC_InitStruct->SignalSel \
+ |TADC_InitStruct->ADTREF1\
+ |TADC_InitStruct->ADTREF2\
+ |TADC_InitStruct->ADTREF3);
+ ANA->REGF = tmp;
+}
+
+/**
+ * @brief Enables or disables Tiny ADC .
+ * @param NewState
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void TADC_Cmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState == ENABLE)
+ ANA->REGF |= ANA_REGF_ADTPDN;
+ else
+ ANA->REGF &= ~ANA_REGF_ADTPDN;
+}
+
+/**
+ * @brief Gets Tiny ADC output value.
+ * @param None
+ * @retval Output of Tiny ADC(0 ~ 3).
+ */
+uint8_t TADC_GetOutput(void)
+{
+ return ((ANA->CMPOUT & ANA_CMPOUT_TADCO) >> ANA_CMPOUT_TADCO_Pos);
+}
+
+/**
+ * @brief Configures Tiny ADC interrupt threshold.
+ * @param THSel:
+ ADCTINY_THSEL_0
+ ADCTINY_THSEL_1
+ ADCTINY_THSEL_2
+ ADCTINY_THSEL_3
+ * @retval None.
+ */
+void TADC_IntTHConfig(uint32_t THSel)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_ADCTINY_THSEL(THSel));
+
+ tmp = ANA->MISC;
+ tmp &= ~ANA_MISC_TADCTH;
+ tmp |= THSel;
+ ANA->MISC = tmp;
+}
+
+/**
+ * @brief Enables or disables Tiny ADC interrupt.
+ * @param NewState
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void TADC_INTConfig(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState == ENABLE)
+ ANA->INTEN |= ANA_INTEN_INTEN13;
+ else
+ ANA->INTEN &= ~ANA_INTEN_INTEN13;
+}
+
+/**
+ * @brief Gets Tiny ADC interrupt status.
+ * @param None
+ * @retval Interrupt status.
+ */
+uint8_t TADC_GetINTStatus(void)
+{
+ if (ANA->INTSTS & ANA_INTSTS_INTSTS13)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Clears Tiny ADC interrupt status.
+ * @param None
+ * @retval None
+ */
+void TADC_ClearINTStatus(void)
+{
+ ANA->INTSTS = ANA_INTSTS_INTSTS13;
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_ana.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_ana.c
new file mode 100644
index 0000000000000000000000000000000000000000..766f8303a0437433b6237d2e1787456eb0280015
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_ana.c
@@ -0,0 +1,160 @@
+/**
+ ******************************************************************************
+ * @file lib_ana.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Analog library.
+ ******************************************************************************
+ * @attention
+ *
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "lib_ana.h"
+
+/**
+ * @brief Gets analog status.
+ * @param StatusMask:
+ ANA_STATUS_AVCCLV
+ ANA_STATUS_VDCINDROP
+ ANA_STATUS_VDDALARM
+ ANA_STATUS_COMP2
+ ANA_STATUS_COMP1
+ ANA_STATUS_LOCKL
+ ANA_STATUS_LOCKH
+ * @retval Analog status
+ */
+uint8_t ANA_GetStatus(uint32_t StatusMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_ANA_STATUS(StatusMask));
+
+ if (ANA->CMPOUT & StatusMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Gets analog interrupt status.
+ * @param IntMask:
+ ANA_INT_UPPER_TH3
+ ANA_INT_LOWER_TH3
+ ANA_INT_UPPER_TH2
+ ANA_INT_LOWER_TH2
+ ANA_INT_UPPER_TH1
+ ANA_INT_LOWER_TH1
+ ANA_INT_UPPER_TH0
+ ANA_INT_LOWER_TH0
+ ANA_INT_TADC_OVER
+ ANA_INT_REGERR
+ ANA_INT_SLPFAIL_VDCIN
+ ANA_INT_AVCCLV
+ ANA_INT_VDCINDROP
+ ANA_INT_VDDALARM
+ ANA_INT_COMP2
+ ANA_INT_COMP1
+ ANA_INT_ADCA
+ ANA_INT_ADCM
+ * @retval interrupt status.
+ */
+uint8_t ANA_GetINTStatus(uint32_t IntMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_ANA_INTSTSR(IntMask));
+
+ if (ANA->INTSTS&IntMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears analog interrupt status.
+ * @param IntMask:status to clear, can use the '|' operator.
+ ANA_INT_UPPER_TH3
+ ANA_INT_LOWER_TH3
+ ANA_INT_UPPER_TH2
+ ANA_INT_LOWER_TH2
+ ANA_INT_UPPER_TH1
+ ANA_INT_LOWER_TH1
+ ANA_INT_UPPER_TH0
+ ANA_INT_LOWER_TH0
+ ANA_INT_TADC_OVER
+ ANA_INT_REGERR
+ ANA_INT_SLPFAIL_VDCIN
+ ANA_INT_AVCCLV
+ ANA_INT_VDCINDROP
+ ANA_INT_VDDALARM
+ ANA_INT_COMP2
+ ANA_INT_COMP1
+ ANA_INT_ADCA
+ ANA_INT_ADCM
+ * @retval None
+ */
+void ANA_ClearINTStatus(uint32_t IntMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_ANA_INTSTSC(IntMask));
+
+ ANA->INTSTS = IntMask;
+}
+
+/**
+ * @brief Enables or disables analog interrupt.
+ * @param IntMask:status to clear, can use the '|' operator.
+ ANA_INT_UPPER_TH3
+ ANA_INT_LOWER_TH3
+ ANA_INT_UPPER_TH2
+ ANA_INT_LOWER_TH2
+ ANA_INT_UPPER_TH1
+ ANA_INT_LOWER_TH1
+ ANA_INT_UPPER_TH0
+ ANA_INT_LOWER_TH0
+ ANA_INT_TADC_OVER
+ ANA_INT_REGERR
+ ANA_INT_SLPFAIL_VDCIN
+ ANA_INT_AVCCLV
+ ANA_INT_VDCINDROP
+ ANA_INT_VDDALARM
+ ANA_INT_COMP2
+ ANA_INT_COMP1
+ ANA_INT_ADCA
+ ANA_INT_ADCM
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void ANA_INTConfig(uint32_t IntMask, uint32_t NewState)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_ANA_INT(IntMask));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = ANA->INTEN;
+ if (NewState == ENABLE)
+ {
+ tmp |= IntMask;
+ }
+ else
+ {
+ tmp &= ~IntMask;
+ }
+ ANA->INTEN = tmp;
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_clk.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_clk.c
new file mode 100644
index 0000000000000000000000000000000000000000..fae28dc9afdf4d4a3450b2482ee8f5ddbe6045fd
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_clk.c
@@ -0,0 +1,675 @@
+/**
+ ******************************************************************************
+ * @file lib_clk.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Clock library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_clk.h"
+
+/**
+ * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
+ * parameters in the CLK_ClkInitStruct.
+ *
+ * @note This function performs the following:
+ * 1. If want to switch AHB clock source, enable BGP, enable 6.5M RC,
+ * AHB clock source switch to RCH first.
+ * 2. configure clock (except AHB clock source configuration). - optional
+ * 3. configure AHB clock source. - optional
+ * 4. HCLK/PCLK divider configuration. - optional
+ *
+ * @note CLK_InitTypeDef *CLK_ClkInitStruct
+ * [in]CLK_ClkInitStruct->ClockType, can use the '|' operator, the selection of parameters is as follows
+ * CLK_TYPE_ALL
+ * CLK_TYPE_AHBSRC
+ * CLK_TYPE_PLLL
+ * CLK_TYPE_PLLH
+ * CLK_TYPE_XTALH
+ * CLK_TYPE_RTCCLK
+ * CLK_TYPE_HCLK
+ * CLK_TYPE_PCLK
+ *
+ * CLK_TYPE_ALL All clocks' configurations is valid
+ * CLK_TYPE_AHBSRC CLK_ClkInitStruct->AHBSource(AHB Clock source configuration) is valid
+ * [in]CLK_ClkInitStruct->AHBSource:
+ * CLK_AHBSEL_6_5MRC
+ * CLK_AHBSEL_6_5MXTAL
+ * CLK_AHBSEL_HSPLL
+ * CLK_AHBSEL_RTCCLK
+ * CLK_AHBSEL_LSPLL
+ * CLK_TYPE_PLLL CLK_ClkInitStruct->PLLL(PLLL configuration) is valid
+ * [in]CLK_ClkInitStruct->PLLL.State:
+ * CLK_PLLL_ON (PLLL.Source/Frequency configuration is valid)
+ * CLK_PLLL_OFF (PLLL.Source/Frequency configuration is not valid)
+ * [in]CLK_ClkInitStruct->PLLL.Source:
+ * CLK_PLLLSRC_RCL
+ * CLK_PLLLSRC_XTALL
+ * [in]CLK_ClkInitStruct->PLLL.Frequency:
+ * CLK_PLLL_26_2144MHz
+ * CLK_PLLL_13_1072MHz
+ * CLK_PLLL_6_5536MHz
+ * CLK_PLLL_3_2768MHz
+ * CLK_PLLL_1_6384MHz
+ * CLK_PLLL_0_8192MHz
+ * CLK_PLLL_0_4096MHz
+ * CLK_PLLL_0_2048MHz
+ * CLK_TYPE_PLLH CLK_ClkInitStruct->PLLH(PLLH configuration) is valid
+ * [in]CLK_ClkInitStruct->PLLH.State:
+ * CLK_PLLH_ON (PLLH.Source/Frequency configuration is valid)
+ * CLK_PLLH_OFF (PLLH.Source/Frequency configuration is not valid)
+ * [in]CLK_ClkInitStruct->PLLH.Source:
+ * CLK_PLLHSRC_RCH
+ * CLK_PLLHSRC_XTALH
+ * [in]CLK_ClkInitStruct->PLLH.Frequency:
+ * CLK_PLLH_13_1072MHz
+ * CLK_PLLH_16_384MHz
+ * CLK_PLLH_19_6608MHz
+ * CLK_PLLH_22_9376MHz
+ * CLK_PLLH_26_2144MHz
+ * CLK_PLLH_29_4912MHz
+ * CLK_PLLH_32_768MHz
+ * CLK_PLLH_36_0448MHz
+ * CLK_PLLH_39_3216MHz
+ * CLK_PLLH_42_5984MHz
+ * CLK_PLLH_45_8752MHz
+ * CLK_PLLH_49_152MHz
+ * CLK_TYPE_XTALH CLK_ClkInitStruct->XTALH(XTALH configuration) is valid
+ * [in]CLK_ClkInitStruct->XTALH.State:
+ * CLK_XTALH_ON
+ * CLK_XTALH_OFF
+ * CLK_TYPE_RTCCLK CLK_ClkInitStruct->RTCCLK(RTCCLK configuration) is valid
+ * [in]CLK_ClkInitStruct->RTCCLK.Source:
+ * CLK_RTCCLKSRC_XTALL
+ * CLK_RTCCLKSRC_RCL
+ * [in]CLK_ClkInitStruct->RTCCLK.Divider:
+ * CLK_RTCCLKDIV_1
+ * CLK_RTCCLKDIV_4
+ * CLK_TYPE_HCLK CLK_ClkInitStruct->HCLK(AHB Clock(divider) configuration) is valid
+ * [in]CLK_ClkInitStruct->HCLK.Divider:
+ * 1 ~ 256
+ * CLK_TYPE_PCLK CLK_ClkInitStruct->PCLK(APB Clock(divider) configuration) is valid
+ * [in]CLK_ClkInitStruct->PCLK.Divider:
+ * 1 ~ 256
+ *
+ * @param CLK_ClkInitStruct pointer to an CLK_InitTypeDef structure that
+ * contains the configuration information for the clocks.
+ *
+ * @retval None
+ */
+void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct)
+{
+ uint32_t tmp;
+
+ assert_parameters(IS_CLK_TYPE(CLK_ClkInitStruct->ClockType));
+
+ if (CLK_ClkInitStruct->ClockType & CLK_TYPE_AHBSRC)
+ {
+ /* Enable BGP */
+ ANA->REG3 &= ~ANA_REG3_BGPPD;
+ /* Enable 6.5M RC */
+ ANA->REG3 &= ~ANA_REG3_RCHPD;
+
+ /* AHB clock source switch to RCH */
+ MISC2->CLKSEL = 0;
+ }
+
+ ANA->REGA &= ~BIT6;
+
+ /*---------- XTALH configuration ----------*/
+ if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_XTALH)
+ {
+ assert_parameters(IS_CLK_XTALHSTA(CLK_ClkInitStruct->XTALH.State));
+
+ /* XTALH state configure */
+ ANA->REG3 &= ~ANA_REG3_XOHPDN;
+ ANA->REG3 |= CLK_ClkInitStruct->XTALH.State;
+
+ }
+
+ /*-------------------- PLLL configuration --------------------*/
+ if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLL)
+ {
+ assert_parameters(IS_CLK_PLLLSRC(CLK_ClkInitStruct->PLLL.Source));
+ assert_parameters(IS_CLK_PLLLSTA(CLK_ClkInitStruct->PLLL.State));
+ assert_parameters(IS_CLK_PLLLFRQ(CLK_ClkInitStruct->PLLL.Frequency));
+
+ /* PLLL state configure */
+ if (CLK_ClkInitStruct->PLLL.State == CLK_PLLL_ON)
+ {
+ /* power up PLLL */
+ ANA->REG3 |= ANA_REG3_PLLLPDN;
+
+ /* Configure PLLL frequency */
+ tmp = ANA->REG9;
+ tmp &= ~ANA_REG9_PLLLSEL;
+ tmp |= CLK_ClkInitStruct->PLLL.Frequency;
+ ANA->REG9 = tmp;
+
+ /* Configure PLLL input clock selection */
+ tmp = PMU->CONTROL;
+ tmp &= ~PMU_CONTROL_PLLL_SEL;
+ tmp |= CLK_ClkInitStruct->PLLL.Source;
+ PMU->CONTROL = tmp;
+ }
+ else
+ {
+ /* power down PLLL */
+ ANA->REG3 &= ~ANA_REG3_PLLLPDN;
+ }
+ }
+
+ /*-------------------- PLLH configuration --------------------*/
+ if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLH)
+ {
+ assert_parameters(IS_CLK_PLLHSRC(CLK_ClkInitStruct->PLLH.Source));
+ assert_parameters(IS_CLK_PLLHSTA(CLK_ClkInitStruct->PLLH.State));
+ assert_parameters(IS_CLK_PLLHFRQ(CLK_ClkInitStruct->PLLH.Frequency));
+
+ /* PLLH state configure */
+ if (CLK_ClkInitStruct->PLLH.State == CLK_PLLH_ON)
+ {
+ /* Power up PLLH */
+ ANA->REG3 |= ANA_REG3_PLLHPDN;
+
+ /* Configure PLLH frequency */
+ tmp = ANA->REG9;
+ tmp &= ~ANA_REG9_PLLHSEL;
+ tmp |= CLK_ClkInitStruct->PLLH.Frequency;
+ ANA->REG9 = tmp;
+
+ /* Clock input source, XTALH, XOH power on*/
+ if (CLK_ClkInitStruct->PLLH.Source == CLK_PLLHSRC_XTALH)
+ {
+ ANA->REG3 |= ANA_REG3_XOHPDN;
+ }
+
+ /* Configure PLLH input clock selection */
+ tmp = PMU->CONTROL;
+ tmp &= ~PMU_CONTROL_PLLH_SEL;
+ tmp |= CLK_ClkInitStruct->PLLH.Source;
+ PMU->CONTROL = tmp;
+ }
+ else
+ {
+ /* Power down PLLH */
+ ANA->REG3 &= ~ANA_REG3_PLLHPDN;
+ }
+ }
+
+ /*---------- RTCCLK configuration ----------*/
+ if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_RTCCLK)
+ {
+ assert_parameters(IS_CLK_RTCSRC(CLK_ClkInitStruct->RTCCLK.Source));
+ assert_parameters(IS_CLK_RTCDIV(CLK_ClkInitStruct->RTCCLK.Divider));
+
+ /* RTCCLK source(optional) */
+ tmp = PMU->CONTROL;
+ tmp &= ~PMU_CONTROL_RTCCLK_SEL;
+ tmp |= CLK_ClkInitStruct->RTCCLK.Source;
+ PMU->CONTROL = tmp;
+
+ /*----- RTCCLK Divider -----*/
+ RTC_PrescalerConfig(CLK_ClkInitStruct->RTCCLK.Divider);
+ }
+
+ /*---------- AHB clock source configuration ----------*/
+ if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_AHBSRC)
+ {
+ assert_parameters(IS_CLK_AHBSRC(CLK_ClkInitStruct->AHBSource));
+
+ /* clock source: 6.5M RC */
+ if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MRC)
+ {
+ /* clock source configuration */
+ MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
+ }
+
+ /* clock source: 6_5MXTAL */
+ else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MXTAL)
+ {
+ /* Power up 6.5M xtal */
+ ANA->REG3 |= ANA_REG3_XOHPDN;
+ /* clock source configuration */
+ MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
+ }
+
+ /* clock source: PLLH */
+ else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_HSPLL)
+ {
+ /* Power up PLLH */
+ ANA->REG3 |= ANA_REG3_PLLHPDN;
+ /* while loop until PLLL is lock */
+ while (!(ANA->CMPOUT & ANA_CMPOUT_LOCKH))
+ {
+ }
+ /* clock source configuration */
+ MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
+ }
+
+ /* clock source: PLLL */
+ else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_LSPLL)
+ {
+ /* Power up PLLL */
+ ANA->REG3 |= ANA_REG3_PLLLPDN;
+ /* while loop until PLLL is lock */
+ while (!(ANA->CMPOUT & ANA_CMPOUT_LOCKL))
+ {
+ }
+ /* clock source configuration */
+ MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
+ }
+ /* clock source: RTCCLK */
+ else
+ {
+ /* clock source configuration */
+ MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
+ }
+ }
+
+ /*---------- HCLK configuration ----------*/
+ if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_HCLK)
+ {
+ assert_parameters(IS_CLK_HCLKDIV(CLK_ClkInitStruct->HCLK.Divider));
+
+ MISC2->CLKDIVH = (CLK_ClkInitStruct->HCLK.Divider) - 1;
+ }
+
+ /*---------- PCLK configuration ----------*/
+ if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PCLK)
+ {
+ assert_parameters(IS_CLK_PCLKDIV(CLK_ClkInitStruct->PCLK.Divider));
+
+ MISC2->CLKDIVP = (CLK_ClkInitStruct->PCLK.Divider) - 1;
+ }
+}
+
+/**
+ * @brief Enables or disables AHB Periphral clock.
+ * @param Periphral: can use the '|' operator
+ CLK_AHBPERIPHRAL_DMA
+ CLK_AHBPERIPHRAL_GPIO
+ CLK_AHBPERIPHRAL_LCD
+ CLK_AHBPERIPHRAL_CRYPT
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_CLK_AHBPERIPHRAL(Periphral));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ MISC2->HCLKEN |= Periphral;
+ }
+ else
+ {
+ MISC2->HCLKEN &= ~Periphral;
+ }
+}
+
+/**
+ * @brief Enables or disables APB Periphral clock.
+ * @param Periphral: can use the '|' operator
+ CLK_APBPERIPHRAL_DMA
+ CLK_APBPERIPHRAL_I2C
+ CLK_APBPERIPHRAL_SPI1
+ CLK_APBPERIPHRAL_SPI2
+ CLK_APBPERIPHRAL_UART0
+ CLK_APBPERIPHRAL_UART1
+ CLK_APBPERIPHRAL_UART2
+ CLK_APBPERIPHRAL_UART3
+ CLK_APBPERIPHRAL_UART4
+ CLK_APBPERIPHRAL_UART5
+ CLK_APBPERIPHRAL_ISO78160
+ CLK_APBPERIPHRAL_ISO78161
+ CLK_APBPERIPHRAL_TIMER
+ CLK_APBPERIPHRAL_MISC
+ CLK_APBPERIPHRAL_MISC2
+ CLK_APBPERIPHRAL_PMU
+ CLK_APBPERIPHRAL_RTC
+ CLK_APBPERIPHRAL_ANA
+ CLK_APBPERIPHRAL_U32K0
+ CLK_APBPERIPHRAL_U32K1
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_CLK_APBPERIPHRAL(Periphral));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ MISC2->PCLKEN |= Periphral;
+ }
+ else
+ {
+ MISC2->PCLKEN &= ~Periphral;
+ }
+}
+
+/**
+ * @brief Returns the HCLK frequency
+ * @param None
+ * @retval HCLK frequency
+ */
+uint32_t CLK_GetHCLKFreq(void)
+{
+ uint32_t ahb_clksrc;
+ uint32_t ahb_div;
+ uint32_t pllh_frq;
+ uint32_t plll_frq;
+ uint32_t rtcclk_div;
+ uint32_t hclk;
+
+ /* Get current AHB clock source */
+ ahb_clksrc = MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL;
+ /* Get AHB clock divider */
+ ahb_div = (MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1;
+
+ switch (ahb_clksrc)
+ {
+ /* AHB Clock source : 6.5M RC */
+ case MISC2_CLKSEL_CLKSEL_RCOH:
+ hclk = 6553600 / ahb_div;
+ break;
+
+ /* AHB Clock source : 6.5M XTAL */
+ case MISC2_CLKSEL_CLKSEL_XOH:
+ hclk = 6553600 / ahb_div;
+ break;
+
+ /* AHB Clock source : PLLH */
+ case MISC2_CLKSEL_CLKSEL_PLLH:
+ /* Get PLLH Frequency */
+ pllh_frq = ANA->REG9 & ANA_REG9_PLLHSEL;
+ switch (pllh_frq)
+ {
+ case ANA_REG9_PLLHSEL_X2:
+ hclk = 13107200 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X2_5:
+ hclk = 16384000 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X3:
+ hclk = 19660800 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X3_5:
+ hclk = 22937600 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X4:
+ hclk = 26214400 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X4_5:
+ hclk = 29491200 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X5:
+ hclk = 32768000 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X5_5:
+ hclk = 36044800 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X6:
+ hclk = 39321600 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X6_5:
+ hclk = 42598400 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X7:
+ hclk = 45875200 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLHSEL_X7_5:
+ hclk = 49152000 / ahb_div;
+ break;
+
+ default:
+ hclk = 0;
+ break;
+ }
+ break;
+
+ /* AHB Clock source : RTCCLK */
+ case MISC2_CLKSEL_CLKSEL_RTCCLK:
+ /* Get current RTC clock divider */
+ rtcclk_div = RTC->PSCA & RTC_PSCA_PSCA;
+ if (rtcclk_div == RTC_PSCA_PSCA_0)
+ {
+ hclk = 32768 / ahb_div;
+ }
+ else if (rtcclk_div == RTC_PSCA_PSCA_1)
+ {
+ hclk = 8192 / ahb_div;
+ }
+ else
+ {
+ hclk = 0;
+ }
+ break;
+
+ /* AHB Clock source : PLLL */
+ case MISC2_CLKSEL_CLKSEL_PLLL:
+ /* Get PLLL Frequency */
+ plll_frq = ANA->REG9 & ANA_REG9_PLLLSEL;
+ switch (plll_frq)
+ {
+ case ANA_REG9_PLLLSEL_26M:
+ hclk = 26214400 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLLSEL_13M:
+ hclk = 13107200 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLLSEL_6_5M:
+ hclk = 6553600 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLLSEL_3_2M:
+ hclk = 3276800 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLLSEL_1_6M:
+ hclk = 1638400 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLLSEL_800K:
+ hclk = 819200 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLLSEL_400K:
+ hclk = 409600 / ahb_div;
+ break;
+
+ case ANA_REG9_PLLLSEL_200K:
+ hclk = 204800 / ahb_div;
+ break;
+
+ default:
+ hclk = 0;
+ break;
+ }
+ break;
+
+ default:
+ hclk = 0;
+ break;
+ }
+
+ return (hclk);
+}
+
+/**
+ * @brief Returns the PLLL frequency
+ * @param None
+ * @retval PLLL frequency
+ */
+uint32_t CLK_GetPLLLFreq(void)
+{
+ uint32_t plll_frq;
+
+ if (!(ANA->REG3 & ANA_REG3_PLLLPDN))
+ return 0;
+ /* Get PLLL Frequency */
+ plll_frq = ANA->REG9 & ANA_REG9_PLLLSEL;
+ switch (plll_frq)
+ {
+ case ANA_REG9_PLLLSEL_26M:
+ plll_frq = 26214400;
+ break;
+
+ case ANA_REG9_PLLLSEL_13M:
+ plll_frq = 13107200;
+ break;
+
+ case ANA_REG9_PLLLSEL_6_5M:
+ plll_frq = 6553600;
+ break;
+
+ case ANA_REG9_PLLLSEL_3_2M:
+ plll_frq = 3276800;
+ break;
+
+ case ANA_REG9_PLLLSEL_1_6M:
+ plll_frq = 1638400;
+ break;
+
+ case ANA_REG9_PLLLSEL_800K:
+ plll_frq = 819200;
+ break;
+
+ case ANA_REG9_PLLLSEL_400K:
+ plll_frq = 409600;
+ break;
+
+ case ANA_REG9_PLLLSEL_200K:
+ plll_frq = 204800;
+ break;
+
+ default:
+ plll_frq = 0;
+ break;
+ }
+
+ return (plll_frq);
+}
+
+/**
+ * @brief Returns the PCLK frequency
+ * @param None
+ * @retval PCLK frequency
+ */
+uint32_t CLK_GetPCLKFreq(void)
+{
+ return ((CLK_GetHCLKFreq()) / ((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1));
+}
+
+/**
+ * @brief Get the CLK_ClkInitStruct according to the internal
+ * Clock configuration registers.
+ *
+ * @param CLK_ClkInitStruct pointer to an CLK_ClkInitStruct structure that
+ * contains the current clock configuration.
+ *
+ * @retval None
+ */
+void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct)
+{
+ /* Set all possible values for the Clock type parameter --------------------*/
+ CLK_ClkInitStruct->ClockType = CLK_TYPE_ALL;
+
+ /* Get AHB clock source ----------------------------------------------------*/
+ CLK_ClkInitStruct->AHBSource = (uint32_t)(MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL);
+ /* Get PLLL clock configration ---------------------------------------------*/
+ CLK_ClkInitStruct->PLLL.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLL_SEL);
+ CLK_ClkInitStruct->PLLL.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLLSEL);
+ CLK_ClkInitStruct->PLLL.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLLPDN);
+ /* Get PLLH clock configuration --------------------------------------------*/
+ CLK_ClkInitStruct->PLLH.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLH_SEL);
+ CLK_ClkInitStruct->PLLH.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLHSEL);
+ CLK_ClkInitStruct->PLLH.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLHPDN);
+ /* Get XTALH configuration -------------------------------------------------*/
+ CLK_ClkInitStruct->XTALH.State = (uint32_t)(ANA->REG3 & ANA_REG3_XOHPDN);
+ /* Get HCLK(Divider) configuration -----------------------------------------*/
+ CLK_ClkInitStruct->HCLK.Divider = (uint32_t)((MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1);
+ /* Get PCLK((Divider) configuration ----------------------------------------*/
+ CLK_ClkInitStruct->PCLK.Divider = (uint32_t)((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1);
+}
+
+/**
+ * @brief Gets current external 6.5M crystal status.
+ *
+ * @param None
+ *
+ * @retval 6.5M crystal status
+ * 0: 6.5536M crystal is absent.
+ * 1: 6.5536M crystal is present.
+ */
+uint8_t CLK_GetXTALHStatus(void)
+{
+ if (PMU->STS & PMU_STS_EXIST_6M)
+ return (1);
+ else
+ return (0);
+}
+
+/**
+ * @brief Gets current external 32K crystal status.
+ *
+ * @param None
+ *
+ * @retval 32K crystal status
+ * 0: 32K crystal is absent
+ * 1: 32K crystal is present.
+ */
+uint8_t CLK_GetXTALLStatus(void)
+{
+ if (PMU->STS & PMU_STS_EXIST_32K)
+ return (1);
+ else
+ return (0);
+}
+
+/**
+ * @brief Gets PLL lock status.
+ * @param PLLStatus:
+ * CLK_STATUS_LOCKL
+ * CLK_STATUS_LOCKH
+ * @retval PLL lock status
+ * 0 PLL is not locked.
+ * 1 PLL is locked.
+ */
+uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus)
+{
+ /* Check parameters */
+ assert_parameters(IS_CLK_PLLLOCK(PLLStatus));
+
+ if (ANA->CMPOUT & PLLStatus)
+ return 1;
+ else
+ return 0;
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_cmp.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_cmp.c
new file mode 100644
index 0000000000000000000000000000000000000000..2a61afb07af81f222764ff13ce64b8f12b469723
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_cmp.c
@@ -0,0 +1,569 @@
+/**
+ ******************************************************************************
+ * @file lib_cmp.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief CMP library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_cmp.h"
+
+/* CMP1 reset values */
+#define CMP1_REG2_Msk (0x13UL)
+#define CMP1_REG3_Msk (0x02UL)
+#define CMP1_REG5_Msk (0x03UL)
+#define CMP1_REGF_Msk (0x01UL)
+#define CMP1_CTRL_Msk (0x300003UL)
+#define CMP1_INTSTS_Msk (0x04UL)
+#define CMP1_INTEN_Msk (0x04UL)
+#define CMP1_THR_Msk (0xFFFFUL)
+#define CMP1_CTL_Msk (0x300FFUL)
+/* CMP2 reset values */
+#define CMP2_REG2_Msk (0x2CUL)
+#define CMP2_REG3_Msk (0x04UL)
+#define CMP2_REG5_Msk (0x0CUL)
+#define CMP2_REGF_Msk (0x02UL)
+#define CMP2_CTRL_Msk (0xC0000CUL)
+#define CMP2_INTSTS_Msk (0x08UL)
+#define CMP2_INTEN_Msk (0x08UL)
+#define CMP2_THR_Msk (0xFFFF0000UL)
+#define CMP2_CTL_Msk (0x30FF00UL)
+
+/**
+ * @brief Initializes the Comparator peripheral registers to their default reset values.
+ * @param CMPx:
+ CMP_1
+ CMP_2
+ * @retval None
+ */
+void CMP_DeInit(uint32_t CMPx)
+{
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+
+ if (CMPx == CMP_1)
+ {
+ ANA->REG2 &= ~CMP1_REG2_Msk;
+ ANA->REG3 &= ~CMP1_REG3_Msk;
+ ANA->REG5 &= ~CMP1_REG5_Msk;
+ ANA->REGF &= ~CMP1_REGF_Msk;
+ ANA->CTRL &= ~CMP1_CTRL_Msk;
+ ANA->INTSTS = CMP1_INTSTS_Msk;
+ ANA->INTEN &= ~CMP1_INTEN_Msk;
+ ANA->CMPTHR &= ~CMP1_THR_Msk;
+ ANA->CMPCTL &= ~CMP1_CTL_Msk;
+ ANA->CMPCNT1 = 0;
+ }
+ else
+ {
+ ANA->REG2 &= ~CMP2_REG2_Msk;
+ ANA->REG3 &= ~CMP2_REG3_Msk;
+ ANA->REG5 &= ~CMP2_REG5_Msk;
+ ANA->REGF &= ~CMP2_REGF_Msk;
+ ANA->CTRL &= ~CMP2_CTRL_Msk;
+ ANA->INTSTS = CMP2_INTSTS_Msk;
+ ANA->INTEN &= ~CMP2_INTEN_Msk;
+ ANA->CMPTHR &= ~CMP2_THR_Msk;
+ ANA->CMPCTL &= ~CMP2_CTL_Msk;
+ ANA->CMPCNT2 = 0;
+ }
+}
+
+/**
+ * @brief Initializes comparator.
+ * @param CMPx:
+ CMP_1
+ CMP_2
+ InitStruct: Comparator configuration
+ DebSel:
+ CMP_DEB_NONE
+ CMP_DEB_RTCCLK_2
+ CMP_DEB_RTCCLK_3
+ CMP_DEB_RTCCLK_4
+ SignalSourceSel:
+ CMP_SIGNALSRC_PPIN_TO_VREF
+ CMP_SIGNALSRC_PPIN_TO_BGPREF
+ CMP_SIGNALSRC_PBAT_TO_VREF
+ CMP_SIGNALSRC_PBAT_TO_BGPREF
+ CMP_SIGNALSRC_NPIN_TO_VREF
+ CMP_SIGNALSRC_NPIN_TO_BGPREF
+ CMP_SIGNALSRC_PPIN_TO_NPIN
+ CMP_SIGNALSRC_PBAT_TO_NPIN
+ BiasSel:
+ CMP_BIAS_20nA
+ CMP_BIAS_100nA
+ CMP_BIAS_500nA
+ * @retval None
+ */
+void CMP_Init(uint32_t CMPx, CMP_TypeDef *InitStruct)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+ assert_parameters(IS_CMP_DEB(InitStruct->DebSel));
+ assert_parameters(IS_CMP_SIGNALSRC(InitStruct->SignalSourceSel));
+ assert_parameters(IS_CMP_BIAS(InitStruct->BiasSel));
+
+ /* CMP1 Configure */
+ if (CMPx == CMP_1)
+ {
+ tmp = ANA->CTRL;
+ tmp &= ~ANA_CTRL_CMP1DEB;
+ tmp |= (InitStruct->DebSel << ANA_CTRL_CMP1DEB_Pos);
+ ANA->CTRL = tmp;
+
+ tmp = ANA->REG5;
+ tmp &= ~ANA_REG5_CMP1IT;
+ tmp |= (InitStruct->BiasSel << ANA_REG5_CMP1IT_Pos);
+ ANA->REG5 = tmp;
+
+ ANA->REG2 &= ~(ANA_REG2_CMP1SEL|ANA_REG2_CMP1REFSEL);
+ ANA->REGF &= ~ANA_REGF_BAT1DETEN;
+ switch(InitStruct->SignalSourceSel)
+ {
+ case CMP_SIGNALSRC_PPIN_TO_VREF:
+ break;
+ case CMP_SIGNALSRC_PPIN_TO_BGPREF: ANA->REG2 |= ANA_REG2_CMP1REFSEL;
+ break;
+ case CMP_SIGNALSRC_PBAT_TO_VREF: ANA->REGF |= ANA_REGF_BAT1DETEN;
+ break;
+ case CMP_SIGNALSRC_PBAT_TO_BGPREF: ANA->REG2 |= ANA_REG2_CMP1REFSEL;
+ ANA->REGF |= ANA_REGF_BAT1DETEN;
+ break;
+ case CMP_SIGNALSRC_NPIN_TO_VREF: ANA->REG2 |= ANA_REG2_CMP1SEL_1;
+ break;
+ case CMP_SIGNALSRC_NPIN_TO_BGPREF: ANA->REG2 |= (ANA_REG2_CMP1SEL_1|ANA_REG2_CMP1REFSEL);
+ break;
+ case CMP_SIGNALSRC_PPIN_TO_NPIN: ANA->REG2 |= ANA_REG2_CMP1SEL_3;
+ break;
+ case CMP_SIGNALSRC_PBAT_TO_NPIN: ANA->REG2 |= ANA_REG2_CMP1SEL_3;
+ ANA->REGF |= ANA_REGF_BAT1DETEN;
+ break;
+ default:
+ break;
+ }
+ }
+ /* CMP2 Configure */
+ else
+ {
+ tmp = ANA->CTRL;
+ tmp &= ~ANA_CTRL_CMP2DEB;
+ tmp |= (InitStruct->DebSel << ANA_CTRL_CMP2DEB_Pos);
+ ANA->CTRL = tmp;
+
+ tmp = ANA->REG5;
+ tmp &= ~ANA_REG5_CMP2IT;
+ tmp |= (InitStruct->BiasSel << ANA_REG5_CMP2IT_Pos);
+ ANA->REG5 = tmp;
+
+ ANA->REG2 &= ~(ANA_REG2_CMP2SEL|ANA_REG2_CMP2REFSEL);
+ ANA->REGF &= ~ANA_REGF_BATRTCDETEN;
+ switch(InitStruct->SignalSourceSel)
+ {
+ case CMP_SIGNALSRC_PPIN_TO_VREF:
+ break;
+ case CMP_SIGNALSRC_PPIN_TO_BGPREF: ANA->REG2 |= ANA_REG2_CMP2REFSEL;
+ break;
+ case CMP_SIGNALSRC_PBAT_TO_VREF: ANA->REGF |= ANA_REGF_BATRTCDETEN;
+ break;
+ case CMP_SIGNALSRC_PBAT_TO_BGPREF: ANA->REG2 |= ANA_REG2_CMP2REFSEL;
+ ANA->REGF |= ANA_REGF_BATRTCDETEN;
+ break;
+ case CMP_SIGNALSRC_NPIN_TO_VREF: ANA->REG2 |= ANA_REG2_CMP2SEL_1;
+ break;
+ case CMP_SIGNALSRC_NPIN_TO_BGPREF: ANA->REG2 |= (ANA_REG2_CMP2SEL_1|ANA_REG2_CMP2REFSEL);
+ break;
+ case CMP_SIGNALSRC_PPIN_TO_NPIN: ANA->REG2 |= ANA_REG2_CMP2SEL_3;
+ break;
+ case CMP_SIGNALSRC_PBAT_TO_NPIN: ANA->REG2 |= ANA_REG2_CMP2SEL_3;
+ ANA->REGF |= ANA_REGF_BATRTCDETEN;
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Fills each CMP_TypeDef member with its default value.
+ * @param InitStruct: pointer to an CMP_TypeDef structure which will be initialized.
+ * @retval None
+ */
+void CMP_StructInit(CMP_TypeDef *InitStruct)
+{
+ InitStruct->DebSel = CMP_DEB_NONE;
+ InitStruct->SignalSourceSel = CMP_SIGNALSRC_PPIN_TO_VREF;
+ InitStruct->BiasSel = CMP_BIAS_20nA;
+}
+
+/**
+ * @brief Initializes comparator Count.
+ * @param CMPx:
+ CMP_1
+ CMP_2
+ InitStruct: Comparator configuration
+ ModeSel:
+ CMP_MODE_OFF
+ CMP_MODE_RISING
+ CMP_MODE_FALLING
+ CMP_MODE_BOTH
+ CheckPeriod:
+ CMP_PERIOD_30US
+ CMP_PERIOD_7_8125MS
+ CMP_PERIOD_125MS
+ CMP_PERIOD_250MS
+ CMP_PERIOD_500MS
+ CheckNum:
+ CMP_CHKNUM_1~CMP_CHKNUM_16
+ * @retval None
+ */
+void CMP_CountInit(uint32_t CMPx, CMP_CountTypeDef *InitStruct)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+ assert_parameters(IS_CMP_MODE(InitStruct->ModeSel));
+ assert_parameters(IS_CMP_CHECKPERIOD(InitStruct->CheckPeriod));
+ assert_parameters(IS_CMP_CHKNUM(InitStruct->CheckNum));
+
+ /* CMP1 Configure */
+ if (CMPx == CMP_1)
+ {
+ /* Configure ModeSel */
+ tmp = ANA->CTRL;
+ tmp &= ~ANA_CTRL_CMP1SEL;
+ tmp |= (InitStruct->ModeSel << ANA_CTRL_CMP1SEL_Pos);
+ ANA->CTRL = tmp;
+
+ /* Configure CheckPeriod/CheckNum */
+ tmp = ANA->CMPCTL;
+ tmp &= ~(ANA_CMPCTL_CMP1_CHK_FRQ|ANA_CMPCTL_CMP1_CHK_NUM);
+ tmp |= ((InitStruct->CheckPeriod << ANA_CMPCTL_CMP1_CHK_FRQ_Pos) | \
+ (InitStruct->CheckNum << ANA_CMPCTL_CMP1_CHK_NUM_Pos));
+ ANA->CMPCTL = tmp;
+ }
+ /* CMP2 Configure */
+ else
+ {
+ /* Configure ModeSel */
+ tmp = ANA->CTRL;
+ tmp &= ~ANA_CTRL_CMP2SEL;
+ tmp |= (InitStruct->ModeSel << ANA_CTRL_CMP2SEL_Pos);
+ ANA->CTRL = tmp;
+
+ /* Configure CheckPeriod/CheckNum */
+ tmp = ANA->CMPCTL;
+ tmp &= ~(ANA_CMPCTL_CMP2_CHK_FRQ|ANA_CMPCTL_CMP2_CHK_NUM);
+ tmp |= ((InitStruct->CheckPeriod << ANA_CMPCTL_CMP2_CHK_FRQ_Pos) | \
+ (InitStruct->CheckNum << ANA_CMPCTL_CMP2_CHK_NUM_Pos));
+ ANA->CMPCTL = tmp;
+ }
+}
+
+/**
+ * @brief Fill each CMP_CountTypeDef member with its default value.
+ * @param InitStruct: pointer to an CMP_CountTypeDef structure which will be initialized.
+ * @retval None
+ */
+void CMP_CountStructInit(CMP_CountTypeDef *InitStruct)
+{
+ InitStruct->ModeSel = CMP_MODE_OFF;
+ InitStruct->CheckPeriod = CMP_PERIOD_30US;
+ InitStruct->CheckNum = CMP_CHKNUM_1;
+}
+
+/**
+ * @brief Initializes Comparator interrupt.
+ * @param CMPx:
+ CMP_1
+ CMP_2
+ InitStruct: Comparator configuration
+ INTNumSel:
+ CMP_INTNUM_EVERY
+ CMP_INTNUM_1
+ SubSel:
+ CMP_COUNT_NOSUB
+ CMP_COUNT_SUB
+ THRNum:0~65535
+ * @retval None
+ */
+void CMP_INTInit(uint32_t CMPx, CMP_INTTypeDef *InitStruct)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+ assert_parameters(IS_CMP_INTNUM(InitStruct->INTNumSel));
+ assert_parameters(IS_CMP_COUNT(InitStruct->SubSel));
+ assert_parameters(IS_CMP_THRNUM(InitStruct->THRNum));
+
+ /* CMP1 Configure */
+ if (CMPx == CMP_1)
+ {
+ /* Configure INTNumSel/SubSel */
+ tmp = ANA->CMPCTL;
+ tmp &= ~(ANA_CMPCTL_CMP1_THR_EN|ANA_CMPCTL_CMP1_INT_MASK_EN);
+ tmp |= ((InitStruct->SubSel << ANA_CMPCTL_CMP1_THR_EN_Pos) | \
+ (InitStruct->INTNumSel << ANA_CMPCTL_CMP1_INT_MASK_EN_Pos));
+ ANA->CMPCTL = tmp;
+
+ /* Configure THRNum */
+ tmp = ANA->CMPTHR;
+ tmp &= ~ANA_CMPTHR_CMP1_THR;
+ tmp |= (InitStruct->THRNum << ANA_CMPTHR_CMP1_THR_Pos);
+ ANA->CMPTHR = tmp;
+ }
+ /* CMP2 Configure */
+ else
+ {
+ /* Configure INTNumSel/SubSel */
+ tmp = ANA->CMPCTL;
+ tmp &= ~(ANA_CMPCTL_CMP2_THR_EN|ANA_CMPCTL_CMP2_INT_MASK_EN);
+ tmp |= ((InitStruct->SubSel << ANA_CMPCTL_CMP2_THR_EN_Pos) | \
+ (InitStruct->INTNumSel << ANA_CMPCTL_CMP2_INT_MASK_EN_Pos));
+ ANA->CMPCTL = tmp;
+
+ /* Configure THRNum */
+ tmp = ANA->CMPTHR;
+ tmp &= ~ANA_CMPTHR_CMP2_THR;
+ tmp |= (InitStruct->THRNum << ANA_CMPTHR_CMP2_THR_Pos);
+ ANA->CMPTHR = tmp;
+ }
+}
+
+/**
+ * @brief Fills each CMP_INTTypeDef member with its default value.
+ * @param InitStruct: pointer to an CMP_INTTypeDef structure which will be initialized.
+ * @retval None
+ */
+void CMP_INTStructInit(CMP_INTTypeDef *InitStruct)
+{
+ InitStruct->INTNumSel = CMP_INTNUM_EVERY;
+ InitStruct->SubSel = CMP_COUNT_NOSUB;
+ InitStruct->THRNum = 0;
+}
+
+/**
+ * @brief Initializes Comparator Output IO.
+ * @param CMPx:
+ CMP_1
+ CMP_2
+ InitStruct: Comparator configuration
+ DebSel:
+ CMP_OUTPUT_DEB
+ CMP_OUTPUT_NODEB
+ OutputSel:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void CMP_OutputInit(uint32_t CMPx, CMP_OutputTypeDef *InitStruct)
+{
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+ assert_parameters(IS_CMP_OUTPUTDEB(InitStruct->DebSel));
+ assert_parameters(IS_FUNCTIONAL_STATE(InitStruct->OutputSel));
+
+ /* CMP1 Configure */
+ if (CMPx == CMP_1)
+ {
+ ANA->CMPCTL &= ~ANA_CMPCTL_CMP1_IO_NODEB;
+ ANA->CMPCTL |= (InitStruct->DebSel << ANA_CMPCTL_CMP1_IO_NODEB_Pos);
+
+ GPIOAF->IOE_SEL &= ~GPIOAF_IOE_SEL_SEL7;
+ GPIOAF->IOE_SEL |= (InitStruct->OutputSel << GPIOAF_IOE_SEL_SEL7_Pos);
+ }
+ /* CMP2 Configure */
+ else
+ {
+ ANA->CMPCTL &= ~ANA_CMPCTL_CMP2_IO_NODEB;
+ ANA->CMPCTL |= (InitStruct->DebSel << ANA_CMPCTL_CMP2_IO_NODEB_Pos);
+
+ GPIOA->SEL &= ~GPIOA_SEL_SEL6;
+ GPIOA->SEL |= (InitStruct->OutputSel << GPIOA_SEL_SEL6_Pos);
+ }
+}
+
+/**
+ * @brief Fills each CMP_OutputTypeDef member with its default value.
+ * @param InitStruct: pointer to an CMP_OutputTypeDef structure which will be initialized.
+ * @retval None
+ */
+void CMP_OutputStructInit(CMP_OutputTypeDef *InitStruct)
+{
+ InitStruct->DebSel = CMP_OUTPUT_DEB;
+ InitStruct->OutputSel = DISABLE;
+}
+
+/**
+ * @brief Gets comparator count value.
+ * @param CMPx:
+ CMP_1
+ CMP_2
+ * @retval Comparator count value.
+ */
+uint32_t CMP_GetCNTValue(uint32_t CMPx)
+{
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+
+ if (CMPx == CMP_1)
+ {
+ return ANA->CMPCNT1;
+ }
+ else
+ {
+ return ANA->CMPCNT2;
+ }
+}
+
+/**
+ * @brief Clears comparator counter value.
+ * @param CMPx:
+ CMP_1
+ CMP_2
+ * @retval None
+ */
+void CMP_ClearCNTValue(uint32_t CMPx)
+{
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+
+ if (CMPx == CMP_1)
+ {
+ ANA->CMPCNT1 = 0;
+ }
+ else
+ {
+ ANA->CMPCNT2 = 0;
+ }
+}
+
+/**
+ * @brief Enables or disables Comparator.
+ * @param CMPx:
+ CMP_1
+ CMP_2
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void CMP_Cmd(uint32_t CMPx, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (CMPx == CMP_1)
+ {
+ ANA->REG3 &= ~ANA_REG3_CMP1PDN;
+ ANA->REG3 |= (NewState << ANA_REG3_CMP1PDN_Pos);
+ }
+ else
+ {
+ ANA->REG3 &= ~ANA_REG3_CMP2PDN;
+ ANA->REG3 |= (NewState << ANA_REG3_CMP2PDN_Pos);
+ }
+}
+
+/**
+ * @brief Gets comparator output level
+ * @param None
+ * @retval Output of comparator
+ */
+uint8_t CMP_GetOutputValue(uint32_t CMPx)
+{
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+
+ if (CMPx == CMP_1)
+ {
+ return ((ANA->CMPOUT & ANA_CMPOUT_CMP1) >> ANA_CMPOUT_CMP1_Pos);
+ }
+ else
+ {
+ return ((ANA->CMPOUT & ANA_CMPOUT_CMP2) >> ANA_CMPOUT_CMP2_Pos);
+ }
+}
+
+/**
+ * @brief Enables or disables Comparator interrupt.
+ * @param CMPx:
+ * CMP_1
+ * CMP_2
+ * NewState:
+ * ENABLE
+ * DISABLE
+ * @retval None
+ */
+void CMP_INTConfig(uint32_t CMPx, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+
+ if (CMPx == CMP_1)
+ {
+ ANA->INTEN &= ~ANA_INTEN_INTEN2;
+ ANA->INTEN |= (NewState<INTEN &= ~ANA_INTEN_INTEN3;
+ ANA->INTEN |= (NewState<INTSTS & ANA_INTSTS_INTSTS2) >> ANA_INTSTS_INTSTS2_Pos);
+ }
+ else
+ {
+ return ((ANA->INTSTS & ANA_INTSTS_INTSTS3) >> ANA_INTSTS_INTSTS3_Pos);
+ }
+}
+
+/**
+ * @brief Clears comparator interrupt flag.
+ * @param CMPx:
+ * CMP_1
+ * CMP_2
+ * @retval None
+ */
+void CMP_ClearINTStatus(uint32_t CMPx)
+{
+ /* Check parameters */
+ assert_parameters(IS_CMP(CMPx));
+
+ if (CMPx == CMP_1)
+ {
+ ANA->INTSTS = ANA_INTSTS_INTSTS2;
+ }
+ else
+ {
+ ANA->INTSTS = ANA_INTSTS_INTSTS3;
+ }
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_crypt.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_crypt.c
new file mode 100644
index 0000000000000000000000000000000000000000..9c253482ae22bda852f05b36d414da552a2eef22
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_crypt.c
@@ -0,0 +1,226 @@
+/**
+ ******************************************************************************
+ * @file lib_crypt.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief CRYPT library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_crypt.h"
+
+/**
+ * @brief Configures PTRA register, data in this address will be read out to do
+ * the CRYPT calculation
+ * @param AddrA: the SRAM address(Bit 15:0)
+ * @retval None
+ */
+void CRYPT_AddressAConfig(uint16_t AddrA)
+{
+ /* Check parameters */
+ assert_parameters(IS_CRYPT_ADDR(AddrA));
+
+ CRYPT->PTRA = AddrA & CRYPT_PTRA_PTRA;
+}
+
+/**
+ * @brief Configures PTRB register, data in this address will be read out to do
+ * the CRYPT calculation
+ * @param AddrB: the SRAM address(Bit 15:0)
+ * @retval None
+ */
+void CRYPT_AddressBConfig(uint16_t AddrB)
+{
+ /* Check parameters */
+ assert_parameters(IS_CRYPT_ADDR(AddrB));
+
+ CRYPT->PTRB = AddrB & CRYPT_PTRB_PTRB;
+}
+
+/**
+ * @brief Configures PTRO register, The CRYPT engine will write calculation
+ * result into this address
+ * @param AddrO: the SRAM address(Bit 15:0)
+ * @retval None
+ */
+void CRYPT_AddressOConfig(uint16_t AddrO)
+{
+ /* Check parameters */
+ assert_parameters(IS_CRYPT_ADDR(AddrO));
+
+ CRYPT->PTRO = AddrO & CRYPT_PTRO_PTRO;
+}
+
+/**
+ * @brief Gets carry/borrow bit of add/sub operation.
+ * @param None
+ * @retval carry/borrow bit value
+ */
+uint8_t CRYPT_GetCarryBorrowBit(void)
+{
+ if (CRYPT->CARRY & CRYPT_CARRY_CARRY)
+ return (1);
+ else
+ return (0);
+}
+
+/**
+ * @brief Starts addition operation.
+ * @param Length:
+ * CRYPT_LENGTH_32
+ * CRYPT_LENGTH_64
+ * CRYPT_LENGTH_96
+ * CRYPT_LENGTH_128
+ * CRYPT_LENGTH_160
+ * CRYPT_LENGTH_192
+ * CRYPT_LENGTH_224
+ * CRYPT_LENGTH_256
+ * CRYPT_LENGTH_288
+ * CRYPT_LENGTH_320
+ * CRYPT_LENGTH_352
+ * CRYPT_LENGTH_384
+ * CRYPT_LENGTH_416
+ * CRYPT_LENGTH_448
+ * CRYPT_LENGTH_480
+ * CRYPT_LENGTH_512
+ * Nostop:
+ * CRYPT_STOPCPU
+ * CRYPT_NOSTOPCPU
+ * @retval None
+ */
+void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop)
+{
+ /* Check parameters */
+ assert_parameters(IS_CRYPT_LENGTH(Length));
+ assert_parameters(IS_CRYPT_NOSTOP(Nostop));
+
+ CRYPT->CTRL = (Nostop \
+ |Length \
+ |CRYPT_CTRL_MODE_ADD \
+ |CRYPT_CTRL_ACT);
+}
+
+/**
+ * @brief Starts multiplication operation.
+ * @param Length:
+ * CRYPT_LENGTH_32
+ * CRYPT_LENGTH_64
+ * CRYPT_LENGTH_96
+ * CRYPT_LENGTH_128
+ * CRYPT_LENGTH_160
+ * CRYPT_LENGTH_192
+ * CRYPT_LENGTH_224
+ * CRYPT_LENGTH_256
+ * CRYPT_LENGTH_288
+ * CRYPT_LENGTH_320
+ * CRYPT_LENGTH_352
+ * CRYPT_LENGTH_384
+ * CRYPT_LENGTH_416
+ * CRYPT_LENGTH_448
+ * CRYPT_LENGTH_480
+ * CRYPT_LENGTH_512
+ * Nostop:
+ * CRYPT_STOPCPU
+ * CRYPT_NOSTOPCPU
+ * @retval None
+ */
+void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop)
+{
+ /* Check parameters */
+ assert_parameters(IS_CRYPT_LENGTH(Length));
+ assert_parameters(IS_CRYPT_NOSTOP(Nostop));
+
+ CRYPT->CTRL = (Nostop \
+ |Length \
+ |CRYPT_CTRL_MODE_MULTIPLY \
+ |CRYPT_CTRL_ACT);
+}
+
+/**
+ * @brief Starts subtraction operation.
+ * @param Length:
+ * CRYPT_LENGTH_32
+ * CRYPT_LENGTH_64
+ * CRYPT_LENGTH_96
+ * CRYPT_LENGTH_128
+ * CRYPT_LENGTH_160
+ * CRYPT_LENGTH_192
+ * CRYPT_LENGTH_224
+ * CRYPT_LENGTH_256
+ * CRYPT_LENGTH_288
+ * CRYPT_LENGTH_320
+ * CRYPT_LENGTH_352
+ * CRYPT_LENGTH_384
+ * CRYPT_LENGTH_416
+ * CRYPT_LENGTH_448
+ * CRYPT_LENGTH_480
+ * CRYPT_LENGTH_512
+ * Nostop:
+ * CRYPT_STOPCPU
+ * CRYPT_NOSTOPCPU
+ * @retval None
+ */
+void CRYPT_StartSub(uint32_t Length, uint32_t Nostop)
+{
+ /* Check parameters */
+ assert_parameters(IS_CRYPT_LENGTH(Length));
+ assert_parameters(IS_CRYPT_NOSTOP(Nostop));
+
+ CRYPT->CTRL = (Nostop \
+ |Length \
+ |CRYPT_CTRL_MODE_SUB \
+ |CRYPT_CTRL_ACT);
+}
+
+/**
+ * @brief Starts rigth shift 1-bit operation.
+ * @param Length:
+ * CRYPT_LENGTH_32
+ * CRYPT_LENGTH_64
+ * CRYPT_LENGTH_96
+ * CRYPT_LENGTH_128
+ * CRYPT_LENGTH_160
+ * CRYPT_LENGTH_192
+ * CRYPT_LENGTH_224
+ * CRYPT_LENGTH_256
+ * CRYPT_LENGTH_288
+ * CRYPT_LENGTH_320
+ * CRYPT_LENGTH_352
+ * CRYPT_LENGTH_384
+ * CRYPT_LENGTH_416
+ * CRYPT_LENGTH_448
+ * CRYPT_LENGTH_480
+ * CRYPT_LENGTH_512
+ * Nostop:
+ * CRYPT_STOPCPU
+ * CRYPT_NOSTOPCPU
+ * @retval None
+ */
+void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop)
+{
+ /* Check parameters */
+ assert_parameters(IS_CRYPT_LENGTH(Length));
+ assert_parameters(IS_CRYPT_NOSTOP(Nostop));
+
+ CRYPT->CTRL = (Nostop \
+ |Length \
+ |CRYPT_CTRL_MODE_RSHIFT1 \
+ |CRYPT_CTRL_ACT);
+}
+
+/**
+ * @brief Waits until last operation to complete.
+ * @param None
+ * @retval None
+ */
+void CRYPT_WaitForLastOperation(void)
+{
+ while (CRYPT->CTRL & CRYPT_CTRL_ACT)
+ {
+ }
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_dma.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_dma.c
new file mode 100644
index 0000000000000000000000000000000000000000..1000b331e4e76496312d98b83752c262e0049bdb
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_dma.c
@@ -0,0 +1,473 @@
+/**
+ ******************************************************************************
+ * @file lib_dma.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief DMA library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_dma.h"
+
+//registers default reset values
+#define DMA_CxCTL_RSTValue (0UL)
+#define DMA_CxSRC_RSTValue (0UL)
+#define DMA_CxDST_RSTValue (0UL)
+#define DMA_AESCTL_RSTValue (0UL)
+#define DMA_AESKEY_RSTValue (0UL)
+
+/**
+ * @brief Initializes the DMA channel peripheral registers to their default reset values.
+ * @param Channel: DMA_CHANNEL_0~DMA_CHANNEL_3
+ * @retval None
+ */
+void DMA_DeInit(uint32_t Channel)
+{
+ __IO uint32_t *addr;
+
+ /* Check parameters */
+ assert_parameters(IS_DMA_CHANNEL(Channel));
+
+ /* channel x disable, clear stop */
+ addr = &DMA->C0CTL + Channel*4;
+ *addr &= ~(DMA_CCTL_EN | DMA_CCTL_STOP);
+
+ /* interrupt disable */
+ DMA->IE &= ~((1<<(Channel))\
+ |(1<<(Channel+4))\
+ |(1<<(Channel+8)));
+
+ /* interrupt state clear */
+ DMA->STS = (1<<(Channel+4))\
+ |(1<<(Channel+8))\
+ |(1<<(Channel+12));
+
+ /* DMA_CxCTL */
+ addr = &DMA->C0CTL + Channel*4;
+ *addr = DMA_CxCTL_RSTValue;
+
+ /* DMA_CxSRC */
+ addr = &DMA->C0SRC + Channel*4;
+ *addr = DMA_CxSRC_RSTValue;
+
+ /* DMA_CxDST */
+ addr = &DMA->C0DST + Channel*4;
+ *addr = DMA_CxDST_RSTValue;
+}
+/**
+ * @brief Fills each DMA_InitType member with its default value.
+ * @param InitStruct: pointer to an DMA_InitType structure which will be initialized.
+ * @retval None
+ */
+void DMA_StructInit(DMA_InitType *InitStruct)
+{
+ /*-------------- Reset DMA init structure parameters values ---------------*/
+ /* Initialize the DestAddr member */
+ InitStruct->DestAddr = 0;
+ /* Initialize the SrcAddr member */
+ InitStruct->SrcAddr = 0;
+ /* Initialize the FrameLen member */
+ InitStruct->FrameLen = 0;
+ /* Initialize the PackLen member */
+ InitStruct->PackLen = 0;
+ /* Initialize the ContMode member */
+ InitStruct->ContMode = DMA_CONTMODE_DISABLE;
+ /* Initialize the TransMode member */
+ InitStruct->TransMode = DMA_TRANSMODE_SINGLE;
+ /* Initialize the ReqSrc member */
+ InitStruct->ReqSrc = DMA_REQSRC_SOFT;
+ /* Initialize the DestAddrMode member */
+ InitStruct->DestAddrMode = DMA_DESTADDRMODE_FIX;
+ /* Initialize the SrcAddrMode member */
+ InitStruct->SrcAddrMode = DMA_SRCADDRMODE_FIX;
+ /* Initialize the TransSize member */
+ InitStruct->TransSize = DMA_TRANSSIZE_BYTE;
+}
+/**
+ * @brief Initializes DMA channel.
+ * @param InitStruct: DMA configuration.
+ DestAddr : destination address
+ SrcAddr : source address
+ FrameLen : Frame length (Ranges 0~255, actual length FrameLen+1)
+ PackLen : Package length (Ranges 0~255, actual length PackLen+1)
+ ContMode:
+ DMA_CONTMODE_ENABLE
+ DMA_CONTMODE_DISABLE
+ TransMode:
+ DMA_TRANSMODE_SINGLE
+ DMA_TRANSMODE_PACK
+ ReqSrc:
+ DMA_REQSRC_SOFT
+ DMA_REQSRC_ADC
+ DMA_REQSRC_UART0TX
+ DMA_REQSRC_UART0RX
+ DMA_REQSRC_UART1TX
+ DMA_REQSRC_UART1RX
+ DMA_REQSRC_UART2TX
+ DMA_REQSRC_UART2RX
+ DMA_REQSRC_UART3TX
+ DMA_REQSRC_UART3RX
+ DMA_REQSRC_UART4TX
+ DMA_REQSRC_UART4RX
+ DMA_REQSRC_UART5TX
+ DMA_REQSRC_UART5RX
+ DMA_REQSRC_ISO78160TX
+ DMA_REQSRC_ISO78160RX
+ DMA_REQSRC_ISO78161TX
+ DMA_REQSRC_ISO78161RX
+ DMA_REQSRC_TIMER0
+ DMA_REQSRC_TIMER1
+ DMA_REQSRC_TIMER2
+ DMA_REQSRC_TIMER3
+ DMA_REQSRC_SPI1TX
+ DMA_REQSRC_SPI1RX
+ DMA_REQSRC_U32K0
+ DMA_REQSRC_U32K1
+ DMA_REQSRC_CMP1
+ DMA_REQSRC_CMP2
+ DMA_REQSRC_SPI2TX
+ DMA_REQSRC_SPI2RX
+ DMA_REQSRC_SPI3TX
+ DMA_REQSRC_SPI3RX
+ DestAddrMode:
+ DMA_DESTADDRMODE_FIX
+ DMA_DESTADDRMODE_PEND
+ DMA_DESTADDRMODE_FEND
+ SrcAddrMode:
+ DMA_SRCADDRMODE_FIX
+ DMA_SRCADDRMODE_PEND
+ DMA_SRCADDRMODE_FEND
+ TransSize:
+ DMA_TRANSSIZE_BYTE
+ DMA_TRANSSIZE_HWORD
+ DMA_TRANSSIZE_WORD
+ Channel:
+ DMA_CHANNEL_0
+ DMA_CHANNEL_1
+ DMA_CHANNEL_2
+ DMA_CHANNEL_3
+ * @retval None
+ */
+void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel)
+{
+ uint32_t tmp;
+ __IO uint32_t *addr;
+
+ /* Check parameters */
+ assert_parameters(IS_DMA_CHANNEL(Channel));
+ assert_parameters(IS_DMA_CONTMOD(InitStruct->ContMode));
+ assert_parameters(IS_DMA_TRANSMOD(InitStruct->TransMode));
+ assert_parameters(IS_DMA_REQSRC(InitStruct->ReqSrc));
+ assert_parameters(IS_DMA_DESTADDRMOD(InitStruct->DestAddrMode));
+ assert_parameters(IS_DMA_SRCADDRMOD(InitStruct->SrcAddrMode));
+ assert_parameters(IS_DMA_TRANSSIZE(InitStruct->TransSize));
+
+ if (InitStruct->TransSize == DMA_TRANSSIZE_HWORD)
+ {
+ assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->SrcAddr));
+ assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->DestAddr));
+ }
+ if (InitStruct->TransSize == DMA_TRANSSIZE_WORD)
+ {
+ assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->SrcAddr));
+ assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->DestAddr));
+ }
+
+ addr = &DMA->C0DST + Channel*4;
+ *addr = InitStruct->DestAddr;
+
+ addr = &DMA->C0SRC + Channel*4;
+ *addr = InitStruct->SrcAddr;
+
+ addr = &DMA->C0CTL + Channel*4;
+
+ tmp = *addr;
+ tmp &= ~(DMA_CCTL_FLEN\
+ |DMA_CCTL_PLEN\
+ |DMA_CCTL_CONT\
+ |DMA_CCTL_TMODE\
+ |DMA_CCTL_DMASEL\
+ |DMA_CCTL_DMODE\
+ |DMA_CCTL_SMODE\
+ |DMA_CCTL_SIZE);
+ tmp |= ((InitStruct->FrameLen<PackLen<ContMode)\
+ |(InitStruct->TransMode)\
+ |(InitStruct->ReqSrc)\
+ |(InitStruct->DestAddrMode)\
+ |(InitStruct->SrcAddrMode)\
+ |(InitStruct->TransSize));
+ *addr = tmp;
+}
+
+/**
+ * @brief Initializes the DMA AES channel3 registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void DMA_ASEDeInit(void)
+{
+ DMA->AESCTL = DMA_AESCTL_RSTValue;
+ DMA->AESKEY[0] = DMA_AESKEY_RSTValue;
+ DMA->AESKEY[1] = DMA_AESKEY_RSTValue;
+ DMA->AESKEY[2] = DMA_AESKEY_RSTValue;
+ DMA->AESKEY[3] = DMA_AESKEY_RSTValue;
+ DMA->AESKEY[4] = DMA_AESKEY_RSTValue;
+ DMA->AESKEY[5] = DMA_AESKEY_RSTValue;
+ DMA->AESKEY[6] = DMA_AESKEY_RSTValue;
+ DMA->AESKEY[7] = DMA_AESKEY_RSTValue;
+}
+
+/**
+ * @brief Initializes AES.
+ * @param InitStruct: AES configuration.
+ Mode:
+ DMA_AESMODE_128
+ DMA_AESMODE_192
+ DMA_AESMODE_256
+ Direction:
+ DMA_AESDIRECTION_ENCODE
+ DMA_AESDIRECTION_DECODE
+ KeyStr: the pointer to DMA_AESKEYx register
+ * @retval None
+ */
+void DMA_AESInit(DMA_AESInitType *InitStruct)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_DMA_AESMOD(InitStruct->Mode));
+ assert_parameters(IS_DMA_AESDIR(InitStruct->Direction));
+
+ tmp = DMA->AESCTL;
+ tmp &= ~(DMA_AESCTL_MODE\
+ |DMA_AESCTL_ENC);
+ tmp |= (InitStruct->Mode\
+ |InitStruct->Direction);
+ DMA->AESCTL = tmp;
+ DMA->AESKEY[0] = InitStruct->KeyStr[0];
+ DMA->AESKEY[1] = InitStruct->KeyStr[1];
+ DMA->AESKEY[2] = InitStruct->KeyStr[2];
+ DMA->AESKEY[3] = InitStruct->KeyStr[3];
+
+ if ((InitStruct->Mode == DMA_AESMODE_192) ||\
+ (InitStruct->Mode == DMA_AESMODE_256))
+ {
+ DMA->AESKEY[4] = InitStruct->KeyStr[4];
+ DMA->AESKEY[5] = InitStruct->KeyStr[5];
+ }
+ if (InitStruct->Mode == DMA_AESMODE_256)
+ {
+ DMA->AESKEY[6] = InitStruct->KeyStr[6];
+ DMA->AESKEY[7] = InitStruct->KeyStr[7];
+ }
+}
+
+/**
+ * @brief Enables or disables DMA interrupt.
+ * @param INTMask: can use the '|' operator
+ DMA_INT_C3DA
+ DMA_INT_C2DA
+ DMA_INT_C1DA
+ DMA_INT_C0DA
+ DMA_INT_C3FE
+ DMA_INT_C2FE
+ DMA_INT_C1FE
+ DMA_INT_C0FE
+ DMA_INT_C3PE
+ DMA_INT_C2PE
+ DMA_INT_C1PE
+ DMA_INT_C0PE
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void DMA_INTConfig(uint32_t INTMask, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_DMA_INT(INTMask));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ DMA->IE |= INTMask;
+ else
+ DMA->IE &= ~INTMask;
+}
+
+/**
+ * @brief Gets DMA interrupt status.
+ * @param INTMask:
+ DMA_INTSTS_C3DA
+ DMA_INTSTS_C2DA
+ DMA_INTSTS_C1DA
+ DMA_INTSTS_C0DA
+ DMA_INTSTS_C3FE
+ DMA_INTSTS_C2FE
+ DMA_INTSTS_C1FE
+ DMA_INTSTS_C0FE
+ DMA_INTSTS_C3PE
+ DMA_INTSTS_C2PE
+ DMA_INTSTS_C1PE
+ DMA_INTSTS_C0PE
+ DMA_INTSTS_C3BUSY
+ DMA_INTSTS_C2BUSY
+ DMA_INTSTS_C1BUSY
+ DMA_INTSTS_C0BUSY
+ * @retval interrupt status.
+ */
+uint8_t DMA_GetINTStatus(uint32_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_DMA_INTFLAGR(INTMask));
+
+ if (DMA->STS&INTMask)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Clears DMA interrupt status.
+ * @param INTMask: can use the '|' operator
+ DMA_INTSTS_C3DA
+ DMA_INTSTS_C2DA
+ DMA_INTSTS_C1DA
+ DMA_INTSTS_C0DA
+ DMA_INTSTS_C3FE
+ DMA_INTSTS_C2FE
+ DMA_INTSTS_C1FE
+ DMA_INTSTS_C0FE
+ DMA_INTSTS_C3PE
+ DMA_INTSTS_C2PE
+ DMA_INTSTS_C1PE
+ DMA_INTSTS_C0PE
+ * @retval None
+ */
+void DMA_ClearINTStatus(uint32_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_DMA_INTFLAGC(INTMask));
+
+ DMA->STS = INTMask;
+}
+
+/**
+ * @brief Enables or disables DMA channel.
+ * @param Channel:
+ DMA_CHANNEL_0
+ DMA_CHANNEL_1
+ DMA_CHANNEL_2
+ DMA_CHANNEL_3
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void DMA_Cmd(uint32_t Channel, uint32_t NewState)
+{
+ __IO uint32_t *addr;
+
+ /* Check parameters */
+ assert_parameters(IS_DMA_CHANNEL(Channel));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ addr = &DMA->C0CTL + Channel*4;
+
+ if (NewState == ENABLE)
+ *addr |= DMA_CCTL_EN;
+ else
+ *addr &= ~DMA_CCTL_EN;
+}
+
+/**
+ * @brief Enables or disables AES encrypt/decrypt function of DMA channel3.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void DMA_AESCmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ DMA->C3CTL |= DMA_CCTL_AESEN;
+ else
+ DMA->C3CTL &= ~DMA_CCTL_AESEN;
+}
+
+/**
+ * @brief Stops DMA transmit.
+ * @param Channel:
+ DMA_CHANNEL_0
+ DMA_CHANNEL_1
+ DMA_CHANNEL_2
+ DMA_CHANNEL_3
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void DMA_StopTransmit(uint32_t Channel, uint32_t NewState)
+{
+ __IO uint32_t *addr;
+
+ /* Check parameters */
+ assert_parameters(IS_DMA_CHANNEL(Channel));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ addr = &DMA->C0CTL + Channel*4;
+
+ if (NewState == ENABLE)
+ *addr |= DMA_CCTL_STOP;
+ else
+ *addr &= ~DMA_CCTL_STOP;
+}
+
+/**
+ * @brief Gets current frame transferred length.
+ * @param Channel:
+ DMA_CHANNEL_0
+ DMA_CHANNEL_1
+ DMA_CHANNEL_2
+ DMA_CHANNEL_3
+ * @retval Current frame transferred length.
+ */
+uint8_t DMA_GetFrameLenTransferred(uint32_t Channel)
+{
+ __IO uint32_t *addr;
+
+ /* Check parameters */
+ assert_parameters(IS_DMA_CHANNEL(Channel));
+
+ addr = &DMA->C0LEN + Channel*4;
+ return ((*addr&0xFF00)>>8);
+}
+
+/**
+ * @brief Gets current package transferred length.
+ * @param Channel:
+ DMA_CHANNEL_0
+ DMA_CHANNEL_1
+ DMA_CHANNEL_2
+ DMA_CHANNEL_3
+ * @retval Current package transferred length.
+ */
+uint8_t DMA_GetPackLenTransferred(uint32_t Channel)
+{
+ __IO uint32_t *addr;
+
+ /* Check parameters */
+ assert_parameters(IS_DMA_CHANNEL(Channel));
+
+ addr = &DMA->C0LEN + Channel*4;
+ return (*addr&0xFF);
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_flash.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_flash.c
new file mode 100644
index 0000000000000000000000000000000000000000..1bea70d7b9cc6404a6ca99e724988bf646f50a64
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_flash.c
@@ -0,0 +1,441 @@
+/**
+ ******************************************************************************
+ * @file lib_flash.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief FLASH library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_flash.h"
+#include "lib_clk.h"
+
+/* FLASH Keys */
+#define FLASH_PASS_KEY 0x55AAAA55
+#define FLASH_SERASE_KEY 0xAA5555AA
+#define FLASH_CERASE_KEY 0xAA5555AA
+#define FLASH_DSTB_KEY 0xAA5555AA
+#define FLASH_ICE_KEY 0xAA5555AA
+
+#define FLASH_MODE_MASK 0x1F3
+
+/**
+ * @brief Initializes FLASH mode.
+ * @param CSMode:
+ FLASH_CSMODE_DISABLE
+ FLASH_CSMODE_ALWAYSON
+ FLASH_CSMODE_TMR2OF
+ FLASH_CSMODE_RTC
+ * @retval None
+ */
+void FLASH_Init(uint32_t CSMode)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_FLASH_CSMODE(CSMode));
+
+ tmp = FLASH->CTRL;
+ tmp &= ~FLASH_MODE_MASK;
+ tmp |= CSMode;
+ FLASH->CTRL = tmp;
+}
+
+/**
+ * @brief Enables or disables FLASH interrupt.
+ * @param IntMask:
+ FLASH_INT_CS
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_FLASH_INT(IntMask));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = FLASH->CTRL;
+ tmp &= ~IntMask;
+ if (NewState == ENABLE)
+ {
+ tmp |= IntMask;
+ }
+ FLASH->CTRL = tmp;
+}
+
+/**
+ * @brief Initializes FLASH 1USCYCLE.
+ * @param None
+ * @retval None
+ */
+void FLASH_CycleInit(void)
+{
+ uint32_t hclk;
+
+ hclk = CLK_GetHCLKFreq();
+
+ if (hclk > 1000000)
+ MISC2->FLASHWC = (hclk/1000000)<<8;
+ else
+ MISC2->FLASHWC = 0;
+}
+
+/**
+ * @brief Erases a specified FLASH sector.
+ * @param SectorAddr: Erase start address.
+ * @retval None
+ */
+void FLASH_SectorErase(uint32_t SectorAddr)
+{
+ /* Check parameters */
+ assert_parameters(IS_FLASH_ADDRESS(SectorAddr));
+
+ /* Unlock flash */
+ FLASH->PASS = FLASH_PASS_KEY;
+
+ FLASH->PGADDR = SectorAddr;
+ FLASH->SERASE = FLASH_SERASE_KEY;
+ while (FLASH->SERASE != 0);
+
+ /* Lock flash */
+ FLASH->PASS = 0;
+}
+
+/**
+ * @brief Erases chip.
+ * @param None.
+ * @retval None
+ */
+void FLASH_ChipErase(void)
+{
+ /* Unlock flash */
+ FLASH->PASS = FLASH_PASS_KEY;
+
+ FLASH->PGADDR = 0;
+ FLASH->CERASE = FLASH_CERASE_KEY;
+ while (FLASH->CERASE != 0);
+
+ /* Lock flash */
+ FLASH->PASS = 0;
+}
+
+/**
+ * @brief Programs n word at a specified start address.
+ * @param Addr: program start address
+ WordBuffer: word's buffer pointer to write
+ Length: The length of WordBuffer
+ * @retval None
+ */
+void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length)
+{
+ uint32_t i;
+
+ /* Check parameters */
+ assert_parameters(IS_FLASH_ADRRW(Addr));
+
+ FLASH->PGADDR = Addr;
+ /* Unlock flash */
+ FLASH->PASS = FLASH_PASS_KEY;
+
+ for (i=0; iPGDATA = *(WordBuffer++);
+ while (FLASH->STS != 1);
+ }
+
+ /* Lock flash */
+ FLASH->PASS = 0;
+}
+
+/**
+ * @brief Programs n half-word at a specified start address.
+ * @param Addr: program start address
+ HWordBuffer: half-word's buffer pointer to write
+ Length: The length of HWordBuffer
+ * @retval None
+ */
+void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length)
+{
+ uint32_t i;
+
+ /* Check parameters */
+ assert_parameters(IS_FLASH_ADRRHW(Addr));
+
+ FLASH->PGADDR = Addr;
+ /* Unlock flash */
+ FLASH->PASS = FLASH_PASS_KEY;
+
+ for (i=0; iPGDATA)) = *(HWordBuffer++);
+ else
+ *((__IO uint16_t*)(&FLASH->PGDATA ) + 1) = *(HWordBuffer++);
+ while (FLASH->STS != 1);
+ }
+
+ /* Lock flash */
+ FLASH->PASS = 0;
+}
+
+/**
+ * @brief Programs n byte at a specified start address.
+ * @param Addr: program start address
+ ByteBuffer: byte's buffer pointer to write
+ Length: The length of ByteBuffer
+ * @retval None
+ */
+void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length)
+{
+ uint32_t i;
+
+ /* Check parameters */
+ assert_parameters(IS_FLASH_ADDRESS(Addr));
+
+ FLASH->PGADDR = Addr;
+ /* Unlock flash */
+ FLASH->PASS = FLASH_PASS_KEY;
+
+ for (i=0; iPGDATA)) = *(ByteBuffer++);
+ else if (((Addr + i)&0x3) == 1)
+ *((__IO uint8_t*)(&FLASH->PGDATA) + 1) = *(ByteBuffer++);
+ else if (((Addr + i)&0x3) == 2)
+ *((__IO uint8_t*)(&FLASH->PGDATA) + 2) = *(ByteBuffer++);
+ else
+ *((__IO uint8_t*)(&FLASH->PGDATA) + 3) = *(ByteBuffer++);
+ while (FLASH->STS != 1);
+ }
+
+ /* Lock flash */
+ FLASH->PASS = 0;
+}
+
+/**
+ * @brief Enables FLASH read protection.
+ * @param Block: can use the '|' operator.
+ FLASH_BLOCK_0 ~ FLASH_BLOCK_31 or FLASH_BLOCK_ALL
+ * @retval None
+ */
+void FLASH_SetReadProtection(uint32_t Block)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_FLASH_RWBLOCK(Block));
+
+ tmp = *(volatile unsigned int *)(0x0007FC00);
+ tmp &= ~Block;
+
+ /* Unlock flash */
+ FLASH->PASS = FLASH_PASS_KEY;
+
+ FLASH->PGADDR = 0x7FC00;
+ FLASH->PGDATA = tmp;
+ while (FLASH->STS != 1);
+ /* Lock flash */
+ FLASH->PASS = 0;
+
+ tmp = *(volatile unsigned int *)(0x0007FC00);
+}
+
+/**
+ * @brief Enables or disables FLASH write protection.
+ * @param Block: can use the '|' operator.
+ FLASH_BLOCK_0 ~ FLASH_BLOCK_31 or FLASH_BLOCK_ALL
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void FLASH_WriteProtection(uint32_t Block, uint32_t NewState)
+{
+ uint32_t wrprot;
+
+ /* Check parameters */
+ assert_parameters(IS_FLASH_RWBLOCK(Block));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ wrprot = FLASH->WRPROT;
+
+ if (NewState == ENABLE)
+ {
+ wrprot |= Block;
+ }
+ else
+ {
+ wrprot &= ~Block;
+ }
+ FLASH->WRPROT = wrprot;
+}
+
+/**
+ * @brief Enables or disables ICE protection.
+ * @param NewState:
+ ENABLE(ICE protection is successful when 0x7FC08 is 0xFFFFFFFF )
+ DISABLE
+ * @retval None.
+ */
+void FLASH_ICEProtection(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ /* Unlock flash */
+ FLASH->PASS = FLASH_PASS_KEY;
+
+ FLASH->PGADDR = 0x7FC08;
+ FLASH->PGDATA = 0x0A;
+ while (FLASH->STS != 1);
+ /* Lock flash */
+ FLASH->PASS = 0;
+ }
+ else
+ {
+ FLASH_SectorErase(0x7FFFF);
+ CORTEX_NVIC_SystemReset();
+ }
+}
+
+/**
+ * @brief Gets read/write/erase protection status.
+ * @param Block:
+ FLASH_BLOCK_0 ~ FLASH_BLOCK_31
+ Operation:
+ FLASH_READ
+ FLASH_WRITE
+ * @retval
+ When Operation is FLASH_READ:
+ 1: Read protection enabled.
+ 0: Read protection disabled.
+ When Operation is FLASH_WRITE:
+ 1: Write/erase protection enabled.
+ 0: Write/erase protection disabled.
+ */
+uint8_t FLASH_GetProtectionStatus(uint32_t Block, uint32_t Operation)
+{
+ /* Check parameters */
+ assert_parameters(IS_FLASH_BLOCK(Block));
+ assert_parameters(IS_FLASH_OPERATION(Operation));
+
+ if (Operation == FLASH_READ)
+ {
+ if (FLASH->RDPROT & Block)
+ return 1;
+ else
+ return 0;
+ }
+ else
+ {
+ if (FLASH->WRPROT & Block)
+ return 1;
+ else
+ return 0;
+ }
+}
+
+/**
+ * @brief Gets read/write/erase protection status.
+ * @param Operation:
+ FLASH_READ
+ FLASH_WRITE
+ * @retval Read or write/erase protection status.
+ */
+uint32_t FLASH_GetAllProtectionStatus(uint32_t Operation)
+{
+ if (Operation == FLASH_READ)
+ {
+ return FLASH->RDPROT;
+ }
+ else
+ {
+ return FLASH->WRPROT;
+ }
+}
+
+/**
+ * @brief Sets checksum range.
+ * @param AddrStart: checksum start address
+ AddrEnd: checksum end address
+ * @retval None
+ */
+void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd)
+{
+ /* Check parameters */
+ assert_parameters(IS_FLASH_CHECKSUMADDR(AddrStart,AddrEnd));
+
+ FLASH->CSSADDR = AddrStart;
+ FLASH->CSEADDR = AddrEnd;
+}
+
+/**
+ * @brief Sets checksum compare value.
+ * @param Checksum: checksum compare value
+ * @retval None
+ */
+void FLASH_SetCheckSumCompValue(uint32_t Checksum)
+{
+ FLASH->CSCVALUE = Checksum;
+}
+
+/**
+ * @brief Gets FLASH checksum value.
+ * @param None
+ * @retval Checksum
+ */
+uint32_t FLASH_GetCheckSum(void)
+{
+ return FLASH->CSVALUE;
+}
+
+/**
+ * @brief Gets FLASH interrupt status.
+ * @param IntMask:
+ FLASH_INT_CS
+ * @retval 1: interrupt status set
+ 0: interrupt status reset
+ */
+uint8_t FLASH_GetINTStatus(uint32_t IntMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_FLASH_INT(IntMask));
+
+ if (FLASH->INTSTS & FLASH_INTSTS_CSERR)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears FLASH interrupt status.
+ * @param IntMask:
+ FLASH_INT_CS
+ * @retval None
+ */
+void FLASH_ClearINTStatus(uint32_t IntMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_FLASH_INT(IntMask));
+
+ if (IntMask == FLASH_INT_CS)
+ {
+ FLASH->INTSTS = FLASH_INTSTS_CSERR;
+ }
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_gpio.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_gpio.c
new file mode 100644
index 0000000000000000000000000000000000000000..5ff418b647790fd6410b4f0d66618e44f178007d
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_gpio.c
@@ -0,0 +1,486 @@
+/**
+ ******************************************************************************
+ * @file lib_gpio.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief GPIO library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_gpio.h"
+
+
+/**
+ * @brief Initializes GPIO.
+ * @param GPIOx: GPIOB~GPIOF
+ InitStruct:GPIO configuration.
+ GPIO_Pin: can use the '|' operator
+ GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All
+ GPIO_Mode:
+ GPIO_MODE_INPUT
+ GPIO_MODE_OUTPUT_CMOS
+ GPIO_MODE_OUTPUT_OD
+ GPIO_MODE_INOUT_OD
+ GPIO_MODE_INOUT_CMOS
+ GPIO_MODE_FORBIDDEN
+ * @retval None
+ */
+void GPIOBToF_Init(GPIO_Type *GPIOx, GPIO_InitType *InitStruct)
+{
+ uint32_t tmp_reg1, tmp_reg2;
+
+ /* Check parameters */
+ assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_parameters(IS_GPIO_PIN(InitStruct->GPIO_Pin));
+ assert_parameters(IS_GPIO_MODE(InitStruct->GPIO_Mode));
+
+ /* Configure ATT */
+ if (InitStruct->GPIO_Mode & 0x2U)
+ {
+ tmp_reg1 = GPIOx->ATT;
+ tmp_reg1 &= ~InitStruct->GPIO_Pin;
+ if (InitStruct->GPIO_Mode & 0x1U)
+ {
+ tmp_reg1 |= InitStruct->GPIO_Pin;
+ }
+ GPIOx->ATT = tmp_reg1;
+ }
+
+ /* Configure output/input mode */
+ tmp_reg1 = GPIOx->OEN;
+ tmp_reg1 &= ~InitStruct->GPIO_Pin;
+ tmp_reg2 = GPIOx->IE;
+ tmp_reg2 &= ~InitStruct->GPIO_Pin;
+ if (InitStruct->GPIO_Mode & 0x8U)
+ {
+ tmp_reg2 |= InitStruct->GPIO_Pin;
+ }
+ if (InitStruct->GPIO_Mode & 0x4U)
+ {
+ tmp_reg1 |= InitStruct->GPIO_Pin;
+ }
+ GPIOx->OEN = tmp_reg1;
+ GPIOx->IE = tmp_reg2;
+}
+
+/**
+ * @brief Initializes GPIOA.
+ * @param GPIOx: GPIOA
+ InitStruct:GPIO configuration.
+ GPIO_Pin: can use the '|' operator
+ GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All
+ GPIO_Mode:
+ GPIO_MODE_INPUT
+ GPIO_MODE_OUTPUT_CMOS
+ GPIO_MODE_OUTPUT_OD
+ GPIO_MODE_INOUT_OD
+ GPIO_MODE_INOUT_CMOS
+ GPIO_MODE_FORBIDDEN
+ * @retval None
+ */
+void GPIOA_Init(GPIOA_Type *GPIOx, GPIO_InitType *InitStruct)
+{
+ uint32_t tmp_reg1, tmp_reg2;
+
+ /* Check parameters */
+ assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
+ assert_parameters(IS_GPIO_PIN(InitStruct->GPIO_Pin));
+ assert_parameters(IS_GPIO_MODE(InitStruct->GPIO_Mode));
+
+ /* Configure ATT */
+ if (InitStruct->GPIO_Mode & 0x2U)
+ {
+ tmp_reg1 = GPIOx->ATT;
+ tmp_reg1 &= ~InitStruct->GPIO_Pin;
+ if (InitStruct->GPIO_Mode & 0x1U)
+ {
+ tmp_reg1 |= InitStruct->GPIO_Pin;
+ }
+ GPIOx->ATT = tmp_reg1;
+ }
+
+ /* Configure output/input mode */
+ tmp_reg1 = GPIOx->OEN;
+ tmp_reg1 &= ~InitStruct->GPIO_Pin;
+ tmp_reg2 = GPIOx->IE;
+ tmp_reg2 &= ~InitStruct->GPIO_Pin;
+ if (InitStruct->GPIO_Mode & 0x8U)
+ {
+ tmp_reg2 |= InitStruct->GPIO_Pin;
+ }
+ if (InitStruct->GPIO_Mode & 0x4U)
+ {
+ tmp_reg1 |= InitStruct->GPIO_Pin;
+ }
+ GPIOx->OEN = tmp_reg1;
+ GPIOx->IE = tmp_reg2;
+}
+
+/**
+ * @brief Reads input data register bit.
+ * @param GPIOx: GPIOB~GPIOF
+ GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15.
+ * @retval input pin value.
+ */
+uint8_t GPIOBToF_ReadInputDataBit(GPIO_Type *GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_parameters(IS_GPIO_PINR(GPIO_Pin));
+
+ if (GPIOx->STS & GPIO_Pin)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Reads input data register bit.
+ * @param GPIOx: GPIOA
+ GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15.
+ * @retval input pin value.
+ */
+uint8_t GPIOA_ReadInputDataBit(GPIOA_Type *GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
+ assert_parameters(IS_GPIO_PINR(GPIO_Pin));
+
+ if (GPIOx->STS & GPIO_Pin)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Reads input data register.
+ * @param GPIOx: GPIOB~GPIOF
+ * @retval input port value.
+ */
+uint16_t GPIOBToF_ReadInputData(GPIO_Type* GPIOx)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ return GPIOx->STS;
+}
+
+/**
+ * @brief Reads input data register.
+ * @param GPIOx: GPIOA
+ * @retval input port value.
+ */
+uint16_t GPIOA_ReadInputData(GPIOA_Type* GPIOx)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
+
+ return GPIOx->STS;
+}
+
+/**
+ * @brief Reads output data register bit.
+ * @param GPIOx: GPIOB~GPIOF
+ GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15
+ * @retval output pin value.
+ */
+uint8_t GPIOBToF_ReadOutputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_parameters(IS_GPIO_PINR(GPIO_Pin));
+
+ if (GPIOx->DAT & GPIO_Pin)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Reads output data register bit.
+ * @param GPIOx: GPIOA
+ GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15
+ * @retval output pin value.
+ */
+uint8_t GPIOA_ReadOutputDataBit(GPIOA_Type* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
+ assert_parameters(IS_GPIO_PINR(GPIO_Pin));
+
+ if (GPIOx->DAT & GPIO_Pin)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Reads output data register.
+ * @param GPIOx: GPIOB~GPIOF
+ * @retval Output port value.
+ */
+uint16_t GPIOBToF_ReadOutputData(GPIO_Type* GPIOx)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ return GPIOx->DAT;
+}
+
+/**
+ * @brief Reads output data register.
+ * @param GPIOx: GPIOA
+ * @retval Output port value.
+ */
+uint16_t GPIOA_ReadOutputData(GPIOA_Type* GPIOx)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
+
+ return GPIOx->DAT;
+}
+
+/**
+ * @brief Writes output data register bit.
+ * @param DATx: GPIO_A~GPIO_F
+ PinNum: 0~15
+ val:value write to register bit.
+ * @retval None.
+ */
+void GPIO_WriteBit(GPIO_DATInitType* DATx, uint8_t PinNum, uint8_t val)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_DAT(DATx));
+ assert_parameters(IS_GPIO_PINNUM(PinNum));
+ assert_parameters(IS_GPIO_BITVAL(val));
+
+ DATx->DATBitBand[PinNum] = val;
+}
+/**
+ * @brief Write output data register bit.
+ * @param GPIOx: GPIOB~GPIOF
+ GPIO_Pin: can use the ‘|’ operator
+ GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All
+ val:value write to register bit.
+ * @retval None.
+ */
+void GPIOBToF_WriteBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin, uint8_t val)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_parameters(IS_GPIO_PIN(GPIO_Pin));
+ assert_parameters(IS_GPIO_BITVAL(val));
+
+ if (val == 1)
+ {
+ GPIOx->DAT |= GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->DAT &= ~GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Write output data register bit.
+ * @param GPIOx: GPIOA
+ GPIO_Pin: can use the ‘|’ operator
+ GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All
+ val:value write to register bit.
+ * @retval None.
+ */
+void GPIOA_WriteBit(GPIOA_Type* GPIOx, uint16_t GPIO_Pin, uint8_t val)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
+ assert_parameters(IS_GPIO_PIN(GPIO_Pin));
+ assert_parameters(IS_GPIO_BITVAL(val));
+
+ if (val == 1)
+ {
+ GPIOx->DAT |= GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->DAT &= ~GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Writes output data register.
+ * @param GPIOx: GPIOB~GPIOF
+ val:value write to register.
+ * @retval None.
+ */
+void GPIOBToF_Write(GPIO_Type* GPIOx, uint16_t val)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ GPIOx->DAT = val;
+}
+
+/**
+ * @brief Writes output data register.
+ * @param GPIOx: GPIOA
+ val:value write to register.
+ * @retval None.
+ */
+void GPIOA_Write(GPIOA_Type* GPIOx, uint16_t val)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
+
+ GPIOx->DAT = val;
+}
+
+/**
+ * @brief Enables or disables GPIO AF functiuon.
+ * @param GPIOx:GPIOB GPIOE
+ GPIO_AFx:
+ GPIOB_AF_PLLHDIV
+ GPIOB_AF_PLLLOUT
+ GPIOB_AF_OSC
+ GPIOE_AF_CMP1O
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void GPIOBToF_AFConfig(GPIO_Type* GPIOx, uint32_t GPIO_AFx, uint8_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIOAF_ALL_INSTANCE(GPIOx));
+ assert_parameters(IS_GPIO_GPIOAF(GPIO_AFx));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (GPIOx == GPIOB)
+ {
+ if (NewState == ENABLE)
+ {
+ GPIOAF->IOB_SEL |= GPIO_AFx;
+ }
+ else
+ {
+ GPIOAF->IOB_SEL &= ~GPIO_AFx;
+ }
+ }
+ if (GPIOx == GPIOE)
+ {
+ if (NewState == ENABLE)
+ {
+ GPIOAF->IOE_SEL |= GPIO_AFx;
+ }
+ else
+ {
+ GPIOAF->IOE_SEL &= ~GPIO_AFx;
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables GPIOA AF function.
+ * @param PMUIO_AFx:can use the '|' operator
+ PMUIO7_AF_PLLDIV
+ PMUIO6_AF_CMP2O
+ PMUIO3_AF_PLLDIV
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_PMUIOAF(PMUIO_AFx));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ GPIOA->SEL |= PMUIO_AFx;
+ }
+ else
+ {
+ GPIOA->SEL &= ~PMUIO_AFx;
+ }
+}
+
+/**
+ * @brief Enables or disables GPIO pin remap function.
+ * @param GPIO_Remap:
+ GPIO_REMAP_I2C
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_REMAP(GPIO_Remap));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ GPIOAF->IO_MISC |= GPIO_Remap;
+ }
+ else
+ {
+ GPIOAF->IO_MISC &= ~GPIO_Remap;
+ }
+}
+
+/**
+ * @brief Configures GPIO PLLDIV function.
+ * @param Divider:
+ GPIO_PLLDIV_1
+ GPIO_PLLDIV_2
+ GPIO_PLLDIV_4
+ GPIO_PLLDIV_8
+ GPIO_PLLDIV_16
+ * @retval None.
+ */
+void GPIO_PLLDIVConfig(uint32_t Divider)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_GPIO_PLLDIV(Divider));
+
+ tmp = GPIOAF->IO_MISC;
+ tmp &= ~GPIOAF_IO_MISC_PLLHDIV;
+ tmp |= Divider;
+ GPIOAF->IO_MISC = tmp;
+}
+
+/**
+ * @brief Enables or disables GPIOA de-glitch circuit.
+ * @param GPIO_Pin: can use the '|' operator
+ GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void GPIOA_DeGlitchCmd(uint16_t GPIO_Pin, uint8_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_PIN(GPIO_Pin));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ /*IOA wake-up signal will go through de-glitch circuit.*/
+ if (NewState == ENABLE)
+ {
+ GPIOA->IOANODEG &= ~GPIO_Pin;
+ }
+ /*IOA wake-up signal will not go through de-glitch circuit.*/
+ else
+ {
+ GPIOA->IOANODEG |= GPIO_Pin;
+ }
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_i2c.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_i2c.c
new file mode 100644
index 0000000000000000000000000000000000000000..304528fc2d3250471a4026aee67e29c468b7921b
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_i2c.c
@@ -0,0 +1,694 @@
+/**
+ ******************************************************************************
+ * @file lib_i2c.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief IIC library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_i2c.h"
+
+//registers default reset values
+#define I2C_ADDR_RSTValue 0
+#define I2C_CTRL_RSTValue 0
+#define I2C_CTRL2_RSTValue 0
+
+/* Private Functions -------------------------------------------------------- */
+static uint16_t I2C_CheckState(uint8_t State);
+static void I2C_SendStart(void);
+static void I2C_SendRestart(void);
+static void I2C_SendByte(uint8_t dat);
+static void I2C_SendStop(void);
+static uint8_t I2C_ReceiveByte(void);
+static void I2C_ClearBus(uint32_t remap);
+static void I2C_WaitForCrossPage(uint8_t sla);
+
+/**
+ * @brief Checks required state.
+ * @param State:
+ Required state.
+ * @retval 0: state OK
+ !0: state Error, [15:8]Required status code, [7:0] real status code.
+ */
+static uint16_t I2C_CheckState(uint8_t State)
+{
+ uint16_t ret;
+ if (I2C_GetStatusCode() != State)
+ {
+ ret = (State<<8)|(I2C_GetStatusCode());
+ return ret;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Sends start signal.
+ * @param None
+ * @retval None
+ */
+static void I2C_SendStart(void)
+{
+ I2C_GenerateSTART(ENABLE);
+ while (I2C_GetINTStatus() == 0);
+ I2C_GenerateSTART(DISABLE);
+}
+
+/**
+ * @brief Sends restart signal.
+ * @param None
+ * @retval None
+ */
+static void I2C_SendRestart(void)
+{
+ I2C_GenerateSTART(ENABLE);
+ I2C_ClearINTStatus();
+ while (I2C_GetINTStatus() == 0);
+ I2C_GenerateSTART(DISABLE);
+}
+
+/**
+ * @brief Sends stop signal.
+ * @param None
+ * @retval None
+ */
+static void I2C_SendStop(void)
+{
+ I2C_GenerateSTOP(ENABLE);
+ I2C_ClearINTStatus();
+ I2C_GenerateSTOP(DISABLE);
+}
+
+/**
+ * @brief Sends data.
+ * @param dat:data to send.
+ * @retval None
+ */
+static void I2C_SendByte(uint8_t dat)
+{
+ I2C_SendData(dat);
+ I2C_ClearINTStatus();
+ while (I2C_GetINTStatus() == 0);
+}
+
+/**
+ * @brief Receives byte.
+ * @param None
+ * @retval Byte received
+ */
+static uint8_t I2C_ReceiveByte(void)
+{
+ I2C_ClearINTStatus();
+ while (I2C_GetINTStatus() == 0);
+ return I2C_ReceiveData();
+}
+
+/**
+ * @brief Waits until cross page operation done.
+ * @param None
+ * @retval None
+ */
+static void I2C_WaitForCrossPage(uint8_t sla)
+{
+ do
+ {
+ I2C_SendRestart();
+ I2C_SendByte(sla); //device address
+ }while (I2C_GetStatusCode() !=0x18);
+ I2C_SendStop(); //stop
+}
+
+/**
+ * @brief Clears bus.
+ * @param None
+ * @retval None
+ */
+static void I2C_ClearBus(uint32_t remap)
+{
+ __IO uint8_t i, j;
+
+ if (remap) // I2C remap enable, SCL IOC4
+ {
+ GPIOC->DAT &= ~BIT4;
+ GPIOC->ATT |= BIT4;
+ GPIOC->OEN &= ~BIT4;
+ for (i=0; i<9; i++)
+ {
+ GPIOC->DAT |= BIT4;
+ for (j=0; j<100; j++)
+ __NOP();
+ GPIOC->DAT &= ~BIT4;
+ for (j=0; j<100; j++)
+ __NOP();
+ }
+ GPIOC->DAT |= BIT4;
+ GPIOC->OEN |= BIT4;
+ GPIOC->IE &= ~BIT4;
+ }
+ else // I2C remap disable, SCL IOB13
+ {
+ GPIOB->DAT &= ~BIT13;
+ GPIOB->ATT |= BIT13;
+ GPIOB->OEN &= ~BIT13;
+ for (i=0; i<9; i++)
+ {
+ GPIOB->DAT |= BIT13;
+ for (j=0; j<100; j++)
+ __NOP();
+ GPIOB->DAT &= ~BIT13;
+ for (j=0; j<100; j++)
+ __NOP();
+ }
+ GPIOB->DAT |= BIT13;
+ GPIOB->OEN |= BIT13;
+ GPIOB->IE &= ~BIT13;
+ }
+}
+
+/* Exported Functions ------------------------------------------------------- */
+
+/**
+ * @brief Initializes the I2C peripheral registers to their default reset values.
+ * @param remap: I2C_REMAP_ENABLE or I2C_REMAP_DISABLE
+ * @retval None
+ */
+void I2C_DeInit(uint32_t remap)
+{
+ I2C->CTRL &= ~I2C_CTRL_EN;
+
+ I2C->ADDR = I2C_ADDR_RSTValue;
+ I2C->CTRL = I2C_CTRL_RSTValue;
+ I2C->CTRL2 = I2C_CTRL2_RSTValue;
+
+ I2C_ClearBus(remap);
+}
+
+/**
+ * @brief Fills each InitStruct member with its default value.
+ * @param InitStruct: pointer to an I2C_InitType structure which will be initialized.
+ * @retval None
+ */
+void I2C_StructInit(I2C_InitType *InitStruct)
+{
+ /*--------------- Reset I2C init structure parameters values ---------------*/
+ /* Initialize the AssertAcknowledge member */
+ InitStruct->AssertAcknowledge = I2C_ASSERTACKNOWLEDGE_DISABLE;
+ /* Initialize the ClockSource member */
+ InitStruct->ClockSource = I2C_CLOCKSOURCE_APBD256;
+ /* Initialize the GeneralCallAck member */
+ InitStruct->GeneralCallAck = I2C_GENERALCALLACK_DISABLE;
+ /* Initialize the SlaveAddr member */
+ InitStruct->SlaveAddr = 0;
+}
+
+/**
+ * @brief Initializes I2C.
+ * @param InitStruct: I2C configuration.
+ SlaveAddr: Own I2C slave address (7 bit)
+ GeneralCallAck:
+ I2C_GENERALCALLACK_ENABLE
+ I2C_GENERALCALLACK_DISABLE
+ AssertAcknowledge:
+ I2C_ASSERTACKNOWLEDGE_ENABLE
+ I2C_ASSERTACKNOWLEDGE_DISABLE
+ ClockSource:
+ I2C_CLOCKSOURCE_APBD256
+ I2C_CLOCKSOURCE_APBD224
+ I2C_CLOCKSOURCE_APBD192
+ I2C_CLOCKSOURCE_APBD160
+ I2C_CLOCKSOURCE_APBD960
+ I2C_CLOCKSOURCE_APBD120
+ I2C_CLOCKSOURCE_APBD60
+ I2C_CLOCKSOURCE_TIM3OFD8
+ * @retval None.
+ */
+void I2C_Init(I2C_InitType *InitStruct)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_I2C_GC(InitStruct->GeneralCallAck));
+ assert_parameters(IS_I2C_AA(InitStruct->AssertAcknowledge));
+ assert_parameters(IS_I2C_CLKSRC(InitStruct->ClockSource));
+
+ I2C->ADDR = InitStruct->SlaveAddr\
+ |InitStruct->GeneralCallAck;
+ tmp = I2C->CTRL;
+ tmp &= ~(I2C_CTRL_CR\
+ |I2C_CTRL_AA);
+ tmp |= (InitStruct->ClockSource\
+ |InitStruct->AssertAcknowledge);
+ I2C->CTRL = tmp;
+}
+
+/**
+ * @brief Enables or disables I2C interrupt.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void I2C_INTConfig(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ I2C->CTRL2 |= I2C_CTRL2_INTEN;
+ else
+ I2C->CTRL2 &= ~I2C_CTRL2_INTEN;
+}
+
+/**
+ * @brief Gets I2C interrupt status.
+ * @param None
+ * @retval Interrupt status.
+ */
+uint8_t I2C_GetINTStatus(void)
+{
+ if (I2C->CTRL&I2C_CTRL_SI)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Clears I2C interrupt status.
+ * @param None
+ * @retval None.
+ */
+void I2C_ClearINTStatus(void)
+{
+ I2C->CTRL &= ~I2C_CTRL_SI;
+}
+
+/**
+ * @brief Reads a packge of data from slave device.
+ * @param InitStruct: I2C_WRType
+ SlaveAddr : Slave device address
+ SubAddress : start of slave device sub-address
+ PageRange : maximum range of page to Read operation
+ pBuffer : Read data pointer
+ Length : sum of Read datas
+ SubAddrType:
+ I2C_SUBADDR_1BYTE (Slave device sub-address type: 1 byte)
+ I2C_SUBADDR_2BYTE (Slave device sub-address type: 2 bytes)
+ I2C_SUBADDR_OTHER (Slave device sub-address type: othres)
+ * @retval 0: true
+ £¡0£ºstatus code
+ bit15~8 status code(true)
+ bit7~0 status code(false)
+ */
+uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct)
+{
+ uint32_t i;
+ uint16_t ret_val;
+
+ /* Check parameters */
+ assert_parameters(I2C_SUBADDR_TYPE(InitStruct->SubAddrType));
+
+ I2C_AssertAcknowledgeConfig(ENABLE); //Enable AA
+ /*-------------------------------- START -----------------------------------*/
+ I2C_SendStart();
+ ret_val = I2C_CheckState(0x08);
+ if (ret_val) return ret_val;
+
+ /*------------------------------ Send SLA+W --------------------------------*/
+ /* Slave device sub-address type: 1 byte */
+ if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE)
+ {
+ I2C_SendByte(InitStruct->SlaveAddr);
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte(InitStruct->SubAddress&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ /* Slave device sub-address type: 2 bytes */
+ if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE)
+ {
+ I2C_SendByte(InitStruct->SlaveAddr);
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte((InitStruct->SubAddress>>8)&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte(InitStruct->SubAddress&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ /* Slave device sub-address type: othres */
+ if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER)
+ {
+ if (InitStruct->PageRange < 256) // 8 + x
+ {
+ I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>7)&0xE));
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte(InitStruct->SubAddress&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ else // 16 + x
+ {
+ I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>15)&0xE));
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte((InitStruct->SubAddress>>8)&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte(InitStruct->SubAddress&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ }
+
+ /*------------------------------- Restart ----------------------------------*/
+ I2C_SendRestart(); //restart
+ ret_val = I2C_CheckState(0x10);
+ if (ret_val) return ret_val;
+
+ /*----------------------------- Send SLA+R ---------------------------------*/
+ /* Slave device sub-address type: othres */
+ if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER)
+ {
+ if (InitStruct->PageRange < 256) // 8 + x
+ I2C_SendByte(InitStruct->SlaveAddr|0x01|((InitStruct->SubAddress>>7)&0xE));
+ else // 16 + x
+ I2C_SendByte(InitStruct->SlaveAddr|0x01|((InitStruct->SubAddress>>15)&0xE));
+ }
+ else
+ I2C_SendByte(InitStruct->SlaveAddr|0x01);
+
+ ret_val = I2C_CheckState(0x40);
+ if (ret_val) return ret_val;
+
+ /*----------------------------- Read datas ---------------------------------*/
+ for (i=0; i<(InitStruct->Length-1); i++)
+ {
+ *InitStruct->pBuffer = I2C_ReceiveByte();
+ InitStruct->pBuffer++;
+ ret_val = I2C_CheckState(0x50);
+ if (ret_val) return ret_val;
+ }
+ /*-------------------- Read the last data, disable AA ----------------------*/
+ I2C_AssertAcknowledgeConfig(DISABLE);
+ *InitStruct->pBuffer = I2C_ReceiveByte();
+ ret_val = I2C_CheckState(0x58);
+ if (ret_val) return ret_val;
+ /*--------------------------------- Stop -----------------------------------*/
+ I2C_SendStop(); //stop
+ return 0;
+}
+
+/**
+ * @brief Writes a packge of data to slave device.
+ * @param InitStruct: I2C_WRType
+ SlaveAddr : Slave device address
+ SubAddress : start of slave device sub-address
+ PageRange : maximum range of page to write operation
+ pBuffer : write data pointer
+ Length : sum of write datas
+ SubAddrType:
+ I2C_SUBADDR_1BYTE (Slave device sub-address type: 1 byte)
+ I2C_SUBADDR_2BYTE (Slave device sub-address type: 2 bytes)
+ I2C_SUBADDR_OTHER (Slave device sub-address type: othres)
+ * @retval 0: true
+ £¡0£ºstatus code
+ bit15~8 status code(true)
+ bit7~0 status code(false)
+ */
+uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct)
+{
+ uint16_t ret_val;
+ uint32_t i;
+
+ /* Check parameters */
+ assert_parameters(I2C_SUBADDR_TYPE(InitStruct->SubAddrType));
+
+ I2C_AssertAcknowledgeConfig(ENABLE); //Enable AA
+ /*-------------------------------- START -----------------------------------*/
+ I2C_SendStart();
+ ret_val = I2C_CheckState(0x08);
+ if (ret_val) return ret_val;
+
+ /*------------------------------ Send SLA+W --------------------------------*/
+ /* Slave device sub-address type: 1 byte */
+ if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE)
+ {
+ I2C_SendByte(InitStruct->SlaveAddr);
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte(InitStruct->SubAddress&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ /* Slave device sub-address type: 2 bytes */
+ else if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE)
+ {
+ I2C_SendByte(InitStruct->SlaveAddr); //device address
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); //first word address
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte(InitStruct->SubAddress&0xFF); //second word address
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ /* Slave device sub-address type: othres */
+ else
+ {
+ if (InitStruct->PageRange < 256) // 8 + x
+ {
+ I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>7)&0xE));
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte(InitStruct->SubAddress&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ else // 16 + x
+ {
+ I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>15)&0xE));
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte((InitStruct->SubAddress>>8)&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte(InitStruct->SubAddress&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ }
+
+ /*----------------------------- Write datas --------------------------------*/
+ for (i=0; i<(InitStruct->Length); i++)
+ {
+ /* Reach the page boundary */
+ if ((i > 0) && ((InitStruct->SubAddress+i)%InitStruct->PageRange == 0))
+ {
+ I2C_SendStop();
+ I2C_WaitForCrossPage(InitStruct->SlaveAddr);
+ I2C_SendStart(); //start
+ ret_val = I2C_CheckState(0x08);
+ if (ret_val) return ret_val;
+ /* WriteAddr: 1 byte */
+ if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE)
+ {
+ I2C_SendByte(InitStruct->SlaveAddr);
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte((InitStruct->SubAddress+i)&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ /* WriteAddr: 2 byte */
+ if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE)
+ {
+ I2C_SendByte(InitStruct->SlaveAddr); //device address
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte(((InitStruct->SubAddress+i)>>8)&0xFF); //first word address
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte((InitStruct->SubAddress+i)&0xFF); //second word address
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ /* WriteAddr: (16 or 8)+x*/
+ if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER)
+ {
+ if (InitStruct->PageRange < 256) // 8 + x
+ {
+ I2C_SendByte(InitStruct->SlaveAddr|(((InitStruct->SubAddress+i)>>7)&0xE));
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte((InitStruct->SubAddress+i)&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ else // 16 + x
+ {
+ I2C_SendByte(InitStruct->SlaveAddr|(((InitStruct->SubAddress+i)>>15)&0xE));
+ ret_val = I2C_CheckState(0x18);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte(((InitStruct->SubAddress+i)>>8)&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+
+ I2C_SendByte((InitStruct->SubAddress+i)&0xFF);
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ }
+
+ I2C_SendByte(*InitStruct->pBuffer);
+ InitStruct->pBuffer++;
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ /* Not reaching the page boundary */
+ else
+ {
+ I2C_SendByte(*InitStruct->pBuffer);
+ InitStruct->pBuffer++;
+ ret_val = I2C_CheckState(0x28);
+ if (ret_val) return ret_val;
+ }
+ }
+
+ I2C_SendStop();
+ I2C_WaitForCrossPage(InitStruct->SlaveAddr);
+ return 0;
+}
+
+/**
+ * @brief Enables or disables I2C.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void I2C_Cmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ I2C->CTRL |= I2C_CTRL_EN;
+ else
+ I2C->CTRL &= ~I2C_CTRL_EN;
+}
+
+/* I2C Exported Functions Group5:
+ Others ------------------------------------*/
+
+/**
+ * @brief Configures sssert acknowledge.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void I2C_AssertAcknowledgeConfig(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ I2C->CTRL |= I2C_CTRL_AA;
+ else
+ I2C->CTRL &= ~I2C_CTRL_AA;
+}
+
+/**
+ * @brief Receives a byte data.
+ * @param None.
+ * @retval Data received.
+ */
+uint8_t I2C_ReceiveData(void)
+{
+ return I2C->DATA;
+}
+
+/**
+ * @brief Sends a byte data.
+ * @param Dat:data to transmit.
+ * @retval None
+ */
+void I2C_SendData(uint8_t Dat)
+{
+ I2C->DATA = Dat;
+}
+
+/**
+ * @brief Generates start signal.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void I2C_GenerateSTART(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ I2C->CTRL |= I2C_CTRL_STA;
+ else
+ I2C->CTRL &= ~I2C_CTRL_STA;
+}
+
+/**
+ * @brief Generates stop signal.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void I2C_GenerateSTOP(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ I2C->CTRL |= I2C_CTRL_STO;
+ else
+ I2C->CTRL &= ~I2C_CTRL_STO;
+}
+
+/**
+ * @brief Gets status code.
+ * @param None
+ * @retval status code.
+ */
+uint8_t I2C_GetStatusCode(void)
+{
+ return (I2C->STS&I2C_STS_STS);
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_iso7816.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_iso7816.c
new file mode 100644
index 0000000000000000000000000000000000000000..a8bf8b56f61e6cb1a858de7c88f71c0ee35e3a2d
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_iso7816.c
@@ -0,0 +1,405 @@
+/**
+ ******************************************************************************
+ * @file lib_iso7816.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief ISO7816 library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_iso7816.h"
+#include "lib_clk.h"
+
+//registers default reset values
+#define ISO7816_BAUDDIVL_RSTValue (0UL)
+#define ISO7816_BAUDDIVH_RSTValue (0UL)
+#define ISO7816_CFG_RSTValue (0x400)
+#define ISO7816_CLK_RSTValue (0UL)
+#define ISO7816_INFO_RC_MASK (0x3ECUL)
+
+
+/**
+ * @brief Initializes the ISO7816 peripheral registers to their default reset values.
+ * @param ISO7816x: ISO78160~ISO78161
+ * @retval None
+ */
+void ISO7816_DeInit(ISO7816_Type *ISO7816x)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+
+ ISO7816x->CFG &= ~ISO7816_CFG_EN;
+
+ ISO7816x->INFO = ISO7816_INFO_RC_MASK; /* clear interrupt flag */
+ ISO7816x->BAUDDIVH = ISO7816_BAUDDIVH_RSTValue;
+ ISO7816x->BAUDDIVL = ISO7816_BAUDDIVL_RSTValue;
+ ISO7816x->CFG = ISO7816_CFG_RSTValue;
+ ISO7816x->CLK = ISO7816_CLK_RSTValue;
+}
+
+
+/**
+ * @brief Fills each InitStruct member with its default value.
+ * @param InitStruct: pointer to an ISO7816_InitType structure which will be initialized.
+ * @retval None
+ */
+void ISO7816_StructInit(ISO7816_InitType *InitStruct)
+{
+ /*--------------- Reset ISO7816 init structure parameters values ---------------*/
+ /* Initialize the FirstBit member */
+ InitStruct->FirstBit = ISO7816_FIRSTBIT_MSB;
+ /* Initialize the Parity member */
+ InitStruct->Parity = ISO7816_PARITY_EVEN;
+ /* Initialize the Baudrate member */
+ InitStruct->Baudrate = 9600;
+ /* Initialize the TXRetry member */
+ InitStruct->TXRetry = ISO7816_TXRTY_0;
+ /* Initialize the RXACKLength member */
+ InitStruct->RXACKLength = ISO7816_RXACKLEN_2;
+ /* Initialize the TXNACKLength member */
+ InitStruct->TXNACKLength = ISO7816_TXNACKLEN_0;
+}
+
+/**
+ * @brief Initializes ISO7816.
+ * @param ISO7816x: ISO78160~ISO78161
+ Init_Struct:iso7816 configuration.
+ FirstBit:
+ ISO7816_FIRSTBIT_MSB
+ ISO7816_FIRSTBIT_LSB
+ Parity:
+ ISO7816_PARITY_EVEN
+ ISO7816_PARITY_ODD
+ Baudrate: baudrate value to configure, 200UL ~ 2625000UL
+ TXRetry:
+ ISO7816_TXRTY_0 ~ ISO7816_TXRTY_15
+ RXACKLength:
+ ISO7816_RXACKLEN_2
+ ISO7816_RXACKLEN_1
+ TXNACKLength:
+ ISO7816_TXNACKLEN_0
+ ISO7816_TXNACKLEN_1
+ ISO7816_TXNACKLEN_2
+ * @retval None
+ */
+void ISO7816_Init(ISO7816_Type *ISO7816x, ISO7816_InitType *Init_Struct)
+{
+ uint32_t tmp;
+ uint16_t div;
+ uint32_t pclk;
+
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+ assert_parameters(IS_ISO7816_FIRSTBIT(Init_Struct->FirstBit));
+ assert_parameters(IS_ISO7816_PARITY(Init_Struct->Parity));
+ assert_parameters(IS_ISO7816_BAUDRATE(Init_Struct->Baudrate));
+ assert_parameters(IS_ISO7816_TXRTY(Init_Struct->TXRetry));
+ assert_parameters(IS_ISO7816_RXACKLEN(Init_Struct->RXACKLength));
+ assert_parameters(IS_ISO7816_TXNACKLEN(Init_Struct->TXNACKLength));
+
+ tmp = ISO7816x->CFG;
+ tmp &= ~(ISO7816_CFG_ACKLEN\
+ |ISO7816_CFG_AUTORXACK\
+ |ISO7816_CFG_LSB\
+ |ISO7816_CFG_CHKP\
+ |ISO7816_CFG_RXACKSET\
+ |ISO7816_CFG_TXRTYCNT);
+ tmp |= (Init_Struct->FirstBit\
+ |Init_Struct->Parity\
+ |Init_Struct->TXRetry\
+ |Init_Struct->RXACKLength\
+ |Init_Struct->TXNACKLength);
+ ISO7816x->CFG = tmp;
+
+ pclk = CLK_GetPCLKFreq();
+ div = 0x10000 - (pclk/Init_Struct->Baudrate);
+ ISO7816x->BAUDDIVH = (div>>8) & ISO7816_BAUDDIVH_BAUDDIVH;
+ ISO7816x->BAUDDIVL = div & ISO7816_BAUDDIVL_BAUDDIVL;
+}
+
+/**
+ * @brief Enables or disables ISO7816.
+ * @param ISO7816x: ISO78160~ISO78161
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None.
+ */
+void ISO7816_Cmd(ISO7816_Type *ISO7816x, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ ISO7816x->CFG |= ISO7816_CFG_EN;
+ }
+ else
+ {
+ ISO7816x->CFG &= ~ISO7816_CFG_EN;
+ }
+}
+
+/**
+ * @brief Configures ISO7816 baudrate.
+ * @param ISO7816x: ISO78160~ISO78161
+ BaudRate:Baud rate value
+ * @retval None
+ */
+void ISO7816_BaudrateConfig(ISO7816_Type *ISO7816x, uint32_t BaudRate)
+{
+ uint32_t pclk;
+ uint16_t div;
+
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+ assert_parameters(IS_ISO7816_BAUDRATE(BaudRate));
+
+ pclk = CLK_GetPCLKFreq();
+ div = 0x10000 - (pclk/BaudRate);
+ ISO7816x->BAUDDIVH = (div>>8) & ISO7816_BAUDDIVH_BAUDDIVH;
+ ISO7816x->BAUDDIVL = div & ISO7816_BAUDDIVL_BAUDDIVL;
+}
+
+/**
+ * @brief Configures ISO7816 clock divider.
+ * @param ISO7816x: ISO78160~ISO78161
+ Prescaler:1~128
+ * @retval None
+ */
+void ISO7816_CLKDIVConfig(ISO7816_Type *ISO7816x, uint32_t Prescaler)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+ assert_parameters(IS_ISO7816_PRESCALER(Prescaler));
+
+ tmp = ISO7816x->CLK;
+ tmp &= ~ISO7816_CLK_CLKDIV;
+ tmp |= (Prescaler - 1);
+ ISO7816x->CLK = tmp;
+}
+
+/**
+ * @brief Enables or disables ISO7816 clock output function.
+ * @param ISO7816x: ISO78160~ISO78161
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void ISO7816_CLKOutputCmd(ISO7816_Type *ISO7816x, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ ISO7816x->CLK |= ISO7816_CLK_CLKEN;
+ }
+ else
+ {
+ ISO7816x->CLK &= ~ISO7816_CLK_CLKEN;
+ }
+}
+
+/**
+ * @brief Reads ISO7816 data.
+ * @param ISO7816: ISO78160~ISO78161
+ * @retval The received data.
+ */
+uint8_t ISO7816_ReceiveData(ISO7816_Type *ISO7816x)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+
+ return ISO7816x->DATA;
+}
+
+/**
+ * @brief Writes ISO7816 data.
+ * @param ISO7816x: ISO78160~ISO78161
+ * ch: data to send
+ * @retval None
+ */
+void ISO7816_SendData(ISO7816_Type *ISO7816x, uint8_t ch)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+
+ ISO7816x->DATA = ch;
+}
+
+/**
+ * @brief ENables or disables ISO7816 interrupt.
+ * @param ISO7816x: ISO78160~ISO78161
+ INTMask:
+ This parameter can be any combination of the following values
+ ISO7816_INT_TXRTYERR
+ ISO7816_INT_RXOV
+ ISO7816_INT_RX
+ ISO7816_INT_TXDONE
+ ISO7816_INT_RXERR
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void ISO7816_INTConfig(ISO7816_Type *ISO7816x, uint32_t INTMask, uint8_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+ assert_parameters(IS_ISO7816_INT(INTMask));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ ISO7816x->CFG |= INTMask;
+ }
+ else
+ {
+ ISO7816x->CFG &= ~INTMask;
+ }
+}
+
+/**
+ * @brief Gets ISO7816 interrupt state.
+ * @param ISO7816x: ISO78160~ISO78161
+ INTMask:
+ ISO7816_INTSTS_TXRTYERR
+ ISO7816_INTSTS_TXDONE
+ ISO7816_INTSTS_RXOV
+ ISO7816_INTSTS_RX
+ ISO7816_INTSTS_RXERR
+ * @retval 1: state set
+ 0: state reset
+ */
+uint8_t ISO7816_GetINTStatus(ISO7816_Type *ISO7816x, uint32_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+ assert_parameters(IS_ISO7816_INTFLAGR(INTMask));
+
+ if (ISO7816x->INFO & INTMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears ISO7816 interrupt state.
+ * @param ISO7816x: ISO78160~ISO78161
+ INTMask:
+ This parameter can be any combination of the following values
+ ISO7816_INTSTS_TXRTYERR
+ ISO7816_INTSTS_TXDONE
+ ISO7816_INTSTS_RXOV
+ ISO7816_INTSTS_RX
+ ISO7816_INTSTS_RXERR
+ * @retval None
+ */
+void ISO7816_ClearINTStatus(ISO7816_Type *ISO7816x, uint32_t INTMask)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+ assert_parameters(IS_ISO7816_INTFLAGC(INTMask));
+
+ tmp = ISO7816x->INFO;
+ tmp &= ~ISO7816_INFO_RC_MASK;
+ tmp |= INTMask;
+ ISO7816x->INFO = tmp;
+}
+
+/**
+ * @brief Gets ISO7816 peripheral flag.
+ * @param ISO7816x: ISO78160~ISO78161
+ FlagMask:
+ ISO7816_FLAG_DMATXDONE
+ * @retval 1: state set
+ 0: state reset
+ */
+uint8_t ISO7816_GetFlag(ISO7816_Type *ISO7816x, uint32_t FlagMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+ assert_parameters(IS_ISO7816_FLAGR(FlagMask));
+
+ if (ISO7816x->INFO & FlagMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears ISO7816 peripheral flag.
+ * @param ISO7816x: ISO78160~ISO78161
+ FlagMask:
+ ISO7816_FLAG_DMATXDONE
+ * @retval None
+ */
+void ISO7816_ClearFlag(ISO7816_Type *ISO7816x, uint32_t FlagMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+ assert_parameters(IS_ISO7816_FLAGC(FlagMask));
+
+ ISO7816x->INFO |= FlagMask;
+}
+
+/**
+ * @brief Gets last transmited ACK.
+ * @param ISO7816: ISO78160~ISO78161
+ * @retval ACK value
+ */
+uint8_t ISO7816_GetLastTransmitACK(ISO7816_Type *ISO7816x)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+
+ if (ISO7816x->INFO&ISO7816_INFO_RXACK)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Gets last received check sum bit.
+ * @param ISO7816: ISO78160~ISO78161
+ * @retval CHKSUM bit value
+ */
+uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_Type *ISO7816x)
+{
+ /* Check parameters */
+ assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
+
+ if (ISO7816x->INFO&ISO7816_INFO_CHKSUM)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_lcd.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_lcd.c
new file mode 100644
index 0000000000000000000000000000000000000000..404cf3381d7a0fc479d44d06fcbb72ee6e5cb1e7
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_lcd.c
@@ -0,0 +1,241 @@
+/**
+ ******************************************************************************
+ * @file lib_lcd.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief LCD library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_lcd.h"
+#include "lib_LoadNVR.h"
+
+//registers default reset values
+#define LCD_CTRL_RSTValue 0
+#define LCD_CTRL2_RSTValue 0
+#define LCD_SEGCTRL0_RSTValue 0
+#define LCD_SEGCTRL1_RSTValue 0
+#define LCD_SEGCTRL2_RSTValue 0
+
+/* COMx IO */
+const LCD_COMIO lcd_comio[] =
+{
+ {&GPIOD->OEN, GPIO_Pin_0},
+ {&GPIOD->OEN, GPIO_Pin_1},
+ {&GPIOD->OEN, GPIO_Pin_2},
+ {&GPIOD->OEN, GPIO_Pin_3},
+ {&GPIOD->OEN, GPIO_Pin_4},
+ {&GPIOD->OEN, GPIO_Pin_5},
+ {&GPIOD->OEN, GPIO_Pin_6},
+ {&GPIOD->OEN, GPIO_Pin_7},
+};
+
+/**
+ * @brief Initializes LCD.
+ * @param InitStruct: LCD configuration.
+ Type:
+ LCD_TYPE_4COM
+ LCD_TYPE_6COM
+ LCD_TYPE_8COM
+ Drv:
+ LCD_DRV_300
+ LCD_DRV_600
+ LCD_DRV_150
+ LCD_DRV_200
+ FRQ:
+ LCD_FRQ_64H
+ LCD_FRQ_128H
+ LCD_FRQ_256H
+ LCD_FRQ_512H
+ SWPR: Frame buffer switch period(0.5 sec * (SWPR + 1)).
+ FBMODE:
+ LCD_FBMODE_BUFA
+ LCD_FBMODE_BUFAB
+ LCD_FBMODE_BUFABLANK
+ BKFILL:
+ LCD_BKFILL_1
+ LCD_BKFILL_0
+ * @retval None
+ */
+void LCD_Init(LCD_InitType *InitStruct)
+{
+ uint32_t tmp_reg1, tmp_reg2;
+
+ /* Check parameters */
+ assert_parameters(IS_LCD_TYPE(InitStruct->Type));
+ assert_parameters(IS_LCD_DRV(InitStruct->Drv));
+ assert_parameters(IS_LCD_FRQ(InitStruct->FRQ));
+ assert_parameters(IS_LCD_SWPR(InitStruct->SWPR));
+ assert_parameters(IS_LCD_FBMODE(InitStruct->FBMODE));
+ assert_parameters(IS_LCD_BKFILL(InitStruct->BKFILL));
+
+ tmp_reg1 = LCD->CTRL;
+ tmp_reg2 = LCD->CTRL2;
+ tmp_reg1 &= ~(LCD_CTRL_TYPE\
+ |LCD_CTRL_DRV\
+ |LCD_CTRL_FRQ);
+ tmp_reg1 |= (InitStruct->Type\
+ |InitStruct->Drv\
+ |InitStruct->FRQ);
+ tmp_reg2 &= ~(LCD_CTRL2_SWPR\
+ |LCD_CTRL2_FBMODE\
+ |LCD_CTRL2_BKFILL);
+ tmp_reg2 |= ((InitStruct->SWPR << 8)\
+ |InitStruct->FBMODE\
+ |InitStruct->BKFILL);
+ LCD->CTRL = tmp_reg1;
+ LCD->CTRL2 = tmp_reg2;
+}
+
+/**
+ * @brief Fills each LCD_InitStruct member with its default value.
+ * @param LCD_InitStruct: pointer to an LCD_InitType structure which will be initialized.
+ * @retval None
+ */
+void LCD_StructInit(LCD_InitType *LCD_InitStruct)
+{
+ /*--------------- Reset LCD init structure parameters values ---------------*/
+ /* Initialize the BKFILL member */
+ LCD_InitStruct->BKFILL = LCD_BKFILL_0;
+ /* Initialize the Drv member */
+ LCD_InitStruct->Drv = LCD_DRV_300;
+ /* Initialize the FBMODE member */
+ LCD_InitStruct->FBMODE = LCD_FBMODE_BUFA;
+ /* Initialize the FRQ member */
+ LCD_InitStruct->FRQ = LCD_FRQ_64H;
+ /* Initialize the SWPR member */
+ LCD_InitStruct->SWPR = 0;
+ /* Initialize the Type member */
+ LCD_InitStruct->Type = LCD_TYPE_4COM;
+}
+
+/**
+ * @brief Initializes the LCD registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void LCD_DeInit(void)
+{
+ LCD->CTRL &= ~LCD_CTRL_EN;
+
+ LCD->CTRL = LCD_CTRL_RSTValue;
+ LCD->CTRL2 = LCD_CTRL2_RSTValue;
+ LCD->SEGCTRL0 = LCD_SEGCTRL0_RSTValue;
+ LCD->SEGCTRL1 = LCD_SEGCTRL1_RSTValue;
+ LCD->SEGCTRL2 = LCD_SEGCTRL2_RSTValue;
+}
+
+/**
+ * @brief Enables or disables LCD controller.
+ * @param IOInitType: LCD SEG and COM configuration.
+ SegCtrl0:
+ SegCtrl1:
+ 0~0xFFFFFFFF
+ SegCtrl2:
+ 0~0xFFFF
+ COMMode:
+ LCD_TYPE_4COM
+ LCD_TYPE_6COM
+ LCD_TYPE_8COM
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void LCD_Cmd(LCD_IOInitType *IOInitType, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+ assert_parameters(IS_LCD_COMMOD(IOInitType->COMMode));
+
+ if (NewState == ENABLE)
+ {
+ LCD->SEGCTRL0 = IOInitType->SegCtrl0;
+ LCD->SEGCTRL1 = IOInitType->SegCtrl1;
+ LCD->SEGCTRL2 = IOInitType->SegCtrl2;
+
+ /* COMs' IO configuration : forbidden */
+ *lcd_comio[0].GPIO |= lcd_comio[0].Pin;
+ *(lcd_comio[0].GPIO+1) &= ~lcd_comio[0].Pin;
+ *lcd_comio[1].GPIO |= lcd_comio[1].Pin;
+ *(lcd_comio[1].GPIO+1) &= ~lcd_comio[1].Pin;
+ *lcd_comio[2].GPIO |= lcd_comio[2].Pin;
+ *(lcd_comio[2].GPIO+1) &= ~lcd_comio[2].Pin;
+ *lcd_comio[3].GPIO |= lcd_comio[3].Pin;
+ *(lcd_comio[3].GPIO+1) &= ~lcd_comio[3].Pin;
+ if (IOInitType->COMMode & 2UL)
+ {
+ *lcd_comio[4].GPIO |= lcd_comio[4].Pin;
+ *(lcd_comio[4].GPIO+1) &= ~lcd_comio[4].Pin;
+ *lcd_comio[5].GPIO |= lcd_comio[5].Pin;
+ *(lcd_comio[5].GPIO+1) &= ~lcd_comio[5].Pin;
+ }
+ if (IOInitType->COMMode & 4UL)
+ {
+ *lcd_comio[6].GPIO |= lcd_comio[6].Pin;
+ *(lcd_comio[6].GPIO+1) &= ~lcd_comio[6].Pin;
+ *lcd_comio[7].GPIO |= lcd_comio[7].Pin;
+ *(lcd_comio[7].GPIO+1) &= ~lcd_comio[7].Pin;
+ }
+
+ /* Enable LCD */
+ LCD->CTRL |= LCD_CTRL_EN;
+ }
+ else
+ {
+ /* Disable LCD */
+ LCD->CTRL &= ~LCD_CTRL_EN;
+
+ LCD->SEGCTRL0 = IOInitType->SegCtrl0;
+ LCD->SEGCTRL1 = IOInitType->SegCtrl1;
+ LCD->SEGCTRL2 = IOInitType->SegCtrl2;
+
+ /* COMs' IO configuration : ouput low */
+ *(lcd_comio[0].GPIO+2) &= ~lcd_comio[0].Pin;
+ *lcd_comio[0].GPIO &= ~lcd_comio[0].Pin;
+ *(lcd_comio[1].GPIO+2) &= ~lcd_comio[1].Pin;
+ *lcd_comio[1].GPIO &= ~lcd_comio[1].Pin;
+ *(lcd_comio[2].GPIO+2) &= ~lcd_comio[2].Pin;
+ *lcd_comio[2].GPIO &= ~lcd_comio[2].Pin;
+ *(lcd_comio[3].GPIO+2) &= ~lcd_comio[3].Pin;
+ *lcd_comio[3].GPIO &= ~lcd_comio[3].Pin;
+ if (IOInitType->COMMode & 2UL)
+ {
+ *(lcd_comio[4].GPIO+2) &= ~lcd_comio[4].Pin;
+ *lcd_comio[4].GPIO &= ~lcd_comio[4].Pin;
+ *(lcd_comio[5].GPIO+2) &= ~lcd_comio[5].Pin;
+ *lcd_comio[5].GPIO &= ~lcd_comio[5].Pin;
+ }
+ if (IOInitType->COMMode & 4UL)
+ {
+ *(lcd_comio[6].GPIO+2) &= ~lcd_comio[6].Pin;
+ *lcd_comio[6].GPIO &= ~lcd_comio[6].Pin;
+ *(lcd_comio[7].GPIO+2) &= ~lcd_comio[7].Pin;
+ *lcd_comio[7].GPIO &= ~lcd_comio[7].Pin;
+ }
+ }
+}
+
+/**
+ * @brief Configures LCD BIAS mode.
+ * @param BiasSelection:
+ LCD_BMODE_DIV3
+ LCD_BMODE_DIV4
+ * @retval None
+ */
+void LCD_BiasModeConfig(uint32_t BiasSelection)
+{
+ uint32_t tmp;
+
+ assert_parameters(IS_LCD_BMODE(BiasSelection));
+
+ tmp = ANA->REG6;
+ tmp &= ~ANA_REG6_LCDBMODE;
+ tmp |= BiasSelection;
+ ANA->REG6 = tmp;
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_misc.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_misc.c
new file mode 100644
index 0000000000000000000000000000000000000000..44d29fc26b1fc0dd9a7e59ec59ab80125235b91f
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_misc.c
@@ -0,0 +1,255 @@
+/**
+ ******************************************************************************
+ * @file lib_misc.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief MISC library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_misc.h"
+
+/**
+ * @brief Gets MISC flag status.
+ * @param FlagMask:
+ MISC_FLAG_LOCKUP
+ MISC_FLAG_PIAC
+ MISC_FLAG_HIAC
+ MISC_FLAG_PERR
+ * @retval Flag status.
+ */
+uint8_t MISC_GetFlag(uint32_t FlagMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_MISC_FLAGR(FlagMask));
+
+ if (MISC1->SRAMINT&FlagMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears MISC flag status.
+ * @param FlagMask: can use the '|' operator
+ MISC_FLAG_LOCKUP
+ MISC_FLAG_PIAC
+ MISC_FLAG_HIAC
+ MISC_FLAG_PERR
+ * @retval None
+ */
+void MISC_ClearFlag(uint32_t FlagMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_MISC_FLAGC(FlagMask));
+
+ MISC1->SRAMINT = FlagMask;
+}
+
+/**
+ * @brief Enables or disables MISC interrupt.
+ * @param INTMask: can use the '|' operator
+ MISC_INT_LOCK
+ MISC_INT_PIAC
+ MISC_INT_HIAC
+ MISC_INT_PERR
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void MISC_INTConfig(uint32_t INTMask, uint32_t NewState)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_MISC_INT(INTMask));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = MISC1->SRAMINIT;
+ if (NewState == ENABLE)
+ {
+ tmp |= INTMask;
+ }
+ else
+ {
+ tmp &= ~INTMask;
+ }
+ MISC1->SRAMINIT = tmp;
+}
+
+/**
+ * @brief Enables or disables SRAM parity.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void MISC_SRAMParityCmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ MISC1->SRAMINIT |= MISC1_SRAMINIT_PEN;
+ }
+ else
+ {
+ MISC1->SRAMINIT &= ~MISC1_SRAMINIT_PEN;
+ }
+}
+
+/**
+ * @brief Gets SRAM parity error address.
+ * @param None
+ * @retval parity error address.
+ */
+uint32_t MISC_GetSRAMPEAddr(void)
+{
+ uint32_t tmp;
+
+ tmp = MISC1->PARERR;
+ tmp = tmp*4 + 0x20000000;
+ return tmp;
+}
+
+/**
+ * @brief Gets APB error address.
+ * @param None
+ * @retval APB error address.
+ */
+uint32_t MISC_GetAPBErrAddr(void)
+{
+ uint32_t tmp;
+
+ tmp = MISC1->PIADDR;
+ tmp = tmp + 0x40000000;
+ return tmp;
+}
+
+/**
+ * @brief Gets AHB error address.
+ * @param None
+ * @retval AHB error address.
+ */
+uint32_t MISC_GetAHBErrAddr(void)
+{
+ return (MISC1->HIADDR);
+}
+
+/**
+ * @brief Enables or disables UART transmit IR function.
+ * @param IRx:
+ MISC_IREN_TX0
+ MISC_IREN_TX1
+ MISC_IREN_TX2
+ MISC_IREN_TX3
+ MISC_IREN_TX4
+ MISC_IREN_TX5
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void MISC_IRCmd(uint32_t IRx, uint32_t NewState)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+ assert_parameters(IS_MISC_IREN(IRx));
+
+ tmp = MISC1->IREN;
+ if (NewState == ENABLE)
+ {
+ tmp |= IRx;
+ }
+ else
+ {
+ tmp &= ~IRx;
+ }
+ MISC1->IREN = tmp;
+}
+
+/**
+ * @brief Configures SUART transmit IR duty.
+ * @param DutyHigh
+ The high pulse width will be (DUTYH + 1)*APBCLK period.
+ DutyLow
+ The low pulse width will be (DUTYL + 1)*APBCLK period.
+ * @retval None
+ */
+void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow)
+{
+ MISC1->DUTYH = DutyHigh;
+ MISC1->DUTYL = DutyLow;
+}
+
+/**
+ * @brief Enables or disables Hardfault generation.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void MISC_HardFaultCmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ MISC1->IRQLAT &= ~MISC1_IRQLAT_NOHARDFAULT;
+ }
+ else
+ {
+ MISC1->IRQLAT |= MISC1_IRQLAT_NOHARDFAULT;
+ }
+}
+
+/**
+ * @brief Enables or disables a system reset when the CM0 lockup happened.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void MISC_LockResetCmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ MISC1->IRQLAT |= MISC1_IRQLAT_LOCKRESET;
+ }
+ else
+ {
+ MISC1->IRQLAT &= ~MISC1_IRQLAT_LOCKRESET;
+ }
+}
+
+/**
+ * @brief Configures IRQ latency.
+ * @param Latency:0~255
+ * @retval None
+ */
+void MISC_IRQLATConfig(uint8_t Latency)
+{
+ uint32_t tmp;
+
+ tmp = MISC1->IRQLAT;
+ tmp &= ~MISC1_IRQLAT_IRQLAT;
+ tmp |= Latency;
+ MISC1->IRQLAT = tmp;
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_pmu.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_pmu.c
new file mode 100644
index 0000000000000000000000000000000000000000..4ee20fa5622afe5c4b6ad5fe549591114464708a
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_pmu.c
@@ -0,0 +1,1194 @@
+/**
+ ******************************************************************************
+ * @file lib_pmu.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief PMU library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_pmu.h"
+#include "lib_gpio.h"
+#include "lib_CodeRAM.h"
+#include "lib_clk.h"
+#include "lib_cortex.h"
+
+#define DSLEEPPASS_KEY 0xAA5555AA
+#define DSLEEPEN_KEY 0x55AAAA55
+
+/**
+ * @brief Enters deep-sleep mode.
+ * @param None
+ * @retval 1: Current mode is debug mode, function failed.
+ * 2: Enter deep-sleep mode failed.
+ */
+uint32_t PMU_EnterDSleepMode(void)
+{
+ uint32_t hclk;
+
+ /* Current MODE is 0, debug mode, return error */
+ if (!(PMU->STS & PMU_STS_MODE))
+ return 1;
+
+ /* Enter deep sleep when WKU event is cleared */
+ while (PMU->DSLEEPEN & PMU_DSLEEPEN_WKU)
+ {
+ }
+
+ /* Flash 1USCYCLE configure */
+ hclk = CLK_GetHCLKFreq();
+ if(hclk > 1000000)
+ {
+ MISC2->FLASHWC = (hclk/1000000)<<8;
+ }
+ else
+ {
+ MISC2->FLASHWC = 0<<8;
+ }
+
+ PMU->DSLEEPPASS = DSLEEPPASS_KEY;
+ PMU->DSLEEPEN = DSLEEPEN_KEY;
+
+ return 2;
+}
+
+/**
+ * @brief Enters idle mode.
+ * @note Any interrupt generates to CPU will break idle mode.
+ * @param None
+ * @retval None
+ */
+void PMU_EnterIdleMode(void)
+{
+ /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+ __WFI();
+}
+
+/**
+ * @brief Enters sleep mode.
+ * @param None
+ * @retval 1: Current mode is debug mode, function failed.
+ * 0: Quit sleep mode succeeded.
+ */
+uint32_t PMU_EnterSleepMode(void)
+{
+ uint32_t hclk;
+
+ /* Current MODE is 0, debug mode, return error */
+ if (!(PMU->STS & PMU_STS_MODE))
+ return 1;
+
+ /* Flash 1USCYCLE configure */
+ hclk = CLK_GetHCLKFreq();
+ if(hclk > 1000000)
+ {
+ MISC2->FLASHWC = (hclk/1000000)<<8;
+ }
+ else
+ {
+ MISC2->FLASHWC = 0<<8;
+ }
+
+ /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ __WFI();
+
+ return 0;
+}
+
+/**
+ * @brief Enables or disables PMU interrupt.
+ * @param INTMask: can use the | operator
+ PMU_INT_IOAEN
+ PMU_INT_32K
+ PMU_INT_6M
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void PMU_INTConfig(uint32_t INTMask, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMU_INT(INTMask));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ PMU->CONTROL |= INTMask;
+ }
+ else
+ {
+ PMU->CONTROL &= ~INTMask;
+ }
+}
+
+/**
+ * @brief Gets PMU interrupt status.
+ * @param INTMask:
+ PMU_INTSTS_32K
+ PMU_INTSTS_6M
+ * @retval 1:status set
+ 0:status reset
+ */
+uint8_t PMU_GetINTStatus(uint32_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMU_INTFLAGR(INTMask));
+
+ if (PMU->STS&INTMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears PMU interrupt status.
+ * @param INTMask:specifies the flag to clear.
+ This parameter can be any combination of the following values
+ PMU_INTSTS_32K
+ PMU_INTSTS_6M
+ * @retval None
+ */
+void PMU_ClearINTStatus(uint32_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMU_INTFLAGC(INTMask));
+
+ PMU->STS = INTMask;
+}
+
+/**
+ * @brief Gets Crystal status.
+ * @param Mask:
+ PMU_STS_32K
+ PMU_STS_6M
+ * @retval 1:status set
+ 0:status reset
+ */
+uint8_t PMU_GetCrystalStatus(uint32_t Mask)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMU_FLAG(Mask));
+
+ if (PMU->STS&Mask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Gest all IOA interrupt status.
+ * @param None
+ * @retval IOA's interrupt status
+ */
+uint16_t PMU_GetIOAAllINTStatus(void)
+{
+ return (GPIOA->IOAINTSTS);
+}
+
+/**
+ * @brief Gest IOA interrupt status.
+ * @param INTMask:
+ GPIO_Pin_0 ~ GPIO_Pin_15
+ * @retval 1:status set
+ 0:status reset
+ */
+uint8_t PMU_GetIOAINTStatus(uint16_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_PINR(INTMask));
+
+ if (GPIOA->IOAINTSTS & INTMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears IOA interrupt status.
+ * @param INTMask:
+ This parameter can be any combination of the following values
+ GPIO_Pin_0 ~ GPIO_Pin_15
+ * @retval None
+ */
+void PMU_ClearIOAINTStatus(uint16_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_PIN(INTMask));
+
+ GPIOA->IOAINTSTS = INTMask;
+}
+
+/**
+ * @brief Configures Wake-up pin functions.
+ * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15
+ Wakeup_Event:
+ IOA_DISABLE
+ IOA_RISING
+ IOA_FALLING
+ IOA_HIGH
+ IOA_LOW
+ IOA_EDGEBOTH
+ * @retval None
+ */
+void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event)
+{
+ uint32_t tmp;
+ uint32_t posision = 0x00U;
+ uint32_t iocurrent = 0x00U;
+
+ /* Check parameters */
+ assert_parameters(IS_GPIO_PINR(IOAx));
+ assert_parameters(IS_PMU_WAKEUP(Wakeup_Event));
+
+ while ((IOAx >> posision) != 0U)
+ {
+ /* Get current io position */
+ iocurrent = IOAx & (0x01U << posision);
+
+ if (iocurrent)
+ {
+ /* Current IO Input configure*/
+ GPIOA->OEN |= iocurrent;
+ GPIOA->IE |= iocurrent;
+
+ tmp = GPIOA->IOAWKUEN;
+ tmp &= ~(3U << (2 * posision));
+ switch (Wakeup_Event)
+ {
+ /* Disable wake-up function */
+ default:
+ case IOA_DISABLE:
+ break;
+
+ /* wake-up function: Rising */
+ case IOA_RISING:
+ GPIOA->DAT &= ~iocurrent;
+ tmp |= 1 << (2 * posision);
+ break;
+
+ /* wake-up function: falling */
+ case IOA_FALLING:
+ GPIOA->DAT |= iocurrent;
+ tmp |= 1 << (2 * posision);
+ break;
+
+ /* wake-up function: high level */
+ case IOA_HIGH:
+ GPIOA->DAT &= ~iocurrent;
+ tmp |= 2 << (2 * posision);
+ break;
+
+ /* wake-up function: low level */
+ case IOA_LOW:
+ GPIOA->DAT |= iocurrent;
+ tmp |= 2 << (2 * posision);
+ break;
+
+ /* wake-up function: both edge */
+ case IOA_EDGEBOTH:
+ tmp |= 3 << (2 * posision);
+ break;
+ }
+ GPIOA->IOAWKUEN = tmp;
+ }
+ posision++;
+ }
+}
+
+/**
+ * @brief Enters deep-sleep mode with low-power configuration.
+ *
+ * @param InitStruct : pointer to PMU_LowPWRTypeDef
+ COMP1Power:
+ PMU_COMP1PWR_ON
+ PMU_COMP1PWR_OFF
+ COMP2Power:
+ PMU_COMP2PWR_ON
+ PMU_COMP2PWR_OFF
+ TADCPower:
+ PMU_TADCPWR_ON
+ PMU_TADCPWR_OFF
+ BGPPower:
+ PMU_BGPPWR_ON
+ PMU_BGPPWR_OFF
+ AVCCPower:
+ PMU_AVCCPWR_ON
+ PMU_AVCCPWR_OFF
+ VDCINDetector:
+ PMU_VDCINDET_ENABLE
+ PMU_VDCINDET_DISABLE
+ VDDDetector:
+ PMU_VDDDET_ENABLE
+ PMU_VDDDET_DISABLE
+ APBPeriphralDisable:
+ PMU_APB_ALL
+ PMU_APB_DMA
+ PMU_APB_I2C
+ PMU_APB_SPI1
+ PMU_APB_UART0
+ PMU_APB_UART1
+ PMU_APB_UART2
+ PMU_APB_UART3
+ PMU_APB_UART4
+ PMU_APB_UART5
+ PMU_APB_ISO78160
+ PMU_APB_ISO78161
+ PMU_APB_TIMER
+ PMU_APB_MISC
+ PMU_APB_U32K0
+ PMU_APB_U32K1
+ PMU_APB_SPI2
+ PMU_APB_SPI3
+ AHBPeriphralDisable:
+ PMU_AHB_ALL
+ PMU_AHB_DMA
+ PMU_AHB_GPIO
+ PMU_AHB_LCD
+ PMU_AHB_CRYPT
+
+ * @note This function performs the following:
+ Comparator 1 power control ON or OFF(optional)
+ Comparator 2 power control ON or OFF(optional)
+ Tiny ADC power control ON or OFF(optional)
+ Bandgap power control ON or OFF(optional)
+ AVCC power control ON or OFF(optional)
+ VDCIN detector control Disable or Enable(optional)
+ VDD detector control Disable or Enable(optional)
+ Disable AHB/APB periphral clock Modules(optional)
+ Disable AVCC output
+ Disable ADC
+ Disable resistance division for ADC input signal
+ Enable LCD
+
+ If 5V power supply, AVCCPower should be ON, if 3.3V power supply, AVCCPower should be OFF.
+
+ * @retval 1: Current MODE is debug mode, enter deep-sleep mode failed.
+ 2: VDCIN is not drop before enter deep-sleep mode or Failure to enter deep sleep mode.
+
+ */
+uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct)
+{
+ uint32_t tmp;
+ uint32_t hclk;
+
+ /* Check parameters */
+ assert_parameters(IS_PMU_COMP1PWR(InitStruct->COMP1Power));
+ assert_parameters(IS_PMU_COMP2PWR(InitStruct->COMP2Power));
+ assert_parameters(IS_PMU_TADCPWR(InitStruct->TADCPower));
+ assert_parameters(IS_PMU_BGPPWR(InitStruct->BGPPower));
+ assert_parameters(IS_PMU_AVCCPWR(InitStruct->AVCCPower));
+ assert_parameters(IS_PMU_VDCINDET(InitStruct->VDCINDetector));
+ assert_parameters(IS_PMU_VDDDET(InitStruct->VDDDetector));
+
+ /* Current MODE is 0, debug mode, return error */
+ if (!(PMU->STS & PMU_STS_MODE))
+ return 1;
+
+ /* Disable AVCC output */
+ ANA->REGF &= ~ANA_REGF_AVCCOEN;
+
+ /* Disable ADC */
+ ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
+
+ /* Disable resistor division for ADC input signal */
+ ANA->ADCCTRL1 &= ~ANA_ADCCTRL1_RESDIV_CHx;
+
+ /******** Comparator 1 power control ********/
+ ANA->REG3 &= ~ANA_REG3_CMP1PDN;
+ ANA->REG3 |= InitStruct->COMP1Power;
+
+ /******** Comparator 2 power control ********/
+ ANA->REG3 &= ~ANA_REG3_CMP2PDN;
+ ANA->REG3 |= InitStruct->COMP2Power;
+
+ /******** Tiny ADC power control ********/
+ tmp = ANA->REGF;
+ tmp &= ~ANA_REGF_ADTPDN;
+ tmp |= InitStruct->TADCPower;
+ ANA->REGF = tmp;
+
+ /******** BGP power control ********/
+ ANA->REG3 &= ~ANA_REG3_BGPPD;
+ ANA->REG3 |= InitStruct->BGPPower;
+
+ /******** AVCC power control ********/
+ tmp = ANA->REG8;
+ tmp &= ~ANA_REG8_AVCCLDOPD;
+ tmp |= InitStruct->AVCCPower;
+ ANA->REG8 = tmp;
+
+ /******** LCD controller power control ********/
+ /* LCD should be ENABLE */
+ tmp = LCD->CTRL;
+ tmp |= LCD_CTRL_EN;
+ LCD->CTRL = tmp;
+
+ tmp = ANA->REG7;
+ tmp |= BIT7;
+ ANA->REG7 = tmp;
+
+ /******** VDCIN detector control ********/
+ tmp = ANA->REGA;
+ tmp &= ~ANA_REGA_VDCINDETPD;
+ tmp |= InitStruct->VDCINDetector;
+ ANA->REGA = tmp;
+
+ /******** VDD detector control *********/
+ tmp = ANA->REG9;
+ tmp &= ~ANA_REG9_VDDDETPD;
+ tmp |= InitStruct->VDDDetector;
+ ANA->REG9 = tmp;
+
+ /******** AHB Periphral clock disable selection ********/
+ tmp = MISC2->HCLKEN;
+ tmp &= ~((InitStruct->AHBPeriphralDisable) & PMU_AHB_ALL);
+ MISC2->HCLKEN = tmp;
+
+ /******** APB Periphral clock disable selection ********/
+ tmp = MISC2->PCLKEN;
+ tmp &= ~((InitStruct->APBPeriphralDisable) & PMU_APB_ALL);
+ MISC2->PCLKEN = tmp;
+
+ if ((InitStruct->VDCINDetector) != PMU_VDCINDET_DISABLE)
+ {
+ if (!(ANA->CMPOUT & ANA_CMPOUT_VDCINDROP))
+ {
+ return 2;
+ }
+ }
+ // make sure WKU is 0 before entering deep-sleep mode
+ while (PMU->DSLEEPEN & PMU_DSLEEPEN_WKU);
+
+ /* Flash 1USCYCLE configure */
+ hclk = CLK_GetHCLKFreq();
+ if(hclk > 1000000)
+ {
+ MISC2->FLASHWC = (hclk/1000000)<<8;
+ }
+ else
+ {
+ MISC2->FLASHWC = 0<<8;
+ }
+
+ /* Enter deep-sleep mode */
+ PMU->DSLEEPPASS = DSLEEPPASS_KEY;
+ PMU->DSLEEPEN = DSLEEPEN_KEY;
+
+ return 2;
+}
+
+/**
+ * @brief Enters sleep mode with low-power configuration.
+ *
+ * @param InitStruct : pointer to PMU_LowPWRTypeDef
+ COMP1Power:
+ PMU_COMP1PWR_ON
+ PMU_COMP1PWR_OFF
+ COMP2Power:
+ PMU_COMP2PWR_ON
+ PMU_COMP2PWR_OFF
+ TADCPower:
+ PMU_TADCPWR_ON
+ PMU_TADCPWR_OFF
+ BGPPower:
+ PMU_BGPPWR_ON
+ PMU_BGPPWR_OFF
+ AVCCPower:
+ PMU_AVCCPWR_ON
+ PMU_AVCCPWR_OFF
+ VDCINDetector:
+ PMU_VDCINDET_ENABLE
+ PMU_VDCINDET_DISABLE
+ VDDDetector:
+ PMU_VDDDET_ENABLE
+ PMU_VDDDET_DISABLE
+ APBPeriphralDisable:
+ PMU_APB_ALL
+ PMU_APB_DMA
+ PMU_APB_I2C
+ PMU_APB_SPI1
+ PMU_APB_SPI2
+ PMU_APB_UART0
+ PMU_APB_UART1
+ PMU_APB_UART2
+ PMU_APB_UART3
+ PMU_APB_UART4
+ PMU_APB_UART5
+ PMU_APB_ISO78160
+ PMU_APB_ISO78161
+ PMU_APB_TIMER
+ PMU_APB_MISC
+ PMU_APB_U32K0
+ PMU_APB_U32K1
+ PMU_APB_SPI3
+ AHBPeriphralDisable:
+ PMU_AHB_ALL
+ PMU_AHB_DMA
+ PMU_AHB_GPIO
+ PMU_AHB_LCD
+ PMU_AHB_CRYPT
+
+ * @note This function performs the following:
+ Comparator 1 power control ON or OFF(optional)
+ Comparator 2 power control ON or OFF(optional)
+ Tiny ADC power control ON or OFF(optional)
+ Bandgap power control ON or OFF(optional)
+ AVCC power control ON or OFF(optional)
+ VDCIN detector control Disable or Enable(optional)
+ VDD detector control Disable or Enable(optional)
+ Disable AHB/APB periphral clock Modules(optional)
+ Disable AVCC output
+ Disable ADC
+ Disable resistance division for ADC input signal
+ Enable LCD
+
+ If 5V power supply, AVCCPower should be ON, if 3.3V power supply, AVCCPower should be OFF.
+
+ * @retval 2: VDCIN is not drop before enter sleep mode(failed).
+ 1: Current mode is debug mode, enter sleep mode failed.
+ 0: Quit from sleep mode success.
+*/
+uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct)
+{
+ uint32_t tmp;
+ uint32_t hclk;
+
+ /* Check parameters */
+ assert_parameters(IS_PMU_COMP1PWR(InitStruct->COMP1Power));
+ assert_parameters(IS_PMU_COMP2PWR(InitStruct->COMP2Power));
+ assert_parameters(IS_PMU_TADCPWR(InitStruct->TADCPower));
+ assert_parameters(IS_PMU_BGPPWR(InitStruct->BGPPower));
+ assert_parameters(IS_PMU_AVCCPWR(InitStruct->AVCCPower));
+ assert_parameters(IS_PMU_VDCINDET(InitStruct->VDCINDetector));
+ assert_parameters(IS_PMU_VDDDET(InitStruct->VDDDetector));
+
+ /* Current MODE is 0, debug mode, return error */
+ if (!(PMU->STS & PMU_STS_MODE))
+ return 1;
+
+ /* Disable AVCC output */
+ ANA->REGF &= ~ANA_REGF_AVCCOEN;
+
+ /* Disable ADC */
+ ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
+
+ /* Disable resistor division for ADC input signal */
+ ANA->ADCCTRL1 &= ~ANA_ADCCTRL1_RESDIV_CHx ;
+
+ /******** Comparator 1 power control ********/
+ ANA->REG3 &= ~ANA_REG3_CMP1PDN;
+ ANA->REG3 |= InitStruct->COMP1Power;
+
+ /******** Comparator 2 power control ********/
+ ANA->REG3 &= ~ANA_REG3_CMP2PDN;
+ ANA->REG3 |= InitStruct->COMP2Power;
+
+
+ /******** Tiny ADC power control ********/
+ tmp = ANA->REGF;
+ tmp &= ~ANA_REGF_ADTPDN;
+ tmp |= InitStruct->TADCPower;
+ ANA->REGF = tmp;
+
+ /******** BGP power control ********/
+ ANA->REG3 &= ~ANA_REG3_BGPPD;
+ ANA->REG3 |= InitStruct->BGPPower;
+
+ /******** AVCC power control ********/
+ tmp = ANA->REG8;
+ tmp &= ~ANA_REG8_AVCCLDOPD;
+ tmp |= InitStruct->AVCCPower;
+ ANA->REG8 = tmp;
+
+ /******** LCD controller power control ********/
+ /* LCD should be ENABLE */
+ tmp = LCD->CTRL;
+ tmp |= LCD_CTRL_EN;
+ LCD->CTRL = tmp;
+
+ tmp = ANA->REG7;
+ tmp |= BIT7;
+ ANA->REG7 = tmp;
+
+ /******** VDCIN detector control ********/
+ tmp = ANA->REGA;
+ tmp &= ~ANA_REGA_VDCINDETPD;
+ tmp |= InitStruct->VDCINDetector;
+ ANA->REGA = tmp;
+
+ /******** VDD detector control *********/
+ tmp = ANA->REG9;
+ tmp &= ~ANA_REG9_VDDDETPD;
+ tmp |= InitStruct->VDDDetector;
+ ANA->REG9 = tmp;
+
+ /******** AHB Periphral clock disable selection ********/
+ tmp = MISC2->HCLKEN;
+ tmp &= ~((InitStruct->AHBPeriphralDisable) & PMU_AHB_ALL);
+ MISC2->HCLKEN = tmp;
+
+ /******** APB Periphral clock disable selection ********/
+ tmp = MISC2->PCLKEN;
+ tmp &= ~((InitStruct->APBPeriphralDisable) & PMU_APB_ALL);
+ MISC2->PCLKEN = tmp;
+
+ if ((InitStruct->VDCINDetector) != PMU_VDCINDET_DISABLE)
+ {
+ if (!(ANA->CMPOUT & ANA_CMPOUT_VDCINDROP))
+ {
+ return 2;
+ }
+ }
+
+ /* Flash 1USCYCLE configure */
+ hclk = CLK_GetHCLKFreq();
+ if(hclk > 1000000)
+ {
+ MISC2->FLASHWC = (hclk/1000000)<<8;
+ }
+ else
+ {
+ MISC2->FLASHWC = 0<<8;
+ }
+
+ /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ __WFI();
+
+ return 0;
+}
+
+
+/**
+ * @brief Enter idle mode with flash deep standby.
+ * @param None
+ * @retval None
+ */
+#ifndef __GNUC__
+void PMU_EnterIdle_LowPower(void)
+{
+ uint32_t hclk;
+
+ /* Flash 1USCYCLE configure */
+ hclk = CLK_GetHCLKFreq();
+ if(hclk > 1000000)
+ {
+ MISC2->FLASHWC = (hclk/1000000)<<8;
+ }
+ else
+ {
+ MISC2->FLASHWC = 0<<8;
+ }
+
+ PMU_EnterIdle_FlashDSTB();
+}
+#endif
+
+/**
+ * @brief Configures IOA wake-up source about sleep mode.
+ * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15
+ Wakeup_Event:
+ IOA_DISABLE
+ IOA_RISING
+ IOA_FALLING
+ IOA_HIGH
+ IOA_LOW
+ IOA_EDGEBOTH
+ Priority: The preemption priority for the IRQn channel.
+ This parameter can be a value between 0 and 3.
+ * @retval
+ */
+void PMU_SleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_PINR(IOAx));
+ assert_parameters(IS_PMU_WAKEUP(Wakeup_Event));
+
+ /* Disable PMU interrupt in NVIC */
+ NVIC_DisableIRQ(PMU_IRQn);
+ /* Wake-up pins configuration */
+ PMU_WakeUpPinConfig(IOAx, Wakeup_Event);
+ /* Clear interrupt flag */
+ GPIOA->IOAINTSTS = IOAx;
+ /* Enable PMU interrupt */
+ PMU->CONTROL |= PMU_CONTROL_INT_IOA_EN;
+ CORTEX_SetPriority_ClearPending_EnableIRQ(PMU_IRQn, Priority);
+}
+
+/**
+ * @brief Configures RTC wake-up source about sleep mode.
+ * @param Wakeup_Event:
+ This parameter can be any combination of the following values
+ PMU_RTCEVT_ALARM
+ PMU_RTCEVT_WKUCNT
+ PMU_RTCEVT_MIDNIGHT
+ PMU_RTCEVT_WKUHOUR
+ PMU_RTCEVT_WKUMIN
+ PMU_RTCEVT_WKUSEC
+ PMU_RTCEVT_TIMEILLE
+ PMU_RTCEVT_ITVSITV
+ Priority: The preemption priority for the IRQn channel.
+ This parameter can be a value between 0 and 3.
+ * @retval
+ */
+void PMU_SleepWKUSRCConfig_RTC(uint32_t Wakeup_Event, uint32_t Priority)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMU_RTCEVT(Wakeup_Event));
+
+ /* Disable RTC interrupt in NVIC */
+ NVIC_DisableIRQ(RTC_IRQn);
+ /* Clear interrupt flag */
+ RTC->INTSTS = Wakeup_Event;
+ /* Enable RTC interrupt */
+ RTC->INTEN |= Wakeup_Event;
+ CORTEX_SetPriority_ClearPending_EnableIRQ(RTC_IRQn, Priority);
+}
+/**
+ * @brief Configures IOA wake-up source about deep-sleep mode.
+ * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15
+ Wakeup_Event:
+ IOA_DISABLE
+ IOA_RISING
+ IOA_FALLING
+ IOA_HIGH
+ IOA_LOW
+ IOA_EDGEBOTH
+ * @retval
+ */
+void PMU_DeepSleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event)
+{
+ /* Check parameters */
+ assert_parameters(IS_GPIO_PINR(IOAx));
+ assert_parameters(IS_PMU_WAKEUP(Wakeup_Event));
+
+ /* Wake-up pins configuration */
+ PMU_WakeUpPinConfig(IOAx, Wakeup_Event);
+ /* Clear interrupt flag */
+ GPIOA->IOAINTSTS = IOAx;
+}
+
+/**
+ * @brief Configures RTC wake-up source about deep-sleep mode.
+ * @param Wakeup_Event:
+ This parameter can be any combination of the following values
+ PMU_RTCEVT_ALARM
+ PMU_RTCEVT_WKUCNT
+ PMU_RTCEVT_MIDNIGHT
+ PMU_RTCEVT_WKUHOUR
+ PMU_RTCEVT_WKUMIN
+ PMU_RTCEVT_WKUSEC
+ PMU_RTCEVT_TIMEILLE
+ PMU_RTCEVT_ITVSITV
+ * @retval
+ */
+void PMU_DeepSleepWKUSRCConfig_RTC(uint32_t Wakeup_Event)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMU_RTCEVT(Wakeup_Event));
+
+ /* Clear interrupt flag */
+ RTC->INTSTS = Wakeup_Event;
+ /* Enable RTC interrupt */
+ RTC->INTEN |= Wakeup_Event;
+}
+
+/**
+ * @brief Configures the deep sleep behavior when VDD/VDCIN is not drop.
+ * @param VDCIN_PDNS:
+ PMU_VDCINPDNS_0 , can't enter deep-sleep mode when VDCIN is not drop
+ can wake-up mcu from deep-sleep, when VDCIN is not drop.
+ PMU_VDCINPDNS_1 , The condition for entering deep sleep mode is independent of VDCIN.
+ VDD_PDNS:
+ PMU_VDDPDNS_0 , can't enter deep-sleep mode when VDD is not drop(>Threshold)
+ can wake-up mcu from deep-sleep, when VDD is not drop.
+ PMU_VDDPDNS_1 , The condition for entering deep sleep mode is independent of VDD.
+ * @retval None
+ */
+void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PMU_VDCINPDNS(VDCIN_PDNS));
+ assert_parameters(IS_PMU_VDDPDNS(VDD_PDNS));
+
+ tmp = ANA->CTRL;
+ tmp &= ~(ANA_CTRL_PDNS | ANA_CTRL_PDNS2);
+ tmp |= (VDCIN_PDNS | VDD_PDNS);
+
+ ANA->CTRL = tmp;
+}
+
+/**
+ * @brief Enables or disables BGP power.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void PMU_BGPCmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ ANA->REG3 &= ~ANA_REG3_BGPPD;
+ else
+ ANA->REG3 |= ANA_REG3_BGPPD;
+}
+
+/**
+ * @brief Configures VDD alarm threshold voltage.
+ * @param CheckTHR:
+ PMU_VDDALARM_4_5V
+ PMU_VDDALARM_4_2V
+ PMU_VDDALARM_3_9V
+ PMU_VDDALARM_3_6V
+ PMU_VDDALARM_3_2V
+ PMU_VDDALARM_2_9V
+ PMU_VDDALARM_2_6V
+ PMU_VDDALARM_2_3V
+ CheckFrequency:
+ PMU_VDDALARM_CHKFRE_NOCHECK
+ PMU_VDDALARM_CHKFRE_30US
+ * @retval None
+ */
+void PMU_VDDAlarmConfig(uint32_t CheckTHR,uint32_t CheckFrequency)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PMU_VDDALARM_THR(CheckTHR));
+ assert_parameters(IS_PMU_VDDALARM_CHKFRE(CheckFrequency));
+
+ /* Configure CheckTHR */
+ tmp = ANA->REG8;
+ tmp &= ~ANA_REG8_VDDPVDSEL;
+ tmp |= CheckTHR;
+ ANA->REG8 = tmp;
+
+ /* Configure CheckFrequency */
+ tmp = ANA->CMPCTL;
+ tmp &= ~ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL;
+ tmp |= CheckFrequency;
+ ANA->CMPCTL = tmp;
+
+ if (CheckFrequency == PMU_VDDALARM_CHKFRE_NOCHECK)
+ {
+ ANA->REG9 |= ANA_REG9_VDDDETPD;
+ }
+ else
+ {
+ ANA->REG9 &= ~ANA_REG9_VDDDETPD;
+ }
+}
+
+/**
+ * @brief Gets VDD alarm status.
+ * @param None
+ * @retval POWALARM status
+ 0: Voltage of VDD is higher than threshold.
+ 1: Voltage of VDD is lower than threshold.
+ */
+uint8_t PMU_GetVDDAlarmStatus(void)
+{
+ if (ANA->CMPOUT & ANA_CMPOUT_VDDALARM)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Gets current MODE pin status.
+ * @param None
+ * @retval MODE pin status
+ * 0: Debug mode.
+ * 1: Normal mode.
+ */
+uint8_t PMU_GetModeStatus(void)
+{
+ if(PMU->STS & PMU_STS_MODE)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Enables or disables AVCC.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void PMU_AVCCCmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ ANA->REG8 &= ~ANA_REG8_AVCCLDOPD;
+ else
+ ANA->REG8 |= ANA_REG8_AVCCLDOPD;
+}
+
+/**
+ * @brief Enables or disables VDD33_O pin power.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void PMU_AVCCOutputCmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == DISABLE)
+ ANA->REGF &= ~ANA_REGF_AVCCOEN;
+ else
+ ANA->REGF |= ANA_REGF_AVCCOEN;
+}
+
+/**
+ * @brief Enables or disables AVCC Low Voltage detector.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void PMU_AVCCLVDetectorCmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ ANA->REG5 &= ~ANA_REG5_AVCCLVDETPD;
+ else
+ ANA->REG5 |= ANA_REG5_AVCCLVDETPD;
+}
+
+/**
+ * @brief Gets AVCC low power status.
+ * @param None
+ * @retval low power status of AVCC
+ * 0: status not set, AVCC is higher than 2.5V.
+ * 1: status set, AVCC is lower than 2.5V.
+ */
+uint8_t PMU_GetAVCCLVStatus(void)
+{
+ if (ANA->CMPOUT & ANA_CMPOUT_AVCCLV)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Enables or disables VDCIN decector.
+ * @param NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void PMU_VDCINDetectorCmd(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ ANA->REGA &= ~ANA_REGA_VDCINDETPD;
+ else
+ ANA->REGA |= ANA_REGA_VDCINDETPD;
+}
+
+/**
+ * @brief Gets VDCIN drop status.
+ * @param None
+ * @retval drop status of VDCIN
+ 0: status not set, VDCIN is not drop.
+ 1: status set, VDCIN is drop.
+ */
+uint8_t PMU_GetVDCINDropStatus(void)
+{
+ if (ANA->CMPOUT & ANA_CMPOUT_VDCINDROP)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Configures VDDALARM, VDCIN and AVCCDET de-bounce.
+ * @param DEBSel:
+ 0: No de-bounce.
+ 1: 2 RTCCLK de-bounce.
+ 2: 3 RTCCLK de-bounce.
+ 3: 4 RTCCLK de-bounce.
+ 4: 5 RTCCLK de-bounce.
+ ...
+ 255: 256 RTCCLK de-bounce.
+ * @retval None
+ */
+void PMU_PWRDEBSel(uint32_t DEBSel)
+{
+ uint32_t tmp;
+ /* Check parameters */
+ assert_parameters(IS_PMU_PWR_DEBSEL(DEBSel));
+
+ tmp = ANA->CMPCTL;
+ tmp &= ~ANA_CMPCTL_PWR_DEB_SEL;
+ tmp |= (DEBSel << ANA_CMPCTL_PWR_DEB_SEL_Pos);
+ ANA->CMPCTL = tmp;
+}
+
+/**
+ * @brief Discharges or not discharges the BAT battery.
+ * @param BATDisc:
+ PMU_BAT1
+ PMU_BATRTC
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMU_BATRTCDISC(BATDisc));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ ANA->REG6 |= BATDisc;
+ else
+ ANA->REG6 &= ~BATDisc;
+}
+
+
+/**
+ * @brief Gets power status.
+ * @param StatusMask:
+ PMU_PWRSTS_AVCCLV
+ PMU_PWRSTS_VDCINDROP
+ PMU_PWRSTS_VDDALARM
+ * @retval power status
+ * 1 status set
+ * 0 status not set
+ */
+uint8_t PMU_GetPowerStatus(uint32_t StatusMask)
+{
+ if (ANA->CMPOUT & StatusMask)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Gets reset source status.
+ * @param Mask:
+ PMU_RSTSRC_EXTRST
+ PMU_RSTSRC_PORST
+ PMU_RSTSRC_DPORST
+ PMU_RSTSRC_WDTRST
+ PMU_RSTSRC_SFTRST
+ PMU_RSTSRC_MODERST
+ * @retval 1: Reset status set
+ 0: Reset status reset
+ */
+uint8_t PMU_GetResetSource(uint32_t Mask)
+{
+ /* Check parameters */
+ assert_parameters(PMU_RESETSRC(Mask));
+
+ if (PMU->STS & Mask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears reset source status.
+ * @param Mask: can use the '|' operator
+ PMU_RSTSRC_EXTRST
+ PMU_RSTSRC_PORST
+ PMU_RSTSRC_DPORST
+ PMU_RSTSRC_WDTRST
+ PMU_RSTSRC_SFTRST
+ PMU_RSTSRC_MODERST
+ PMU_RSTSRC_ALL
+ * @retval None
+ */
+void PMU_ClearResetSource(uint32_t Mask)
+{
+ /* Check parameters */
+ assert_parameters(PMU_RESETSRC_CLR(Mask));
+
+ PMU->STS = Mask;
+}
+
+/**
+ * @brief Gets all reset source status.
+ * @param None
+ * @retval All reset source status
+ */
+uint32_t PMU_GetAllResetSource(void)
+{
+ return (PMU->STS & PMU_RSTSRC_Msk);
+}
+
+/**
+ * @brief Gets deep-sleep wakeup source status.
+ * @param Mask:
+ PMU_DSLEEPWKUSRC_MODE
+ PMU_DSLEEPWKUSRC_XTAL
+ PMU_DSLEEPWKUSRC_U32K
+ PMU_DSLEEPWKUSRC_ANA
+ PMU_DSLEEPWKUSRC_RTC
+ PMU_DSLEEPWKUSRC_IOA
+ * @retval 1: Wakeup status set
+ 0: Wakeup status reset
+ */
+uint8_t PMU_GetDSleepWKUSource(uint32_t Mask)
+{
+ /* Check parameters */
+ assert_parameters(IS_PMU_DSLEEPWKUSRC(Mask));
+
+ if (PMU->STS & Mask)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Gest deep-sleep wakeup source status.
+ * @param None
+ * @retval All deep-sleep wakeup source status
+ */
+uint32_t PMU_GetAllDSleepWKUSource(void)
+{
+ return (PMU->STS & PMU_DSLEEPWKUSRC_Msk);
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_pwm.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_pwm.c
new file mode 100644
index 0000000000000000000000000000000000000000..23f3f64c7b84501dbc1f30cc2de45de8560d08d0
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_pwm.c
@@ -0,0 +1,530 @@
+/**
+ ******************************************************************************
+ * @file lib_pwm.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief PWM library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_pwm.h"
+
+/**
+ * @brief Initializes PWM timebase.
+ * @param PWMx: PWM0~PWM3
+ InitStruct:PWM BASE configuration.
+ ClockDivision:
+ PWM_CLKDIV_2
+ PWM_CLKDIV_4
+ PWM_CLKDIV_8
+ PWM_CLKDIV_16
+ Mode:
+ PWM_MODE_STOP
+ PWM_MODE_UPCOUNT
+ PWM_MODE_CONTINUOUS
+ PWM_MODE_UPDOWN
+ ClockSource:
+ PWM_CLKSRC_APB
+ PWM_CLKSRC_APBD128
+ * @retval None
+ */
+void PWM_BaseInit(PWM_Type *PWMx, PWM_BaseInitType *InitStruct)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CLKDIV(InitStruct->ClockDivision));
+ assert_parameters(IS_PWM_CNTMODE(InitStruct->Mode));
+ assert_parameters(IS_PWM_CLKSRC(InitStruct->ClockSource));
+
+ tmp = PWMx->CTL;
+ tmp &= ~(PWM_CTL_ID\
+ |PWM_CTL_MC\
+ |PWM_CTL_TSEL);
+ tmp |= (InitStruct->ClockDivision\
+ |InitStruct->Mode\
+ |InitStruct->ClockSource);
+ PWMx->CTL = tmp;
+}
+
+/**
+ * @brief Fills each PWM_BaseInitType member with its default value.
+ * @param InitStruct: pointer to an PWM_BaseInitType structure which will be initialized.
+ * @retval None
+ */
+void PWM_BaseStructInit(PWM_BaseInitType *InitStruct)
+{
+ /*------------ Reset PWM base init structure parameters values ------------*/
+ /* Initialize the ClockDivision member */
+ InitStruct->ClockDivision = PWM_CLKDIV_2;
+ /* Initialize the ClockSource member */
+ InitStruct->ClockSource = PWM_CLKSRC_APBD128;
+ /* Initialize the Mode member */
+ InitStruct->Mode = PWM_MODE_STOP;
+}
+
+/**
+ * @brief Fills each PWM_OCInitType member with its default value.
+ * @param OCInitType: pointer to an PWM_OCInitType structure which will be initialized.
+ * @retval None
+ */
+void PWM_OCStructInit(PWM_OCInitType *OCInitType)
+{
+ /*------- Reset PWM output channel init structure parameters values --------*/
+ /* Initialize the Channel member */
+ OCInitType->Channel = PWM_CHANNEL_0;
+ /* Initialize the OutMode member */
+ OCInitType->OutMode = PWM_OUTMOD_CONST;
+ /* Initialize the Period member */
+ OCInitType->Period = 0;
+}
+
+/**
+ * @brief Initializes PWM channel output compare function.
+ * @param PWMx: PWM0~PWM3
+ OCInitType:PWM output compare configuration.
+ Channel:
+ PWM_CHANNEL_0
+ PWM_CHANNEL_1
+ PWM_CHANNEL_2
+ OutMode:
+ PWM_OUTMOD_CONST
+ PWM_OUTMOD_SET
+ PWM_OUTMOD_TOGGLE_RESET
+ PWM_OUTMOD_SET_RESET
+ PWM_OUTMOD_TOGGLE
+ PWM_OUTMOD_RESET
+ PWM_OUTMOD_TOGGLE_SET
+ PWM_OUTMOD_RESET_SET
+ Period: 0 ~ 0xFFFF
+ * @retval None
+ */
+void PWM_OCInit(PWM_Type *PWMx, PWM_OCInitType *OCInitType)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CHANNEL(OCInitType->Channel));
+ assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode));
+ assert_parameters(IS_PWM_CCR(OCInitType->Period));
+
+ tmp = PWMx->CCTL[OCInitType->Channel];
+ tmp &= ~(PWM_CCTL_CAP | PWM_CCTL_OUTMOD | PWM_CCTL_CCIFG | PWM_CCTL_COV);
+ tmp |= OCInitType->OutMode;
+ PWMx->CCTL[OCInitType->Channel] = tmp;
+ PWMx->CCR[OCInitType->Channel] = OCInitType->Period;
+}
+
+/**
+ * @brief Fills each PWM_ICInitType member with its default value.
+ * @param ICInitType: pointer to a PWM_OCInitType structure which will be initialized.
+ * @retval None
+ */
+void PWM_ICStructInit(PWM_ICInitType *ICInitType)
+{
+ /*------- Reset PWM output channel init structure parameters values --------*/
+ /* Initialize the Channel member */
+ ICInitType->Channel = PWM_CHANNEL_0;
+ /* Initialize the CaptureMode member */
+ ICInitType->CaptureMode = PWM_CM_DISABLE;
+}
+
+
+/**
+ * @brief Initializes PWM channel input capture function.
+ * @param PWMx: PWM0~PWM3
+ ICInitType:PWM output compare configuration.
+ Channel:
+ PWM_CHANNEL_0
+ PWM_CHANNEL_1
+ PWM_CHANNEL_2
+ CaptureMode:
+ PWM_CM_DISABLE
+ PWM_CM_RISING
+ PWM_CM_FALLING
+ PWM_CM_BOTH
+ * @retval None
+ */
+void PWM_ICInit(PWM_Type *PWMx, PWM_ICInitType *ICInitType)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CHANNEL(ICInitType->Channel));
+ assert_parameters(IS_PWM_CAPMODE(ICInitType->CaptureMode));
+
+ tmp = PWMx->CCTL[ICInitType->Channel];
+ tmp &= ~(PWM_CCTL_CM | PWM_CCTL_CAP | PWM_CCTL_CCIFG | PWM_CCTL_COV);
+ tmp |= (ICInitType->CaptureMode | PWM_CCTL_CAP);
+ PWMx->CCTL[ICInitType->Channel] = tmp;
+}
+
+/**
+ * @brief Enables or disables PWM base interrupt.
+ * @param PWMx: PWM0~PWM3
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void PWM_BaseINTConfig(PWM_Type *PWMx, uint32_t NewState)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = PWMx->CTL;
+ tmp &= ~(PWM_CTL_IE | PWM_CTL_IFG);
+ if (NewState == ENABLE)
+ {
+ tmp |= PWM_CTL_IE;
+ }
+ PWMx->CTL = tmp;
+}
+
+/**
+ * @brief Gets PWM base interrupt status.
+ * @param PWMx: PWM0~PWM3
+ * @retval interrupt status.
+ */
+uint8_t PWM_GetBaseINTStatus(PWM_Type *PWMx)
+{
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+
+ if (PWMx->CTL&PWM_CTL_IFG)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Clears PWM base interrupt status.
+ * @param PWMx: PWM0~PWM3
+ * @retval None.
+ */
+void PWM_ClearBaseINTStatus(PWM_Type *PWMx)
+{
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+
+ PWMx->CTL |= PWM_CTL_IFG;
+}
+
+/**
+ * @brief Enables or disables channel interrupt.
+ * @param PWMx: PWM0~PWM3
+ Channel:
+ PWM_CHANNEL_0
+ PWM_CHANNEL_1
+ PWM_CHANNEL_2
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void PWM_ChannelINTConfig(PWM_Type *PWMx, uint32_t Channel, uint32_t NewState)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CHANNEL(Channel));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = PWMx->CCTL[Channel];
+ tmp &= ~(PWM_CCTL_CCIE | PWM_CCTL_CCIFG | PWM_CCTL_COV);
+ if (NewState == ENABLE)
+ {
+ tmp |= PWM_CCTL_CCIE;
+ }
+ PWMx->CCTL[Channel] = tmp;
+}
+
+/**
+ * @brief Gets channel interrupt status.
+ * @param PWMx: PWM0~PWM3
+ Channel:
+ PWM_CHANNEL_0
+ PWM_CHANNEL_1
+ PWM_CHANNEL_2
+ IntMask:
+ PWM_INT_CCIFG
+ PWM_INT_COV
+ * @retval interrupt status
+ */
+uint8_t PWM_GetChannelINTStatus(PWM_Type *PWMx, uint32_t Channel, uint32_t IntMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CHANNEL(Channel));
+ assert_parameters(IS_PWM_INTFLAGR(IntMask));
+
+ if (PWMx->CCTL[Channel] & IntMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears channel interrupt status.
+ * @param PWMx: PWM0~PWM3
+ Channel:
+ PWM_CHANNEL_0
+ PWM_CHANNEL_1
+ PWM_CHANNEL_2
+ Int_Mask:
+ PWM_INT_CCIFG
+ PWM_INT_COV
+ * @retval None
+ */
+void PWM_ClearChannelINTStatus(PWM_Type *PWMx, uint32_t Channel, uint32_t IntMask)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CHANNEL(Channel));
+ assert_parameters(IS_PWM_INTFLAGC(IntMask));
+
+ tmp = PWMx->CCTL[Channel];
+ tmp &= ~PWM_INT_Msk;
+ tmp |= IntMask;
+ PWMx->CCTL[Channel] = tmp;
+}
+
+/**
+ * @brief Clears PWM counter.
+ * @param PWMx: PWM0~PWM3
+ * @retval None
+ */
+void PWM_ClearCounter(PWM_Type *PWMx)
+{
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+
+ PWMx->CTL |= PWM_CTL_CLR;
+}
+
+/**
+ * @brief Configures PWM channel CCR value.
+ * @param PWMx: PWM0~PWM3
+ Channel:
+ PWM_CHANNEL_0
+ PWM_CHANNEL_1
+ PWM_CHANNEL_2
+ Period: 0 ~ 0xFFFF
+ * @retval None
+ */
+void PWM_CCRConfig(PWM_Type *PWMx, uint32_t Channel, uint16_t Period)
+{
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CHANNEL(Channel));
+
+ PWMx->CCR[Channel] = Period;
+}
+
+/**
+ * @brief Configures PWM output line.
+ * @param OutSelection:
+ PWM0_OUT0
+ PWM0_OUT1
+ PWM0_OUT2
+ PWM1_OUT0
+ PWM1_OUT1
+ PWM1_OUT2
+ PWM2_OUT0
+ PWM2_OUT1
+ PWM2_OUT2
+ PWM3_OUT0
+ PWM3_OUT1
+ PWM3_OUT2
+ OLine: can use the '|' operator
+ PWM_OLINE_0
+ PWM_OLINE_1
+ PWM_OLINE_2
+ PWM_OLINE_3
+ * @note PWM Single channel's output waveform can be output on multiple output lines.
+ * Multiple-line configuration can be performed by using the '|' operator.
+ * ex: PWM_OLineConfig(PWM0_OUT0, PWM_OLINE_0 | PWM_OLINE_2)
+ * PWM0 channel0 output by PWM0&PWM2's line.
+ * @retval None
+ */
+void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine)
+{
+ uint32_t tmp;
+ uint32_t position = 0;
+
+ /* Check parameters */
+ assert_parameters(IS_PWM_OUTLINE(OLine));
+ assert_parameters(IS_PWM_OUTSEL(OutSelection));
+
+ tmp = PWM_SEL->O_SEL;
+ while ((OLine >> position) != 0UL)
+ {
+ if ((OLine >> position) & 1UL)
+ {
+ tmp &= ~(PWM_SEL_O_SEL_SEL0 << (position * 4));
+ tmp |= (OutSelection << (position * 4));
+ }
+ position++;
+ }
+ PWM_SEL->O_SEL = tmp;
+}
+
+/**
+ * @brief Enables disables PWM output function.
+ * @param PWMx: PWM0~PWM3
+ Channel:
+ PWM_CHANNEL_0
+ PWM_CHANNEL_1
+ PWM_CHANNEL_2
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void PWM_OutputCmd(PWM_Type *PWMx, uint32_t Channel, uint32_t NewState)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CHANNEL(Channel));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = PWMx->CCTL[Channel];
+ tmp &= ~(PWM_CCTL_CCIFG | PWM_CCTL_COV);
+ if (NewState == ENABLE)
+ {
+ tmp |= PWM_CCTL_OUTEN;
+ }
+ else
+ {
+ tmp &= ~PWM_CCTL_OUTEN;
+ }
+ PWMx->CCTL[Channel] = tmp;
+}
+
+/**
+ * @brief Sets PWM channel output level.
+ * @param PWMx: PWM0~PWM3
+ Channel:
+ PWM_CHANNEL_0
+ PWM_CHANNEL_1
+ PWM_CHANNEL_2
+ Level:
+ PWM_LEVEL_HIGH
+ PWM_LEVEL_LOW
+ * @retval None
+ */
+void PWM_SetOutLevel(PWM_Type *PWMx, uint32_t Channel, uint32_t Level)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CHANNEL(Channel));
+ assert_parameters(IS_PWM_OUTLVL(Level));
+
+ tmp = PWMx->CCTL[Channel];
+ tmp &= ~(PWM_CCTL_OUT | PWM_CCTL_CCIFG | PWM_CCTL_COV);
+ tmp |= Level;
+ PWMx->CCTL[Channel] = tmp;
+}
+
+/**
+ * @brief Configures PWM input line.
+ * @param InSelection:
+ PWM1_IN2
+ PWM1_IN1
+ PWM1_IN0
+ PWM0_IN2
+ PWM0_IN1
+ PWM0_IN0
+ PWM3_IN2
+ PWM3_IN1
+ PWM3_IN0
+ PWM2_IN2
+ PWM2_IN1
+ PWM2_IN0
+ ILine:
+ PWM_ILINE_0
+ PWM_ILINE_1
+ PWM_ILINE_2
+ PWM_ILINE_3
+ * @retval None
+ */
+void PWM_ILineConfig(uint32_t InSelection, uint32_t ILine)
+{
+ __IO uint32_t *addr;
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_PWM_INLINE(ILine));
+ assert_parameters(IS_PWM_INSEL(InSelection));
+
+ addr = &PWM_SEL->I_SEL01 + ((InSelection&0xF00)>>8);
+ tmp = *addr;
+ tmp &= ~( 3 << (InSelection&0xFF));
+ tmp |= (ILine << (InSelection&0xFF));
+ *addr = tmp;
+}
+
+/**
+ * @brief Gets PWM channel SCCI value.
+ * @param PWMx: PWM0~PWM3
+ Channel:
+ PWM_CHANNEL_0
+ PWM_CHANNEL_1
+ PWM_CHANNEL_2
+ * @retval INx¡¯s input value when the TAR is equal to CCRx
+ */
+uint8_t PWM_GetSCCI(PWM_Type *PWMx, uint32_t Channel)
+{
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CHANNEL(Channel));
+
+ if (PWMx->CCTL[Channel] & PWM_CCTL_SCCI)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Gets PWM channel capture value.
+ * @param PWMx: PWM0~PWM3
+ Channel:
+ PWM_CHANNEL_0
+ PWM_CHANNEL_1
+ PWM_CHANNEL_2
+ * @retval The value of CCRx.
+ */
+uint32_t PWM_GetCapture(PWM_Type *PWMx, uint32_t Channel)
+{
+ /* Check parameters */
+ assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
+ assert_parameters(IS_PWM_CHANNEL(Channel));
+
+ return PWMx->CCR[Channel];
+}
+
+/******************* (C) COPYRIGHT Vango Technologies, Inc *****END OF FILE****/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_rtc.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_rtc.c
new file mode 100644
index 0000000000000000000000000000000000000000..b20546572d715c08e13354ae0ad35a48fc02800d
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_rtc.c
@@ -0,0 +1,793 @@
+/**
+ ******************************************************************************
+ * @file lib_rtc.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief RTC library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_rtc.h"
+
+#define RTCPWD_KEY 0x5AA55AA5
+#define RTCCE_SETKEY 0xA55AA55B
+#define RTCCE_CLRKEY 0xA55AA55A
+
+/**
+ * @brief Enables or disables RTC registers write protection.
+ * @param NewState:
+ * ENABLE
+ * DISABLE
+ * @retval None
+ */
+void RTC_WriteProtection(uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Enable RTC Write-Protection */
+ if (NewState != DISABLE)
+ {
+ RTC->PWD = RTCPWD_KEY;
+ RTC->CE = RTCCE_CLRKEY;
+ }
+ /* Disable RTC Write-Protection */
+ else
+ {
+ RTC->PWD = RTCPWD_KEY;
+ RTC->CE = RTCCE_SETKEY;
+ }
+}
+
+/**
+ * @brief Waits until the RTC registers (be W/R protected) are synchronized
+ * with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * RTC_WriteProtection(DISABLE) before calling this function.
+ * Write-Operation process as follows:
+ * 1. RTC_WriteProtection(DISABLE);
+ * 2. RTC Registers write operation(only first write-operation be
+ * valid on the same register).
+ * 3. RTC_WriteProtection(ENABLE);
+ * 4. RTC_WaitForSynchro(); Wait until the RTC registers be
+ * synchronized by calling this function.
+ * @retval None
+ */
+void RTC_WaitForSynchro(void)
+{
+ while (RTC->CE & RTC_CE_BSY)
+ {
+ }
+}
+
+/**
+ * @brief Writes RTC registers(continuous/be write-protected).
+ * @param[in] StartAddr the start address of registers be written
+ * @param[in] wBuffer pointer to write
+ * @param[in] Len number of registers be written
+ * @retval None
+ */
+void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len)
+{
+ uint8_t cnt;
+
+ /* Parameter check */
+ assert_parameters(IS_RTC_REGOP_STARTADDR(StartAddr));
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ /* Write registers */
+ for (cnt=0; cntLOAD */
+ tmp = RTC->LOAD;
+ tmp += 1;
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+
+ /* Read registers */
+ for (cnt=0; cntYear));
+ assert_parameters(IS_RTC_TIME_MONTH(sTime->Month));
+ assert_parameters(IS_RTC_TIME_DATE(sTime->Date));
+ assert_parameters(IS_RTC_TIME_WEEKDAY(sTime->WeekDay));
+ assert_parameters(IS_RTC_TIME_HOURS(sTime->Hours));
+ assert_parameters(IS_RTC_TIME_MINS(sTime->Minutes));
+ assert_parameters(IS_RTC_TIME_SECS(sTime->Seconds));
+ if (AccurateSel == RTC_ACCURATE)
+ assert_parameters(IS_RTC_TIME_SubSECS(sTime->SubSeconds));
+ assert_parameters(IS_RTC_ACCURATESEL(AccurateSel));
+
+ subsec = sTime->SubSeconds;
+ subsec = subsec -(subsec>>8)*156 -((subsec&0xFF)>>4)*6;
+ sec = sTime->Seconds;
+ sec = sec - (sec>>4)*6;
+ subsec = sec * 32768 + subsec * 32768 / 1000;
+
+ alarmctl = RTC->ALARMCTL;
+ if (AccurateSel == RTC_ACCURATE)
+ alarmctl |= RTC_ALARMCTL_TIME_CNT_EN;
+ else
+ alarmctl &= ~RTC_ALARMCTL_TIME_CNT_EN;
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ /* Write RTC time registers */
+ RTC->TIME = subsec;
+ RTC->SEC = sTime->Seconds;
+ RTC->MIN = sTime->Minutes;
+ RTC->HOUR = sTime->Hours;
+ RTC->DAY = sTime->Date;
+ RTC->WEEK = sTime->WeekDay;
+ RTC->MON = sTime->Month;
+ RTC->YEAR = sTime->Year;
+ RTC->ALARMCTL = alarmctl;
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/**
+ * @brief Gets RTC current time.
+ * @param[out] gTime: Pointer to Time structure
+ * @param[in] AccurateSel:
+ * RTC_ACCURATE
+ * RTC_INACCURATE
+ * @retval None
+*/
+void RTC_GetTime(RTC_TimeTypeDef *gTime, uint32_t AccurateSel)
+{
+ __IO uint32_t dummy_data = 0;
+ uint32_t subsec,sec;
+
+ /* Parameter check */
+ assert_parameters(IS_RTC_ACCURATESEL(AccurateSel));
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+
+ /* Dummy read-operation to RTC->LOAD register */
+ dummy_data = RTC->LOAD;
+ dummy_data += 1;
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+
+ /* Read RTC time registers */
+ gTime->Seconds = RTC->SEC;
+ gTime->Minutes = RTC->MIN;
+ gTime->Hours = RTC->HOUR;
+ gTime->Date = RTC->DAY;
+ gTime->WeekDay = RTC->WEEK;
+ gTime->Month = RTC->MON;
+ gTime->Year = RTC->YEAR;
+ subsec = RTC->TIME;
+
+ if (AccurateSel == RTC_ACCURATE)
+ {
+ sec = subsec/32768;
+ sec = sec + (sec/10)*6;
+ gTime->Seconds = sec;
+ subsec = (subsec%32768)*1000/32768;
+ subsec = subsec + ((subsec%100)/10)*6 + (subsec/100)*156;
+ gTime->SubSeconds = subsec;
+ }
+ else
+ {
+ gTime->SubSeconds = 0;
+ }
+}
+
+/**
+ * @brief Enables or disables the RTC Sub Seconds.
+ * @param NewState:
+ * ENABLE
+ * DISABLE
+ * @retval None
+ */
+void RTC_SubSecondCmd(uint32_t NewState)
+{
+ uint32_t tmp;
+
+ /* Parameter check */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = RTC->ALARMCTL;
+ if (NewState == ENABLE)
+ {
+ tmp |= RTC_ALARMCTL_TIME_CNT_EN;
+ }
+ else
+ {
+ tmp &= ~RTC_ALARMCTL_TIME_CNT_EN;
+ }
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ RTC->ALARMCTL = tmp;
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/**
+ * @brief Sets the RTC Alarm.
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * AccurateSel:
+ * RTC_ACCURATE
+ * RTC_INACCURATE
+ * @retval None
+ */
+void RTC_SetAlarm(RTC_AlarmTypeDef *RTC_AlarmStruct, uint32_t AccurateSel)
+{
+ uint32_t subsec,sec,alarmctl;
+ /* Parameter check */
+ assert_parameters(IS_RTC_TIME_HOURS(RTC_AlarmStruct->AlarmHours));
+ assert_parameters(IS_RTC_TIME_MINS(RTC_AlarmStruct->AlarmMinutes));
+ assert_parameters(IS_RTC_TIME_SECS(RTC_AlarmStruct->AlarmSeconds));
+ if (AccurateSel == RTC_ACCURATE)
+ assert_parameters(IS_RTC_TIME_SubSECS(RTC_AlarmStruct->AlarmSubSeconds));
+ assert_parameters(IS_RTC_ACCURATESEL(AccurateSel));
+
+ subsec = RTC_AlarmStruct->AlarmSubSeconds;
+ subsec = subsec -(subsec>>8)*156 -((subsec&0xFF)>>4)*6;
+ sec = RTC_AlarmStruct->AlarmSeconds;
+ sec = sec - (sec>>4)*6;
+ subsec = sec * 32768 + subsec * 32768 / 1000;
+
+ alarmctl = RTC->ALARMCTL;
+ if (AccurateSel == RTC_ACCURATE)
+ alarmctl &= ~RTC_ALARMCTL_ALARM_INACCURATE;
+ else
+ alarmctl |= RTC_ALARMCTL_ALARM_INACCURATE;
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ RTC->ALARMHOUR = RTC_AlarmStruct->AlarmHours;
+ RTC->ALARMMIN = RTC_AlarmStruct->AlarmMinutes;
+ RTC->ALARMSEC = RTC_AlarmStruct->AlarmSeconds;
+ RTC->ALARMTIME = subsec;
+ RTC->ALARMCTL = alarmctl;
+ /* Write RTC time registers */
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/**
+ * @brief Gets the RTC Alarm.
+ * @param[out] RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will
+ * contains the output alarm configuration values.
+ * @param[in] AccurateSel:
+ * RTC_ACCURATE
+ * RTC_INACCURATE
+ * @retval None
+ */
+void RTC_GetAlarm(RTC_AlarmTypeDef *RTC_AlarmStruct, uint32_t AccurateSel)
+{
+ uint32_t sec,subsec;
+
+ /* Parameter check */
+ assert_parameters(IS_RTC_ACCURATESEL(AccurateSel));
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+
+ /* Read RTC time registers */
+ RTC_AlarmStruct->AlarmHours = RTC->ALARMHOUR;
+ RTC_AlarmStruct->AlarmMinutes = RTC->ALARMMIN;
+ RTC_AlarmStruct->AlarmSeconds = RTC->ALARMSEC;
+ subsec = RTC->ALARMTIME;
+
+ if (AccurateSel == RTC_ACCURATE)
+ {
+ sec = subsec/32768;
+ sec = sec + (sec/10)*6;
+ RTC_AlarmStruct->AlarmSeconds = sec;
+ subsec = (subsec%32768)*1000/32768;
+ subsec = subsec + ((subsec%100)/10)*6 + (subsec/100)*156;
+ RTC_AlarmStruct->AlarmSubSeconds = subsec;
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmSubSeconds = 0;
+ }
+}
+
+/**
+ * @brief Enables or disables the RTC Alarm.
+ * @param NewState:
+ * ENABLE
+ * DISABLE
+ * @retval None
+ */
+void RTC_AlarmCmd(uint32_t NewState)
+{
+ uint32_t tmp;
+ /* Parameter check */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = RTC->ALARMCTL;
+ if (NewState == ENABLE)
+ {
+ tmp |= (RTC_ALARMCTL_ALARM_EN);
+ }
+ else
+ {
+ tmp &= ~(RTC_ALARMCTL_ALARM_EN);
+ }
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ RTC->ALARMCTL = tmp;
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/**
+ * @brief Enables or disables the RTC alarm accurate.
+ * @param NewState:
+ * ENABLE
+ * DISABLE
+ * @retval None
+ */
+void RTC_AlarmAccurateCmd(uint32_t NewState)
+{
+ uint32_t tmp = 0;
+ /* Parameter check */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = RTC->ALARMCTL;
+ if (NewState == ENABLE)
+ {
+ tmp &= ~RTC_ALARMCTL_ALARM_INACCURATE;
+ }
+ else
+ {
+ tmp |= RTC_ALARMCTL_ALARM_INACCURATE;
+ }
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ RTC->ALARMCTL = tmp;
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/**
+ * @brief Enables or disables RTC interrupt.
+ * @param INTMask: can use the '|' operator
+ RTC_INT_ALARM
+ RTC_INT_CEILLE
+ RTC_INT_ACDONE
+ RTC_INT_WKUCNT
+ RTC_INT_MIDNIGHT
+ RTC_INT_WKUHOUR
+ RTC_INT_WKUMIN
+ RTC_INT_WKUSEC
+ RTC_INT_TIMEILLE
+ RTC_INT_ITVSITV
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void RTC_INTConfig(uint32_t INTMask, uint32_t NewState)
+{
+ /* Parameter check */
+ assert_parameters(IS_RTC_INT(INTMask));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ RTC->INTEN |= INTMask;
+ else
+ RTC->INTEN &= ~INTMask;
+}
+
+/**
+ * @brief Gets RTC interrupt status.
+ * @param INTMask:
+ RTC_INTSTS_ALARM
+ RTC_INTSTS_CEILLE
+ RTC_INTSTS_WKUCNT
+ RTC_INTSTS_MIDNIGHT
+ RTC_INTSTS_WKUHOUR
+ RTC_INTSTS_WKUMIN
+ RTC_INTSTS_WKUSEC
+ RTC_INTSTS_TIMEILLE
+ RTC_INTSTS_ITVSITV
+ * @retval 1: status set
+ 0: status reset.
+ */
+uint8_t RTC_GetINTStatus(uint32_t FlagMask)
+{
+ /* Parameter check */
+ assert_parameters(IS_RTC_INTFLAGR(FlagMask));
+
+ if (RTC->INTSTS&FlagMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears RTC interrupt status.
+ * @param INTMask: can use the '|' operator
+ RTC_INTSTS_ALARM
+ RTC_INTSTS_CEILLE
+ RTC_INTSTS_WKUCNT
+ RTC_INTSTS_MIDNIGHT
+ RTC_INTSTS_WKUHOUR
+ RTC_INTSTS_WKUMIN
+ RTC_INTSTS_WKUSEC
+ RTC_INTSTS_TIMEILLE
+ RTC_INTSTS_ITVSITV
+ * @retval None
+ */
+void RTC_ClearINTStatus(uint32_t FlagMask)
+{
+ /* Parameter check */
+ assert_parameters(IS_RTC_INTFLAGC(FlagMask));
+
+ RTC->INTSTS = FlagMask;
+}
+
+/*
+ * @brief Configures Multi-second wake up function.
+ * @param nPeriod£ºN seconds interval.
+ * @note For the first interrupt generated by calling this function, it may
+ * have < 1 sec error if the new WKUSEC number(parameter) is not equal
+ * to current WKUSEC number. If the new WKUSEC is equal to current WKUSEC,
+ * the first interrupt time may have 0~(WKUSEC +1) variation.
+ * To avoid this problem, set an alternative parameter (like 1) by calling
+ * this function, then set the correct parameter to it.
+ * @retval None
+ */
+void RTC_WKUSecondsConfig(uint8_t nPeriod)
+{
+ /* Parameter check */
+ assert_parameters(IS_RTC_WKUSEC_PERIOD(nPeriod));
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ /* Write registers */
+ RTC->WKUSEC = nPeriod - 1;
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/*
+ * @brief Configures Multi-minute wake up function.
+ * @param nPeriod£ºN minute interval.
+ * @note For the first interrupt generated by calling this function, it may
+ * have < 1 min error if the new WKUMIN number(parameter) is not equal
+ * to current WKUMIN number. If the new WKUMIN is equal to current WKUMIN,
+ * the first interrupt time may have 0~(WKUMIN +1) variation.
+ * To avoid this problem, set an alternative parameter (like 1) by calling
+ * this function, then set the correct parameter to it.
+ * @retval None
+ */
+void RTC_WKUMinutesConfig(uint8_t nPeriod)
+{
+ /* Parameter check */
+ assert_parameters(IS_RTC_WKUMIN_PERIOD(nPeriod));
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ /* Write registers */
+ RTC->WKUMIN = nPeriod - 1;
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/*
+ * @brief Configures Multi-hour wake up function.
+ * @param nPeriod£ºN hour interval.
+ * @note For the first interrupt generated by calling this function, it may
+ * have < 1 hour error if the new WKUHOUR number(parameter) is not equal
+ * to current WKUHOUR number. If the new WKUHOUR is equal to current WKUHOUR,
+ * the first interrupt time may have 0~(WKUHOUR +1) variation.
+ * To avoid this problem, set an alternative parameter (like 1) by calling
+ * this function, then set the correct parameter to it.
+ * @retval None
+ */
+void RTC_WKUHoursConfig(uint8_t nPeriod)
+{
+ /* Parameter check */
+ assert_parameters(IS_RTC_WKUHOUR_PERIOD(nPeriod));
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ /* Write registers */
+ RTC->WKUHOUR = nPeriod - 1;
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/**
+ * @brief Configures RTC counter wake up function.
+ * @param nClock:
+ CNTCLK:
+ RTC_WKUCNT_RTCCLK
+ RTC_WKUCNT_2048
+ RTC_WKUCNT_512
+ RTC_WKUCNT_128
+ * @retval None
+ */
+void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK)
+{
+ /* Parameter check */
+ assert_parameters(IS_RTC_WKUCNT_PERIOD(nClock));
+ assert_parameters(IS_RTC_WKUCNT_CNTSEL(CNTCLK));
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ /* Write registers */
+ RTC->WKUCNT = (CNTCLK & RTC_WKUCNT_CNTSEL) | ((nClock & RTC_WKUCNT_WKUCNT) -1 );
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/**
+ * @brief Configures RTC ITV wake up function.
+ * @param nType:
+ RTC_ITV_SEC
+ RTC_ITV_MIN
+ RTC_ITV_HOUR
+ RTC_ITV_DAY
+ RTC_ITV_500MS
+ RTC_ITV_250MS
+ RTC_ITV_125MS
+ RTC_ITV_62MS
+ * @retval None
+ */
+void RTC_WAKE_ITV(uint8_t nType)
+{
+ /* Parameter check */
+ assert_parameters(IS_RTC_ITV(nType));
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ RTC->ITV = nType;
+ RTC->SITV = 0;
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/**
+ * @brief Configures RTC SITV wake up function.
+ * @param nPeriod:1~63
+ * @retval None
+ */
+void RTC_WAKE_SITV(uint8_t nPeriod)
+{
+ /* Parameter check */
+ assert_parameters(IS_RTC_SITV(nPeriod));
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ RTC->ITV = RTC_ITV_SITVSEC;
+ RTC->SITV = RTC_SITV_SITVEN | (nPeriod - 1);
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/**
+ * @brief Gets RTC wake-up counter value.
+ * @retval RTC wake-up counter value
+ */
+uint32_t RTC_GetWKUCounterValue(void)
+{
+ return RTC->WKUCNTR;
+}
+
+/**
+ * @brief Configures RTC clock prescaler.
+ * @param[in] Prescaler:
+ * RTC_CLKDIV_1
+ * RTC_CLKDIV_4
+ * @retval None
+ */
+void RTC_PrescalerConfig(uint32_t Prescaler)
+{
+ uint32_t tmp;
+
+ /* Parameter check */
+ assert_parameters(IS_RTC_CLKDIV(Prescaler));
+
+ tmp = RTC->PSCA;
+ tmp &= ~RTC_PSCA_PSCA;
+ tmp |= Prescaler;
+
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+ /* Disable RTC Registers write-protection */
+ RTC_WriteProtection(DISABLE);
+
+ RTC->PSCA = tmp;
+
+ /* Enable RTC Registers write-protection */
+ RTC_WriteProtection(ENABLE);
+ /* Wait until the RTC registers be synchronized */
+ RTC_WaitForSynchro();
+}
+
+/**
+ * @brief Configures RTC PLLDIV clock-source and frequency.
+ * @param Source:
+ RTC_PLLDIVSOURCE_PLLL
+ RTC_PLLDIVSOURCE_PCLK
+ nfrequency(HZ): the frequency of RTC PLLDIV output configuration.
+ * @note Ensure clocks be configured by calling function CLK_ClockConfig(),
+ * get correct PCLK frequency by calling function CLK_GetPCLKFreq().
+ * @retval None
+ */
+void RTC_PLLDIVConfig(uint32_t DIVSource,uint32_t nfrequency)
+{
+ /* Parameter check */
+ assert_parameters(IS_RTC_PLLDIVSOURCE(DIVSource));
+
+ if (DIVSource == RTC_PLLDIVSOURCE_PLLL)
+ {
+ RTC->CTL |= RTC_CTL_RTCPLLCLKSEL;
+ if (nfrequency == 0)
+ {
+ RTC->DIV = RTC_DIV_RTCDIV;
+ }
+ else
+ {
+ RTC->DIV = CLK_GetPLLLFreq()/2/nfrequency - 1;
+ }
+ }
+ else
+ {
+ RTC->CTL &= ~RTC_CTL_RTCPLLCLKSEL;
+ if (nfrequency == 0)
+ {
+ RTC->DIV = RTC_DIV_RTCDIV;
+ }
+ else
+ {
+ RTC->DIV = CLK_GetPLLLFreq()/2/nfrequency - 1;
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables RTC PLLDIV output function.
+ * @param NewState:
+ * ENABLE
+ * DISABLE
+ * @retval None
+ */
+void RTC_PLLDIVOutputCmd(uint8_t NewState)
+{
+ /* Parameter check */
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE) RTC->CTL |= RTC_CTL_RTCPLLOE;
+ else RTC->CTL &= ~RTC_CTL_RTCPLLOE;
+}
+
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_spi.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_spi.c
new file mode 100644
index 0000000000000000000000000000000000000000..5da4a1e3d0f7756698493482e8ccdf046bbfff0c
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_spi.c
@@ -0,0 +1,433 @@
+/**
+ ******************************************************************************
+ * @file lib_spi.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief SPI library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_spi.h"
+
+#define SPI_MISC_RSTValue (0UL)
+
+/**
+ * @brief Initializes SPI peripheral registers to their default reset values(Reset SPI FIFO when this function is called).
+ * @param SPIx:SPI1~SPI3
+ * @retval None
+ */
+void SPI_DeviceInit(SPI_Type *SPIx)
+{
+ __IO uint32_t dummy_data = 0UL;
+
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+
+ /* Disable SPI */
+ SPIx->CTRL = 0;
+ /* SPI soft reset */
+ SPIx->CTRL |= SPI_CTRL_RST;
+ SPIx->CTRL &= ~SPI_CTRL_RST;
+ /* Clear flag */
+ dummy_data = SPIx->RXDAT;
+ dummy_data += 1;
+ SPIx->TXSTS = SPI_TXSTS_TXIF|SPI_TXSTS_DMATXDONE;
+ SPIx->RXSTS = SPI_RXSTS_RXIF;
+ /* write default values */
+ SPIx->MISC = SPI_MISC_RSTValue;
+}
+
+/**
+ * @brief Fills each SPI_InitType member with its default value.
+ * @param InitStruct: pointer to an SPI_InitType structure which will be initialized.
+ * @retval None
+ */
+void SPI_StructInit(SPI_InitType *InitStruct)
+{
+ /*--------------- Reset SPI init structure parameters values ---------------*/
+ /* Initialize the ClockDivision member */
+ InitStruct->ClockDivision = SPI_CLKDIV_2;
+ /* Initialize the CSNSoft member */
+ InitStruct->CSNSoft = SPI_CSNSOFT_DISABLE;
+ /* Initialize the Mode member */
+ InitStruct->Mode = SPI_MODE_MASTER;
+ /* Initialize the SPH member */
+ InitStruct->SPH = SPI_SPH_0;
+ /* Initialize the SPO member */
+ InitStruct->SPO = SPI_SPO_0;
+ /* Initialize the SWAP member */
+ InitStruct->SWAP = SPI_SWAP_DISABLE;
+}
+
+/**
+ * @brief Initializes SPI.
+ * @param SPIx:SPI1~SPI3
+ InitStruct: SPI configuration.
+ Mode:
+ SPI_MODE_MASTER
+ SPI_MODE_SLAVE
+ SPH:
+ SPI_SPH_0
+ SPI_SPH_1
+ SPO:
+ SPI_SPO_0
+ SPI_SPO_1
+ ClockDivision:
+ SPI_CLKDIV_2
+ SPI_CLKDIV_4
+ SPI_CLKDIV_8
+ SPI_CLKDIV_16
+ SPI_CLKDIV_32
+ SPI_CLKDIV_64
+ SPI_CLKDIV_128
+ CSNSoft:
+ SPI_CSNSOFT_ENABLE
+ SPI_CSNSOFT_DISABLE
+ SWAP:
+ SPI_SWAP_ENABLE
+ SPI_SWAP_DISABLE
+ * @retval None
+ */
+void SPI_Init(SPI_Type *SPIx, SPI_InitType *InitStruct)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+ assert_parameters(IS_SPI_MODE(InitStruct->Mode));
+ assert_parameters(IS_SPI_SPH(InitStruct->SPH));
+ assert_parameters(IS_SPI_SPO(InitStruct->SPO));
+ assert_parameters(IS_SPI_CLKDIV(InitStruct->ClockDivision));
+ assert_parameters(IS_SPI_CSN(InitStruct->CSNSoft));
+ assert_parameters(IS_SPI_SWAP(InitStruct->SWAP));
+
+ tmp = SPIx->CTRL;
+ tmp &= ~(SPI_CTRL_MOD\
+ |SPI_CTRL_SCKPHA\
+ |SPI_CTRL_SCKPOL\
+ |SPI_CTRL_CSGPIO\
+ |SPI_CTRL_SWAP\
+ |SPI_CTRL_SCKSEL);
+ tmp |= (InitStruct->Mode\
+ |InitStruct->SPH\
+ |InitStruct->SPO\
+ |InitStruct->CSNSoft\
+ |InitStruct->SWAP\
+ |InitStruct->ClockDivision);
+ SPIx->CTRL = tmp;
+}
+
+/**
+ * @brief Enables or disables SPI.
+ * @param SPIx:SPI1~SPI3
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void SPI_Cmd(SPI_Type *SPIx, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ SPIx->CTRL |= SPI_CTRL_EN;
+ else
+ SPIx->CTRL &= ~SPI_CTRL_EN;
+}
+
+/**
+ * @brief Enables or disables SPI interrupt.
+ * @param SPIx:SPI1~SPI3
+ INTMask: can use the '|' operator
+ SPI_INT_TX
+ SPI_INT_RX
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void SPI_INTConfig(SPI_Type *SPIx, uint32_t INTMask, uint32_t NewState)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+ assert_parameters(IS_SPI_INT(INTMask));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (INTMask & 0x80000000)
+ {
+ INTMask &= 0xFFFF;
+ tmp = SPIx->TXSTS;
+ tmp &= ~SPI_TXSTS_TXIF;
+ if (NewState == ENABLE)
+ {
+ tmp |= INTMask;
+ SPIx->TXSTS = tmp;
+ }
+ else
+ {
+ tmp &= ~INTMask;
+ SPIx->TXSTS = tmp;
+ }
+ }
+ if (INTMask & 0x40000000)
+ {
+ INTMask &= 0xFFFF;
+ tmp = SPIx->RXSTS;
+ tmp &= ~SPI_RXSTS_RXIF;
+ if (NewState == ENABLE)
+ {
+ tmp |= INTMask;
+ SPIx->RXSTS = tmp;
+ }
+ else
+ {
+ tmp &= ~INTMask;
+ SPIx->RXSTS = tmp;
+ }
+ }
+}
+
+/**
+ * @brief Gets SPI status flag.
+ * @param SPIx:SPI1~SPI3
+ Status:
+ SPI_STS_TXIF
+ SPI_STS_TXEMPTY
+ SPI_STS_TXFUR
+ SPI_STS_DMATXDONE
+ SPI_STS_RXIF
+ SPI_STS_RXFULL
+ SPI_STS_RXFOV
+ SPI_STS_BSY
+ SPI_STS_RFF
+ SPI_STS_RNE
+ SPI_STS_TNF
+ SPI_STS_TFE
+ * @retval Flag status.
+ */
+uint8_t SPI_GetStatus(SPI_Type *SPIx, uint32_t Status)
+{
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+ assert_parameters(IS_SPI_STSR(Status));
+
+ if ((Status&0xE0000000) == 0x80000000)
+ {
+ if (Status&SPIx->TXSTS)
+ return 1;
+ else
+ return 0;
+ }
+ else if ((Status&0xE0000000) == 0x40000000)
+ {
+ if (Status&SPIx->RXSTS)
+ return 1;
+ else
+ return 0;
+ }
+ else
+ {
+ if (Status&SPIx->MISC)
+ return 1;
+ else
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears SPI status flag.
+ * @param SPIx:SPI1~SPI3
+ Status: can use the '|' operator
+ SPI_STS_TXIF
+ SPI_STS_RXIF
+ SPI_STS_DMATXDONE
+ * @retval None
+ */
+void SPI_ClearStatus(SPI_Type *SPIx, uint32_t Status)
+{
+ uint32_t tmp = 0UL;
+
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+ assert_parameters(IS_SPI_STSC(Status));
+
+ if (Status & 0x80000000)
+ {
+ Status &= 0xFFFF;
+ tmp = SPIx->TXSTS;
+ tmp &= ~(SPI_TXSTS_DMATXDONE | SPI_TXSTS_TXIF);
+ tmp |= Status;
+ SPIx->TXSTS = tmp;
+ }
+ if (Status & 0x40000000)
+ {
+ Status &= 0xFFFF;
+ SPIx->RXSTS |= Status;
+ }
+}
+
+/**
+ * @brief Loads send data register.
+ * @param SPIx:SPI1~SPI3
+ ch: data write to send data register
+ * @retval None
+ */
+void SPI_SendData(SPI_Type *SPIx, uint8_t ch)
+{
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+
+ SPIx->TXDAT = ch;
+}
+
+/**
+ * @brief Reads receive data register.
+ * @param SPIx:SPI1~SPI3
+ * @retval receive data value
+ */
+uint8_t SPI_ReceiveData(SPI_Type *SPIx)
+{
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+
+ return (SPIx->RXDAT);
+}
+
+/**
+ * @brief Configures transmit fifo level.
+ * @param SPIx:SPI1~SPI3
+ FIFOLevel:
+ SPI_TXFLEV_0
+ SPI_TXFLEV_1
+ SPI_TXFLEV_2
+ SPI_TXFLEV_3
+ SPI_TXFLEV_4
+ SPI_TXFLEV_5
+ SPI_TXFLEV_6
+ SPI_TXFLEV_7
+ * @retval None
+ */
+void SPI_TransmitFIFOLevelConfig(SPI_Type *SPIx, uint32_t FIFOLevel)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+ assert_parameters(IS_SPI_TXFLEV(FIFOLevel));
+
+ tmp = SPIx->TXSTS;
+ tmp &= ~(SPI_TXSTS_TXFLEV | SPI_TXSTS_TXIF|SPI_TXSTS_DMATXDONE);
+ tmp |= FIFOLevel;
+ SPIx->TXSTS = tmp;
+}
+
+/**
+ * @brief Configures receive fifo level.
+ * @param SPIx:SPI1~SPI3
+ FIFOLevel:
+ SPI_RXFLEV_0
+ SPI_RXFLEV_1
+ SPI_RXFLEV_2
+ SPI_RXFLEV_3
+ SPI_RXFLEV_4
+ SPI_RXFLEV_5
+ SPI_RXFLEV_6
+ SPI_RXFLEV_7
+ * @retval None
+ */
+void SPI_ReceiveFIFOLevelConfig(SPI_Type *SPIx, uint32_t FIFOLevel)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+ assert_parameters(IS_SPI_RXFLEV(FIFOLevel));
+
+ tmp = SPIx->RXSTS;
+ tmp &= ~(SPI_RXSTS_RXFLEV | SPI_RXSTS_RXIF);
+ tmp |= FIFOLevel;
+ SPIx->RXSTS = tmp;
+}
+
+/**
+ * @brief Gets transmit fifo level.
+ * @param SPIx:SPI1~SPI3
+ * @retval Transmit fifo level.
+ */
+uint8_t SPI_GetTransmitFIFOLevel(SPI_Type *SPIx)
+{
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+
+ return (SPIx->TXSTS & SPI_TXSTS_TXFFLAG);
+}
+
+/**
+ * @brief Gets receive fifo level.
+ * @param SPIx:SPI1~SPI3
+ * @retval Receive fifo level.
+ */
+uint8_t SPI_GetReceiveFIFOLevel(SPI_Type *SPIx)
+{
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+
+ return (SPIx->RXSTS & SPI_RXSTS_RXFFLAG);
+}
+
+/**
+ * @brief Enables or disables FIFO smart mode.
+ * @param SPIx:SPI1~SPI3
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void SPI_SmartModeCmd(SPI_Type *SPIx, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ SPIx->MISC |= SPI_MISC_SMART;
+ }
+ else
+ {
+ SPIx->MISC &= ~SPI_MISC_SMART;
+ }
+}
+
+/**
+ * @brief Enables or disables FIFO over write mode.
+ * @param SPIx:SPI1~SPI3
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void SPI_OverWriteModeCmd(SPI_Type *SPIx, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ SPIx->MISC |= SPI_MISC_OVER;
+ }
+ else
+ {
+ SPIx->MISC &= ~SPI_MISC_OVER;
+ }
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_tmr.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_tmr.c
new file mode 100644
index 0000000000000000000000000000000000000000..9c1f0e401c9222c76a4f422cd883b19c14e8ef4e
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_tmr.c
@@ -0,0 +1,178 @@
+/**
+ ******************************************************************************
+ * @file lib_tmr.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Timer library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_tmr.h"
+
+#define TMR_CTRL_RSTValue (0UL)
+#define TMR_VALUE_RSTValue (0UL)
+#define TMR_RELOAD_RSTValue (0UL)
+
+/**
+ * @brief Initializes the timer peripheral registers to their default reset values.
+ * @param TMRx:
+ TMR0 ~ TMR3
+ * @retval None
+ */
+void TMR_DeInit(TMR_Type *TMRx)
+{
+ /* Check parameters */
+ assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
+
+ /* Disable timer */
+ TMRx->CTRL &= ~TMR_CTRL_EN;
+ /* clear interrupt status */
+ TMRx->INTSTS = TMR_INTSTS_INTSTS;
+ /* write default reset values */
+ TMRx->CTRL = TMR_CTRL_RSTValue;
+ TMRx->RELOAD = TMR_RELOAD_RSTValue;
+ TMRx->VALUE = TMR_VALUE_RSTValue;
+}
+
+/**
+ * @brief Initializes timer.
+ * @param TMRx:
+ TMR0 ~ TMR3
+ InitStruct: Timer configuration.
+ ClockSource:
+ TMR_CLKSRC_INTERNAL
+ TMR_CLKSRC_EXTERNAL
+ EXTGT:
+ TMR_EXTGT_DISABLE
+ TMR_EXTGT_ENABLE
+ Period: the auto-reload value
+ * @retval None
+ */
+void TMR_Init(TMR_Type *TMRx, TMR_InitType *InitStruct)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
+ assert_parameters(IS_TMR_CLKSRC(InitStruct->ClockSource));
+ assert_parameters(IS_TMR_EXTGT(InitStruct->EXTGT));
+
+ tmp = TMRx->CTRL;
+ tmp &= ~(TMR_CTRL_EXTCLK|TMR_CTRL_EXTEN);
+ tmp |= (InitStruct->ClockSource|InitStruct->EXTGT);
+ TMRx->CTRL = tmp;
+ TMRx->VALUE = InitStruct->Period;
+ TMRx->RELOAD = InitStruct->Period;
+}
+
+/**
+ * @brief Fills each TMR_InitType member with its default value.
+ * @param InitStruct: pointer to an TMR_InitType structure which will be initialized.
+ * @retval None
+ */
+void TMR_StructInit(TMR_InitType *InitStruct)
+{
+ /*--------------- Reset TMR init structure parameters values ---------------*/
+ /* Initialize the ClockSource member */
+ InitStruct->ClockSource = TMR_CLKSRC_INTERNAL;
+ /* Initialize the EXTGT member */
+ InitStruct->EXTGT = TMR_EXTGT_DISABLE;
+ /* Initialize the Period member */
+ InitStruct->Period = 0;
+}
+
+/**
+ * @brief Enables or disables timer interrupt.
+ * @param TMRx:
+ TMR0~TMR3
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void TMR_INTConfig(TMR_Type *TMRx, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ TMRx->CTRL |= TMR_CTRL_INTEN;
+ }
+ else
+ {
+ TMRx->CTRL &= ~TMR_CTRL_INTEN;
+ }
+}
+
+/**
+ * @brief Gets timer interrupt status.
+ * @param TMRx:
+ TMR0~TMR3
+ * @retval Interrupt status.
+ */
+uint8_t TMR_GetINTStatus(TMR_Type *TMRx)
+{
+ /* Check parameters */
+ assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
+
+ if (TMRx->INTSTS & TMR_INTSTS_INTSTS)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Clears timer interrupt status bit.
+ * @param TMRx:
+ TMR0~TMR3
+ * @retval None.
+ */
+void TMR_ClearINTStatus(TMR_Type *TMRx)
+{
+ /* Check parameters */
+ assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
+
+ TMRx->INTSTS = TMR_INTSTS_INTSTS;
+}
+
+/**
+ * @brief Enables or disables timer.
+ * @param TMRx:
+ TMR0~TMR3
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void TMR_Cmd(TMR_Type *TMRx, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ TMRx->CTRL |= TMR_CTRL_EN;
+ else
+ TMRx->CTRL &= ~TMR_CTRL_EN;
+}
+
+/**
+ * @brief Gets timer current value.
+ * @param TMRx:
+ TMR0~TMR3
+ * @retval timer value.
+ */
+uint32_t TMR_GetCurrentValue(TMR_Type *TMRx)
+{
+ /* Check parameters */
+ assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
+
+ return (TMRx->VALUE);
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_u32k.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_u32k.c
new file mode 100644
index 0000000000000000000000000000000000000000..825e144d77ff0c2a6bf88b33a4509fdeb7b4f5db
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_u32k.c
@@ -0,0 +1,309 @@
+/**
+ ******************************************************************************
+ * @file lib_u32k.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief UART 32K library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_u32k.h"
+
+#define U32K_STS_Msk (0x7UL)
+#define U32K_CTRL0_RSTValue (0UL)
+#define U32K_CTRL1_RSTValue (0UL)
+#define U32K_PHASE_RSTValue (0x4B00UL)
+
+/**
+ * @brief Initializes the U32Kx peripheral registers to their default reset values.
+ * @param U32Kx: U32K0~U32K1
+ * @retval None
+ */
+void U32K_DeInit(U32K_Type *U32Kx)
+{
+ /* Check parameters */
+ assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
+
+ /* Disable U32K */
+ U32Kx->CTRL0 &= ~U32K_CTRL0_EN;
+ /* clear interrupt status */
+ U32Kx->STS = U32K_STS_Msk;
+ /* write default reset values */
+ U32Kx->CTRL0 = U32K_CTRL0_RSTValue;
+ U32Kx->CTRL1 = U32K_CTRL1_RSTValue;
+ U32Kx->BAUDDIV = U32K_PHASE_RSTValue;
+}
+
+/**
+ * @brief Initializes U32K.
+ * @param U32Kx:
+ U32K0~U32K1
+ InitStruct: U32K configuration
+ Debsel:
+ U32K_DEBSEL_0
+ U32K_DEBSEL_1
+ U32K_DEBSEL_2
+ U32K_DEBSEL_3
+ Parity:
+ U32K_PARITY_EVEN
+ U32K_PARITY_ODD
+ U32K_PARITY_0
+ U32K_PARITY_1
+ U32K_PARITY_NONE
+ FirstBit:
+ U32K_FIRSTBIT_LSB
+ U32K_FIRSTBIT_MSB
+ AutoCal:
+ U32K_AUTOCAL_ON
+ U32K_AUTOCAL_OFF
+ LineSel:
+ U32K_LINE_RX0
+ U32K_LINE_RX1
+ U32K_LINE_RX2
+ U32K_LINE_RX3
+ Baudrate: Baudrate value, 300UL ~ 14400UL
+ * @retval None
+ */
+void U32K_Init(U32K_Type *U32Kx, U32K_InitType *InitStruct)
+{
+ uint32_t tmp_reg1, tmp_reg2;
+
+ /* Check parameters */
+ assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
+ assert_parameters(IS_U32K_DEBSEL(InitStruct->Debsel));
+ assert_parameters(IS_U32K_PARITY(InitStruct->Parity));
+ assert_parameters(IS_U32K_FIRSTBIT(InitStruct->FirstBit));
+ assert_parameters(IS_U32K_AUTOCAL(InitStruct->AutoCal));
+ assert_parameters(IS_U32K_LINE(InitStruct->LineSel));
+ assert_parameters(IS_U32K_BAUDRATE(InitStruct->Baudrate));
+
+ tmp_reg1 = U32Kx->CTRL0;
+ tmp_reg1 &= ~(U32K_CTRL0_DEBSEL\
+ |U32K_CTRL0_PMODE\
+ |U32K_CTRL0_MSB\
+ |U32K_CTRL0_ACOFF);
+ tmp_reg1 |= (InitStruct->Debsel\
+ |InitStruct->Parity\
+ |InitStruct->FirstBit\
+ |InitStruct->AutoCal);
+ U32Kx->CTRL0 = tmp_reg1;
+ if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_0) //RTCCLK 32768Hz
+ U32Kx->BAUDDIV = 65536*InitStruct->Baudrate/32768;
+ else if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_1) //RTCCLK 8192Hz
+ U32Kx->BAUDDIV = 65536*InitStruct->Baudrate/8192;
+ else
+ assert_parameters(0);
+
+ tmp_reg2 = U32Kx->CTRL1;
+ tmp_reg2 &= ~(U32K_CTRL1_RXSEL);
+ tmp_reg2 |= (InitStruct->LineSel);
+ U32Kx->CTRL1 = tmp_reg2;
+}
+
+/**
+ * @brief Fills each U32K_InitType member with its default value.
+ * @param InitStruct: pointer to an U32K_InitType structure which will be initialized.
+ * @retval None
+ */
+void U32K_StructInit(U32K_InitType *InitStruct)
+{
+ /*-------------- Reset U32K init structure parameters values ---------------*/
+ /* Initialize the AutoCal member */
+ InitStruct->AutoCal = U32K_AUTOCAL_ON;
+ /* Initialize the Baudrate member */
+ InitStruct->Baudrate = 9600;
+ /* Initialize the Debsel member */
+ InitStruct->Debsel = U32K_DEBSEL_0;
+ /* Initialize the FirstBit member */
+ InitStruct->FirstBit = U32K_FIRSTBIT_LSB;
+ /* Initialize the LineSel member */
+ InitStruct->LineSel = U32K_LINE_RX0;
+ /* Initialize the Parity member */
+ InitStruct->Parity = U32K_PARITY_NONE;
+}
+
+/**
+ * @brief Enables or disables U32K interrupt.
+ * @param U32Kx:
+ U32K0~U32K1
+ INTMask: can use the '|' operator
+ U32K_INT_RXOV
+ U32K_INT_RXPE
+ U32K_INT_RX
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void U32K_INTConfig(U32K_Type *U32Kx, uint32_t INTMask, uint8_t NewState)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
+ assert_parameters(IS_U32K_INT(INTMask));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = U32Kx->CTRL1;
+ tmp &= ~INTMask;
+ if (NewState == ENABLE)
+ {
+ tmp |= INTMask;
+ }
+ U32Kx->CTRL1 = tmp;
+}
+
+/**
+ * @brief Gets interrupt flag status.
+ * @param U32Kx:
+ U32K0~U32K1
+ INTMask:
+ U32K_INTSTS_RXOV
+ U32K_INTSTS_RXPE
+ U32K_INTSTS_RX
+ * @retval Flag status
+ */
+uint8_t U32K_GetINTStatus(U32K_Type *U32Kx, uint32_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
+ assert_parameters(IS_U32K_INTFLAGR(INTMask));
+
+ if (U32Kx->STS&INTMask)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * @brief Clears flag status.
+ * @param U32Kx:
+ U32K0~U32K1
+ INTMask: can use the '|' operator
+ U32K_INTSTS_RXOV
+ U32K_INTSTS_RXPE
+ U32K_INTSTS_RX
+ * @retval None
+ */
+void U32K_ClearINTStatus(U32K_Type *U32Kx, uint32_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
+ assert_parameters(IS_U32K_INTFLAGC(INTMask));
+
+ U32Kx->STS = INTMask;
+}
+
+/**
+ * @brief Reads receive data register.
+ * @param U32Kx:
+ U32K0~U32K1
+ * @retval Receive data value
+ */
+uint8_t U32K_ReceiveData(U32K_Type *U32Kx)
+{
+ /* Check parameters */
+ assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
+
+ return (U32Kx->DATA);
+}
+
+/**
+ * @brief Configures U32K baudrate.
+ * @param U32Kx: U32K0~U32K1
+ BaudRate: Baudrate value
+ * @retval None
+ */
+void U32K_BaudrateConfig(U32K_Type *U32Kx, uint32_t BaudRate)
+{
+ /* Check parameters */
+ assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
+ assert_parameters(IS_U32K_BAUDRATE(BaudRate));
+
+ if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_0) //RTCCLK 32768Hz
+ U32Kx->BAUDDIV = 65536*BaudRate/32768;
+ else if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_1) //RTCCLK 8192Hz
+ U32Kx->BAUDDIV = 65536*BaudRate/8192;
+ else
+ assert_parameters(0);
+}
+
+/**
+ * @brief Enables or disables U32K controlller.
+ * @param U32Kx:
+ U32K0~U32K1
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void U32K_Cmd(U32K_Type *U32Kx, uint32_t NewState)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ tmp = U32Kx->CTRL0;
+ tmp &= ~(U32K_CTRL0_EN);
+ if (NewState == ENABLE)
+ {
+ tmp |= U32K_CTRL0_EN;
+ }
+ U32Kx->CTRL0 = tmp;
+}
+
+/**
+ * @brief Configures U32K receive line.
+ * @param U32Kx:
+ U32K0~U32K1
+ Line:
+ U32K_LINE_RX0
+ U32K_LINE_RX1
+ U32K_LINE_RX2
+ U32K_LINE_RX3
+ * @retval None
+ */
+void U32K_LineConfig(U32K_Type *U32Kx, uint32_t Line)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
+ assert_parameters(IS_U32K_LINE(Line));
+
+ tmp = U32Kx->CTRL1;
+ tmp &= ~U32K_CTRL1_RXSEL_Msk;
+ tmp |= Line;
+
+ U32Kx->CTRL1 = tmp;
+}
+
+/**
+ * @brief Configures Wake-up mode.
+ * @param U32Kx:
+ U32K0~U32K1
+ WKUMode:
+ U32K_WKUMOD_RX
+ U32K_WKUMOD_PC
+ * @retval None
+ */
+void U32K_WKUModeConfig(U32K_Type *U32Kx, uint32_t WKUMode)
+{
+ uint32_t tmp;
+
+ /* Check parameters */
+ assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
+ assert_parameters(IS_U32K_WKUMODE(WKUMode));
+
+ tmp = U32Kx->CTRL0;
+ tmp &= ~U32K_CTRL0_WKUMODE_Msk;
+ tmp |= WKUMode;
+ U32Kx->CTRL0 = tmp;
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_uart.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_uart.c
new file mode 100644
index 0000000000000000000000000000000000000000..3af83facdc00e5841b41d5aad42a7d0a90aa0e25
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_uart.c
@@ -0,0 +1,372 @@
+/**
+ ******************************************************************************
+ * @file lib_uart.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief UART library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_uart.h"
+#include "lib_clk.h"
+
+#define UART_STATE_RCMsk (0xBCUL)
+#define UART_INTSTS_RCMsk (0x3FUL)
+#define UART_BAUDDIV_RSTValue (0UL)
+#define UART_CTRL_RSTValue (0UL)
+#define UART_CTRL2_RSTValue (0UL)
+
+/**
+ * @brief Iinitializes the UARTx peripheral registers to their default reset
+ values.
+ * @param UARTx: UART0~UART5
+ * @retval None
+ */
+void UART_DeInit(UART_Type *UARTx)
+{
+ __IO uint32_t dummy_data = 0UL;
+
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+
+ /* read data, clear RXFULL flag */
+ dummy_data = UARTx->DATA;
+ dummy_data += 1;
+
+ UARTx->INTSTS = UART_INTSTS_RCMsk;
+ UARTx->STATE = UART_STATE_RCMsk;
+ UARTx->BAUDDIV = UART_BAUDDIV_RSTValue;
+ UARTx->CTRL2 = UART_CTRL2_RSTValue;
+ UARTx->CTRL = UART_CTRL_RSTValue;
+}
+
+/**
+ * @brief Iinitializes UART.
+ * @param UARTx: UART0~UART5
+ InitStruct:UART configuration.
+ Mode: (between UART_MODE_RX and UART_MODE_TX, can use the '|' operator)
+ UART_MODE_RX
+ UART_MODE_TX
+ UART_MODE_OFF
+ Parity:
+ UART_PARITY_EVEN
+ UART_PARITY_ODD
+ UART_PARITY_0
+ UART_PARITY_1
+ UART_PARITY_NONE
+ FirstBit:
+ UART_FIRSTBIT_LSB
+ UART_FIRSTBIT_MSB
+ Baudrate: Baudrate value, 300UL ~ 819200UL
+ * @retval None
+ */
+void UART_Init(UART_Type *UARTx, UART_InitType *InitStruct)
+{
+ uint32_t pclk;
+ uint32_t div;
+ uint32_t tmp_reg1, tmp_reg2;
+
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+ assert_parameters(IS_UART_MODE(InitStruct->Mode));
+ assert_parameters(IS_UART_PARITY(InitStruct->Parity));
+ assert_parameters(IS_UART_FIRSTBIT(InitStruct->FirstBit));
+ assert_parameters(IS_UART_BAUDRATE(InitStruct->Baudrate));
+
+ tmp_reg1 = UARTx->CTRL;
+ tmp_reg1 &= ~(UART_CTRL_RXEN_Msk\
+ |UART_CTRL_TXEN_Msk);
+ tmp_reg1 |= (InitStruct->Mode);
+
+ tmp_reg2 = UARTx->CTRL2;
+ tmp_reg2 &= ~(UART_CTRL2_MSB_Msk \
+ |UART_CTRL2_PMODE_Msk);
+ tmp_reg2 |= (InitStruct->Parity\
+ |InitStruct->FirstBit);
+ UARTx->CTRL2 = tmp_reg2;
+
+ pclk = CLK_GetPCLKFreq();
+ div = pclk/InitStruct->Baudrate;
+
+ if ((pclk%InitStruct->Baudrate) > (InitStruct->Baudrate/2))
+ {
+ div++;
+ }
+
+ UARTx->BAUDDIV = div;
+ UARTx->CTRL = tmp_reg1;
+}
+
+/**
+ * @brief Fills each UART_InitType member with its default value.
+ * @param InitStruct: pointer to an UART_InitType structure which will be initialized.
+ * @retval None
+ */
+void UART_StructInit(UART_InitType *InitStruct)
+{
+ /*-------------- Reset UART init structure parameters values ---------------*/
+ /* Initialize the Baudrate member */
+ InitStruct->Baudrate = 9600;
+ /* Initialize the FirstBit member */
+ InitStruct->FirstBit = UART_FIRSTBIT_LSB;
+ /* Initialize the Mode member */
+ InitStruct->Mode = UART_MODE_OFF;
+ /* Initialize the Parity member */
+ InitStruct->Parity = UART_PARITY_NONE;
+}
+
+/**
+ * @brief Gets peripheral flag.
+ * @param UARTx: UART0~UART5
+ FlagMask: flag to get.
+ --UART_FLAG_DMATXDONE
+ --UART_FLAG_RXPARITY
+ --UART_FLAG_TXDONE
+ --UART_FLAG_RXPE
+ --UART_FLAG_RXOV
+ --UART_FLAG_TXOV
+ --UART_FLAG_RXFULL
+ * @retval 1:flag set
+ 0:flag reset
+ */
+uint8_t UART_GetFlag(UART_Type *UARTx, uint32_t FlagMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+ assert_parameters(IS_UART_FLAGR(FlagMask));
+
+ if (UARTx->STATE&FlagMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears peripheral flag.
+ * @param UARTx: UART0~UART5
+ FlagMask: status to clear, can use the '|' operator.
+ --UART_FLAG_DMATXDONE
+ --UART_FLAG_TXDONE
+ --UART_FLAG_RXPE
+ --UART_FLAG_RXOV
+ --UART_FLAG_TXOV
+ * @retval None
+ */
+void UART_ClearFlag(UART_Type *UARTx, uint32_t FlagMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+ assert_parameters(IS_UART_FLAGC(FlagMask));
+
+ UARTx->STATE = FlagMask;
+}
+
+/**
+ * @brief Enables or disables the specified UART interrupts.
+ * @param UARTx: UART0~UART5
+ INTMask: can use the '|' operator.
+ --UART_INT_TXDONE
+ --UART_INT_RXPE
+ --UART_INT_RXOV
+ --UART_INT_TXOV
+ --UART_INT_RX
+ NewState:New status of interrupt mask.
+ * @retval None
+ */
+void UART_INTConfig(UART_Type *UARTx, uint32_t INTMask, uint8_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+ assert_parameters(IS_UART_INT(INTMask));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ UARTx->CTRL |= INTMask;
+ }
+ else
+ {
+ UARTx->CTRL &= ~INTMask;
+ }
+}
+
+/**
+ * @brief Gets interrupt status.
+ * @param UARTx: UART0~UART5
+ INTMask: status to get.
+ --UART_INTSTS_TXDONE
+ --UART_INTSTS_RXPE
+ --UART_INTSTS_RXOV
+ --UART_INTSTS_TXOV
+ --UART_INTSTS_RX
+ * @retval 1:status set
+ 0:status reset
+ */
+uint8_t UART_GetINTStatus(UART_Type *UARTx, uint32_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+ assert_parameters(IS_UART_INTFLAGR(INTMask));
+
+ if (UARTx->INTSTS&INTMask)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Clears interrupt status.
+ * @param UARTx: UART0~UART5
+ INTMask: status to clear, can use the '|' operator.
+ --UART_INTSTS_TXDONE
+ --UART_INTSTS_RXPE
+ --UART_INTSTS_RXOV
+ --UART_INTSTS_TXOV
+ --UART_INTSTS_RX
+ * @retval None
+ */
+void UART_ClearINTStatus(UART_Type *UARTx, uint32_t INTMask)
+{
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+ assert_parameters(IS_UART_INTFLAGC(INTMask));
+
+ UARTx->INTSTS = INTMask;
+}
+
+/**
+ * @brief Loads send data register.
+ * @param UARTx: UART0~USART5
+ ch: data to send.
+ * @retval None
+ */
+void UART_SendData(UART_Type *UARTx, uint8_t ch)
+{
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+
+ UARTx->DATA = ch;
+}
+
+/**
+ * @brief Reads receive data register.
+ * @param UARTx: UART0~UART5
+ * @retval The received data.
+ */
+uint8_t UART_ReceiveData(UART_Type *UARTx)
+{
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+
+ return UARTx->DATA;
+}
+
+/**
+ * @brief Configures UART baudrate.
+ * @param UARTx: UART0~UART5
+ BaudRate: Baudrate value
+ * @retval None
+ */
+void UART_BaudrateConfig(UART_Type *UARTx, uint32_t BaudRate)
+{
+ uint32_t pclk;
+ uint32_t div;
+
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+ assert_parameters(IS_UART_BAUDRATE(BaudRate));
+
+ pclk = CLK_GetPCLKFreq();
+ div = pclk/BaudRate;
+ if ((pclk%BaudRate) > (BaudRate/2))
+ {
+ div++;
+ }
+
+ UARTx->BAUDDIV = div;
+}
+
+/**
+ * @brief Enables or disables UART Transmitter/Receiver.
+ * @param UARTx: UART0~UART5
+ Mode:
+ UART_MODE_RX
+ UART_MODE_TX
+ NewState:
+ ENABLE
+ DISABLE
+ * @retval None
+ */
+void UART_Cmd(UART_Type *UARTx, uint32_t Mode, uint32_t NewState)
+{
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+ assert_parameters(IS_UART_MODE(Mode));
+ assert_parameters(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ UARTx->CTRL |= Mode;
+ }
+ else
+ {
+ UARTx->CTRL &= ~Mode;
+ }
+}
+
+/**
+ * @brief Gets UART configure information.
+ * @param[in] UARTx: UART0~UART5
+ * @param[out] ConfigInfo: The pointer of UART configuration.
+ * @retval None
+ */
+void UART_GetConfigINFO(UART_Type *UARTx, UART_ConfigINFOType *ConfigInfo)
+{
+ uint32_t tmp1, tmp2, tmp3;
+ uint32_t pclk;
+
+ /* Check parameters */
+ assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
+
+ tmp1 = UARTx->CTRL;
+ tmp2 = UARTx->BAUDDIV;
+ pclk = CLK_GetPCLKFreq();
+ tmp3 = UARTx->CTRL2;
+
+ /* Mode_Transmit */
+ if (tmp1 & UART_CTRL_TXEN_Msk)
+ ConfigInfo->Mode_Transmit = 1;
+ else
+ ConfigInfo->Mode_Transmit = 0;
+
+ /* Mode_Receive */
+ if (tmp1 & UART_CTRL_RXEN_Msk)
+ ConfigInfo->Mode_Receive = 1;
+ else
+ ConfigInfo->Mode_Receive = 0;
+
+ /* Baudrate */
+ ConfigInfo->Baudrate = pclk / tmp2;
+
+ /* LSB/MSB */
+ if (tmp3 & UART_CTRL2_MSB_Msk)
+ ConfigInfo->FirstBit = 1;
+ else
+ ConfigInfo->FirstBit = 0;
+
+ /* Parity */
+ ConfigInfo->Parity = (tmp3 & UART_CTRL2_PMODE) >> UART_CTRL2_PMODE_Pos;
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_version.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_version.c
new file mode 100644
index 0000000000000000000000000000000000000000..2c723f6262de0e788e17b4c5a8e4aeb4f402e134
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_version.c
@@ -0,0 +1,25 @@
+/**
+*******************************************************************************
+ * @file lib_version.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief Version library.
+*******************************************************************************/
+#include "lib_version.h"
+
+#define Target_DriveVersion DRIVER_VERSION(1, 1)
+
+/**
+ * @brief Gets Target driver's current version.
+ * @param None
+ * @retval Version value
+ * Bit[15:8] : Major version
+ * Bit[7:0] : Minor version
+ */
+uint16_t Target_GetDriveVersion(void)
+{
+ return (Target_DriveVersion);
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_wdt.c b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_wdt.c
new file mode 100644
index 0000000000000000000000000000000000000000..00e47707be40b80ed9a7ff17a05e3cc2495773d0
--- /dev/null
+++ b/bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_wdt.c
@@ -0,0 +1,88 @@
+/**
+ ******************************************************************************
+ * @file lib_wdt.c
+ * @author Application Team
+ * @version V1.1.0
+ * @date 2019-10-28
+ * @brief WDT library.
+ ******************************************************************************
+ * @attention
+ *
+ ******************************************************************************
+ */
+#include "lib_wdt.h"
+
+#define WDTPASS_KEY 0xAA5555AA
+#define WDTCLR_KEY 0x55AAAA55
+
+/**
+ * @brief Enables WDT timer.
+ * @param None
+ * @retval None
+ */
+void WDT_Enable(void)
+{
+ PMU->WDTPASS = WDTPASS_KEY;
+ PMU->WDTEN |= PMU_WDTEN_WDTEN;
+
+ PMU->WDTPASS = WDTPASS_KEY;
+ PMU->WDTEN |= PMU_WDTEN_WDTEN;
+}
+
+/**
+ * @brief Disables WDT timer.
+ * @param None
+ * @retval None
+ */
+void WDT_Disable(void)
+{
+ PMU->WDTPASS = WDTPASS_KEY;
+ PMU->WDTEN &= ~PMU_WDTEN_WDTEN;
+
+ PMU->WDTPASS = WDTPASS_KEY;
+ PMU->WDTEN &= ~PMU_WDTEN_WDTEN;
+}
+
+/**
+ * @brief Clears WDT counter.
+ * @param None
+ * @retval None
+ */
+void WDT_Clear(void)
+{
+ PMU->WDTCLR = WDTCLR_KEY;
+}
+
+/**
+ * @brief Configures WDT counting period.
+ * @param counting period:
+ WDT_2_SECS
+ WDT_4_SECS
+ WDT_8_SECS
+ WDT_16_SECS
+ * @retval None
+ */
+void WDT_SetPeriod(uint32_t period)
+{
+ uint32_t tmp;
+
+ assert_parameters(IS_WDT_PERIOD(period));
+
+ tmp = PMU->WDTEN;
+ tmp &= ~PMU_WDTEN_WDTSEL;
+ tmp |= period;
+ PMU->WDTPASS = WDTPASS_KEY;
+ PMU->WDTEN = tmp;
+}
+
+/**
+ * @brief Gets WDT counter value.
+ * @param None
+ * @retval current counter value.
+ */
+uint16_t WDT_GetCounterValue(void)
+{
+ return (PMU->WDTCLR & PMU_WDTCLR_WDTCNT);
+}
+
+/*********************************** END OF FILE ******************************/
diff --git a/bsp/v85xxp/README.md b/bsp/v85xxp/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..f22b7e4f425ddf965ee6de43180b95c771f66cc3
--- /dev/null
+++ b/bsp/v85xxp/README.md
@@ -0,0 +1,77 @@
+# VANGOV85XXP-EVAL
+
+## 简介
+
+VANGOV85XXP-EVAL是-æ州万高科技推出的一款基于V85XXP的评估æ¿ï¼Œæ¿è½½èµ„æºä¸»è¦å¦‚下：
+
+| 硬件 | æè¿° |
+| --------- | ------------- |
+| èŠ¯ç‰‡åž‹å· | V8530P |
+| CPU | ARM Cortex M0 |
+| 主频 | 26M |
+| 片内SRAM | 64K |
+| 片内FLASH | 512K |
+
+## æ•°æ®æ‰‹å†Œ
+
+[产å“页é¢](http://www.vangotech.com/product.php?areas=0&bigs=1&smalls=4&id=65)
+[datasheet](http://www.vangotech.com/uploadpic/162798394156.pdf)
+
+## 编译说明
+
+VANGOV85XXP-EVALæ¿çº§åŒ…支æŒMDK4﹑MDK5﹑IARå¼€å‘环境和GCC编译器，以下是具体版本信æ¯ï¼š
+
+| IDE/编译器 | 已测试版本 |
+| ---------- | ---------------------------- |
+| GCC |gcc version 6.2.1 20161205 (release) |
+
+## 烧写åŠæ‰§è¡Œ
+
+供电方å¼ï¼šå¼€å‘æ¿ä½¿ç”¨ USB TypeA 接å£æˆ–者 DC-005 连接器æä¾› 5V 电æºã€‚
+
+下载程åºï¼šä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿éœ€è¦ä¸€å¥— JLink 或者使用 SD612 工具。
+
+串å£è¿žæŽ¥ï¼šä½¿ç”¨ä¸²å£çº¿è¿žæŽ¥åˆ°COM1(UART0)，或者使用USB转TTL模å—连接PA9(MCU TX)å’ŒPA10(MCU RX)。
+
+### è¿è¡Œç»“æžœ
+
+如果编译 & çƒ§å†™æ— è¯¯ï¼Œå½“å¤ä½è®¾å¤‡åŽï¼Œä¼šåœ¨ä¸²å£ä¸Šçœ‹åˆ°RT-Threadçš„å¯åŠ¨logoä¿¡æ¯ï¼š
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 4.0.3 build Jan 4 2021
+ 2006 - 2021 Copyright by rt-thread team
+msh />
+```
+## 驱动支æŒæƒ…况åŠè®¡åˆ’
+
+| 驱动 | 支æŒæƒ…况 | 备注 |
+| --------- | -------- | :------------------------: |
+| UART | æ”¯æŒ | UART0~5 |
+| GPIO | æ”¯æŒ | GPIOA~F |
+| ADC | æœªæ”¯æŒ | ADC0~7 |
+| HWTIMER | æœªæ”¯æŒ | TIMER0~3 |
+| RTC | æœªæ”¯æŒ | RTC |
+| WDT | æœªæ”¯æŒ | Free watchdog timer |
+| IIC | æœªæ”¯æŒ | I2C0 |
+| SPI | æœªæ”¯æŒ | SPI0~1 |
+| LCD | æœªæ”¯æŒ | |
+| SDRAM | æœªæ”¯æŒ | |
+| SPI FLASH | æœªæ”¯æŒ | |
+
+### IO在æ¿çº§æ”¯æŒåŒ…ä¸çš„æ˜ å°„æƒ…å†µ
+
+| IOå· | æ¿çº§åŒ…ä¸çš„定义 |
+| ---- | -------------- |
+| PC0 | LED1 |
+| PC2 | LED2 |
+| PE0 | LED3 |
+| PE1 | LED4 |
+| PA0 | KEY1 |
+| PC13 | KEY2 |
+| PB14 | KEY3 |
+
+## è”系人信æ¯
+
+维护人：[zhuxw-z](https://github.com/zhuxw-z)
diff --git a/bsp/v85xxp/SConscript b/bsp/v85xxp/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..fe0ae941ae9a759ae478de901caec1c961e56af8
--- /dev/null
+++ b/bsp/v85xxp/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/v85xxp/SConstruct b/bsp/v85xxp/SConstruct
new file mode 100644
index 0000000000000000000000000000000000000000..4c860d1e2b9782b64e2404b19c4156be241c1dfd
--- /dev/null
+++ b/bsp/v85xxp/SConstruct
@@ -0,0 +1,40 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rtthread-VangoV85xxP.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/v85xxp/Target_FLASH.ld b/bsp/v85xxp/Target_FLASH.ld
new file mode 100644
index 0000000000000000000000000000000000000000..3ec0c2499d9a1f8b5cda44f46340f20d26975511
--- /dev/null
+++ b/bsp/v85xxp/Target_FLASH.ld
@@ -0,0 +1,173 @@
+/*
+*****************************************************************************
+**
+
+** File : Target_FLASH.ld
+**
+** Abstract : Linker script for Target Device with
+** 512Byte FLASH, 64KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Date : 2019-10-28
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20010000; /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x400; /* required amount of heap */
+_Min_Stack_Size = 0x1000; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
+FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector : AT(0)
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ .chipinit_section : AT(0xC0)
+ {
+ . = ALIGN(4);
+ *(.chipinit_section) /* .text sections (code) */
+ *(.chipinit_section*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/bsp/v85xxp/Target_FLASH.sct b/bsp/v85xxp/Target_FLASH.sct
new file mode 100644
index 0000000000000000000000000000000000000000..6d104642301f52fb7e7bad48ea9a633d9d685688
--- /dev/null
+++ b/bsp/v85xxp/Target_FLASH.sct
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00008000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/v85xxp/applications/SConscript b/bsp/v85xxp/applications/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..ca2395451a1c167069eca74f37637dd6ed94c7d4
--- /dev/null
+++ b/bsp/v85xxp/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/v85xxp/applications/main.c b/bsp/v85xxp/applications/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..c0926c341c9b7d6848b3c570fbbd34615532b08d
--- /dev/null
+++ b/bsp/v85xxp/applications/main.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-01-04 iysheng first version
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "board.h"
+
+#define LED1 GET_PIN(C, 0)
+
+int main(void)
+{
+ rt_pin_mode(LED1, PIN_MODE_OUTPUT);
+
+ while (1)
+ {
+ rt_pin_write(LED1, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED1, PIN_LOW);
+ rt_thread_mdelay(500);
+ }
+
+ return 0;
+}
+
+#ifndef ASSERT_NDEBUG
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_errhandler error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_errhandler error line source number
+ * @retval None
+ */
+void assert_errhandler(uint8_t* file, uint32_t line)
+{
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+ /* Infinite loop */
+ while (1)
+ {
+ }
+}
+#endif
diff --git a/bsp/v85xxp/drivers/SConscript b/bsp/v85xxp/drivers/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..30a1a338d071383b6ac5fdb73c5d3ba618e0f6f6
--- /dev/null
+++ b/bsp/v85xxp/drivers/SConscript
@@ -0,0 +1,35 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'drivers')
+
+# add the general drivers.
+src = Split("""
+board.c
+""")
+
+CPPPATH = [cwd]
+
+# add uart drivers.
+if GetDepend('RT_USING_SERIAL'):
+ src += ['drv_usart.c']
+
+if GetDepend('RT_USING_PIN'):
+ src += ['drv_gpio.c']
+
+if GetDepend('RT_USING_ADC'):
+ src += ['drv_adc.c']
+
+if GetDepend('RT_USING_HWTIMER'):
+ src += ['drv_hwtimer.c']
+
+if GetDepend('RT_USING_RTC'):
+ src += ['drv_rtc.c']
+
+if GetDepend('RT_USING_WDT'):
+ src += ['drv_iwdt.c']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/v85xxp/drivers/board.c b/bsp/v85xxp/drivers/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..2e0f069d1a5568a8cb49d7c240a12ae6d7a09bd9
--- /dev/null
+++ b/bsp/v85xxp/drivers/board.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-01-04 iysheng first version
+ * 2021-09-07 FuC Suit for V85xx
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+uint32_t SystemCoreClock;
+/*
+ * System Clock Configuration
+ */
+void SystemClock_Config(void)
+{
+// SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+ NVIC_SetPriority(SysTick_IRQn, 0);
+ CLK_InitTypeDef CLK_Struct;
+
+ CLK_Struct.ClockType = CLK_TYPE_AHBSRC \
+ |CLK_TYPE_PLLL \
+ |CLK_TYPE_HCLK \
+ |CLK_TYPE_PCLK;
+ CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL;
+
+ CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz;
+ CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL;
+ CLK_Struct.PLLL.State = CLK_PLLL_ON;
+ CLK_Struct.HCLK.Divider = 1;
+ CLK_Struct.PCLK.Divider = 2;
+ CLK_ClockConfig(&CLK_Struct);
+
+ SystemCoreClock = 26214400UL;
+}
+
+/*
+ * This is the timer interrupt service routine.
+ */
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+/**
+ * This function will initial V85xx board.
+ */
+void rt_hw_board_init()
+{
+ SystemClock_Config();
+
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef BSP_USING_SDRAM
+ rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
+#else
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+}
+
+
+void rt_hw_us_delay(rt_uint32_t us)
+{
+ rt_uint32_t ticks;
+ rt_uint32_t told, tnow, tcnt = 0;
+ rt_uint32_t reload = SysTick->LOAD;
+
+ ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+ told = SysTick->VAL;
+ while (1)
+ {
+ tnow = SysTick->VAL;
+ if (tnow != told)
+ {
+ if (tnow < told)
+ {
+ tcnt += told - tnow;
+ }
+ else
+ {
+ tcnt += reload - tnow + told;
+ }
+ told = tnow;
+ if (tcnt >= ticks)
+ {
+ break;
+ }
+ }
+ }
+}
+
+/*@}*/
diff --git a/bsp/v85xxp/drivers/board.h b/bsp/v85xxp/drivers/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..c3ecc54a364f818916cd00ef32756ec15738584b
--- /dev/null
+++ b/bsp/v85xxp/drivers/board.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-01-04 iysheng first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include
+
+#include "drv_gpio.h"
+
+#define V85XX_SRAM_SIZE 32
+#define V85XX_SRAM_END (0x20000000 + V85XX_SRAM_SIZE * 1024)
+
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN (&__bss_end)
+#endif
+
+#define HEAP_END V85XX_SRAM_END
+
+#endif
diff --git a/bsp/v85xxp/drivers/drv_comm.h b/bsp/v85xxp/drivers/drv_comm.h
new file mode 100644
index 0000000000000000000000000000000000000000..5aef53cce2e0ace5e6c571bb3c39809b2947b0a6
--- /dev/null
+++ b/bsp/v85xxp/drivers/drv_comm.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-01-28 iysheng first version
+ */
+
+#ifndef __DRV_COMM_H__
+#define __DRV_COMM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_HWTIMER_H__ */
+
diff --git a/bsp/v85xxp/drivers/drv_gpio.c b/bsp/v85xxp/drivers/drv_gpio.c
new file mode 100644
index 0000000000000000000000000000000000000000..6711cb7dd0e87b25ac2200ddd8786e964ba3dfd2
--- /dev/null
+++ b/bsp/v85xxp/drivers/drv_gpio.c
@@ -0,0 +1,448 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-12-27 iysheng first version
+ * 2021-01-01 iysheng support exti interrupt
+ * 2021-09-07 FuC Suit for V85XX
+ * 2021-09-09 ZhuXW Add GPIO interrupt
+ * 2021-09-12 ZhuXW Suit for V85XXP
+*/
+
+#include
+#include "drv_gpio.h"
+
+#ifdef RT_USING_PIN
+
+#if defined(GPIOF)
+#define __V85XXP_PORT_MAX 6u
+#elif defined(GPIOE)
+#define __V85XXP_PORT_MAX 5u
+#elif defined(GPIOD)
+#define __V85XXP_PORT_MAX 4u
+#elif defined(GPIOC)
+#define __V85XXP_PORT_MAX 3u
+#elif defined(GPIOB)
+#define __V85XXP_PORT_MAX 2u
+#elif defined(GPIOA)
+#define __V85XXP_PORT_MAX 1u
+#else
+#define __V85XXP_PORT_MAX 0u
+#error Unsupported V85XXP GPIO peripheral.
+#endif
+
+#define PIN_V85XXPPORT_MAX __V85XXP_PORT_MAX
+#define PIN_V85XXPPORT_A 0u
+
+static const struct pin_irq_map pin_irq_map[] =
+{
+#if defined(SOC_SERIES_V85XXP)
+ {GPIO_Pin_0, PMU_IRQn},
+ {GPIO_Pin_1, PMU_IRQn},
+ {GPIO_Pin_2, PMU_IRQn},
+ {GPIO_Pin_3, PMU_IRQn},
+ {GPIO_Pin_4, PMU_IRQn},
+ {GPIO_Pin_5, PMU_IRQn},
+ {GPIO_Pin_6, PMU_IRQn},
+ {GPIO_Pin_7, PMU_IRQn},
+ {GPIO_Pin_8, PMU_IRQn},
+ {GPIO_Pin_9, PMU_IRQn},
+ {GPIO_Pin_10, PMU_IRQn},
+ {GPIO_Pin_11, PMU_IRQn},
+ {GPIO_Pin_12, PMU_IRQn},
+ {GPIO_Pin_13, PMU_IRQn},
+ {GPIO_Pin_14, PMU_IRQn},
+ {GPIO_Pin_15, PMU_IRQn},
+#else
+#error "Unsupported soc series"
+#endif
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+
+static rt_base_t V85XXP_pin_get(const char *name)
+{
+ rt_base_t pin = 0;
+ int hw_port_num, hw_pin_num = 0;
+ int i, name_len;
+
+ name_len = rt_strlen(name);
+
+ if ((name_len < 4) || (name_len >= 6))
+ {
+ return -RT_EINVAL;
+ }
+ if ((name[0] != 'P') || (name[2] != '.'))
+ {
+ return -RT_EINVAL;
+ }
+
+ if ((name[1] >= 'A') && (name[1] <= 'F'))
+ {
+ hw_port_num = (int)(name[1] - 'A');
+ }
+ else
+ {
+ return -RT_EINVAL;
+ }
+
+ for (i = 3; i < name_len; i++)
+ {
+ hw_pin_num *= 10;
+ hw_pin_num += name[i] - '0';
+ }
+
+ pin = PIN_NUM(hw_port_num, hw_pin_num);
+
+ return pin;
+}
+
+static void V85XXP_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+ GPIO_Type *gpio_port;
+ uint16_t gpio_pin;
+
+ if (PIN_PORT(pin) == PIN_V85XXPPORT_A)
+ {
+ gpio_pin = PIN_V85XXPPIN(pin);
+
+ GPIOA_WriteBit(GPIOA, gpio_pin, (BitState)value);
+ }
+ else if (PIN_PORT(pin) < PIN_V85XXPPORT_MAX)
+ {
+ gpio_port = PIN_V85XXPPORT(pin);
+ gpio_pin = PIN_V85XXPPIN(pin);
+
+ GPIOBToF_WriteBit(gpio_port, gpio_pin, (BitState)value);
+ }
+}
+
+static int V85XXP_pin_read(rt_device_t dev, rt_base_t pin)
+{
+ GPIO_Type *gpio_port;
+ uint16_t gpio_pin;
+ int value = PIN_LOW;
+
+ if (PIN_PORT(pin) == PIN_V85XXPPORT_A)
+ {
+ gpio_pin = PIN_V85XXPPIN(pin);
+ value = GPIOA_ReadInputDataBit(GPIOA, gpio_pin);
+ }
+ else if (PIN_PORT(pin) < PIN_V85XXPPORT_MAX)
+ {
+ gpio_port = PIN_V85XXPPORT(pin);
+ gpio_pin = PIN_V85XXPPIN(pin);
+ value = GPIOBToF_ReadInputDataBit(gpio_port, gpio_pin);
+ }
+
+ return value;
+}
+
+static void V85XXP_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+ GPIO_InitType GPIO_InitStruct = {0};
+
+ if (PIN_PORT(pin) >= PIN_V85XXPPORT_MAX)
+ {
+ return;
+ }
+
+ /* Configure GPIO_InitStructure */
+ GPIO_InitStruct.GPIO_Pin = PIN_V85XXPPIN(pin);
+ GPIO_InitStruct.GPIO_Mode = GPIO_MODE_INPUT;
+
+ switch (mode)
+ {
+ case PIN_MODE_OUTPUT:
+ GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS;
+ break;
+ case PIN_MODE_INPUT:
+ GPIO_InitStruct.GPIO_Mode = GPIO_MODE_INPUT;
+ break;
+ case PIN_MODE_INPUT_PULLUP:
+ GPIO_InitStruct.GPIO_Mode = GPIO_MODE_INOUT_CMOS;
+ break;
+ case PIN_MODE_INPUT_PULLDOWN:
+ GPIO_InitStruct.GPIO_Mode = GPIO_MODE_INOUT_OD;
+ break;
+ case PIN_MODE_OUTPUT_OD:
+ GPIO_InitStruct.GPIO_Mode = GPIO_MODE_INOUT_OD;
+ break;
+ default:
+ break;
+ }
+
+ if (PIN_PORT(pin) == PIN_V85XXPPORT_A)
+ {
+ GPIOA_Init(GPIOA, &GPIO_InitStruct);
+ }
+ else if (PIN_PORT(pin) < PIN_V85XXPPORT_MAX)
+ {
+ GPIOBToF_Init(PIN_V85XXPPORT(pin), &GPIO_InitStruct);
+ }
+}
+
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+ int i;
+ for (i = 0; i < 32; i++)
+ {
+ if ((0x01 << i) == bit)
+ {
+ return i;
+ }
+ }
+ return -1;
+}
+
+
+static rt_err_t V85XXP_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+ rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+ rt_base_t level;
+ rt_int32_t irqindex = -1;
+
+ if (PIN_PORT(pin) > PIN_V85XXPPORT_A)
+ {
+ return -RT_ENOSYS;
+ }
+
+ irqindex = bit2bitno(PIN_V85XXPPIN(pin));
+ if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+ {
+ return RT_ENOSYS;
+ }
+
+ level = rt_hw_interrupt_disable();
+ if (pin_irq_hdr_tab[irqindex].pin == pin &&
+ pin_irq_hdr_tab[irqindex].hdr == hdr &&
+ pin_irq_hdr_tab[irqindex].mode == mode &&
+ pin_irq_hdr_tab[irqindex].args == args)
+ {
+ rt_hw_interrupt_enable(level);
+ return RT_EOK;
+ }
+ if (pin_irq_hdr_tab[irqindex].pin != -1)
+ {
+ rt_hw_interrupt_enable(level);
+ return RT_EBUSY;
+ }
+ pin_irq_hdr_tab[irqindex].pin = pin;
+ pin_irq_hdr_tab[irqindex].hdr = hdr;
+ pin_irq_hdr_tab[irqindex].mode = mode;
+ pin_irq_hdr_tab[irqindex].args = args;
+ rt_hw_interrupt_enable(level);
+
+ return RT_EOK;
+}
+static rt_err_t V85XXP_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+ rt_base_t level;
+ rt_int32_t irqindex = -1;
+
+ if (PIN_PORT(pin) > PIN_V85XXPPORT_A)
+ {
+ return -RT_ENOSYS;
+ }
+
+ irqindex = bit2bitno(PIN_V85XXPPIN(pin));
+ if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+ {
+ return RT_ENOSYS;
+ }
+
+ level = rt_hw_interrupt_disable();
+ if (pin_irq_hdr_tab[irqindex].pin == -1)
+ {
+ rt_hw_interrupt_enable(level);
+ return RT_EOK;
+ }
+ pin_irq_hdr_tab[irqindex].pin = -1;
+ pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+ pin_irq_hdr_tab[irqindex].mode = 0;
+ pin_irq_hdr_tab[irqindex].args = RT_NULL;
+ rt_hw_interrupt_enable(level);
+
+ return RT_EOK;
+}
+static rt_err_t V85XXP_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+ const struct pin_irq_map *irqmap;
+ rt_base_t level;
+ rt_int32_t irqindex = -1;
+ GPIO_InitType GPIO_InitStruct = {0};
+
+ if (PIN_PORT(pin) > PIN_V85XXPPORT_A)
+ {
+ return -RT_ENOSYS;
+ }
+
+ GPIO_InitStruct.GPIO_Pin = PIN_V85XXPPIN(pin);
+ if (enabled == PIN_IRQ_ENABLE)
+ {
+ irqindex = bit2bitno(PIN_V85XXPPIN(pin));
+ if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+ {
+ return RT_ENOSYS;
+ }
+
+ level = rt_hw_interrupt_disable();
+
+ if (pin_irq_hdr_tab[irqindex].pin == -1)
+ {
+ rt_hw_interrupt_enable(level);
+ return RT_ENOSYS;
+ }
+
+ GPIO_InitStruct.GPIO_Mode = GPIO_MODE_INPUT;
+ GPIO_InitStruct.GPIO_Pin = PIN_V85XXPPIN(pin);
+ GPIOA_Init(GPIOA, &GPIO_InitStruct);
+
+ irqmap = &pin_irq_map[irqindex];
+
+ switch (pin_irq_hdr_tab[irqindex].mode)
+ {
+ case PIN_IRQ_MODE_RISING:
+ PMU_WakeUpPinConfig(PIN_V85XXPPIN(pin), IOA_RISING);
+ break;
+ case PIN_IRQ_MODE_FALLING:
+ PMU_WakeUpPinConfig(PIN_V85XXPPIN(pin), IOA_FALLING);
+ break;
+ case PIN_IRQ_MODE_RISING_FALLING:
+ PMU_WakeUpPinConfig(PIN_V85XXPPIN(pin), IOA_EDGEBOTH);
+ break;
+ case PIN_IRQ_MODE_HIGH_LEVEL:
+ PMU_WakeUpPinConfig(PIN_V85XXPPIN(pin), IOA_HIGH);
+ break;
+ case PIN_IRQ_MODE_LOW_LEVEL:
+ PMU_WakeUpPinConfig(PIN_V85XXPPIN(pin), IOA_LOW);
+ break;
+ default:
+ break;
+ }
+ PMU_INTConfig(PMU_INT_IOAEN, ENABLE);
+
+ NVIC_SetPriority(irqmap->irqno, 0);
+ NVIC_EnableIRQ(irqmap->irqno);
+ pin_irq_enable_mask |= irqmap->pinbit;
+
+ rt_hw_interrupt_enable(level);
+ }
+ else if (enabled == PIN_IRQ_DISABLE)
+ {
+
+ level = rt_hw_interrupt_disable();
+
+ PMU_INTConfig(PMU_INT_IOAEN, DISABLE);
+
+ NVIC_DisableIRQ(irqmap->irqno);
+
+ rt_hw_interrupt_enable(level);
+ }
+ else
+ {
+ return -RT_ENOSYS;
+ }
+ return RT_EOK;
+}
+
+
+
+const static struct rt_pin_ops _V85XXP_pin_ops =
+{
+ V85XXP_pin_mode,
+ V85XXP_pin_write,
+ V85XXP_pin_read,
+ V85XXP_pin_attach_irq,
+ V85XXP_pin_detach_irq,
+ V85XXP_pin_irq_enable,
+ V85XXP_pin_get,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+ if (pin_irq_hdr_tab[irqno].hdr)
+ {
+ pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+ }
+}
+
+
+void V85XXP_pin_exti_irqhandler()
+{
+ rt_base_t intsts=0;
+ int i=0;
+
+ intsts = PMU_GetIOAAllINTStatus();
+ for(i=0; i<16; i++)
+ {
+ if((1<
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __V85XXP_PORT(port) GPIO##port##_BASE
+
+#define GET_PIN(PORTx,PIN) (__V85XXP_PORT(PORTx)==GPIOA_BASE) ? (rt_base_t)(0 + PIN):(rt_base_t)((16 * ( ((rt_base_t)__V85XXP_PORT(PORTx) - (rt_base_t)GPIOB_BASE)/(0x0400UL) +1)) + PIN)
+
+#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
+#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
+#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
+
+#define PIN_V85XXPPORT(pin) ((GPIO_Type *)(GPIOB_BASE + (0x400u * PIN_PORT(pin))))
+#define PIN_V85XXPPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
+
+struct pin_irq_map
+{
+ rt_uint16_t pinbit;
+ IRQn_Type irqno;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
+
diff --git a/bsp/v85xxp/drivers/drv_usart.c b/bsp/v85xxp/drivers/drv_usart.c
new file mode 100644
index 0000000000000000000000000000000000000000..dd4a2bc87297120a08101cd9c1b38f5cef41837c
--- /dev/null
+++ b/bsp/v85xxp/drivers/drv_usart.c
@@ -0,0 +1,325 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-01-04 iysheng first version
+ * 2021-09-07 FuC Suit for V85xx
+ * 2021-09-12 ZhuXW Suit for V85xxP
+ */
+
+#include
+#include
+#include
+
+#ifdef RT_USING_SERIAL
+
+#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \
+ !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
+ !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5)
+ #error "Please define at least one UARTx"
+
+#endif
+
+#include
+
+static void uart_isr(struct rt_serial_device *serial);
+
+#if defined(BSP_USING_UART0)
+struct rt_serial_device serial0;
+
+void UART0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&serial0);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+struct rt_serial_device serial1;
+
+void UART1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&serial1);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+struct rt_serial_device serial2;
+
+void UART2_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&serial2);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+struct rt_serial_device serial3;
+
+void UART3_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&serial3);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+struct rt_serial_device serial4;
+
+void UART4_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&serial4);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+struct rt_serial_device serial5;
+
+void UART5_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&serial5);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART4 */
+
+static const struct V85xxP_uart uarts[] =
+{
+#ifdef BSP_USING_UART0
+ {
+ UART0, /* uart peripheral index */
+ UART0_IRQn, /* uart iqrn */
+ &serial0,
+ "uart0",
+ },
+#endif
+
+#ifdef BSP_USING_UART1
+ {
+ UART1, /* uart peripheral index */
+ UART1_IRQn, /* uart iqrn */
+ &serial1,
+ "uart1",
+ },
+#endif
+
+#ifdef BSP_USING_UART2
+ {
+ UART2, /* uart peripheral index */
+ UART2_IRQn, /* uart iqrn */
+ &serial2,
+ "uart2",
+ },
+#endif
+
+#ifdef BSP_USING_UART3
+ {
+ UART3, /* uart peripheral index */
+ UART3_IRQn, /* uart iqrn */
+ &serial3,
+ "uart3",
+ },
+#endif
+
+#ifdef BSP_USING_UART4
+ {
+ UART4, /* uart peripheral index */
+ UART4_IRQn, /* uart iqrn */
+ &serial4,
+ "uart4",
+ },
+#endif
+
+#ifdef BSP_USING_UART5
+ {
+ UART5, /* uart peripheral index */
+ UART5_IRQn, /* uart iqrn */
+ &serial5,
+ "uart5",
+ },
+#endif
+};
+
+static rt_err_t V85xxP_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+ struct V85xxP_uart *uart;
+ UART_Type *UARTx;
+ UART_InitType UART_InitParaStruct = {0};
+
+ UART_StructInit(&UART_InitParaStruct);
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+
+ uart = (struct V85xxP_uart *)serial->parent.user_data;
+
+ UARTx = (UART_Type *)uart->uart_periph;
+ UART_InitParaStruct.Baudrate = cfg->baud_rate;
+
+ if (cfg->data_bits == DATA_BITS_8)
+ {
+ UART_InitParaStruct.Parity = UART_PARITY_NONE;
+ }
+
+ switch (cfg->parity)
+ {
+ case PARITY_ODD:
+ UART_InitParaStruct.Parity = UART_PARITY_ODD;
+ break;
+ case PARITY_EVEN:
+ UART_InitParaStruct.Parity = UART_PARITY_EVEN;
+ break;
+ default:
+ UART_InitParaStruct.Parity = UART_PARITY_NONE;
+ break;
+ }
+
+ UART_InitParaStruct.Mode = UART_MODE_RX | UART_MODE_TX;
+ UART_Init(UARTx, &UART_InitParaStruct);
+ UART_Cmd(UARTx, UART_InitParaStruct.Mode, ENABLE);
+
+ return RT_EOK;
+}
+
+static rt_err_t V85xxP_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+ struct V85xxP_uart *uart;
+ UART_Type *UARTx;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = (struct V85xxP_uart *)serial->parent.user_data;
+ UARTx = (UART_Type *)uart->uart_periph;
+
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_CLR_INT:
+ /* disable rx irq */
+ NVIC_DisableIRQ(uart->irqn);
+ /* disable interrupt */
+ UART_INTConfig(UARTx, UART_INT_RX, DISABLE);
+ break;
+ case RT_DEVICE_CTRL_SET_INT:
+ /* enable rx irq */
+ NVIC_EnableIRQ(uart->irqn);
+ /* enable interrupt */
+ UART_INTConfig(UARTx, UART_INT_RX, ENABLE);
+ break;
+ }
+
+ return RT_EOK;
+}
+
+static int V85xxP_putc(struct rt_serial_device *serial, char ch)
+{
+ struct V85xxP_uart *uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = (struct V85xxP_uart *)serial->parent.user_data;
+
+ UART_SendData((UART_Type *)uart->uart_periph, ch);
+ while ((UART_GetFlag((UART_Type *)uart->uart_periph, UART_FLAG_TXDONE) == RESET));
+ UART_ClearFlag((UART_Type *)uart->uart_periph, UART_FLAG_TXDONE);
+ return 1;
+}
+
+static int V85xxP_getc(struct rt_serial_device *serial)
+{
+ int ch;
+ struct V85xxP_uart *uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = (struct V85xxP_uart *)serial->parent.user_data;
+
+ ch = -1;
+ if (UART_GetFlag((UART_Type *)uart->uart_periph, UART_FLAG_RXFULL) != RESET)
+ ch = UART_ReceiveData((UART_Type *)uart->uart_periph);
+ return ch;
+}
+
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void uart_isr(struct rt_serial_device *serial)
+{
+ struct V85xxP_uart *uart = (struct V85xxP_uart *) serial->parent.user_data;
+
+ RT_ASSERT(uart != RT_NULL);
+
+ if ((UART_GetINTStatus((UART_Type *)uart->uart_periph, UART_INTSTS_RX) != RESET) &&
+ (UART_GetFlag((UART_Type *)uart->uart_periph, UART_FLAG_RXFULL) != RESET))
+ {
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+ /* Clear RXNE interrupt flag */
+ UART_ClearINTStatus((UART_Type *)uart->uart_periph, UART_INTSTS_RX);
+ }
+}
+
+static const struct rt_uart_ops V85xxP_uart_ops =
+{
+ V85xxP_configure,
+ V85xxP_control,
+ V85xxP_putc,
+ V85xxP_getc,
+};
+
+int V85xxP_hw_usart_init(void)
+{
+ struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+ int i;
+
+
+ for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
+ {
+ uarts[i].serial->ops = &V85xxP_uart_ops;
+ uarts[i].serial->config = config;
+
+ /* register UART device */
+ rt_hw_serial_register(uarts[i].serial,
+ uarts[i].device_name,
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+ (void *)&uarts[i]);
+ }
+
+ return 0;
+}
+INIT_BOARD_EXPORT(V85xxP_hw_usart_init);
+#endif
diff --git a/bsp/v85xxp/drivers/drv_usart.h b/bsp/v85xxp/drivers/drv_usart.h
new file mode 100644
index 0000000000000000000000000000000000000000..f5b87183b5dfb3e7cc87cd17b85270aa5de9fdf1
--- /dev/null
+++ b/bsp/v85xxp/drivers/drv_usart.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-01-04 iysheng first version
+ * 2021-09-07 FuC Suit for V85xx
+ * 2021-09-12 ZhuXW Suit for V85xxP
+*/
+
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+
+#include
+#include
+
+/* V85XXP uart driver */
+struct V85xxP_uart {
+ UART_Type * uart_periph;
+ IRQn_Type irqn;
+
+ struct rt_serial_device *serial;
+ char *device_name;
+};
+
+#endif
diff --git a/bsp/v85xxp/keil_Kill.bat b/bsp/v85xxp/keil_Kill.bat
new file mode 100644
index 0000000000000000000000000000000000000000..ba17d320fe9e7ce4fd7f5f10ae8d57fb96a88220
--- /dev/null
+++ b/bsp/v85xxp/keil_Kill.bat
@@ -0,0 +1,37 @@
+@echo off
+set n=%USERNAME%
+del *.%n% /s
+
+del *.hex /s
+del *.bak /s
+del *.ddk /s
+del *.edk /s
+del *.lst /s
+del *.lnp /s
+del *.mpf /s
+del *.mpj /s
+del *.obj /s
+del *.omf /s
+del *.plg /s
+del *.rpt /s
+del *.tmp /s
+del *.__i /s
+del *.crf /s
+del *.o /s
+del *.d /s
+del *.axf /s
+del *.tra /s
+del *.dep /s
+del JLinkLog.txt /s
+del *.iex /s
+del *.htm /s
+rem del *.sct /s
+del *.map /s
+del *.ini /s
+del *.scvd /s
+
+for /r %%d in (.) do rd /s /q "%%d\Listings" 2>nul
+for /r %%d in (.) do rd /s /q "%%d\RTE" 2>nul
+for /r %%d in (.) do rd /s /q "%%d\Objects" 2>nul
+
+exit
diff --git a/bsp/v85xxp/project.uvoptx b/bsp/v85xxp/project.uvoptx
new file mode 100644
index 0000000000000000000000000000000000000000..71ca100f7725c6e1efba872fc798258b09260b2d
--- /dev/null
+++ b/bsp/v85xxp/project.uvoptx
@@ -0,0 +1,1288 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ Target 1
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 0
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
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+ 0
+
+
+ 79
+ 66
+ 8
+ .\Listings\
+
+
+ 1
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+ 0
+ 1
+
+
+
+
+
+
+
+
+
+
+ BIN\UL2CM3.DLL
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM))
+
+
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diff --git a/bsp/v85xxp/project.uvprojx b/bsp/v85xxp/project.uvprojx
new file mode 100644
index 0000000000000000000000000000000000000000..faacb17a3716abf505c0d4ac3e39b8de5aa6f8c6
--- /dev/null
+++ b/bsp/v85xxp/project.uvprojx
@@ -0,0 +1,871 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ Target 1
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::ARMCC
+ 0
+
+
+ V85XX
+ Generic
+ Vango.V85XX.4.0.2
+ IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM))
+ 0
+ $$Device:V85XX$Device\Include\V85XX.h
+
+
+
+
+
+
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+ $$Device:V85XX$SVD\V85XX.svd
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+
+ SARMCM3.DLL
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+ DARMCM1.DLL
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+ SARMCM3.DLL
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+ TARMCM1.DLL
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+
+ USE_STDPERIPH_DRIVER, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, USE_TARGET_DRIVER, RT_USING_ARM_LIBC, V85XXP
+
+ applications;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel;Libraries\CMSIS\Vango\V85xxP\Include;Libraries\CMSIS;Libraries\VangoV85xxP_standard_peripheral\Include
+
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+
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+
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+
+ context_rvds.S
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+
+
+
+
+ DeviceDrivers
+
+
+ pin.c
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+
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+
+
+
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+ Drivers
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+
+ drv_gpio.c
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+
+
+ drv_usart.c
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+ drivers\drv_usart.c
+
+
+ board.c
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+
+
+
+
+ Filesystem
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+
+ dfs_posix.c
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+
+
+ dfs_file.c
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+ poll.c
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+
+ dfs_fs.c
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+
+
+ devfs.c
+ 1
+ ..\..\components\dfs\filesystems\devfs\devfs.c
+
+
+
+
+ finsh
+
+
+ finsh_node.c
+ 1
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+
+
+ finsh_parser.c
+ 1
+ ..\..\components\finsh\finsh_parser.c
+
+
+ cmd.c
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+
+
+ finsh_vm.c
+ 1
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+
+
+ msh_file.c
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+
+
+ shell.c
+ 1
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+
+
+ finsh_var.c
+ 1
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+
+
+ finsh_compiler.c
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+
+
+ finsh_heap.c
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+
+
+ finsh_ops.c
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+
+ finsh_error.c
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+
+ msh.c
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+
+
+ finsh_token.c
+ 1
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+
+
+ finsh_init.c
+ 1
+ ..\..\components\finsh\finsh_init.c
+
+
+
+
+ Kernel
+
+
+ components.c
+ 1
+ ..\..\src\components.c
+
+
+ thread.c
+ 1
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+
+
+ mempool.c
+ 1
+ ..\..\src\mempool.c
+
+
+ mem.c
+ 1
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+
+
+ irq.c
+ 1
+ ..\..\src\irq.c
+
+
+ timer.c
+ 1
+ ..\..\src\timer.c
+
+
+ kservice.c
+ 1
+ ..\..\src\kservice.c
+
+
+ idle.c
+ 1
+ ..\..\src\idle.c
+
+
+ clock.c
+ 1
+ ..\..\src\clock.c
+
+
+ object.c
+ 1
+ ..\..\src\object.c
+
+
+ device.c
+ 1
+ ..\..\src\device.c
+
+
+ scheduler.c
+ 1
+ ..\..\src\scheduler.c
+
+
+ ipc.c
+ 1
+ ..\..\src\ipc.c
+
+
+
+
+ libc
+
+
+ stdio.c
+ 1
+ ..\..\components\libc\compilers\armlibc\stdio.c
+
+
+ syscalls.c
+ 1
+ ..\..\components\libc\compilers\armlibc\syscalls.c
+
+
+ libc.c
+ 1
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+
+
+ mem_std.c
+ 1
+ ..\..\components\libc\compilers\armlibc\mem_std.c
+
+
+ time.c
+ 1
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+
+
+ stdlib.c
+ 1
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+
+
+ delay.c
+ 1
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+
+
+ unistd.c
+ 1
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+
+
+
+
+ Vango_Lib
+
+
+ lib_wdt.c
+ 1
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+
+
+ lib_cmp.c
+ 1
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+
+
+ lib_rtc.c
+ 1
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_rtc.c
+
+
+ lib_lcd.c
+ 1
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_lcd.c
+
+
+ lib_misc.c
+ 1
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+
+
+ lib_adc_tiny.c
+ 1
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+
+
+ lib_pmu.c
+ 1
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+
+
+ lib_pwm.c
+ 1
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_pwm.c
+
+
+ lib_gpio.c
+ 1
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+
+
+ lib_CodeRAM.c
+ 1
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+
+
+ lib_adc.c
+ 1
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+
+
+ lib_version.c
+ 1
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+
+
+ lib_dma.c
+ 1
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+
+
+ lib_LoadNVR.c
+ 1
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+
+ lib_crypt.c
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+
+ lib_uart.c
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+
+ startup_target.S
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+ lib_iso7816.c
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+ lib_clk.c
+ 1
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_clk.c
+
+
+ lib_tmr.c
+ 1
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_tmr.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/bsp/v85xxp/rtconfig.h b/bsp/v85xxp/rtconfig.h
new file mode 100644
index 0000000000000000000000000000000000000000..ed395ed2ada09fca9c4b63bce3b89b49089bef9c
--- /dev/null
+++ b/bsp/v85xxp/rtconfig.h
@@ -0,0 +1,164 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x40003
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#define SOC_SERIES_V85XXP
+#define SOC_V85XXP
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define BSP_USING_UART0
+
+#endif
diff --git a/bsp/v85xxp/rtconfig.py b/bsp/v85xxp/rtconfig.py
new file mode 100644
index 0000000000000000000000000000000000000000..22c83aa6ef4d7dfb3715dbb65a8f98e626548e5b
--- /dev/null
+++ b/bsp/v85xxp/rtconfig.py
@@ -0,0 +1,126 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+ PLATFORM = 'iar'
+ EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # tool-chains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
+ CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-v85xxp.map,-cref,-u,Reset_Handler -T Target_FLASH.ld'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2 -g'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --cpu Cortex-M0'
+ CFLAGS = DEVICE + ' --apcs=interwork'
+ AFLAGS = DEVICE
+ LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-v85xxp.map --scatter Target_FLASH.sct'
+
+ LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)'
+
+ EXEC_PATH += '/ARM/ARMCC/bin'
+ print(EXEC_PATH)
+
+ CFLAGS += ' --c99'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D VANGOV85XXPDEV'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --debug'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M0'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=None'
+ CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' -Ol'
+ CFLAGS += ' --use_c++_inline'
+
+ AFLAGS = ''
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M0'
+ AFLAGS += ' --fpu None'
+
+ LFLAGS = ' --config Target_FLASH.icf'
+ LFLAGS += ' --redirect _Printf=_PrintfTiny'
+ LFLAGS += ' --redirect _Scanf=_ScanfSmall'
+ LFLAGS += ' --entry __iar_program_start'
+
+ EXEC_PATH += '/arm/bin/'
+ POST_ACTION = ''
+
diff --git a/bsp/v85xxp/template.uvoptx b/bsp/v85xxp/template.uvoptx
new file mode 100644
index 0000000000000000000000000000000000000000..83cd4925762701225227ae5fe5aed86a7b1edca7
--- /dev/null
+++ b/bsp/v85xxp/template.uvoptx
@@ -0,0 +1,180 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ Target 1
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 0
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\Listings\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 0
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+
+
+
+
+
+
+
+
+
+
+ BIN\UL2CM3.DLL
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM))
+
+
+
+
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+ Source Group 1
+ 0
+ 0
+ 0
+ 0
+
+
+
diff --git a/bsp/v85xxp/template.uvprojx b/bsp/v85xxp/template.uvprojx
new file mode 100644
index 0000000000000000000000000000000000000000..b26c9a0261ffb322d1d2f5584fe7be95d0334bf0
--- /dev/null
+++ b/bsp/v85xxp/template.uvprojx
@@ -0,0 +1,393 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ Target 1
+ 0x4
+ ARM-ADS
+ 0
+
+
+ V85XX
+ Generic
+ Vango.V85XX.4.0.2
+ IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM))
+ 0
+ $$Device:V85XX$Device\Include\V85XX.h
+
+
+
+
+
+
+
+
+
+ $$Device:V85XX$SVD\V85XX.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\Objects\
+ template
+ 1
+ 0
+ 0
+ 1
+ 1
+ .\Listings\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+
+ DARMCM1.DLL
+ -pCM0
+ SARMCM3.DLL
+
+ TARMCM1.DLL
+ -pCM0
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ -1
+
+ 1
+ BIN\UL2CM3.DLL
+
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M0"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 8
+ 0
+ 0
+ 0
+ 0
+ 3
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x8000
+
+
+ 1
+ 0x0
+ 0x40000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x40000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x8000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 2
+ 0
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ Source Group 1
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/device.c b/src/device.c
index 9bfaf776d600cc557358748111575f9aa9ec5c1c..4e1abbeb6f25c96ce5a23f4187248239bb0f9b61 100644
--- a/src/device.c
+++ b/src/device.c
@@ -307,7 +307,7 @@ RTM_EXPORT(rt_device_close);
*
* @param size is the size of buffer.
*
- * @return the actually read size on successful, otherwise negative returned.
+ * @return the actually read size on successful, otherwise zero returned.
*
* @note since 0.4.0, the unit of size/pos is a block for block device.
*/
@@ -350,7 +350,7 @@ RTM_EXPORT(rt_device_read);
*
* @param size is the size of buffer.
*
- * @return the actually written size on successful, otherwise negative returned.
+ * @return the actually written size on successful, otherwise zero returned.
*
* @note since 0.4.0, the unit of size/pos is a block for block device.
*/