From 592284c66c8a93270cb77cb2a0afb36b64d2bc51 Mon Sep 17 00:00:00 2001
From: Meco Man <920369182@qq.com>
Date: Sun, 8 Jan 2023 21:16:47 -0500
Subject: [PATCH] format link scripts
---
bsp/CME_M7/CME_M7.sct | 44 +-
.../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 544 ++--
.../TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf | 506 +--
.../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 554 ++--
.../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 494 +--
.../TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct | 584 ++--
.../TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct | 622 ++--
.../TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct | 622 ++--
.../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 622 ++--
.../TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct | 622 ++--
.../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 622 ++--
.../TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct | 576 ++--
.../TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct | 614 ++--
.../TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct | 614 ++--
.../TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct | 590 ++--
.../TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct | 628 ++--
.../TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct | 628 ++--
.../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 628 ++--
.../TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct | 628 ++--
.../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 628 ++--
.../TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct | 596 ++--
.../TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct | 634 ++--
.../TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct | 634 ++--
.../TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct | 506 +--
.../TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct | 544 ++--
.../TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct | 544 ++--
.../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 544 ++--
.../TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct | 544 ++--
.../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 544 ++--
.../TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct | 488 +--
.../TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct | 526 +--
.../TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct | 526 +--
.../TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf | 4 +-
.../TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf | 4 +-
.../TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf | 4 +-
.../TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf | 4 +-
.../TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf | 4 +-
.../TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf | 4 +-
.../TOOLCHAIN_ARM/cy8c6xx4_cm4.sct | 480 +--
.../TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct | 516 +--
.../TOOLCHAIN_ARM/cy8c6xx5_cm4.sct | 518 +--
.../TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct | 554 ++--
.../TOOLCHAIN_ARM/cy8c6xx6_cm4.sct | 518 +--
.../TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct | 554 ++--
.../TOOLCHAIN_ARM/cy8c6xx7_cm4.sct | 518 +--
.../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 554 ++--
.../cy8c6xx7_cm4_dual_cm0p_bless.sct | 560 ++--
.../TOOLCHAIN_ARM/cy8c6xx8_cm4.sct | 518 +--
.../TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct | 554 ++--
.../TOOLCHAIN_ARM/cy8c6xxa_cm4.sct | 518 +--
.../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 554 ++--
.../TOOLCHAIN_ARM/cyb06xx5_cm4.sct | 266 +-
.../TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct | 294 +-
.../TOOLCHAIN_ARM/cyb06xx7_cm4.sct | 296 +-
.../TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct | 324 +-
.../TOOLCHAIN_ARM/cyb06xxa_cm4.sct | 296 +-
.../TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct | 324 +-
.../TOOLCHAIN_ARM/cys06xxa_cm4.sct | 296 +-
.../TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct | 318 +-
.../TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct | 326 +-
.../PSOC62/board/linker_scripts/link.icf | 494 +--
.../PSOC62/board/linker_scripts/link.sct | 554 ++--
.../board/linker_scripts/link.icf | 494 +--
.../board/linker_scripts/link.sct | 554 ++--
.../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 548 ++--
.../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 480 +--
bsp/Vango/v85xx/Target_FLASH.icf | 2 +-
.../drivers/linker_scripts/link.icf | 68 +-
.../drivers/linker_scripts/link.icf | 68 +-
.../air105/board/linker_scripts/link.lds | 4 +-
.../air32f103/board/linker_scripts/link.icf | 2 +-
.../air32f103/board/linker_scripts/link.lds | 8 +-
bsp/allwinner/d1/link.lds | 20 +-
bsp/allwinner/d1/link_stacksize.lds | 2 +-
bsp/allwinner/d1s/link.lds | 18 +-
bsp/allwinner/d1s/link_stacksize.lds | 2 +-
bsp/allwinner_tina/link.lds | 80 +-
bsp/amebaz/bootloader_symbol.icf | 26 +-
bsp/amebaz/image2.icf | 140 +-
bsp/amebaz/rom_symbol_v01_iar.icf | 2848 ++++++++---------
.../board/linker_scripts/link.lds | 16 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 8 +-
.../startup/iar/linker/AT32F403AxC.icf | 2 +-
.../startup/iar/linker/AT32F403AxE.icf | 2 +-
.../startup/iar/linker/AT32F403AxG.icf | 2 +-
.../startup/iar/linker/AT32F407xC.icf | 2 +-
.../startup/iar/linker/AT32F407xE.icf | 2 +-
.../startup/iar/linker/AT32F407xG.icf | 2 +-
.../startup/iar/linker/AT32F413x8.icf | 2 +-
.../startup/iar/linker/AT32F413xB.icf | 2 +-
.../startup/iar/linker/AT32F413xC.icf | 2 +-
.../startup/iar/linker/AT32F415x8.icf | 2 +-
.../startup/iar/linker/AT32F415xB.icf | 2 +-
.../startup/iar/linker/AT32F415xC.icf | 2 +-
.../startup/iar/linker/AT32F435xC.icf | 2 +-
.../startup/iar/linker/AT32F435xG.icf | 2 +-
.../startup/iar/linker/AT32F435xM.icf | 2 +-
.../startup/iar/linker/AT32F437xC.icf | 2 +-
.../startup/iar/linker/AT32F437xG.icf | 2 +-
.../startup/iar/linker/AT32F437xM.icf | 2 +-
bsp/avr32uc3b0/avr32elf_uc3b0256.lds | 18 +-
bsp/beaglebone/beaglebone_ram.icf | 2 +-
bsp/beaglebone/beaglebone_ram.lds | 2 +-
bsp/bl808/m0/link_stacksize.lds | 2 +-
bsp/bm3803/bm3803.lds | 2 +-
.../es32f365x/drivers/linker_scripts/link.icf | 8 +-
.../es32f369x/drivers/linker_scripts/link.icf | 8 +-
.../es32f369x/drivers/linker_scripts/link.lds | 4 +-
bsp/frdm-k64f/MK64F.sct | 28 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../mb9x/mb9bf506r/rtthread-mb9bf506.icf | 2 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../RISCV/env_Eclipse/GD32VF103x4.lds | 64 +-
.../RISCV/env_Eclipse/GD32VF103x6.lds | 66 +-
.../RISCV/env_Eclipse/GD32VF103x8.lds | 66 +-
.../RISCV/env_Eclipse/GD32VF103xB.lds | 56 +-
.../board/linker_script/gd32_rom.icf | 4 +-
.../board/linker_script/gd32_rom.icf | 4 +-
bsp/gd32303e-eval/gd32_rom.icf | 4 +-
bsp/gd32350r-eval/gd32_rom.icf | 4 +-
bsp/gd32450z-eval/gd32_rom.icf | 4 +-
bsp/gd32e230k-start/gd32_rom.icf | 4 +-
.../libraries/n22/env_Eclipse/GD32VF103x4.lds | 64 +-
.../libraries/n22/env_Eclipse/GD32VF103x6.lds | 66 +-
.../libraries/n22/env_Eclipse/GD32VF103x8.lds | 66 +-
.../libraries/n22/env_Eclipse/GD32VF103xB.lds | 60 +-
.../n22/env_Eclipse/GD32VF103xB_I2S.lds | 72 +-
.../config/linker/HC32F460_ram.icf | 2 +-
.../hc32f460_ddl/config/linker/HC32F460xC.icf | 2 +-
.../hc32f460_ddl/config/linker/HC32F460xE.icf | 2 +-
.../Source/IAR/linker/HC32F460_RAM.icf | 2 +-
.../hc32f4xx/Source/IAR/linker/HC32F460xC.icf | 2 +-
.../hc32f4xx/Source/IAR/linker/HC32F460xE.icf | 2 +-
.../config/linker/HC32F4A0_RAM.icf | 2 +-
.../hc32f4a0_ddl/config/linker/HC32F4A0xG.icf | 2 +-
.../hc32f4a0_ddl/config/linker/HC32F4A0xI.icf | 2 +-
.../Source/IAR/linker/HC32F4A0_RAM.icf | 2 +-
.../hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf | 2 +-
.../hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf | 2 +-
bsp/hc32l136/board/linker_scripts/link.icf | 2 +-
bsp/hc32l196/board/linker_scripts/link.lds | 4 +-
.../bsp/env/coreplexip-e31-arty/flash.lds | 2 +-
.../bsp/env/coreplexip-e51-arty/flash.lds | 2 +-
.../env/coreplexip-e51-arty/scratchpad.lds | 2 +-
.../bsp/env/freedom-e300-arty/flash.lds | 2 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 8 +-
.../soc/HPM6360/toolchains/segger/flash.icf | 178 +-
.../toolchains/segger/flash_sdram_uf2.icf | 170 +-
.../toolchains/segger/flash_sdram_xip.icf | 196 +-
.../HPM6360/toolchains/segger/flash_uf2.icf | 174 +-
.../HPM6360/toolchains/segger/flash_xip.icf | 196 +-
.../soc/HPM6360/toolchains/segger/ram.icf | 156 +-
.../soc/HPM6750/toolchains/segger/flash.icf | 178 +-
.../toolchains/segger/flash_sdram_uf2.icf | 170 +-
.../toolchains/segger/flash_sdram_xip.icf | 192 +-
.../HPM6750/toolchains/segger/flash_uf2.icf | 184 +-
.../HPM6750/toolchains/segger/flash_xip.icf | 206 +-
.../soc/HPM6750/toolchains/segger/ram.icf | 158 +-
.../HPM6750/toolchains/segger/ram_core1.icf | 158 +-
.../board/linker_scripts/link.icf | 254 +-
.../board/linker_scripts/link.lds | 2 +-
.../board/linker_scripts/link.sct | 268 +-
.../board/linker_scripts/link.lds | 2 +-
.../board/linker_scripts/link.sct | 16 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.lds | 2 +-
.../board/linker_scripts/link.sct | 44 +-
.../board/linker_scripts/link.lds | 2 +-
.../board/linker_scripts/link.sct | 16 +-
.../board/linker_scripts/link.lds | 2 +-
.../board/linker_scripts/link.lds | 2 +-
.../board/linker_scripts/link.sct | 26 +-
.../iar/MIMXRT1021xxxxx_flexspi_nor.icf | 186 +-
.../iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf | 202 +-
.../MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf | 162 +-
.../MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf | 178 +-
.../iar/MIMXRT1021xxxxx_sdram_txt.icf | 178 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.lds | 2 +-
.../board/linker_scripts/link.sct | 28 +-
bsp/juicevm/link.lds | 18 +-
bsp/juicevm/link_stacksize.lds | 2 +-
bsp/k210/link.lds | 24 +-
bsp/k210/link_stacksize.lds | 2 +-
bsp/loongson/ls1bdev/ls1b_ram.lds | 2 +-
bsp/loongson/ls1cdev/ls1c_ram.lds | 2 +-
bsp/loongson/ls2kdev/ls2k_ram.lds | 20 +-
bsp/lpc1114/link.lds | 4 +-
.../LPC177x_8x/linker/ldscript_iram_iar.icf | 2 +-
.../LPC177x_8x/linker/ldscript_irom_iar.icf | 2 +-
bsp/lpc2478/lpc2478_ram.lds | 26 +-
bsp/lpc408x/drivers/linker_scripts/link.lds | 10 +-
.../LPC54114/iar/LPC54114J256_cm0plus.icf | 2 +-
.../LPC54114/iar/LPC54114J256_cm0plus_ram.icf | 2 +-
.../LPC54114/iar/LPC54114J256_cm4_ram.icf | 2 +-
.../drivers/linker_scripts/link.icf | 2 +-
.../drivers/linker_scripts/link.lds | 4 +-
bsp/lpc54608-LPCXpresso/link.lds | 12 +-
.../iar/LPC55S69_cm33_core0_flash_s.icf | 8 +-
.../board/linker_scripts/link.lds | 6 +-
.../bsp/samc21/iar/iar/samc21j18a_flash.icf | 4 +-
.../bsp/samc21/iar/iar/samc21j18a_sram.icf | 4 +-
.../same54/bsp/iar/iar/same54p20a_flash.icf | 4 +-
.../same54/bsp/iar/iar/same54p20a_sram.icf | 4 +-
bsp/mini2440/rtthread-mini2440.sct | 36 +-
bsp/mini4020/rtthread-mini4020.sct | 24 +-
bsp/mipssim/mipssim_ram.lds | 20 +-
.../Templates/iar/linker/mm32f3273g.icf | 60 +-
.../board/linker_scripts/link.icf | 60 +-
bsp/mm32f103x/drivers/linker_scripts/link.lds | 4 +-
bsp/mm32f327x/drivers/linker_scripts/link.lds | 4 +-
bsp/mm32l07x/drivers/linker_scripts/link.lds | 4 +-
bsp/mm32l3xx/drivers/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../n32l436-evb/board/linker_scripts/link.icf | 4 +-
.../n32l436-evb/board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../nrf51822/board/linker_scripts/link.lds | 8 +-
.../nrf52832/board/linker_scripts/link.lds | 6 +-
.../nrf52833/board/linker_scripts/link.lds | 8 +-
.../nrf52840/board/linker_scripts/link.lds | 8 +-
.../nrf5340/board/linker_scripts/link.lds | 24 +-
.../linking_scripts/m031_flash.icf | 2 +-
bsp/phytium/aarch32/link.lds | 2 +-
bsp/phytium/aarch64/link.lds | 6 +-
bsp/qemu-virt64-riscv/link.lds | 18 +-
bsp/qemu-virt64-riscv/link_stacksize.lds | 2 +-
bsp/raspberry-pi/raspi2/link.lds | 2 +-
bsp/raspberry-pi/raspi3-32/link.lds | 2 +-
bsp/raspberry-pi/raspi3-64/link.lds | 2 +-
bsp/raspberry-pi/raspi4-32/link.lds | 2 +-
bsp/raspberry-pi/raspi4-64/link.lds | 2 +-
bsp/rockchip/rk3568/link.lds | 2 +-
bsp/rx/lnkr5f562n8.icf | 12 +-
bsp/sam7x/sam7x_rom.sct | 30 +-
.../samd20/iar/samd20e18_flash.icf | 158 +-
.../samd20/iar/samd20e18_sram.icf | 152 +-
.../samd20/iar/samd20g17u_flash.icf | 158 +-
.../samd20/iar/samd20g17u_sram.icf | 152 +-
.../samd20/iar/samd20g18u_flash.icf | 158 +-
.../samd20/iar/samd20g18u_sram.icf | 152 +-
.../samd21/iar/samd21e15b_flash.icf | 152 +-
.../samd21/iar/samd21e15b_sram.icf | 146 +-
.../samd21/iar/samd21e15bu_flash.icf | 152 +-
.../samd21/iar/samd21e15bu_sram.icf | 146 +-
.../samd21/iar/samd21e15l_flash.icf | 152 +-
.../samd21/iar/samd21e15l_sram.icf | 146 +-
.../samd21/iar/samd21e16b_flash.icf | 152 +-
.../samd21/iar/samd21e16b_sram.icf | 146 +-
.../samd21/iar/samd21e16bu_flash.icf | 152 +-
.../samd21/iar/samd21e16bu_sram.icf | 146 +-
.../samd21/iar/samd21e16l_flash.icf | 152 +-
.../samd21/iar/samd21e16l_sram.icf | 146 +-
.../samd21/iar/samd21e18a_flash.icf | 152 +-
.../samd21/iar/samd21e18a_sram.icf | 146 +-
.../samd21/iar/samd21g15a_flash.icf | 152 +-
.../samd21/iar/samd21g15a_sram.icf | 146 +-
.../samd21/iar/samd21g15b_flash.icf | 152 +-
.../samd21/iar/samd21g15b_sram.icf | 146 +-
.../samd21/iar/samd21g15l_flash.icf | 152 +-
.../samd21/iar/samd21g15l_sram.icf | 146 +-
.../samd21/iar/samd21g16b_flash.icf | 152 +-
.../samd21/iar/samd21g16b_sram.icf | 146 +-
.../samd21/iar/samd21g16l_flash.icf | 152 +-
.../samd21/iar/samd21g16l_sram.icf | 146 +-
.../samd21/iar/samd21g17au_flash.icf | 152 +-
.../samd21/iar/samd21g17au_sram.icf | 146 +-
.../samd21/iar/samd21g18au_flash.icf | 152 +-
.../samd21/iar/samd21g18au_sram.icf | 146 +-
.../samd21/iar/samd21j15a_flash.icf | 152 +-
.../samd21/iar/samd21j15a_sram.icf | 146 +-
.../samd21/iar/samd21j15b_flash.icf | 152 +-
.../samd21/iar/samd21j15b_sram.icf | 146 +-
.../samd21/iar/samd21j16b_flash.icf | 152 +-
.../samd21/iar/samd21j16b_sram.icf | 146 +-
.../startup_arm/smartfusion2_esram_debug.sct | 8 +-
.../smartfusion2_execute_in_place.sct | 12 +-
.../startup_arm/smartfusion2_mddr_debug.sct | 8 +-
.../smartfusion2_relocate_to_external_ram.sct | 18 +-
.../bsp/env/coreplexip-e31-arty/flash.lds | 2 +-
.../bsp/env/coreplexip-e51-arty/flash.lds | 2 +-
.../env/coreplexip-e51-arty/scratchpad.lds | 2 +-
.../bsp/env/freedom-e300-arty/flash.lds | 2 +-
.../Templates/iar/linker/stm32f091xc_sram.icf | 2 +-
.../Templates/iar/linker/stm32f098xx_sram.icf | 2 +-
.../iar/linker/stm32f301x8_flash.icf | 2 +-
.../iar/linker/stm32f302x8_flash.icf | 2 +-
.../iar/linker/stm32f302xc_flash.icf | 2 +-
.../iar/linker/stm32f302xe_flash.icf | 2 +-
.../iar/linker/stm32f303x8_flash.icf | 2 +-
.../iar/linker/stm32f303xc_flash.icf | 2 +-
.../iar/linker/stm32f303xe_flash.icf | 2 +-
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.../iar/linker/stm32f373xc_flash.icf | 2 +-
.../iar/linker/stm32f378xx_flash.icf | 2 +-
.../iar/linker/stm32f398xx_flash.icf | 2 +-
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.../iar/linker/stm32f750xx_flash.icf | 2 +-
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.../iar/linker/stm32l162xc_flash.icf | 2 +-
.../Templates/iar/linker/stm32l162xc_sram.icf | 2 +-
.../iar/linker/stm32l162xca_flash.icf | 2 +-
.../iar/linker/stm32l162xca_sram.icf | 2 +-
.../iar/linker/stm32l162xd_flash.icf | 2 +-
.../Templates/iar/linker/stm32l162xd_sram.icf | 2 +-
.../iar/linker/stm32l162xdx_flash.icf | 4 +-
.../iar/linker/stm32l162xdx_sram.icf | 2 +-
.../iar/linker/stm32l162xe_flash.icf | 2 +-
.../Templates/iar/linker/stm32l162xe_sram.icf | 2 +-
.../iar/linker/stm32l412xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l412xx_sram.icf | 2 +-
.../iar/linker/stm32l422xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l422xx_sram.icf | 2 +-
.../iar/linker/stm32l431xx_flash.icf | 4 +-
.../Templates/iar/linker/stm32l431xx_sram.icf | 2 +-
.../iar/linker/stm32l432xx_flash.icf | 4 +-
.../Templates/iar/linker/stm32l432xx_sram.icf | 2 +-
.../iar/linker/stm32l433xx_flash.icf | 4 +-
.../Templates/iar/linker/stm32l433xx_sram.icf | 2 +-
.../iar/linker/stm32l442xx_flash.icf | 4 +-
.../Templates/iar/linker/stm32l442xx_sram.icf | 2 +-
.../iar/linker/stm32l443xx_flash.icf | 4 +-
.../Templates/iar/linker/stm32l443xx_sram.icf | 2 +-
.../Templates/iar/linker/stm32l451xx_sram.icf | 2 +-
.../Templates/iar/linker/stm32l452xx_sram.icf | 2 +-
.../Templates/iar/linker/stm32l462xx_sram.icf | 2 +-
.../iar/linker/stm32l471xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l471xx_sram.icf | 2 +-
.../iar/linker/stm32l475xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l475xx_sram.icf | 2 +-
.../iar/linker/stm32l476xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l476xx_sram.icf | 2 +-
.../iar/linker/stm32l485xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l485xx_sram.icf | 2 +-
.../iar/linker/stm32l486xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l486xx_sram.icf | 2 +-
.../iar/linker/stm32l496xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l496xx_sram.icf | 2 +-
.../iar/linker/stm32l4a6xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l4a6xx_sram.icf | 2 +-
.../iar/linker/stm32l4p5xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l4p5xx_sram.icf | 2 +-
.../iar/linker/stm32l4q5xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l4q5xx_sram.icf | 2 +-
.../iar/linker/stm32l4r5xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l4r5xx_sram.icf | 2 +-
.../iar/linker/stm32l4r7xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l4r7xx_sram.icf | 2 +-
.../iar/linker/stm32l4r9xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l4r9xx_sram.icf | 2 +-
.../iar/linker/stm32l4s5xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l4s5xx_sram.icf | 2 +-
.../iar/linker/stm32l4s7xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l4s7xx_sram.icf | 2 +-
.../iar/linker/stm32l4s9xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32l4s9xx_sram.icf | 2 +-
.../iar/linker/stm32l552xc_flash.icf | 2 +-
.../iar/linker/stm32l552xe_flash.icf | 2 +-
.../Templates/iar/linker/stm32l552xx_sram.icf | 2 +-
.../iar/linker/stm32l562xe_flash.icf | 2 +-
.../Templates/iar/linker/stm32l562xx_sram.icf | 2 +-
.../iar/linker/stm32mp15xx_retram.icf | 2 +-
.../Templates/iar/linker/stm32mp15xx_sram.icf | 2 +-
.../iar/linker/stm32u575xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32u575xx_sram.icf | 2 +-
.../iar/linker/stm32u575xx_sram_ns.icf | 2 +-
.../Templates/iar/linker/stm32u585xx_sram.icf | 2 +-
.../iar/linker/stm32u585xx_sram_ns.icf | 2 +-
.../iar/linker/stm32wb10xx_flash_cm4.icf | 2 +-
.../iar/linker/stm32wb10xx_sram_cm4.icf | 2 +-
.../iar/linker/stm32wb15xx_flash_cm4.icf | 2 +-
.../iar/linker/stm32wb15xx_sram_cm4.icf | 2 +-
.../iar/linker/stm32wb30xx_sram_cm4.icf | 2 +-
.../iar/linker/stm32wb35xx_sram_cm4.icf | 2 +-
.../iar/linker/stm32wb50xx_sram_cm4.icf | 2 +-
.../iar/linker/stm32wb55xx_sram_cm4.icf | 2 +-
.../iar/linker/stm32wb5mxx_sram_cm4.icf | 2 +-
.../iar/linker/stm32wl54xx_flash_cm0plus.icf | 2 +-
.../iar/linker/stm32wl54xx_flash_cm4.icf | 2 +-
.../iar/linker/stm32wl54xx_sram_cm0plus.icf | 2 +-
.../iar/linker/stm32wl55xx_flash_cm0plus.icf | 2 +-
.../iar/linker/stm32wl55xx_flash_cm4.icf | 2 +-
.../iar/linker/stm32wl55xx_sram_cm0plus.icf | 2 +-
.../iar/linker/stm32wl55xx_sram_cm4.icf | 2 +-
.../iar/linker/stm32wle4xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32wle4xx_sram.icf | 2 +-
.../iar/linker/stm32wle5xx_flash.icf | 2 +-
.../Templates/iar/linker/stm32wle5xx_sram.icf | 2 +-
.../stm32f0xx/board/linker_scripts/link.lds | 4 +-
.../stm32f10x/board/linker_scripts/link.lds | 4 +-
.../stm32f2xx/board/linker_scripts/link.lds | 4 +-
.../stm32f3xx/board/linker_scripts/link.lds | 4 +-
.../stm32f4xx/board/linker_scripts/link.lds | 4 +-
.../stm32f7xx/board/linker_scripts/link.lds | 4 +-
.../stm32h7xx/board/linker_scripts/link.lds | 4 +-
.../stm32l1xx/board/linker_scripts/link.lds | 8 +-
.../stm32l4xx/board/linker_scripts/link.lds | 4 +-
.../stm32l5xx/board/linker_scripts/link.lds | 4 +-
.../stm32mp1xx/board/linker_scripts/link.lds | 4 +-
.../stm32mp1xx/board/linker_scripts/link.sct | 70 +-
.../stm32wbxx/board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.sct | 30 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.sct | 30 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.sct | 30 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 6 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 6 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.sct | 30 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.sct | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 8 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 2 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.icf | 16 +-
.../board/linker_scripts/link.lds | 6 +-
.../board/linker_scripts/link.sct | 18 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.sct | 18 +-
.../board/linker_scripts/link.icf | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.sct | 18 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.sct | 54 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.sct | 54 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 6 +-
.../swm320/drivers/linker_scripts/link.icf | 2 +-
.../swm320/drivers/linker_scripts/link.lds | 4 +-
.../swm341/drivers/linker_scripts/link.icf | 2 +-
.../swm341/drivers/linker_scripts/link.lds | 4 +-
.../Source/ARM/tae32f53xx_ac5_sram.sct | 6 +-
bsp/tae32f5300/board/linker_scripts/link.icf | 4 +-
.../linker_scripts/tae32f53xx_ac5_flash.sct | 6 +-
bsp/tkm32F499/drivers/linker_scripts/link.lds | 4 +-
bsp/tm4c123bsp/board/linker_scripts/link.icf | 6 +-
bsp/tm4c123bsp/board/linker_scripts/link.sct | 6 +-
bsp/tm4c129x/tm4c_rom.icf | 8 +-
bsp/tm4c129x/tm4c_rom.sct | 6 +-
bsp/w60x/drivers/linker_scripts/link.icf | 60 +-
bsp/w60x/drivers/linker_scripts/link.lds | 12 +-
bsp/w60x/drivers/linker_scripts/link.sct | 30 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 4 +-
.../board/linker_scripts/link.lds | 195 +-
.../board/linker_scripts/link.lds | 276 +-
bsp/wh44b0/wh44b0_ram.lds | 74 +-
bsp/wh44b0/wh44b0_rom.lds | 72 +-
bsp/x86/x86_ram.lds | 6 +-
.../drivers/linker_scripts/link.lds | 226 +-
.../drivers/linker_scripts/link.sct | 26 +-
869 files changed, 24203 insertions(+), 24010 deletions(-)
diff --git a/bsp/CME_M7/CME_M7.sct b/bsp/CME_M7/CME_M7.sct
index ece5e2a5ec..31364ac0a5 100644
--- a/bsp/CME_M7/CME_M7.sct
+++ b/bsp/CME_M7/CME_M7.sct
@@ -1,22 +1,22 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-; load region size_region
-LR_IROM1 (0) (1024 * 128)
-{
- ; load address = execution address
- ER_IROM1 (0) (1024 * 128)
- {
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ; RW data
- RW_IRAM1 0x20000000 (1024 * 48)
- {
- .ANY (+RW +ZI)
- }
-}
-
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+; load region size_region
+LR_IROM1 (0) (1024 * 128)
+{
+ ; load address = execution address
+ ER_IROM1 (0) (1024 * 128)
+ {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; RW data
+ RW_IRAM1 0x20000000 (1024 * 48)
+ {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
index aebee8de30..a7264c63ac 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x00002000
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-; Public RAM
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE %REGION_SIZE%
-; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
- ;RW_IRAM2 PUBLIC_RAM_START UNINIT
- ;{
- ; * (.cy_sharedmem)
- ;}
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x00002000
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE %REGION_SIZE%
+; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+ ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+ ;{
+ ; * (.cy_sharedmem)
+ ;}
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
index 08d924448d..7480a10906 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
@@ -1,253 +1,253 @@
-/*******************************************************************************
-* \file cy8c6xxa_cm0plus.icf
-* \version 2.91
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
- define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
- define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
- define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
- define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM0+ core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
-define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF;
-
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-/* Public RAM
- * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
- * This region is used to place objects that require full access from both cores.
- * Uncomment the following lines, define region size, and uncomment the placement of
- * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__
- * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region.
- */
-/*
-define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
-*/
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block RO {first section .intvec, readonly};
-
-define block cy_xip { section .cy_xip };
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application */
-".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
-place in IROM1_region { block RO };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-"cy_xip" : place at start of EROM1_region { block cy_xip };
-
-/* RAM */
-place at start of IRAM1_region { readwrite section .intvec_ram};
-place in IRAM1_region { readwrite };
-place at end of IRAM1_region { block HSTACK };
-
-/* Public RAM
- *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
- */
-/*
-place at start of IRAM2_region { section .cy_sharedmem };
-*/
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep { section .cy_app_header,
- section .cy_em_eeprom,
- section .cy_sflash_user_data,
- section .cy_sflash_nar,
- section .cy_sflash_public_key,
- section .cy_toc_part2,
- section .cy_rtoc_part2,
- section .cy_efuse,
- section .cy_xip,
- section .cymeta,
- };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start = 0x10000000;
-define exported symbol __cy_memory_0_length = 0x00200000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start = 0x14000000;
-define exported symbol __cy_memory_1_length = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start = 0x16000000;
-define exported symbol __cy_memory_2_length = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start = 0x18000000;
-define exported symbol __cy_memory_3_length = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start = 0x90700000;
-define exported symbol __cy_memory_4_length = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/*******************************************************************************
+* \file cy8c6xxa_cm0plus.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+ define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+ define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+/* Public RAM
+ * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+ * This region is used to place objects that require full access from both cores.
+ * Uncomment the following lines, define region size, and uncomment the placement of
+ * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__
+ * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region.
+ */
+/*
+define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+*/
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block RO {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application */
+".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
+place in IROM1_region { block RO };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region { readwrite section .intvec_ram};
+place in IRAM1_region { readwrite };
+place at end of IRAM1_region { block HSTACK };
+
+/* Public RAM
+ *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
+ */
+/*
+place at start of IRAM2_region { section .cy_sharedmem };
+*/
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep { section .cy_app_header,
+ section .cy_em_eeprom,
+ section .cy_sflash_user_data,
+ section .cy_sflash_nar,
+ section .cy_sflash_public_key,
+ section .cy_toc_part2,
+ section .cy_rtoc_part2,
+ section .cy_efuse,
+ section .cy_xip,
+ section .cymeta,
+ };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start = 0x10000000;
+define exported symbol __cy_memory_0_length = 0x00200000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start = 0x14000000;
+define exported symbol __cy_memory_1_length = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start = 0x16000000;
+define exported symbol __cy_memory_2_length = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start = 0x18000000;
+define exported symbol __cy_memory_3_length = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start = 0x90700000;
+define exported symbol __cy_memory_4_length = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
index 4c3b188cc9..edd6046930 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08002000
-#define RAM_SIZE 0x000FD800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00200000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08002000
+#define RAM_SIZE 0x000FD800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
index fb4071c60d..14ea8bcbac 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
@@ -1,247 +1,247 @@
-/*******************************************************************************
-* \file cy8c6xxa_cm4_dual.icf
-* \version 2.91
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
-define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF;
-
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
- define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
- define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
- define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
- define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
- * More about CM0+ prebuilt images, see here:
- * https://github.com/cypresssemiconductorco/psoc6cm0p
- */
-/* The size of the Cortex-M0+ application image */
-define symbol FLASH_CM0P_SIZE = 0x2000;
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
-define block RO {first section .intvec, readonly};
-
-define block cy_xip { section .cy_xip };
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application image */
-place at start of IROM1_region { block CM0P_RO };
-
-/* Flash - Cortex-M4 application */
-place in IROM1_region { block RO };
-
-/* Used for the digital signature of the secure application and the Bootloader SDK application. */
-".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-"cy_xip" : place at start of EROM1_region { block cy_xip };
-
-/* RAM */
-place at start of IRAM1_region { readwrite section .intvec_ram};
-place in IRAM1_region { readwrite };
-place at end of IRAM1_region { block HSTACK };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep { section .cy_m0p_image,
- section .cy_app_signature,
- section .cy_em_eeprom,
- section .cy_sflash_user_data,
- section .cy_sflash_nar,
- section .cy_sflash_public_key,
- section .cy_toc_part2,
- section .cy_rtoc_part2,
- section .cy_efuse,
- section .cy_xip,
- section .cymeta,
- };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start = 0x10000000;
-define exported symbol __cy_memory_0_length = 0x00200000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start = 0x14000000;
-define exported symbol __cy_memory_1_length = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start = 0x16000000;
-define exported symbol __cy_memory_2_length = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start = 0x18000000;
-define exported symbol __cy_memory_3_length = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start = 0x90700000;
-define exported symbol __cy_memory_4_length = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/*******************************************************************************
+* \file cy8c6xxa_cm4_dual.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+ define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+ define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+ * More about CM0+ prebuilt images, see here:
+ * https://github.com/cypresssemiconductorco/psoc6cm0p
+ */
+/* The size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
+define block RO {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in IROM1_region { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region { readwrite section .intvec_ram};
+place in IRAM1_region { readwrite };
+place at end of IRAM1_region { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep { section .cy_m0p_image,
+ section .cy_app_signature,
+ section .cy_em_eeprom,
+ section .cy_sflash_user_data,
+ section .cy_sflash_nar,
+ section .cy_sflash_public_key,
+ section .cy_toc_part2,
+ section .cy_rtoc_part2,
+ section .cy_efuse,
+ section .cy_xip,
+ section .cymeta,
+ };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start = 0x10000000;
+define exported symbol __cy_memory_0_length = 0x00200000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start = 0x14000000;
+define exported symbol __cy_memory_1_length = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start = 0x16000000;
+define exported symbol __cy_memory_2_length = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start = 0x18000000;
+define exported symbol __cy_memory_3_length = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start = 0x90700000;
+define exported symbol __cy_memory_4_length = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct
index 425ce1da0b..88cb7751d5 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct
@@ -1,292 +1,292 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx4_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
- #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x80000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
- #define MBED_PUBLIC_RAM_SIZE 0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
- #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00040000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx4_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x80000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+ #define MBED_PUBLIC_RAM_SIZE 0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+ #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00040000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
index ebe15e2a3b..cb14c283d3 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
@@ -1,311 +1,311 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx5_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
- #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x80000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
- #define MBED_PUBLIC_RAM_SIZE 0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
- #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x80000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+ #define MBED_PUBLIC_RAM_SIZE 0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+ #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct
index 42069ae160..d47e3fd6b6 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct
@@ -1,311 +1,311 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx6_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
- #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x80000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
- #define MBED_PUBLIC_RAM_SIZE 0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
- #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx6_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x80000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+ #define MBED_PUBLIC_RAM_SIZE 0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+ #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
index 6fac0911a6..84f1e3d4f9 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
@@ -1,311 +1,311 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
- #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x80000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
- #define MBED_PUBLIC_RAM_SIZE 0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
- #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x80000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+ #define MBED_PUBLIC_RAM_SIZE 0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+ #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct
index 116340f4a7..dd59dd6cf5 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct
@@ -1,311 +1,311 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx8_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
- #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x80000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
- #define MBED_PUBLIC_RAM_SIZE 0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
- #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx8_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x80000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+ #define MBED_PUBLIC_RAM_SIZE 0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+ #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
index 396f39cbc4..08ad870ec0 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
@@ -1,311 +1,311 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
- #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x80000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
- #define MBED_PUBLIC_RAM_SIZE 0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
- #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x80000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+ #define MBED_PUBLIC_RAM_SIZE 0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+ #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct
index cb46c0103f..efef939e8f 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct
@@ -1,288 +1,288 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx5_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
- #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00010000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08020000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x0000C000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
- #define MBED_PUBLIC_RAM_SIZE 0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
- #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00070000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx5_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00010000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08020000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x0000C000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+ #define MBED_PUBLIC_RAM_SIZE 0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+ #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00070000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct
index 0fc6b61c8f..d1a588245a 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct
@@ -1,307 +1,307 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
- #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00010000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08020000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x0000C000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
- #define MBED_PUBLIC_RAM_SIZE 0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
- #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x000D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx7_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00010000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08020000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x0000C000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+ #define MBED_PUBLIC_RAM_SIZE 0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+ #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x000D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
index b0b99a6d8d..4fb7a6ad9d 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
@@ -1,307 +1,307 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
- #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00010000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x080E0000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x0000C000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
- #define MBED_PUBLIC_RAM_SIZE 0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
- #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x001D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00010000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x080E0000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x0000C000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+ #define MBED_PUBLIC_RAM_SIZE 0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+ #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x001D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct
index 675831f8fd..2a70bf9b48 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct
@@ -1,295 +1,295 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx4_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00040000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x0001D800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00040000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx4_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00040000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x0001D800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00040000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
index 153d577ac2..8e15b545f0 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
@@ -1,314 +1,314 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx5_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00080000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x0003D800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00080000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x0003D800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct
index f6403e6b38..f89e92fe2c 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct
@@ -1,314 +1,314 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx6_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00080000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x0001D800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx6_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00080000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x0001D800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
index a9c4ac0cbe..3ca5d47fdb 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
@@ -1,314 +1,314 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00100000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x00045800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00100000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x00045800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct
index 947c560a44..84ba02e724 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct
@@ -1,314 +1,314 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx8_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00100000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x0007D800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx8_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00100000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x0007D800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
index 185f0cc4ef..7148dc7dee 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
@@ -1,314 +1,314 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00200000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x000FD800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00200000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x000FD800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct
index 2c54484d12..0ae7ed0907 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct
@@ -1,298 +1,298 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx5_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x10000
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00030000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08000800
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x0001F800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00070000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx5_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x10000
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00030000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08000800
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x0001F800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00070000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
index e589c96d3f..593d74167c 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
@@ -1,317 +1,317 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x10000
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x00068000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08000800
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x0001F800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x000D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx7_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x10000
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x00068000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08000800
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x0001F800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x000D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
index 349f7cdcff..510070751f 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
@@ -1,317 +1,317 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x10000
-
-#if !defined(MBED_ROM_START)
- #define MBED_ROM_START 0x10000000
-#endif
-
-;* MBED_APP_START is being used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-#if !defined(MBED_ROM_SIZE)
- #define MBED_ROM_SIZE 0x000E0000
-#endif
-
-;* MBED_APP_SIZE is being used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 0x08000800
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x000DF800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
- #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START MBED_RAM_START
-#define RAM_SIZE MBED_RAM_SIZE
-; Flash
-#define FLASH_START MBED_APP_START
-#define FLASH_SIZE MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x001D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x10000
+
+#if !defined(MBED_ROM_START)
+ #define MBED_ROM_START 0x10000000
+#endif
+
+;* MBED_APP_START is being used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+#if !defined(MBED_ROM_SIZE)
+ #define MBED_ROM_SIZE 0x000E0000
+#endif
+
+;* MBED_APP_SIZE is being used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+ #define MBED_RAM_START 0x08000800
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+ #define MBED_RAM_SIZE 0x000DF800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START MBED_RAM_START
+#define RAM_SIZE MBED_RAM_SIZE
+; Flash
+#define FLASH_START MBED_APP_START
+#define FLASH_SIZE MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x001D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct
index da8478fcd9..20f93b9d31 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct
@@ -1,253 +1,253 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx4_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x00002000
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE 0x00001000
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-; Public RAM
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE %REGION_SIZE%
-; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
- ;RW_IRAM2 PUBLIC_RAM_START UNINIT
- ;{
- ; * (.cy_sharedmem)
- ;}
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00040000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx4_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x00002000
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE 0x00001000
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE %REGION_SIZE%
+; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+ ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+ ;{
+ ; * (.cy_sharedmem)
+ ;}
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00040000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
index 796c29ab17..f164926a12 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx5_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x00002000
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-; Public RAM
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE %REGION_SIZE%
-; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
- ;RW_IRAM2 PUBLIC_RAM_START UNINIT
- ;{
- ; * (.cy_sharedmem)
- ;}
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x00002000
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE %REGION_SIZE%
+; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+ ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+ ;{
+ ; * (.cy_sharedmem)
+ ;}
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct
index 09e04730fa..2ca1e091e8 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct
@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx6_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x00002000
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-; Public RAM
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE %REGION_SIZE%
-; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
- ;RW_IRAM2 PUBLIC_RAM_START UNINIT
- ;{
- ; * (.cy_sharedmem)
- ;}
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx6_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x00002000
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE %REGION_SIZE%
+; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+ ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+ ;{
+ ; * (.cy_sharedmem)
+ ;}
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
index 7d9777abc4..c54c106ec1 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x00002000
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-; Public RAM
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE %REGION_SIZE%
-; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
- ;RW_IRAM2 PUBLIC_RAM_START UNINIT
- ;{
- ; * (.cy_sharedmem)
- ;}
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x00002000
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE %REGION_SIZE%
+; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+ ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+ ;{
+ ; * (.cy_sharedmem)
+ ;}
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct
index de1f303dae..09ccbda21b 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct
@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx8_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x00002000
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-; Public RAM
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE %REGION_SIZE%
-; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
- ;RW_IRAM2 PUBLIC_RAM_START UNINIT
- ;{
- ; * (.cy_sharedmem)
- ;}
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx8_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x00002000
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE %REGION_SIZE%
+; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+ ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+ ;{
+ ; * (.cy_sharedmem)
+ ;}
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
index aebee8de30..a7264c63ac 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x00002000
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-; Public RAM
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE %REGION_SIZE%
-; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- .cy_app_header +0
- {
- * (.cy_app_header)
- }
-
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
- ;RW_IRAM2 PUBLIC_RAM_START UNINIT
- ;{
- ; * (.cy_sharedmem)
- ;}
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x00002000
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE %REGION_SIZE%
+; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+ ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+ ;{
+ ; * (.cy_sharedmem)
+ ;}
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct
index ff156a114a..453596df89 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct
@@ -1,244 +1,244 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx5_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START 0x08020000
-#define RAM_SIZE 0x0000C000
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00010000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-; Public RAM
-#define PUBLIC_RAM_SIZE 0x800
-#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00070000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx5_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START 0x08020000
+#define RAM_SIZE 0x0000C000
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00010000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+; Public RAM
+#define PUBLIC_RAM_SIZE 0x800
+#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00070000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct
index 097000cb52..d9de0fcef3 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct
@@ -1,263 +1,263 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START 0x08020000
-#define RAM_SIZE 0x0000C000
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00010000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-; Public RAM
-#define PUBLIC_RAM_SIZE 0x800
-#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x000D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx7_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START 0x08020000
+#define RAM_SIZE 0x0000C000
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00010000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+; Public RAM
+#define PUBLIC_RAM_SIZE 0x800
+#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x000D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
index 8c51598493..d44a8a70a6 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
@@ -1,263 +1,263 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START 0x080E0000
-#define RAM_SIZE 0x0000C000
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00010000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-; Public RAM
-#define PUBLIC_RAM_SIZE 0x800
-#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- RW_IRAM2 PUBLIC_RAM_START UNINIT
- {
- * (.cy_sharedmem)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x001D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START 0x080E0000
+#define RAM_SIZE 0x0000C000
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00010000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+; Public RAM
+#define PUBLIC_RAM_SIZE 0x800
+#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ RW_IRAM2 PUBLIC_RAM_START UNINIT
+ {
+ * (.cy_sharedmem)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x001D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf
index 5e32a338e1..d628114384 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf
@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-/* Public RAM
+/* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of
@@ -198,7 +198,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
-/* Public RAM
+/* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/
/*
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf
index 15f3f5feed..95e65d84fa 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf
@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-/* Public RAM
+/* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
-/* Public RAM
+/* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/
/*
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf
index b945bbdfc8..f704bba22f 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf
@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-/* Public RAM
+/* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
-/* Public RAM
+/* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/
/*
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
index c53fc413f0..41e5e75061 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-/* Public RAM
+/* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
-/* Public RAM
+/* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/
/*
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf
index 98af027cb8..05ce3d70c3 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf
@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-/* Public RAM
+/* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
-/* Public RAM
+/* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/
/*
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
index 57e88ec72a..7480a10906 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-/* Public RAM
+/* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
-/* Public RAM
+/* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/
/*
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct
index 6d18b843a8..bb0c7c0e7e 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct
@@ -1,240 +1,240 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx4_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x0001F780
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00040000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00040000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx4_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x0001F780
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00040000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00040000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct
index 508cd4146c..bcfaaac2c5 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct
@@ -1,258 +1,258 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx4_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08002000
-#define RAM_SIZE 0x0001D800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00040000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00040000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx4_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08002000
+#define RAM_SIZE 0x0001D800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00040000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00040000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct
index 65f379ce04..2f6005ce92 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct
@@ -1,259 +1,259 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx5_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x0003F780
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00080000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x0003F780
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00080000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
index c807911140..c6d41174de 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx5_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08002000
-#define RAM_SIZE 0x0003D800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00080000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08002000
+#define RAM_SIZE 0x0003D800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00080000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct
index ad7f999f35..b238b17565 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct
@@ -1,259 +1,259 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx6_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x0001F780
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00080000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx6_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x0001F780
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00080000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct
index 56fabc2e5e..aab696d6fa 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct
@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx6_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08002000
-#define RAM_SIZE 0x0001D800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00080000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx6_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08002000
+#define RAM_SIZE 0x0001D800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00080000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct
index 85129023af..8e71321b07 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct
@@ -1,259 +1,259 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x00047780
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00100000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x00047780
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00100000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
index 5188f053df..a4d7de18ab 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08002000
-#define RAM_SIZE 0x00045800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00100000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08002000
+#define RAM_SIZE 0x00045800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00100000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual_cm0p_bless.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual_cm0p_bless.sct
index 615be1fea2..a6c1c5727a 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual_cm0p_bless.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual_cm0p_bless.sct
@@ -1,280 +1,280 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual_cm0p_bless.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* This linker script is modified from cy8c6xx7_cm4_dual.sct for CM0P_BLESS image.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08003000
-#define RAM_SIZE 0x00044800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00100000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-; Size and start address of the Cortex-M0+ application image
-FLASH_CM0P_SIZE = 0x20000;
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4_dual_cm0p_bless.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* This linker script is modified from cy8c6xx7_cm4_dual.sct for CM0P_BLESS image.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08003000
+#define RAM_SIZE 0x00044800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00100000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+; Size and start address of the Cortex-M0+ application image
+FLASH_CM0P_SIZE = 0x20000;
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct
index 1ed7c95aee..71e8ea7a5d 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct
@@ -1,259 +1,259 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx8_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x0007F780
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00100000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx8_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x0007F780
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00100000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct
index 21a4d64a40..6974354f3f 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct
@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx8_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08002000
-#define RAM_SIZE 0x0007D800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00100000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx8_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08002000
+#define RAM_SIZE 0x0007D800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00100000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct
index 352f298460..777a4630e6 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct
@@ -1,259 +1,259 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START 0x08000000
-#define RAM_SIZE 0x000FF780
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00200000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x000FF780
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
index 4c3b188cc9..edd6046930 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08002000
-#define RAM_SIZE 0x000FD800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00200000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08002000
+#define RAM_SIZE 0x000FD800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct
index f3eeddeb65..df2a91a7f8 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct
@@ -1,133 +1,133 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx5_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10020000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; RAM
-#define RAM_START 0x08001800
-#define RAM_SIZE 0x0001E800
-; Flash
-#define FLASH_START 0x10020000
-#define FLASH_SIZE 0x00020000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx5_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10020000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; RAM
+#define RAM_START 0x08001800
+#define RAM_SIZE 0x0001E800
+; Flash
+#define FLASH_START 0x10020000
+#define FLASH_SIZE 0x00020000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct
index 4e2826d45d..1a2ed0c260 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct
@@ -1,147 +1,147 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx5_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08000800
-#define RAM_SIZE 0x0001F800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00030000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-; The size of the Cortex-M0+ application image (including MCU boot header area)
-#define FLASH_CM0P_SIZE 0x10000
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
- .cy_m0p_image +0
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx5_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08000800
+#define RAM_SIZE 0x0001F800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00030000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+; The size of the Cortex-M0+ application image (including MCU boot header area)
+#define FLASH_CM0P_SIZE 0x10000
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+ .cy_m0p_image +0
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct
index 3c3398d9f0..39753f8c16 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct
@@ -1,148 +1,148 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10060000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; RAM
-#define RAM_START 0x08001800
-#define RAM_SIZE 0x0001E800
-; Flash
-#define FLASH_START 0x10060000
-#define FLASH_SIZE 0x00030000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx7_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10060000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; RAM
+#define RAM_START 0x08001800
+#define RAM_SIZE 0x0001E800
+; Flash
+#define FLASH_START 0x10060000
+#define FLASH_SIZE 0x00030000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
index 8a319053dd..1088b3f2cf 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
@@ -1,162 +1,162 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08000800
-#define RAM_SIZE 0x0001F800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00068000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-; The size of the Cortex-M0+ application image (including MCU boot header area)
-#define FLASH_CM0P_SIZE 0x10000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
- .cy_m0p_image +0
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx7_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08000800
+#define RAM_SIZE 0x0001F800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00068000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+; The size of the Cortex-M0+ application image (including MCU boot header area)
+#define FLASH_CM0P_SIZE 0x10000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+ .cy_m0p_image +0
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct
index 4e95b5e68b..eb2ab7a048 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct
@@ -1,148 +1,148 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x100E0000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; RAM
-#define RAM_START 0x08001800
-#define RAM_SIZE 0x000DE800
-; Flash
-#define FLASH_START 0x100E0000
-#define FLASH_SIZE 0x00070000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xxa_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x100E0000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; RAM
+#define RAM_START 0x08001800
+#define RAM_SIZE 0x000DE800
+; Flash
+#define FLASH_START 0x100E0000
+#define FLASH_SIZE 0x00070000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
index 55293df906..e50d22c8ee 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
@@ -1,162 +1,162 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08000800
-#define RAM_SIZE 0x000DF800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x000E0000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-; The size of the Cortex-M0+ application image (including MCU boot header area)
-#define FLASH_CM0P_SIZE 0x10000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
- .cy_m0p_image +0
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08000800
+#define RAM_SIZE 0x000DF800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x000E0000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+; The size of the Cortex-M0+ application image (including MCU boot header area)
+#define FLASH_CM0P_SIZE 0x10000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+ .cy_m0p_image +0
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cys06xxa_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cys06xxa_cm4.sct
index e5001ffa1e..ee4d7b3b64 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cys06xxa_cm4.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cys06xxa_cm4.sct
@@ -1,148 +1,148 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cys06xxa_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10050000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; RAM
-#define RAM_START 0x08030000
-#define RAM_SIZE 0x000B7000
-; Flash
-#define FLASH_START 0x10050000
-#define FLASH_SIZE 0x0011C000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cys06xxa_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10050000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; RAM
+#define RAM_START 0x08030000
+#define RAM_SIZE 0x000B7000
+; Flash
+#define FLASH_START 0x10050000
+#define FLASH_SIZE 0x0011C000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct
index dc25deabc3..368da5ccf2 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct
@@ -1,159 +1,159 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 -march=armv8-m.main
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-/***************************************************************************//**
-* \file cyw20829_ns_flash_cbus.sct
-* \version 1.0.0
-*
-* Linker file for the ARMCC compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point location starts at 0x0401e000. The valid
-* application image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#define flash_start_addr_cbus 0x08000000
-#define ram_start_addr_sahb 0x20000000
-#define ram_start_addr_cbus 0x04000000
-#define ram_end_addr_sahb 0x20020000
-
-#define app_code_offset_flash 0x00002200
-#define bootstrap_offset_ram 0x0001E000
-
-; The size of the stack section at the end of CM33 SRAM
-#define STACK_SIZE 0x00001000
-
-
-/* VMA for bootstrap Text */
-#define bootstrapText_vma ram_start_addr_cbus + bootstrap_offset_ram /* 0x0401E000 */
-/* Size of bootstrap section */
-#define bootstrapText_size 0x00002000
-
-/* VMA for bootstrap Data */
-#define bootstrapRamVect_vma ram_start_addr_sahb + STACK_SIZE /* 0x20001000 */
-
-/* VMA for flash */
-#define appText_vma flash_start_addr_cbus + app_code_offset_flash /* 0x08002200 */
-
-/* Memory reserved for Bootstrap code and data */
-#define BOOTSTRAP_SIZE ram_end_addr_sahb - ram_start_addr_sahb - bootstrap_offset_ram; /* 0x00002000 */
-
-; Cortex-M33 application flash area
-LR_1 bootstrapText_vma BOOTSTRAP_SIZE
-{
- bootstrap bootstrapText_vma bootstrapText_size
- {
- * (RESET, +FIRST)
- * (InRoot$$Sections)
-
- ns_start_cyw20829.o (+RO)
- ns_system_cyw20829.o (+RO)
-
- /* drivers */
- cy_device.o (+RO)
- cy_btss.o (+RO)
- cy_sysclk_v2.o (+RO)
- cy_syspm_v2.o (+RO)
- cy_sysint_v2.o (+RO)
- cy_syslib*.o (+RO)
- ppu_v1.o (+RO)
- cy_mpc.o (+RO)
- cy_pd_ppu.o (+RO)
- *(.cy_l1func*)
- }
-
-/* converting c-bus to sahb address */
-#define bootstrapData_vma AlignExpr((ImageLimit(bootstrap) - ram_start_addr_cbus) + ram_start_addr_sahb, 4)
-
- bootstrapData bootstrapData_vma ALIGN 4
- {
- ns_start_cyw20829.o (+RW, +ZI)
- ns_system_cyw20829.o (+RW, +ZI)
-
- /* drivers */
- cy_device.o (+RW, +ZI)
- cy_btss.o (+RW, +ZI)
- cy_sysclk_v2.o (+RW, +ZI)
- cy_syspm_v2.o (+RW, +ZI)
- cy_sysint_v2.o (+RW, +ZI)
- cy_syslib*.o (+RW, +ZI)
- ppu_v1.o (+RW, +ZI)
- cy_mpc.o (+RW, +ZI)
- cy_pd_ppu.o (+RW, +ZI)
- }
-
- bootstrap_vector bootstrapRamVect_vma UNINIT
- {
- * (.bss.noinit.RESET_RAM, +FIRST)
- }
-}
-
-#define appTextRam_vma AlignExpr(ImageLimit( bootstrap_vector), 8)
-
-LR_2 appText_vma
-{
- app appText_vma
- {
- * (+RO)
- }
-
- appTextRam appTextRam_vma
- {
- * (.cy_ramfunc)
- cy_smif.o (+RO)
- cy_smif_memslot.o (+RO)
- }
-
-#define appData_vma AlignExpr((ImageLimit(appTextRam) - ImageBase(appTextRam) + ImageLimit(bootstrap_vector)), 8)
-
- appData appData_vma
- {
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- appData_noinit +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((ram_start_addr_sahb + bootstrap_offset_ram)-AlignExpr(ImageLimit(appData_noinit), 8))
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (ram_start_addr_sahb + STACK_SIZE) ALIGN 32 EMPTY -STACK_SIZE
- {
- }
-}
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 -march=armv8-m.main
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+/***************************************************************************//**
+* \file cyw20829_ns_flash_cbus.sct
+* \version 1.0.0
+*
+* Linker file for the ARMCC compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location starts at 0x0401e000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#define flash_start_addr_cbus 0x08000000
+#define ram_start_addr_sahb 0x20000000
+#define ram_start_addr_cbus 0x04000000
+#define ram_end_addr_sahb 0x20020000
+
+#define app_code_offset_flash 0x00002200
+#define bootstrap_offset_ram 0x0001E000
+
+; The size of the stack section at the end of CM33 SRAM
+#define STACK_SIZE 0x00001000
+
+
+/* VMA for bootstrap Text */
+#define bootstrapText_vma ram_start_addr_cbus + bootstrap_offset_ram /* 0x0401E000 */
+/* Size of bootstrap section */
+#define bootstrapText_size 0x00002000
+
+/* VMA for bootstrap Data */
+#define bootstrapRamVect_vma ram_start_addr_sahb + STACK_SIZE /* 0x20001000 */
+
+/* VMA for flash */
+#define appText_vma flash_start_addr_cbus + app_code_offset_flash /* 0x08002200 */
+
+/* Memory reserved for Bootstrap code and data */
+#define BOOTSTRAP_SIZE ram_end_addr_sahb - ram_start_addr_sahb - bootstrap_offset_ram; /* 0x00002000 */
+
+; Cortex-M33 application flash area
+LR_1 bootstrapText_vma BOOTSTRAP_SIZE
+{
+ bootstrap bootstrapText_vma bootstrapText_size
+ {
+ * (RESET, +FIRST)
+ * (InRoot$$Sections)
+
+ ns_start_cyw20829.o (+RO)
+ ns_system_cyw20829.o (+RO)
+
+ /* drivers */
+ cy_device.o (+RO)
+ cy_btss.o (+RO)
+ cy_sysclk_v2.o (+RO)
+ cy_syspm_v2.o (+RO)
+ cy_sysint_v2.o (+RO)
+ cy_syslib*.o (+RO)
+ ppu_v1.o (+RO)
+ cy_mpc.o (+RO)
+ cy_pd_ppu.o (+RO)
+ *(.cy_l1func*)
+ }
+
+/* converting c-bus to sahb address */
+#define bootstrapData_vma AlignExpr((ImageLimit(bootstrap) - ram_start_addr_cbus) + ram_start_addr_sahb, 4)
+
+ bootstrapData bootstrapData_vma ALIGN 4
+ {
+ ns_start_cyw20829.o (+RW, +ZI)
+ ns_system_cyw20829.o (+RW, +ZI)
+
+ /* drivers */
+ cy_device.o (+RW, +ZI)
+ cy_btss.o (+RW, +ZI)
+ cy_sysclk_v2.o (+RW, +ZI)
+ cy_syspm_v2.o (+RW, +ZI)
+ cy_sysint_v2.o (+RW, +ZI)
+ cy_syslib*.o (+RW, +ZI)
+ ppu_v1.o (+RW, +ZI)
+ cy_mpc.o (+RW, +ZI)
+ cy_pd_ppu.o (+RW, +ZI)
+ }
+
+ bootstrap_vector bootstrapRamVect_vma UNINIT
+ {
+ * (.bss.noinit.RESET_RAM, +FIRST)
+ }
+}
+
+#define appTextRam_vma AlignExpr(ImageLimit( bootstrap_vector), 8)
+
+LR_2 appText_vma
+{
+ app appText_vma
+ {
+ * (+RO)
+ }
+
+ appTextRam appTextRam_vma
+ {
+ * (.cy_ramfunc)
+ cy_smif.o (+RO)
+ cy_smif_memslot.o (+RO)
+ }
+
+#define appData_vma AlignExpr((ImageLimit(appTextRam) - ImageBase(appTextRam) + ImageLimit(bootstrap_vector)), 8)
+
+ appData appData_vma
+ {
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ appData_noinit +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((ram_start_addr_sahb + bootstrap_offset_ram)-AlignExpr(ImageLimit(appData_noinit), 8))
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (ram_start_addr_sahb + STACK_SIZE) ALIGN 32 EMPTY -STACK_SIZE
+ {
+ }
+}
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct
index ffe5496c8b..cfb1fa6a55 100644
--- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct
+++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct
@@ -1,163 +1,163 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyw20829_ns.sct
-;* \version 1.0.0
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2020 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM33 core.
-; RAM
-
-#define CODE_ROM_NS_CBUS_START 0x00000000
-#define CODE_ROM_NS_CBUS_SIZE 0x00010000
-#define CODE_SRAM0_NS_CBUS_START 0x04004200
-#define CODE_SRAM0_NS_CBUS_SIZE 0x0000E000
-#define CODE_XIP_NS_CBUS_START 0x08000000
-#define CODE_XIP_NS_CBUS_SIZE 0x08000000
-
-#define DATA_ROM_NS_SAHB_START 0x00000000
-#define DATA_ROM_NS_SAHB_SIZE 0x00000000
-#define BSS_ROM_NS_SAHB_START 0x00000000
-#define BSS_ROM_NS_SAHB_SIZE 0x00000000
-#define DATA_SRAM0_NS_SAHB_START 0x20012200
-#define DATA_SRAM0_NS_SAHB_SIZE 0x0000DE00
-#define BSS_SRAM0_NS_SAHB_START 0x20000000
-#define BSS_SRAM0_NS_SAHB_SIZE 0x00000000
-#define DATA_XIP_NS_SAHB_START 0x60000000
-#define DATA_XIP_NS_SAHB_SIZE 0x00000000
-#define BSS_XIP_NS_SAHB_START 0x60000000
-#define BSS_XIP_NS_SAHB_SIZE 0x00000000
-
-
-/*
-#define RAM_START 0x20004200
-#define RAM_SIZE 0x0001BE00
-*/
-#define RAM_START DATA_SRAM0_NS_SAHB_START
-#define RAM_SIZE DATA_SRAM0_NS_SAHB_SIZE
-
-; Flash
-/*
-#define FLASH_START 0x60000000
-#define FLASH_SIZE 0x00010000
-*/
-
-#define FLASH_START CODE_SRAM0_NS_CBUS_START
-#define FLASH_SIZE CODE_SRAM0_NS_CBUS_SIZE
-
-; The size of the stack section at the end of CM33 SRAM
-#define STACK_SIZE 0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE 0x00000000
-
-; The following defines describe device specific memory regions and must not be changed.
-
-; External memory
-#define XIP_START CODE_XIP_NS_CBUS_START
-#define XIP_SIZE CODE_XIP_NS_CBUS_SIZE
-
-
-; Cortex-M33 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (.bss.noinit.RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) ALIGN 32 EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyw20829_ns.sct
+;* \version 1.0.0
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2020 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM33 core.
+; RAM
+
+#define CODE_ROM_NS_CBUS_START 0x00000000
+#define CODE_ROM_NS_CBUS_SIZE 0x00010000
+#define CODE_SRAM0_NS_CBUS_START 0x04004200
+#define CODE_SRAM0_NS_CBUS_SIZE 0x0000E000
+#define CODE_XIP_NS_CBUS_START 0x08000000
+#define CODE_XIP_NS_CBUS_SIZE 0x08000000
+
+#define DATA_ROM_NS_SAHB_START 0x00000000
+#define DATA_ROM_NS_SAHB_SIZE 0x00000000
+#define BSS_ROM_NS_SAHB_START 0x00000000
+#define BSS_ROM_NS_SAHB_SIZE 0x00000000
+#define DATA_SRAM0_NS_SAHB_START 0x20012200
+#define DATA_SRAM0_NS_SAHB_SIZE 0x0000DE00
+#define BSS_SRAM0_NS_SAHB_START 0x20000000
+#define BSS_SRAM0_NS_SAHB_SIZE 0x00000000
+#define DATA_XIP_NS_SAHB_START 0x60000000
+#define DATA_XIP_NS_SAHB_SIZE 0x00000000
+#define BSS_XIP_NS_SAHB_START 0x60000000
+#define BSS_XIP_NS_SAHB_SIZE 0x00000000
+
+
+/*
+#define RAM_START 0x20004200
+#define RAM_SIZE 0x0001BE00
+*/
+#define RAM_START DATA_SRAM0_NS_SAHB_START
+#define RAM_SIZE DATA_SRAM0_NS_SAHB_SIZE
+
+; Flash
+/*
+#define FLASH_START 0x60000000
+#define FLASH_SIZE 0x00010000
+*/
+
+#define FLASH_START CODE_SRAM0_NS_CBUS_START
+#define FLASH_SIZE CODE_SRAM0_NS_CBUS_SIZE
+
+; The size of the stack section at the end of CM33 SRAM
+#define STACK_SIZE 0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE 0x00000000
+
+; The following defines describe device specific memory regions and must not be changed.
+
+; External memory
+#define XIP_START CODE_XIP_NS_CBUS_START
+#define XIP_SIZE CODE_XIP_NS_CBUS_SIZE
+
+
+; Cortex-M33 application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (.bss.noinit.RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) ALIGN 32 EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.icf b/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.icf
index fb4071c60d..14ea8bcbac 100644
--- a/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.icf
+++ b/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.icf
@@ -1,247 +1,247 @@
-/*******************************************************************************
-* \file cy8c6xxa_cm4_dual.icf
-* \version 2.91
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
-define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF;
-
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
- define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
- define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
- define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
- define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
- * More about CM0+ prebuilt images, see here:
- * https://github.com/cypresssemiconductorco/psoc6cm0p
- */
-/* The size of the Cortex-M0+ application image */
-define symbol FLASH_CM0P_SIZE = 0x2000;
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
-define block RO {first section .intvec, readonly};
-
-define block cy_xip { section .cy_xip };
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application image */
-place at start of IROM1_region { block CM0P_RO };
-
-/* Flash - Cortex-M4 application */
-place in IROM1_region { block RO };
-
-/* Used for the digital signature of the secure application and the Bootloader SDK application. */
-".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-"cy_xip" : place at start of EROM1_region { block cy_xip };
-
-/* RAM */
-place at start of IRAM1_region { readwrite section .intvec_ram};
-place in IRAM1_region { readwrite };
-place at end of IRAM1_region { block HSTACK };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep { section .cy_m0p_image,
- section .cy_app_signature,
- section .cy_em_eeprom,
- section .cy_sflash_user_data,
- section .cy_sflash_nar,
- section .cy_sflash_public_key,
- section .cy_toc_part2,
- section .cy_rtoc_part2,
- section .cy_efuse,
- section .cy_xip,
- section .cymeta,
- };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start = 0x10000000;
-define exported symbol __cy_memory_0_length = 0x00200000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start = 0x14000000;
-define exported symbol __cy_memory_1_length = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start = 0x16000000;
-define exported symbol __cy_memory_2_length = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start = 0x18000000;
-define exported symbol __cy_memory_3_length = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start = 0x90700000;
-define exported symbol __cy_memory_4_length = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/*******************************************************************************
+* \file cy8c6xxa_cm4_dual.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+ define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+ define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+ * More about CM0+ prebuilt images, see here:
+ * https://github.com/cypresssemiconductorco/psoc6cm0p
+ */
+/* The size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
+define block RO {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in IROM1_region { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region { readwrite section .intvec_ram};
+place in IRAM1_region { readwrite };
+place at end of IRAM1_region { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep { section .cy_m0p_image,
+ section .cy_app_signature,
+ section .cy_em_eeprom,
+ section .cy_sflash_user_data,
+ section .cy_sflash_nar,
+ section .cy_sflash_public_key,
+ section .cy_toc_part2,
+ section .cy_rtoc_part2,
+ section .cy_efuse,
+ section .cy_xip,
+ section .cymeta,
+ };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start = 0x10000000;
+define exported symbol __cy_memory_0_length = 0x00200000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start = 0x14000000;
+define exported symbol __cy_memory_1_length = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start = 0x16000000;
+define exported symbol __cy_memory_2_length = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start = 0x18000000;
+define exported symbol __cy_memory_3_length = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start = 0x90700000;
+define exported symbol __cy_memory_4_length = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.sct b/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.sct
index 4c3b188cc9..edd6046930 100644
--- a/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.sct
+++ b/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.sct
@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08002000
-#define RAM_SIZE 0x000FD800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00200000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08002000
+#define RAM_SIZE 0x000FD800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.icf b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.icf
index fb4071c60d..14ea8bcbac 100644
--- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.icf
+++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.icf
@@ -1,247 +1,247 @@
-/*******************************************************************************
-* \file cy8c6xxa_cm4_dual.icf
-* \version 2.91
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
-define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF;
-
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
- define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
- define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
- define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
- define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
- * More about CM0+ prebuilt images, see here:
- * https://github.com/cypresssemiconductorco/psoc6cm0p
- */
-/* The size of the Cortex-M0+ application image */
-define symbol FLASH_CM0P_SIZE = 0x2000;
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
-define block RO {first section .intvec, readonly};
-
-define block cy_xip { section .cy_xip };
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application image */
-place at start of IROM1_region { block CM0P_RO };
-
-/* Flash - Cortex-M4 application */
-place in IROM1_region { block RO };
-
-/* Used for the digital signature of the secure application and the Bootloader SDK application. */
-".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-"cy_xip" : place at start of EROM1_region { block cy_xip };
-
-/* RAM */
-place at start of IRAM1_region { readwrite section .intvec_ram};
-place in IRAM1_region { readwrite };
-place at end of IRAM1_region { block HSTACK };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep { section .cy_m0p_image,
- section .cy_app_signature,
- section .cy_em_eeprom,
- section .cy_sflash_user_data,
- section .cy_sflash_nar,
- section .cy_sflash_public_key,
- section .cy_toc_part2,
- section .cy_rtoc_part2,
- section .cy_efuse,
- section .cy_xip,
- section .cymeta,
- };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start = 0x10000000;
-define exported symbol __cy_memory_0_length = 0x00200000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start = 0x14000000;
-define exported symbol __cy_memory_1_length = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start = 0x16000000;
-define exported symbol __cy_memory_2_length = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start = 0x18000000;
-define exported symbol __cy_memory_3_length = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start = 0x90700000;
-define exported symbol __cy_memory_4_length = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/*******************************************************************************
+* \file cy8c6xxa_cm4_dual.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+ define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+ define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+ * More about CM0+ prebuilt images, see here:
+ * https://github.com/cypresssemiconductorco/psoc6cm0p
+ */
+/* The size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
+define block RO {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in IROM1_region { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region { readwrite section .intvec_ram};
+place in IRAM1_region { readwrite };
+place at end of IRAM1_region { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep { section .cy_m0p_image,
+ section .cy_app_signature,
+ section .cy_em_eeprom,
+ section .cy_sflash_user_data,
+ section .cy_sflash_nar,
+ section .cy_sflash_public_key,
+ section .cy_toc_part2,
+ section .cy_rtoc_part2,
+ section .cy_efuse,
+ section .cy_xip,
+ section .cymeta,
+ };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start = 0x10000000;
+define exported symbol __cy_memory_0_length = 0x00200000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start = 0x14000000;
+define exported symbol __cy_memory_1_length = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start = 0x16000000;
+define exported symbol __cy_memory_2_length = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start = 0x18000000;
+define exported symbol __cy_memory_3_length = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start = 0x90700000;
+define exported symbol __cy_memory_4_length = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.sct b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.sct
index 4c3b188cc9..edd6046930 100644
--- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.sct
+++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.sct
@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08002000
-#define RAM_SIZE 0x000FD800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00200000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08002000
+#define RAM_SIZE 0x000FD800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
index 5af1eb2067..e557eedf7c 100644
--- a/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
+++ b/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
@@ -1,274 +1,274 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.60
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2019 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;* http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START 0x08002000
-#define RAM_SIZE 0x00045800
-; Flash
-#define FLASH_START 0x10000000
-#define FLASH_SIZE 0x00100000
-
-; Size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE 0x00001000
-
-; Size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE 0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START 0x14000000
-#define EM_EEPROM_SIZE 0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START 0x16000800
-#define SFLASH_USER_DATA_SIZE 0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START 0x16001A00
-#define SFLASH_NAR_SIZE 0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START 0x16007C00
-#define SFLASH_TOC_2_SIZE 0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START 0x16007E00
-#define SFLASH_RTOC_2_SIZE 0x00000200
-
-; External memory
-#define XIP_START 0x18000000
-#define XIP_SIZE 0x08000000
-
-; eFuse
-#define EFUSE_START 0x90700000
-#define EFUSE_SIZE 0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
- .cy_m0p_image +0 FLASH_CM0P_SIZE
- {
- * (.cy_m0p_image)
- }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
- ER_FLASH_VECTORS +0
- {
- * (RESET, +FIRST)
- }
-
- ER_FLASH_CODE +0 FIXED
- {
- * (InRoot$$Sections)
- * (+RO)
- }
-
- ER_RAM_VECTORS RAM_START UNINIT
- {
- * (RESET_RAM, +FIRST)
- }
-
- RW_RAM_DATA +0
- {
- * (.cy_ramfunc)
- * (+RW, +ZI)
- }
-
- ; Place variables in the section that should not be initialized during the
- ; device startup.
- RW_IRAM1 +0 UNINIT
- {
- * (.noinit)
- }
-
- ; Application heap area (HEAP)
- ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
- {
- }
-
- ; Stack region growing down
- ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
- {
- }
-
- ; Used for the digital signature of the secure application and the
- ; Bootloader SDK application. The size of the section depends on the required
- ; data size.
- .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
- {
- * (.cy_app_signature)
- }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
- .cy_em_eeprom +0
- {
- * (.cy_em_eeprom)
- }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
- .cy_sflash_user_data +0
- {
- * (.cy_sflash_user_data)
- }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
- .cy_sflash_nar +0
- {
- * (.cy_sflash_nar)
- }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
- .cy_sflash_public_key +0
- {
- * (.cy_sflash_public_key)
- }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
- .cy_toc_part2 +0
- {
- * (.cy_toc_part2)
- }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
- .cy_rtoc_part2 +0
- {
- * (.cy_rtoc_part2)
- }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
- .cy_xip +0
- {
- * (.cy_xip)
- }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
- .cy_efuse +0
- {
- * (.cy_efuse)
- }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
- .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length 0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start 0x14000000
-#define __cy_memory_1_length 0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start 0x16000000
-#define __cy_memory_2_length 0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start 0x18000000
-#define __cy_memory_3_length 0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start 0x90700000
-#define __cy_memory_4_length 0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4_dual.sct
+;* \version 2.60
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2019 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START 0x08002000
+#define RAM_SIZE 0x00045800
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00100000
+
+; Size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE 0x00001000
+
+; Size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE 0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+ .cy_m0p_image +0 FLASH_CM0P_SIZE
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK application. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ .cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length 0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start 0x14000000
+#define __cy_memory_1_length 0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start 0x16000000
+#define __cy_memory_2_length 0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start 0x18000000
+#define __cy_memory_3_length 0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start 0x90700000
+#define __cy_memory_4_length 0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */
diff --git a/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
index e30133713a..fd57bb7b51 100644
--- a/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
+++ b/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
@@ -1,240 +1,240 @@
-/***************************************************************************//**
-* \file cy8c6xx7_cm4_dual.icf
-* \version 2.60
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
-define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
- define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
- define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
- define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
- define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-/* Size of the Cortex-M0+ application image */
-define symbol FLASH_CM0P_SIZE = 0x2000;
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
-define block RO {first section .intvec, readonly};
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application image */
-place at start of IROM1_region { block CM0P_RO };
-
-/* Flash - Cortex-M4 application */
-place in IROM1_region { block RO };
-
-/* Used for the digital signature of the secure application and the Bootloader SDK application. */
-".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-".cy_xip" : place at start of EROM1_region { section .cy_xip };
-
-/* RAM */
-place at start of IRAM1_region { readwrite section .intvec_ram};
-place in IRAM1_region { readwrite };
-place at end of IRAM1_region { block HSTACK };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep { section .cy_m0p_image,
- section .cy_app_signature,
- section .cy_em_eeprom,
- section .cy_sflash_user_data,
- section .cy_sflash_nar,
- section .cy_sflash_public_key,
- section .cy_toc_part2,
- section .cy_rtoc_part2,
- section .cy_efuse,
- section .cy_xip,
- section .cymeta,
- };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start = 0x10000000;
-define exported symbol __cy_memory_0_length = 0x00100000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start = 0x14000000;
-define exported symbol __cy_memory_1_length = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start = 0x16000000;
-define exported symbol __cy_memory_2_length = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start = 0x18000000;
-define exported symbol __cy_memory_3_length = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start = 0x90700000;
-define exported symbol __cy_memory_4_length = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/***************************************************************************//**
+* \file cy8c6xx7_cm4_dual.icf
+* \version 2.60
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+ define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+ define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* Size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
+define block RO {first section .intvec, readonly};
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in IROM1_region { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+".cy_xip" : place at start of EROM1_region { section .cy_xip };
+
+/* RAM */
+place at start of IRAM1_region { readwrite section .intvec_ram};
+place in IRAM1_region { readwrite };
+place at end of IRAM1_region { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep { section .cy_m0p_image,
+ section .cy_app_signature,
+ section .cy_em_eeprom,
+ section .cy_sflash_user_data,
+ section .cy_sflash_nar,
+ section .cy_sflash_public_key,
+ section .cy_toc_part2,
+ section .cy_rtoc_part2,
+ section .cy_efuse,
+ section .cy_xip,
+ section .cymeta,
+ };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start = 0x10000000;
+define exported symbol __cy_memory_0_length = 0x00100000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start = 0x14000000;
+define exported symbol __cy_memory_1_length = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start = 0x16000000;
+define exported symbol __cy_memory_2_length = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start = 0x18000000;
+define exported symbol __cy_memory_3_length = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start = 0x90700000;
+define exported symbol __cy_memory_4_length = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/bsp/Vango/v85xx/Target_FLASH.icf b/bsp/Vango/v85xx/Target_FLASH.icf
index f10a7cb75e..0ef8edebb5 100644
--- a/bsp/Vango/v85xx/Target_FLASH.icf
+++ b/bsp/Vango/v85xx/Target_FLASH.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/acm32/acm32f0x0-nucleo/drivers/linker_scripts/link.icf b/bsp/acm32/acm32f0x0-nucleo/drivers/linker_scripts/link.icf
index bf3975c7e7..946d411c32 100644
--- a/bsp/acm32/acm32f0x0-nucleo/drivers/linker_scripts/link.icf
+++ b/bsp/acm32/acm32f0x0-nucleo/drivers/linker_scripts/link.icf
@@ -1,34 +1,34 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x0800;
-define symbol __ICFEDIT_size_heap__ = 0x0000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-
-export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
-
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0800;
+define symbol __ICFEDIT_size_heap__ = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+
diff --git a/bsp/acm32/acm32f4xx-nucleo/drivers/linker_scripts/link.icf b/bsp/acm32/acm32f4xx-nucleo/drivers/linker_scripts/link.icf
index 9b0aee84ff..b805795141 100644
--- a/bsp/acm32/acm32f4xx-nucleo/drivers/linker_scripts/link.icf
+++ b/bsp/acm32/acm32f4xx-nucleo/drivers/linker_scripts/link.icf
@@ -1,34 +1,34 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x0800;
-define symbol __ICFEDIT_size_heap__ = 0x0000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-
-export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
-
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0800;
+define symbol __ICFEDIT_size_heap__ = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+
diff --git a/bsp/airm2m/air105/board/linker_scripts/link.lds b/bsp/airm2m/air105/board/linker_scripts/link.lds
index 9b49ab1c3f..e8f4b1da46 100644
--- a/bsp/airm2m/air105/board/linker_scripts/link.lds
+++ b/bsp/airm2m/air105/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/airm2m/air32f103/board/linker_scripts/link.icf b/bsp/airm2m/air32f103/board/linker_scripts/link.icf
index 5019b2d673..758734c181 100644
--- a/bsp/airm2m/air32f103/board/linker_scripts/link.icf
+++ b/bsp/airm2m/air32f103/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/airm2m/air32f103/board/linker_scripts/link.lds b/bsp/airm2m/air32f103/board/linker_scripts/link.lds
index 644fe83314..5a45f64a27 100644
--- a/bsp/airm2m/air32f103/board/linker_scripts/link.lds
+++ b/bsp/airm2m/air32f103/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/allwinner/d1/link.lds b/bsp/allwinner/d1/link.lds
index a6784a00ff..e6a3829fc8 100644
--- a/bsp/allwinner/d1/link.lds
+++ b/bsp/allwinner/d1/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -38,7 +38,7 @@ SECTIONS
. = ALIGN(8);
- .text :
+ .text :
{
*(.text) /* remaining code */
*(.text.*) /* remaining code */
@@ -47,7 +47,7 @@ SECTIONS
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
-
+
/* section information for finsh shell */
. = ALIGN(8);
__fsymtab_start = .;
@@ -74,20 +74,20 @@ SECTIONS
_etext = .;
} > SRAM
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
*(.eh_frame_entry)
} > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
. = ALIGN(8);
- .data :
+ .data :
{
*(.data)
*(.data.*)
-
+
*(.data1)
*(.data1.*)
@@ -97,7 +97,7 @@ SECTIONS
*(.sdata)
*(.sdata.*)
} > SRAM
-
+
. = ALIGN(8);
.ctors :
{
@@ -139,7 +139,7 @@ SECTIONS
. = ALIGN(8);
- .sbss :
+ .sbss :
{
__bss_start = .;
*(.sbss)
diff --git a/bsp/allwinner/d1/link_stacksize.lds b/bsp/allwinner/d1/link_stacksize.lds
index 8685bc0f1c..14c2aad91f 100644
--- a/bsp/allwinner/d1/link_stacksize.lds
+++ b/bsp/allwinner/d1/link_stacksize.lds
@@ -1 +1 @@
-__STACKSIZE__ = 16384;
\ No newline at end of file
+__STACKSIZE__ = 16384;
diff --git a/bsp/allwinner/d1s/link.lds b/bsp/allwinner/d1s/link.lds
index a9f838120e..5a8daa054b 100644
--- a/bsp/allwinner/d1s/link.lds
+++ b/bsp/allwinner/d1s/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -38,7 +38,7 @@ SECTIONS
. = ALIGN(8);
- .text :
+ .text :
{
*(.text) /* remaining code */
*(.text.*) /* remaining code */
@@ -47,7 +47,7 @@ SECTIONS
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
-
+
/* section information for finsh shell */
. = ALIGN(8);
__fsymtab_start = .;
@@ -74,9 +74,9 @@ SECTIONS
_etext = .;
} > SRAM
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
*(.eh_frame_entry)
} > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
@@ -85,11 +85,11 @@ SECTIONS
__text_end = .;
__text_size = __text_end - __text_start;
- .data :
+ .data :
{
*(.data)
*(.data.*)
-
+
*(.data1)
*(.data1.*)
@@ -141,7 +141,7 @@ SECTIONS
. = ALIGN(8);
- .sbss :
+ .sbss :
{
__bss_start = .;
*(.sbss)
diff --git a/bsp/allwinner/d1s/link_stacksize.lds b/bsp/allwinner/d1s/link_stacksize.lds
index 8685bc0f1c..14c2aad91f 100644
--- a/bsp/allwinner/d1s/link_stacksize.lds
+++ b/bsp/allwinner/d1s/link_stacksize.lds
@@ -1 +1 @@
-__STACKSIZE__ = 16384;
\ No newline at end of file
+__STACKSIZE__ = 16384;
diff --git a/bsp/allwinner_tina/link.lds b/bsp/allwinner_tina/link.lds
index 8fb0e9e84d..7ce5caaa8a 100644
--- a/bsp/allwinner_tina/link.lds
+++ b/bsp/allwinner_tina/link.lds
@@ -4,7 +4,7 @@ OUTPUT_ARCH(arm)
SECTIONS
{
. = 0x80000000;
-
+
. = ALIGN(4);
__text_start = .;
.text :
@@ -12,7 +12,7 @@ SECTIONS
*(.vectors)
*(.text)
*(.text.*)
- KEEP(*(.fini))
+ KEEP(*(.fini))
/* section information for finsh shell */
. = ALIGN(4);
@@ -47,18 +47,18 @@ SECTIONS
.ctors :
{
PROVIDE(__ctors_start__ = .);
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
- PROVIDE(__ctors_end__ = .);
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+ PROVIDE(__ctors_end__ = .);
}
- .ARM.extab :
+ .ARM.extab :
{
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- }
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ }
/* The .ARM.exidx section is used for C++ exception handling. */
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
@@ -70,15 +70,15 @@ SECTIONS
_sidata = .;
}
__exidx_end = .;
-
+
.dtors :
{
PROVIDE(__dtors_start__ = .);
*crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
PROVIDE(__dtors_end__ = .);
}
@@ -89,30 +89,30 @@ SECTIONS
*(.data)
*(.data.*)
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- KEEP(*(.jcr*))
- . = ALIGN(4);
- /* All data end */
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
*(.gnu.linkonce.d*)
}
diff --git a/bsp/amebaz/bootloader_symbol.icf b/bsp/amebaz/bootloader_symbol.icf
index 092379e623..1c6ce92b41 100644
--- a/bsp/amebaz/bootloader_symbol.icf
+++ b/bsp/amebaz/bootloader_symbol.icf
@@ -1,13 +1,13 @@
-/* Bootloader symbol list */
-define exported symbol BOOT_FLASH_RDP_VALID = 0x08000123;
-define exported symbol BOOT_FLASH_SetStatusReg = 0x080003f5;
-define exported symbol BOOT_FLASH_Image1 = 0x0800043b;
-define exported symbol IMAGE1$$Base = 0x10002001;
-define exported symbol RamStartTable = 0x10002001;
-define exported symbol RAM_IMG1_VALID_PATTEN = 0x10002019;
-define exported symbol boot_export_symbol = 0x10002021;
-define exported symbol BOOT_System_Init1 = 0x10002251;
-define exported symbol BOOT_System_Init2 = 0x10002263;
-define exported symbol BOOT_Swd_Off = 0x10002275;
-define exported symbol boot_ram_end = 0x10002455;
-define exported symbol IMAGE1$$Limit = 0x10002459;
+/* Bootloader symbol list */
+define exported symbol BOOT_FLASH_RDP_VALID = 0x08000123;
+define exported symbol BOOT_FLASH_SetStatusReg = 0x080003f5;
+define exported symbol BOOT_FLASH_Image1 = 0x0800043b;
+define exported symbol IMAGE1$$Base = 0x10002001;
+define exported symbol RamStartTable = 0x10002001;
+define exported symbol RAM_IMG1_VALID_PATTEN = 0x10002019;
+define exported symbol boot_export_symbol = 0x10002021;
+define exported symbol BOOT_System_Init1 = 0x10002251;
+define exported symbol BOOT_System_Init2 = 0x10002263;
+define exported symbol BOOT_Swd_Off = 0x10002275;
+define exported symbol boot_ram_end = 0x10002455;
+define exported symbol IMAGE1$$Limit = 0x10002459;
diff --git a/bsp/amebaz/image2.icf b/bsp/amebaz/image2.icf
index 3c5deadf70..5d83361847 100644
--- a/bsp/amebaz/image2.icf
+++ b/bsp/amebaz/image2.icf
@@ -9,24 +9,24 @@ include "rom_symbol_v01_iar.icf";
/****************************************
* Memory Regions *
****************************************/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_ROMBSS_RAM_start__ = 0x10000000;
-define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF;
+define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF;
define symbol __ICFEDIT_region_BOOTLOADER_RAM_start__ = 0x10002000;
define symbol __ICFEDIT_region_BOOTLOADER_RAM_end__ = 0x10004FFF;
-define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000;
-define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1002FFFF;
-define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000;
-define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF;
-define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000;
-define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF;
-define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000;
-define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF;
-define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20;
-define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF;
-define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20;
-define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000;
+define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1002FFFF;
+define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000;
+define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF;
+define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000;
+define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF;
+define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000;
+define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF;
+define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20;
+define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF;
+define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20;
+define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF;
/****************************************
* Sizes *
****************************************/
@@ -68,16 +68,16 @@ keep { section .hal.rom.bss* };
keep { section .wlan_ram_map* };
keep { section .libc.ram.bss* };
keep { section .ssl_ram_map* };
-define block .hal.rom.bss with fixed order{ section .ram_vector_table1,
+define block .hal.rom.bss with fixed order{ section .ram_vector_table1,
section .ram_vector_table2,
section .ram_vector_table3,
section .hal.rom.bss*,
section .wlan_ram_map*,
section .libc.ram.bss*,
- section .ssl_ram_map*,
+ section .ssl_ram_map*,
};
define block ROM_BSS with fixed order { block .hal.rom.bss};
-place at start of ROM_BSS_region { readwrite,
+place at start of ROM_BSS_region { readwrite,
block ROM_BSS,
};
/****************************************
@@ -86,21 +86,21 @@ place at start of ROM_BSS_region { readwrite,
keep { section .image1.entry.data* };
keep { section .image1.validate.rodata* };
define block .ram_image1.entry with fixed order{section .image1.entry.data*,
- section .image1.validate.rodata*,
- };
+ section .image1.validate.rodata*,
+ };
keep { section .boot.ram.text* };
keep { section .boot.rodata* };
define block .ram_image1.text with fixed order{section .boot.ram.text*,
- section .boot.rodata*,
- };
+ section .boot.rodata*,
+ };
keep { section .boot.ram.data* };
define block .ram_image1.data with fixed order{section .boot.ram.data*,
- };
+ };
keep { section .boot.ram.bss* };
define block .ram_image1.bss with fixed order{section .boot.ram.bss*,
- };
+ };
define block IMAGE1 with fixed order { block .ram_image1.entry, block .ram_image1.text, block .ram_image1.data, block .ram_image1.bss};
-place at start of BOOT_RAM_region { readwrite,
+place at start of BOOT_RAM_region { readwrite,
block IMAGE1,
};
/****************************************
@@ -109,39 +109,39 @@ place at start of BOOT_RAM_region { readwrite,
keep { section .image2.entry.data* };
keep { section .image2.validate.rodata* };
define block .ram_image2.entry with fixed order{ section .image2.entry.data*,
- section .image2.validate.rodata*,
- };
+ section .image2.validate.rodata*,
+ };
define block SHT$$PREINIT_ARRAY { preinit_array };
define block SHT$$INIT_ARRAY { init_array };
define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY,
- block SHT$$INIT_ARRAY };
-define block .ram.data with fixed order{ section .data*,
- section DATA,
- section .iar.init_table,
- section __DLIB_PERTHREAD,
- block CPP_INIT,
- section .mdns.data,
- section .mdns.text
- };
+ block SHT$$INIT_ARRAY };
+define block .ram.data with fixed order{ section .data*,
+ section DATA,
+ section .iar.init_table,
+ section __DLIB_PERTHREAD,
+ block CPP_INIT,
+ section .mdns.data,
+ section .mdns.text
+ };
define block .ram.text with fixed order{ section .image2.ram.text*,
- };
+ };
define block IMAGE2 with fixed order { block .ram_image2.entry,
- block .ram.data,
- block .ram.text,
- };
+ block .ram.data,
+ block .ram.text,
+ };
define block .ram_image2.bss with fixed order{ section .bss*,
section COMMON,
};
define block .ram_image2.skb.bss with fixed order{ section .bdsram.data* };
define block .ram_heap.data with fixed order{ section .bfsram.data* };
-place in BD_RAM_region { readwrite,
- block IMAGE2,
- block .ram_image2.bss,
- block .ram_image2.skb.bss,
- block .ram_heap.data,
- section .heap.stdlib,
+place in BD_RAM_region { readwrite,
+ block IMAGE2,
+ block .ram_image2.bss,
+ block .ram_image2.skb.bss,
+ block .ram_heap.data,
+ section .heap.stdlib,
last block HEAP,
- };
+ };
/****************************************
* XIP BOOT Section config *
****************************************/
@@ -149,8 +149,8 @@ keep { section .flashboot.text* };
define block .xip_image1.text with fixed order{ section .flashboot.text* };
define block Bootloader with fixed order { section LOADER };
place at start of XIP_BOOT_region { block Bootloader,
- readwrite,
- block .xip_image1.text };
+ readwrite,
+ block .xip_image1.text };
/****************************************
* XIP OTA1 Section config *
****************************************/
@@ -158,30 +158,30 @@ keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
define block .xip_image2.text with fixed order{ section .img2_custom_signature*,
- section .text*,
- section .rodata*,
- section .debug_trace,
- section CODE,
- section Veneer, // object startup.o,
- section FSymTab,
- section VSymTab,
- section .rti_fn*,
- };
-place at start of XIP_OTA1_region { readwrite,
- block .xip_image2.text };
+ section .text*,
+ section .rodata*,
+ section .debug_trace,
+ section CODE,
+ section Veneer, // object startup.o,
+ section FSymTab,
+ section VSymTab,
+ section .rti_fn*,
+ };
+place at start of XIP_OTA1_region { readwrite,
+ block .xip_image2.text };
/****************************************
* RDP Section config *
****************************************/
-keep { section .rdp.ram.text* };
-keep { section .rdp.ram.data* };
+keep { section .rdp.ram.text* };
+keep { section .rdp.ram.data* };
define block .RDP_RAM with fixed order {
- section .rdp.ram.text*,
- section .rdp.ram.data* };
+ section .rdp.ram.text*,
+ section .rdp.ram.data* };
place at start of RDP_RAM_region{
- readwrite,
- block .RDP_RAM };
-define exported symbol __ram_start_table_start__= 0x10002000; // use in rom
-define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code
-define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code
+ readwrite,
+ block .RDP_RAM };
+define exported symbol __ram_start_table_start__= 0x10002000; // use in rom
+define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code
+define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code
define exported symbol __flash_text_start__= 0x0800b020; // needed by ram code
-define exported symbol boot_export_symbol = 0x10002020;
+define exported symbol boot_export_symbol = 0x10002020;
diff --git a/bsp/amebaz/rom_symbol_v01_iar.icf b/bsp/amebaz/rom_symbol_v01_iar.icf
index f4b2a14b60..96d8b35cce 100644
--- a/bsp/amebaz/rom_symbol_v01_iar.icf
+++ b/bsp/amebaz/rom_symbol_v01_iar.icf
@@ -1,1424 +1,1424 @@
-define exported symbol __vectors_table = 0x0;
-define exported symbol Reset_Handler = 0x101;
-define exported symbol NMI_Handler = 0x115;
-/*define exported symbol HardFault_Handler = 0x119;*/
-define exported symbol MemManage_Handler = 0x12d;
-define exported symbol BusFault_Handler = 0x131;
-define exported symbol UsageFault_Handler = 0x135;
-define exported symbol VSprintf = 0x201;
-define exported symbol DiagPrintf = 0x4dd;
-define exported symbol DiagSPrintf = 0x509;
-define exported symbol DiagSnPrintf = 0x535;
-define exported symbol prvDiagPrintf = 0x7ed;
-define exported symbol prvDiagSPrintf = 0x821;
-define exported symbol UARTIMG_Write = 0x855;
-define exported symbol UARTIMG_Download = 0x901;
-define exported symbol _memcmp = 0x991;
-define exported symbol _memcpy = 0x9c5;
-define exported symbol _memset = 0xa7d;
-define exported symbol DumpForOneBytes = 0xae9;
-define exported symbol CmdRomHelp = 0xc69;
-define exported symbol CmdDumpWord = 0xccd;
-define exported symbol CmdWriteWord = 0xd7d;
-define exported symbol CmdFlash = 0xdd1;
-define exported symbol CmdEfuse = 0x12c1;
-define exported symbol CmdDumpByte = 0x1775;
-define exported symbol CmdDumpHalfWord = 0x17c9;
-define exported symbol CmdWriteByte = 0x1881;
-define exported symbol SramReadWriteCpy = 0x18c1;
-define exported symbol SramReadWriteTest = 0x19f9;
-define exported symbol CmdSRamTest = 0x1ac9;
-define exported symbol GetRomCmdNum = 0x1b59;
-define exported symbol Rand = 0x1b5d;
-define exported symbol Rand_Arc4 = 0x1bdd;
-define exported symbol RandBytes_Get = 0x1c0d;
-define exported symbol Isspace = 0x1c59;
-define exported symbol Strtoul = 0x1c6d;
-define exported symbol ArrayInitialize = 0x1d15;
-define exported symbol GetArgc = 0x1d29;
-define exported symbol GetArgv = 0x1d55;
-define exported symbol UartLogCmdExecute = 0x1db1;
-define exported symbol UartLogShowBackSpace = 0x1e49;
-define exported symbol UartLogRecallOldCmd = 0x1e7d;
-define exported symbol UartLogHistoryCmd = 0x1eb1;
-define exported symbol UartLogCmdChk = 0x1f2d;
-define exported symbol UartLogIrqHandle = 0x2035;
-define exported symbol RtlConsolInit = 0x2101;
-define exported symbol RtlConsolTaskRom = 0x218d;
-define exported symbol RtlExitConsol = 0x21b9;
-define exported symbol RtlConsolRom = 0x2205;
-define exported symbol BKUP_Write = 0x2249;
-define exported symbol BKUP_Read = 0x226d;
-define exported symbol BKUP_Set = 0x228d;
-define exported symbol BKUP_Clear = 0x22b9;
-define exported symbol NCO32K_Init = 0x22e9;
-define exported symbol EXT32K_Cmd = 0x2349;
-define exported symbol NCO8M_Init = 0x2365;
-define exported symbol NCO8M_Cmd = 0x23bd;
-define exported symbol ISO_Set = 0x23d9;
-define exported symbol PLL0_Set = 0x23f1;
-define exported symbol PLL1_Set = 0x2409;
-define exported symbol PLL2_Set = 0x2421;
-define exported symbol PLL3_Set = 0x2439;
-define exported symbol XTAL0_Set = 0x2451;
-define exported symbol XTAL1_Set = 0x2469;
-define exported symbol XTAL2_Set = 0x2481;
-define exported symbol XTAL_ClkGet = 0x2499;
-define exported symbol CPU_ClkSet = 0x24b1;
-define exported symbol CPU_ClkGet = 0x24c5;
-define exported symbol OSC32K_Calibration = 0x24e5;
-define exported symbol OSC32K_Cmd = 0x25f9;
-define exported symbol OSC8M_Get = 0x2631;
-define exported symbol rtl_cryptoEngine_SrcDesc_Show = 0x2641;
-define exported symbol rtl_cryptoEngine_info = 0x27f1;
-define exported symbol rtl_cryptoEngine_init = 0x2949;
-define exported symbol rtl_crypto_md5_init = 0x2975;
-define exported symbol rtl_crypto_md5_process = 0x29b1;
-define exported symbol rtl_crypto_md5 = 0x2a09;
-define exported symbol rtl_crypto_sha1_init = 0x2a2d;
-define exported symbol rtl_crypto_sha1_process = 0x2a69;
-define exported symbol rtl_crypto_sha1 = 0x2a9d;
-define exported symbol rtl_crypto_sha2_init = 0x2ac1;
-define exported symbol rtl_crypto_sha2_process = 0x2b15;
-define exported symbol rtl_crypto_sha2 = 0x2b4d;
-define exported symbol rtl_crypto_hmac_md5_init = 0x2b71;
-define exported symbol rtl_crypto_hmac_md5_process = 0x2bd1;
-define exported symbol rtl_crypto_hmac_md5 = 0x2c0d;
-define exported symbol rtl_crypto_hmac_sha1_init = 0x2c31;
-define exported symbol rtl_crypto_hmac_sha1_process = 0x2c91;
-define exported symbol rtl_crypto_hmac_sha1 = 0x2cc9;
-define exported symbol rtl_crypto_hmac_sha2_init = 0x2ced;
-define exported symbol rtl_crypto_hmac_sha2_process = 0x2d65;
-define exported symbol rtl_crypto_hmac_sha2 = 0x2da1;
-define exported symbol rtl_crypto_aes_cbc_init = 0x2dc5;
-define exported symbol rtl_crypto_aes_cbc_encrypt = 0x2dfd;
-define exported symbol rtl_crypto_aes_cbc_decrypt = 0x2e45;
-define exported symbol rtl_crypto_aes_ecb_init = 0x2e8d;
-define exported symbol rtl_crypto_aes_ecb_encrypt = 0x2ec5;
-define exported symbol rtl_crypto_aes_ecb_decrypt = 0x2ef5;
-define exported symbol rtl_crypto_aes_ctr_init = 0x2f25;
-define exported symbol rtl_crypto_aes_ctr_encrypt = 0x2f5d;
-define exported symbol rtl_crypto_aes_ctr_decrypt = 0x2f99;
-define exported symbol rtl_crypto_3des_cbc_init = 0x2fd5;
-define exported symbol rtl_crypto_3des_cbc_encrypt = 0x300d;
-define exported symbol rtl_crypto_3des_cbc_decrypt = 0x3055;
-define exported symbol rtl_crypto_3des_ecb_init = 0x309d;
-define exported symbol rtl_crypto_3des_ecb_encrypt = 0x30d5;
-define exported symbol rtl_crypto_3des_ecb_decrypt = 0x311d;
-define exported symbol rtl_crypto_des_cbc_init = 0x3165;
-define exported symbol rtl_crypto_des_cbc_encrypt = 0x319d;
-define exported symbol rtl_crypto_des_cbc_decrypt = 0x31f5;
-define exported symbol rtl_crypto_des_ecb_init = 0x324d;
-define exported symbol rtl_crypto_des_ecb_encrypt = 0x3285;
-define exported symbol rtl_crypto_des_ecb_decrypt = 0x32dd;
-define exported symbol SYSTIMER_Init = 0x3335;
-define exported symbol SYSTIMER_TickGet = 0x33a1;
-define exported symbol SYSTIMER_GetPassTime = 0x33c1;
-define exported symbol DelayNop = 0x3401;
-define exported symbol DelayUs = 0x3411;
-define exported symbol DelayMs = 0x346d;
-define exported symbol USOC_DongleSpecialCmd = 0x3481;
-define exported symbol USOC_DongleCmd = 0x35d9;
-define exported symbol USOC_DongleIsr = 0x35f9;
-define exported symbol USOC_SIE_INTConfig = 0x3621;
-define exported symbol USOC_SIE_INTClear = 0x3639;
-define exported symbol USOC_PHY_Write = 0x3645;
-define exported symbol USOC_PHY_Read = 0x3679;
-define exported symbol USOC_PHY_Autoload = 0x36c1;
-define exported symbol USOC_DongleInit = 0x37a5;
-define exported symbol EFUSE_USER_Read = 0x386d;
-define exported symbol EFUSE_USER1_Read = 0x3971;
-define exported symbol EFUSE_USER2_Read = 0x397d;
-define exported symbol EFUSE_USER3_Read = 0x3989;
-define exported symbol EFUSE_RemainLength = 0x3995;
-define exported symbol EFUSE_USER_Write = 0x3a21;
-define exported symbol EFUSE_USER1_Write = 0x3bb1;
-define exported symbol EFUSE_USER2_Write = 0x3bc1;
-define exported symbol EFUSE_USER3_Write = 0x3bd1;
-define exported symbol EFUSE_OTP_Read1B = 0x3be1;
-define exported symbol EFUSE_OTP_Write1B = 0x3c01;
-define exported symbol EFUSE_OTP_Read32B = 0x3c21;
-define exported symbol EFUSE_OTP_Write32B = 0x3c4d;
-define exported symbol EFUSE_RDP_EN = 0x3cad;
-define exported symbol EFUSE_RDP_KEY = 0x3ccd;
-define exported symbol EFUSE_OTF_KEY = 0x3cf9;
-define exported symbol EFUSE_JTAG_OFF = 0x3d25;
-define exported symbol PAD_DrvStrength = 0x3d45;
-define exported symbol PAD_PullCtrl = 0x3d75;
-define exported symbol Pinmux_Config = 0x3dc5;
-define exported symbol Pinmux_ConfigGet = 0x3dfd;
-define exported symbol Pinmux_Deinit = 0x3e19;
-define exported symbol PINMUX_UART0_Ctrl = 0x3e39;
-define exported symbol PINMUX_UART1_Ctrl = 0x3e81;
-define exported symbol PINMUX_UARTLOG_Ctrl = 0x3ea9;
-define exported symbol PINMUX_SPI0_Ctrl = 0x3ef9;
-define exported symbol PINMUX_SPI1_Ctrl = 0x3f8d;
-define exported symbol PINMUX_SPIF_Ctrl = 0x400d;
-define exported symbol PINMUX_I2C0_Ctrl = 0x406d;
-define exported symbol PINMUX_I2C1_Ctrl = 0x40e1;
-define exported symbol PINMUX_SDIOD_Ctrl = 0x4151;
-define exported symbol PINMUX_I2S0_Ctrl = 0x41e5;
-define exported symbol PINMUX_SWD_Ctrl = 0x4265;
-define exported symbol PINMUX_SWD_OFF = 0x42b5;
-define exported symbol PINMUX_SWD_REG = 0x42d9;
-define exported symbol PINMUX_Ctrl = 0x42fd;
-define exported symbol SOCPS_BackupCPUClk = 0x4391;
-define exported symbol SOCPS_RestoreCPUClk = 0x43b1;
-define exported symbol SOCPS_BootFromPS = 0x43d1;
-define exported symbol SOCPS_TrapPin = 0x43f1;
-define exported symbol SOCPS_ANACKSel = 0x4411;
-define exported symbol SOCPS_CLKCal = 0x442d;
-define exported symbol SOCPS_SetWakeEvent = 0x4485;
-define exported symbol SOCPS_ClearWakeEvent = 0x449d;
-define exported symbol SOCPS_WakePinsCtrl = 0x44a9;
-define exported symbol SOCPS_WakePinCtrl = 0x44d9;
-define exported symbol SOCPS_WakePinClear = 0x4529;
-define exported symbol SOCPS_GetANATimerParam = 0x4539;
-define exported symbol SOCPS_SetANATimer = 0x4575;
-define exported symbol SOCPS_SetReguWakepin = 0x45dd;
-define exported symbol SOCPS_SetReguTimer = 0x4605;
-define exported symbol SOCPS_PWROption = 0x46d9;
-define exported symbol SOCPS_PWROptionExt = 0x46e5;
-define exported symbol SOCPS_PWRMode = 0x46f9;
-define exported symbol SOCPS_SNZMode = 0x4721;
-define exported symbol SOCPS_DeepStandby = 0x473d;
-define exported symbol SOCPS_DeepSleep = 0x4791;
-define exported symbol SDIO_StructInit = 0x47d5;
-define exported symbol SDIO_Init = 0x47f1;
-define exported symbol SDIO_INTClear = 0x486d;
-define exported symbol SDIO_INTConfig = 0x487d;
-define exported symbol SDIO_RPWM1_Get = 0x4895;
-define exported symbol SDIO_RPWM2_Get = 0x48a1;
-define exported symbol SDIO_CPWM1_Set = 0x48ad;
-define exported symbol SDIO_CPWM2_Set = 0x48c1;
-define exported symbol SDIO_RXBD_RPTR_Get = 0x48dd;
-define exported symbol SDIO_RXBD_WPTR_Set = 0x48e9;
-define exported symbol SDIO_TXBD_WPTR_Get = 0x48f5;
-define exported symbol SDIO_TXBD_RPTR_Set = 0x4901;
-define exported symbol SDIO_DMA_Reset = 0x490d;
-define exported symbol BOOT_ROM_Simulation = 0x4919;
-define exported symbol USOC_BOOT_TXBD_Proc = 0x491d;
-define exported symbol USOC_BOOT_Init = 0x4a3d;
-define exported symbol USB_Boot_ROM = 0x4aa9;
-define exported symbol USOC_CH_Cmd = 0x4b59;
-define exported symbol USOC_Cmd = 0x4bb1;
-define exported symbol USOC_PHY_Cmd = 0x4bf5;
-define exported symbol USOC_MODE_Cfg = 0x4c09;
-define exported symbol USOC_TXBD_SWIDX_Cfg = 0x4c25;
-define exported symbol USOC_TXBD_SWIDX_Get = 0x4c2d;
-define exported symbol USOC_TXBD_HWIDX_Get = 0x4c35;
-define exported symbol USOC_RXBD_HWIDX_Get = 0x4c3d;
-define exported symbol USOC_RXBD_SWIDX_Cfg = 0x4c45;
-define exported symbol USOC_RXBD_SWIDX_Get = 0x4c4d;
-define exported symbol USOC_StructInit = 0x4c55;
-define exported symbol USOC_Init = 0x4c85;
-define exported symbol USOC_SW_RST = 0x4d7d;
-define exported symbol USOC_INTCfg = 0x4d91;
-define exported symbol USOC_INTClr = 0x4d95;
-define exported symbol USOC_INTGet = 0x4d9d;
-define exported symbol USOC_MIT_Cfg = 0x4da1;
-define exported symbol USOC_TXSTUCK_Cfg = 0x4dc5;
-define exported symbol USOC_RXSTUCK_Cfg = 0x4de9;
-define exported symbol USOC_POWER_On = 0x4e0d;
-define exported symbol ADC_RXGDMA_Init = 0x4e9d;
-define exported symbol ADC_SetAudio = 0x4f45;
-define exported symbol ADC_SetAnalog = 0x4f61;
-define exported symbol ADC_Cmd = 0x4fbd;
-define exported symbol ADC_INTConfig = 0x5031;
-define exported symbol ADC_SetOneShot = 0x5049;
-define exported symbol ADC_SetComp = 0x50fd;
-define exported symbol ADC_INTClear = 0x517d;
-define exported symbol ADC_INTClearPendingBits = 0x5189;
-define exported symbol ADC_GetISR = 0x5195;
-define exported symbol ADC_Read = 0x51a1;
-define exported symbol ADC_ReceiveBuf = 0x51ad;
-define exported symbol ADC_InitStruct = 0x5205;
-define exported symbol ADC_Init = 0x524d;
-define exported symbol BOOT_ROM_ShowBuildInfo = 0x52ed;
-define exported symbol BOOT_ROM_OTFCheck = 0x5335;
-define exported symbol BOOT_ROM_InitFlash = 0x5345;
-define exported symbol BOOT_ROM_FromFlash = 0x5405;
-define exported symbol BOOT_ROM_InitUsb = 0x5511;
-define exported symbol BOOT_ROM_Process = 0x553d;
-define exported symbol BOOT_ROM_InitDebugFlg = 0x5605;
-define exported symbol HalResetVsr = 0x5639;
-define exported symbol Cache_Enable = 0x5811;
-define exported symbol Cache_Flush = 0x5831;
-define exported symbol Cache_Debug = 0x5851;
-define exported symbol CRYPTO_AlignToBe32 = 0x58bd;
-define exported symbol CRYPTO_MemDump = 0x58d5;
-define exported symbol CRYPTO_GetAESKey = 0x599d;
-define exported symbol CRYPTO_SetAESKey = 0x5cb5;
-define exported symbol CRYPTO_SetSecurityMode = 0x5d29;
-define exported symbol CRYPTO_Init = 0x5f5d;
-define exported symbol CRYPTO_DeInit = 0x60b9;
-define exported symbol CRYPTO_Reset = 0x6101;
-define exported symbol CRYPTO_Process = 0x6129;
-define exported symbol CRYPTO_CipherInit = 0x6a11;
-define exported symbol CRYPTO_CipherEncrypt = 0x6a35;
-define exported symbol CRYPTO_CipherDecrypt = 0x6a61;
-define exported symbol CRYPTO_SetCheckSumEn = 0x6a95;
-define exported symbol CRYPTO_GetCheckSumData = 0x6ab1;
-define exported symbol LOGUART_StructInit = 0x6abd;
-define exported symbol LOGUART_Init = 0x6ad5;
-define exported symbol LOGUART_PutChar = 0x6b15;
-define exported symbol LOGUART_GetChar = 0x6b49;
-define exported symbol LOGUART_GetIMR = 0x6b65;
-define exported symbol LOGUART_SetIMR = 0x6b71;
-define exported symbol LOGUART_WaitBusy = 0x6b7d;
-define exported symbol DIAG_UartInit = 0x6b9d;
-define exported symbol DIAG_UartReInit = 0x6c25;
-define exported symbol EFUSE_PowerSwitchROM = 0x6c49;
-define exported symbol EFUSE_OneByteReadROM = 0x6d65;
-define exported symbol EFUSE_OneByteWriteROM = 0x6e0d;
-define exported symbol EFUSE_PG_Packet = 0x6e29;
-define exported symbol EFUSE_LogicalMap_Read = 0x7091;
-define exported symbol EFUSE_LogicalMap_Write = 0x71f5;
-define exported symbol FLASH_SetSpiMode = 0x73dd;
-define exported symbol FLASH_RxCmd = 0x7465;
-define exported symbol FLASH_WaitBusy = 0x74cd;
-define exported symbol FLASH_RxData = 0x754d;
-define exported symbol FLASH_TxCmd = 0x75cd;
-define exported symbol FLASH_WriteEn = 0x763d;
-define exported symbol FLASH_TxData12B = 0x7661;
-define exported symbol FLASH_SetStatus = 0x7735;
-define exported symbol FLASH_Erase = 0x7755;
-define exported symbol FLASH_DeepPowerDown = 0x77f5;
-define exported symbol FLASH_SetStatusBits = 0x784d;
-define exported symbol FLASH_Calibration = 0x791d;
-define exported symbol FLASH_StructInit_Micron = 0x7a65;
-define exported symbol FLASH_StructInit_MXIC = 0x7af5;
-define exported symbol FLASH_StructInit_GD = 0x7b81;
-define exported symbol FLASH_StructInit = 0x7c11;
-define exported symbol FLASH_Init = 0x7ca1;
-define exported symbol FLASH_ClockDiv = 0x7d15;
-define exported symbol FLASH_CalibrationInit = 0x7d99;
-define exported symbol FLASH_Calibration500MPSCmd = 0x7db1;
-define exported symbol FLASH_CalibrationPhase = 0x7dcd;
-define exported symbol FLASH_CalibrationPhaseIdx = 0x7e59;
-define exported symbol FLASH_CalibrationNewCmd = 0x7e6d;
-define exported symbol FLASH_CalibrationNew = 0x7ea9;
-define exported symbol GDMA_StructInit = 0x80dd;
-define exported symbol GDMA_SetLLP = 0x80f9;
-define exported symbol GDMA_ClearINTPendingBit = 0x8191;
-define exported symbol GDMA_ClearINT = 0x81d5;
-define exported symbol GDMA_INTConfig = 0x8211;
-define exported symbol GDMA_Cmd = 0x8259;
-define exported symbol GDMA_Init = 0x828d;
-define exported symbol GDMA_ChCleanAutoReload = 0x83c1;
-define exported symbol GDMA_SetSrcAddr = 0x83f9;
-define exported symbol GDMA_GetSrcAddr = 0x8411;
-define exported symbol GDMA_GetDstAddr = 0x8429;
-define exported symbol GDMA_SetDstAddr = 0x843d;
-define exported symbol GDMA_SetBlkSize = 0x8459;
-define exported symbol GDMA_GetBlkSize = 0x8489;
-define exported symbol GDMA_ChnlRegister = 0x84a1;
-define exported symbol GDMA_ChnlUnRegister = 0x8529;
-define exported symbol GDMA_ChnlAlloc = 0x8591;
-define exported symbol GDMA_ChnlFree = 0x8615;
-define exported symbol GPIO_INTMode = 0x864d;
-define exported symbol GPIO_INTConfig = 0x86e5;
-define exported symbol GPIO_INTHandler = 0x8725;
-define exported symbol GPIO_Direction = 0x8771;
-define exported symbol GPIO_Init = 0x87a1;
-define exported symbol GPIO_DeInit = 0x886d;
-define exported symbol GPIO_ReadDataBit = 0x88c9;
-define exported symbol GPIO_WriteBit = 0x88ed;
-define exported symbol GPIO_PortDirection = 0x891d;
-define exported symbol GPIO_PortRead = 0x893d;
-define exported symbol GPIO_PortWrite = 0x894d;
-define exported symbol GPIO_UserRegIrq = 0x8969;
-define exported symbol I2C_StructInit = 0x899d;
-define exported symbol I2C_SetSpeed = 0x89e5;
-define exported symbol I2C_SetSlaveAddress = 0x8b3d;
-define exported symbol I2C_CheckFlagState = 0x8b79;
-define exported symbol I2C_INTConfig = 0x8bad;
-define exported symbol I2C_ClearINT = 0x8be5;
-define exported symbol I2C_ClearAllINT = 0x8c85;
-define exported symbol I2C_Init = 0x8cad;
-define exported symbol I2C_GetRawINT = 0x8dc9;
-define exported symbol I2C_GetINT = 0x8df1;
-define exported symbol I2C_MasterSendNullData = 0x8e19;
-define exported symbol I2C_MasterSend = 0x8e65;
-define exported symbol I2C_SlaveSend = 0x8ead;
-define exported symbol I2C_ReceiveData = 0x8ed9;
-define exported symbol I2C_MasterWrite = 0x8f05;
-define exported symbol I2C_MasterReadDW = 0x8f89;
-define exported symbol I2C_MasterRead = 0x9019;
-define exported symbol I2C_SlaveWrite = 0x9089;
-define exported symbol I2C_SlaveRead = 0x90f1;
-define exported symbol I2C_MasterRepeatRead = 0x9141;
-define exported symbol I2C_Cmd = 0x91c1;
-define exported symbol I2C_PinMuxInit = 0x91fd;
-define exported symbol I2C_PinMuxDeInit = 0x9255;
-define exported symbol I2C_DMAControl = 0x92ad;
-define exported symbol I2C_DmaMode1Config = 0x92e9;
-define exported symbol I2C_DmaMode2Config = 0x9331;
-define exported symbol I2C_TXGDMA_Init = 0x9375;
-define exported symbol I2C_RXGDMA_Init = 0x9459;
-define exported symbol I2C_Sleep_Cmd = 0x9521;
-define exported symbol I2C_WakeUp = 0x95a1;
-define exported symbol I2S_StructInit = 0x95e9;
-define exported symbol I2S_Cmd = 0x9611;
-define exported symbol I2S_TxDmaCmd = 0x962d;
-define exported symbol I2S_RxDmaCmd = 0x9641;
-define exported symbol I2S_INTConfig = 0x9655;
-define exported symbol I2S_INTClear = 0x965d;
-define exported symbol I2S_INTClearAll = 0x9665;
-define exported symbol I2S_Init = 0x9671;
-define exported symbol I2S_ISRGet = 0x97a9;
-define exported symbol I2S_SetRate = 0x97b5;
-define exported symbol I2S_SetWordLen = 0x9811;
-define exported symbol I2S_SetChNum = 0x9839;
-define exported symbol I2S_SetPageNum = 0x9861;
-define exported symbol I2S_SetPageSize = 0x9895;
-define exported symbol I2S_GetPageSize = 0x98a9;
-define exported symbol I2S_SetDirection = 0x98b5;
-define exported symbol I2S_SetDMABuf = 0x98dd;
-define exported symbol I2S_TxPageBusy = 0x9905;
-define exported symbol I2S_GetTxPage = 0x9911;
-define exported symbol I2S_GetRxPage = 0x991d;
-define exported symbol I2S_SetTxPageAddr = 0x9929;
-define exported symbol I2S_GetTxPageAddr = 0x9939;
-define exported symbol I2S_SetRxPageAddr = 0x9949;
-define exported symbol I2S_GetRxPageAddr = 0x9959;
-define exported symbol I2S_TxPageDMA_EN = 0x9969;
-define exported symbol I2S_RxPageDMA_EN = 0x998d;
-define exported symbol io_assert_failed = 0x99d9;
-define exported symbol OTF_init = 0x99fd;
-define exported symbol OTF_Cmd = 0x9a79;
-define exported symbol OTF_Mask = 0x9a8d;
-define exported symbol KEY_Request = 0x9add;
-define exported symbol RDP_EN_Request = 0x9b21;
-define exported symbol RCC_PeriphClockCmd = 0x9b65;
-define exported symbol FUNC_HCI_COM = 0x9c95;
-define exported symbol RTC_ByteToBcd2 = 0x9cad;
-define exported symbol RTC_Bcd2ToByte = 0x9cc9;
-define exported symbol RTC_ClokSource = 0x9cdd;
-define exported symbol RTC_EnterInitMode = 0x9d19;
-define exported symbol RTC_ExitInitMode = 0x9d51;
-define exported symbol RTC_WaitForSynchro = 0x9d61;
-define exported symbol RTC_BypassShadowCmd = 0x9da9;
-define exported symbol RTC_StructInit = 0x9dd9;
-define exported symbol RTC_Init = 0x9de5;
-define exported symbol RTC_TimeStructInit = 0x9e7d;
-define exported symbol RTC_SetTime = 0x9e8d;
-define exported symbol RTC_GetTime = 0x9ff9;
-define exported symbol RTC_SetAlarm = 0xa051;
-define exported symbol RTC_AlarmStructInit = 0xa211;
-define exported symbol RTC_GetAlarm = 0xa231;
-define exported symbol RTC_AlarmCmd = 0xa2a1;
-define exported symbol RTC_AlarmClear = 0xa2f5;
-define exported symbol RTC_DayLightSavingConfig = 0xa305;
-define exported symbol RTC_GetStoreOperation = 0xa355;
-define exported symbol RTC_OutputConfig = 0xa365;
-define exported symbol RTC_SmoothCalibConfig = 0xa39d;
-define exported symbol SDIO_IsTimeout = 0xa459;
-define exported symbol SDIOB_Init = 0xa481;
-define exported symbol SDIOB_INTConfig = 0xa575;
-define exported symbol SDIOB_DeInit = 0xa591;
-define exported symbol SDIOB_H2C_WriteMem = 0xa5d9;
-define exported symbol SDIOB_H2C_SetMem = 0xa605;
-define exported symbol SDIOB_H2C_DataHandle = 0xa631;
-define exported symbol SDIOB_H2C_DataReady = 0xa73d;
-define exported symbol SDIOB_IRQ_Handler_BH = 0xa80d;
-define exported symbol SDIOB_H2C_Task = 0xa8c9;
-define exported symbol SDIO_Boot_Up = 0xa8e5;
-define exported symbol SPI_DmaInit = 0xa91d;
-define exported symbol SPI_DataHandle = 0xa9d1;
-define exported symbol SPI_Boot_DmaRxIrqHandle = 0xaa01;
-define exported symbol SPI_Boot_ROM = 0xaa5d;
-define exported symbol SSI_StructInit = 0xabbd;
-define exported symbol SSI_Cmd = 0xabf5;
-define exported symbol SSI_INTConfig = 0xac09;
-define exported symbol SSI_SetSclkPolarity = 0xac19;
-define exported symbol SSI_SetSclkPhase = 0xac3d;
-define exported symbol SSI_SetDataFrameSize = 0xac61;
-define exported symbol SSI_SetReadLen = 0xac81;
-define exported symbol SSI_SetBaudDiv = 0xacb1;
-define exported symbol SSI_SetBaud = 0xaccd;
-define exported symbol SSI_SetDmaEnable = 0xad2d;
-define exported symbol SSI_SetDmaLevel = 0xad41;
-define exported symbol SSI_SetIsrClean = 0xad49;
-define exported symbol SSI_WriteData = 0xad65;
-define exported symbol SSI_SetRxFifoLevel = 0xad6d;
-define exported symbol SSI_SetTxFifoLevel = 0xad71;
-define exported symbol SSI_ReadData = 0xad75;
-define exported symbol SSI_GetRxCount = 0xad79;
-define exported symbol SSI_GetTxCount = 0xad81;
-define exported symbol SSI_GetStatus = 0xad89;
-define exported symbol SSI_Writeable = 0xad8d;
-define exported symbol SSI_Readable = 0xad9d;
-define exported symbol SSI_GetDataFrameSize = 0xadad;
-define exported symbol SSI_TXGDMA_Init = 0xadb9;
-define exported symbol SSI_RXGDMA_Init = 0xaef9;
-define exported symbol SSI_ReceiveData = 0xb021;
-define exported symbol SSI_SendData = 0xb0b9;
-define exported symbol SSI_Busy = 0xb165;
-define exported symbol SSI_SetSlaveEnable = 0xb175;
-define exported symbol SSI_Init = 0xb1ad;
-define exported symbol SSI_GetIsr = 0xb235;
-define exported symbol SSI_GetRawIsr = 0xb239;
-define exported symbol SSI_GetSlaveEnable = 0xb23d;
-define exported symbol SSI_PinmuxInit = 0xb241;
-define exported symbol SSI_PinmuxDeInit = 0xb2a9;
-define exported symbol SYSCFG0_Get = 0xb311;
-define exported symbol SYSCFG0_CUTVersion = 0xb31d;
-define exported symbol SYSCFG0_BDOption = 0xb32d;
-define exported symbol SYSCFG1_Get = 0xb33d;
-define exported symbol SYSCFG1_AutoLoadDone = 0xb349;
-define exported symbol SYSCFG1_TRP_LDOMode = 0xb359;
-define exported symbol SYSCFG1_TRP_UARTImage = 0xb369;
-define exported symbol SYSCFG1_TRP_ICFG = 0xb37d;
-define exported symbol SYSCFG2_Get = 0xb389;
-define exported symbol SYSCFG2_ROMINFO_Get = 0xb395;
-define exported symbol SYSCFG2_ROMINFO_Set = 0xb3a1;
-define exported symbol RTIM_TimeBaseStructInit = 0xb3b5;
-define exported symbol RTIM_Cmd = 0xb3cd;
-define exported symbol RTIM_GetCount = 0xb42d;
-define exported symbol RTIM_UpdateDisableConfig = 0xb475;
-define exported symbol RTIM_ARRPreloadConfig = 0xb4c5;
-define exported symbol RTIM_UpdateRequestConfig = 0xb515;
-define exported symbol RTIM_PrescalerConfig = 0xb575;
-define exported symbol RTIM_GenerateEvent = 0xb5a1;
-define exported symbol RTIM_ChangePeriod = 0xb5f9;
-define exported symbol RTIM_Reset = 0xb64d;
-define exported symbol RTIM_CCStructInit = 0xb68d;
-define exported symbol RTIM_CCxInit = 0xb6a1;
-define exported symbol RTIM_CCRxMode = 0xb749;
-define exported symbol RTIM_CCRxSet = 0xb785;
-define exported symbol RTIM_CCRxGet = 0xb7dd;
-define exported symbol RTIM_OCxPreloadConfig = 0xb80d;
-define exported symbol RTIM_CCxPolarityConfig = 0xb85d;
-define exported symbol RTIM_CCxCmd = 0xb8ad;
-define exported symbol RTIM_SetOnePulseOutputMode = 0xb901;
-define exported symbol RTIM_DMACmd = 0xb959;
-define exported symbol RTIM_TXGDMA_Init = 0xb9a9;
-define exported symbol RTIM_RXGDMA_Init = 0xba5d;
-define exported symbol RTIM_INTConfig = 0xbb3d;
-define exported symbol RTIM_INTClear = 0xbba9;
-define exported symbol RTIM_TimeBaseInit = 0xbbed;
-define exported symbol RTIM_DeInit = 0xbced;
-define exported symbol RTIM_INTClearPendingBit = 0xbd41;
-define exported symbol RTIM_GetFlagStatus = 0xbd81;
-define exported symbol RTIM_GetINTStatus = 0xbded;
-define exported symbol UART_DeInit = 0xbe61;
-define exported symbol UART_StructInit = 0xbe69;
-define exported symbol UART_BaudParaGet = 0xbe81;
-define exported symbol UART_BaudParaGetFull = 0xbec9;
-define exported symbol UART_SetBaud = 0xbf01;
-define exported symbol UART_SetBaudExt = 0xbf71;
-define exported symbol UART_SetRxLevel = 0xbfc1;
-define exported symbol UART_RxCmd = 0xbfe9;
-define exported symbol UART_Writable = 0xbffd;
-define exported symbol UART_Readable = 0xc005;
-define exported symbol UART_CharPut = 0xc00d;
-define exported symbol UART_CharGet = 0xc011;
-define exported symbol UART_ReceiveData = 0xc019;
-define exported symbol UART_SendData = 0xc041;
-define exported symbol UART_ReceiveDataTO = 0xc069;
-define exported symbol UART_SendDataTO = 0xc0a9;
-define exported symbol UART_RxByteCntClear = 0xc0e9;
-define exported symbol UART_RxByteCntGet = 0xc0f5;
-define exported symbol UART_BreakCtl = 0xc0fd;
-define exported symbol UART_ClearRxFifo = 0xc111;
-define exported symbol UART_Init = 0xc135;
-define exported symbol UART_ClearTxFifo = 0xc1d1;
-define exported symbol UART_INTConfig = 0xc1dd;
-define exported symbol UART_IntStatus = 0xc1ed;
-define exported symbol UART_ModemStatusGet = 0xc1f1;
-define exported symbol UART_LineStatusGet = 0xc1f5;
-define exported symbol UART_WaitBusy = 0xc1f9;
-define exported symbol UART_PinMuxInit = 0xc221;
-define exported symbol UART_PinMuxDeinit = 0xc289;
-define exported symbol UART_TXDMAConfig = 0xc2f1;
-define exported symbol UART_RXDMAConfig = 0xc301;
-define exported symbol UART_TXDMACmd = 0xc315;
-define exported symbol UART_RXDMACmd = 0xc329;
-define exported symbol UART_TXGDMA_Init = 0xc33d;
-define exported symbol UART_RXGDMA_Init = 0xc425;
-define exported symbol UART_LPRxStructInit = 0xc501;
-define exported symbol UART_LPRxInit = 0xc50d;
-define exported symbol UART_LPRxBaudSet = 0xc575;
-define exported symbol UART_LPRxMonitorCmd = 0xc5f1;
-define exported symbol UART_LPRxpathSet = 0xc62d;
-define exported symbol UART_LPRxIPClockSet = 0xc641;
-define exported symbol UART_LPRxCmd = 0xc6b1;
-define exported symbol UART_LPRxMonBaudCtrlRegGet = 0xc6c5;
-define exported symbol UART_LPRxMonitorSatusGet = 0xc6c9;
-define exported symbol UART_IrDAStructInit = 0xc6cd;
-define exported symbol UART_IrDAInit = 0xc6e5;
-define exported symbol UART_IrDACmd = 0xc7bd;
-define exported symbol INT_SysOn = 0xc7d1;
-define exported symbol INT_Wdg = 0xc811;
-define exported symbol INT_Timer0 = 0xc855;
-define exported symbol INT_Timer1 = 0xc899;
-define exported symbol INT_Timer2 = 0xc8dd;
-define exported symbol INT_Timer3 = 0xc921;
-define exported symbol INT_SPI0 = 0xc965;
-define exported symbol INT_GPIO = 0xc9a9;
-define exported symbol INT_Uart0 = 0xc9ed;
-define exported symbol INT_SPIFlash = 0xca31;
-define exported symbol INT_Uart1 = 0xca75;
-define exported symbol INT_Timer4 = 0xcab9;
-define exported symbol INT_I2S0 = 0xcafd;
-define exported symbol INT_Timer5 = 0xcb41;
-define exported symbol INT_WlDma = 0xcb85;
-define exported symbol INT_WlProtocol = 0xcbc9;
-define exported symbol INT_IPSEC = 0xcc0d;
-define exported symbol INT_SPI1 = 0xcc51;
-define exported symbol INT_Peripheral = 0xcc95;
-define exported symbol INT_Gdma0Ch0 = 0xccd9;
-define exported symbol INT_Gdma0Ch1 = 0xcd1d;
-define exported symbol INT_Gdma0Ch2 = 0xcd61;
-define exported symbol INT_Gdma0Ch3 = 0xcda5;
-define exported symbol INT_Gdma0Ch4 = 0xcde9;
-define exported symbol INT_Gdma0Ch5 = 0xce2d;
-define exported symbol INT_I2C0 = 0xce71;
-define exported symbol INT_I2C1 = 0xceb5;
-define exported symbol INT_Uartlog = 0xcef9;
-define exported symbol INT_ADC = 0xcf3d;
-define exported symbol INT_RDP = 0xcf81;
-define exported symbol INT_RTC = 0xcfc5;
-define exported symbol INT_Gdma1Ch0 = 0xd009;
-define exported symbol INT_Gdma1Ch1 = 0xd051;
-define exported symbol INT_Gdma1Ch2 = 0xd099;
-define exported symbol INT_Gdma1Ch3 = 0xd0e1;
-define exported symbol INT_Gdma1Ch4 = 0xd129;
-define exported symbol INT_Gdma1Ch5 = 0xd171;
-define exported symbol INT_USB = 0xd1b9;
-define exported symbol INT_RXI300 = 0xd201;
-define exported symbol INT_USB_SIE = 0xd249;
-define exported symbol INT_SdioD = 0xd291;
-define exported symbol INT_NMI = 0xd2d1;
-define exported symbol INT_HardFault = 0xd305;
-define exported symbol INT_MemManage = 0xd4b5;
-define exported symbol INT_BusFault = 0xd4d5;
-define exported symbol INT_UsageFault = 0xd4f5;
-define exported symbol VECTOR_TableInit = 0xd515;
-define exported symbol VECTOR_TableInitForOS = 0xd6c5;
-define exported symbol VECTOR_IrqRegister = 0xd6d5;
-define exported symbol VECTOR_IrqUnRegister = 0xd6f9;
-define exported symbol VECTOR_IrqEn = 0xd715;
-define exported symbol VECTOR_IrqDis = 0xd765;
-define exported symbol WDG_Scalar = 0xd7a1;
-define exported symbol WDG_Init = 0xd7e1;
-define exported symbol WDG_IrqClear = 0xd7fd;
-define exported symbol WDG_IrqInit = 0xd80d;
-define exported symbol WDG_Cmd = 0xd83d;
-define exported symbol WDG_Refresh = 0xd85d;
-define exported symbol _strncpy = 0xd86d;
-define exported symbol _strcpy = 0xd889;
-define exported symbol prvStrCpy = 0xd899;
-define exported symbol _strlen = 0xd8b1;
-define exported symbol _strnlen = 0xd8c9;
-define exported symbol prvStrLen = 0xd8fd;
-define exported symbol _strcmp = 0xd919;
-define exported symbol _strncmp = 0xd939;
-define exported symbol prvStrCmp = 0xd985;
-define exported symbol StrUpr = 0xd9b5;
-define exported symbol prvAtoi = 0xd9d1;
-define exported symbol prvStrtok = 0xda29;
-define exported symbol prvStrStr = 0xda81;
-define exported symbol _strsep = 0xdab9;
-define exported symbol skip_spaces = 0xdaf5;
-define exported symbol skip_atoi = 0xdb11;
-define exported symbol _parse_integer_fixup_radix = 0xdb49;
-define exported symbol _parse_integer = 0xdb9d;
-define exported symbol simple_strtoull = 0xdc01;
-define exported symbol simple_strtoll = 0xdc21;
-define exported symbol simple_strtoul = 0xdc41;
-define exported symbol simple_strtol = 0xdc49;
-define exported symbol _vsscanf = 0xdc61;
-define exported symbol _sscanf = 0xe1c9;
-define exported symbol div_u64 = 0xe1e5;
-define exported symbol div_s64 = 0xe1ed;
-define exported symbol div_u64_rem = 0xe1f5;
-define exported symbol div_s64_rem = 0xe205;
-define exported symbol _strpbrk = 0xe215;
-define exported symbol _strchr = 0xe241;
-define exported symbol COMMPORT_GET_T = 0xe259;
-define exported symbol COMMPORT_CLEAN_RX = 0xe289;
-define exported symbol xModemDebugInit = 0xe2a5;
-define exported symbol xModemDebug = 0xe2dd;
-define exported symbol xModemInquiry = 0xe315;
-define exported symbol xModemGetFirst = 0xe339;
-define exported symbol xModemGetOthers = 0xe45d;
-define exported symbol xModemRxFrame = 0xe691;
-define exported symbol xModemHandshake = 0xe6d5;
-define exported symbol xModemRxBuffer = 0xe945;
-define exported symbol xmodem_log_close = 0xe9f5;
-define exported symbol xmodem_log_open = 0xea01;
-define exported symbol xmodem_uart_init = 0xea39;
-define exported symbol xmodem_uart_deinit = 0xeb25;
-define exported symbol xmodem_uart_port_init = 0xeb35;
-define exported symbol xmodem_uart_port_deinit = 0xeb99;
-define exported symbol xmodem_uart_readable = 0xebdd;
-define exported symbol xmodem_uart_writable = 0xebf5;
-define exported symbol xmodem_uart_getc = 0xec0d;
-define exported symbol xmodem_uart_putc = 0xec35;
-define exported symbol xmodem_uart_putdata = 0xec49;
-define exported symbol aes_set_key = 0xec65;
-define exported symbol aes_encrypt = 0xf021;
-define exported symbol aes_decrypt = 0x10171;
-define exported symbol AES_WRAP = 0x112b1;
-define exported symbol AES_UnWRAP = 0x113fd;
-define exported symbol crc32_get = 0x11549;
-define exported symbol arc4_byte = 0x1157d;
-define exported symbol rt_arc4_init = 0x115a5;
-define exported symbol rt_arc4_crypt = 0x115e9;
-define exported symbol rt_md5_init = 0x11df5;
-define exported symbol rt_md5_append = 0x11e25;
-define exported symbol rt_md5_final = 0x11ec9;
-define exported symbol rt_md5_hmac = 0x11f21;
-define exported symbol RC4 = 0x12061;
-define exported symbol RC4_set_key = 0x1238d;
-define exported symbol ROM_WIFI_ReadPowerValue = 0x1246d;
-define exported symbol ROM_WIFI_EfuseParseTxPowerInfo = 0x1251d;
-define exported symbol ROM_WIFI_8051Reset = 0x125c5;
-define exported symbol ROM_WIFI_FWDownloadEnable = 0x125dd;
-define exported symbol ROM_WIFI_BlockWrite = 0x12619;
-define exported symbol ROM_WIFI_PageWrite = 0x12661;
-define exported symbol ROM_WIFI_FillDummy = 0x12685;
-define exported symbol ROM_WIFI_WriteFW = 0x126b1;
-define exported symbol ROM_WIFI_FWFreeToGo = 0x1275d;
-define exported symbol ROM_WIFI_InitLLTTable = 0x127f9;
-define exported symbol ROM_WIFI_GetChnlGroup = 0x12879;
-define exported symbol ROM_WIFI_BWMapping = 0x129f1;
-define exported symbol ROM_WIFI_SCMapping = 0x12a19;
-define exported symbol ROM_WIFI_FillTxdescSectype = 0x12a99;
-define exported symbol ROM_WIFI_FillFakeTxdesc = 0x12ab9;
-define exported symbol ROM_WIFI_32K_Cmd = 0x12b91;
-define exported symbol ROM_WIFI_DISCONNECT = 0x12bc1;
-define exported symbol ROM_WIFI_SET_TSF = 0x12bfd;
-define exported symbol ROM_WIFI_BCN_FUNC = 0x12ca5;
-define exported symbol ROM_WIFI_BSSID_SET = 0x12ccd;
-define exported symbol ROM_WIFI_MACADDR_SET = 0x12d09;
-define exported symbol ROM_WIFI_EnableInterrupt = 0x12d39;
-define exported symbol ROM_WIFI_DisableInterrupt = 0x12d4d;
-define exported symbol ROM_WIFI_RESUME_TxBeacon = 0x12d61;
-define exported symbol ROM_WIFI_STOP_TXBeacon = 0x12d91;
-define exported symbol ROM_WIFI_BCN_Interval = 0x12dc1;
-define exported symbol ROM_WIFI_BCN_FUNC_Enable = 0x12dcd;
-define exported symbol ROM_WIFI_INIT_BeaconParameters = 0x12de5;
-define exported symbol ROM_WIFI_MEDIA_STATUS1 = 0x12e35;
-define exported symbol ROM_WIFI_MEDIA_STATUS = 0x12e4d;
-define exported symbol ROM_WIFI_SetBrateCfg = 0x12e61;
-define exported symbol ROM_WIFI_BASIC_RATE = 0x12f69;
-define exported symbol ROM_WIFI_CHECK_BSSID = 0x12fc9;
-define exported symbol ROM_WIFI_RESP_SIFS = 0x12fe9;
-define exported symbol ROM_WIFI_CAM_WRITE = 0x13001;
-define exported symbol ROM_WIFI_ACM_CTRL = 0x13021;
-define exported symbol ROM_WIFI_FIFO_CLEARN_UP = 0x13051;
-define exported symbol ROM_WIFI_CHECK_TXBUF = 0x130b9;
-define exported symbol ROM_WIFI_BCN_VALID = 0x130fd;
-define exported symbol ROM_WIFI_PROMISC_Cmd = 0x13119;
-define exported symbol ROM_WIFI_SetOpmodeAP = 0x13189;
-define exported symbol ROM_WIFI_ReadChipVersion = 0x132a9;
-define exported symbol ROM_WIFI_DumpChipInfo = 0x1330d;
-define exported symbol ROM_WIFI_InitLxDma = 0x135b1;
-define exported symbol ROM_WIFI_InitQueueReservedPage = 0x13671;
-define exported symbol ROM_WIFI_InitTxBufferBoundary = 0x136f1;
-define exported symbol ROM_WIFI_InitNormalChipRegPriority = 0x1373d;
-define exported symbol ROM_WIFI_InitPageBoundary = 0x13789;
-define exported symbol ROM_WIFI_InitTransferPageSize = 0x13795;
-define exported symbol ROM_WIFI_InitDriverInfoSize = 0x137a1;
-define exported symbol ROM_WIFI_InitNetworkType = 0x137ad;
-define exported symbol ROM_WIFI_InitRCR = 0x137c5;
-define exported symbol ROM_WIFI_InitAdaptiveCtrl = 0x13805;
-define exported symbol ROM_WIFI_InitSIFS = 0x1383d;
-define exported symbol ROM_WIFI_InitEDCA = 0x13865;
-define exported symbol ROM_WIFI_InitRateFallback = 0x138a1;
-define exported symbol ROM_WIFI_InitRetryFunction = 0x138c9;
-define exported symbol ROM_WIFI_InitOperationMode = 0x138e5;
-define exported symbol ROM_WIFI_InitBurstPktLen = 0x138f9;
-define exported symbol phy_CalculateBitShift = 0x13905;
-define exported symbol PHY_SetBBReg_8711B = 0x1391d;
-define exported symbol PHY_QueryBBReg_8711B = 0x13921;
-define exported symbol ROM_odm_QueryRxPwrPercentage = 0x13925;
-define exported symbol ROM_odm_EVMdbToPercentage = 0x13931;
-define exported symbol ROM_odm_SignalScaleMapping_8711B = 0x13935;
-define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x13a11;
-define exported symbol ROM_odm_SetEDCCAThreshold = 0x13d39;
-define exported symbol ROM_odm_SetTRxMux = 0x13d61;
-define exported symbol ROM_odm_SetCrystalCap = 0x13d89;
-define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x13ded;
-define exported symbol ROM_ODM_CfoTrackingReset = 0x13dfd;
-define exported symbol ROM_odm_CfoTrackingFlow = 0x13e21;
-define exported symbol rtw_get_bit_value_from_ieee_value = 0x14045;
-define exported symbol rtw_is_cckrates_included = 0x14071;
-define exported symbol rtw_is_cckratesonly_included = 0x140a5;
-define exported symbol rtw_check_network_type = 0x140cd;
-define exported symbol rtw_set_fixed_ie = 0x14155;
-define exported symbol rtw_set_ie = 0x14175;
-define exported symbol rtw_get_ie = 0x141a1;
-define exported symbol rtw_set_supported_rate = 0x141b5;
-define exported symbol rtw_get_rateset_len = 0x14229;
-define exported symbol rtw_get_wpa_ie = 0x14245;
-define exported symbol rtw_get_wpa2_ie = 0x142d1;
-define exported symbol rtw_get_wpa_cipher_suite = 0x142e5;
-define exported symbol rtw_get_wpa2_cipher_suite = 0x1434d;
-define exported symbol rtw_parse_wpa_ie = 0x143b5;
-define exported symbol rtw_parse_wpa2_ie = 0x14481;
-define exported symbol rtw_get_sec_ie = 0x14535;
-define exported symbol rtw_get_wps_ie = 0x145e5;
-define exported symbol rtw_get_wps_attr = 0x14659;
-define exported symbol rtw_get_wps_attr_content = 0x146f1;
-define exported symbol rtw_ieee802_11_parse_elems = 0x14739;
-define exported symbol str_2char2num = 0x14909;
-define exported symbol key_2char2num = 0x14925;
-define exported symbol convert_ip_addr = 0x1493d;
-define exported symbol rom_psk_PasswordHash = 0x14a21;
-define exported symbol rom_psk_CalcGTK = 0x14a59;
-define exported symbol rom_psk_CalcPTK = 0x14ae9;
-define exported symbol _htons_rom = 0x14bdd;
-define exported symbol _ntohs_rom = 0x14be5;
-define exported symbol _htonl_rom = 0x14bed;
-define exported symbol _ntohl_rom = 0x14bf1;
-define exported symbol Message_ReplayCounter_OC2LI = 0x14bf5;
-define exported symbol Message_EqualReplayCounter = 0x14c35;
-define exported symbol Message_SmallerEqualReplayCounter = 0x14c6d;
-define exported symbol Message_LargerReplayCounter = 0x14cad;
-define exported symbol Message_setReplayCounter = 0x14ce5;
-define exported symbol INCLargeInteger = 0x14d15;
-define exported symbol INCOctet16_INTEGER = 0x14d25;
-define exported symbol INCOctet32_INTEGER = 0x14d8d;
-define exported symbol SetEAPOL_KEYIV = 0x14df5;
-define exported symbol CheckMIC = 0x14e89;
-define exported symbol CalcMIC = 0x14f29;
-define exported symbol DecWPA2KeyData_rom = 0x14f9d;
-define exported symbol DecGTK = 0x15055;
-define exported symbol GetRandomBuffer = 0x15119;
-define exported symbol GenNonce = 0x15181;
-define exported symbol ClientConstructEAPOL_2Of4Way = 0x151c5;
-define exported symbol ClientConstructEAPOL_4Of4Way = 0x152cd;
-define exported symbol ClientConstructEAPOL_2Of2Way = 0x1537d;
-define exported symbol ClientConstructEAPOL_MICOf2Way = 0x15459;
-define exported symbol psk_strip_rsn_pairwise = 0x1552d;
-define exported symbol psk_strip_wpa_pairwise = 0x155c1;
-define exported symbol wep_80211_encrypt = 0x1587d;
-define exported symbol wep_80211_decrypt = 0x158e1;
-define exported symbol tkip_micappendbyte = 0x15975;
-define exported symbol rtw_secmicsetkey = 0x159b9;
-define exported symbol rtw_secmicappend = 0x159f9;
-define exported symbol rtw_secgetmic = 0x15a15;
-define exported symbol rtw_seccalctkipmic = 0x15a89;
-define exported symbol tkip_phase1 = 0x15b7d;
-define exported symbol tkip_phase2 = 0x15ce5;
-define exported symbol tkip_80211_encrypt = 0x15f01;
-define exported symbol tkip_80211_decrypt = 0x15f91;
-define exported symbol aes1_encrypt = 0x16055;
-define exported symbol aesccmp_construct_mic_iv = 0x1625d;
-define exported symbol aesccmp_construct_mic_header1 = 0x162b1;
-define exported symbol aesccmp_construct_mic_header2 = 0x16321;
-define exported symbol aesccmp_construct_ctr_preload = 0x163a5;
-define exported symbol aes_80211_encrypt = 0x16429;
-define exported symbol aes_80211_decrypt = 0x167f9;
-define exported symbol cckrates_included = 0x16c39;
-define exported symbol cckratesonly_included = 0x16c7d;
-define exported symbol networktype_to_raid_ex_rom = 0x16ca9;
-define exported symbol judge_network_type_rom = 0x16cf5;
-define exported symbol ratetbl_val_2wifirate = 0x16d89;
-define exported symbol is_basicrate_rom = 0x16d9d;
-define exported symbol ratetbl2rateset_rom = 0x16dd5;
-define exported symbol get_rate_set_rom = 0x16e3d;
-define exported symbol UpdateBrateTbl_rom = 0x16e71;
-define exported symbol UpdateBrateTblForSoftAP = 0x16ec9;
-define exported symbol write_cam_rom = 0x16f0d;
-define exported symbol HT_caps_handler_rom = 0x16fc1;
-define exported symbol wifirate2_ratetbl_inx = 0x17015;
-define exported symbol update_basic_rate = 0x170bd;
-define exported symbol update_supported_rate = 0x170f5;
-define exported symbol update_MCS_rate = 0x17125;
-define exported symbol get_highest_rate_idx = 0x17131;
-define exported symbol _sha1_process_message_block = 0x1714d;
-define exported symbol _sha1_pad_message = 0x172d1;
-define exported symbol rt_sha1_init = 0x1736d;
-define exported symbol rt_sha1_update = 0x173b1;
-define exported symbol rt_sha1_finish = 0x17429;
-define exported symbol rt_hmac_sha1 = 0x17489;
-define exported symbol rom_aes_128_cbc_encrypt = 0x175e5;
-define exported symbol rom_aes_128_cbc_decrypt = 0x17669;
-define exported symbol rom_rijndaelKeySetupEnc = 0x176ed;
-define exported symbol rom_aes_decrypt_init = 0x177c1;
-define exported symbol rom_aes_internal_decrypt = 0x17899;
-define exported symbol rom_aes_decrypt_deinit = 0x17bdd;
-define exported symbol rom_aes_encrypt_init = 0x17be9;
-define exported symbol rom_aes_internal_encrypt = 0x17c01;
-define exported symbol rom_aes_encrypt_deinit = 0x17f81;
-define exported symbol bignum_init = 0x1963d;
-define exported symbol bignum_deinit = 0x19665;
-define exported symbol bignum_get_unsigned_bin_len = 0x19685;
-define exported symbol bignum_get_unsigned_bin = 0x19689;
-define exported symbol bignum_set_unsigned_bin = 0x19741;
-define exported symbol bignum_cmp = 0x197f9;
-define exported symbol bignum_cmp_d = 0x197fd;
-define exported symbol bignum_add = 0x19825;
-define exported symbol bignum_sub = 0x19835;
-define exported symbol bignum_mul = 0x19845;
-define exported symbol bignum_exptmod = 0x19855;
-define exported symbol WPS_realloc = 0x19879;
-define exported symbol os_zalloc = 0x198bd;
-define exported symbol rom_hmac_sha256_vector = 0x198e1;
-define exported symbol rom_hmac_sha256 = 0x199e1;
-define exported symbol rom_sha256_vector = 0x19b3d;
-define exported symbol CRYPTO_chacha_20 = 0x19d45;
-define exported symbol rom_ed25519_gen_keypair = 0x1a1bd;
-define exported symbol rom_ed25519_gen_signature = 0x1a1c1;
-define exported symbol rom_ed25519_verify_signature = 0x1a1d9;
-define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x1c4c9;
-define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x1c8c1;
-define exported symbol rom_ed25519_ge_p3_tobytes = 0x1d43d;
-define exported symbol rom_ed25519_ge_scalarmult_base = 0x1d489;
-define exported symbol rom_ed25519_ge_tobytes = 0x1d64d;
-define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x1d699;
-define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x1d6f1;
-define exported symbol rom_ed25519_sc_muladd = 0x1d9e5;
-define exported symbol rom_ed25519_sc_reduce = 0x24175;
-define exported symbol rom_ed25519_crypto_sign_detached = 0x26c25;
-define exported symbol CRYPTO_poly1305_init = 0x270dd;
-define exported symbol CRYPTO_poly1305_update = 0x271b5;
-define exported symbol CRYPTO_poly1305_finish = 0x27245;
-define exported symbol rom_sha512_starts = 0x28511;
-define exported symbol rom_sha512_update = 0x28659;
-define exported symbol rom_sha512_finish = 0x28661;
-define exported symbol rom_sha512 = 0x288a9;
-define exported symbol rom_sha512_hmac_starts = 0x288e1;
-define exported symbol rom_sha512_hmac_update = 0x289a5;
-define exported symbol rom_sha512_hmac_finish = 0x289ad;
-define exported symbol rom_sha512_hmac_reset = 0x289fd;
-define exported symbol rom_sha512_hmac = 0x28a19;
-define exported symbol rom_sha512_hkdf = 0x28a51;
-define exported symbol aes_test_alignment_detection = 0x28b59;
-define exported symbol aes_mode_reset = 0x28bbd;
-define exported symbol aes_ecb_encrypt = 0x28bc9;
-define exported symbol aes_ecb_decrypt = 0x28c05;
-define exported symbol aes_cbc_encrypt = 0x28c41;
-define exported symbol aes_cbc_decrypt = 0x28dad;
-define exported symbol aes_cfb_encrypt = 0x28f49;
-define exported symbol aes_cfb_decrypt = 0x2920d;
-define exported symbol aes_ofb_crypt = 0x294d5;
-define exported symbol aes_ctr_crypt = 0x29769;
-define exported symbol aes_encrypt_key128 = 0x29a79;
-define exported symbol aes_encrypt_key192 = 0x29a95;
-define exported symbol aes_encrypt_key256 = 0x29ab1;
-define exported symbol aes_encrypt_key = 0x29ad1;
-define exported symbol aes_decrypt_key128 = 0x29b41;
-define exported symbol aes_decrypt_key192 = 0x29b5d;
-define exported symbol aes_decrypt_key256 = 0x29b79;
-define exported symbol aes_decrypt_key = 0x29b99;
-define exported symbol aes_init = 0x29c09;
-define exported symbol curve25519_donna = 0x2a939;
-define exported symbol __rtl_dtoa_r_v1_00 = 0x2b7f1;
-define exported symbol __rtl_ltoa_v1_00 = 0x2c7f9;
-define exported symbol __rtl_ultoa_v1_00 = 0x2c885;
-define exported symbol __rtl_dtoi_v1_00 = 0x2c8ed;
-define exported symbol __rtl_dtoi64_v1_00 = 0x2c96d;
-define exported symbol __rtl_dtoui_v1_00 = 0x2ca09;
-define exported symbol __rtl_ftol_v1_00 = 0x2ca11;
-define exported symbol __rtl_itof_v1_00 = 0x2ca75;
-define exported symbol __rtl_itod_v1_00 = 0x2cb05;
-define exported symbol __rtl_i64tod_v1_00 = 0x2cb71;
-define exported symbol __rtl_uitod_v1_00 = 0x2cc4d;
-define exported symbol __rtl_ftod_v1_00 = 0x2cd29;
-define exported symbol __rtl_dtof_v1_00 = 0x2cde1;
-define exported symbol __rtl_uitof_v1_00 = 0x2ce75;
-define exported symbol __rtl_fadd_v1_00 = 0x2cf59;
-define exported symbol __rtl_fsub_v1_00 = 0x2d259;
-define exported symbol __rtl_fmul_v1_00 = 0x2d565;
-define exported symbol __rtl_fdiv_v1_00 = 0x2d695;
-define exported symbol __rtl_dadd_v1_00 = 0x2d809;
-define exported symbol __rtl_dsub_v1_00 = 0x2de49;
-define exported symbol __rtl_dmul_v1_00 = 0x2e4a1;
-define exported symbol __rtl_ddiv_v1_00 = 0x2e7dd;
-define exported symbol __rtl_dcmpeq_v1_00 = 0x2ed71;
-define exported symbol __rtl_dcmplt_v1_00 = 0x2eded;
-define exported symbol __rtl_dcmpgt_v1_00 = 0x2ee85;
-define exported symbol __rtl_dcmple_v1_00 = 0x2ef95;
-define exported symbol __rtl_fcmplt_v1_00 = 0x2f0a9;
-define exported symbol __rtl_fcmpgt_v1_00 = 0x2f105;
-define exported symbol __rtl_fpclassifyd = 0x2f1ad;
-define exported symbol __rtl_close_v1_00 = 0x2f205;
-define exported symbol __rtl_fstat_v1_00 = 0x2f219;
-define exported symbol __rtl_isatty_v1_00 = 0x2f22d;
-define exported symbol __rtl_lseek_v1_00 = 0x2f23d;
-define exported symbol __rtl_open_v1_00 = 0x2f251;
-define exported symbol __rtl_read_v1_00 = 0x2f265;
-define exported symbol __rtl_write_v1_00 = 0x2f279;
-define exported symbol __rtl_sbrk_v1_00 = 0x2f28d;
-define exported symbol __rom_mallocr_init_v1_00 = 0x2f29d;
-define exported symbol __rtl_free_r_v1_00 = 0x2f309;
-define exported symbol __rtl_malloc_r_v1_00 = 0x2f521;
-define exported symbol __rtl_realloc_r_v1_00 = 0x2f9f5;
-define exported symbol __rtl_memalign_r_v1_00 = 0x2fdb5;
-define exported symbol __rtl_valloc_r_v1_00 = 0x2fe81;
-define exported symbol __rtl_pvalloc_r_v1_00 = 0x2fe8d;
-define exported symbol __rtl_calloc_r_v1_00 = 0x2fea1;
-define exported symbol __rtl_cfree_r_v1_00 = 0x2ff05;
-define exported symbol __rtl_cos_f32_v1_00 = 0x2ff15;
-define exported symbol __rtl_sin_f32_v1_00 = 0x300e9;
-define exported symbol __rtl_fabs_v1_00 = 0x302ad;
-define exported symbol __rtl_fabsf_v1_00 = 0x302b5;
-define exported symbol __rtl_memchr_v1_00 = 0x302bd;
-define exported symbol __rtl_memcmp_v1_00 = 0x30351;
-define exported symbol __rtl_memcpy_v1_00 = 0x303b5;
-define exported symbol __rtl_memmove_v1_00 = 0x3045d;
-define exported symbol __rtl_memset_v1_00 = 0x30525;
-define exported symbol __rtl_Balloc_v1_00 = 0x3061d;
-define exported symbol __rtl_Bfree_v1_00 = 0x3066d;
-define exported symbol __rtl_i2b_v1_00 = 0x30681;
-define exported symbol __rtl_multadd_v1_00 = 0x30695;
-define exported symbol __rtl_mult_v1_00 = 0x30721;
-define exported symbol __rtl_pow5mult_v1_00 = 0x30855;
-define exported symbol __rtl_hi0bits_v1_00 = 0x308f5;
-define exported symbol __rtl_d2b_v1_00 = 0x30935;
-define exported symbol __rtl_lshift_v1_00 = 0x309ed;
-define exported symbol __rtl_cmp_v1_00 = 0x30a99;
-define exported symbol __rtl_diff_v1_00 = 0x30ae1;
-define exported symbol __rtl_sread_v1_00 = 0x30bb5;
-define exported symbol __rtl_seofread_v1_00 = 0x30c01;
-define exported symbol __rtl_swrite_v1_00 = 0x30c05;
-define exported symbol __rtl_sseek_v1_00 = 0x30c75;
-define exported symbol __rtl_sclose_v1_00 = 0x30cc1;
-define exported symbol __rtl_sbrk_r_v1_00 = 0x30ced;
-define exported symbol __rtl_strcat_v1_00 = 0x30d15;
-define exported symbol __rtl_strchr_v1_00 = 0x30d59;
-define exported symbol __rtl_strcmp_v1_00 = 0x30e25;
-define exported symbol __rtl_strcpy_v1_00 = 0x30e99;
-define exported symbol __rtl_strlen_v1_00 = 0x30ee5;
-define exported symbol __rtl_strncat_v1_00 = 0x30f39;
-define exported symbol __rtl_strncmp_v1_00 = 0x30f95;
-define exported symbol __rtl_strncpy_v1_00 = 0x3102d;
-define exported symbol __rtl_strsep_v1_00 = 0x31095;
-define exported symbol __rtl_strstr_v1_00 = 0x3136d;
-define exported symbol __rtl_strtok_v1_00 = 0x315a5;
-define exported symbol __rtl__strtok_r_v1_00 = 0x315b5;
-define exported symbol __rtl_strtok_r_v1_00 = 0x31619;
-define exported symbol __rtl_fflush_r_v1_00 = 0x31ae9;
-define exported symbol __rtl_vfprintf_r_v1_00 = 0x31f99;
-define exported symbol polarssl_aes_init = 0x335b9;
-define exported symbol aes_free = 0x335c9;
-define exported symbol aes_setkey_enc = 0x335dd;
-define exported symbol aes_setkey_dec = 0x33829;
-define exported symbol aes_crypt_ecb = 0x339a1;
-define exported symbol aes_crypt_cbc = 0x343d1;
-define exported symbol aes_crypt_cfb128 = 0x34649;
-define exported symbol aes_crypt_cfb8 = 0x346c9;
-define exported symbol aes_crypt_ctr = 0x3474d;
-define exported symbol arc4_init = 0x347b1;
-define exported symbol arc4_free = 0x347bd;
-define exported symbol arc4_setup = 0x347d1;
-define exported symbol arc4_crypt = 0x3481d;
-define exported symbol asn1_get_len = 0x34861;
-define exported symbol asn1_get_tag = 0x34901;
-define exported symbol asn1_get_bool = 0x34929;
-define exported symbol asn1_get_int = 0x3495d;
-define exported symbol asn1_get_mpi = 0x349a9;
-define exported symbol asn1_get_bitstring = 0x349d1;
-define exported symbol asn1_get_bitstring_null = 0x34a19;
-define exported symbol asn1_get_sequence_of = 0x34a4d;
-define exported symbol asn1_get_alg = 0x34ad1;
-define exported symbol asn1_get_alg_null = 0x34b65;
-define exported symbol asn1_free_named_data = 0x34ba5;
-define exported symbol asn1_free_named_data_list = 0x34bcd;
-define exported symbol asn1_find_named_data = 0x34bf5;
-define exported symbol asn1_write_len = 0x34c25;
-define exported symbol asn1_write_tag = 0x34c8d;
-define exported symbol asn1_write_raw_buffer = 0x34ca9;
-define exported symbol asn1_write_mpi = 0x34ccd;
-define exported symbol asn1_write_null = 0x34d41;
-define exported symbol asn1_write_oid = 0x34d6d;
-define exported symbol asn1_write_algorithm_identifier = 0x34dc5;
-define exported symbol asn1_write_bool = 0x34e21;
-define exported symbol asn1_write_int = 0x34e65;
-define exported symbol asn1_write_printable_string = 0x34ecd;
-define exported symbol asn1_write_ia5_string = 0x34f25;
-define exported symbol asn1_write_bitstring = 0x34f7d;
-define exported symbol asn1_write_octet_string = 0x34fe5;
-define exported symbol asn1_store_named_data = 0x3503d;
-define exported symbol base64_encode = 0x35111;
-define exported symbol base64_decode = 0x3523d;
-define exported symbol mpi_init = 0x35e09;
-define exported symbol mpi_free = 0x35e19;
-define exported symbol mpi_grow = 0x35e55;
-define exported symbol mpi_shrink = 0x35e79;
-define exported symbol mpi_copy = 0x35f21;
-define exported symbol mpi_swap = 0x35fa1;
-define exported symbol mpi_safe_cond_assign = 0x35fcd;
-define exported symbol mpi_safe_cond_swap = 0x36069;
-define exported symbol mpi_lset = 0x3610d;
-define exported symbol mpi_get_bit = 0x3614d;
-define exported symbol mpi_set_bit = 0x3616d;
-define exported symbol mpi_lsb = 0x361d5;
-define exported symbol mpi_msb = 0x36215;
-define exported symbol mpi_size = 0x36261;
-define exported symbol mpi_read_binary = 0x3626d;
-define exported symbol mpi_write_binary = 0x362f9;
-define exported symbol mpi_shift_l = 0x36341;
-define exported symbol mpi_shift_r = 0x363f1;
-define exported symbol mpi_cmp_abs = 0x36475;
-define exported symbol mpi_cmp_mpi = 0x36619;
-define exported symbol mpi_cmp_int = 0x366f1;
-define exported symbol mpi_add_abs = 0x3671d;
-define exported symbol mpi_sub_abs = 0x3680d;
-define exported symbol mpi_add_mpi = 0x3689d;
-define exported symbol mpi_sub_mpi = 0x368ed;
-define exported symbol mpi_add_int = 0x3693d;
-define exported symbol mpi_sub_int = 0x36969;
-define exported symbol mpi_mul_mpi = 0x36995;
-define exported symbol mpi_read_string = 0x36ac5;
-define exported symbol mpi_mul_int = 0x36c45;
-define exported symbol mpi_div_mpi = 0x36c61;
-define exported symbol mpi_div_int = 0x370ed;
-define exported symbol mpi_mod_mpi = 0x37119;
-define exported symbol mpi_mod_int = 0x3717d;
-define exported symbol mpi_write_string = 0x3722d;
-define exported symbol mpi_exp_mod = 0x37395;
-define exported symbol mpi_gcd = 0x37915;
-define exported symbol mpi_fill_random = 0x37a39;
-define exported symbol mpi_inv_mod = 0x37c4d;
-define exported symbol mpi_is_prime = 0x37f15;
-define exported symbol mpi_gen_prime = 0x37f71;
-define exported symbol ctr_drbg_free = 0x38285;
-define exported symbol ctr_drbg_set_prediction_resistance = 0x382a1;
-define exported symbol ctr_drbg_set_entropy_len = 0x382a5;
-define exported symbol ctr_drbg_set_reseed_interval = 0x382a9;
-define exported symbol ctr_drbg_update = 0x382ad;
-define exported symbol ctr_drbg_reseed = 0x382c9;
-define exported symbol ctr_drbg_init_entropy_len = 0x38341;
-define exported symbol ctr_drbg_init = 0x38399;
-define exported symbol ctr_drbg_random_with_add = 0x383ad;
-define exported symbol ctr_drbg_random = 0x38469;
-define exported symbol des_init = 0x388a5;
-define exported symbol des_free = 0x388b1;
-define exported symbol des3_init = 0x388c5;
-define exported symbol des3_free = 0x388d5;
-define exported symbol des_key_set_parity = 0x388e9;
-define exported symbol des_key_check_key_parity = 0x38909;
-define exported symbol des_key_check_weak = 0x38939;
-define exported symbol des_setkey_enc = 0x38965;
-define exported symbol des_setkey_dec = 0x3898d;
-define exported symbol des3_set2key_enc = 0x389d9;
-define exported symbol des3_set2key_dec = 0x38a25;
-define exported symbol des3_set3key_enc = 0x38a71;
-define exported symbol des3_set3key_dec = 0x38ab1;
-define exported symbol des_crypt_ecb = 0x38af1;
-define exported symbol des_crypt_cbc = 0x38d09;
-define exported symbol des3_crypt_ecb = 0x38f99;
-define exported symbol des3_crypt_cbc = 0x39401;
-define exported symbol dhm_init = 0x39729;
-define exported symbol dhm_read_params = 0x39731;
-define exported symbol dhm_make_params = 0x3978d;
-define exported symbol dhm_read_public = 0x398c1;
-define exported symbol dhm_make_public = 0x398e9;
-define exported symbol dhm_calc_secret = 0x399ad;
-define exported symbol dhm_free = 0x39ba1;
-define exported symbol dhm_parse_dhm = 0x39c01;
-define exported symbol ecdh_gen_public = 0x39cc5;
-define exported symbol ecdh_compute_shared = 0x39cc9;
-define exported symbol ecdh_init = 0x39d2d;
-define exported symbol ecdh_free = 0x39d39;
-define exported symbol ecdh_make_params = 0x39d81;
-define exported symbol ecdh_read_params = 0x39e05;
-define exported symbol ecdh_get_params = 0x39e2d;
-define exported symbol ecdh_make_public = 0x39e79;
-define exported symbol ecdh_read_public = 0x39ed1;
-define exported symbol ecdh_calc_secret = 0x39f01;
-define exported symbol ecdsa_sign = 0x3a041;
-define exported symbol ecdsa_sign_det = 0x3a1c5;
-define exported symbol ecdsa_verify = 0x3a2a9;
-define exported symbol ecdsa_write_signature = 0x3a431;
-define exported symbol ecdsa_write_signature_det = 0x3a46d;
-define exported symbol ecdsa_read_signature = 0x3a4a5;
-define exported symbol ecdsa_genkey = 0x3a531;
-define exported symbol ecdsa_init = 0x3a565;
-define exported symbol ecdsa_free = 0x3a591;
-define exported symbol ecdsa_from_keypair = 0x3a5bd;
-define exported symbol ecp_curve_list = 0x3aee5;
-define exported symbol ecp_curve_info_from_grp_id = 0x3aeed;
-define exported symbol ecp_curve_info_from_tls_id = 0x3af0d;
-define exported symbol ecp_curve_info_from_name = 0x3af31;
-define exported symbol ecp_point_init = 0x3af61;
-define exported symbol ecp_group_init = 0x3af81;
-define exported symbol ecp_keypair_init = 0x3af8d;
-define exported symbol ecp_point_free = 0x3afb1;
-define exported symbol ecp_group_free = 0x3afd1;
-define exported symbol ecp_keypair_free = 0x3b03d;
-define exported symbol ecp_copy = 0x3b05d;
-define exported symbol ecp_group_copy = 0x3b08d;
-define exported symbol ecp_set_zero = 0x3b095;
-define exported symbol ecp_is_zero = 0x3ba61;
-define exported symbol ecp_point_read_string = 0x3ba75;
-define exported symbol ecp_point_write_binary = 0x3baa5;
-define exported symbol ecp_point_read_binary = 0x3bb4d;
-define exported symbol ecp_tls_read_point = 0x3bbc1;
-define exported symbol ecp_tls_write_point = 0x3bbf5;
-define exported symbol ecp_group_read_string = 0x3bc25;
-define exported symbol ecp_tls_read_group = 0x3bc95;
-define exported symbol ecp_tls_write_group = 0x3bcf1;
-define exported symbol ecp_add = 0x3bd39;
-define exported symbol ecp_sub = 0x3bd65;
-define exported symbol ecp_check_pubkey = 0x3bddd;
-define exported symbol ecp_check_privkey = 0x3bf8d;
-define exported symbol ecp_mul = 0x3bff5;
-define exported symbol ecp_gen_keypair = 0x3c565;
-define exported symbol ecp_gen_key = 0x3c669;
-define exported symbol ecp_use_known_dp = 0x3d741;
-define exported symbol hmac_drbg_update = 0x3daa9;
-define exported symbol hmac_drbg_init_buf = 0x3db41;
-define exported symbol hmac_drbg_reseed = 0x3db91;
-define exported symbol hmac_drbg_init = 0x3dc09;
-define exported symbol hmac_drbg_set_prediction_resistance = 0x3dc81;
-define exported symbol hmac_drbg_set_entropy_len = 0x3dc85;
-define exported symbol hmac_drbg_set_reseed_interval = 0x3dc89;
-define exported symbol hmac_drbg_random_with_add = 0x3dc8d;
-define exported symbol hmac_drbg_random = 0x3dd4d;
-define exported symbol hmac_drbg_free = 0x3dd61;
-define exported symbol md_list = 0x3dd7d;
-define exported symbol md_info_from_string = 0x3dd85;
-define exported symbol md_info_from_type = 0x3de59;
-define exported symbol md_init = 0x3de9d;
-define exported symbol md_free = 0x3dea5;
-define exported symbol md_init_ctx = 0x3dec5;
-define exported symbol md_free_ctx = 0x3defd;
-define exported symbol md_starts = 0x3df09;
-define exported symbol md_update = 0x3df29;
-define exported symbol md_finish = 0x3df49;
-define exported symbol md = 0x3df69;
-define exported symbol md_file = 0x3df89;
-define exported symbol md_hmac_starts = 0x3dfa1;
-define exported symbol md_hmac_update = 0x3dfc1;
-define exported symbol md_hmac_finish = 0x3dfe1;
-define exported symbol md_hmac_reset = 0x3e001;
-define exported symbol md_hmac = 0x3e021;
-define exported symbol md_process = 0x3e049;
-define exported symbol md5_init = 0x3e301;
-define exported symbol md5_free = 0x3e309;
-define exported symbol md5_starts = 0x3e31d;
-define exported symbol md5_process = 0x3e34d;
-define exported symbol md5_update = 0x3ed51;
-define exported symbol md5_finish = 0x3ed59;
-define exported symbol md5 = 0x3ee11;
-define exported symbol md5_hmac_starts = 0x3ee75;
-define exported symbol md5_hmac_update = 0x3ef51;
-define exported symbol md5_hmac_finish = 0x3ef59;
-define exported symbol md5_hmac_reset = 0x3efbd;
-define exported symbol md5_hmac = 0x3eff1;
-define exported symbol oid_get_attr_short_name = 0x3f071;
-define exported symbol oid_get_x509_ext_type = 0x3f0b1;
-define exported symbol oid_get_extended_key_usage = 0x3f0f1;
-define exported symbol oid_get_sig_alg_desc = 0x3f131;
-define exported symbol oid_get_sig_alg = 0x3f149;
-define exported symbol oid_get_oid_by_sig_alg = 0x3f169;
-define exported symbol oid_get_pk_alg = 0x3f1a1;
-define exported symbol oid_get_oid_by_pk_alg = 0x3f1e1;
-define exported symbol oid_get_ec_grp = 0x3f219;
-define exported symbol oid_get_oid_by_ec_grp = 0x3f259;
-define exported symbol oid_get_cipher_alg = 0x3f291;
-define exported symbol oid_get_md_alg = 0x3f2d1;
-define exported symbol oid_get_oid_by_md = 0x3f311;
-define exported symbol oid_get_pkcs12_pbe_alg = 0x3f349;
-define exported symbol oid_get_numeric_string = 0x3f391;
-define exported symbol pem_init = 0x3f649;
-define exported symbol pem_read_buffer = 0x3f651;
-define exported symbol pem_free = 0x3f955;
-define exported symbol pem_write_buffer = 0x3f97d;
-define exported symbol pk_init = 0x3fa81;
-define exported symbol pk_free = 0x3fa8d;
-define exported symbol pk_info_from_type = 0x3faad;
-define exported symbol pk_init_ctx = 0x3fae1;
-define exported symbol pk_init_ctx_rsa_alt = 0x3fb11;
-define exported symbol pk_can_do = 0x3fb69;
-define exported symbol pk_verify = 0x3fb79;
-define exported symbol pk_verify_ext = 0x3fbc9;
-define exported symbol pk_sign = 0x3fc8d;
-define exported symbol pk_decrypt = 0x3fce9;
-define exported symbol pk_encrypt = 0x3fd15;
-define exported symbol pk_get_size = 0x3fd41;
-define exported symbol pk_debug = 0x3fd51;
-define exported symbol pk_get_name = 0x3fd79;
-define exported symbol pk_get_type = 0x3fd8d;
-define exported symbol pk_write_pubkey = 0x40181;
-define exported symbol pk_write_pubkey_der = 0x40201;
-define exported symbol pk_write_key_der = 0x402dd;
-define exported symbol pk_write_pubkey_pem = 0x404f5;
-define exported symbol pk_write_key_pem = 0x40545;
-define exported symbol rsa_init = 0x4065d;
-define exported symbol rsa_set_padding = 0x40679;
-define exported symbol rsa_check_pubkey = 0x40685;
-define exported symbol rsa_check_privkey = 0x406e1;
-define exported symbol rsa_public = 0x409a5;
-define exported symbol rsa_private = 0x40a25;
-define exported symbol rsa_rsaes_oaep_encrypt = 0x40c29;
-define exported symbol rsa_rsaes_pkcs1_v15_encrypt = 0x40d31;
-define exported symbol rsa_pkcs1_encrypt = 0x40e19;
-define exported symbol rsa_rsaes_oaep_decrypt = 0x40e59;
-define exported symbol rsa_rsaes_pkcs1_v15_decrypt = 0x40fbd;
-define exported symbol rsa_pkcs1_decrypt = 0x410c1;
-define exported symbol rsa_rsassa_pss_sign = 0x4110d;
-define exported symbol rsa_rsassa_pkcs1_v15_sign = 0x41271;
-define exported symbol rsa_pkcs1_sign = 0x41389;
-define exported symbol rsa_rsassa_pss_verify_ext = 0x413c9;
-define exported symbol rsa_rsassa_pss_verify = 0x41575;
-define exported symbol rsa_rsassa_pkcs1_v15_verify = 0x415a5;
-define exported symbol rsa_pkcs1_verify = 0x41709;
-define exported symbol rsa_free = 0x41765;
-define exported symbol rsa_gen_key = 0x417d5;
-define exported symbol rsa_copy = 0x4198d;
-define exported symbol sha1_init = 0x41a9d;
-define exported symbol sha1_free = 0x41aa5;
-define exported symbol sha1_starts = 0x41ab9;
-define exported symbol sha1_process = 0x41aed;
-define exported symbol sha1_update = 0x42e15;
-define exported symbol sha1_finish = 0x42e1d;
-define exported symbol sha1 = 0x42ee5;
-define exported symbol sha1_hmac_starts = 0x42f51;
-define exported symbol sha1_hmac_update = 0x43039;
-define exported symbol sha1_hmac_finish = 0x43041;
-define exported symbol sha1_hmac_reset = 0x430b5;
-define exported symbol sha1_hmac = 0x430f1;
-define exported symbol sha256_init = 0x43139;
-define exported symbol sha256_free = 0x43141;
-define exported symbol sha256_starts = 0x43155;
-define exported symbol sha256_process = 0x431e5;
-define exported symbol sha256_update = 0x4513d;
-define exported symbol sha256_finish = 0x45145;
-define exported symbol sha256 = 0x4524d;
-define exported symbol sha256_hmac_starts = 0x45325;
-define exported symbol sha256_hmac_update = 0x45475;
-define exported symbol sha256_hmac_finish = 0x4547d;
-define exported symbol sha256_hmac_reset = 0x45569;
-define exported symbol sha256_hmac = 0x45601;
-define exported symbol sha512_init = 0x45651;
-define exported symbol sha512_free = 0x4565d;
-define exported symbol sha512_starts = 0x45671;
-define exported symbol sha512_process = 0x457b9;
-define exported symbol sha512_update = 0x46879;
-define exported symbol sha512_finish = 0x46881;
-define exported symbol sha512 = 0x46ac9;
-define exported symbol sha512_hmac_starts = 0x46b11;
-define exported symbol sha512_hmac_update = 0x46bd9;
-define exported symbol sha512_hmac_finish = 0x46be1;
-define exported symbol sha512_hmac_reset = 0x46c35;
-define exported symbol sha512_hmac = 0x46c51;
-define exported symbol UartLogRomCmdTable = 0x46ca0;
-define exported symbol XTAL_CLK = 0x46e10;
-define exported symbol CpkClkTbl_FPAG = 0x46e50;
-define exported symbol CpkClkTbl_ASIC = 0x46e68;
-define exported symbol ROM_IMG1_VALID_PATTEN = 0x46e90;
-define exported symbol __AES_rcon = 0x46e98;
-define exported symbol __AES_Te4 = 0x46ec0;
-define exported symbol SpicCalibrationPattern = 0x472c0;
-define exported symbol NEW_CALIBREATION_DIV = 0x472c8;
-define exported symbol NEW_CALIBREATION_DATA = 0x472e4;
-define exported symbol GDMA_IrqNum = 0x47344;
-define exported symbol I2C_DEV_TABLE = 0x47350;
-define exported symbol spi_clk_pin = 0x47370;
-define exported symbol SPI_DEV_TABLE = 0x47374;
-define exported symbol PWM_GDMA_HSx = 0x47394;
-define exported symbol TIM_DMA_CCx = 0x473ac;
-define exported symbol TIM_IT_CCx = 0x473c4;
-define exported symbol TIMx = 0x473dc;
-define exported symbol TIMx_irq = 0x473f4;
-define exported symbol BAUDRATE_TABLE_40M = 0x4740c;
-define exported symbol UART_DEV_TABLE = 0x475bc;
-define exported symbol RTW_WPA_OUI_TYPE = 0x4b270;
-define exported symbol WPA_CIPHER_SUITE_NONE = 0x4b274;
-define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x4b278;
-define exported symbol WPA_CIPHER_SUITE_TKIP = 0x4b27c;
-define exported symbol WPA_CIPHER_SUITE_CCMP = 0x4b280;
-define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x4b284;
-define exported symbol RSN_CIPHER_SUITE_NONE = 0x4b288;
-define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x4b28c;
-define exported symbol RSN_CIPHER_SUITE_TKIP = 0x4b290;
-define exported symbol RSN_CIPHER_SUITE_CCMP = 0x4b294;
-define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x4b298;
-define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x4b2a8;
-define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x4b2ac;
-define exported symbol RSN_VERSION_BSD = 0x4b2b0;
-define exported symbol rom_e_rtw_msgp_str_ = 0x4b2b4;
-define exported symbol rtw_basic_rate_mix = 0x4b9a8;
-define exported symbol rtw_basic_rate_ofdm = 0x4b9b0;
-define exported symbol rtw_basic_rate_cck = 0x4b9b4;
-define exported symbol REALTEK_96B_IE = 0x4b9b8;
-define exported symbol AIRGOCAP_OUI = 0x4b9c0;
-define exported symbol REALTEK_OUI = 0x4b9c4;
-define exported symbol RALINK_OUI = 0x4b9c8;
-define exported symbol MARVELL_OUI = 0x4b9cc;
-define exported symbol CISCO_OUI = 0x4b9d0;
-define exported symbol BROADCOM_OUI3 = 0x4b9d4;
-define exported symbol BROADCOM_OUI2 = 0x4b9d8;
-define exported symbol BROADCOM_OUI1 = 0x4b9dc;
-define exported symbol ARTHEROS_OUI2 = 0x4b9e0;
-define exported symbol ARTHEROS_OUI1 = 0x4b9e4;
-define exported symbol rom_wps_rcons = 0x4b9e8;
-define exported symbol rom_wps_Te0 = 0x4b9f4;
-define exported symbol rom_wps_Td4s = 0x4bdf4;
-define exported symbol rom_wps_Td0 = 0x4bef4;
-define exported symbol sha512_info = 0x5850c;
-define exported symbol sha384_info = 0x5854c;
-define exported symbol sha256_info = 0x5858c;
-define exported symbol sha224_info = 0x585cc;
-define exported symbol sha1_info = 0x5860c;
-define exported symbol md5_info = 0x5864c;
-define exported symbol rsa_alt_info = 0x58d28;
-define exported symbol ecdsa_info = 0x58d54;
-define exported symbol eckeydh_info = 0x58d80;
-define exported symbol eckey_info = 0x58dac;
-define exported symbol rsa_info = 0x58dd8;
-define exported symbol __rom_bss_start__ = 0x10000000;
-define exported symbol NewVectorTable = 0x10000000;
-define exported symbol UserIrqFunTable = 0x10000100;
-define exported symbol UserIrqDataTable = 0x10000200;
-define exported symbol ConfigDebugClose = 0x10000300;
-define exported symbol CfgSysDebugWarn = 0x10000304;
-define exported symbol CfgSysDebugInfo = 0x10000308;
-define exported symbol CfgSysDebugErr = 0x1000030c;
-define exported symbol ConfigDebugWarn = 0x10000310;
-define exported symbol ConfigDebugInfo = 0x10000314;
-define exported symbol ConfigDebugErr = 0x10000318;
-define exported symbol sector_addr = 0x1000031c;
-define exported symbol _rtl_impure_ptr = 0x10000338;
-define exported symbol ArgvArray = 0x1000033c;
-define exported symbol pUartLogCtl = 0x10000364;
-define exported symbol UartLogBuf = 0x10000368;
-define exported symbol UartLogCtl = 0x100003e8;
-define exported symbol UartLogHistoryBuf = 0x10000408;
-define exported symbol NCO32K_Enable = 0x10000684;
-define exported symbol g_rtl_cipherEngine = 0x100006a0;
-define exported symbol DONGLE_InitStruct = 0x10000ba0;
-define exported symbol EFUSE_MAP = 0x10000ba4;
-define exported symbol USOC_BOOT_TXBD = 0x10000da4;
-define exported symbol USOC_BOOT_RXBD = 0x10000db4;
-define exported symbol USB_RXBuff = 0x10000dc4;
-define exported symbol USB_TXBuff = 0x10000dcc;
-define exported symbol ADC_AnaparAd = 0x10000dd4;
-define exported symbol flash_init_para = 0x10000dec;
-define exported symbol NEW_CALIBREATION_END = 0x10000e44;
-define exported symbol GDMA_Reg = 0x10000e4c;
-define exported symbol PortA_IrqHandler = 0x10000e50;
-define exported symbol PortA_IrqData = 0x10000ed0;
-define exported symbol IC_FS_SCL_HCNT_TRIM = 0x10000f50;
-define exported symbol IC_FS_SCL_LCNT_TRIM = 0x10000f54;
-define exported symbol I2C_SLAVEWRITE_PATCH = 0x10000f58;
-define exported symbol i2s_cur_tx_page = 0x10000f5c;
-define exported symbol i2s_cur_rx_page = 0x10000f60;
-define exported symbol i2s_page_num = 0x10000f64;
-define exported symbol i2s_txpage_entry = 0x10000f68;
-define exported symbol i2s_rxpage_entry = 0x10000f78;
-define exported symbol TXBDAddrAligned = 0x10000f88;
-define exported symbol H2C_Buff = 0x10000f90;
-define exported symbol SPI_RECV_Buff = 0x10000f94;
-define exported symbol spi_boot_recv_done = 0x10000f98;
-define exported symbol UART_StateRx = 0x10000f9c;
-define exported symbol UART_StateTx = 0x10000fa8;
-define exported symbol xMCtrl = 0x10000fb8;
-define exported symbol XComUARTx = 0x10000fc4;
-define exported symbol FalseAlmCnt = 0x10000fc8;
-define exported symbol ROMInfo = 0x10001008;
-define exported symbol DM_CfoTrack = 0x10001020;
-define exported symbol rom_wlan_ram_map = 0x10001048;
-define exported symbol rom_libgloss_ram_map = 0x10001050;
-define exported symbol __rtl_errno = 0x100014b4;
-define exported symbol rom_ssl_ram_map = 0x100014b8;
-define exported symbol __rom_bss_end__ = 0x100014f8;
+define exported symbol __vectors_table = 0x0;
+define exported symbol Reset_Handler = 0x101;
+define exported symbol NMI_Handler = 0x115;
+/*define exported symbol HardFault_Handler = 0x119;*/
+define exported symbol MemManage_Handler = 0x12d;
+define exported symbol BusFault_Handler = 0x131;
+define exported symbol UsageFault_Handler = 0x135;
+define exported symbol VSprintf = 0x201;
+define exported symbol DiagPrintf = 0x4dd;
+define exported symbol DiagSPrintf = 0x509;
+define exported symbol DiagSnPrintf = 0x535;
+define exported symbol prvDiagPrintf = 0x7ed;
+define exported symbol prvDiagSPrintf = 0x821;
+define exported symbol UARTIMG_Write = 0x855;
+define exported symbol UARTIMG_Download = 0x901;
+define exported symbol _memcmp = 0x991;
+define exported symbol _memcpy = 0x9c5;
+define exported symbol _memset = 0xa7d;
+define exported symbol DumpForOneBytes = 0xae9;
+define exported symbol CmdRomHelp = 0xc69;
+define exported symbol CmdDumpWord = 0xccd;
+define exported symbol CmdWriteWord = 0xd7d;
+define exported symbol CmdFlash = 0xdd1;
+define exported symbol CmdEfuse = 0x12c1;
+define exported symbol CmdDumpByte = 0x1775;
+define exported symbol CmdDumpHalfWord = 0x17c9;
+define exported symbol CmdWriteByte = 0x1881;
+define exported symbol SramReadWriteCpy = 0x18c1;
+define exported symbol SramReadWriteTest = 0x19f9;
+define exported symbol CmdSRamTest = 0x1ac9;
+define exported symbol GetRomCmdNum = 0x1b59;
+define exported symbol Rand = 0x1b5d;
+define exported symbol Rand_Arc4 = 0x1bdd;
+define exported symbol RandBytes_Get = 0x1c0d;
+define exported symbol Isspace = 0x1c59;
+define exported symbol Strtoul = 0x1c6d;
+define exported symbol ArrayInitialize = 0x1d15;
+define exported symbol GetArgc = 0x1d29;
+define exported symbol GetArgv = 0x1d55;
+define exported symbol UartLogCmdExecute = 0x1db1;
+define exported symbol UartLogShowBackSpace = 0x1e49;
+define exported symbol UartLogRecallOldCmd = 0x1e7d;
+define exported symbol UartLogHistoryCmd = 0x1eb1;
+define exported symbol UartLogCmdChk = 0x1f2d;
+define exported symbol UartLogIrqHandle = 0x2035;
+define exported symbol RtlConsolInit = 0x2101;
+define exported symbol RtlConsolTaskRom = 0x218d;
+define exported symbol RtlExitConsol = 0x21b9;
+define exported symbol RtlConsolRom = 0x2205;
+define exported symbol BKUP_Write = 0x2249;
+define exported symbol BKUP_Read = 0x226d;
+define exported symbol BKUP_Set = 0x228d;
+define exported symbol BKUP_Clear = 0x22b9;
+define exported symbol NCO32K_Init = 0x22e9;
+define exported symbol EXT32K_Cmd = 0x2349;
+define exported symbol NCO8M_Init = 0x2365;
+define exported symbol NCO8M_Cmd = 0x23bd;
+define exported symbol ISO_Set = 0x23d9;
+define exported symbol PLL0_Set = 0x23f1;
+define exported symbol PLL1_Set = 0x2409;
+define exported symbol PLL2_Set = 0x2421;
+define exported symbol PLL3_Set = 0x2439;
+define exported symbol XTAL0_Set = 0x2451;
+define exported symbol XTAL1_Set = 0x2469;
+define exported symbol XTAL2_Set = 0x2481;
+define exported symbol XTAL_ClkGet = 0x2499;
+define exported symbol CPU_ClkSet = 0x24b1;
+define exported symbol CPU_ClkGet = 0x24c5;
+define exported symbol OSC32K_Calibration = 0x24e5;
+define exported symbol OSC32K_Cmd = 0x25f9;
+define exported symbol OSC8M_Get = 0x2631;
+define exported symbol rtl_cryptoEngine_SrcDesc_Show = 0x2641;
+define exported symbol rtl_cryptoEngine_info = 0x27f1;
+define exported symbol rtl_cryptoEngine_init = 0x2949;
+define exported symbol rtl_crypto_md5_init = 0x2975;
+define exported symbol rtl_crypto_md5_process = 0x29b1;
+define exported symbol rtl_crypto_md5 = 0x2a09;
+define exported symbol rtl_crypto_sha1_init = 0x2a2d;
+define exported symbol rtl_crypto_sha1_process = 0x2a69;
+define exported symbol rtl_crypto_sha1 = 0x2a9d;
+define exported symbol rtl_crypto_sha2_init = 0x2ac1;
+define exported symbol rtl_crypto_sha2_process = 0x2b15;
+define exported symbol rtl_crypto_sha2 = 0x2b4d;
+define exported symbol rtl_crypto_hmac_md5_init = 0x2b71;
+define exported symbol rtl_crypto_hmac_md5_process = 0x2bd1;
+define exported symbol rtl_crypto_hmac_md5 = 0x2c0d;
+define exported symbol rtl_crypto_hmac_sha1_init = 0x2c31;
+define exported symbol rtl_crypto_hmac_sha1_process = 0x2c91;
+define exported symbol rtl_crypto_hmac_sha1 = 0x2cc9;
+define exported symbol rtl_crypto_hmac_sha2_init = 0x2ced;
+define exported symbol rtl_crypto_hmac_sha2_process = 0x2d65;
+define exported symbol rtl_crypto_hmac_sha2 = 0x2da1;
+define exported symbol rtl_crypto_aes_cbc_init = 0x2dc5;
+define exported symbol rtl_crypto_aes_cbc_encrypt = 0x2dfd;
+define exported symbol rtl_crypto_aes_cbc_decrypt = 0x2e45;
+define exported symbol rtl_crypto_aes_ecb_init = 0x2e8d;
+define exported symbol rtl_crypto_aes_ecb_encrypt = 0x2ec5;
+define exported symbol rtl_crypto_aes_ecb_decrypt = 0x2ef5;
+define exported symbol rtl_crypto_aes_ctr_init = 0x2f25;
+define exported symbol rtl_crypto_aes_ctr_encrypt = 0x2f5d;
+define exported symbol rtl_crypto_aes_ctr_decrypt = 0x2f99;
+define exported symbol rtl_crypto_3des_cbc_init = 0x2fd5;
+define exported symbol rtl_crypto_3des_cbc_encrypt = 0x300d;
+define exported symbol rtl_crypto_3des_cbc_decrypt = 0x3055;
+define exported symbol rtl_crypto_3des_ecb_init = 0x309d;
+define exported symbol rtl_crypto_3des_ecb_encrypt = 0x30d5;
+define exported symbol rtl_crypto_3des_ecb_decrypt = 0x311d;
+define exported symbol rtl_crypto_des_cbc_init = 0x3165;
+define exported symbol rtl_crypto_des_cbc_encrypt = 0x319d;
+define exported symbol rtl_crypto_des_cbc_decrypt = 0x31f5;
+define exported symbol rtl_crypto_des_ecb_init = 0x324d;
+define exported symbol rtl_crypto_des_ecb_encrypt = 0x3285;
+define exported symbol rtl_crypto_des_ecb_decrypt = 0x32dd;
+define exported symbol SYSTIMER_Init = 0x3335;
+define exported symbol SYSTIMER_TickGet = 0x33a1;
+define exported symbol SYSTIMER_GetPassTime = 0x33c1;
+define exported symbol DelayNop = 0x3401;
+define exported symbol DelayUs = 0x3411;
+define exported symbol DelayMs = 0x346d;
+define exported symbol USOC_DongleSpecialCmd = 0x3481;
+define exported symbol USOC_DongleCmd = 0x35d9;
+define exported symbol USOC_DongleIsr = 0x35f9;
+define exported symbol USOC_SIE_INTConfig = 0x3621;
+define exported symbol USOC_SIE_INTClear = 0x3639;
+define exported symbol USOC_PHY_Write = 0x3645;
+define exported symbol USOC_PHY_Read = 0x3679;
+define exported symbol USOC_PHY_Autoload = 0x36c1;
+define exported symbol USOC_DongleInit = 0x37a5;
+define exported symbol EFUSE_USER_Read = 0x386d;
+define exported symbol EFUSE_USER1_Read = 0x3971;
+define exported symbol EFUSE_USER2_Read = 0x397d;
+define exported symbol EFUSE_USER3_Read = 0x3989;
+define exported symbol EFUSE_RemainLength = 0x3995;
+define exported symbol EFUSE_USER_Write = 0x3a21;
+define exported symbol EFUSE_USER1_Write = 0x3bb1;
+define exported symbol EFUSE_USER2_Write = 0x3bc1;
+define exported symbol EFUSE_USER3_Write = 0x3bd1;
+define exported symbol EFUSE_OTP_Read1B = 0x3be1;
+define exported symbol EFUSE_OTP_Write1B = 0x3c01;
+define exported symbol EFUSE_OTP_Read32B = 0x3c21;
+define exported symbol EFUSE_OTP_Write32B = 0x3c4d;
+define exported symbol EFUSE_RDP_EN = 0x3cad;
+define exported symbol EFUSE_RDP_KEY = 0x3ccd;
+define exported symbol EFUSE_OTF_KEY = 0x3cf9;
+define exported symbol EFUSE_JTAG_OFF = 0x3d25;
+define exported symbol PAD_DrvStrength = 0x3d45;
+define exported symbol PAD_PullCtrl = 0x3d75;
+define exported symbol Pinmux_Config = 0x3dc5;
+define exported symbol Pinmux_ConfigGet = 0x3dfd;
+define exported symbol Pinmux_Deinit = 0x3e19;
+define exported symbol PINMUX_UART0_Ctrl = 0x3e39;
+define exported symbol PINMUX_UART1_Ctrl = 0x3e81;
+define exported symbol PINMUX_UARTLOG_Ctrl = 0x3ea9;
+define exported symbol PINMUX_SPI0_Ctrl = 0x3ef9;
+define exported symbol PINMUX_SPI1_Ctrl = 0x3f8d;
+define exported symbol PINMUX_SPIF_Ctrl = 0x400d;
+define exported symbol PINMUX_I2C0_Ctrl = 0x406d;
+define exported symbol PINMUX_I2C1_Ctrl = 0x40e1;
+define exported symbol PINMUX_SDIOD_Ctrl = 0x4151;
+define exported symbol PINMUX_I2S0_Ctrl = 0x41e5;
+define exported symbol PINMUX_SWD_Ctrl = 0x4265;
+define exported symbol PINMUX_SWD_OFF = 0x42b5;
+define exported symbol PINMUX_SWD_REG = 0x42d9;
+define exported symbol PINMUX_Ctrl = 0x42fd;
+define exported symbol SOCPS_BackupCPUClk = 0x4391;
+define exported symbol SOCPS_RestoreCPUClk = 0x43b1;
+define exported symbol SOCPS_BootFromPS = 0x43d1;
+define exported symbol SOCPS_TrapPin = 0x43f1;
+define exported symbol SOCPS_ANACKSel = 0x4411;
+define exported symbol SOCPS_CLKCal = 0x442d;
+define exported symbol SOCPS_SetWakeEvent = 0x4485;
+define exported symbol SOCPS_ClearWakeEvent = 0x449d;
+define exported symbol SOCPS_WakePinsCtrl = 0x44a9;
+define exported symbol SOCPS_WakePinCtrl = 0x44d9;
+define exported symbol SOCPS_WakePinClear = 0x4529;
+define exported symbol SOCPS_GetANATimerParam = 0x4539;
+define exported symbol SOCPS_SetANATimer = 0x4575;
+define exported symbol SOCPS_SetReguWakepin = 0x45dd;
+define exported symbol SOCPS_SetReguTimer = 0x4605;
+define exported symbol SOCPS_PWROption = 0x46d9;
+define exported symbol SOCPS_PWROptionExt = 0x46e5;
+define exported symbol SOCPS_PWRMode = 0x46f9;
+define exported symbol SOCPS_SNZMode = 0x4721;
+define exported symbol SOCPS_DeepStandby = 0x473d;
+define exported symbol SOCPS_DeepSleep = 0x4791;
+define exported symbol SDIO_StructInit = 0x47d5;
+define exported symbol SDIO_Init = 0x47f1;
+define exported symbol SDIO_INTClear = 0x486d;
+define exported symbol SDIO_INTConfig = 0x487d;
+define exported symbol SDIO_RPWM1_Get = 0x4895;
+define exported symbol SDIO_RPWM2_Get = 0x48a1;
+define exported symbol SDIO_CPWM1_Set = 0x48ad;
+define exported symbol SDIO_CPWM2_Set = 0x48c1;
+define exported symbol SDIO_RXBD_RPTR_Get = 0x48dd;
+define exported symbol SDIO_RXBD_WPTR_Set = 0x48e9;
+define exported symbol SDIO_TXBD_WPTR_Get = 0x48f5;
+define exported symbol SDIO_TXBD_RPTR_Set = 0x4901;
+define exported symbol SDIO_DMA_Reset = 0x490d;
+define exported symbol BOOT_ROM_Simulation = 0x4919;
+define exported symbol USOC_BOOT_TXBD_Proc = 0x491d;
+define exported symbol USOC_BOOT_Init = 0x4a3d;
+define exported symbol USB_Boot_ROM = 0x4aa9;
+define exported symbol USOC_CH_Cmd = 0x4b59;
+define exported symbol USOC_Cmd = 0x4bb1;
+define exported symbol USOC_PHY_Cmd = 0x4bf5;
+define exported symbol USOC_MODE_Cfg = 0x4c09;
+define exported symbol USOC_TXBD_SWIDX_Cfg = 0x4c25;
+define exported symbol USOC_TXBD_SWIDX_Get = 0x4c2d;
+define exported symbol USOC_TXBD_HWIDX_Get = 0x4c35;
+define exported symbol USOC_RXBD_HWIDX_Get = 0x4c3d;
+define exported symbol USOC_RXBD_SWIDX_Cfg = 0x4c45;
+define exported symbol USOC_RXBD_SWIDX_Get = 0x4c4d;
+define exported symbol USOC_StructInit = 0x4c55;
+define exported symbol USOC_Init = 0x4c85;
+define exported symbol USOC_SW_RST = 0x4d7d;
+define exported symbol USOC_INTCfg = 0x4d91;
+define exported symbol USOC_INTClr = 0x4d95;
+define exported symbol USOC_INTGet = 0x4d9d;
+define exported symbol USOC_MIT_Cfg = 0x4da1;
+define exported symbol USOC_TXSTUCK_Cfg = 0x4dc5;
+define exported symbol USOC_RXSTUCK_Cfg = 0x4de9;
+define exported symbol USOC_POWER_On = 0x4e0d;
+define exported symbol ADC_RXGDMA_Init = 0x4e9d;
+define exported symbol ADC_SetAudio = 0x4f45;
+define exported symbol ADC_SetAnalog = 0x4f61;
+define exported symbol ADC_Cmd = 0x4fbd;
+define exported symbol ADC_INTConfig = 0x5031;
+define exported symbol ADC_SetOneShot = 0x5049;
+define exported symbol ADC_SetComp = 0x50fd;
+define exported symbol ADC_INTClear = 0x517d;
+define exported symbol ADC_INTClearPendingBits = 0x5189;
+define exported symbol ADC_GetISR = 0x5195;
+define exported symbol ADC_Read = 0x51a1;
+define exported symbol ADC_ReceiveBuf = 0x51ad;
+define exported symbol ADC_InitStruct = 0x5205;
+define exported symbol ADC_Init = 0x524d;
+define exported symbol BOOT_ROM_ShowBuildInfo = 0x52ed;
+define exported symbol BOOT_ROM_OTFCheck = 0x5335;
+define exported symbol BOOT_ROM_InitFlash = 0x5345;
+define exported symbol BOOT_ROM_FromFlash = 0x5405;
+define exported symbol BOOT_ROM_InitUsb = 0x5511;
+define exported symbol BOOT_ROM_Process = 0x553d;
+define exported symbol BOOT_ROM_InitDebugFlg = 0x5605;
+define exported symbol HalResetVsr = 0x5639;
+define exported symbol Cache_Enable = 0x5811;
+define exported symbol Cache_Flush = 0x5831;
+define exported symbol Cache_Debug = 0x5851;
+define exported symbol CRYPTO_AlignToBe32 = 0x58bd;
+define exported symbol CRYPTO_MemDump = 0x58d5;
+define exported symbol CRYPTO_GetAESKey = 0x599d;
+define exported symbol CRYPTO_SetAESKey = 0x5cb5;
+define exported symbol CRYPTO_SetSecurityMode = 0x5d29;
+define exported symbol CRYPTO_Init = 0x5f5d;
+define exported symbol CRYPTO_DeInit = 0x60b9;
+define exported symbol CRYPTO_Reset = 0x6101;
+define exported symbol CRYPTO_Process = 0x6129;
+define exported symbol CRYPTO_CipherInit = 0x6a11;
+define exported symbol CRYPTO_CipherEncrypt = 0x6a35;
+define exported symbol CRYPTO_CipherDecrypt = 0x6a61;
+define exported symbol CRYPTO_SetCheckSumEn = 0x6a95;
+define exported symbol CRYPTO_GetCheckSumData = 0x6ab1;
+define exported symbol LOGUART_StructInit = 0x6abd;
+define exported symbol LOGUART_Init = 0x6ad5;
+define exported symbol LOGUART_PutChar = 0x6b15;
+define exported symbol LOGUART_GetChar = 0x6b49;
+define exported symbol LOGUART_GetIMR = 0x6b65;
+define exported symbol LOGUART_SetIMR = 0x6b71;
+define exported symbol LOGUART_WaitBusy = 0x6b7d;
+define exported symbol DIAG_UartInit = 0x6b9d;
+define exported symbol DIAG_UartReInit = 0x6c25;
+define exported symbol EFUSE_PowerSwitchROM = 0x6c49;
+define exported symbol EFUSE_OneByteReadROM = 0x6d65;
+define exported symbol EFUSE_OneByteWriteROM = 0x6e0d;
+define exported symbol EFUSE_PG_Packet = 0x6e29;
+define exported symbol EFUSE_LogicalMap_Read = 0x7091;
+define exported symbol EFUSE_LogicalMap_Write = 0x71f5;
+define exported symbol FLASH_SetSpiMode = 0x73dd;
+define exported symbol FLASH_RxCmd = 0x7465;
+define exported symbol FLASH_WaitBusy = 0x74cd;
+define exported symbol FLASH_RxData = 0x754d;
+define exported symbol FLASH_TxCmd = 0x75cd;
+define exported symbol FLASH_WriteEn = 0x763d;
+define exported symbol FLASH_TxData12B = 0x7661;
+define exported symbol FLASH_SetStatus = 0x7735;
+define exported symbol FLASH_Erase = 0x7755;
+define exported symbol FLASH_DeepPowerDown = 0x77f5;
+define exported symbol FLASH_SetStatusBits = 0x784d;
+define exported symbol FLASH_Calibration = 0x791d;
+define exported symbol FLASH_StructInit_Micron = 0x7a65;
+define exported symbol FLASH_StructInit_MXIC = 0x7af5;
+define exported symbol FLASH_StructInit_GD = 0x7b81;
+define exported symbol FLASH_StructInit = 0x7c11;
+define exported symbol FLASH_Init = 0x7ca1;
+define exported symbol FLASH_ClockDiv = 0x7d15;
+define exported symbol FLASH_CalibrationInit = 0x7d99;
+define exported symbol FLASH_Calibration500MPSCmd = 0x7db1;
+define exported symbol FLASH_CalibrationPhase = 0x7dcd;
+define exported symbol FLASH_CalibrationPhaseIdx = 0x7e59;
+define exported symbol FLASH_CalibrationNewCmd = 0x7e6d;
+define exported symbol FLASH_CalibrationNew = 0x7ea9;
+define exported symbol GDMA_StructInit = 0x80dd;
+define exported symbol GDMA_SetLLP = 0x80f9;
+define exported symbol GDMA_ClearINTPendingBit = 0x8191;
+define exported symbol GDMA_ClearINT = 0x81d5;
+define exported symbol GDMA_INTConfig = 0x8211;
+define exported symbol GDMA_Cmd = 0x8259;
+define exported symbol GDMA_Init = 0x828d;
+define exported symbol GDMA_ChCleanAutoReload = 0x83c1;
+define exported symbol GDMA_SetSrcAddr = 0x83f9;
+define exported symbol GDMA_GetSrcAddr = 0x8411;
+define exported symbol GDMA_GetDstAddr = 0x8429;
+define exported symbol GDMA_SetDstAddr = 0x843d;
+define exported symbol GDMA_SetBlkSize = 0x8459;
+define exported symbol GDMA_GetBlkSize = 0x8489;
+define exported symbol GDMA_ChnlRegister = 0x84a1;
+define exported symbol GDMA_ChnlUnRegister = 0x8529;
+define exported symbol GDMA_ChnlAlloc = 0x8591;
+define exported symbol GDMA_ChnlFree = 0x8615;
+define exported symbol GPIO_INTMode = 0x864d;
+define exported symbol GPIO_INTConfig = 0x86e5;
+define exported symbol GPIO_INTHandler = 0x8725;
+define exported symbol GPIO_Direction = 0x8771;
+define exported symbol GPIO_Init = 0x87a1;
+define exported symbol GPIO_DeInit = 0x886d;
+define exported symbol GPIO_ReadDataBit = 0x88c9;
+define exported symbol GPIO_WriteBit = 0x88ed;
+define exported symbol GPIO_PortDirection = 0x891d;
+define exported symbol GPIO_PortRead = 0x893d;
+define exported symbol GPIO_PortWrite = 0x894d;
+define exported symbol GPIO_UserRegIrq = 0x8969;
+define exported symbol I2C_StructInit = 0x899d;
+define exported symbol I2C_SetSpeed = 0x89e5;
+define exported symbol I2C_SetSlaveAddress = 0x8b3d;
+define exported symbol I2C_CheckFlagState = 0x8b79;
+define exported symbol I2C_INTConfig = 0x8bad;
+define exported symbol I2C_ClearINT = 0x8be5;
+define exported symbol I2C_ClearAllINT = 0x8c85;
+define exported symbol I2C_Init = 0x8cad;
+define exported symbol I2C_GetRawINT = 0x8dc9;
+define exported symbol I2C_GetINT = 0x8df1;
+define exported symbol I2C_MasterSendNullData = 0x8e19;
+define exported symbol I2C_MasterSend = 0x8e65;
+define exported symbol I2C_SlaveSend = 0x8ead;
+define exported symbol I2C_ReceiveData = 0x8ed9;
+define exported symbol I2C_MasterWrite = 0x8f05;
+define exported symbol I2C_MasterReadDW = 0x8f89;
+define exported symbol I2C_MasterRead = 0x9019;
+define exported symbol I2C_SlaveWrite = 0x9089;
+define exported symbol I2C_SlaveRead = 0x90f1;
+define exported symbol I2C_MasterRepeatRead = 0x9141;
+define exported symbol I2C_Cmd = 0x91c1;
+define exported symbol I2C_PinMuxInit = 0x91fd;
+define exported symbol I2C_PinMuxDeInit = 0x9255;
+define exported symbol I2C_DMAControl = 0x92ad;
+define exported symbol I2C_DmaMode1Config = 0x92e9;
+define exported symbol I2C_DmaMode2Config = 0x9331;
+define exported symbol I2C_TXGDMA_Init = 0x9375;
+define exported symbol I2C_RXGDMA_Init = 0x9459;
+define exported symbol I2C_Sleep_Cmd = 0x9521;
+define exported symbol I2C_WakeUp = 0x95a1;
+define exported symbol I2S_StructInit = 0x95e9;
+define exported symbol I2S_Cmd = 0x9611;
+define exported symbol I2S_TxDmaCmd = 0x962d;
+define exported symbol I2S_RxDmaCmd = 0x9641;
+define exported symbol I2S_INTConfig = 0x9655;
+define exported symbol I2S_INTClear = 0x965d;
+define exported symbol I2S_INTClearAll = 0x9665;
+define exported symbol I2S_Init = 0x9671;
+define exported symbol I2S_ISRGet = 0x97a9;
+define exported symbol I2S_SetRate = 0x97b5;
+define exported symbol I2S_SetWordLen = 0x9811;
+define exported symbol I2S_SetChNum = 0x9839;
+define exported symbol I2S_SetPageNum = 0x9861;
+define exported symbol I2S_SetPageSize = 0x9895;
+define exported symbol I2S_GetPageSize = 0x98a9;
+define exported symbol I2S_SetDirection = 0x98b5;
+define exported symbol I2S_SetDMABuf = 0x98dd;
+define exported symbol I2S_TxPageBusy = 0x9905;
+define exported symbol I2S_GetTxPage = 0x9911;
+define exported symbol I2S_GetRxPage = 0x991d;
+define exported symbol I2S_SetTxPageAddr = 0x9929;
+define exported symbol I2S_GetTxPageAddr = 0x9939;
+define exported symbol I2S_SetRxPageAddr = 0x9949;
+define exported symbol I2S_GetRxPageAddr = 0x9959;
+define exported symbol I2S_TxPageDMA_EN = 0x9969;
+define exported symbol I2S_RxPageDMA_EN = 0x998d;
+define exported symbol io_assert_failed = 0x99d9;
+define exported symbol OTF_init = 0x99fd;
+define exported symbol OTF_Cmd = 0x9a79;
+define exported symbol OTF_Mask = 0x9a8d;
+define exported symbol KEY_Request = 0x9add;
+define exported symbol RDP_EN_Request = 0x9b21;
+define exported symbol RCC_PeriphClockCmd = 0x9b65;
+define exported symbol FUNC_HCI_COM = 0x9c95;
+define exported symbol RTC_ByteToBcd2 = 0x9cad;
+define exported symbol RTC_Bcd2ToByte = 0x9cc9;
+define exported symbol RTC_ClokSource = 0x9cdd;
+define exported symbol RTC_EnterInitMode = 0x9d19;
+define exported symbol RTC_ExitInitMode = 0x9d51;
+define exported symbol RTC_WaitForSynchro = 0x9d61;
+define exported symbol RTC_BypassShadowCmd = 0x9da9;
+define exported symbol RTC_StructInit = 0x9dd9;
+define exported symbol RTC_Init = 0x9de5;
+define exported symbol RTC_TimeStructInit = 0x9e7d;
+define exported symbol RTC_SetTime = 0x9e8d;
+define exported symbol RTC_GetTime = 0x9ff9;
+define exported symbol RTC_SetAlarm = 0xa051;
+define exported symbol RTC_AlarmStructInit = 0xa211;
+define exported symbol RTC_GetAlarm = 0xa231;
+define exported symbol RTC_AlarmCmd = 0xa2a1;
+define exported symbol RTC_AlarmClear = 0xa2f5;
+define exported symbol RTC_DayLightSavingConfig = 0xa305;
+define exported symbol RTC_GetStoreOperation = 0xa355;
+define exported symbol RTC_OutputConfig = 0xa365;
+define exported symbol RTC_SmoothCalibConfig = 0xa39d;
+define exported symbol SDIO_IsTimeout = 0xa459;
+define exported symbol SDIOB_Init = 0xa481;
+define exported symbol SDIOB_INTConfig = 0xa575;
+define exported symbol SDIOB_DeInit = 0xa591;
+define exported symbol SDIOB_H2C_WriteMem = 0xa5d9;
+define exported symbol SDIOB_H2C_SetMem = 0xa605;
+define exported symbol SDIOB_H2C_DataHandle = 0xa631;
+define exported symbol SDIOB_H2C_DataReady = 0xa73d;
+define exported symbol SDIOB_IRQ_Handler_BH = 0xa80d;
+define exported symbol SDIOB_H2C_Task = 0xa8c9;
+define exported symbol SDIO_Boot_Up = 0xa8e5;
+define exported symbol SPI_DmaInit = 0xa91d;
+define exported symbol SPI_DataHandle = 0xa9d1;
+define exported symbol SPI_Boot_DmaRxIrqHandle = 0xaa01;
+define exported symbol SPI_Boot_ROM = 0xaa5d;
+define exported symbol SSI_StructInit = 0xabbd;
+define exported symbol SSI_Cmd = 0xabf5;
+define exported symbol SSI_INTConfig = 0xac09;
+define exported symbol SSI_SetSclkPolarity = 0xac19;
+define exported symbol SSI_SetSclkPhase = 0xac3d;
+define exported symbol SSI_SetDataFrameSize = 0xac61;
+define exported symbol SSI_SetReadLen = 0xac81;
+define exported symbol SSI_SetBaudDiv = 0xacb1;
+define exported symbol SSI_SetBaud = 0xaccd;
+define exported symbol SSI_SetDmaEnable = 0xad2d;
+define exported symbol SSI_SetDmaLevel = 0xad41;
+define exported symbol SSI_SetIsrClean = 0xad49;
+define exported symbol SSI_WriteData = 0xad65;
+define exported symbol SSI_SetRxFifoLevel = 0xad6d;
+define exported symbol SSI_SetTxFifoLevel = 0xad71;
+define exported symbol SSI_ReadData = 0xad75;
+define exported symbol SSI_GetRxCount = 0xad79;
+define exported symbol SSI_GetTxCount = 0xad81;
+define exported symbol SSI_GetStatus = 0xad89;
+define exported symbol SSI_Writeable = 0xad8d;
+define exported symbol SSI_Readable = 0xad9d;
+define exported symbol SSI_GetDataFrameSize = 0xadad;
+define exported symbol SSI_TXGDMA_Init = 0xadb9;
+define exported symbol SSI_RXGDMA_Init = 0xaef9;
+define exported symbol SSI_ReceiveData = 0xb021;
+define exported symbol SSI_SendData = 0xb0b9;
+define exported symbol SSI_Busy = 0xb165;
+define exported symbol SSI_SetSlaveEnable = 0xb175;
+define exported symbol SSI_Init = 0xb1ad;
+define exported symbol SSI_GetIsr = 0xb235;
+define exported symbol SSI_GetRawIsr = 0xb239;
+define exported symbol SSI_GetSlaveEnable = 0xb23d;
+define exported symbol SSI_PinmuxInit = 0xb241;
+define exported symbol SSI_PinmuxDeInit = 0xb2a9;
+define exported symbol SYSCFG0_Get = 0xb311;
+define exported symbol SYSCFG0_CUTVersion = 0xb31d;
+define exported symbol SYSCFG0_BDOption = 0xb32d;
+define exported symbol SYSCFG1_Get = 0xb33d;
+define exported symbol SYSCFG1_AutoLoadDone = 0xb349;
+define exported symbol SYSCFG1_TRP_LDOMode = 0xb359;
+define exported symbol SYSCFG1_TRP_UARTImage = 0xb369;
+define exported symbol SYSCFG1_TRP_ICFG = 0xb37d;
+define exported symbol SYSCFG2_Get = 0xb389;
+define exported symbol SYSCFG2_ROMINFO_Get = 0xb395;
+define exported symbol SYSCFG2_ROMINFO_Set = 0xb3a1;
+define exported symbol RTIM_TimeBaseStructInit = 0xb3b5;
+define exported symbol RTIM_Cmd = 0xb3cd;
+define exported symbol RTIM_GetCount = 0xb42d;
+define exported symbol RTIM_UpdateDisableConfig = 0xb475;
+define exported symbol RTIM_ARRPreloadConfig = 0xb4c5;
+define exported symbol RTIM_UpdateRequestConfig = 0xb515;
+define exported symbol RTIM_PrescalerConfig = 0xb575;
+define exported symbol RTIM_GenerateEvent = 0xb5a1;
+define exported symbol RTIM_ChangePeriod = 0xb5f9;
+define exported symbol RTIM_Reset = 0xb64d;
+define exported symbol RTIM_CCStructInit = 0xb68d;
+define exported symbol RTIM_CCxInit = 0xb6a1;
+define exported symbol RTIM_CCRxMode = 0xb749;
+define exported symbol RTIM_CCRxSet = 0xb785;
+define exported symbol RTIM_CCRxGet = 0xb7dd;
+define exported symbol RTIM_OCxPreloadConfig = 0xb80d;
+define exported symbol RTIM_CCxPolarityConfig = 0xb85d;
+define exported symbol RTIM_CCxCmd = 0xb8ad;
+define exported symbol RTIM_SetOnePulseOutputMode = 0xb901;
+define exported symbol RTIM_DMACmd = 0xb959;
+define exported symbol RTIM_TXGDMA_Init = 0xb9a9;
+define exported symbol RTIM_RXGDMA_Init = 0xba5d;
+define exported symbol RTIM_INTConfig = 0xbb3d;
+define exported symbol RTIM_INTClear = 0xbba9;
+define exported symbol RTIM_TimeBaseInit = 0xbbed;
+define exported symbol RTIM_DeInit = 0xbced;
+define exported symbol RTIM_INTClearPendingBit = 0xbd41;
+define exported symbol RTIM_GetFlagStatus = 0xbd81;
+define exported symbol RTIM_GetINTStatus = 0xbded;
+define exported symbol UART_DeInit = 0xbe61;
+define exported symbol UART_StructInit = 0xbe69;
+define exported symbol UART_BaudParaGet = 0xbe81;
+define exported symbol UART_BaudParaGetFull = 0xbec9;
+define exported symbol UART_SetBaud = 0xbf01;
+define exported symbol UART_SetBaudExt = 0xbf71;
+define exported symbol UART_SetRxLevel = 0xbfc1;
+define exported symbol UART_RxCmd = 0xbfe9;
+define exported symbol UART_Writable = 0xbffd;
+define exported symbol UART_Readable = 0xc005;
+define exported symbol UART_CharPut = 0xc00d;
+define exported symbol UART_CharGet = 0xc011;
+define exported symbol UART_ReceiveData = 0xc019;
+define exported symbol UART_SendData = 0xc041;
+define exported symbol UART_ReceiveDataTO = 0xc069;
+define exported symbol UART_SendDataTO = 0xc0a9;
+define exported symbol UART_RxByteCntClear = 0xc0e9;
+define exported symbol UART_RxByteCntGet = 0xc0f5;
+define exported symbol UART_BreakCtl = 0xc0fd;
+define exported symbol UART_ClearRxFifo = 0xc111;
+define exported symbol UART_Init = 0xc135;
+define exported symbol UART_ClearTxFifo = 0xc1d1;
+define exported symbol UART_INTConfig = 0xc1dd;
+define exported symbol UART_IntStatus = 0xc1ed;
+define exported symbol UART_ModemStatusGet = 0xc1f1;
+define exported symbol UART_LineStatusGet = 0xc1f5;
+define exported symbol UART_WaitBusy = 0xc1f9;
+define exported symbol UART_PinMuxInit = 0xc221;
+define exported symbol UART_PinMuxDeinit = 0xc289;
+define exported symbol UART_TXDMAConfig = 0xc2f1;
+define exported symbol UART_RXDMAConfig = 0xc301;
+define exported symbol UART_TXDMACmd = 0xc315;
+define exported symbol UART_RXDMACmd = 0xc329;
+define exported symbol UART_TXGDMA_Init = 0xc33d;
+define exported symbol UART_RXGDMA_Init = 0xc425;
+define exported symbol UART_LPRxStructInit = 0xc501;
+define exported symbol UART_LPRxInit = 0xc50d;
+define exported symbol UART_LPRxBaudSet = 0xc575;
+define exported symbol UART_LPRxMonitorCmd = 0xc5f1;
+define exported symbol UART_LPRxpathSet = 0xc62d;
+define exported symbol UART_LPRxIPClockSet = 0xc641;
+define exported symbol UART_LPRxCmd = 0xc6b1;
+define exported symbol UART_LPRxMonBaudCtrlRegGet = 0xc6c5;
+define exported symbol UART_LPRxMonitorSatusGet = 0xc6c9;
+define exported symbol UART_IrDAStructInit = 0xc6cd;
+define exported symbol UART_IrDAInit = 0xc6e5;
+define exported symbol UART_IrDACmd = 0xc7bd;
+define exported symbol INT_SysOn = 0xc7d1;
+define exported symbol INT_Wdg = 0xc811;
+define exported symbol INT_Timer0 = 0xc855;
+define exported symbol INT_Timer1 = 0xc899;
+define exported symbol INT_Timer2 = 0xc8dd;
+define exported symbol INT_Timer3 = 0xc921;
+define exported symbol INT_SPI0 = 0xc965;
+define exported symbol INT_GPIO = 0xc9a9;
+define exported symbol INT_Uart0 = 0xc9ed;
+define exported symbol INT_SPIFlash = 0xca31;
+define exported symbol INT_Uart1 = 0xca75;
+define exported symbol INT_Timer4 = 0xcab9;
+define exported symbol INT_I2S0 = 0xcafd;
+define exported symbol INT_Timer5 = 0xcb41;
+define exported symbol INT_WlDma = 0xcb85;
+define exported symbol INT_WlProtocol = 0xcbc9;
+define exported symbol INT_IPSEC = 0xcc0d;
+define exported symbol INT_SPI1 = 0xcc51;
+define exported symbol INT_Peripheral = 0xcc95;
+define exported symbol INT_Gdma0Ch0 = 0xccd9;
+define exported symbol INT_Gdma0Ch1 = 0xcd1d;
+define exported symbol INT_Gdma0Ch2 = 0xcd61;
+define exported symbol INT_Gdma0Ch3 = 0xcda5;
+define exported symbol INT_Gdma0Ch4 = 0xcde9;
+define exported symbol INT_Gdma0Ch5 = 0xce2d;
+define exported symbol INT_I2C0 = 0xce71;
+define exported symbol INT_I2C1 = 0xceb5;
+define exported symbol INT_Uartlog = 0xcef9;
+define exported symbol INT_ADC = 0xcf3d;
+define exported symbol INT_RDP = 0xcf81;
+define exported symbol INT_RTC = 0xcfc5;
+define exported symbol INT_Gdma1Ch0 = 0xd009;
+define exported symbol INT_Gdma1Ch1 = 0xd051;
+define exported symbol INT_Gdma1Ch2 = 0xd099;
+define exported symbol INT_Gdma1Ch3 = 0xd0e1;
+define exported symbol INT_Gdma1Ch4 = 0xd129;
+define exported symbol INT_Gdma1Ch5 = 0xd171;
+define exported symbol INT_USB = 0xd1b9;
+define exported symbol INT_RXI300 = 0xd201;
+define exported symbol INT_USB_SIE = 0xd249;
+define exported symbol INT_SdioD = 0xd291;
+define exported symbol INT_NMI = 0xd2d1;
+define exported symbol INT_HardFault = 0xd305;
+define exported symbol INT_MemManage = 0xd4b5;
+define exported symbol INT_BusFault = 0xd4d5;
+define exported symbol INT_UsageFault = 0xd4f5;
+define exported symbol VECTOR_TableInit = 0xd515;
+define exported symbol VECTOR_TableInitForOS = 0xd6c5;
+define exported symbol VECTOR_IrqRegister = 0xd6d5;
+define exported symbol VECTOR_IrqUnRegister = 0xd6f9;
+define exported symbol VECTOR_IrqEn = 0xd715;
+define exported symbol VECTOR_IrqDis = 0xd765;
+define exported symbol WDG_Scalar = 0xd7a1;
+define exported symbol WDG_Init = 0xd7e1;
+define exported symbol WDG_IrqClear = 0xd7fd;
+define exported symbol WDG_IrqInit = 0xd80d;
+define exported symbol WDG_Cmd = 0xd83d;
+define exported symbol WDG_Refresh = 0xd85d;
+define exported symbol _strncpy = 0xd86d;
+define exported symbol _strcpy = 0xd889;
+define exported symbol prvStrCpy = 0xd899;
+define exported symbol _strlen = 0xd8b1;
+define exported symbol _strnlen = 0xd8c9;
+define exported symbol prvStrLen = 0xd8fd;
+define exported symbol _strcmp = 0xd919;
+define exported symbol _strncmp = 0xd939;
+define exported symbol prvStrCmp = 0xd985;
+define exported symbol StrUpr = 0xd9b5;
+define exported symbol prvAtoi = 0xd9d1;
+define exported symbol prvStrtok = 0xda29;
+define exported symbol prvStrStr = 0xda81;
+define exported symbol _strsep = 0xdab9;
+define exported symbol skip_spaces = 0xdaf5;
+define exported symbol skip_atoi = 0xdb11;
+define exported symbol _parse_integer_fixup_radix = 0xdb49;
+define exported symbol _parse_integer = 0xdb9d;
+define exported symbol simple_strtoull = 0xdc01;
+define exported symbol simple_strtoll = 0xdc21;
+define exported symbol simple_strtoul = 0xdc41;
+define exported symbol simple_strtol = 0xdc49;
+define exported symbol _vsscanf = 0xdc61;
+define exported symbol _sscanf = 0xe1c9;
+define exported symbol div_u64 = 0xe1e5;
+define exported symbol div_s64 = 0xe1ed;
+define exported symbol div_u64_rem = 0xe1f5;
+define exported symbol div_s64_rem = 0xe205;
+define exported symbol _strpbrk = 0xe215;
+define exported symbol _strchr = 0xe241;
+define exported symbol COMMPORT_GET_T = 0xe259;
+define exported symbol COMMPORT_CLEAN_RX = 0xe289;
+define exported symbol xModemDebugInit = 0xe2a5;
+define exported symbol xModemDebug = 0xe2dd;
+define exported symbol xModemInquiry = 0xe315;
+define exported symbol xModemGetFirst = 0xe339;
+define exported symbol xModemGetOthers = 0xe45d;
+define exported symbol xModemRxFrame = 0xe691;
+define exported symbol xModemHandshake = 0xe6d5;
+define exported symbol xModemRxBuffer = 0xe945;
+define exported symbol xmodem_log_close = 0xe9f5;
+define exported symbol xmodem_log_open = 0xea01;
+define exported symbol xmodem_uart_init = 0xea39;
+define exported symbol xmodem_uart_deinit = 0xeb25;
+define exported symbol xmodem_uart_port_init = 0xeb35;
+define exported symbol xmodem_uart_port_deinit = 0xeb99;
+define exported symbol xmodem_uart_readable = 0xebdd;
+define exported symbol xmodem_uart_writable = 0xebf5;
+define exported symbol xmodem_uart_getc = 0xec0d;
+define exported symbol xmodem_uart_putc = 0xec35;
+define exported symbol xmodem_uart_putdata = 0xec49;
+define exported symbol aes_set_key = 0xec65;
+define exported symbol aes_encrypt = 0xf021;
+define exported symbol aes_decrypt = 0x10171;
+define exported symbol AES_WRAP = 0x112b1;
+define exported symbol AES_UnWRAP = 0x113fd;
+define exported symbol crc32_get = 0x11549;
+define exported symbol arc4_byte = 0x1157d;
+define exported symbol rt_arc4_init = 0x115a5;
+define exported symbol rt_arc4_crypt = 0x115e9;
+define exported symbol rt_md5_init = 0x11df5;
+define exported symbol rt_md5_append = 0x11e25;
+define exported symbol rt_md5_final = 0x11ec9;
+define exported symbol rt_md5_hmac = 0x11f21;
+define exported symbol RC4 = 0x12061;
+define exported symbol RC4_set_key = 0x1238d;
+define exported symbol ROM_WIFI_ReadPowerValue = 0x1246d;
+define exported symbol ROM_WIFI_EfuseParseTxPowerInfo = 0x1251d;
+define exported symbol ROM_WIFI_8051Reset = 0x125c5;
+define exported symbol ROM_WIFI_FWDownloadEnable = 0x125dd;
+define exported symbol ROM_WIFI_BlockWrite = 0x12619;
+define exported symbol ROM_WIFI_PageWrite = 0x12661;
+define exported symbol ROM_WIFI_FillDummy = 0x12685;
+define exported symbol ROM_WIFI_WriteFW = 0x126b1;
+define exported symbol ROM_WIFI_FWFreeToGo = 0x1275d;
+define exported symbol ROM_WIFI_InitLLTTable = 0x127f9;
+define exported symbol ROM_WIFI_GetChnlGroup = 0x12879;
+define exported symbol ROM_WIFI_BWMapping = 0x129f1;
+define exported symbol ROM_WIFI_SCMapping = 0x12a19;
+define exported symbol ROM_WIFI_FillTxdescSectype = 0x12a99;
+define exported symbol ROM_WIFI_FillFakeTxdesc = 0x12ab9;
+define exported symbol ROM_WIFI_32K_Cmd = 0x12b91;
+define exported symbol ROM_WIFI_DISCONNECT = 0x12bc1;
+define exported symbol ROM_WIFI_SET_TSF = 0x12bfd;
+define exported symbol ROM_WIFI_BCN_FUNC = 0x12ca5;
+define exported symbol ROM_WIFI_BSSID_SET = 0x12ccd;
+define exported symbol ROM_WIFI_MACADDR_SET = 0x12d09;
+define exported symbol ROM_WIFI_EnableInterrupt = 0x12d39;
+define exported symbol ROM_WIFI_DisableInterrupt = 0x12d4d;
+define exported symbol ROM_WIFI_RESUME_TxBeacon = 0x12d61;
+define exported symbol ROM_WIFI_STOP_TXBeacon = 0x12d91;
+define exported symbol ROM_WIFI_BCN_Interval = 0x12dc1;
+define exported symbol ROM_WIFI_BCN_FUNC_Enable = 0x12dcd;
+define exported symbol ROM_WIFI_INIT_BeaconParameters = 0x12de5;
+define exported symbol ROM_WIFI_MEDIA_STATUS1 = 0x12e35;
+define exported symbol ROM_WIFI_MEDIA_STATUS = 0x12e4d;
+define exported symbol ROM_WIFI_SetBrateCfg = 0x12e61;
+define exported symbol ROM_WIFI_BASIC_RATE = 0x12f69;
+define exported symbol ROM_WIFI_CHECK_BSSID = 0x12fc9;
+define exported symbol ROM_WIFI_RESP_SIFS = 0x12fe9;
+define exported symbol ROM_WIFI_CAM_WRITE = 0x13001;
+define exported symbol ROM_WIFI_ACM_CTRL = 0x13021;
+define exported symbol ROM_WIFI_FIFO_CLEARN_UP = 0x13051;
+define exported symbol ROM_WIFI_CHECK_TXBUF = 0x130b9;
+define exported symbol ROM_WIFI_BCN_VALID = 0x130fd;
+define exported symbol ROM_WIFI_PROMISC_Cmd = 0x13119;
+define exported symbol ROM_WIFI_SetOpmodeAP = 0x13189;
+define exported symbol ROM_WIFI_ReadChipVersion = 0x132a9;
+define exported symbol ROM_WIFI_DumpChipInfo = 0x1330d;
+define exported symbol ROM_WIFI_InitLxDma = 0x135b1;
+define exported symbol ROM_WIFI_InitQueueReservedPage = 0x13671;
+define exported symbol ROM_WIFI_InitTxBufferBoundary = 0x136f1;
+define exported symbol ROM_WIFI_InitNormalChipRegPriority = 0x1373d;
+define exported symbol ROM_WIFI_InitPageBoundary = 0x13789;
+define exported symbol ROM_WIFI_InitTransferPageSize = 0x13795;
+define exported symbol ROM_WIFI_InitDriverInfoSize = 0x137a1;
+define exported symbol ROM_WIFI_InitNetworkType = 0x137ad;
+define exported symbol ROM_WIFI_InitRCR = 0x137c5;
+define exported symbol ROM_WIFI_InitAdaptiveCtrl = 0x13805;
+define exported symbol ROM_WIFI_InitSIFS = 0x1383d;
+define exported symbol ROM_WIFI_InitEDCA = 0x13865;
+define exported symbol ROM_WIFI_InitRateFallback = 0x138a1;
+define exported symbol ROM_WIFI_InitRetryFunction = 0x138c9;
+define exported symbol ROM_WIFI_InitOperationMode = 0x138e5;
+define exported symbol ROM_WIFI_InitBurstPktLen = 0x138f9;
+define exported symbol phy_CalculateBitShift = 0x13905;
+define exported symbol PHY_SetBBReg_8711B = 0x1391d;
+define exported symbol PHY_QueryBBReg_8711B = 0x13921;
+define exported symbol ROM_odm_QueryRxPwrPercentage = 0x13925;
+define exported symbol ROM_odm_EVMdbToPercentage = 0x13931;
+define exported symbol ROM_odm_SignalScaleMapping_8711B = 0x13935;
+define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x13a11;
+define exported symbol ROM_odm_SetEDCCAThreshold = 0x13d39;
+define exported symbol ROM_odm_SetTRxMux = 0x13d61;
+define exported symbol ROM_odm_SetCrystalCap = 0x13d89;
+define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x13ded;
+define exported symbol ROM_ODM_CfoTrackingReset = 0x13dfd;
+define exported symbol ROM_odm_CfoTrackingFlow = 0x13e21;
+define exported symbol rtw_get_bit_value_from_ieee_value = 0x14045;
+define exported symbol rtw_is_cckrates_included = 0x14071;
+define exported symbol rtw_is_cckratesonly_included = 0x140a5;
+define exported symbol rtw_check_network_type = 0x140cd;
+define exported symbol rtw_set_fixed_ie = 0x14155;
+define exported symbol rtw_set_ie = 0x14175;
+define exported symbol rtw_get_ie = 0x141a1;
+define exported symbol rtw_set_supported_rate = 0x141b5;
+define exported symbol rtw_get_rateset_len = 0x14229;
+define exported symbol rtw_get_wpa_ie = 0x14245;
+define exported symbol rtw_get_wpa2_ie = 0x142d1;
+define exported symbol rtw_get_wpa_cipher_suite = 0x142e5;
+define exported symbol rtw_get_wpa2_cipher_suite = 0x1434d;
+define exported symbol rtw_parse_wpa_ie = 0x143b5;
+define exported symbol rtw_parse_wpa2_ie = 0x14481;
+define exported symbol rtw_get_sec_ie = 0x14535;
+define exported symbol rtw_get_wps_ie = 0x145e5;
+define exported symbol rtw_get_wps_attr = 0x14659;
+define exported symbol rtw_get_wps_attr_content = 0x146f1;
+define exported symbol rtw_ieee802_11_parse_elems = 0x14739;
+define exported symbol str_2char2num = 0x14909;
+define exported symbol key_2char2num = 0x14925;
+define exported symbol convert_ip_addr = 0x1493d;
+define exported symbol rom_psk_PasswordHash = 0x14a21;
+define exported symbol rom_psk_CalcGTK = 0x14a59;
+define exported symbol rom_psk_CalcPTK = 0x14ae9;
+define exported symbol _htons_rom = 0x14bdd;
+define exported symbol _ntohs_rom = 0x14be5;
+define exported symbol _htonl_rom = 0x14bed;
+define exported symbol _ntohl_rom = 0x14bf1;
+define exported symbol Message_ReplayCounter_OC2LI = 0x14bf5;
+define exported symbol Message_EqualReplayCounter = 0x14c35;
+define exported symbol Message_SmallerEqualReplayCounter = 0x14c6d;
+define exported symbol Message_LargerReplayCounter = 0x14cad;
+define exported symbol Message_setReplayCounter = 0x14ce5;
+define exported symbol INCLargeInteger = 0x14d15;
+define exported symbol INCOctet16_INTEGER = 0x14d25;
+define exported symbol INCOctet32_INTEGER = 0x14d8d;
+define exported symbol SetEAPOL_KEYIV = 0x14df5;
+define exported symbol CheckMIC = 0x14e89;
+define exported symbol CalcMIC = 0x14f29;
+define exported symbol DecWPA2KeyData_rom = 0x14f9d;
+define exported symbol DecGTK = 0x15055;
+define exported symbol GetRandomBuffer = 0x15119;
+define exported symbol GenNonce = 0x15181;
+define exported symbol ClientConstructEAPOL_2Of4Way = 0x151c5;
+define exported symbol ClientConstructEAPOL_4Of4Way = 0x152cd;
+define exported symbol ClientConstructEAPOL_2Of2Way = 0x1537d;
+define exported symbol ClientConstructEAPOL_MICOf2Way = 0x15459;
+define exported symbol psk_strip_rsn_pairwise = 0x1552d;
+define exported symbol psk_strip_wpa_pairwise = 0x155c1;
+define exported symbol wep_80211_encrypt = 0x1587d;
+define exported symbol wep_80211_decrypt = 0x158e1;
+define exported symbol tkip_micappendbyte = 0x15975;
+define exported symbol rtw_secmicsetkey = 0x159b9;
+define exported symbol rtw_secmicappend = 0x159f9;
+define exported symbol rtw_secgetmic = 0x15a15;
+define exported symbol rtw_seccalctkipmic = 0x15a89;
+define exported symbol tkip_phase1 = 0x15b7d;
+define exported symbol tkip_phase2 = 0x15ce5;
+define exported symbol tkip_80211_encrypt = 0x15f01;
+define exported symbol tkip_80211_decrypt = 0x15f91;
+define exported symbol aes1_encrypt = 0x16055;
+define exported symbol aesccmp_construct_mic_iv = 0x1625d;
+define exported symbol aesccmp_construct_mic_header1 = 0x162b1;
+define exported symbol aesccmp_construct_mic_header2 = 0x16321;
+define exported symbol aesccmp_construct_ctr_preload = 0x163a5;
+define exported symbol aes_80211_encrypt = 0x16429;
+define exported symbol aes_80211_decrypt = 0x167f9;
+define exported symbol cckrates_included = 0x16c39;
+define exported symbol cckratesonly_included = 0x16c7d;
+define exported symbol networktype_to_raid_ex_rom = 0x16ca9;
+define exported symbol judge_network_type_rom = 0x16cf5;
+define exported symbol ratetbl_val_2wifirate = 0x16d89;
+define exported symbol is_basicrate_rom = 0x16d9d;
+define exported symbol ratetbl2rateset_rom = 0x16dd5;
+define exported symbol get_rate_set_rom = 0x16e3d;
+define exported symbol UpdateBrateTbl_rom = 0x16e71;
+define exported symbol UpdateBrateTblForSoftAP = 0x16ec9;
+define exported symbol write_cam_rom = 0x16f0d;
+define exported symbol HT_caps_handler_rom = 0x16fc1;
+define exported symbol wifirate2_ratetbl_inx = 0x17015;
+define exported symbol update_basic_rate = 0x170bd;
+define exported symbol update_supported_rate = 0x170f5;
+define exported symbol update_MCS_rate = 0x17125;
+define exported symbol get_highest_rate_idx = 0x17131;
+define exported symbol _sha1_process_message_block = 0x1714d;
+define exported symbol _sha1_pad_message = 0x172d1;
+define exported symbol rt_sha1_init = 0x1736d;
+define exported symbol rt_sha1_update = 0x173b1;
+define exported symbol rt_sha1_finish = 0x17429;
+define exported symbol rt_hmac_sha1 = 0x17489;
+define exported symbol rom_aes_128_cbc_encrypt = 0x175e5;
+define exported symbol rom_aes_128_cbc_decrypt = 0x17669;
+define exported symbol rom_rijndaelKeySetupEnc = 0x176ed;
+define exported symbol rom_aes_decrypt_init = 0x177c1;
+define exported symbol rom_aes_internal_decrypt = 0x17899;
+define exported symbol rom_aes_decrypt_deinit = 0x17bdd;
+define exported symbol rom_aes_encrypt_init = 0x17be9;
+define exported symbol rom_aes_internal_encrypt = 0x17c01;
+define exported symbol rom_aes_encrypt_deinit = 0x17f81;
+define exported symbol bignum_init = 0x1963d;
+define exported symbol bignum_deinit = 0x19665;
+define exported symbol bignum_get_unsigned_bin_len = 0x19685;
+define exported symbol bignum_get_unsigned_bin = 0x19689;
+define exported symbol bignum_set_unsigned_bin = 0x19741;
+define exported symbol bignum_cmp = 0x197f9;
+define exported symbol bignum_cmp_d = 0x197fd;
+define exported symbol bignum_add = 0x19825;
+define exported symbol bignum_sub = 0x19835;
+define exported symbol bignum_mul = 0x19845;
+define exported symbol bignum_exptmod = 0x19855;
+define exported symbol WPS_realloc = 0x19879;
+define exported symbol os_zalloc = 0x198bd;
+define exported symbol rom_hmac_sha256_vector = 0x198e1;
+define exported symbol rom_hmac_sha256 = 0x199e1;
+define exported symbol rom_sha256_vector = 0x19b3d;
+define exported symbol CRYPTO_chacha_20 = 0x19d45;
+define exported symbol rom_ed25519_gen_keypair = 0x1a1bd;
+define exported symbol rom_ed25519_gen_signature = 0x1a1c1;
+define exported symbol rom_ed25519_verify_signature = 0x1a1d9;
+define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x1c4c9;
+define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x1c8c1;
+define exported symbol rom_ed25519_ge_p3_tobytes = 0x1d43d;
+define exported symbol rom_ed25519_ge_scalarmult_base = 0x1d489;
+define exported symbol rom_ed25519_ge_tobytes = 0x1d64d;
+define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x1d699;
+define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x1d6f1;
+define exported symbol rom_ed25519_sc_muladd = 0x1d9e5;
+define exported symbol rom_ed25519_sc_reduce = 0x24175;
+define exported symbol rom_ed25519_crypto_sign_detached = 0x26c25;
+define exported symbol CRYPTO_poly1305_init = 0x270dd;
+define exported symbol CRYPTO_poly1305_update = 0x271b5;
+define exported symbol CRYPTO_poly1305_finish = 0x27245;
+define exported symbol rom_sha512_starts = 0x28511;
+define exported symbol rom_sha512_update = 0x28659;
+define exported symbol rom_sha512_finish = 0x28661;
+define exported symbol rom_sha512 = 0x288a9;
+define exported symbol rom_sha512_hmac_starts = 0x288e1;
+define exported symbol rom_sha512_hmac_update = 0x289a5;
+define exported symbol rom_sha512_hmac_finish = 0x289ad;
+define exported symbol rom_sha512_hmac_reset = 0x289fd;
+define exported symbol rom_sha512_hmac = 0x28a19;
+define exported symbol rom_sha512_hkdf = 0x28a51;
+define exported symbol aes_test_alignment_detection = 0x28b59;
+define exported symbol aes_mode_reset = 0x28bbd;
+define exported symbol aes_ecb_encrypt = 0x28bc9;
+define exported symbol aes_ecb_decrypt = 0x28c05;
+define exported symbol aes_cbc_encrypt = 0x28c41;
+define exported symbol aes_cbc_decrypt = 0x28dad;
+define exported symbol aes_cfb_encrypt = 0x28f49;
+define exported symbol aes_cfb_decrypt = 0x2920d;
+define exported symbol aes_ofb_crypt = 0x294d5;
+define exported symbol aes_ctr_crypt = 0x29769;
+define exported symbol aes_encrypt_key128 = 0x29a79;
+define exported symbol aes_encrypt_key192 = 0x29a95;
+define exported symbol aes_encrypt_key256 = 0x29ab1;
+define exported symbol aes_encrypt_key = 0x29ad1;
+define exported symbol aes_decrypt_key128 = 0x29b41;
+define exported symbol aes_decrypt_key192 = 0x29b5d;
+define exported symbol aes_decrypt_key256 = 0x29b79;
+define exported symbol aes_decrypt_key = 0x29b99;
+define exported symbol aes_init = 0x29c09;
+define exported symbol curve25519_donna = 0x2a939;
+define exported symbol __rtl_dtoa_r_v1_00 = 0x2b7f1;
+define exported symbol __rtl_ltoa_v1_00 = 0x2c7f9;
+define exported symbol __rtl_ultoa_v1_00 = 0x2c885;
+define exported symbol __rtl_dtoi_v1_00 = 0x2c8ed;
+define exported symbol __rtl_dtoi64_v1_00 = 0x2c96d;
+define exported symbol __rtl_dtoui_v1_00 = 0x2ca09;
+define exported symbol __rtl_ftol_v1_00 = 0x2ca11;
+define exported symbol __rtl_itof_v1_00 = 0x2ca75;
+define exported symbol __rtl_itod_v1_00 = 0x2cb05;
+define exported symbol __rtl_i64tod_v1_00 = 0x2cb71;
+define exported symbol __rtl_uitod_v1_00 = 0x2cc4d;
+define exported symbol __rtl_ftod_v1_00 = 0x2cd29;
+define exported symbol __rtl_dtof_v1_00 = 0x2cde1;
+define exported symbol __rtl_uitof_v1_00 = 0x2ce75;
+define exported symbol __rtl_fadd_v1_00 = 0x2cf59;
+define exported symbol __rtl_fsub_v1_00 = 0x2d259;
+define exported symbol __rtl_fmul_v1_00 = 0x2d565;
+define exported symbol __rtl_fdiv_v1_00 = 0x2d695;
+define exported symbol __rtl_dadd_v1_00 = 0x2d809;
+define exported symbol __rtl_dsub_v1_00 = 0x2de49;
+define exported symbol __rtl_dmul_v1_00 = 0x2e4a1;
+define exported symbol __rtl_ddiv_v1_00 = 0x2e7dd;
+define exported symbol __rtl_dcmpeq_v1_00 = 0x2ed71;
+define exported symbol __rtl_dcmplt_v1_00 = 0x2eded;
+define exported symbol __rtl_dcmpgt_v1_00 = 0x2ee85;
+define exported symbol __rtl_dcmple_v1_00 = 0x2ef95;
+define exported symbol __rtl_fcmplt_v1_00 = 0x2f0a9;
+define exported symbol __rtl_fcmpgt_v1_00 = 0x2f105;
+define exported symbol __rtl_fpclassifyd = 0x2f1ad;
+define exported symbol __rtl_close_v1_00 = 0x2f205;
+define exported symbol __rtl_fstat_v1_00 = 0x2f219;
+define exported symbol __rtl_isatty_v1_00 = 0x2f22d;
+define exported symbol __rtl_lseek_v1_00 = 0x2f23d;
+define exported symbol __rtl_open_v1_00 = 0x2f251;
+define exported symbol __rtl_read_v1_00 = 0x2f265;
+define exported symbol __rtl_write_v1_00 = 0x2f279;
+define exported symbol __rtl_sbrk_v1_00 = 0x2f28d;
+define exported symbol __rom_mallocr_init_v1_00 = 0x2f29d;
+define exported symbol __rtl_free_r_v1_00 = 0x2f309;
+define exported symbol __rtl_malloc_r_v1_00 = 0x2f521;
+define exported symbol __rtl_realloc_r_v1_00 = 0x2f9f5;
+define exported symbol __rtl_memalign_r_v1_00 = 0x2fdb5;
+define exported symbol __rtl_valloc_r_v1_00 = 0x2fe81;
+define exported symbol __rtl_pvalloc_r_v1_00 = 0x2fe8d;
+define exported symbol __rtl_calloc_r_v1_00 = 0x2fea1;
+define exported symbol __rtl_cfree_r_v1_00 = 0x2ff05;
+define exported symbol __rtl_cos_f32_v1_00 = 0x2ff15;
+define exported symbol __rtl_sin_f32_v1_00 = 0x300e9;
+define exported symbol __rtl_fabs_v1_00 = 0x302ad;
+define exported symbol __rtl_fabsf_v1_00 = 0x302b5;
+define exported symbol __rtl_memchr_v1_00 = 0x302bd;
+define exported symbol __rtl_memcmp_v1_00 = 0x30351;
+define exported symbol __rtl_memcpy_v1_00 = 0x303b5;
+define exported symbol __rtl_memmove_v1_00 = 0x3045d;
+define exported symbol __rtl_memset_v1_00 = 0x30525;
+define exported symbol __rtl_Balloc_v1_00 = 0x3061d;
+define exported symbol __rtl_Bfree_v1_00 = 0x3066d;
+define exported symbol __rtl_i2b_v1_00 = 0x30681;
+define exported symbol __rtl_multadd_v1_00 = 0x30695;
+define exported symbol __rtl_mult_v1_00 = 0x30721;
+define exported symbol __rtl_pow5mult_v1_00 = 0x30855;
+define exported symbol __rtl_hi0bits_v1_00 = 0x308f5;
+define exported symbol __rtl_d2b_v1_00 = 0x30935;
+define exported symbol __rtl_lshift_v1_00 = 0x309ed;
+define exported symbol __rtl_cmp_v1_00 = 0x30a99;
+define exported symbol __rtl_diff_v1_00 = 0x30ae1;
+define exported symbol __rtl_sread_v1_00 = 0x30bb5;
+define exported symbol __rtl_seofread_v1_00 = 0x30c01;
+define exported symbol __rtl_swrite_v1_00 = 0x30c05;
+define exported symbol __rtl_sseek_v1_00 = 0x30c75;
+define exported symbol __rtl_sclose_v1_00 = 0x30cc1;
+define exported symbol __rtl_sbrk_r_v1_00 = 0x30ced;
+define exported symbol __rtl_strcat_v1_00 = 0x30d15;
+define exported symbol __rtl_strchr_v1_00 = 0x30d59;
+define exported symbol __rtl_strcmp_v1_00 = 0x30e25;
+define exported symbol __rtl_strcpy_v1_00 = 0x30e99;
+define exported symbol __rtl_strlen_v1_00 = 0x30ee5;
+define exported symbol __rtl_strncat_v1_00 = 0x30f39;
+define exported symbol __rtl_strncmp_v1_00 = 0x30f95;
+define exported symbol __rtl_strncpy_v1_00 = 0x3102d;
+define exported symbol __rtl_strsep_v1_00 = 0x31095;
+define exported symbol __rtl_strstr_v1_00 = 0x3136d;
+define exported symbol __rtl_strtok_v1_00 = 0x315a5;
+define exported symbol __rtl__strtok_r_v1_00 = 0x315b5;
+define exported symbol __rtl_strtok_r_v1_00 = 0x31619;
+define exported symbol __rtl_fflush_r_v1_00 = 0x31ae9;
+define exported symbol __rtl_vfprintf_r_v1_00 = 0x31f99;
+define exported symbol polarssl_aes_init = 0x335b9;
+define exported symbol aes_free = 0x335c9;
+define exported symbol aes_setkey_enc = 0x335dd;
+define exported symbol aes_setkey_dec = 0x33829;
+define exported symbol aes_crypt_ecb = 0x339a1;
+define exported symbol aes_crypt_cbc = 0x343d1;
+define exported symbol aes_crypt_cfb128 = 0x34649;
+define exported symbol aes_crypt_cfb8 = 0x346c9;
+define exported symbol aes_crypt_ctr = 0x3474d;
+define exported symbol arc4_init = 0x347b1;
+define exported symbol arc4_free = 0x347bd;
+define exported symbol arc4_setup = 0x347d1;
+define exported symbol arc4_crypt = 0x3481d;
+define exported symbol asn1_get_len = 0x34861;
+define exported symbol asn1_get_tag = 0x34901;
+define exported symbol asn1_get_bool = 0x34929;
+define exported symbol asn1_get_int = 0x3495d;
+define exported symbol asn1_get_mpi = 0x349a9;
+define exported symbol asn1_get_bitstring = 0x349d1;
+define exported symbol asn1_get_bitstring_null = 0x34a19;
+define exported symbol asn1_get_sequence_of = 0x34a4d;
+define exported symbol asn1_get_alg = 0x34ad1;
+define exported symbol asn1_get_alg_null = 0x34b65;
+define exported symbol asn1_free_named_data = 0x34ba5;
+define exported symbol asn1_free_named_data_list = 0x34bcd;
+define exported symbol asn1_find_named_data = 0x34bf5;
+define exported symbol asn1_write_len = 0x34c25;
+define exported symbol asn1_write_tag = 0x34c8d;
+define exported symbol asn1_write_raw_buffer = 0x34ca9;
+define exported symbol asn1_write_mpi = 0x34ccd;
+define exported symbol asn1_write_null = 0x34d41;
+define exported symbol asn1_write_oid = 0x34d6d;
+define exported symbol asn1_write_algorithm_identifier = 0x34dc5;
+define exported symbol asn1_write_bool = 0x34e21;
+define exported symbol asn1_write_int = 0x34e65;
+define exported symbol asn1_write_printable_string = 0x34ecd;
+define exported symbol asn1_write_ia5_string = 0x34f25;
+define exported symbol asn1_write_bitstring = 0x34f7d;
+define exported symbol asn1_write_octet_string = 0x34fe5;
+define exported symbol asn1_store_named_data = 0x3503d;
+define exported symbol base64_encode = 0x35111;
+define exported symbol base64_decode = 0x3523d;
+define exported symbol mpi_init = 0x35e09;
+define exported symbol mpi_free = 0x35e19;
+define exported symbol mpi_grow = 0x35e55;
+define exported symbol mpi_shrink = 0x35e79;
+define exported symbol mpi_copy = 0x35f21;
+define exported symbol mpi_swap = 0x35fa1;
+define exported symbol mpi_safe_cond_assign = 0x35fcd;
+define exported symbol mpi_safe_cond_swap = 0x36069;
+define exported symbol mpi_lset = 0x3610d;
+define exported symbol mpi_get_bit = 0x3614d;
+define exported symbol mpi_set_bit = 0x3616d;
+define exported symbol mpi_lsb = 0x361d5;
+define exported symbol mpi_msb = 0x36215;
+define exported symbol mpi_size = 0x36261;
+define exported symbol mpi_read_binary = 0x3626d;
+define exported symbol mpi_write_binary = 0x362f9;
+define exported symbol mpi_shift_l = 0x36341;
+define exported symbol mpi_shift_r = 0x363f1;
+define exported symbol mpi_cmp_abs = 0x36475;
+define exported symbol mpi_cmp_mpi = 0x36619;
+define exported symbol mpi_cmp_int = 0x366f1;
+define exported symbol mpi_add_abs = 0x3671d;
+define exported symbol mpi_sub_abs = 0x3680d;
+define exported symbol mpi_add_mpi = 0x3689d;
+define exported symbol mpi_sub_mpi = 0x368ed;
+define exported symbol mpi_add_int = 0x3693d;
+define exported symbol mpi_sub_int = 0x36969;
+define exported symbol mpi_mul_mpi = 0x36995;
+define exported symbol mpi_read_string = 0x36ac5;
+define exported symbol mpi_mul_int = 0x36c45;
+define exported symbol mpi_div_mpi = 0x36c61;
+define exported symbol mpi_div_int = 0x370ed;
+define exported symbol mpi_mod_mpi = 0x37119;
+define exported symbol mpi_mod_int = 0x3717d;
+define exported symbol mpi_write_string = 0x3722d;
+define exported symbol mpi_exp_mod = 0x37395;
+define exported symbol mpi_gcd = 0x37915;
+define exported symbol mpi_fill_random = 0x37a39;
+define exported symbol mpi_inv_mod = 0x37c4d;
+define exported symbol mpi_is_prime = 0x37f15;
+define exported symbol mpi_gen_prime = 0x37f71;
+define exported symbol ctr_drbg_free = 0x38285;
+define exported symbol ctr_drbg_set_prediction_resistance = 0x382a1;
+define exported symbol ctr_drbg_set_entropy_len = 0x382a5;
+define exported symbol ctr_drbg_set_reseed_interval = 0x382a9;
+define exported symbol ctr_drbg_update = 0x382ad;
+define exported symbol ctr_drbg_reseed = 0x382c9;
+define exported symbol ctr_drbg_init_entropy_len = 0x38341;
+define exported symbol ctr_drbg_init = 0x38399;
+define exported symbol ctr_drbg_random_with_add = 0x383ad;
+define exported symbol ctr_drbg_random = 0x38469;
+define exported symbol des_init = 0x388a5;
+define exported symbol des_free = 0x388b1;
+define exported symbol des3_init = 0x388c5;
+define exported symbol des3_free = 0x388d5;
+define exported symbol des_key_set_parity = 0x388e9;
+define exported symbol des_key_check_key_parity = 0x38909;
+define exported symbol des_key_check_weak = 0x38939;
+define exported symbol des_setkey_enc = 0x38965;
+define exported symbol des_setkey_dec = 0x3898d;
+define exported symbol des3_set2key_enc = 0x389d9;
+define exported symbol des3_set2key_dec = 0x38a25;
+define exported symbol des3_set3key_enc = 0x38a71;
+define exported symbol des3_set3key_dec = 0x38ab1;
+define exported symbol des_crypt_ecb = 0x38af1;
+define exported symbol des_crypt_cbc = 0x38d09;
+define exported symbol des3_crypt_ecb = 0x38f99;
+define exported symbol des3_crypt_cbc = 0x39401;
+define exported symbol dhm_init = 0x39729;
+define exported symbol dhm_read_params = 0x39731;
+define exported symbol dhm_make_params = 0x3978d;
+define exported symbol dhm_read_public = 0x398c1;
+define exported symbol dhm_make_public = 0x398e9;
+define exported symbol dhm_calc_secret = 0x399ad;
+define exported symbol dhm_free = 0x39ba1;
+define exported symbol dhm_parse_dhm = 0x39c01;
+define exported symbol ecdh_gen_public = 0x39cc5;
+define exported symbol ecdh_compute_shared = 0x39cc9;
+define exported symbol ecdh_init = 0x39d2d;
+define exported symbol ecdh_free = 0x39d39;
+define exported symbol ecdh_make_params = 0x39d81;
+define exported symbol ecdh_read_params = 0x39e05;
+define exported symbol ecdh_get_params = 0x39e2d;
+define exported symbol ecdh_make_public = 0x39e79;
+define exported symbol ecdh_read_public = 0x39ed1;
+define exported symbol ecdh_calc_secret = 0x39f01;
+define exported symbol ecdsa_sign = 0x3a041;
+define exported symbol ecdsa_sign_det = 0x3a1c5;
+define exported symbol ecdsa_verify = 0x3a2a9;
+define exported symbol ecdsa_write_signature = 0x3a431;
+define exported symbol ecdsa_write_signature_det = 0x3a46d;
+define exported symbol ecdsa_read_signature = 0x3a4a5;
+define exported symbol ecdsa_genkey = 0x3a531;
+define exported symbol ecdsa_init = 0x3a565;
+define exported symbol ecdsa_free = 0x3a591;
+define exported symbol ecdsa_from_keypair = 0x3a5bd;
+define exported symbol ecp_curve_list = 0x3aee5;
+define exported symbol ecp_curve_info_from_grp_id = 0x3aeed;
+define exported symbol ecp_curve_info_from_tls_id = 0x3af0d;
+define exported symbol ecp_curve_info_from_name = 0x3af31;
+define exported symbol ecp_point_init = 0x3af61;
+define exported symbol ecp_group_init = 0x3af81;
+define exported symbol ecp_keypair_init = 0x3af8d;
+define exported symbol ecp_point_free = 0x3afb1;
+define exported symbol ecp_group_free = 0x3afd1;
+define exported symbol ecp_keypair_free = 0x3b03d;
+define exported symbol ecp_copy = 0x3b05d;
+define exported symbol ecp_group_copy = 0x3b08d;
+define exported symbol ecp_set_zero = 0x3b095;
+define exported symbol ecp_is_zero = 0x3ba61;
+define exported symbol ecp_point_read_string = 0x3ba75;
+define exported symbol ecp_point_write_binary = 0x3baa5;
+define exported symbol ecp_point_read_binary = 0x3bb4d;
+define exported symbol ecp_tls_read_point = 0x3bbc1;
+define exported symbol ecp_tls_write_point = 0x3bbf5;
+define exported symbol ecp_group_read_string = 0x3bc25;
+define exported symbol ecp_tls_read_group = 0x3bc95;
+define exported symbol ecp_tls_write_group = 0x3bcf1;
+define exported symbol ecp_add = 0x3bd39;
+define exported symbol ecp_sub = 0x3bd65;
+define exported symbol ecp_check_pubkey = 0x3bddd;
+define exported symbol ecp_check_privkey = 0x3bf8d;
+define exported symbol ecp_mul = 0x3bff5;
+define exported symbol ecp_gen_keypair = 0x3c565;
+define exported symbol ecp_gen_key = 0x3c669;
+define exported symbol ecp_use_known_dp = 0x3d741;
+define exported symbol hmac_drbg_update = 0x3daa9;
+define exported symbol hmac_drbg_init_buf = 0x3db41;
+define exported symbol hmac_drbg_reseed = 0x3db91;
+define exported symbol hmac_drbg_init = 0x3dc09;
+define exported symbol hmac_drbg_set_prediction_resistance = 0x3dc81;
+define exported symbol hmac_drbg_set_entropy_len = 0x3dc85;
+define exported symbol hmac_drbg_set_reseed_interval = 0x3dc89;
+define exported symbol hmac_drbg_random_with_add = 0x3dc8d;
+define exported symbol hmac_drbg_random = 0x3dd4d;
+define exported symbol hmac_drbg_free = 0x3dd61;
+define exported symbol md_list = 0x3dd7d;
+define exported symbol md_info_from_string = 0x3dd85;
+define exported symbol md_info_from_type = 0x3de59;
+define exported symbol md_init = 0x3de9d;
+define exported symbol md_free = 0x3dea5;
+define exported symbol md_init_ctx = 0x3dec5;
+define exported symbol md_free_ctx = 0x3defd;
+define exported symbol md_starts = 0x3df09;
+define exported symbol md_update = 0x3df29;
+define exported symbol md_finish = 0x3df49;
+define exported symbol md = 0x3df69;
+define exported symbol md_file = 0x3df89;
+define exported symbol md_hmac_starts = 0x3dfa1;
+define exported symbol md_hmac_update = 0x3dfc1;
+define exported symbol md_hmac_finish = 0x3dfe1;
+define exported symbol md_hmac_reset = 0x3e001;
+define exported symbol md_hmac = 0x3e021;
+define exported symbol md_process = 0x3e049;
+define exported symbol md5_init = 0x3e301;
+define exported symbol md5_free = 0x3e309;
+define exported symbol md5_starts = 0x3e31d;
+define exported symbol md5_process = 0x3e34d;
+define exported symbol md5_update = 0x3ed51;
+define exported symbol md5_finish = 0x3ed59;
+define exported symbol md5 = 0x3ee11;
+define exported symbol md5_hmac_starts = 0x3ee75;
+define exported symbol md5_hmac_update = 0x3ef51;
+define exported symbol md5_hmac_finish = 0x3ef59;
+define exported symbol md5_hmac_reset = 0x3efbd;
+define exported symbol md5_hmac = 0x3eff1;
+define exported symbol oid_get_attr_short_name = 0x3f071;
+define exported symbol oid_get_x509_ext_type = 0x3f0b1;
+define exported symbol oid_get_extended_key_usage = 0x3f0f1;
+define exported symbol oid_get_sig_alg_desc = 0x3f131;
+define exported symbol oid_get_sig_alg = 0x3f149;
+define exported symbol oid_get_oid_by_sig_alg = 0x3f169;
+define exported symbol oid_get_pk_alg = 0x3f1a1;
+define exported symbol oid_get_oid_by_pk_alg = 0x3f1e1;
+define exported symbol oid_get_ec_grp = 0x3f219;
+define exported symbol oid_get_oid_by_ec_grp = 0x3f259;
+define exported symbol oid_get_cipher_alg = 0x3f291;
+define exported symbol oid_get_md_alg = 0x3f2d1;
+define exported symbol oid_get_oid_by_md = 0x3f311;
+define exported symbol oid_get_pkcs12_pbe_alg = 0x3f349;
+define exported symbol oid_get_numeric_string = 0x3f391;
+define exported symbol pem_init = 0x3f649;
+define exported symbol pem_read_buffer = 0x3f651;
+define exported symbol pem_free = 0x3f955;
+define exported symbol pem_write_buffer = 0x3f97d;
+define exported symbol pk_init = 0x3fa81;
+define exported symbol pk_free = 0x3fa8d;
+define exported symbol pk_info_from_type = 0x3faad;
+define exported symbol pk_init_ctx = 0x3fae1;
+define exported symbol pk_init_ctx_rsa_alt = 0x3fb11;
+define exported symbol pk_can_do = 0x3fb69;
+define exported symbol pk_verify = 0x3fb79;
+define exported symbol pk_verify_ext = 0x3fbc9;
+define exported symbol pk_sign = 0x3fc8d;
+define exported symbol pk_decrypt = 0x3fce9;
+define exported symbol pk_encrypt = 0x3fd15;
+define exported symbol pk_get_size = 0x3fd41;
+define exported symbol pk_debug = 0x3fd51;
+define exported symbol pk_get_name = 0x3fd79;
+define exported symbol pk_get_type = 0x3fd8d;
+define exported symbol pk_write_pubkey = 0x40181;
+define exported symbol pk_write_pubkey_der = 0x40201;
+define exported symbol pk_write_key_der = 0x402dd;
+define exported symbol pk_write_pubkey_pem = 0x404f5;
+define exported symbol pk_write_key_pem = 0x40545;
+define exported symbol rsa_init = 0x4065d;
+define exported symbol rsa_set_padding = 0x40679;
+define exported symbol rsa_check_pubkey = 0x40685;
+define exported symbol rsa_check_privkey = 0x406e1;
+define exported symbol rsa_public = 0x409a5;
+define exported symbol rsa_private = 0x40a25;
+define exported symbol rsa_rsaes_oaep_encrypt = 0x40c29;
+define exported symbol rsa_rsaes_pkcs1_v15_encrypt = 0x40d31;
+define exported symbol rsa_pkcs1_encrypt = 0x40e19;
+define exported symbol rsa_rsaes_oaep_decrypt = 0x40e59;
+define exported symbol rsa_rsaes_pkcs1_v15_decrypt = 0x40fbd;
+define exported symbol rsa_pkcs1_decrypt = 0x410c1;
+define exported symbol rsa_rsassa_pss_sign = 0x4110d;
+define exported symbol rsa_rsassa_pkcs1_v15_sign = 0x41271;
+define exported symbol rsa_pkcs1_sign = 0x41389;
+define exported symbol rsa_rsassa_pss_verify_ext = 0x413c9;
+define exported symbol rsa_rsassa_pss_verify = 0x41575;
+define exported symbol rsa_rsassa_pkcs1_v15_verify = 0x415a5;
+define exported symbol rsa_pkcs1_verify = 0x41709;
+define exported symbol rsa_free = 0x41765;
+define exported symbol rsa_gen_key = 0x417d5;
+define exported symbol rsa_copy = 0x4198d;
+define exported symbol sha1_init = 0x41a9d;
+define exported symbol sha1_free = 0x41aa5;
+define exported symbol sha1_starts = 0x41ab9;
+define exported symbol sha1_process = 0x41aed;
+define exported symbol sha1_update = 0x42e15;
+define exported symbol sha1_finish = 0x42e1d;
+define exported symbol sha1 = 0x42ee5;
+define exported symbol sha1_hmac_starts = 0x42f51;
+define exported symbol sha1_hmac_update = 0x43039;
+define exported symbol sha1_hmac_finish = 0x43041;
+define exported symbol sha1_hmac_reset = 0x430b5;
+define exported symbol sha1_hmac = 0x430f1;
+define exported symbol sha256_init = 0x43139;
+define exported symbol sha256_free = 0x43141;
+define exported symbol sha256_starts = 0x43155;
+define exported symbol sha256_process = 0x431e5;
+define exported symbol sha256_update = 0x4513d;
+define exported symbol sha256_finish = 0x45145;
+define exported symbol sha256 = 0x4524d;
+define exported symbol sha256_hmac_starts = 0x45325;
+define exported symbol sha256_hmac_update = 0x45475;
+define exported symbol sha256_hmac_finish = 0x4547d;
+define exported symbol sha256_hmac_reset = 0x45569;
+define exported symbol sha256_hmac = 0x45601;
+define exported symbol sha512_init = 0x45651;
+define exported symbol sha512_free = 0x4565d;
+define exported symbol sha512_starts = 0x45671;
+define exported symbol sha512_process = 0x457b9;
+define exported symbol sha512_update = 0x46879;
+define exported symbol sha512_finish = 0x46881;
+define exported symbol sha512 = 0x46ac9;
+define exported symbol sha512_hmac_starts = 0x46b11;
+define exported symbol sha512_hmac_update = 0x46bd9;
+define exported symbol sha512_hmac_finish = 0x46be1;
+define exported symbol sha512_hmac_reset = 0x46c35;
+define exported symbol sha512_hmac = 0x46c51;
+define exported symbol UartLogRomCmdTable = 0x46ca0;
+define exported symbol XTAL_CLK = 0x46e10;
+define exported symbol CpkClkTbl_FPAG = 0x46e50;
+define exported symbol CpkClkTbl_ASIC = 0x46e68;
+define exported symbol ROM_IMG1_VALID_PATTEN = 0x46e90;
+define exported symbol __AES_rcon = 0x46e98;
+define exported symbol __AES_Te4 = 0x46ec0;
+define exported symbol SpicCalibrationPattern = 0x472c0;
+define exported symbol NEW_CALIBREATION_DIV = 0x472c8;
+define exported symbol NEW_CALIBREATION_DATA = 0x472e4;
+define exported symbol GDMA_IrqNum = 0x47344;
+define exported symbol I2C_DEV_TABLE = 0x47350;
+define exported symbol spi_clk_pin = 0x47370;
+define exported symbol SPI_DEV_TABLE = 0x47374;
+define exported symbol PWM_GDMA_HSx = 0x47394;
+define exported symbol TIM_DMA_CCx = 0x473ac;
+define exported symbol TIM_IT_CCx = 0x473c4;
+define exported symbol TIMx = 0x473dc;
+define exported symbol TIMx_irq = 0x473f4;
+define exported symbol BAUDRATE_TABLE_40M = 0x4740c;
+define exported symbol UART_DEV_TABLE = 0x475bc;
+define exported symbol RTW_WPA_OUI_TYPE = 0x4b270;
+define exported symbol WPA_CIPHER_SUITE_NONE = 0x4b274;
+define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x4b278;
+define exported symbol WPA_CIPHER_SUITE_TKIP = 0x4b27c;
+define exported symbol WPA_CIPHER_SUITE_CCMP = 0x4b280;
+define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x4b284;
+define exported symbol RSN_CIPHER_SUITE_NONE = 0x4b288;
+define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x4b28c;
+define exported symbol RSN_CIPHER_SUITE_TKIP = 0x4b290;
+define exported symbol RSN_CIPHER_SUITE_CCMP = 0x4b294;
+define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x4b298;
+define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x4b2a8;
+define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x4b2ac;
+define exported symbol RSN_VERSION_BSD = 0x4b2b0;
+define exported symbol rom_e_rtw_msgp_str_ = 0x4b2b4;
+define exported symbol rtw_basic_rate_mix = 0x4b9a8;
+define exported symbol rtw_basic_rate_ofdm = 0x4b9b0;
+define exported symbol rtw_basic_rate_cck = 0x4b9b4;
+define exported symbol REALTEK_96B_IE = 0x4b9b8;
+define exported symbol AIRGOCAP_OUI = 0x4b9c0;
+define exported symbol REALTEK_OUI = 0x4b9c4;
+define exported symbol RALINK_OUI = 0x4b9c8;
+define exported symbol MARVELL_OUI = 0x4b9cc;
+define exported symbol CISCO_OUI = 0x4b9d0;
+define exported symbol BROADCOM_OUI3 = 0x4b9d4;
+define exported symbol BROADCOM_OUI2 = 0x4b9d8;
+define exported symbol BROADCOM_OUI1 = 0x4b9dc;
+define exported symbol ARTHEROS_OUI2 = 0x4b9e0;
+define exported symbol ARTHEROS_OUI1 = 0x4b9e4;
+define exported symbol rom_wps_rcons = 0x4b9e8;
+define exported symbol rom_wps_Te0 = 0x4b9f4;
+define exported symbol rom_wps_Td4s = 0x4bdf4;
+define exported symbol rom_wps_Td0 = 0x4bef4;
+define exported symbol sha512_info = 0x5850c;
+define exported symbol sha384_info = 0x5854c;
+define exported symbol sha256_info = 0x5858c;
+define exported symbol sha224_info = 0x585cc;
+define exported symbol sha1_info = 0x5860c;
+define exported symbol md5_info = 0x5864c;
+define exported symbol rsa_alt_info = 0x58d28;
+define exported symbol ecdsa_info = 0x58d54;
+define exported symbol eckeydh_info = 0x58d80;
+define exported symbol eckey_info = 0x58dac;
+define exported symbol rsa_info = 0x58dd8;
+define exported symbol __rom_bss_start__ = 0x10000000;
+define exported symbol NewVectorTable = 0x10000000;
+define exported symbol UserIrqFunTable = 0x10000100;
+define exported symbol UserIrqDataTable = 0x10000200;
+define exported symbol ConfigDebugClose = 0x10000300;
+define exported symbol CfgSysDebugWarn = 0x10000304;
+define exported symbol CfgSysDebugInfo = 0x10000308;
+define exported symbol CfgSysDebugErr = 0x1000030c;
+define exported symbol ConfigDebugWarn = 0x10000310;
+define exported symbol ConfigDebugInfo = 0x10000314;
+define exported symbol ConfigDebugErr = 0x10000318;
+define exported symbol sector_addr = 0x1000031c;
+define exported symbol _rtl_impure_ptr = 0x10000338;
+define exported symbol ArgvArray = 0x1000033c;
+define exported symbol pUartLogCtl = 0x10000364;
+define exported symbol UartLogBuf = 0x10000368;
+define exported symbol UartLogCtl = 0x100003e8;
+define exported symbol UartLogHistoryBuf = 0x10000408;
+define exported symbol NCO32K_Enable = 0x10000684;
+define exported symbol g_rtl_cipherEngine = 0x100006a0;
+define exported symbol DONGLE_InitStruct = 0x10000ba0;
+define exported symbol EFUSE_MAP = 0x10000ba4;
+define exported symbol USOC_BOOT_TXBD = 0x10000da4;
+define exported symbol USOC_BOOT_RXBD = 0x10000db4;
+define exported symbol USB_RXBuff = 0x10000dc4;
+define exported symbol USB_TXBuff = 0x10000dcc;
+define exported symbol ADC_AnaparAd = 0x10000dd4;
+define exported symbol flash_init_para = 0x10000dec;
+define exported symbol NEW_CALIBREATION_END = 0x10000e44;
+define exported symbol GDMA_Reg = 0x10000e4c;
+define exported symbol PortA_IrqHandler = 0x10000e50;
+define exported symbol PortA_IrqData = 0x10000ed0;
+define exported symbol IC_FS_SCL_HCNT_TRIM = 0x10000f50;
+define exported symbol IC_FS_SCL_LCNT_TRIM = 0x10000f54;
+define exported symbol I2C_SLAVEWRITE_PATCH = 0x10000f58;
+define exported symbol i2s_cur_tx_page = 0x10000f5c;
+define exported symbol i2s_cur_rx_page = 0x10000f60;
+define exported symbol i2s_page_num = 0x10000f64;
+define exported symbol i2s_txpage_entry = 0x10000f68;
+define exported symbol i2s_rxpage_entry = 0x10000f78;
+define exported symbol TXBDAddrAligned = 0x10000f88;
+define exported symbol H2C_Buff = 0x10000f90;
+define exported symbol SPI_RECV_Buff = 0x10000f94;
+define exported symbol spi_boot_recv_done = 0x10000f98;
+define exported symbol UART_StateRx = 0x10000f9c;
+define exported symbol UART_StateTx = 0x10000fa8;
+define exported symbol xMCtrl = 0x10000fb8;
+define exported symbol XComUARTx = 0x10000fc4;
+define exported symbol FalseAlmCnt = 0x10000fc8;
+define exported symbol ROMInfo = 0x10001008;
+define exported symbol DM_CfoTrack = 0x10001020;
+define exported symbol rom_wlan_ram_map = 0x10001048;
+define exported symbol rom_libgloss_ram_map = 0x10001050;
+define exported symbol __rtl_errno = 0x100014b4;
+define exported symbol rom_ssl_ram_map = 0x100014b8;
+define exported symbol __rom_bss_end__ = 0x100014f8;
diff --git a/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds b/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds
index 8f9c4fa1a8..b5adb02196 100644
--- a/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds
+++ b/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds
@@ -65,7 +65,7 @@ SECTIONS
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
- _start_address_init_data = .;
+ _start_address_init_data = .;
} > ROM
__exidx_end = .;
@@ -76,7 +76,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
- _start_address_data = .;
+ _start_address_data = .;
*(.data)
*(.data.*)
@@ -91,21 +91,21 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
- _end_address_data = .;
+ _end_address_data = .;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
- _end_stack = .;
+ _end_stack = .;
} >RAM
__bss_start = .;
- _start_address_bss = .;
+ _start_address_bss = .;
.bss :
{
. = ALIGN(4);
@@ -119,11 +119,11 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
- _end_address_bss = .;
+ _end_address_bss = .;
_end = .;
diff --git a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds
index 5d1d12bbfb..646a746d7c 100644
--- a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds
+++ b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds
@@ -80,7 +80,7 @@ SECTIONS
_end_address_data = .;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -102,7 +102,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/apm32/apm32f407ig-minibroard/board/linker_scripts/link.lds b/bsp/apm32/apm32f407ig-minibroard/board/linker_scripts/link.lds
index 88364839a9..c748aece1e 100644
--- a/bsp/apm32/apm32f407ig-minibroard/board/linker_scripts/link.lds
+++ b/bsp/apm32/apm32f407ig-minibroard/board/linker_scripts/link.lds
@@ -77,7 +77,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -98,7 +98,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/at32/at32f403a-start/board/linker_scripts/link.icf b/bsp/at32/at32f403a-start/board/linker_scripts/link.icf
index 65c2bfc8b7..00f54e12f8 100644
--- a/bsp/at32/at32f403a-start/board/linker_scripts/link.icf
+++ b/bsp/at32/at32f403a-start/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/at32/at32f403a-start/board/linker_scripts/link.lds b/bsp/at32/at32f403a-start/board/linker_scripts/link.lds
index 27269dd77e..cdf8ad6390 100644
--- a/bsp/at32/at32f403a-start/board/linker_scripts/link.lds
+++ b/bsp/at32/at32f403a-start/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/at32/at32f407-start/board/linker_scripts/link.icf b/bsp/at32/at32f407-start/board/linker_scripts/link.icf
index 65c2bfc8b7..00f54e12f8 100644
--- a/bsp/at32/at32f407-start/board/linker_scripts/link.icf
+++ b/bsp/at32/at32f407-start/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/at32/at32f407-start/board/linker_scripts/link.lds b/bsp/at32/at32f407-start/board/linker_scripts/link.lds
index 27269dd77e..cdf8ad6390 100644
--- a/bsp/at32/at32f407-start/board/linker_scripts/link.lds
+++ b/bsp/at32/at32f407-start/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/at32/at32f413-start/board/linker_scripts/link.icf b/bsp/at32/at32f413-start/board/linker_scripts/link.icf
index e4ea2b34d4..4435360fce 100644
--- a/bsp/at32/at32f413-start/board/linker_scripts/link.icf
+++ b/bsp/at32/at32f413-start/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/at32/at32f413-start/board/linker_scripts/link.lds b/bsp/at32/at32f413-start/board/linker_scripts/link.lds
index 3d755e4b43..c9241466e6 100644
--- a/bsp/at32/at32f413-start/board/linker_scripts/link.lds
+++ b/bsp/at32/at32f413-start/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/at32/at32f415-start/board/linker_scripts/link.icf b/bsp/at32/at32f415-start/board/linker_scripts/link.icf
index e4ea2b34d4..4435360fce 100644
--- a/bsp/at32/at32f415-start/board/linker_scripts/link.icf
+++ b/bsp/at32/at32f415-start/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/at32/at32f415-start/board/linker_scripts/link.lds b/bsp/at32/at32f415-start/board/linker_scripts/link.lds
index 3d755e4b43..c9241466e6 100644
--- a/bsp/at32/at32f415-start/board/linker_scripts/link.lds
+++ b/bsp/at32/at32f415-start/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/at32/at32f435-start/board/linker_scripts/link.icf b/bsp/at32/at32f435-start/board/linker_scripts/link.icf
index 5db573c108..03e77791cf 100644
--- a/bsp/at32/at32f435-start/board/linker_scripts/link.icf
+++ b/bsp/at32/at32f435-start/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/at32/at32f435-start/board/linker_scripts/link.lds b/bsp/at32/at32f435-start/board/linker_scripts/link.lds
index 4fb708f97a..e1780c00f4 100644
--- a/bsp/at32/at32f435-start/board/linker_scripts/link.lds
+++ b/bsp/at32/at32f435-start/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/at32/at32f437-start/board/linker_scripts/link.icf b/bsp/at32/at32f437-start/board/linker_scripts/link.icf
index 5db573c108..03e77791cf 100644
--- a/bsp/at32/at32f437-start/board/linker_scripts/link.icf
+++ b/bsp/at32/at32f437-start/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/at32/at32f437-start/board/linker_scripts/link.lds b/bsp/at32/at32f437-start/board/linker_scripts/link.lds
index 4fb708f97a..e1780c00f4 100644
--- a/bsp/at32/at32f437-start/board/linker_scripts/link.lds
+++ b/bsp/at32/at32f437-start/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf
index 5c133472cb..71df0ba7c2 100644
--- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf
+++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf
index 4b5ba6a97b..8a228f4a4c 100644
--- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf
+++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf
index 97734051a2..af77afd570 100644
--- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf
+++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf
index 5c133472cb..71df0ba7c2 100644
--- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf
+++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf
index 4b5ba6a97b..8a228f4a4c 100644
--- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf
+++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xG.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xG.icf
index 97734051a2..af77afd570 100644
--- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xG.icf
+++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xG.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413x8.icf b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413x8.icf
index cd94ed669e..57b2d0d9bd 100644
--- a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413x8.icf
+++ b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413x8.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xB.icf b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xB.icf
index 912235b9c0..8771dcbc34 100644
--- a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xB.icf
+++ b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xB.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xC.icf b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xC.icf
index 0f25e92744..b35733b786 100644
--- a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xC.icf
+++ b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xC.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415x8.icf b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415x8.icf
index cd94ed669e..57b2d0d9bd 100644
--- a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415x8.icf
+++ b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415x8.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xB.icf b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xB.icf
index 912235b9c0..8771dcbc34 100644
--- a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xB.icf
+++ b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xB.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xC.icf b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xC.icf
index 0f25e92744..b35733b786 100644
--- a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xC.icf
+++ b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xC.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xC.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xC.icf
index e9b6bd1a08..72cf92a0d6 100644
--- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xC.icf
+++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xC.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xG.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xG.icf
index 690530ac82..f70f3d762f 100644
--- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xG.icf
+++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xG.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xM.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xM.icf
index 398099a3df..2da95a07e0 100644
--- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xM.icf
+++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xM.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xC.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xC.icf
index e9b6bd1a08..72cf92a0d6 100644
--- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xC.icf
+++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xC.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xG.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xG.icf
index 690530ac82..f70f3d762f 100644
--- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xG.icf
+++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xG.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xM.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xM.icf
index 398099a3df..2da95a07e0 100644
--- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xM.icf
+++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xM.icf
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/avr32uc3b0/avr32elf_uc3b0256.lds b/bsp/avr32uc3b0/avr32elf_uc3b0256.lds
index 3f4ff5705a..ee86add7a9 100644
--- a/bsp/avr32uc3b0/avr32elf_uc3b0256.lds
+++ b/bsp/avr32uc3b0/avr32elf_uc3b0256.lds
@@ -1,6 +1,6 @@
/* Default linker script, for normal executables */
OUTPUT_FORMAT("elf32-avr32", "elf32-avr32",
- "elf32-avr32")
+ "elf32-avr32")
OUTPUT_ARCH(avr32:uc)
ENTRY(_start)
SEARCH_DIR("/home/mingwbuild/mingwavr32/avr32/lib");
@@ -37,10 +37,10 @@ SECTIONS
.rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH
- .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH
- .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH
- .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH
- .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH
+ .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH
+ .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH
+ .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH
+ .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH
.rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH
.rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH
.rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH
@@ -85,15 +85,15 @@ SECTIONS
.eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH
.gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH
- .dalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH
+ .dalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH
PROVIDE (_data = ORIGIN(CPUSRAM));
. = ORIGIN(CPUSRAM);
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH
.gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH
/* Thread Local Storage sections */
- .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH
- .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM
+ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH
+ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM
/* Ensure the __preinit_array_start label is properly aligned. We
could instead move the label definition inside the section, but
the linker would then create the section even if it turns out to
@@ -145,7 +145,7 @@ SECTIONS
SORT(CONSTRUCTORS)
} >CPUSRAM AT>FLASH
.data1 : { *(.data1) } >CPUSRAM AT>FLASH
- .balign : { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH
+ .balign : { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
diff --git a/bsp/beaglebone/beaglebone_ram.icf b/bsp/beaglebone/beaglebone_ram.icf
index dc894bc69f..d79a7691f7 100644
--- a/bsp/beaglebone/beaglebone_ram.icf
+++ b/bsp/beaglebone/beaglebone_ram.icf
@@ -42,4 +42,4 @@ place at address mem :__ICFEDIT_intvec_start__ {readonly section .intvec};
place in ROM_region { readonly, block RTT_INIT_FUNC };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
- block UND_STACK, block ABT_STACK, block HEAP };
\ No newline at end of file
+ block UND_STACK, block ABT_STACK, block HEAP };
diff --git a/bsp/beaglebone/beaglebone_ram.lds b/bsp/beaglebone/beaglebone_ram.lds
index 5847cb08dd..e5c76f420c 100644
--- a/bsp/beaglebone/beaglebone_ram.lds
+++ b/bsp/beaglebone/beaglebone_ram.lds
@@ -20,7 +20,7 @@ SECTIONS
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
- . = ALIGN(4);
+ . = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
diff --git a/bsp/bl808/m0/link_stacksize.lds b/bsp/bl808/m0/link_stacksize.lds
index 1dd893422c..28438c7da1 100644
--- a/bsp/bl808/m0/link_stacksize.lds
+++ b/bsp/bl808/m0/link_stacksize.lds
@@ -1 +1 @@
-__STACKSIZE__ = 4096;
\ No newline at end of file
+__STACKSIZE__ = 4096;
diff --git a/bsp/bm3803/bm3803.lds b/bsp/bm3803/bm3803.lds
index e8984325c1..f7bce59089 100644
--- a/bsp/bm3803/bm3803.lds
+++ b/bsp/bm3803/bm3803.lds
@@ -19,7 +19,7 @@ SECTIONS
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
- . = ALIGN(4);
+ . = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
diff --git a/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf b/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf
index d8055f6f83..954163a26a 100644
--- a/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf
+++ b/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf
@@ -26,9 +26,9 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, last block HEAP };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, last block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/essemi/es32f369x/drivers/linker_scripts/link.icf b/bsp/essemi/es32f369x/drivers/linker_scripts/link.icf
index 34d8124773..eb0c0f28dc 100644
--- a/bsp/essemi/es32f369x/drivers/linker_scripts/link.icf
+++ b/bsp/essemi/es32f369x/drivers/linker_scripts/link.icf
@@ -26,9 +26,9 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, last block HEAP };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, last block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/essemi/es32f369x/drivers/linker_scripts/link.lds b/bsp/essemi/es32f369x/drivers/linker_scripts/link.lds
index 6843e2a218..44efde1e90 100644
--- a/bsp/essemi/es32f369x/drivers/linker_scripts/link.lds
+++ b/bsp/essemi/es32f369x/drivers/linker_scripts/link.lds
@@ -104,7 +104,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -127,7 +127,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/frdm-k64f/MK64F.sct b/bsp/frdm-k64f/MK64F.sct
index 4c91774b2d..75920a0cd6 100644
--- a/bsp/frdm-k64f/MK64F.sct
+++ b/bsp/frdm-k64f/MK64F.sct
@@ -1,14 +1,14 @@
-
-LR_IROM1 0x00000000 0x100000 { ; load region size_region (1000k)
- ER_IROM1 0x00000000 0x100000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
- ; 0x40000 - 0x198 = 0x3FE68
- RW_IRAM2 0x20000000 0x30000 {
- .ANY (+RW +ZI)
- }
-}
-
+
+LR_IROM1 0x00000000 0x100000 { ; load region size_region (1000k)
+ ER_IROM1 0x00000000 0x100000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
+ ; 0x40000 - 0x198 = 0x3FE68
+ RW_IRAM2 0x20000000 0x30000 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.icf b/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.icf
index 6d0177d0bb..7f352fc72a 100644
--- a/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.icf
+++ b/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.lds b/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.lds
index bb905d06b1..2292c96e96 100644
--- a/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.lds
+++ b/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf b/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf
index 66b859d099..26e670978f 100644
--- a/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf
+++ b/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/gd32/arm/gd32103c-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32103c-eval/board/linker_scripts/link.icf
index c1b7bfa182..6edb095a6d 100644
--- a/bsp/gd32/arm/gd32103c-eval/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32103c-eval/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32105c-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32105c-eval/board/linker_scripts/link.icf
index 283881a728..ce253de238 100644
--- a/bsp/gd32/arm/gd32105c-eval/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32105c-eval/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32105r-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32105r-start/board/linker_scripts/link.icf
index 283881a728..ce253de238 100644
--- a/bsp/gd32/arm/gd32105r-start/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32105r-start/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32107c-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32107c-eval/board/linker_scripts/link.icf
index 283881a728..ce253de238 100644
--- a/bsp/gd32/arm/gd32107c-eval/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32107c-eval/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32205r-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32205r-start/board/linker_scripts/link.icf
index ac4747c3cb..5bdf74aa6b 100644
--- a/bsp/gd32/arm/gd32205r-start/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32205r-start/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32207i-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32207i-eval/board/linker_scripts/link.icf
index be287f2c06..7b6d8150f0 100644
--- a/bsp/gd32/arm/gd32207i-eval/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32207i-eval/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32303c-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32303c-start/board/linker_scripts/link.icf
index 4dd2a2010e..654022e767 100644
--- a/bsp/gd32/arm/gd32303c-start/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32303c-start/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32303e-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32303e-eval/board/linker_scripts/link.icf
index f68fd14425..2b52bbb04c 100644
--- a/bsp/gd32/arm/gd32303e-eval/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32303e-eval/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32305r-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32305r-start/board/linker_scripts/link.icf
index 283881a728..ce253de238 100644
--- a/bsp/gd32/arm/gd32305r-start/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32305r-start/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32307e-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32307e-start/board/linker_scripts/link.icf
index 498c2369e2..53523dab38 100644
--- a/bsp/gd32/arm/gd32307e-start/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32307e-start/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32407v-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32407v-start/board/linker_scripts/link.icf
index 2dd20cf186..aab8be6e69 100644
--- a/bsp/gd32/arm/gd32407v-start/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32407v-start/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/arm/gd32450z-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32450z-eval/board/linker_scripts/link.icf
index c32661c11b..f6f2f03387 100644
--- a/bsp/gd32/arm/gd32450z-eval/board/linker_scripts/link.icf
+++ b/bsp/gd32/arm/gd32450z-eval/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x4.lds b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x4.lds
index fe1d0befb6..ab9f7e99b8 100644
--- a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x4.lds
+++ b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x4.lds
@@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
-{
- /* Run in FLASH */
- flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k
- ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k
-
- /* Run in RAM */
-/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k
- ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K
-*/
+{
+ /* Run in FLASH */
+ flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k
+ ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k
+
+ /* Run in RAM */
+/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k
+ ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K
+*/
}
@@ -23,18 +23,18 @@ SECTIONS
.init :
{
KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash
+ } >flash AT>flash
.ilalign :
{
. = ALIGN(4);
PROVIDE( _ilm_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.ialign :
{
PROVIDE( _ilm = . );
- } >flash AT>flash
+ } >flash AT>flash
.text :
{
@@ -68,12 +68,12 @@ SECTIONS
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
- } >flash AT>flash
+ } >flash AT>flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
@@ -87,7 +87,7 @@ SECTIONS
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.init_array :
{
@@ -95,7 +95,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.fini_array :
{
@@ -103,7 +103,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.ctors :
{
@@ -125,7 +125,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
- } >flash AT>flash
+ } >flash AT>flash
.dtors :
{
@@ -134,7 +134,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
PROVIDE( _eilm = . );
@@ -143,24 +143,24 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
- } >ram AT>flash
-
-
+ } >ram AT>flash
+
+
.data :
{
- *(.rdata)
-
+ *(.rdata)
+
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800);
+ PROVIDE( __global_pointer$ = . + 0x800);
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
@@ -169,7 +169,7 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
- } >ram AT>flash
+ } >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
@@ -185,7 +185,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
- } >ram AT>ram
+ } >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . ); /*0X2000,0340*/
@@ -193,8 +193,8 @@ SECTIONS
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram
}
diff --git a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x6.lds b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x6.lds
index 4aea1558d2..b8e0bda6cc 100644
--- a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x6.lds
+++ b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x6.lds
@@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
-{
- /* Run in FLASH */
- flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k
- ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k
-
- /* Run in RAM */
-/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k
- ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K
-*/
+{
+ /* Run in FLASH */
+ flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k
+ ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k
+
+ /* Run in RAM */
+/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k
+ ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K
+*/
}
@@ -23,22 +23,22 @@ SECTIONS
.init :
{
KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash
+ } >flash AT>flash
.ilalign :
{
. = ALIGN(4);
PROVIDE( _ilm_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.ialign :
{
PROVIDE( _ilm = . );
- } >flash AT>flash
+ } >flash AT>flash
.text :
{
- *(.rodata .rodata.*)
+ *(.rodata .rodata.*)
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
@@ -68,12 +68,12 @@ SECTIONS
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
- } >flash AT>flash
+ } >flash AT>flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
@@ -87,7 +87,7 @@ SECTIONS
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.init_array :
{
@@ -95,7 +95,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.fini_array :
{
@@ -103,7 +103,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.ctors :
{
@@ -125,7 +125,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
- } >flash AT>flash
+ } >flash AT>flash
.dtors :
{
@@ -134,7 +134,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
PROVIDE( _eilm = . );
@@ -143,24 +143,24 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
- } >ram AT>flash
-
-
+ } >ram AT>flash
+
+
.data :
{
- *(.rdata)
-
+ *(.rdata)
+
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800);
+ PROVIDE( __global_pointer$ = . + 0x800);
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
@@ -169,7 +169,7 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
- } >ram AT>flash
+ } >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
@@ -185,7 +185,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
- } >ram AT>ram
+ } >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . ); /*0X2000,0340*/
@@ -193,8 +193,8 @@ SECTIONS
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram
}
diff --git a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x8.lds b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x8.lds
index daa0369232..6dd171378e 100644
--- a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x8.lds
+++ b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x8.lds
@@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
-{
- /* Run in FLASH */
- flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
- ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k
-
- /* Run in RAM */
-/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k
- ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K
-*/
+{
+ /* Run in FLASH */
+ flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
+ ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k
+
+ /* Run in RAM */
+/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k
+ ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K
+*/
}
@@ -23,22 +23,22 @@ SECTIONS
.init :
{
KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash
+ } >flash AT>flash
.ilalign :
{
. = ALIGN(4);
PROVIDE( _ilm_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.ialign :
{
PROVIDE( _ilm = . );
- } >flash AT>flash
+ } >flash AT>flash
.text :
{
- *(.rodata .rodata.*)
+ *(.rodata .rodata.*)
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
@@ -68,12 +68,12 @@ SECTIONS
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
- } >flash AT>flash
+ } >flash AT>flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
@@ -87,7 +87,7 @@ SECTIONS
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.init_array :
{
@@ -95,7 +95,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.fini_array :
{
@@ -103,7 +103,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.ctors :
{
@@ -125,7 +125,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
- } >flash AT>flash
+ } >flash AT>flash
.dtors :
{
@@ -134,7 +134,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
PROVIDE( _eilm = . );
@@ -143,24 +143,24 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
- } >ram AT>flash
-
-
+ } >ram AT>flash
+
+
.data :
{
- *(.rdata)
-
+ *(.rdata)
+
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800);
+ PROVIDE( __global_pointer$ = . + 0x800);
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
@@ -169,7 +169,7 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
- } >ram AT>flash
+ } >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
@@ -185,7 +185,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
- } >ram AT>ram
+ } >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . ); /*0X2000,0340*/
@@ -193,8 +193,8 @@ SECTIONS
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram
}
diff --git a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103xB.lds b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103xB.lds
index 7651c00255..00d45a99d8 100644
--- a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103xB.lds
+++ b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103xB.lds
@@ -3,12 +3,12 @@ OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
-{
- /* Run in FLASH */
+{
+ /* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
- ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
+ ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
- /* Run in RAM */
+ /* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
*/
@@ -23,22 +23,22 @@ SECTIONS
.init :
{
KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash
+ } >flash AT>flash
.ilalign :
{
. = ALIGN(4);
PROVIDE( _ilm_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.ialign :
{
PROVIDE( _ilm = . );
- } >flash AT>flash
+ } >flash AT>flash
.text :
{
- *(.rodata .rodata.*)
+ *(.rodata .rodata.*)
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
@@ -67,12 +67,12 @@ SECTIONS
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
- } >flash AT>flash
+ } >flash AT>flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
@@ -86,7 +86,7 @@ SECTIONS
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.init_array :
{
@@ -94,7 +94,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.fini_array :
{
@@ -102,7 +102,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.ctors :
{
@@ -124,7 +124,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
- } >flash AT>flash
+ } >flash AT>flash
.dtors :
{
@@ -133,7 +133,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
PROVIDE( _eilm = . );
@@ -142,24 +142,24 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
- } >ram AT>flash
-
-
+ } >ram AT>flash
+
+
.data :
{
- *(.rdata)
-
+ *(.rdata)
+
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800);
+ PROVIDE( __global_pointer$ = . + 0x800);
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
@@ -168,7 +168,7 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
- } >ram AT>flash
+ } >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
@@ -184,7 +184,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
- } >ram AT>ram
+ } >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . ); /*0X2000,0340*/
@@ -192,8 +192,8 @@ SECTIONS
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram
}
diff --git a/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf b/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf
index d6665c3649..27790e4197 100644
--- a/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf
+++ b/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf b/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf
index d6665c3649..27790e4197 100644
--- a/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf
+++ b/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32303e-eval/gd32_rom.icf b/bsp/gd32303e-eval/gd32_rom.icf
index d6665c3649..27790e4197 100644
--- a/bsp/gd32303e-eval/gd32_rom.icf
+++ b/bsp/gd32303e-eval/gd32_rom.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32350r-eval/gd32_rom.icf b/bsp/gd32350r-eval/gd32_rom.icf
index 1741be6a71..80461d6dfa 100644
--- a/bsp/gd32350r-eval/gd32_rom.icf
+++ b/bsp/gd32350r-eval/gd32_rom.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32450z-eval/gd32_rom.icf b/bsp/gd32450z-eval/gd32_rom.icf
index 1741be6a71..80461d6dfa 100644
--- a/bsp/gd32450z-eval/gd32_rom.icf
+++ b/bsp/gd32450z-eval/gd32_rom.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32e230k-start/gd32_rom.icf b/bsp/gd32e230k-start/gd32_rom.icf
index d6665c3649..27790e4197 100644
--- a/bsp/gd32e230k-start/gd32_rom.icf
+++ b/bsp/gd32e230k-start/gd32_rom.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds
index fc3d331ede..709ed76361 100644
--- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds
@@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
-{
- /* Run in FLASH */
- flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k
- ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k
-
- /* Run in RAM */
-/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k
- ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K
-*/
+{
+ /* Run in FLASH */
+ flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k
+ ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k
+
+ /* Run in RAM */
+/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k
+ ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K
+*/
}
@@ -23,18 +23,18 @@ SECTIONS
.init :
{
KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash
+ } >flash AT>flash
.ilalign :
{
. = ALIGN(4);
PROVIDE( _ilm_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.ialign :
{
PROVIDE( _ilm = . );
- } >flash AT>flash
+ } >flash AT>flash
.text :
{
@@ -43,12 +43,12 @@ SECTIONS
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
- } >flash AT>flash
+ } >flash AT>flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
@@ -62,7 +62,7 @@ SECTIONS
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.init_array :
{
@@ -70,7 +70,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.fini_array :
{
@@ -78,7 +78,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.ctors :
{
@@ -100,7 +100,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
- } >flash AT>flash
+ } >flash AT>flash
.dtors :
{
@@ -109,7 +109,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
PROVIDE( _eilm = . );
@@ -118,24 +118,24 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
- } >ram AT>flash
-
-
+ } >ram AT>flash
+
+
.data :
{
- *(.rdata)
-
+ *(.rdata)
+
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800);
+ PROVIDE( __global_pointer$ = . + 0x800);
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
@@ -144,7 +144,7 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
- } >ram AT>flash
+ } >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
@@ -160,7 +160,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
- } >ram AT>ram
+ } >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . ); /*0X2000,0340*/
@@ -168,8 +168,8 @@ SECTIONS
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram
}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds
index 3cfe58ac5f..6d2e894d28 100644
--- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds
@@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
-{
- /* Run in FLASH */
- flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k
- ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k
-
- /* Run in RAM */
-/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k
- ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K
-*/
+{
+ /* Run in FLASH */
+ flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k
+ ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k
+
+ /* Run in RAM */
+/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k
+ ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K
+*/
}
@@ -23,32 +23,32 @@ SECTIONS
.init :
{
KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash
+ } >flash AT>flash
.ilalign :
{
. = ALIGN(4);
PROVIDE( _ilm_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.ialign :
{
PROVIDE( _ilm = . );
- } >flash AT>flash
+ } >flash AT>flash
.text :
{
- *(.rodata .rodata.*)
+ *(.rodata .rodata.*)
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
- } >flash AT>flash
+ } >flash AT>flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
@@ -62,7 +62,7 @@ SECTIONS
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.init_array :
{
@@ -70,7 +70,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.fini_array :
{
@@ -78,7 +78,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.ctors :
{
@@ -100,7 +100,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
- } >flash AT>flash
+ } >flash AT>flash
.dtors :
{
@@ -109,7 +109,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
PROVIDE( _eilm = . );
@@ -118,24 +118,24 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
- } >ram AT>flash
-
-
+ } >ram AT>flash
+
+
.data :
{
- *(.rdata)
-
+ *(.rdata)
+
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800);
+ PROVIDE( __global_pointer$ = . + 0x800);
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
@@ -144,7 +144,7 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
- } >ram AT>flash
+ } >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
@@ -160,7 +160,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
- } >ram AT>ram
+ } >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . ); /*0X2000,0340*/
@@ -168,8 +168,8 @@ SECTIONS
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram
}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds
index a10769dc86..36563311b6 100644
--- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds
@@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
-{
- /* Run in FLASH */
- flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
- ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k
-
- /* Run in RAM */
-/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k
- ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K
-*/
+{
+ /* Run in FLASH */
+ flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
+ ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k
+
+ /* Run in RAM */
+/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k
+ ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K
+*/
}
@@ -23,32 +23,32 @@ SECTIONS
.init :
{
KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash
+ } >flash AT>flash
.ilalign :
{
. = ALIGN(4);
PROVIDE( _ilm_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.ialign :
{
PROVIDE( _ilm = . );
- } >flash AT>flash
+ } >flash AT>flash
.text :
{
- *(.rodata .rodata.*)
+ *(.rodata .rodata.*)
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
- } >flash AT>flash
+ } >flash AT>flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
@@ -62,7 +62,7 @@ SECTIONS
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.init_array :
{
@@ -70,7 +70,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.fini_array :
{
@@ -78,7 +78,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.ctors :
{
@@ -100,7 +100,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
- } >flash AT>flash
+ } >flash AT>flash
.dtors :
{
@@ -109,7 +109,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
PROVIDE( _eilm = . );
@@ -118,24 +118,24 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
- } >ram AT>flash
-
-
+ } >ram AT>flash
+
+
.data :
{
- *(.rdata)
-
+ *(.rdata)
+
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800);
+ PROVIDE( __global_pointer$ = . + 0x800);
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
@@ -144,7 +144,7 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
- } >ram AT>flash
+ } >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
@@ -160,7 +160,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
- } >ram AT>ram
+ } >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . ); /*0X2000,0340*/
@@ -168,8 +168,8 @@ SECTIONS
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram
}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds
index 45b93cf8eb..3ea227b113 100644
--- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds
@@ -3,12 +3,12 @@ OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
-{
- /* Run in FLASH */
+{
+ /* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
- ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
+ ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
- /* Run in RAM */
+ /* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
*/
@@ -23,27 +23,27 @@ SECTIONS
.init :
{
KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash
+ } >flash AT>flash
.ilalign :
{
. = ALIGN(4);
PROVIDE( _ilm_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.ialign :
{
PROVIDE( _ilm = . );
- } >flash AT>flash
+ } >flash AT>flash
.text :
{
- *(.rodata .rodata.*)
+ *(.rodata .rodata.*)
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
-
+
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
@@ -54,7 +54,7 @@ SECTIONS
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
-
+
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
@@ -67,12 +67,12 @@ SECTIONS
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
- } >flash AT>flash
+ } >flash AT>flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
@@ -86,7 +86,7 @@ SECTIONS
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.init_array :
{
@@ -94,7 +94,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.fini_array :
{
@@ -102,7 +102,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.ctors :
{
@@ -124,7 +124,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
- } >flash AT>flash
+ } >flash AT>flash
.dtors :
{
@@ -133,7 +133,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
PROVIDE( _eilm = . );
@@ -142,24 +142,24 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
- } >ram AT>flash
-
-
+ } >ram AT>flash
+
+
.data :
{
- *(.rdata)
-
+ *(.rdata)
+
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800);
+ PROVIDE( __global_pointer$ = . + 0x800);
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
@@ -168,7 +168,7 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
- } >ram AT>flash
+ } >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
@@ -184,7 +184,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
- } >ram AT>ram
+ } >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . ); /*0X2000,0340*/
@@ -192,8 +192,8 @@ SECTIONS
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram
}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds
index f273c1930d..cfb0b88107 100644
--- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds
@@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
-{
- /* Run in FLASH */
- flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
- ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
-
- /* Run in RAM */
-/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
- ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
-*/
+{
+ /* Run in FLASH */
+ flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
+ ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
+
+ /* Run in RAM */
+/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
+ ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
+*/
}
@@ -23,39 +23,39 @@ SECTIONS
.init :
{
KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash
+ } >flash AT>flash
.ilalign :
{
. = ALIGN(4);
PROVIDE( _ilm_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.ialign :
{
PROVIDE( _ilm = . );
- } >flash AT>flash
+ } >flash AT>flash
.PrgData ALIGN(0x08004000,4) : AT(ALIGN(0x08004000,4))
{
- KEEP(*(.PrgData))
+ KEEP(*(.PrgData))
}
-
+
.text :
{
- *(.rodata .rodata.*)
+ *(.rodata .rodata.*)
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
*(.sdata2 .sdata2. *)
- } >flash AT>flash
+ } >flash AT>flash
+
-
.fini :
{
KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
@@ -69,7 +69,7 @@ SECTIONS
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.init_array :
{
@@ -77,7 +77,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.fini_array :
{
@@ -85,7 +85,7 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash
+ } >flash AT>flash
.ctors :
{
@@ -107,7 +107,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
- } >flash AT>flash
+ } >flash AT>flash
.dtors :
{
@@ -116,7 +116,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
- } >flash AT>flash
+ } >flash AT>flash
. = ALIGN(4);
PROVIDE( _eilm = . );
@@ -125,24 +125,24 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
- } >flash AT>flash
+ } >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
- } >ram AT>flash
-
-
+ } >ram AT>flash
+
+
.data :
{
- *(.rdata)
-
+ *(.rdata)
+
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800);
+ PROVIDE( __global_pointer$ = . + 0x800);
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
@@ -151,7 +151,7 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
- } >ram AT>flash
+ } >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
@@ -167,7 +167,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
- } >ram AT>ram
+ } >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . ); /*0X2000,0340*/
@@ -175,8 +175,8 @@ SECTIONS
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram
}
diff --git a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf
index 3ac4e24e18..315cad68eb 100644
--- a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf
+++ b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf
@@ -55,4 +55,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf
index 3ee43c73cd..d4ab64ed60 100644
--- a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf
+++ b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf
@@ -47,4 +47,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf
index 5f0edccc15..0ad9e89f73 100644
--- a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf
+++ b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf
@@ -47,4 +47,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf
index dcc0be6376..502ad34f41 100644
--- a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf
+++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf
@@ -53,4 +53,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf
index e938594387..41073ed6b2 100644
--- a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf
+++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf
@@ -47,4 +47,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf
index 35a29c5fa1..8d2005dff4 100644
--- a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf
+++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf
@@ -47,4 +47,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf
index 73c070bfb5..c1553e99ec 100644
--- a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf
+++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf
@@ -48,4 +48,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf
index 159df7daa4..23fbf9cbbf 100644
--- a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf
+++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf
@@ -50,4 +50,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in QSPI_region { readonly section .ex_rom };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf
index 82734efbd6..4dec7d352b 100644
--- a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf
+++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf
@@ -50,4 +50,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in QSPI_region { readonly section .ex_rom };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf
index 73c070bfb5..c1553e99ec 100644
--- a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf
+++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf
@@ -48,4 +48,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf
index 735d43311f..393abcb073 100644
--- a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf
+++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf
@@ -48,4 +48,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf
index b47254e04e..f653427843 100644
--- a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf
+++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf
@@ -48,4 +48,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/hc32l136/board/linker_scripts/link.icf b/bsp/hc32l136/board/linker_scripts/link.icf
index 719e8b673c..6907c5dc5b 100644
--- a/bsp/hc32l136/board/linker_scripts/link.icf
+++ b/bsp/hc32l136/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/hc32l196/board/linker_scripts/link.lds b/bsp/hc32l196/board/linker_scripts/link.lds
index fc5b6197af..3b5c615c7a 100644
--- a/bsp/hc32l196/board/linker_scripts/link.lds
+++ b/bsp/hc32l196/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds
index 90415e319a..3cd3180273 100644
--- a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds
+++ b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds
@@ -30,7 +30,7 @@ SECTIONS
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
-
+
/* section information for finsh shell */
. = ALIGN(4);
diff --git a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds
index 54c102641e..c571a0f876 100644
--- a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds
+++ b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds
@@ -1 +1 @@
-../coreplexip-e31-arty/flash.lds
\ No newline at end of file
+../coreplexip-e31-arty/flash.lds
diff --git a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds
index 7fbe10a3ea..f7f33b8de2 100644
--- a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds
+++ b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds
@@ -1 +1 @@
-../coreplexip-e31-arty/scratchpad.lds
\ No newline at end of file
+../coreplexip-e31-arty/scratchpad.lds
diff --git a/bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds b/bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds
index 6441ce598f..9661121ef7 100644
--- a/bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds
+++ b/bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds
@@ -1 +1 @@
-../freedom-e300-hifive1/flash.lds
\ No newline at end of file
+../freedom-e300-hifive1/flash.lds
diff --git a/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.icf b/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.icf
index a40b9d422b..a9511546b7 100644
--- a/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.icf
+++ b/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.lds b/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.lds
index 90a0df7e47..88f67766bd 100644
--- a/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.lds
+++ b/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf
index 1e87e297e2..846a935841 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf
@@ -1,89 +1,89 @@
-/*
- * Copyright 2022 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-
-/* Regions */
-define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */
-define region ILM = [from 0x0 size 128k]; /* ILM */
-define region DLM = [from 0x80000 size 128k]; /* DLM */
-define region AXI_SRAM = [from 0x1080000 size 256k];
-define region SDRAM = [from 0x40000000 size _extram_size];
-define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k];
-
-/* Blocks */
-define block vectors { section .isr_vector, section .vector_table };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-define block framebuffer with alignment = 8 { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-
-/* Symbols */
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-
-define exported symbol _stack_safe = end of block safe_stack + 1;
-define exported symbol _stack = end of block stack + 1;
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-place at start of XPI0 with fixed order { symbol _start};
-
-place at start of ILM_SLV with fixed order { block vectors };
-initialize by copy { block vectors };
-
-place in XPI0 with minimum size order {
- block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-place in ILM {
- section .fast, section .fast.*, // "ramfunc" section
- };
-
-place in DLM with auto order {
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-
-place in AXI_SRAM { block framebuffer };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in AXI_SRAM { block heap }; // Heap reserved block
-place at end of AXI_SRAM { block stack }; // Stack reserved block at the end
-place at end of DLM { block safe_stack }; // Safe stack reserved block at the end
+/*
+ * Copyright 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+
+/* Regions */
+define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */
+define region ILM = [from 0x0 size 128k]; /* ILM */
+define region DLM = [from 0x80000 size 128k]; /* DLM */
+define region AXI_SRAM = [from 0x1080000 size 256k];
+define region SDRAM = [from 0x40000000 size _extram_size];
+define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k];
+
+/* Blocks */
+define block vectors { section .isr_vector, section .vector_table };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+define block framebuffer with alignment = 8 { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+
+/* Symbols */
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+
+define exported symbol _stack_safe = end of block safe_stack + 1;
+define exported symbol _stack = end of block stack + 1;
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+place at start of XPI0 with fixed order { symbol _start};
+
+place at start of ILM_SLV with fixed order { block vectors };
+initialize by copy { block vectors };
+
+place in XPI0 with minimum size order {
+ block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+place in ILM {
+ section .fast, section .fast.*, // "ramfunc" section
+ };
+
+place in DLM with auto order {
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+
+place in AXI_SRAM { block framebuffer };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in AXI_SRAM { block heap }; // Heap reserved block
+place at end of AXI_SRAM { block stack }; // Stack reserved block at the end
+place at end of DLM { block safe_stack }; // Safe stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf
index 75b1221ad9..e2e66adf50 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf
@@ -1,85 +1,85 @@
-/*
- * Copyright 2022 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000;
-
-/* Regions */
-define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH ];
-define region AXI_SRAM = [from 0x1040000 size 768K];
-define region SDRAM = [from 0x40000000 size _extram_size - 4M];
-define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M];
-
-/* Blocks */
-define block vectors with fixed order { section .vector_table, section .isr_vector };
-define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-define block framebuffer with alignment = 8 { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-
-/* Symbols */
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-
-define exported symbol _stack_safe = end of block safe_stack + 1;
-define exported symbol _stack = end of block stack + 1;
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-place at start of XPI0 with fixed order { section .uf2_signature };
-place in XPI0 with fixed order {symbol _start};
-keep { section .uf2_signature };
-
-place at start of AXI_SRAM with fixed order { block vectors, block vectors_s };
-initialize by copy { block vectors, block vectors_s };
-
-place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-
-place in SDRAM { block framebuffer };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in SDRAM { block heap }; // Heap reserved block
-place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end
+/*
+ * Copyright 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000;
+
+/* Regions */
+define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH ];
+define region AXI_SRAM = [from 0x1040000 size 768K];
+define region SDRAM = [from 0x40000000 size _extram_size - 4M];
+define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M];
+
+/* Blocks */
+define block vectors with fixed order { section .vector_table, section .isr_vector };
+define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+define block framebuffer with alignment = 8 { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+
+/* Symbols */
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+
+define exported symbol _stack_safe = end of block safe_stack + 1;
+define exported symbol _stack = end of block stack + 1;
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+place at start of XPI0 with fixed order { section .uf2_signature };
+place in XPI0 with fixed order {symbol _start};
+keep { section .uf2_signature };
+
+place at start of AXI_SRAM with fixed order { block vectors, block vectors_s };
+initialize by copy { block vectors, block vectors_s };
+
+place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+
+place in SDRAM { block framebuffer };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in SDRAM { block heap }; // Heap reserved block
+place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf
index 3f5bc4fb56..99ca6bbe92 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf
@@ -1,98 +1,98 @@
-/*
- * Copyright 2022 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-
-/* Regions */
-define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ];
-define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ];
-define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */
-define region ILM = [from 0x0 size 256K];
-define region DLM = [from 0x80000 size 256K];
-define region AXI_SRAM = [from 0x1080000 size 512K];
-define region SDRAM = [from 0x40000000 size _extram_size - 4M];
-define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M];
-
-/* Blocks */
-define block vectors with fixed order { section .vector_table, section .isr_vector };
-define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-define block framebuffer with alignment = 8 { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-
-define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info };
-
-/* Symbols */
-define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION;
-define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER;
-define exported symbol __app_load_addr__ = start of region XPI0;
-define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
-define exported symbol __boot_header_length__ = size of block boot_header;
-define exported symbol __fw_size__ = 0x1000;
-
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-
-define exported symbol _stack_safe = end of block safe_stack + 1;
-define exported symbol _stack = end of block stack + 1;
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info };
-place in NOR_CFG_OPTION { section .nor_cfg_option };
-place in BOOT_HEADER with fixed order { block boot_header };
-place at start of XPI0 with fixed order { symbol _start};
-
-place at start of ILM with fixed order { block vectors, block vectors_s };
-initialize by copy { block vectors, block vectors_s };
-
-place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-place in ILM { section .fast, section .fast.* }; // "ramfunc" section
-place in AXI_SRAM with auto order { block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-
-place in SDRAM { block framebuffer };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in SDRAM { block heap }; // Heap reserved block
-place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end
+/*
+ * Copyright 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+
+/* Regions */
+define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ];
+define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ];
+define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */
+define region ILM = [from 0x0 size 256K];
+define region DLM = [from 0x80000 size 256K];
+define region AXI_SRAM = [from 0x1080000 size 512K];
+define region SDRAM = [from 0x40000000 size _extram_size - 4M];
+define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M];
+
+/* Blocks */
+define block vectors with fixed order { section .vector_table, section .isr_vector };
+define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+define block framebuffer with alignment = 8 { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+
+define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info };
+
+/* Symbols */
+define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION;
+define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER;
+define exported symbol __app_load_addr__ = start of region XPI0;
+define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+define exported symbol __boot_header_length__ = size of block boot_header;
+define exported symbol __fw_size__ = 0x1000;
+
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+
+define exported symbol _stack_safe = end of block safe_stack + 1;
+define exported symbol _stack = end of block stack + 1;
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info };
+place in NOR_CFG_OPTION { section .nor_cfg_option };
+place in BOOT_HEADER with fixed order { block boot_header };
+place at start of XPI0 with fixed order { symbol _start};
+
+place at start of ILM with fixed order { block vectors, block vectors_s };
+initialize by copy { block vectors, block vectors_s };
+
+place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+place in ILM { section .fast, section .fast.* }; // "ramfunc" section
+place in AXI_SRAM with auto order { block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+
+place in SDRAM { block framebuffer };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in SDRAM { block heap }; // Heap reserved block
+place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf
index 87188c823c..9e99e1e753 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf
@@ -1,87 +1,87 @@
-/*
- * Copyright 2022 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000;
-
-/* Regions */
-define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */
-define region ILM = [from 0 size 128k]; /* ILM slave */
-define region DLM = [from 0x80000 size 128k]; /* DLM */
-define region AXI_SRAM = [from 0x1080000 size 256k];
-define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k];
-
-/* Blocks */
-define block vectors with fixed order { section .vector_table, section .isr_vector };
-define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-define block framebuffer with alignment = 8 { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-
-/* Symbols */
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-
-define exported symbol _stack_safe = end of block safe_stack + 1;
-define exported symbol _stack = end of block stack + 1;
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-place at start of XPI0 with fixed order { section .uf2_signature };
-place in XPI0 with fixed order {symbol _start};
-keep { section .uf2_signature };
-
-place at start of ILM with fixed order { block vectors, block vectors_s };
-initialize by copy { block vectors, block vectors_s };
-
-place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-place in ILM { section .fast, section .fast.* }; // "ramfunc" section
-place in DLM with auto order {
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-
-place in AXI_SRAM { block framebuffer };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in AXI_SRAM { block heap }; // Heap reserved block
-place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end
+/*
+ * Copyright 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000;
+
+/* Regions */
+define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */
+define region ILM = [from 0 size 128k]; /* ILM slave */
+define region DLM = [from 0x80000 size 128k]; /* DLM */
+define region AXI_SRAM = [from 0x1080000 size 256k];
+define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k];
+
+/* Blocks */
+define block vectors with fixed order { section .vector_table, section .isr_vector };
+define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+define block framebuffer with alignment = 8 { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+
+/* Symbols */
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+
+define exported symbol _stack_safe = end of block safe_stack + 1;
+define exported symbol _stack = end of block stack + 1;
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+place at start of XPI0 with fixed order { section .uf2_signature };
+place in XPI0 with fixed order {symbol _start};
+keep { section .uf2_signature };
+
+place at start of ILM with fixed order { block vectors, block vectors_s };
+initialize by copy { block vectors, block vectors_s };
+
+place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+place in ILM { section .fast, section .fast.* }; // "ramfunc" section
+place in DLM with auto order {
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+
+place in AXI_SRAM { block framebuffer };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in AXI_SRAM { block heap }; // Heap reserved block
+place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf
index eee3e8a6c2..8ead4f2e24 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf
@@ -1,98 +1,98 @@
-/*
- * Copyright 2022 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-
-/* Regions */
-define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ];
-define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ];
-define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */
-define region ILM = [from 0 size 128k]; /* ILM */
-define region DLM = [from 0x80000 size 128k]; /* DLM */
-define region AXI_SRAM = [from 0x1080000 size 256k];
-define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k];
-
-/* Blocks */
-define block vectors with fixed order { section .vector_table, section .isr_vector };
-define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-define block framebuffer with alignment = 8 { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-
-define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info };
-
-/* Symbols */
-define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION;
-define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER;
-define exported symbol __app_load_addr__ = start of region XPI0;
-define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
-define exported symbol __boot_header_length__ = size of block boot_header;
-define exported symbol __fw_size__ = 0x1000;
-
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-
-define exported symbol _stack_safe = end of block safe_stack + 1;
-define exported symbol _stack = end of block stack + 1;
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info };
-place in NOR_CFG_OPTION { section .nor_cfg_option };
-place in BOOT_HEADER with fixed order { block boot_header };
-place at start of XPI0 with fixed order { symbol _start};
-
-place at start of ILM with fixed order { block vectors, block vectors_s };
-initialize by copy { block vectors, block vectors_s };
-
-place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-place in ILM { section .fast, section .fast.* }; // "ramfunc" section
-
-place in DLM with auto order { block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-
-place in AXI_SRAM { block framebuffer };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in AXI_SRAM { block heap }; // Heap reserved block
-place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end
+/*
+ * Copyright 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+
+/* Regions */
+define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ];
+define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ];
+define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */
+define region ILM = [from 0 size 128k]; /* ILM */
+define region DLM = [from 0x80000 size 128k]; /* DLM */
+define region AXI_SRAM = [from 0x1080000 size 256k];
+define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k];
+
+/* Blocks */
+define block vectors with fixed order { section .vector_table, section .isr_vector };
+define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+define block framebuffer with alignment = 8 { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+
+define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info };
+
+/* Symbols */
+define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION;
+define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER;
+define exported symbol __app_load_addr__ = start of region XPI0;
+define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+define exported symbol __boot_header_length__ = size of block boot_header;
+define exported symbol __fw_size__ = 0x1000;
+
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+
+define exported symbol _stack_safe = end of block safe_stack + 1;
+define exported symbol _stack = end of block stack + 1;
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info };
+place in NOR_CFG_OPTION { section .nor_cfg_option };
+place in BOOT_HEADER with fixed order { block boot_header };
+place at start of XPI0 with fixed order { symbol _start};
+
+place at start of ILM with fixed order { block vectors, block vectors_s };
+initialize by copy { block vectors, block vectors_s };
+
+place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+place in ILM { section .fast, section .fast.* }; // "ramfunc" section
+
+place in DLM with auto order { block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+
+place in AXI_SRAM { block framebuffer };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in AXI_SRAM { block heap }; // Heap reserved block
+place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf
index 94e0dae066..c618182147 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf
@@ -1,78 +1,78 @@
-/*
- * Copyright 2022 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-
-/* Regions */
-define region ILM = [from 0 size 128k]; /* ILM */
-define region RAM = [from 0x80000 size 128k]; /* DLM */
-define region AXI_SRAM = [from 0x1080000 size 256k];
-define region NONCACHEABLE_RAM = [from 0x10C0000 size 256K];
-
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-define exported symbol _stack = end of block stack + 1;
-define block safe_stack with size = 512, readwrite access {};
-define exported symbol _stack_safe = end of block safe_stack + 1;
-
-/* Blocks */
-define block vectors with fixed order { section .vector_table, section .isr_vector };
-define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-define block framebuffer { section .framebuffer };
-
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-place at start of ILM { symbol _start };
-place in ILM { block vectors, block vectors_s }; // Vector table section
-place in ILM with minimum size order { block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-/* Explicit placement in AXI_SRAM */
-place in AXI_SRAM { block framebuffer };
-
-place in RAM with auto order { section .fast, section .fast.*, // "ramfunc" section
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in RAM { block heap }; // Heap reserved block
-place at end of RAM { block stack, block safe_stack }; // Stack reserved block at the end
+/*
+ * Copyright 2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+
+/* Regions */
+define region ILM = [from 0 size 128k]; /* ILM */
+define region RAM = [from 0x80000 size 128k]; /* DLM */
+define region AXI_SRAM = [from 0x1080000 size 256k];
+define region NONCACHEABLE_RAM = [from 0x10C0000 size 256K];
+
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+define exported symbol _stack = end of block stack + 1;
+define block safe_stack with size = 512, readwrite access {};
+define exported symbol _stack_safe = end of block safe_stack + 1;
+
+/* Blocks */
+define block vectors with fixed order { section .vector_table, section .isr_vector };
+define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+define block framebuffer { section .framebuffer };
+
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+place at start of ILM { symbol _start };
+place in ILM { block vectors, block vectors_s }; // Vector table section
+place in ILM with minimum size order { block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+/* Explicit placement in AXI_SRAM */
+place in AXI_SRAM { block framebuffer };
+
+place in RAM with auto order { section .fast, section .fast.*, // "ramfunc" section
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in RAM { block heap }; // Heap reserved block
+place at end of RAM { block stack, block safe_stack }; // Stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf
index fd9b3a0a9d..7e28e152c6 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf
@@ -1,89 +1,89 @@
-/*
- * Copyright 2021-2022 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-
-/* Regions */
-define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */
-define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */
-define region DLM = [from 0x80000 size 256k]; /* DLM */
-define region AXI_SRAM = [from 0x1080000 size 768k];
-define region SDRAM = [from 0x40000000 size _extram_size];
-define region NONCACHEABLE_RAM = [from 0x1140000 size 256k];
-
-/* Blocks */
-define block vectors { section .isr_vector, section .vector_table };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-define block framebuffer with alignment = 8 { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-
-/* Symbols */
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-
-define exported symbol _stack_safe = end of block safe_stack + 1;
-define exported symbol _stack = end of block stack + 1;
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-place at start of XPI0 with fixed order { symbol _start};
-
-place at start of ILM_SLV with fixed order { block vectors };
-initialize by copy { block vectors };
-
-place in XPI0 with minimum size order {
- block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-place in ILM_SLV {
- section .fast, section .fast.*, // "ramfunc" section
- };
-
-place in DLM with auto order {
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-
-place in AXI_SRAM { block framebuffer };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in AXI_SRAM { block heap }; // Heap reserved block
-place at end of AXI_SRAM { block stack }; // Stack reserved block at the end
-place at end of DLM { block safe_stack }; // Safe stack reserved block at the end
+/*
+ * Copyright 2021-2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+
+/* Regions */
+define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */
+define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */
+define region DLM = [from 0x80000 size 256k]; /* DLM */
+define region AXI_SRAM = [from 0x1080000 size 768k];
+define region SDRAM = [from 0x40000000 size _extram_size];
+define region NONCACHEABLE_RAM = [from 0x1140000 size 256k];
+
+/* Blocks */
+define block vectors { section .isr_vector, section .vector_table };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+define block framebuffer with alignment = 8 { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+
+/* Symbols */
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+
+define exported symbol _stack_safe = end of block safe_stack + 1;
+define exported symbol _stack = end of block stack + 1;
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+place at start of XPI0 with fixed order { symbol _start};
+
+place at start of ILM_SLV with fixed order { block vectors };
+initialize by copy { block vectors };
+
+place in XPI0 with minimum size order {
+ block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+place in ILM_SLV {
+ section .fast, section .fast.*, // "ramfunc" section
+ };
+
+place in DLM with auto order {
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+
+place in AXI_SRAM { block framebuffer };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in AXI_SRAM { block heap }; // Heap reserved block
+place at end of AXI_SRAM { block stack }; // Stack reserved block at the end
+place at end of DLM { block safe_stack }; // Safe stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf
index 962c865fa6..854e22e207 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf
@@ -1,85 +1,85 @@
-/*
- * Copyright 2021-2022 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000;
-
-/* Regions */
-define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */
-define region AXI_SRAM = [from 0x1000000 size 2M];
-define region SDRAM = [from 0x40000000 size _extram_size - 4M];
-define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M];
-
-/* Blocks */
-define block vectors { section .isr_vector, section .vector_table };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-define block framebuffer with alignment = 8 { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-
-/* Symbols */
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-
-define exported symbol _stack_safe = end of block safe_stack + 1;
-define exported symbol _stack = end of block stack + 1;
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-place at start of XPI0 with fixed order { section .uf2_signature };
-place in XPI0 with fixed order {symbol _start};
-keep { section .uf2_signature };
-
-place at start of AXI_SRAM with fixed order { block vectors };
-initialize by copy { block vectors };
-
-place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-
-place in SDRAM { block framebuffer };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in SDRAM { block heap }; // Heap reserved block
-place at end of SDRAM { block stack }; // Stack reserved block at the end
-place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end
+/*
+ * Copyright 2021-2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000;
+
+/* Regions */
+define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */
+define region AXI_SRAM = [from 0x1000000 size 2M];
+define region SDRAM = [from 0x40000000 size _extram_size - 4M];
+define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M];
+
+/* Blocks */
+define block vectors { section .isr_vector, section .vector_table };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+define block framebuffer with alignment = 8 { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+
+/* Symbols */
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+
+define exported symbol _stack_safe = end of block safe_stack + 1;
+define exported symbol _stack = end of block stack + 1;
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+place at start of XPI0 with fixed order { section .uf2_signature };
+place in XPI0 with fixed order {symbol _start};
+keep { section .uf2_signature };
+
+place at start of AXI_SRAM with fixed order { block vectors };
+initialize by copy { block vectors };
+
+place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+
+place in SDRAM { block framebuffer };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in SDRAM { block heap }; // Heap reserved block
+place at end of SDRAM { block stack }; // Stack reserved block at the end
+place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf
index da4cec78f1..23f6c2d968 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf
@@ -1,96 +1,96 @@
-/*
- * Copyright 2021 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-
-/* Regions */
-define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ];
-define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ];
-define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */
-define region AXI_SRAM = [from 0x1000000 size 2M];
-define region SDRAM = [from 0x40000000 size _extram_size - 4M];
-define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M];
-
-/* Blocks */
-define block vectors { section .isr_vector, section .vector_table };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-define block framebuffer with alignment = 8 { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-
-define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info };
-
-/* Symbols */
-define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION;
-define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER;
-define exported symbol __app_load_addr__ = start of region XPI0;
-define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
-define exported symbol __boot_header_length__ = size of block boot_header;
-define exported symbol __fw_size__ = 0x1000;
-
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-
-define exported symbol _stack_safe = end of block safe_stack + 1;
-define exported symbol _stack = end of block stack + 1;
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info };
-place in NOR_CFG_OPTION { section .nor_cfg_option };
-place in BOOT_HEADER with fixed order { block boot_header };
-place at start of XPI0 with fixed order { symbol _start};
-
-place at start of AXI_SRAM with fixed order { block vectors };
-initialize by copy { block vectors };
-
-place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-
-place in SDRAM { block framebuffer };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in SDRAM { block heap }; // Heap reserved block
-place at end of SDRAM { block stack }; // Stack reserved block at the end
-place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end
+/*
+ * Copyright 2021 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+
+/* Regions */
+define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ];
+define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ];
+define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */
+define region AXI_SRAM = [from 0x1000000 size 2M];
+define region SDRAM = [from 0x40000000 size _extram_size - 4M];
+define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M];
+
+/* Blocks */
+define block vectors { section .isr_vector, section .vector_table };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+define block framebuffer with alignment = 8 { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+
+define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info };
+
+/* Symbols */
+define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION;
+define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER;
+define exported symbol __app_load_addr__ = start of region XPI0;
+define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+define exported symbol __boot_header_length__ = size of block boot_header;
+define exported symbol __fw_size__ = 0x1000;
+
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+
+define exported symbol _stack_safe = end of block safe_stack + 1;
+define exported symbol _stack = end of block stack + 1;
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info };
+place in NOR_CFG_OPTION { section .nor_cfg_option };
+place in BOOT_HEADER with fixed order { block boot_header };
+place at start of XPI0 with fixed order { symbol _start};
+
+place at start of AXI_SRAM with fixed order { block vectors };
+initialize by copy { block vectors };
+
+place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+
+place in SDRAM { block framebuffer };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in SDRAM { block heap }; // Heap reserved block
+place at end of SDRAM { block stack }; // Stack reserved block at the end
+place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf
index 0ecf3ae292..fe190a9225 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf
@@ -1,92 +1,92 @@
-/*
- * Copyright 2021-2022 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000;
-
-/* Regions */
-define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */
-define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */
-define region DLM = [from 0x80000 size 256k]; /* DLM */
-define region AXI_SRAM = [from 0x1080000 size 768k];
-define region SDRAM = [from 0x40000000 size _extram_size];
-define region NONCACHEABLE_RAM = [from 0x1140000 size 256k];
-
-/* Blocks */
-define block vectors { section .isr_vector, section .vector_table };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-define block framebuffer with alignment = 8 { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-
-/* Symbols */
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-
-define exported symbol _stack_safe = end of block safe_stack + 1;
-define exported symbol _stack = end of block stack + 1;
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-place at start of XPI0 with fixed order { section .uf2_signature };
-place in XPI0 with fixed order {symbol _start};
-keep { section .uf2_signature };
-
-place at start of ILM_SLV with fixed order { block vectors };
-initialize by copy { block vectors };
-
-place in XPI0 with minimum size order {
- block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-place in ILM_SLV {
- section .fast, section .fast.*, // "ramfunc" section
- };
-
-place in DLM with auto order {
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-
-place in AXI_SRAM { block framebuffer };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in AXI_SRAM { block heap }; // Heap reserved block
-place at end of AXI_SRAM { block stack }; // Stack reserved block at the end
-place at end of DLM { block safe_stack }; // Safe stack reserved block at the end
+/*
+ * Copyright 2021-2022 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000;
+
+/* Regions */
+define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */
+define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */
+define region DLM = [from 0x80000 size 256k]; /* DLM */
+define region AXI_SRAM = [from 0x1080000 size 768k];
+define region SDRAM = [from 0x40000000 size _extram_size];
+define region NONCACHEABLE_RAM = [from 0x1140000 size 256k];
+
+/* Blocks */
+define block vectors { section .isr_vector, section .vector_table };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+define block framebuffer with alignment = 8 { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+
+/* Symbols */
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+
+define exported symbol _stack_safe = end of block safe_stack + 1;
+define exported symbol _stack = end of block stack + 1;
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+place at start of XPI0 with fixed order { section .uf2_signature };
+place in XPI0 with fixed order {symbol _start};
+keep { section .uf2_signature };
+
+place at start of ILM_SLV with fixed order { block vectors };
+initialize by copy { block vectors };
+
+place in XPI0 with minimum size order {
+ block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+place in ILM_SLV {
+ section .fast, section .fast.*, // "ramfunc" section
+ };
+
+place in DLM with auto order {
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+
+place in AXI_SRAM { block framebuffer };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in AXI_SRAM { block heap }; // Heap reserved block
+place at end of AXI_SRAM { block stack }; // Stack reserved block at the end
+place at end of DLM { block safe_stack }; // Safe stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf
index 4905f88846..273c6b0a38 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf
@@ -1,103 +1,103 @@
-/*
- * Copyright 2021 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-
-/* Regions */
-define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ];
-define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ];
-define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */
-define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */
-define region DLM = [from 0x80000 size 256k]; /* DLM */
-define region AXI_SRAM = [from 0x1080000 size 768k];
-define region SDRAM = [from 0x40000000 size _extram_size];
-define region NONCACHEABLE_RAM = [from 0x1140000 size 256k];
-
-/* Blocks */
-define block vectors { section .isr_vector, section .vector_table };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-define block framebuffer with alignment = 8 { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-
-define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info };
-
-/* Symbols */
-define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION;
-define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER;
-define exported symbol __app_load_addr__ = start of region XPI0;
-define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
-define exported symbol __boot_header_length__ = size of block boot_header;
-define exported symbol __fw_size__ = 0x1000;
-
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-
-define exported symbol _stack_safe = end of block safe_stack + 1;
-define exported symbol _stack = end of block stack + 1;
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info };
-place in NOR_CFG_OPTION { section .nor_cfg_option };
-place in BOOT_HEADER with fixed order { block boot_header };
-place at start of XPI0 with fixed order { symbol _start};
-
-place at start of ILM_SLV with fixed order { block vectors };
-initialize by copy { block vectors };
-
-place in XPI0 with minimum size order {
- block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec // Catch-all for (readonly) executable code (e.g. .text)
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-place in ILM_SLV {
- section .fast, section .fast.*, // "ramfunc" section
- };
-
-place in DLM with auto order {
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-
-place in AXI_SRAM { block framebuffer };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
-place in AXI_SRAM { block heap }; // Heap reserved block
-place at end of AXI_SRAM { block stack }; // Stack reserved block at the end
-place at end of DLM { block safe_stack }; // Safe stack reserved block at the end
+/*
+ * Copyright 2021 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+
+/* Regions */
+define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ];
+define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ];
+define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */
+define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */
+define region DLM = [from 0x80000 size 256k]; /* DLM */
+define region AXI_SRAM = [from 0x1080000 size 768k];
+define region SDRAM = [from 0x40000000 size _extram_size];
+define region NONCACHEABLE_RAM = [from 0x1140000 size 256k];
+
+/* Blocks */
+define block vectors { section .isr_vector, section .vector_table };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+define block framebuffer with alignment = 8 { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+
+define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info };
+
+/* Symbols */
+define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION;
+define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER;
+define exported symbol __app_load_addr__ = start of region XPI0;
+define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+define exported symbol __boot_header_length__ = size of block boot_header;
+define exported symbol __fw_size__ = 0x1000;
+
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+
+define exported symbol _stack_safe = end of block safe_stack + 1;
+define exported symbol _stack = end of block stack + 1;
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info };
+place in NOR_CFG_OPTION { section .nor_cfg_option };
+place in BOOT_HEADER with fixed order { block boot_header };
+place at start of XPI0 with fixed order { symbol _start};
+
+place at start of ILM_SLV with fixed order { block vectors };
+initialize by copy { block vectors };
+
+place in XPI0 with minimum size order {
+ block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec // Catch-all for (readonly) executable code (e.g. .text)
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+place in ILM_SLV {
+ section .fast, section .fast.*, // "ramfunc" section
+ };
+
+place in DLM with auto order {
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+
+place in AXI_SRAM { block framebuffer };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss };
+place in AXI_SRAM { block heap }; // Heap reserved block
+place at end of AXI_SRAM { block stack }; // Stack reserved block at the end
+place at end of DLM { block safe_stack }; // Safe stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf
index 25e32ed3f7..28076234d2 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf
@@ -1,79 +1,79 @@
-/*
- * Copyright 2021 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-
-/* Regions */
-define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */
-define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */
-define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */
-define region NONCACHEABLE_RAM = [from 0x1140000 size 256K];
-
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-define exported symbol _stack = end of block stack + 1;
-
-/* Blocks */
-define block vectors { section .isr_vector, section .vector_table };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-define block framebuffer { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-define exported symbol _stack_safe = end of block safe_stack + 1;
-
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-place at start of CORE0_LM_SLV { symbol _start };
-place in CORE0_LM_SLV { block vectors }; // Vector table section
-place in CORE0_LM_SLV with minimum size order {
- block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec, // Catch-all for (readonly) executable code (e.g. .text)
- section .fast, section .fast.*, // "ramfunc" section
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-/* Explicit placement in AXI_SRAM */
-place in AXI_SRAM { block framebuffer };
-
-place in AXI_SRAM with auto order {
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable
-place in AXI_SRAM { block heap }; // Heap reserved block
-place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end
+/*
+ * Copyright 2021 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+
+/* Regions */
+define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */
+define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */
+define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */
+define region NONCACHEABLE_RAM = [from 0x1140000 size 256K];
+
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+define exported symbol _stack = end of block stack + 1;
+
+/* Blocks */
+define block vectors { section .isr_vector, section .vector_table };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+define block framebuffer { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+define exported symbol _stack_safe = end of block safe_stack + 1;
+
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+place at start of CORE0_LM_SLV { symbol _start };
+place in CORE0_LM_SLV { block vectors }; // Vector table section
+place in CORE0_LM_SLV with minimum size order {
+ block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec, // Catch-all for (readonly) executable code (e.g. .text)
+ section .fast, section .fast.*, // "ramfunc" section
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+/* Explicit placement in AXI_SRAM */
+place in AXI_SRAM { block framebuffer };
+
+place in AXI_SRAM with auto order {
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable
+place in AXI_SRAM { block heap }; // Heap reserved block
+place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end
diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf
index 600e3a16ca..e7617c78e7 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf
+++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf
@@ -1,79 +1,79 @@
-/*
- * Copyright 2021 hpmicro
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-define memory with size = 4G;
-
-/* Regions */
-define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */
-define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */
-define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */
-define region NONCACHEABLE_RAM = [from 0x1140000 size 256K];
-
-define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
-define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
-define exported symbol _stack = end of block stack + 1;
-
-/* Blocks */
-define block vectors { section .isr_vector, section .vector_table };
-define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
-define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block eh_frame { section .eh_frame, section .eh_frame.* };
-define block tbss { section .tbss, section .tbss.* };
-define block tdata { section .tdata, section .tdata.* };
-define block tls { block tbss, block tdata };
-define block tdata_load { copy of block tdata };
-define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
-define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-define block framebuffer { section .framebuffer };
-define block safe_stack with size = 512, readwrite access {};
-define exported symbol _stack_safe = end of block safe_stack + 1;
-
-
-do not initialize { section .noncacheable };
-do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
-do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
-
-initialize by copy with packing=auto { section .noncacheable.init };
-initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
-initialize by copy with packing=auto { section .sdata, section .sdata.* };
-initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
-
-initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
-initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-place at start of CORE1_LM_SLV { symbol _start };
-place in CORE1_LM_SLV { block vectors }; // Vector table section
-place in CORE1_LM_SLV with minimum size order {
- block tdata_load, // Thread-local-storage load image
- block ctors, // Constructors block
- block dtors, // Destructors block
- block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
- readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
- readexec, // Catch-all for (readonly) executable code (e.g. .text)
- section .fast, section .fast.*, // "ramfunc" section
- };
-
-//
-// The GNU compiler creates these exception-related sections as writeable.
-// Override the section header flag and make them readonly so they can be
-// placed into flash.
-//
-define access readonly { section .gcc_except_table, section .gcc_except_table.* };
-define access readonly { section .eh_frame, section .eh_frame.* };
-define access readonly { section .sdata.DW.* };
-
-/* Explicit placement in AXI_SRAM */
-place in AXI_SRAM { block framebuffer };
-
-place in AXI_SRAM with auto order {
- block tls, // Thread-local-storage block
- readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
- zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss)
- };
-place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable
-place in AXI_SRAM { block heap }; // Heap reserved block
-place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end
+/*
+ * Copyright 2021 hpmicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+define memory with size = 4G;
+
+/* Regions */
+define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */
+define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */
+define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */
+define region NONCACHEABLE_RAM = [from 0x1140000 size 256K];
+
+define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM;
+define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1;
+define exported symbol _stack = end of block stack + 1;
+
+/* Blocks */
+define block vectors { section .isr_vector, section .vector_table };
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block eh_frame { section .eh_frame, section .eh_frame.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+define block framebuffer { section .framebuffer };
+define block safe_stack with size = 512, readwrite access {};
+define exported symbol _stack_safe = end of block safe_stack + 1;
+
+
+do not initialize { section .noncacheable };
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility
+do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs
+
+initialize by copy with packing=auto { section .noncacheable.init };
+initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections
+initialize by copy with packing=auto { section .sdata, section .sdata.* };
+initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections
+
+initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one
+initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+place at start of CORE1_LM_SLV { symbol _start };
+place in CORE1_LM_SLV { block vectors }; // Vector table section
+place in CORE1_LM_SLV with minimum size order {
+ block tdata_load, // Thread-local-storage load image
+ block ctors, // Constructors block
+ block dtors, // Destructors block
+ block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable)
+ readonly, // Catch-all for readonly data (e.g. .rodata, .srodata)
+ readexec, // Catch-all for (readonly) executable code (e.g. .text)
+ section .fast, section .fast.*, // "ramfunc" section
+ };
+
+//
+// The GNU compiler creates these exception-related sections as writeable.
+// Override the section header flag and make them readonly so they can be
+// placed into flash.
+//
+define access readonly { section .gcc_except_table, section .gcc_except_table.* };
+define access readonly { section .eh_frame, section .eh_frame.* };
+define access readonly { section .sdata.DW.* };
+
+/* Explicit placement in AXI_SRAM */
+place in AXI_SRAM { block framebuffer };
+
+place in AXI_SRAM with auto order {
+ block tls, // Thread-local-storage block
+ readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+ zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss)
+ };
+place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable
+place in AXI_SRAM { block heap }; // Heap reserved block
+place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end
diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf
index 0f11aa45cb..1563925f19 100644
--- a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf
+++ b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf
@@ -1,127 +1,127 @@
-/*
-** ###################################################################
-** Processors: MIMXRT1052CVL5A
-** MIMXRT1052DVL6A
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1050RM Rev.C, 08/2017
-** Version: rev. 0.1, 2017-01-10
-** Build: b170927
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2017 NXP
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** 1. Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** 2. Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** 3. Neither the name of the copyright holder nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** ###################################################################
-*/
-
-define symbol m_interrupts_start = 0x60002000;
-define symbol m_interrupts_end = 0x600023FF;
-
-define symbol m_itcm_start = 0x00000000;
-define symbol m_itcm_end = 0x0001FFFF;
-
-define symbol m_spiflash_start = 0x60002400;
-define symbol m_spiflash_end = 0x7F7FFFFF;
-
-define symbol m_dtcm_start = 0x20000000;
-define symbol m_dtcm_end = 0x2001FFFF;/* DTCM 128KB */
-
-define symbol m_ocram_start = 0x20200000;
-define symbol m_ocram_end = 0x2020FFFF;/* OCRAM 64KB */
-
-define symbol m_sdram_start = 0x80000000;
-define symbol m_sdram_end = 0x81DFFFFF;
-
-define symbol m_ncache_start = 0x81E00000;
-define symbol m_ncache_end = 0x81FFFFFF;
-
-define exported symbol m_boot_hdr_conf_start = 0x60000000;
-define symbol m_boot_hdr_ivt_start = 0x60001000;
-define symbol m_boot_hdr_boot_data_start = 0x60001020;
-define symbol m_boot_hdr_dcd_data_start = 0x60001030;
-
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-define exported symbol __VECTOR_RAM = m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
-define exported symbol __RTT_HEAP_END = m_dtcm_end;
-
-define memory mem with size = 4G;
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_spiflash_start to m_spiflash_end];
-
-define region ITCM_region = mem:[from m_itcm_start to m_itcm_end];
-define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end];
-define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end];
-define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
-define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { readwrite };
-define block ZI { zi };
-define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
-
-initialize by copy { readwrite, section .textrw};
-do not initialize { section .noinit };
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-
-place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
-place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
-place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
-place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
-
-keep { section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
-keep { section FSymTab };
-keep { section VSymTab };
-keep { section .rti_fn* };
-
-place in TEXT_region { readonly };
-place in DTCM_region { block RW };
-place in DTCM_region { block ZI };
-place in DTCM_region { last block HEAP };
-place in DTCM_region { block CSTACK };
-place in NCACHE_region { block NCACHE_VAR };
\ No newline at end of file
+/*
+** ###################################################################
+** Processors: MIMXRT1052CVL5A
+** MIMXRT1052DVL6A
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMXRT1050RM Rev.C, 08/2017
+** Version: rev. 0.1, 2017-01-10
+** Build: b170927
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** 1. Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** 2. Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** 3. Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x60002000;
+define symbol m_interrupts_end = 0x600023FF;
+
+define symbol m_itcm_start = 0x00000000;
+define symbol m_itcm_end = 0x0001FFFF;
+
+define symbol m_spiflash_start = 0x60002400;
+define symbol m_spiflash_end = 0x7F7FFFFF;
+
+define symbol m_dtcm_start = 0x20000000;
+define symbol m_dtcm_end = 0x2001FFFF;/* DTCM 128KB */
+
+define symbol m_ocram_start = 0x20200000;
+define symbol m_ocram_end = 0x2020FFFF;/* OCRAM 64KB */
+
+define symbol m_sdram_start = 0x80000000;
+define symbol m_sdram_end = 0x81DFFFFF;
+
+define symbol m_ncache_start = 0x81E00000;
+define symbol m_ncache_end = 0x81FFFFFF;
+
+define exported symbol m_boot_hdr_conf_start = 0x60000000;
+define symbol m_boot_hdr_ivt_start = 0x60001000;
+define symbol m_boot_hdr_boot_data_start = 0x60001020;
+define symbol m_boot_hdr_dcd_data_start = 0x60001030;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+define exported symbol __RTT_HEAP_END = m_dtcm_end;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_spiflash_start to m_spiflash_end];
+
+define region ITCM_region = mem:[from m_itcm_start to m_itcm_end];
+define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end];
+define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end];
+define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
+define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
+
+initialize by copy { readwrite, section .textrw};
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+
+place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
+place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
+place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
+place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
+
+keep { section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+
+place in TEXT_region { readonly };
+place in DTCM_region { block RW };
+place in DTCM_region { block ZI };
+place in DTCM_region { last block HEAP };
+place in DTCM_region { block CSTACK };
+place in NCACHE_region { block NCACHE_VAR };
diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds
index 7ef0bb392e..cf0b16b7b9 100644
--- a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds
+++ b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds
@@ -260,7 +260,7 @@ SECTIONS
stack_end = .;
__StackTop = .;
} > m_dtcm
-
+
.RTT_HEAP :
{
heap_start = .;
diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct
index d6a1f80056..24ecc854aa 100644
--- a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct
+++ b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct
@@ -1,134 +1,134 @@
-#! armcc -E
-/*
-** ###################################################################
-** Processors: MIMXRT1052CVL5A
-** MIMXRT1052DVL6A
-**
-** Compiler: Keil ARM C/C++ Compiler
-** Reference manual: IMXRT1050RM Rev.C, 08/2017
-** Version: rev. 0.1, 2017-01-10
-** Build: b170927
-**
-** Abstract:
-** Linker file for the Keil ARM C/C++ Compiler
-**
-** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2017 NXP
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** 1. Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** 2. Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** 3. Neither the name of the copyright holder nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** ###################################################################
-*/
-
-#define m_flash_config_start 0x60000000
-#define m_flash_config_size 0x00001000
-
-#define m_ivt_start 0x60001000
-#define m_ivt_size 0x00001000
-
-#define m_text_start 0x60002000
-#define m_text_size 0x007FE000
-
-#define m_data_start 0x20000000
-#define m_data_size 0x00020000
-
-#define m_ncache_start 0x81E00000
-#define m_ncache_size 0x00200000
-
-/* Sizes */
-#if (defined(__stack_size__))
- #define Stack_Size __stack_size__
-#else
- #define Stack_Size 0x1000
-#endif
-
-#if (defined(__heap_size__))
- #define Heap_Size __heap_size__
-#else
- #define Heap_Size 0x0400
-#endif
-
-#include "../../rtconfig.h"
-;BSP_USING_HYPERFLASH
-#if (defined(BOARD_USING_QSPIFLASH))
-LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region
-{
- RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
- {
- * (.boot_hdr.conf, +FIRST)
- }
-}
-
-LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
-{
- RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
- {
- * (.boot_hdr.ivt, +FIRST)
- * (.boot_hdr.boot_data)
- * (.boot_hdr.dcd_data)
- }
-}
-#endif
-
-#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
-
-; load region size_region
-LR_IROM1 m_text_start m_text_size
-{
- ER_IROM1 m_text_start m_text_size ; load address = execution address
- {
- * (RESET,+FIRST)
- * (InRoot$$Sections)
- .ANY (+RO)
- }
-
- RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
- {
- .ANY (+RW +ZI)
- }
-
- ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
- ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
- RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
-
- ; ncache RW data
- RW_m_ncache m_ncache_start m_ncache_size
- {
- * (NonCacheable.init)
- * (NonCacheable)
- }
- ITCM 0x400 0xFBFF {
- ;drv_flexspi_hyper.o(+RO)
- ;fsl_flexspi.o(+RO)
- * (*CLOCK_DisableClock)
- * (*CLOCK_ControlGate)
- * (*CLOCK_EnableClock)
- * (*CLOCK_SetDiv)
- * (itcm)
- }
-}
+#! armcc -E
+/*
+** ###################################################################
+** Processors: MIMXRT1052CVL5A
+** MIMXRT1052DVL6A
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: IMXRT1050RM Rev.C, 08/2017
+** Version: rev. 0.1, 2017-01-10
+** Build: b170927
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** 1. Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** 2. Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** 3. Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_flash_config_start 0x60000000
+#define m_flash_config_size 0x00001000
+
+#define m_ivt_start 0x60001000
+#define m_ivt_size 0x00001000
+
+#define m_text_start 0x60002000
+#define m_text_size 0x007FE000
+
+#define m_data_start 0x20000000
+#define m_data_size 0x00020000
+
+#define m_ncache_start 0x81E00000
+#define m_ncache_size 0x00200000
+
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x1000
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+#include "../../rtconfig.h"
+;BSP_USING_HYPERFLASH
+#if (defined(BOARD_USING_QSPIFLASH))
+LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region
+{
+ RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
+ {
+ * (.boot_hdr.conf, +FIRST)
+ }
+}
+
+LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
+{
+ RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
+ {
+ * (.boot_hdr.ivt, +FIRST)
+ * (.boot_hdr.boot_data)
+ * (.boot_hdr.dcd_data)
+ }
+}
+#endif
+
+#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
+
+; load region size_region
+LR_IROM1 m_text_start m_text_size
+{
+ ER_IROM1 m_text_start m_text_size ; load address = execution address
+ {
+ * (RESET,+FIRST)
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
+ {
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
+ ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
+ RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
+
+ ; ncache RW data
+ RW_m_ncache m_ncache_start m_ncache_size
+ {
+ * (NonCacheable.init)
+ * (NonCacheable)
+ }
+ ITCM 0x400 0xFBFF {
+ ;drv_flexspi_hyper.o(+RO)
+ ;fsl_flexspi.o(+RO)
+ * (*CLOCK_DisableClock)
+ * (*CLOCK_ControlGate)
+ * (*CLOCK_EnableClock)
+ * (*CLOCK_SetDiv)
+ * (itcm)
+ }
+}
diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds
index b8c229ae3c..d21ddb6a79 100644
--- a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds
+++ b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds
@@ -261,7 +261,7 @@ SECTIONS
stack_end = .;
__StackTop = .;
} > m_dtcm
-
+
.RTT_HEAP :
{
heap_start = .;
diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct
index 7200f9d479..ef0ddf80f3 100644
--- a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct
+++ b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct
@@ -76,27 +76,27 @@
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
; load region size_region
-LR_IROM1 m_text_start m_text_size
-{
+LR_IROM1 m_text_start m_text_size
+{
ER_IROM1 m_text_start m_text_size ; load address = execution address
- {
+ {
* (RESET,+FIRST)
* (InRoot$$Sections)
.ANY (+RO)
}
-
+
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
- {
+ {
.ANY (+RW +ZI)
}
-
+
ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
; ncache RW data
- RW_m_ncache m_ncache_start m_ncache_size
- {
+ RW_m_ncache m_ncache_start m_ncache_size
+ {
* (NonCacheable.init)
* (NonCacheable)
}
diff --git a/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds
index f585fbced8..1e11ddc014 100644
--- a/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds
+++ b/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds
@@ -86,9 +86,9 @@ SECTIONS
.ivt : AT(ivt_begin)
{
. = ALIGN(4);
- KEEP(* (.boot_hdr.ivt)) /* ivt section */
- KEEP(* (.boot_hdr.boot_data)) /* boot section */
- KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
+ KEEP(* (.boot_hdr.ivt)) /* ivt section */
+ KEEP(* (.boot_hdr.boot_data)) /* boot section */
+ KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
. = ALIGN(4);
} > m_ivt
@@ -278,7 +278,7 @@ SECTIONS
stack_end = .;
__StackTop = .;
} > m_data
-
+
.RTT_HEAP :
{
heap_start = .;
diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds
index b8c229ae3c..d21ddb6a79 100644
--- a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds
+++ b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds
@@ -261,7 +261,7 @@ SECTIONS
stack_end = .;
__StackTop = .;
} > m_dtcm
-
+
.RTT_HEAP :
{
heap_start = .;
diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct
index 654c165f02..9e7f6546d2 100644
--- a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct
+++ b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct
@@ -77,58 +77,58 @@
#if (defined(BSP_USING_HYPERFLASH))
LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region
-{
+{
RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
- {
+ {
* (.boot_hdr.conf, +FIRST)
- }
+ }
}
LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
-{
+{
RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
- {
+ {
* (.boot_hdr.ivt, +FIRST)
* (.boot_hdr.boot_data)
* (.boot_hdr.dcd_data)
- }
+ }
}
#endif
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
; load region size_region
-LR_IROM1 m_text_start m_text_size
-{
+LR_IROM1 m_text_start m_text_size
+{
ER_IROM1 m_text_start m_text_size ; load address = execution address
- {
+ {
* (RESET,+FIRST)
* (InRoot$$Sections)
.ANY (+RO)
}
-
+
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
- {
+ {
.ANY (+RW +ZI)
}
-
+
ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
; ncache RW data
- RW_m_ncache m_ncache_start m_ncache_size
- {
+ RW_m_ncache m_ncache_start m_ncache_size
+ {
* (NonCacheable.init)
* (NonCacheable)
}
ITCM 0x400 0xFBFF {
- ;drv_flexspi_hyper.o(+RO)
- ;fsl_flexspi.o(+RO)
- * (*CLOCK_DisableClock)
- * (*CLOCK_ControlGate)
- * (*CLOCK_EnableClock)
- * (*CLOCK_SetDiv)
- * (itcm)
- }
+ ;drv_flexspi_hyper.o(+RO)
+ ;fsl_flexspi.o(+RO)
+ * (*CLOCK_DisableClock)
+ * (*CLOCK_ControlGate)
+ * (*CLOCK_EnableClock)
+ * (*CLOCK_SetDiv)
+ * (itcm)
+ }
}
diff --git a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds
index b8c229ae3c..d21ddb6a79 100644
--- a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds
+++ b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds
@@ -261,7 +261,7 @@ SECTIONS
stack_end = .;
__StackTop = .;
} > m_dtcm
-
+
.RTT_HEAP :
{
heap_start = .;
diff --git a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct
index 7200f9d479..ef0ddf80f3 100644
--- a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct
+++ b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct
@@ -76,27 +76,27 @@
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
; load region size_region
-LR_IROM1 m_text_start m_text_size
-{
+LR_IROM1 m_text_start m_text_size
+{
ER_IROM1 m_text_start m_text_size ; load address = execution address
- {
+ {
* (RESET,+FIRST)
* (InRoot$$Sections)
.ANY (+RO)
}
-
+
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
- {
+ {
.ANY (+RW +ZI)
}
-
+
ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
; ncache RW data
- RW_m_ncache m_ncache_start m_ncache_size
- {
+ RW_m_ncache m_ncache_start m_ncache_size
+ {
* (NonCacheable.init)
* (NonCacheable)
}
diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds
index 0691d0fe48..ab64f3ef37 100644
--- a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds
+++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds
@@ -268,7 +268,7 @@ SECTIONS
stack_end = .;
__StackTop = .;
} > m_sdram
-
+
.RTT_HEAP :
{
heap_start = .;
diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds
index 9942889d58..169a2d310a 100644
--- a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds
+++ b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds
@@ -268,7 +268,7 @@ SECTIONS
stack_end = .;
__StackTop = .;
} > m_dtcm
-
+
.RTT_HEAP :
{
heap_start = .;
diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct
index f36201c200..d2a77d7319 100644
--- a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct
+++ b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct
@@ -86,48 +86,48 @@
#if (defined(BSP_USING_4MFLASH))
LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region
-{
+{
RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
- {
+ {
* (.boot_hdr.conf, +FIRST)
- }
+ }
}
LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
-{
+{
RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
- {
+ {
* (.boot_hdr.ivt, +FIRST)
* (.boot_hdr.boot_data)
* (.boot_hdr.dcd_data)
- }
+ }
}
#endif
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
; load region size_region
-LR_IROM1 m_text_start m_text_size
-{
+LR_IROM1 m_text_start m_text_size
+{
ER_IROM1 m_text_start m_text_size ; load address = execution address
- {
+ {
* (RESET,+FIRST)
* (InRoot$$Sections)
.ANY (+RO)
}
-
+
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
- {
+ {
.ANY (+RW +ZI)
}
-
+
ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
; ncache RW data
RW_m_ncache m_ncache_start m_ncache_size
- {
+ {
* (NonCacheable.init)
* (NonCacheable)
}
diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf
index a3a39c4731..497e6285c5 100644
--- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf
+++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf
@@ -1,93 +1,93 @@
-/*
-** ###################################################################
-** Processors: MIMXRT1021CAF4A
-** MIMXRT1021CAG4A
-** MIMXRT1021DAF5A
-** MIMXRT1021DAG5A
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018
-** Version: rev. 0.1, 2017-06-06
-** Build: b180801
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2018 NXP
-**
-** SPDX-License-Identifier: BSD-3-Clause
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** ###################################################################
-*/
-
-define symbol m_interrupts_start = 0x60002000;
-define symbol m_interrupts_end = 0x600023FF;
-
-define symbol m_text_start = 0x60002400;
-define symbol m_text_end = 0x607FFFFF;
-
-define symbol m_data_start = 0x20000000;
-define symbol m_data_end = 0x2000FFFF;
-
-define symbol m_data2_start = 0x20200000;
-define symbol m_data2_end = 0x2021FFFF;
-
-define exported symbol m_boot_hdr_conf_start = 0x60000000;
-define symbol m_boot_hdr_ivt_start = 0x60001000;
-define symbol m_boot_hdr_boot_data_start = 0x60001020;
-define symbol m_boot_hdr_dcd_data_start = 0x60001030;
-
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-define exported symbol __VECTOR_RAM = m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
-
-define memory mem with size = 4G;
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_text_start to m_text_end];
-
-define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
-define region DATA2_region = mem:[from m_data2_start to m_data2_end];
-define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { readwrite };
-define block ZI { zi };
-define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
-
-initialize by copy { readwrite, section .textrw };
-do not initialize { section .noinit };
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-
-place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
-place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
-place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
-place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
-
-keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
-
-place in TEXT_region { readonly };
-place in DATA_region { block RW };
-place in DATA_region { block ZI };
-place in DATA_region { last block HEAP };
-place in DATA_region { block NCACHE_VAR };
-place in CSTACK_region { block CSTACK };
-
+/*
+** ###################################################################
+** Processors: MIMXRT1021CAF4A
+** MIMXRT1021CAG4A
+** MIMXRT1021DAF5A
+** MIMXRT1021DAG5A
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018
+** Version: rev. 0.1, 2017-06-06
+** Build: b180801
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2018 NXP
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x60002000;
+define symbol m_interrupts_end = 0x600023FF;
+
+define symbol m_text_start = 0x60002400;
+define symbol m_text_end = 0x607FFFFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x2000FFFF;
+
+define symbol m_data2_start = 0x20200000;
+define symbol m_data2_end = 0x2021FFFF;
+
+define exported symbol m_boot_hdr_conf_start = 0x60000000;
+define symbol m_boot_hdr_ivt_start = 0x60001000;
+define symbol m_boot_hdr_boot_data_start = 0x60001020;
+define symbol m_boot_hdr_dcd_data_start = 0x60001030;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
+
+initialize by copy { readwrite, section .textrw };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+
+place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
+place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
+place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
+place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
+
+keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
+
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in DATA_region { block NCACHE_VAR };
+place in CSTACK_region { block CSTACK };
+
diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf
index 5da51d70c6..54b091e58f 100644
--- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf
+++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf
@@ -1,101 +1,101 @@
-/*
-** ###################################################################
-** Processors: MIMXRT1021CAF4A
-** MIMXRT1021CAG4A
-** MIMXRT1021DAF5A
-** MIMXRT1021DAG5A
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018
-** Version: rev. 0.1, 2017-06-06
-** Build: b180801
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2018 NXP
-**
-** SPDX-License-Identifier: BSD-3-Clause
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** ###################################################################
-*/
-
-define symbol m_interrupts_start = 0x60002000;
-define symbol m_interrupts_end = 0x600023FF;
-
-define symbol m_text_start = 0x60002400;
-define symbol m_text_end = 0x607FFFFF;
-
-define symbol m_data_start = 0x20000000;
-define symbol m_data_end = 0x2000FFFF;
-
-define symbol m_data2_start = 0x20200000;
-define symbol m_data2_end = 0x2021FFFF;
-
-define symbol m_data3_start = 0x80000000;
-define symbol m_data3_end = 0x81DFFFFF;
-
-define symbol m_ncache_start = 0x81E00000;
-define symbol m_ncache_end = 0x81FFFFFF;
-
-define exported symbol m_boot_hdr_conf_start = 0x60000000;
-define symbol m_boot_hdr_ivt_start = 0x60001000;
-define symbol m_boot_hdr_boot_data_start = 0x60001020;
-define symbol m_boot_hdr_dcd_data_start = 0x60001030;
-
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-define exported symbol __VECTOR_RAM = m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
-
-define memory mem with size = 4G;
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_text_start to m_text_end];
-
-define region DATA_region = mem:[from m_data_start to m_data_end];
-define region DATA2_region = mem:[from m_data2_start to m_data2_end];
-define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__];
-define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end];
-define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { first readwrite, section m_usb_dma_init_data };
-define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
-define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
-
-initialize by copy { readwrite, section .textrw };
-do not initialize { section .noinit };
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-
-place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
-place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
-place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
-place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
-
-keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
-
-place in TEXT_region { readonly };
-place in DATA3_region { block RW };
-place in DATA3_region { block ZI };
-place in DATA3_region { last block HEAP };
-place in CSTACK_region { block CSTACK };
-place in NCACHE_region { block NCACHE_VAR };
-
+/*
+** ###################################################################
+** Processors: MIMXRT1021CAF4A
+** MIMXRT1021CAG4A
+** MIMXRT1021DAF5A
+** MIMXRT1021DAG5A
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018
+** Version: rev. 0.1, 2017-06-06
+** Build: b180801
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2018 NXP
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x60002000;
+define symbol m_interrupts_end = 0x600023FF;
+
+define symbol m_text_start = 0x60002400;
+define symbol m_text_end = 0x607FFFFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x2000FFFF;
+
+define symbol m_data2_start = 0x20200000;
+define symbol m_data2_end = 0x2021FFFF;
+
+define symbol m_data3_start = 0x80000000;
+define symbol m_data3_end = 0x81DFFFFF;
+
+define symbol m_ncache_start = 0x81E00000;
+define symbol m_ncache_end = 0x81FFFFFF;
+
+define exported symbol m_boot_hdr_conf_start = 0x60000000;
+define symbol m_boot_hdr_ivt_start = 0x60001000;
+define symbol m_boot_hdr_boot_data_start = 0x60001020;
+define symbol m_boot_hdr_dcd_data_start = 0x60001030;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+
+define region DATA_region = mem:[from m_data_start to m_data_end];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end];
+define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end];
+define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { first readwrite, section m_usb_dma_init_data };
+define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
+define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
+
+initialize by copy { readwrite, section .textrw };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+
+place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
+place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
+place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
+place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
+
+keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
+
+place in TEXT_region { readonly };
+place in DATA3_region { block RW };
+place in DATA3_region { block ZI };
+place in DATA3_region { last block HEAP };
+place in CSTACK_region { block CSTACK };
+place in NCACHE_region { block NCACHE_VAR };
+
diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf
index a835ba92c7..73a34d0385 100644
--- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf
+++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf
@@ -1,81 +1,81 @@
-/*
-** ###################################################################
-** Processors: MIMXRT1021CAF4A
-** MIMXRT1021CAG4A
-** MIMXRT1021DAF5A
-** MIMXRT1021DAG5A
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018
-** Version: rev. 0.1, 2017-06-06
-** Build: b180801
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2018 NXP
-**
-** SPDX-License-Identifier: BSD-3-Clause
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** ###################################################################
-*/
-
-define symbol m_interrupts_start = 0x00000000;
-define symbol m_interrupts_end = 0x000003FF;
-
-define symbol m_text_start = 0x00000400;
-define symbol m_text_end = 0x0000FFFF;
-
-define symbol m_data_start = 0x20000000;
-define symbol m_data_end = 0x2000FFFF;
-
-define symbol m_data2_start = 0x20200000;
-define symbol m_data2_end = 0x2021FFFF;
-
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-define exported symbol __VECTOR_RAM = m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
-
-define memory mem with size = 4G;
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_text_start to m_text_end];
-
-define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
-define region DATA2_region = mem:[from m_data2_start to m_data2_end];
-define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { readwrite };
-define block ZI { zi };
-define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
-
-initialize by copy { readwrite, section .textrw };
-do not initialize { section .noinit };
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-
-place in TEXT_region { readonly };
-place in DATA_region { block RW };
-place in DATA_region { block ZI };
-place in DATA_region { last block HEAP };
-place in DATA_region { block NCACHE_VAR };
-place in CSTACK_region { block CSTACK };
-
+/*
+** ###################################################################
+** Processors: MIMXRT1021CAF4A
+** MIMXRT1021CAG4A
+** MIMXRT1021DAF5A
+** MIMXRT1021DAG5A
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018
+** Version: rev. 0.1, 2017-06-06
+** Build: b180801
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2018 NXP
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x00000000;
+define symbol m_interrupts_end = 0x000003FF;
+
+define symbol m_text_start = 0x00000400;
+define symbol m_text_end = 0x0000FFFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x2000FFFF;
+
+define symbol m_data2_start = 0x20200000;
+define symbol m_data2_end = 0x2021FFFF;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
+
+initialize by copy { readwrite, section .textrw };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in DATA_region { block NCACHE_VAR };
+place in CSTACK_region { block CSTACK };
+
diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf
index c2056d3ddc..6788c317e2 100644
--- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf
+++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf
@@ -1,89 +1,89 @@
-/*
-** ###################################################################
-** Processors: MIMXRT1021CAF4A
-** MIMXRT1021CAG4A
-** MIMXRT1021DAF5A
-** MIMXRT1021DAG5A
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018
-** Version: rev. 0.1, 2017-06-06
-** Build: b180801
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2018 NXP
-**
-** SPDX-License-Identifier: BSD-3-Clause
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** ###################################################################
-*/
-
-define symbol m_interrupts_start = 0x00000000;
-define symbol m_interrupts_end = 0x000003FF;
-
-define symbol m_text_start = 0x00000400;
-define symbol m_text_end = 0x0000FFFF;
-
-define symbol m_data_start = 0x20000000;
-define symbol m_data_end = 0x2000FFFF;
-
-define symbol m_data2_start = 0x20200000;
-define symbol m_data2_end = 0x2021FFFF;
-
-define symbol m_data3_start = 0x80000000;
-define symbol m_data3_end = 0x81DFFFFF;
-
-define symbol m_ncache_start = 0x81E00000;
-define symbol m_ncache_end = 0x81FFFFFF;
-
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-define exported symbol __VECTOR_RAM = m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
-
-define memory mem with size = 4G;
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_text_start to m_text_end];
-
-define region DATA_region = mem:[from m_data_start to m_data_end];
-define region DATA2_region = mem:[from m_data2_start to m_data2_end];
-define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__];
-define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end];
-define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { first readwrite, section m_usb_dma_init_data };
-define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
-define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
-
-initialize by copy { readwrite, section .textrw };
-do not initialize { section .noinit };
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-
-place in TEXT_region { readonly };
-place in DATA3_region { block RW };
-place in DATA3_region { block ZI };
-place in DATA3_region { last block HEAP };
-place in CSTACK_region { block CSTACK };
-place in NCACHE_region { block NCACHE_VAR };
-
+/*
+** ###################################################################
+** Processors: MIMXRT1021CAF4A
+** MIMXRT1021CAG4A
+** MIMXRT1021DAF5A
+** MIMXRT1021DAG5A
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018
+** Version: rev. 0.1, 2017-06-06
+** Build: b180801
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2018 NXP
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x00000000;
+define symbol m_interrupts_end = 0x000003FF;
+
+define symbol m_text_start = 0x00000400;
+define symbol m_text_end = 0x0000FFFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x2000FFFF;
+
+define symbol m_data2_start = 0x20200000;
+define symbol m_data2_end = 0x2021FFFF;
+
+define symbol m_data3_start = 0x80000000;
+define symbol m_data3_end = 0x81DFFFFF;
+
+define symbol m_ncache_start = 0x81E00000;
+define symbol m_ncache_end = 0x81FFFFFF;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+
+define region DATA_region = mem:[from m_data_start to m_data_end];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end];
+define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end];
+define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { first readwrite, section m_usb_dma_init_data };
+define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
+define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
+
+initialize by copy { readwrite, section .textrw };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+
+place in TEXT_region { readonly };
+place in DATA3_region { block RW };
+place in DATA3_region { block ZI };
+place in DATA3_region { last block HEAP };
+place in CSTACK_region { block CSTACK };
+place in NCACHE_region { block NCACHE_VAR };
+
diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf
index b94c4e4939..827d248639 100644
--- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf
+++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf
@@ -1,89 +1,89 @@
-/*
-** ###################################################################
-** Processors: MIMXRT1021CAF4A
-** MIMXRT1021CAG4A
-** MIMXRT1021DAF5A
-** MIMXRT1021DAG5A
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018
-** Version: rev. 0.1, 2017-06-06
-** Build: b180801
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2018 NXP
-**
-** SPDX-License-Identifier: BSD-3-Clause
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** ###################################################################
-*/
-
-define symbol m_interrupts_start = 0x80000000;
-define symbol m_interrupts_end = 0x800003FF;
-
-define symbol m_text_start = 0x80000400;
-define symbol m_text_end = 0x801FFFFF;
-
-define symbol m_data_start = 0x20000000;
-define symbol m_data_end = 0x2000FFFF;
-
-define symbol m_data2_start = 0x20200000;
-define symbol m_data2_end = 0x2021FFFF;
-
-define symbol m_data3_start = 0x80200000;
-define symbol m_data3_end = 0x81DFFFFF;
-
-define symbol m_ncache_start = 0x81E00000;
-define symbol m_ncache_end = 0x81FFFFFF;
-
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-define exported symbol __VECTOR_RAM = m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
-
-define memory mem with size = 4G;
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_text_start to m_text_end];
-
-define region DATA_region = mem:[from m_data_start to m_data_end];
-define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__];
-define region DATA3_region = mem:[from m_data3_start to m_data3_end];
-define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end];
-define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { first readwrite, section m_usb_dma_init_data };
-define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
-define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
-
-initialize by copy { readwrite, section .textrw };
-do not initialize { section .noinit };
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-
-place in TEXT_region { readonly };
-place in DATA2_region { block RW };
-place in DATA2_region { block ZI };
-place in DATA2_region { last block HEAP };
-place in CSTACK_region { block CSTACK };
-place in NCACHE_region { block NCACHE_VAR };
-
+/*
+** ###################################################################
+** Processors: MIMXRT1021CAF4A
+** MIMXRT1021CAG4A
+** MIMXRT1021DAF5A
+** MIMXRT1021DAG5A
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018
+** Version: rev. 0.1, 2017-06-06
+** Build: b180801
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2018 NXP
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x80000000;
+define symbol m_interrupts_end = 0x800003FF;
+
+define symbol m_text_start = 0x80000400;
+define symbol m_text_end = 0x801FFFFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x2000FFFF;
+
+define symbol m_data2_start = 0x20200000;
+define symbol m_data2_end = 0x2021FFFF;
+
+define symbol m_data3_start = 0x80200000;
+define symbol m_data3_end = 0x81DFFFFF;
+
+define symbol m_ncache_start = 0x81E00000;
+define symbol m_ncache_end = 0x81FFFFFF;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+
+define region DATA_region = mem:[from m_data_start to m_data_end];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__];
+define region DATA3_region = mem:[from m_data3_start to m_data3_end];
+define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end];
+define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { first readwrite, section m_usb_dma_init_data };
+define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
+define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
+
+initialize by copy { readwrite, section .textrw };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+
+place in TEXT_region { readonly };
+place in DATA2_region { block RW };
+place in DATA2_region { block ZI };
+place in DATA2_region { last block HEAP };
+place in CSTACK_region { block CSTACK };
+place in NCACHE_region { block NCACHE_VAR };
+
diff --git a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds
index a0a306f370..d2f73ebaf0 100644
--- a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds
+++ b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds
@@ -86,9 +86,9 @@ SECTIONS
.ivt : AT(ivt_begin)
{
. = ALIGN(4);
- KEEP(* (.boot_hdr.ivt)) /* ivt section */
- KEEP(* (.boot_hdr.boot_data)) /* boot section */
- KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
+ KEEP(* (.boot_hdr.ivt)) /* ivt section */
+ KEEP(* (.boot_hdr.boot_data)) /* boot section */
+ KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
. = ALIGN(4);
} > m_ivt
@@ -278,7 +278,7 @@ SECTIONS
stack_end = .;
__StackTop = .;
} > m_data
-
+
.RTT_HEAP :
{
heap_start = .;
diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds
index 9942889d58..169a2d310a 100644
--- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds
+++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds
@@ -268,7 +268,7 @@ SECTIONS
stack_end = .;
__StackTop = .;
} > m_dtcm
-
+
.RTT_HEAP :
{
heap_start = .;
diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct
index 7b7bf4fbba..d179e6093f 100644
--- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct
+++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct
@@ -84,48 +84,48 @@
#if (defined(BSP_USING_4MFLASH))
LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region
-{
+{
RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
- {
+ {
* (.boot_hdr.conf, +FIRST)
- }
+ }
}
LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
-{
+{
RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
- {
+ {
* (.boot_hdr.ivt, +FIRST)
* (.boot_hdr.boot_data)
* (.boot_hdr.dcd_data)
- }
+ }
}
#endif
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
; load region size_region
-LR_IROM1 m_text_start m_text_size
-{
+LR_IROM1 m_text_start m_text_size
+{
ER_IROM1 m_text_start m_text_size ; load address = execution address
- {
+ {
* (RESET,+FIRST)
* (InRoot$$Sections)
.ANY (+RO)
}
-
+
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
- {
+ {
.ANY (+RW +ZI)
}
-
+
ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
; ncache RW data
- RW_m_ncache m_data2_start m_data2_size
- {
+ RW_m_ncache m_data2_start m_data2_size
+ {
* (NonCacheable.init)
* (NonCacheable)
}
diff --git a/bsp/juicevm/link.lds b/bsp/juicevm/link.lds
index b96558d7cd..74d01910b0 100755
--- a/bsp/juicevm/link.lds
+++ b/bsp/juicevm/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -35,7 +35,7 @@ SECTIONS
. = ALIGN(8);
- .text :
+ .text :
{
*(.text) /* remaining code */
*(.text.*) /* remaining code */
@@ -44,7 +44,7 @@ SECTIONS
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
-
+
/* section information for finsh shell */
. = ALIGN(8);
__fsymtab_start = .;
@@ -71,20 +71,20 @@ SECTIONS
_etext = .;
} > SRAM
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
*(.eh_frame_entry)
} > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
. = ALIGN(8);
- .data :
+ .data :
{
*(.data)
*(.data.*)
-
+
*(.data1)
*(.data1.*)
@@ -105,7 +105,7 @@ SECTIONS
__stack = .;
} > SRAM
- .sbss :
+ .sbss :
{
__bss_start = .;
*(.sbss)
diff --git a/bsp/juicevm/link_stacksize.lds b/bsp/juicevm/link_stacksize.lds
index 1dd893422c..28438c7da1 100755
--- a/bsp/juicevm/link_stacksize.lds
+++ b/bsp/juicevm/link_stacksize.lds
@@ -1 +1 @@
-__STACKSIZE__ = 4096;
\ No newline at end of file
+__STACKSIZE__ = 4096;
diff --git a/bsp/k210/link.lds b/bsp/k210/link.lds
index 60b39fb5f1..f37579c255 100644
--- a/bsp/k210/link.lds
+++ b/bsp/k210/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -35,7 +35,7 @@ SECTIONS
. = ALIGN(8);
- .text :
+ .text :
{
*(.text) /* remaining code */
*(.text.*) /* remaining code */
@@ -55,8 +55,8 @@ SECTIONS
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
-
-
+
+
/* section information for finsh shell */
. = ALIGN(8);
__fsymtab_start = .;
@@ -81,7 +81,7 @@ SECTIONS
__spi_func_end = .;
. = ALIGN(8);
-
+
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
@@ -90,20 +90,20 @@ SECTIONS
_etext = .;
} > SRAM
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
*(.eh_frame_entry)
} > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
. = ALIGN(8);
- .data :
+ .data :
{
*(.data)
*(.data.*)
-
+
*(.data1)
*(.data1.*)
@@ -117,7 +117,7 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
} > SRAM
/* stack for dual core */
@@ -133,7 +133,7 @@ SECTIONS
__stack_cpu1 = .;
} > SRAM
- .sbss :
+ .sbss :
{
__bss_start = .;
*(.sbss)
diff --git a/bsp/k210/link_stacksize.lds b/bsp/k210/link_stacksize.lds
index 1dd893422c..28438c7da1 100644
--- a/bsp/k210/link_stacksize.lds
+++ b/bsp/k210/link_stacksize.lds
@@ -1 +1 @@
-__STACKSIZE__ = 4096;
\ No newline at end of file
+__STACKSIZE__ = 4096;
diff --git a/bsp/loongson/ls1bdev/ls1b_ram.lds b/bsp/loongson/ls1bdev/ls1b_ram.lds
index a3419501c0..f5543822fc 100644
--- a/bsp/loongson/ls1bdev/ls1b_ram.lds
+++ b/bsp/loongson/ls1bdev/ls1b_ram.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/loongson/ls1cdev/ls1c_ram.lds b/bsp/loongson/ls1cdev/ls1c_ram.lds
index aced32b90b..6318cc7909 100644
--- a/bsp/loongson/ls1cdev/ls1c_ram.lds
+++ b/bsp/loongson/ls1cdev/ls1c_ram.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/loongson/ls2kdev/ls2k_ram.lds b/bsp/loongson/ls2kdev/ls2k_ram.lds
index 313a52969c..4d5ac94caf 100644
--- a/bsp/loongson/ls2kdev/ls2k_ram.lds
+++ b/bsp/loongson/ls2kdev/ls2k_ram.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -22,7 +22,7 @@ SECTIONS
__ebase_end = .;
start = .;
*(.start);
- . = ALIGN(4);
+ . = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
@@ -54,26 +54,26 @@ SECTIONS
__rt_utest_tc_tab_end = .;
. = ALIGN(4);
}
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
*(.eh_frame_entry)
}
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
. = ALIGN(4);
- .data :
+ .data :
{
*(.data)
*(.data.*)
-
+
*(.data1)
*(.data1.*)
. = ALIGN(8);
_gp = ABSOLUTE(.); /* Base of small data */
-
+
*(.sdata)
*(.sdata.*)
}
@@ -103,7 +103,7 @@ SECTIONS
_system_stack = .;
}
- .sbss :
+ .sbss :
{
__bss_start = .;
*(.sbss)
diff --git a/bsp/lpc1114/link.lds b/bsp/lpc1114/link.lds
index 19d0a053cb..90e5f47ed2 100644
--- a/bsp/lpc1114/link.lds
+++ b/bsp/lpc1114/link.lds
@@ -74,7 +74,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -95,7 +95,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end__ = .;
diff --git a/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf b/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf
index 0e0dc6efcf..7da727d4c7 100644
--- a/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf
+++ b/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
place in RAM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in AHB_RAM_region { section USB_RAM };
\ No newline at end of file
+place in AHB_RAM_region { section USB_RAM };
diff --git a/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf b/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf
index fba9952179..e68e2b0a62 100644
--- a/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf
+++ b/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf
@@ -32,4 +32,4 @@ place at address mem:0x2FC { section CRPKEY };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in AHB_RAM_region { section USB_RAM };
\ No newline at end of file
+place in AHB_RAM_region { section USB_RAM };
diff --git a/bsp/lpc2478/lpc2478_ram.lds b/bsp/lpc2478/lpc2478_ram.lds
index 28e8cdd7f5..d5c55a4ac5 100644
--- a/bsp/lpc2478/lpc2478_ram.lds
+++ b/bsp/lpc2478/lpc2478_ram.lds
@@ -3,7 +3,7 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
- . = 0xa0000000;
+ . = 0xa0000000;
__text_start = .;
.text :
@@ -17,14 +17,14 @@ SECTIONS
__rodata_start = .;
.rodata : { *(.rodata) *(.rodata.*) }
__rodata_end = .;
-
- . = 0xa0100000;
+
+ . = 0xa0100000;
. = ALIGN(8);
__data_start = .;
- .data :
- {
- *(.data)
- *(.data.*)
+ .data :
+ {
+ *(.data)
+ *(.data.*)
}
__data_end = .;
@@ -44,32 +44,32 @@ SECTIONS
__UndStack_start = __bss_end;
.UndStack : { *(.UndStack) }
__UndStack_end = ( __UndStack_start + 0x00000100 );
-
+
. = ALIGN(4);
__IRQStack_start = __UndStack_end;
.IRQStack : { *(.IRQStack) }
__IRQStack_end = ( __IRQStack_start + 0x00000100 );
-
+
. = ALIGN(4);
__FIQStack_start = __IRQStack_end;
.FIQStack : { *(.FIQStack) }
__FIQStack_end = ( __FIQStack_start + 0x00000100 );
-
+
. = ALIGN(4);
__SVCStack_start = __FIQStack_end;
.SVCStack : { *(.SVCStack) }
__SVCStack_end = ( __SVCStack_start + 0x00000100 );
-
+
. = ALIGN(4);
__ABTStack_start = __SVCStack_end;
.ABTStack : { *(.ABTStack) }
__ABTStack_end = ( __ABTStack_start + 0x00000100 );
-
+
. = ALIGN(4);
__USRStack_start = __ABTStack_end;
.USRStack : { *(.USRStack) }
__USRStack_end = ( __USRStack_start + 0x00003B00 );
-
+
. = ALIGN(4);
__Heap_start = __USRStack_end;
.Heap : { *(.Heap) }
diff --git a/bsp/lpc408x/drivers/linker_scripts/link.lds b/bsp/lpc408x/drivers/linker_scripts/link.lds
index ddf10a2c20..e9bfccfd74 100644
--- a/bsp/lpc408x/drivers/linker_scripts/link.lds
+++ b/bsp/lpc408x/drivers/linker_scripts/link.lds
@@ -58,9 +58,9 @@ SECTIONS
_etext = .;
} > CODE = 0
- .ARM.extab :
- {
- *(.ARM.extab*)
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
} > CODE
/* The .ARM.exidx section is used for C++ exception handling. */
@@ -98,7 +98,7 @@ SECTIONS
_edata = . ;
} > DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -118,7 +118,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
- _ebss = . ;
+ _ebss = . ;
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf
index 3eb7d6eeb8..5ba71403bc 100644
--- a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf
+++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf
@@ -15,7 +15,7 @@
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
-**
+**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted (subject to the limitations in the disclaimer below) provided
** that the following conditions are met:
diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf
index bc8768da39..59cc28d9de 100644
--- a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf
+++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf
@@ -15,7 +15,7 @@
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
-**
+**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted (subject to the limitations in the disclaimer below) provided
** that the following conditions are met:
diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf
index fb096f80b2..b338527500 100644
--- a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf
+++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf
@@ -15,7 +15,7 @@
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
-**
+**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted (subject to the limitations in the disclaimer below) provided
** that the following conditions are met:
diff --git a/bsp/lpc54114-lite/drivers/linker_scripts/link.icf b/bsp/lpc54114-lite/drivers/linker_scripts/link.icf
index b3f169d4a2..36a0c47ec9 100644
--- a/bsp/lpc54114-lite/drivers/linker_scripts/link.icf
+++ b/bsp/lpc54114-lite/drivers/linker_scripts/link.icf
@@ -15,7 +15,7 @@
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
-**
+**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted (subject to the limitations in the disclaimer below) provided
** that the following conditions are met:
diff --git a/bsp/lpc54114-lite/drivers/linker_scripts/link.lds b/bsp/lpc54114-lite/drivers/linker_scripts/link.lds
index e1fb7acd66..7158cf1563 100644
--- a/bsp/lpc54114-lite/drivers/linker_scripts/link.lds
+++ b/bsp/lpc54114-lite/drivers/linker_scripts/link.lds
@@ -14,7 +14,7 @@
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
-**
+**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted (subject to the limitations in the disclaimer below) provided
** that the following conditions are met:
@@ -243,7 +243,7 @@ SECTIONS
} > m_data
PROVIDE(heap_end = ORIGIN(m_data) + LENGTH(m_data));
-
+
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
diff --git a/bsp/lpc54608-LPCXpresso/link.lds b/bsp/lpc54608-LPCXpresso/link.lds
index 585e846084..799aa9e2a3 100644
--- a/bsp/lpc54608-LPCXpresso/link.lds
+++ b/bsp/lpc54608-LPCXpresso/link.lds
@@ -45,7 +45,7 @@ SECTIONS
. = ALIGN(4);
/* section information for modules */
-
+
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
@@ -73,9 +73,9 @@ SECTIONS
_etext = .;
} > CODE = 0
- .ARM.extab :
- {
- *(.ARM.extab*)
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
} > CODE
/* The .ARM.exidx section is used for C++ exception handling. */
@@ -113,7 +113,7 @@ SECTIONS
_edata = . ;
} > DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -133,7 +133,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
- _ebss = . ;
+ _ebss = . ;
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf
index 6be960151a..5d07ddcf8c 100644
--- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf
+++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf
@@ -62,8 +62,8 @@ if (isdefinedsymbol(__use_shmem__)) {
}
/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */
-define symbol m_veneer_table_start = 0x1000FE00;
-define symbol m_veneer_table_size = 0x200;
+define symbol m_veneer_table_start = 0x1000FE00;
+define symbol m_veneer_table_size = 0x200;
define symbol m_usb_sram_start = 0x50100000;
define symbol m_usb_sram_end = 0x50103FFF;
@@ -78,7 +78,7 @@ if (isdefinedsymbol(__use_shmem__)) {
define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end];
}
-define region VENEER_TABLE_region = mem:[from m_veneer_table_start to m_veneer_table_start + m_veneer_table_size - 1];
+define region VENEER_TABLE_region = mem:[from m_veneer_table_start to m_veneer_table_start + m_veneer_table_size - 1];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
@@ -113,7 +113,7 @@ place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in CSTACK_region { block CSTACK };
-place in VENEER_TABLE_region { section Veneer$$CMSE };
+place in VENEER_TABLE_region { section Veneer$$CMSE };
if (isdefinedsymbol(__use_shmem__)) {
place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section };
diff --git a/bsp/maxim/max32660-evsys/board/linker_scripts/link.lds b/bsp/maxim/max32660-evsys/board/linker_scripts/link.lds
index 4736a8d23f..d2f37d7fde 100644
--- a/bsp/maxim/max32660-evsys/board/linker_scripts/link.lds
+++ b/bsp/maxim/max32660-evsys/board/linker_scripts/link.lds
@@ -19,7 +19,7 @@ SECTIONS {
/* C++ Exception handling */
KEEP(*(.eh_frame*))
-
+
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
@@ -36,7 +36,7 @@ SECTIONS {
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
-
+
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
@@ -45,7 +45,7 @@ SECTIONS {
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
-
+
_etext = .;
} > FLASH
diff --git a/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf
index 892080e9f4..094445f31f 100644
--- a/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf
+++ b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf
@@ -14,9 +14,9 @@
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
- *
+ *
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf
index e6cc6d91d6..e134e0fa18 100644
--- a/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf
+++ b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf
@@ -14,9 +14,9 @@
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
- *
+ *
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf b/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf
index 5a1c3e3d18..afe1b5b622 100644
--- a/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf
+++ b/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf
@@ -14,9 +14,9 @@
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
- *
+ *
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf b/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf
index 5f8d451acd..b32871b650 100644
--- a/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf
+++ b/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf
@@ -14,9 +14,9 @@
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
- *
+ *
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/bsp/mini2440/rtthread-mini2440.sct b/bsp/mini2440/rtthread-mini2440.sct
index 5b0c1d734c..f55d975f1e 100644
--- a/bsp/mini2440/rtthread-mini2440.sct
+++ b/bsp/mini2440/rtthread-mini2440.sct
@@ -1,18 +1,18 @@
-LR_IROM1 0x30000000 0x1000000 {
- ER_IROM1 0x30000000 0x00200000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- RW_IRAM1 +0 { ; RW data
- .ANY (+RW)
- }
-
- ER_ZI +0 { ; ZI data
- .ANY (+ZI)
- }
-
- ER_MMU 0x33FF0000 EMPTY 0x00100000 {
- }
-}
+LR_IROM1 0x30000000 0x1000000 {
+ ER_IROM1 0x30000000 0x00200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 +0 { ; RW data
+ .ANY (+RW)
+ }
+
+ ER_ZI +0 { ; ZI data
+ .ANY (+ZI)
+ }
+
+ ER_MMU 0x33FF0000 EMPTY 0x00100000 {
+ }
+}
diff --git a/bsp/mini4020/rtthread-mini4020.sct b/bsp/mini4020/rtthread-mini4020.sct
index f491876a08..50f448280f 100644
--- a/bsp/mini4020/rtthread-mini4020.sct
+++ b/bsp/mini4020/rtthread-mini4020.sct
@@ -7,18 +7,18 @@
; *************************************************************
-LR_ROM1 0x30000000 0x0FFD00 ; load region size_region
- {
- ER_ROM1 0x30000000 0x0FFD00 ; load address = execution address
- {
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- RW_RAM1 0x30100000 0x100000 ; RW data
- {
- .ANY (+RW +ZI)
- }
+LR_ROM1 0x30000000 0x0FFD00 ; load region size_region
+ {
+ ER_ROM1 0x30000000 0x0FFD00 ; load address = execution address
+ {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_RAM1 0x30100000 0x100000 ; RW data
+ {
+ .ANY (+RW +ZI)
+ }
}
diff --git a/bsp/mipssim/mipssim_ram.lds b/bsp/mipssim/mipssim_ram.lds
index 196b6e8e02..98f11462c0 100644
--- a/bsp/mipssim/mipssim_ram.lds
+++ b/bsp/mipssim/mipssim_ram.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -22,7 +22,7 @@ SECTIONS
__ebase_end = .;
start = .;
*(.start);
- . = ALIGN(4);
+ . = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
@@ -54,26 +54,26 @@ SECTIONS
__rt_utest_tc_tab_end = .;
. = ALIGN(4);
}
-
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
*(.eh_frame_entry)
}
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
. = ALIGN(4);
- .data :
+ .data :
{
*(.data)
*(.data.*)
-
+
*(.data1)
*(.data1.*)
. = ALIGN(8);
_gp = ABSOLUTE(.); /* Base of small data */
-
+
*(.sdata)
*(.sdata.*)
}
@@ -86,7 +86,7 @@ SECTIONS
_system_stack = .;
}
- .sbss :
+ .sbss :
{
__bss_start = .;
*(.sbss)
diff --git a/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/iar/linker/mm32f3273g.icf b/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/iar/linker/mm32f3273g.icf
index 92ab6c7b93..a462e968ae 100644
--- a/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/iar/linker/mm32f3273g.icf
+++ b/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/iar/linker/mm32f3273g.icf
@@ -1,30 +1,30 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x800;
-define symbol __ICFEDIT_size_heap__ = 0x800;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/bsp/mm32/mm32f3270-100ask-pitaya/board/linker_scripts/link.icf b/bsp/mm32/mm32f3270-100ask-pitaya/board/linker_scripts/link.icf
index 92ab6c7b93..a462e968ae 100644
--- a/bsp/mm32/mm32f3270-100ask-pitaya/board/linker_scripts/link.icf
+++ b/bsp/mm32/mm32f3270-100ask-pitaya/board/linker_scripts/link.icf
@@ -1,30 +1,30 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x800;
-define symbol __ICFEDIT_size_heap__ = 0x800;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/bsp/mm32f103x/drivers/linker_scripts/link.lds b/bsp/mm32f103x/drivers/linker_scripts/link.lds
index aad42bdb39..21222812c4 100644
--- a/bsp/mm32f103x/drivers/linker_scripts/link.lds
+++ b/bsp/mm32f103x/drivers/linker_scripts/link.lds
@@ -73,7 +73,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -94,7 +94,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/mm32f327x/drivers/linker_scripts/link.lds b/bsp/mm32f327x/drivers/linker_scripts/link.lds
index aad42bdb39..21222812c4 100644
--- a/bsp/mm32f327x/drivers/linker_scripts/link.lds
+++ b/bsp/mm32f327x/drivers/linker_scripts/link.lds
@@ -73,7 +73,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -94,7 +94,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/mm32l07x/drivers/linker_scripts/link.lds b/bsp/mm32l07x/drivers/linker_scripts/link.lds
index c7b5f1be0b..1aea6643d9 100644
--- a/bsp/mm32l07x/drivers/linker_scripts/link.lds
+++ b/bsp/mm32l07x/drivers/linker_scripts/link.lds
@@ -73,7 +73,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -94,7 +94,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/mm32l3xx/drivers/linker_scripts/link.lds b/bsp/mm32l3xx/drivers/linker_scripts/link.lds
index aad42bdb39..21222812c4 100644
--- a/bsp/mm32l3xx/drivers/linker_scripts/link.lds
+++ b/bsp/mm32l3xx/drivers/linker_scripts/link.lds
@@ -73,7 +73,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -94,7 +94,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.icf b/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.icf
index 5cb78a4d65..84dd3b35a1 100644
--- a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.lds b/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.lds
index d0355f22ad..9a8fd415eb 100644
--- a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.icf b/bsp/n32/n32g457qel-stb/board/linker_scripts/link.icf
index 4f961659c1..0b160ea127 100644
--- a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32g457qel-stb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.lds b/bsp/n32/n32g457qel-stb/board/linker_scripts/link.lds
index caf3947f1a..25f4bd25ba 100644
--- a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32g457qel-stb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.icf b/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.icf
index 35a1d043e8..473fd1b2af 100644
--- a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.lds b/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.lds
index 6561a7249d..c64fe82311 100644
--- a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.icf b/bsp/n32/n32g45xml-stb/board/linker_scripts/link.icf
index 4f961659c1..0b160ea127 100644
--- a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32g45xml-stb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.lds b/bsp/n32/n32g45xml-stb/board/linker_scripts/link.lds
index caf3947f1a..25f4bd25ba 100644
--- a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32g45xml-stb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.icf b/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.icf
index 4f961659c1..0b160ea127 100644
--- a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.lds b/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.lds
index caf3947f1a..25f4bd25ba 100644
--- a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.icf b/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.icf
index 4f961659c1..0b160ea127 100644
--- a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.lds b/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.lds
index caf3947f1a..25f4bd25ba 100644
--- a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.icf b/bsp/n32/n32g4frml-stb/board/linker_scripts/link.icf
index 4f961659c1..0b160ea127 100644
--- a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32g4frml-stb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.lds b/bsp/n32/n32g4frml-stb/board/linker_scripts/link.lds
index a96bb81398..2cb0afe87a 100644
--- a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32g4frml-stb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.icf b/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.icf
index 3228ad860e..d23ad8b48e 100644
--- a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.lds b/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.lds
index b52bb21de0..27940ba15a 100644
--- a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32l436-evb/board/linker_scripts/link.icf b/bsp/n32/n32l436-evb/board/linker_scripts/link.icf
index 5cb78a4d65..84dd3b35a1 100644
--- a/bsp/n32/n32l436-evb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32l436-evb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32l436-evb/board/linker_scripts/link.lds b/bsp/n32/n32l436-evb/board/linker_scripts/link.lds
index c495e70a2a..085daeeab9 100644
--- a/bsp/n32/n32l436-evb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32l436-evb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.icf b/bsp/n32/n32l43xml-stb/board/linker_scripts/link.icf
index 5cb78a4d65..84dd3b35a1 100644
--- a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32l43xml-stb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.lds b/bsp/n32/n32l43xml-stb/board/linker_scripts/link.lds
index c495e70a2a..085daeeab9 100644
--- a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32l43xml-stb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.icf b/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.icf
index 5cb78a4d65..84dd3b35a1 100644
--- a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.lds b/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.lds
index c495e70a2a..085daeeab9 100644
--- a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.icf b/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.icf
index 6644872295..4ff561f605 100644
--- a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.icf
+++ b/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.icf
@@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
-place in RAM1_region { section .sram };
\ No newline at end of file
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
diff --git a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.lds b/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.lds
index 17a441e711..9545672994 100644
--- a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.lds
+++ b/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.lds
@@ -78,7 +78,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds b/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds
index 0865f58953..5f69cf3a14 100755
--- a/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds
+++ b/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds b/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds
index 2a0443924f..a97906e19f 100644
--- a/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds
+++ b/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds
@@ -38,7 +38,7 @@ SECTIONS
*(.rodata*)
KEEP(*(.eh_frame*))
- /* section information for finsh shell */
+ /* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
@@ -121,7 +121,7 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
} > RAM
-
+
.heap (COPY):
{
__HeapBase = .;
@@ -147,13 +147,13 @@ SECTIONS
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
+
/* Check if text sections + data exceeds FLASH limit */
DataInitFlashUsed = __bss_start__ - __data_start__;
CodeFlashUsed = __etext - ORIGIN(FLASH);
TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed;
ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data")
-
+
}
diff --git a/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds b/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds
index f4cf7ebbf7..ae7d91fb5e 100644
--- a/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds
+++ b/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds
@@ -49,7 +49,7 @@ SECTIONS
__rtmsymtab_end = .;
. = ALIGN(4);
-
+
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds b/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds
index e699e0079a..e3fea7bd3a 100644
--- a/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds
+++ b/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds
@@ -38,7 +38,7 @@ SECTIONS
*(.rodata*)
KEEP(*(.eh_frame*))
- /* section information for finsh shell */
+ /* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
@@ -121,7 +121,7 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
} > RAM
-
+
.heap (COPY):
{
__HeapBase = .;
@@ -147,13 +147,13 @@ SECTIONS
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
+
/* Check if text sections + data exceeds FLASH limit */
DataInitFlashUsed = __bss_start__ - __data_start__;
CodeFlashUsed = __etext - ORIGIN(FLASH);
TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed;
ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data")
-
+
}
diff --git a/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds b/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds
index e699e0079a..e3fea7bd3a 100644
--- a/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds
+++ b/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds
@@ -38,7 +38,7 @@ SECTIONS
*(.rodata*)
KEEP(*(.eh_frame*))
- /* section information for finsh shell */
+ /* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
@@ -121,7 +121,7 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
} > RAM
-
+
.heap (COPY):
{
__HeapBase = .;
@@ -147,13 +147,13 @@ SECTIONS
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
+
/* Check if text sections + data exceeds FLASH limit */
DataInitFlashUsed = __bss_start__ - __data_start__;
CodeFlashUsed = __etext - ORIGIN(FLASH);
TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed;
ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data")
-
+
}
diff --git a/bsp/nrf5x/nrf5340/board/linker_scripts/link.lds b/bsp/nrf5x/nrf5340/board/linker_scripts/link.lds
index d7fcb7c7dc..7f2592b316 100644
--- a/bsp/nrf5x/nrf5340/board/linker_scripts/link.lds
+++ b/bsp/nrf5x/nrf5340/board/linker_scripts/link.lds
@@ -38,7 +38,7 @@ SECTIONS
*(.rodata*)
KEEP(*(.eh_frame*))
- /* section information for finsh shell */
+ /* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
@@ -63,14 +63,14 @@ SECTIONS
PROVIDE(__ctors_end__ = .);
} > FLASH
-
- .nrf_queue :
- {
- PROVIDE(__start_nrf_queue = .);
- KEEP(*(.nrf_balloc))
- PROVIDE(__stop_nrf_queue = .);
- } > FLASH
-
+
+ .nrf_queue :
+ {
+ PROVIDE(__start_nrf_queue = .);
+ KEEP(*(.nrf_balloc))
+ PROVIDE(__stop_nrf_queue = .);
+ } > FLASH
+
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -128,7 +128,7 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
} > RAM
-
+
.heap (COPY):
{
__HeapBase = .;
@@ -154,13 +154,13 @@ SECTIONS
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
+
/* Check if text sections + data exceeds FLASH limit */
DataInitFlashUsed = __bss_start__ - __data_start__;
CodeFlashUsed = __etext - ORIGIN(FLASH);
TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed;
ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data")
-
+
}
diff --git a/bsp/nuvoton/numaker-m032ki/linking_scripts/m031_flash.icf b/bsp/nuvoton/numaker-m032ki/linking_scripts/m031_flash.icf
index 5c594d150f..2b50d070da 100644
--- a/bsp/nuvoton/numaker-m032ki/linking_scripts/m031_flash.icf
+++ b/bsp/nuvoton/numaker-m032ki/linking_scripts/m031_flash.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, block CSTACK };
\ No newline at end of file
+place in RAM_region { readwrite, block CSTACK };
diff --git a/bsp/phytium/aarch32/link.lds b/bsp/phytium/aarch32/link.lds
index d1acac738f..0e7194b9ea 100644
--- a/bsp/phytium/aarch32/link.lds
+++ b/bsp/phytium/aarch32/link.lds
@@ -12,7 +12,7 @@ SECTIONS
*(.boot)
. = ALIGN(64);
-
+
*(.vectors)
*(.text)
*(.text.*)
diff --git a/bsp/phytium/aarch64/link.lds b/bsp/phytium/aarch64/link.lds
index 86bb78e88e..2e4b2ef10b 100644
--- a/bsp/phytium/aarch64/link.lds
+++ b/bsp/phytium/aarch64/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -108,7 +108,7 @@ SECTIONS
PROVIDE(__heap_start = .);
. = ALIGN(8);
PROVIDE(end = .);
- }
+ }
_end = .;
@@ -147,4 +147,4 @@ SECTIONS
.debug_varnames 0 : { *(.debug_varnames) }
}
-__bss_size = SIZEOF(.bss);
\ No newline at end of file
+__bss_size = SIZEOF(.bss);
diff --git a/bsp/qemu-virt64-riscv/link.lds b/bsp/qemu-virt64-riscv/link.lds
index b0d6a6aed5..a76fed4fa3 100644
--- a/bsp/qemu-virt64-riscv/link.lds
+++ b/bsp/qemu-virt64-riscv/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -37,7 +37,7 @@ SECTIONS
. = ALIGN(8);
- .text :
+ .text :
{
*(.text) /* remaining code */
*(.text.*) /* remaining code */
@@ -46,7 +46,7 @@ SECTIONS
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
-
+
/* section information for finsh shell */
. = ALIGN(8);
__fsymtab_start = .;
@@ -73,9 +73,9 @@ SECTIONS
_etext = .;
} > SRAM
- .eh_frame_hdr :
- {
- *(.eh_frame_hdr)
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
*(.eh_frame_entry)
} > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
@@ -84,11 +84,11 @@ SECTIONS
__text_end = .;
__text_size = __text_end - __text_start;
- .data :
+ .data :
{
*(.data)
*(.data.*)
-
+
*(.data1)
*(.data1.*)
@@ -129,7 +129,7 @@ SECTIONS
__stack_cpu1 = .;
} > SRAM
- .sbss :
+ .sbss :
{
__bss_start = .;
*(.sbss)
diff --git a/bsp/qemu-virt64-riscv/link_stacksize.lds b/bsp/qemu-virt64-riscv/link_stacksize.lds
index 8685bc0f1c..14c2aad91f 100644
--- a/bsp/qemu-virt64-riscv/link_stacksize.lds
+++ b/bsp/qemu-virt64-riscv/link_stacksize.lds
@@ -1 +1 @@
-__STACKSIZE__ = 16384;
\ No newline at end of file
+__STACKSIZE__ = 16384;
diff --git a/bsp/raspberry-pi/raspi2/link.lds b/bsp/raspberry-pi/raspi2/link.lds
index 71c92384fa..2ba97172e2 100644
--- a/bsp/raspberry-pi/raspi2/link.lds
+++ b/bsp/raspberry-pi/raspi2/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/raspberry-pi/raspi3-32/link.lds b/bsp/raspberry-pi/raspi3-32/link.lds
index 71c92384fa..2ba97172e2 100644
--- a/bsp/raspberry-pi/raspi3-32/link.lds
+++ b/bsp/raspberry-pi/raspi3-32/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/raspberry-pi/raspi3-64/link.lds b/bsp/raspberry-pi/raspi3-64/link.lds
index d03d0bd42e..953be4c28b 100644
--- a/bsp/raspberry-pi/raspi3-64/link.lds
+++ b/bsp/raspberry-pi/raspi3-64/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/raspberry-pi/raspi4-32/link.lds b/bsp/raspberry-pi/raspi4-32/link.lds
index 344c765acc..c1a5b9e1b1 100644
--- a/bsp/raspberry-pi/raspi4-32/link.lds
+++ b/bsp/raspberry-pi/raspi4-32/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/raspberry-pi/raspi4-64/link.lds b/bsp/raspberry-pi/raspi4-64/link.lds
index d03d0bd42e..953be4c28b 100644
--- a/bsp/raspberry-pi/raspi4-64/link.lds
+++ b/bsp/raspberry-pi/raspi4-64/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/rockchip/rk3568/link.lds b/bsp/rockchip/rk3568/link.lds
index 6401f4a40d..dd62ae35d0 100644
--- a/bsp/rockchip/rk3568/link.lds
+++ b/bsp/rockchip/rk3568/link.lds
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/rx/lnkr5f562n8.icf b/bsp/rx/lnkr5f562n8.icf
index 38790c05d5..318aae8914 100644
--- a/bsp/rx/lnkr5f562n8.icf
+++ b/bsp/rx/lnkr5f562n8.icf
@@ -34,17 +34,17 @@ place at address mem:0xFFFFFF80 { ro section .nmivec };
ro section .data24* };
"RAM24":place in RAM_region24 { rw section .data24* };
"ROM32":place in ROM_region32 { ro,
- ro section FSymTab,
- ro section VSymTab,
- ro section .rti_fn*,
- };
+ ro section FSymTab,
+ ro section VSymTab,
+ ro section .rti_fn*,
+ };
"RAM32":place in RAM_region32 { rw,
ro section D,
ro section D_1,
ro section D_2,
block STACKS,
- block HEAP,
- };
+ block HEAP,
+ };
"DATAFLASH":place in DATA_FLASH_region
{ ro section .dataflash* };
diff --git a/bsp/sam7x/sam7x_rom.sct b/bsp/sam7x/sam7x_rom.sct
index 13999ef666..67809e950b 100644
--- a/bsp/sam7x/sam7x_rom.sct
+++ b/bsp/sam7x/sam7x_rom.sct
@@ -1,15 +1,15 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x00100000 0x00040000 { ; load region size_region
- ER_IROM1 0x00100000 0x00040000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- RW_IRAM1 0x00200000 0x00010000 { ; RW data
- .ANY (+RW +ZI)
- }
-}
-
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00100000 0x00040000 { ; load region size_region
+ ER_IROM1 0x00100000 0x00040000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x00200000 0x00010000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf
index b7499054a9..477c3882bb 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf
@@ -1,79 +1,79 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD20E18
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
- /**
- * Support and FAQ: visit Atmel Support
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x2000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20E18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit Atmel Support
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf
index ebe618f943..14979c650c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD20E18
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
- /**
- * Support and FAQ: visit Atmel Support
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x2000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20E18
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit Atmel Support
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf
index bbbfad223e..9f340f2fda 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf
@@ -1,79 +1,79 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD20G17U
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
- /**
- * Support and FAQ: visit Atmel Support
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x1000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G17U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit Atmel Support
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf
index 7118d0745b..fd0412701a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD20G17U
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
- /**
- * Support and FAQ: visit Atmel Support
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x1000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G17U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit Atmel Support
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf
index fdde4065aa..0ea7273bc4 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf
@@ -1,79 +1,79 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD20G18U
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
- /**
- * Support and FAQ: visit Atmel Support
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x2000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD20G18U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit Atmel Support
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf
index 9b9d2a518b..f0637d84d3 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD20G18U
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
- /**
- * Support and FAQ: visit Atmel Support
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x2000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD20G18U
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /**
+ * Support and FAQ: visit Atmel Support
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf
index c0f9fa5ce9..ad32c4fc8a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21E15B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf
index a4cd4d1777..04a342f4a3 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21E15B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf
index 1df26bf7e1..cb33811b17 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21E15BU
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf
index 998c94a680..1da3da45a5 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21E15BU
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf
index 8c7d6cdc1c..4750e7371c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21E15L
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf
index 7bf9184da8..893a4b9f56 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21E15L
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf
index bb14fd7ef0..319bc85ac9 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21E16B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf
index f608892d1b..8195284914 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21E16B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf
index a0dfd30410..5b15689db5 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21E16BU
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf
index 1d49c0ed4c..0f68efa0dd 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21E16BU
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf
index 343b46fb3b..c63dd3c6ed 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21E16L
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf
index cc2524f0c3..75619e7d36 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21E16L
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16L
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf
index e0cd4f40ed..8497ded2e9 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21E18A
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x2000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf
index a46e7c87d0..e3b59d9990 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21E18A
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x2000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf
index 4bba7c0c7a..df519af26a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G15A
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf
index 2b42ca0d8f..112262215f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21G15A
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf
index c2ef3389e9..c71c51393c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G15B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf
index b8dbdaae9b..0a70c80dcb 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21G15B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf
index 161d96c214..54f8578fd3 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G15L
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf
index fe382e12b6..2cf0f8a342 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21G15L
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf
index c5de64da26..b018c1ad7e 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G16B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf
index 22bb2eaa10..7f92977e71 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21G16B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf
index a6807c1227..ed480c4bad 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G16L
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf
index e8b76d4dd5..6180f15460 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21G16L
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf
index 300b38d563..3356435625 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G17AU
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x1000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf
index c48c77daf9..a7c91496a1 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21G17AU
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x1000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf
index 403160016c..b5fba1db04 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G18AU
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x2000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf
index 34bfdb06e4..19c6491b87 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21G18AU
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x2000;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf
index 63eaab0f55..3a7b1c926f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21J15A
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf
index 778ea6dcef..de97081778 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21J15A
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J15A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf
index 82d992b66a..231c466fe8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21J15B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf
index 49cf464df6..468fae24c7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21J15B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x400;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J15B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf
index d7f04148e8..62894fe1f5 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21J16B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf
index 05dfb6888a..f301ed8623 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf
@@ -1,73 +1,73 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAMD21J16B
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
-/*-Sizes-*/
-if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
- define symbol __ICFEDIT_size_cstack__ = 0x800;
-}
-if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
- define symbol __ICFEDIT_size_heap__ = 0x0;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy with packing=none { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in RAM_region { readonly };
-place in RAM_region { readwrite };
-place at end of RAM_region { block CSTACK, block HEAP };
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J16B
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+ define symbol __ICFEDIT_size_heap__ = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite };
+place at end of RAM_region { block CSTACK, block HEAP };
diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct
index 3d214ad675..50ab6f8dff 100644
--- a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct
+++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct
@@ -1,7 +1,7 @@
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for debugging code executing in internal eSRAM.
-;
+;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
@@ -23,7 +23,7 @@
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
-; eNVM=256KB eRAM=64KB External memory = 64MB
+; eNVM=256KB eRAM=64KB External memory = 64MB
RAM_LOAD 0x20000000 0x10000
{
@@ -35,10 +35,10 @@ RAM_LOAD 0x20000000 0x10000
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
- ; Heap will be added after RW data in ER_RW unless explicitly
+ ; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
- ; Stack will be added after heap in ER_RW unless explicitly
+ ; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file
; Second half of RAM allocated to RW data, heap and stack
ER_RW 0x20008000 0x8000
diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct
index e5663e79b5..5c2fd504d8 100644
--- a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct
+++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct
@@ -1,7 +1,7 @@
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for executing code in internal eNVM.
-;
+;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
@@ -23,22 +23,22 @@
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
-; eNVM=256KB eRAM=64KB External memory = 64MB
+; eNVM=256KB eRAM=64KB External memory = 64MB
-FLASH_LOAD 0x00000000 0x40000
+FLASH_LOAD 0x00000000 0x40000
{
; All R only code/data is located in ENVM
ER_RO 0x00000000 0x40000
{
- *.o (RESET, +First)
+ *.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
-; Heap will be added after RW data in ER_RW unless explicitly
+; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
-; Stack will be added after heap in ER_RW unless explicitly
+; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file
ER_RW 0x20000000 0x10000
{
diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct
index b2cb935927..3f6ee574cd 100644
--- a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct
+++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct
@@ -1,7 +1,7 @@
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for debugging code executing in external MDDR.
-;
+;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
@@ -23,7 +23,7 @@
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
-; eNVM=256KB eRAM=64KB External memory = 64MB
+; eNVM=256KB eRAM=64KB External memory = 64MB
; Extern RAM 64M in total
; allocate 1/2 to progam, 1/2 to variable data
@@ -37,10 +37,10 @@ RAM_LOAD 0x00000000 0x04000000
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
- ; Heap will be added after RW data in ER_RW unless explicitly
+ ; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
- ; Stack will be added after heap in ER_RW unless explicitly
+ ; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file as is the case below
STACKS 0x20000000 UNINIT
{
diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct
index 3769a8cda3..293a1e4bed 100644
--- a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct
+++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct
@@ -1,7 +1,7 @@
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for relocating code to external RAM.
-;
+;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
@@ -23,7 +23,7 @@
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
-; eNVM=256KB eRAM=64KB External memory = 64MB
+; eNVM=256KB eRAM=64KB External memory = 64MB
FLASH_LOAD 0x60000000 0x40000
{
@@ -36,23 +36,23 @@ FLASH_LOAD 0x60000000 0x40000
system_m2sxxx.o
sys_config.o
low_level_init.o
- sys_config_SERDESIF_?.o
- mscc_post_hw_cfg_init.o
- ecc_error_handler.o
+ sys_config_SERDESIF_?.o
+ mscc_post_hw_cfg_init.o
+ ecc_error_handler.o
}
- ; MDDR_RAM 0xA0000000 0x4000000
+ ; MDDR_RAM 0xA0000000 0x4000000
; -MDDR is mapped to address space from 0 on startup
; This allows the use of cache which is restriced to this area.
; Code is copied to RAM_EXEC space on startup by boot code.
- RAM_EXEC 0x00000000 0x00040000
+ RAM_EXEC 0x00000000 0x00040000
{
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
- ; Heap will be added after RW data in ER_RW unless explicitly
+ ; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
- ; Stack will be added after heap in ER_RW unless explicitly
+ ; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file as is the case below
STACKS 0x20000000 UNINIT
{
diff --git a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds
index 90415e319a..3cd3180273 100644
--- a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds
+++ b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds
@@ -30,7 +30,7 @@ SECTIONS
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
-
+
/* section information for finsh shell */
. = ALIGN(4);
diff --git a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds
index 54c102641e..c571a0f876 100644
--- a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds
+++ b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds
@@ -1 +1 @@
-../coreplexip-e31-arty/flash.lds
\ No newline at end of file
+../coreplexip-e31-arty/flash.lds
diff --git a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds
index 7fbe10a3ea..f7f33b8de2 100644
--- a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds
+++ b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds
@@ -1 +1 @@
-../coreplexip-e31-arty/scratchpad.lds
\ No newline at end of file
+../coreplexip-e31-arty/scratchpad.lds
diff --git a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds
index 6441ce598f..9661121ef7 100644
--- a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds
+++ b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds
@@ -1 +1 @@
-../freedom-e300-hifive1/flash.lds
\ No newline at end of file
+../freedom-e300-hifive1/flash.lds
diff --git a/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f091xc_sram.icf b/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f091xc_sram.icf
index 3fb0651395..15980fec45 100644
--- a/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f091xc_sram.icf
+++ b/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f091xc_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f098xx_sram.icf b/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f098xx_sram.icf
index 3fb0651395..15980fec45 100644
--- a/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f098xx_sram.icf
+++ b/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f098xx_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf
index 13405854d1..7c0037531b 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf
index 1b5ef5a4b9..c39a043bae 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf
index eb2bb9d7d8..e48eda5767 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf
index 90208d57df..ed4fb445f7 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf
index 515e779c46..c49e25fa40 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf
index 6f209f2e35..16414a9a3e 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf
index 5f1e44027f..7a80276f73 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf
index 13405854d1..7c0037531b 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf
index 515e779c46..c49e25fa40 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf
index 515e779c46..c49e25fa40 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf
index 6f209f2e35..16414a9a3e 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf
index dbfbec286e..1ff96727b2 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf
index dbfbec286e..1ff96727b2 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf
index 5f1e44027f..7a80276f73 100644
--- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xc_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xc_flash.icf
index b6029122d3..0d442b2807 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xc_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xc_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xe_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xe_flash.icf
index a071d017d9..213647e5d7 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xe_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xe_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f405xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f405xx_flash.icf
index 88462334e2..1758878ffd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f405xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f405xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f407xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f407xx_flash.icf
index 88462334e2..1758878ffd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f407xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f407xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410cx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410cx_flash.icf
index 0758c01716..edad34cb66 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410cx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410cx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410rx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410rx_flash.icf
index 0758c01716..edad34cb66 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410rx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410rx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410tx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410tx_flash.icf
index 0758c01716..edad34cb66 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410tx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410tx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f411xe_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f411xe_flash.icf
index 6c3a139ad9..5209ada3ae 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f411xe_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f411xe_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412cx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412cx_flash.icf
index 6ef8277a43..5e592d0956 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412cx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412cx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412rx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412rx_flash.icf
index 6ef8277a43..5e592d0956 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412rx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412rx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412vx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412vx_flash.icf
index 6ef8277a43..5e592d0956 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412vx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412vx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412zx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412zx_flash.icf
index 6ef8277a43..5e592d0956 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412zx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412zx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f413xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f413xx_flash.icf
index 068644aade..688e56519a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f413xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f413xx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f415xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f415xx_flash.icf
index 88462334e2..1758878ffd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f415xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f415xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f417xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f417xx_flash.icf
index 88462334e2..1758878ffd 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f417xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f417xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f423xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f423xx_flash.icf
index 068644aade..688e56519a 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f423xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f423xx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_flash.icf
index 8d2caf0218..509203dae0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_flash.icf
index 8d2caf0218..509203dae0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_flash.icf
index 8d2caf0218..509203dae0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f439xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f439xx_flash.icf
index 8d2caf0218..509203dae0 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f439xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f439xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f446xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f446xx_flash.icf
index 6c3a139ad9..5209ada3ae 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f446xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f446xx_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f469xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f469xx_flash.icf
index 8887acdc17..0a2d4db599 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f469xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f469xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f479xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f479xx_flash.icf
index 8887acdc17..0a2d4db599 100644
--- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f479xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f479xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf
index e846ed657b..ba273774c6 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf
index 6907b2ba22..dcb8691c1c 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf
index e846ed657b..ba273774c6 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf
index 6907b2ba22..dcb8691c1c 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_ITCM_flash.icf
index 9195b7dc11..588364a9ca 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_flash.icf
index 4fe1321962..75e56e2726 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf
index e846ed657b..ba273774c6 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf
index 6907b2ba22..dcb8691c1c 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf
index e846ed657b..ba273774c6 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf
index 6907b2ba22..dcb8691c1c 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf
index d7482e4bff..df31425288 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf
index 8c407835b9..b16979544b 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf
index d7482e4bff..df31425288 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf
index 8c407835b9..b16979544b 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_ITCM_flash.icf
index 73781e04c6..56039bd9c8 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_flash.icf
index dc1d0dab08..2b2cefe064 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf
index d7482e4bff..df31425288 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf
index 8c407835b9..b16979544b 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf
index 4b64e00aaf..366561f53a 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf
index 909fe02b3a..8e410e58e6 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf
index 4b64e00aaf..366561f53a 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf
index 909fe02b3a..8e410e58e6 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf
index 4b64e00aaf..366561f53a 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf
index 909fe02b3a..8e410e58e6 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf
index 4b64e00aaf..366561f53a 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf
index 909fe02b3a..8e410e58e6 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf
index 4b64e00aaf..366561f53a 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in ITCMRAM_region { };
\ No newline at end of file
+place in ITCMRAM_region { };
diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf
index 909fe02b3a..8e410e58e6 100644
--- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf
+++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_flash.icf
index ac19dec3da..397a960ef4 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_flash.icf
@@ -30,4 +30,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_sram.icf
index b02c6b1489..831df87606 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_flash.icf
index ac19dec3da..397a960ef4 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_flash.icf
@@ -30,4 +30,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_sram.icf
index b02c6b1489..831df87606 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_flash.icf
index ac19dec3da..397a960ef4 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_flash.icf
@@ -30,4 +30,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_sram.icf
index b02c6b1489..831df87606 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_flash.icf
index e37d1888f8..ce8f039c38 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_flash.icf
@@ -30,4 +30,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_sram.icf
index d640cad32b..0c92b30afc 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_flash.icf
index e37d1888f8..ce8f039c38 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_flash.icf
@@ -30,4 +30,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_sram.icf
index d640cad32b..0c92b30afc 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_flash.icf
index e37d1888f8..ce8f039c38 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_flash.icf
@@ -30,4 +30,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_sram.icf
index d640cad32b..0c92b30afc 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_flash.icf
index 687d9e51dc..d2657b8733 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_flash.icf
@@ -30,4 +30,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_sram.icf
index ea3df3ff87..0d1b532169 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_flash.icf
index 687d9e51dc..d2657b8733 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_flash.icf
@@ -30,4 +30,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_sram.icf
index ea3df3ff87..0d1b532169 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_flash.icf
index 687d9e51dc..d2657b8733 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_flash.icf
@@ -30,4 +30,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_sram.icf
index 67dc6c1b99..3b8cf65d3a 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_flash.icf
index ee2ad5f713..34555c70e4 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_flash.icf
@@ -31,4 +31,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_sram.icf
index 25c78d83a5..dceb24ccf8 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_flash.icf
index ee2ad5f713..34555c70e4 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_flash.icf
@@ -31,4 +31,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_sram.icf
index 25c78d83a5..dceb24ccf8 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_flash.icf
index ee2ad5f713..34555c70e4 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_flash.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_flash.icf
@@ -31,4 +31,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
+export symbol __ICFEDIT_region_RAM_end__;
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_sram.icf
index 25c78d83a5..dceb24ccf8 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_sram.icf
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf
index d8ee3b29a0..120e408800 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf
index c13609a56c..786b5309fa 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf
index 36299129c2..6fac414de8 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf
index 36299129c2..6fac414de8 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf
index c13609a56c..786b5309fa 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf
index 06dda3fb48..0a311b3b98 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf
index 7e0c766318..25107b9c73 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf
index 5700b38c90..a36d5107d7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf
index 5700b38c90..a36d5107d7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf
index 7e0c766318..25107b9c73 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf
index d8ee3b29a0..120e408800 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf
index c13609a56c..786b5309fa 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf
index 36299129c2..6fac414de8 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf
index 36299129c2..6fac414de8 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf
index c13609a56c..786b5309fa 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf
index 06dda3fb48..0a311b3b98 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf
index 7e0c766318..25107b9c73 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf
index 5700b38c90..a36d5107d7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf
index 5700b38c90..a36d5107d7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf
index 7e0c766318..25107b9c73 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf
index bac75da3f6..775795c3ef 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf
index 43d3b0e5dc..580ff62f6d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf
index 8a239fda65..5e845c1ea8 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf
index 8a239fda65..5e845c1ea8 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf
index 43d3b0e5dc..580ff62f6d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf
index bac75da3f6..775795c3ef 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf
index 43d3b0e5dc..580ff62f6d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf
index 8a239fda65..5e845c1ea8 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf
index 8a239fda65..5e845c1ea8 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf
index 43d3b0e5dc..580ff62f6d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf
index 06dda3fb48..0a311b3b98 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf
index 7e0c766318..25107b9c73 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf
index 5700b38c90..a36d5107d7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf
index 5700b38c90..a36d5107d7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf
index 7e0c766318..25107b9c73 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf
index 06dda3fb48..0a311b3b98 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf
index 7e0c766318..25107b9c73 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf
index 5700b38c90..a36d5107d7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf
index 5700b38c90..a36d5107d7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf
index 7e0c766318..25107b9c73 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf
index 8181a07b57..d220fad4a0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf
index 178e68833c..2f746c0de0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf
@@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf
index 3ff287d162..9cdf4e896a 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf
@@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf
index 90448efaa8..801b290542 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf
@@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf
index e9acc00ccd..4030ade196 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf
index 97b074590e..569b1b1f39 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf
index 4580655b71..ebec5e3d12 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf
index 7dbb925a5c..0a45c8f05d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf
index 178e68833c..2f746c0de0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf
@@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf
index 2592f281f7..b99ff58e2a 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf
@@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf
index b8aeb0e44a..f14c7979b7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf
@@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf
index e9acc00ccd..4030ade196 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf
index fabf1a576e..acf62a20af 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf
index 40be3e00d9..b882a4708d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf
index d507b31e08..26e370a493 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf
index 43db630fe0..1d13de71f0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf
index d8ee3b29a0..120e408800 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf
index 60c963fe2b..55f2bd5c23 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf
index 06dda3fb48..0a311b3b98 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf
index 77078ce679..1e146ebfb7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf
index 60c963fe2b..55f2bd5c23 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf
index d507b31e08..26e370a493 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf
index b743f61c92..da01275fcc 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf
index 43db630fe0..1d13de71f0 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf
index d8ee3b29a0..120e408800 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf
index 60c963fe2b..55f2bd5c23 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf
index 06dda3fb48..0a311b3b98 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf
index 77078ce679..1e146ebfb7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf
index 60c963fe2b..55f2bd5c23 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf
index d507b31e08..26e370a493 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf
index b743f61c92..da01275fcc 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf
index bac75da3f6..775795c3ef 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf
index 1f0300f111..29bdd062c2 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf
index 7a1a38f779..4366e25078 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf
index d507b31e08..26e370a493 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf
index e9acc00ccd..4030ade196 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf
index fabf1a576e..acf62a20af 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf
index 40be3e00d9..b882a4708d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf
index d507b31e08..26e370a493 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf
index 60c963fe2b..55f2bd5c23 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf
index 06dda3fb48..0a311b3b98 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf
index 77078ce679..1e146ebfb7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf
index 60c963fe2b..55f2bd5c23 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf
index d507b31e08..26e370a493 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf
index b743f61c92..da01275fcc 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf
index d134adadc0..6ba5b25337 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf
index 60c963fe2b..55f2bd5c23 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf
index 06dda3fb48..0a311b3b98 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf
index 77078ce679..1e146ebfb7 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf
index 60c963fe2b..55f2bd5c23 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf
index d507b31e08..26e370a493 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf
index b743f61c92..da01275fcc 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf
index 7baac68acc..a891cbe98a 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf
index bf367cc909..eaab44260b 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf
index 01dbf5ddda..2eb3e6c4cc 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf
index 7baac68acc..a891cbe98a 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf
index bf367cc909..eaab44260b 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf
index 7b7313f0ea..941b1c70b1 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf
index 605b4a7069..9eea96f468 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf
index 3f42126940..b6e14a917e 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf
index 335965b146..6206b5e26d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf
index 605b4a7069..9eea96f468 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf
index 3f42126940..b6e14a917e 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf
index 335965b146..6206b5e26d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf
index e401b4cbbc..d794d6840e 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf
index 8da98b181f..152d46c4b5 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf
index 17615f1638..c191644931 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf
index e401b4cbbc..d794d6840e 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf
index 8da98b181f..152d46c4b5 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf
index 17615f1638..c191644931 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf
index 605b4a7069..9eea96f468 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf
index 3f42126940..b6e14a917e 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf
index 335965b146..6206b5e26d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf
index 605b4a7069..9eea96f468 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf
index 3f42126940..b6e14a917e 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf
index 335965b146..6206b5e26d 100644
--- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf
+++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf
@@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf
index 6961d18bb9..df2b701643 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf
index dd1738f9bd..50f3429d49 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf
index 5e6f04e19c..5103af67a2 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf
index 89ca0b8a16..b736298384 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf
index fe649baf1d..2c509140db 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf
index b7bee2a287..21e87f4cbc 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf
index fe649baf1d..2c509140db 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf
index b7bee2a287..21e87f4cbc 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf
index 2694412b5a..b23b63e7cd 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf
index ab13a073d4..bdcd3702bb 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf
index 2694412b5a..b23b63e7cd 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf
index ab13a073d4..bdcd3702bb 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf
index 58b6084015..667bb40456 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf
index 70a8c3e326..42ede5c303 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf
index 58b6084015..667bb40456 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf
index 70a8c3e326..42ede5c303 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf
index 58b6084015..667bb40456 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf
index 70a8c3e326..42ede5c303 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf
index 58b6084015..667bb40456 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf
index 70a8c3e326..42ede5c303 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf
index 58b6084015..667bb40456 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf
index 70a8c3e326..42ede5c303 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf
index 58b6084015..667bb40456 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf
index 70a8c3e326..42ede5c303 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf
index 650aa680a0..7b89f73b85 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf
index c2699c75b2..48b9fe84ce 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf
index 650aa680a0..7b89f73b85 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf
index c2699c75b2..48b9fe84ce 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf
index 650aa680a0..7b89f73b85 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf
index c2699c75b2..48b9fe84ce 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf
index 650aa680a0..7b89f73b85 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf
index c2699c75b2..48b9fe84ce 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf
index 650aa680a0..7b89f73b85 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf
index c2699c75b2..48b9fe84ce 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf
index 650aa680a0..7b89f73b85 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf
index c2699c75b2..48b9fe84ce 100644
--- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf
index bf73f08303..60a65a3661 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf
index 3ab8d539bf..31816211d0 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf
index 43b2852bbb..ef5c378303 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf
index 100be96c76..10206dc016 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf
index 43e70adc73..172bc663bd 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf
index 100be96c76..10206dc016 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf
index 43b2852bbb..ef5c378303 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf
index 100be96c76..10206dc016 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf
index a54a4cc823..bc51d1f07f 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf
index a554910794..2374f5c85a 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf
index 008afe1f43..8bc6a84fb5 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf
index a554910794..2374f5c85a 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf
index 008afe1f43..8bc6a84fb5 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf
index a554910794..2374f5c85a 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf
index e243b7a1ac..5d0c798639 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf
index c9c03d05ec..d332a4b46e 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf
index 2fc629bd24..60ae633020 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf
@@ -17,7 +17,7 @@ define symbol __ICFEDIT_size_heap__ = 0x000;
define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] |
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] |
mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf
index c9c03d05ec..d332a4b46e 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf
index 7f75472ad0..c9e97b1955 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf
index f3adea524f..3ee399dc17 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf
index 43b2852bbb..ef5c378303 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf
index 100be96c76..10206dc016 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf
index a54a4cc823..bc51d1f07f 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf
index a554910794..2374f5c85a 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf
index 008afe1f43..8bc6a84fb5 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf
index a554910794..2374f5c85a 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf
index 008afe1f43..8bc6a84fb5 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf
index a554910794..2374f5c85a 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf
index ecba53e43b..3aeec61d41 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf
index c9c03d05ec..d332a4b46e 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf
index 2fc629bd24..60ae633020 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf
@@ -17,7 +17,7 @@ define symbol __ICFEDIT_size_heap__ = 0x000;
define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] |
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] |
mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf
index c9c03d05ec..d332a4b46e 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf
index 7f75472ad0..c9e97b1955 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf
index f3adea524f..3ee399dc17 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf
index 008afe1f43..8bc6a84fb5 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf
index a554910794..2374f5c85a 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf
index 008afe1f43..8bc6a84fb5 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf
index a554910794..2374f5c85a 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf
index e243b7a1ac..5d0c798639 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf
index c9c03d05ec..d332a4b46e 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf
index 2fc629bd24..60ae633020 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf
@@ -17,7 +17,7 @@ define symbol __ICFEDIT_size_heap__ = 0x000;
define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] |
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] |
mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
@@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf
index c9c03d05ec..d332a4b46e 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf
index 7f75472ad0..c9e97b1955 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf
index f3adea524f..3ee399dc17 100644
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf
+++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_flash.icf
index 88e7323450..635f4e2c84 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_sram.icf
index 2901494ad2..6c253f8052 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_sram.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_flash.icf
index 88e7323450..635f4e2c84 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_sram.icf
index 2901494ad2..6c253f8052 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_sram.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_flash.icf
index d17c136af5..0fbb6c66c4 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_flash.icf
@@ -36,6 +36,6 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in SRAM1_region { };
+place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_sram.icf
index b2f947087c..90fb7264f6 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_sram.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_flash.icf
index d17c136af5..0fbb6c66c4 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_flash.icf
@@ -36,6 +36,6 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in SRAM1_region { };
+place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_sram.icf
index b2f947087c..90fb7264f6 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_sram.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_flash.icf
index d17c136af5..0fbb6c66c4 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_flash.icf
@@ -36,6 +36,6 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in SRAM1_region { };
+place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_sram.icf
index b2f947087c..90fb7264f6 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_sram.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_flash.icf
index d17c136af5..0fbb6c66c4 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_flash.icf
@@ -36,6 +36,6 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in SRAM1_region { };
+place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_sram.icf
index b2f947087c..90fb7264f6 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_sram.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_flash.icf
index d17c136af5..0fbb6c66c4 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_flash.icf
@@ -36,6 +36,6 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in SRAM1_region { };
+place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_sram.icf
index b2f947087c..90fb7264f6 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_sram.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l451xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l451xx_sram.icf
index ee8e4cd5eb..8189bff597 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l451xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l451xx_sram.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l452xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l452xx_sram.icf
index ee8e4cd5eb..8189bff597 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l452xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l452xx_sram.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l462xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l462xx_sram.icf
index ee8e4cd5eb..8189bff597 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l462xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l462xx_sram.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_flash.icf
index 8377a51765..b4894e4c23 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_sram.icf
index f024509d57..3a7c24140f 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_sram.icf
@@ -38,4 +38,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_flash.icf
index 8377a51765..b4894e4c23 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_sram.icf
index f024509d57..3a7c24140f 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_sram.icf
@@ -38,4 +38,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_flash.icf
index 8377a51765..b4894e4c23 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_sram.icf
index f024509d57..3a7c24140f 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_sram.icf
@@ -38,4 +38,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_flash.icf
index 8377a51765..b4894e4c23 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_sram.icf
index f024509d57..3a7c24140f 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_sram.icf
@@ -38,4 +38,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_flash.icf
index 8377a51765..b4894e4c23 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_sram.icf
index f024509d57..3a7c24140f 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_sram.icf
@@ -38,4 +38,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
-place in SRAM2_region { };
\ No newline at end of file
+place in SRAM2_region { };
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_flash.icf
index 3bba337e33..2f6d9b243b 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_sram.icf
index e2e2316a99..e4f0b87d42 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_sram.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_flash.icf
index 3bba337e33..2f6d9b243b 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_sram.icf
index e2e2316a99..e4f0b87d42 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_sram.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_flash.icf
index 03830346f4..4a853f0633 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_flash.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_sram.icf
index 3d87dba073..da3001d868 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_sram.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_flash.icf
index 03830346f4..4a853f0633 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_flash.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_sram.icf
index 3d87dba073..da3001d868 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_sram.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_flash.icf
index 65c554a3a8..ab7bb5ebe1 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_flash.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_sram.icf
index 387363a750..b8a1f9eb92 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_sram.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_flash.icf
index 65c554a3a8..ab7bb5ebe1 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_flash.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_sram.icf
index 387363a750..b8a1f9eb92 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_sram.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_flash.icf
index 65c554a3a8..ab7bb5ebe1 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_flash.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_sram.icf
index 387363a750..b8a1f9eb92 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_sram.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_flash.icf
index 65c554a3a8..ab7bb5ebe1 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_flash.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_sram.icf
index 387363a750..b8a1f9eb92 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_sram.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_flash.icf
index 65c554a3a8..ab7bb5ebe1 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_flash.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_sram.icf
index 387363a750..b8a1f9eb92 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_sram.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_flash.icf
index 65c554a3a8..ab7bb5ebe1 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_flash.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_flash.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_sram.icf
index 387363a750..b8a1f9eb92 100644
--- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_sram.icf
@@ -42,4 +42,4 @@ place in RAM_region { readwrite,
place in SRAM1_region { };
place in SRAM2_region { };
place in SRAM3_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash.icf b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash.icf
index d5b6e6e15a..d49d1059ce 100644
--- a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash.icf
+++ b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash.icf b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash.icf
index 0d533dbf06..e043d72a77 100644
--- a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash.icf
+++ b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram.icf b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram.icf
index 7318e19497..800415c14c 100644
--- a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in RAM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash.icf b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash.icf
index 0d533dbf06..e043d72a77 100644
--- a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash.icf
+++ b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash.icf
@@ -38,4 +38,4 @@ place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM1_region { };
place in SRAM2_region { };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram.icf b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram.icf
index 7318e19497..800415c14c 100644
--- a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram.icf
+++ b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram.icf
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in RAM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf
index bd36226b63..eaf022c154 100644
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf
@@ -37,4 +37,4 @@ do not initialize { section .noinit};
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in text_region { readonly };
place in data_region { readwrite,
- block CSTACK, block HEAP};
\ No newline at end of file
+ block CSTACK, block HEAP};
diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf
index 61c66cb76c..efdecc1199 100644
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf
@@ -37,4 +37,4 @@ do not initialize { section .noinit};
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in text_region { readonly };
place in data_region { readwrite,
- block CSTACK, block HEAP};
\ No newline at end of file
+ block CSTACK, block HEAP};
diff --git a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_flash.icf b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_flash.icf
index bf0e800149..21c8d9a48a 100644
--- a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_flash.icf
+++ b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_flash.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram.icf b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram.icf
index ddf2f772a0..28df48f0e1 100644
--- a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram.icf
+++ b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram_ns.icf b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram_ns.icf
index 395e068033..96c8d2b1a0 100644
--- a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram_ns.icf
+++ b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram_ns.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram.icf b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram.icf
index ddf2f772a0..28df48f0e1 100644
--- a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram.icf
+++ b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram_ns.icf b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram_ns.icf
index 395e068033..96c8d2b1a0 100644
--- a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram_ns.icf
+++ b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram_ns.icf
@@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-
\ No newline at end of file
+
diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_flash_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_flash_cm4.icf
index e9cc1dd3ae..a2c29f599a 100644
--- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_flash_cm4.icf
+++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_flash_cm4.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite, block CSTACK, block HEAP };
place in RAM_SHARED_region { first section MAPPING_TABLE};
place in RAM_SHARED_region { section MB_MEM1};
-place in RAM_SHARED_region { section MB_MEM2};
\ No newline at end of file
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_sram_cm4.icf
index f56ca8007a..e70f49f0df 100644
--- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_sram_cm4.icf
+++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_sram_cm4.icf
@@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_flash_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_flash_cm4.icf
index e9cc1dd3ae..a2c29f599a 100644
--- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_flash_cm4.icf
+++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_flash_cm4.icf
@@ -37,4 +37,4 @@ place in ROM_region { readonly };
place in RAM_region { readwrite, block CSTACK, block HEAP };
place in RAM_SHARED_region { first section MAPPING_TABLE};
place in RAM_SHARED_region { section MB_MEM1};
-place in RAM_SHARED_region { section MB_MEM2};
\ No newline at end of file
+place in RAM_SHARED_region { section MB_MEM2};
diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_sram_cm4.icf
index f56ca8007a..e70f49f0df 100644
--- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_sram_cm4.icf
+++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_sram_cm4.icf
@@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf
index ffb2da76dc..a21a5ebd82 100644
--- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf
+++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf
@@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf
index ffb2da76dc..a21a5ebd82 100644
--- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf
+++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf
@@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb50xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb50xx_sram_cm4.icf
index c7a00ef6a7..4643ea1b34 100644
--- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb50xx_sram_cm4.icf
+++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb50xx_sram_cm4.icf
@@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb55xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb55xx_sram_cm4.icf
index 360f4eb57d..beccb31d51 100644
--- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb55xx_sram_cm4.icf
+++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb55xx_sram_cm4.icf
@@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf
index 360f4eb57d..beccb31d51 100644
--- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf
+++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf
@@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm0plus.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm0plus.icf
index cd3c90193b..92958bea2b 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm0plus.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm0plus.icf
@@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in RAM2_region { };
\ No newline at end of file
+place in RAM2_region { };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm4.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm4.icf
index e07c1ad667..058f058152 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm4.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm4.icf
@@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in RAM2_region { };
\ No newline at end of file
+place in RAM2_region { };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm0plus.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm0plus.icf
index 7fa21e5c39..029f546655 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm0plus.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm0plus.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm0plus.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm0plus.icf
index 8bdef4aea8..703e6948e5 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm0plus.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm0plus.icf
@@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in RAM2_region { };
\ No newline at end of file
+place in RAM2_region { };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm4.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm4.icf
index e07c1ad667..058f058152 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm4.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm4.icf
@@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in RAM2_region { };
\ No newline at end of file
+place in RAM2_region { };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm0plus.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm0plus.icf
index 7fa21e5c39..029f546655 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm0plus.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm0plus.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm4.icf
index bfb4b54211..97de5deaae 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm4.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm4.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_flash.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_flash.icf
index 927b92a6c7..5a03913be1 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_flash.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_flash.icf
@@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in RAM2_region { };
\ No newline at end of file
+place in RAM2_region { };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_sram.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_sram.icf
index 8b109fa87e..79387b77fc 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_sram.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_sram.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_flash.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_flash.icf
index 927b92a6c7..5a03913be1 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_flash.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_flash.icf
@@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
-place in RAM2_region { };
\ No newline at end of file
+place in RAM2_region { };
diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_sram.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_sram.icf
index 8b109fa87e..79387b77fc 100644
--- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_sram.icf
+++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_sram.icf
@@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/templates/stm32f0xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f0xx/board/linker_scripts/link.lds
index 22d7036562..2549f2660f 100644
--- a/bsp/stm32/libraries/templates/stm32f0xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32f0xx/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f10x/board/linker_scripts/link.lds
index 3832982688..5a45f64a27 100644
--- a/bsp/stm32/libraries/templates/stm32f10x/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32f10x/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32f2xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f2xx/board/linker_scripts/link.lds
index fb9ea9b609..cfa0efbe09 100644
--- a/bsp/stm32/libraries/templates/stm32f2xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32f2xx/board/linker_scripts/link.lds
@@ -77,7 +77,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -100,7 +100,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32f3xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f3xx/board/linker_scripts/link.lds
index 94abb757aa..39ec830ad7 100644
--- a/bsp/stm32/libraries/templates/stm32f3xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32f3xx/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f4xx/board/linker_scripts/link.lds
index a00d6b74bd..224d1119a5 100644
--- a/bsp/stm32/libraries/templates/stm32f4xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32f4xx/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32f7xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f7xx/board/linker_scripts/link.lds
index a00d6b74bd..224d1119a5 100644
--- a/bsp/stm32/libraries/templates/stm32f7xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32f7xx/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32h7xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32h7xx/board/linker_scripts/link.lds
index 9339c6af7c..904cb2b14d 100644
--- a/bsp/stm32/libraries/templates/stm32h7xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32h7xx/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32l1xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32l1xx/board/linker_scripts/link.lds
index 9a0a7ef44e..1cb995953a 100644
--- a/bsp/stm32/libraries/templates/stm32l1xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32l1xx/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32l4xx/board/linker_scripts/link.lds
index 3950cbac38..4f3832bd9c 100644
--- a/bsp/stm32/libraries/templates/stm32l4xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32l4xx/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32l5xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32l5xx/board/linker_scripts/link.lds
index 3950cbac38..4f3832bd9c 100644
--- a/bsp/stm32/libraries/templates/stm32l5xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32l5xx/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.lds
index e407492c39..b9410db545 100644
--- a/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.sct b/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.sct
index df7bcadf06..630576f580 100644
--- a/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.sct
+++ b/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.sct
@@ -1,35 +1,35 @@
-; *************************************************************
-; *** Scatter-Loading Description ***
-; *************************************************************
-
-LR_VECTORS 0x00000000 0x00000400 { ; load region size_region
- .isr_vector +0 {
- startup*.o (RESET, +First)
- }
-}
-
-LR_IROM1 0x10000000 0x00020000 { ; load region size_region
- ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
- *(InRoot$$Sections)
- .ANY (+RO)
- .ANY (+XO)
- }
- RW_IRAM1 0x10020000 0x00050000 { ; RW data
- .ANY (+RW +ZI)
- }
-; RW_IRAM2 0x10020000 0x00020000 { ; RW data
-; .ANY (+RW +ZI)
-; }
-; RW_IRAM3 0x10040000 0x00010000 { ; RW data
-; .ANY (+RW +ZI)
-; }
-; RW_IRAM4 0x10050000 0x00010000 { ; RW data
-; .ANY (+RW +ZI)
-; }
-; ***** To uncomment these 4 lines if OPENAMP used *****
-; *** Create region for OPENAMP ***
- .resource_table +0 ALIGN 4 { ; resource table
- *(.resource_table)
- }
- __OpenAMP_SHMEM__ 0x10050000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP
-}
+; *************************************************************
+; *** Scatter-Loading Description ***
+; *************************************************************
+
+LR_VECTORS 0x00000000 0x00000400 { ; load region size_region
+ .isr_vector +0 {
+ startup*.o (RESET, +First)
+ }
+}
+
+LR_IROM1 0x10000000 0x00020000 { ; load region size_region
+ ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x10020000 0x00050000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+; RW_IRAM2 0x10020000 0x00020000 { ; RW data
+; .ANY (+RW +ZI)
+; }
+; RW_IRAM3 0x10040000 0x00010000 { ; RW data
+; .ANY (+RW +ZI)
+; }
+; RW_IRAM4 0x10050000 0x00010000 { ; RW data
+; .ANY (+RW +ZI)
+; }
+; ***** To uncomment these 4 lines if OPENAMP used *****
+; *** Create region for OPENAMP ***
+ .resource_table +0 ALIGN 4 { ; resource table
+ *(.resource_table)
+ }
+ __OpenAMP_SHMEM__ 0x10050000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP
+}
diff --git a/bsp/stm32/libraries/templates/stm32wbxx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32wbxx/board/linker_scripts/link.lds
index 6afe5ee484..77137ed754 100644
--- a/bsp/stm32/libraries/templates/stm32wbxx/board/linker_scripts/link.lds
+++ b/bsp/stm32/libraries/templates/stm32wbxx/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf
index 6d0177d0bb..7f352fc72a 100644
--- a/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.lds
index bb905d06b1..2292c96e96 100644
--- a/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.icf
index f63d188766..e897e945c1 100644
--- a/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.lds
index bac6b71c30..463b33c098 100644
--- a/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.lds
index cc7da7d507..1e321b30bb 100644
--- a/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.sct b/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.sct
index f64b03c941..6930ff4b50 100644
--- a/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.sct
+++ b/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.sct
@@ -1,15 +1,15 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00010000 { ; load region size_region
- ER_IROM1 0x08000000 0x00010000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- RW_IRAM1 0x20000000 0x00005000 { ; RW data
- .ANY (+RW +ZI)
- }
-}
-
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00010000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00010000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00005000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.lds
index 66c31ef7f8..64f4be1e7a 100644
--- a/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.sct b/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.sct
index d500431408..0835abf43e 100644
--- a/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.sct
+++ b/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.sct
@@ -1,15 +1,15 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00080000 { ; load region size_region
- ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- RW_IRAM1 0x20000000 0x00010000 { ; RW data
- .ANY (+RW +ZI)
- }
-}
-
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00010000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.icf b/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.icf
index 5019b2d673..758734c181 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.lds
index 644fe83314..5a45f64a27 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-atk-warshipv3/board/linker_scripts/link.lds
index 66c31ef7f8..64f4be1e7a 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.lds
index 3832982688..5a45f64a27 100644
--- a/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.sct b/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.sct
index c26b647ebf..f67cd68761 100644
--- a/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.sct
+++ b/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.sct
@@ -1,15 +1,15 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00020000 { ; load region size_region
- ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- RW_IRAM1 0x20000000 0x00005000 { ; RW data
- .ANY (+RW +ZI)
- }
-}
-
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00020000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00005000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-dofly-M3S/board/linker_scripts/link.lds
index 66c31ef7f8..64f4be1e7a 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.icf b/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.icf
index 6f5c19b1a0..6569a9cfc6 100644
--- a/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.lds
index 9c7d04da77..99c745fe4c 100644
--- a/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.icf b/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.icf
index 2b7eabee47..c1d6615d89 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.lds
index deb1086a6e..64f4be1e7a 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.lds
@@ -51,9 +51,9 @@ SECTIONS
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
-
+
. = ALIGN(4);
-
+
_etext = .;
} > ROM = 0
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-gizwits-gokitv21/board/linker_scripts/link.lds
index cc7da7d507..1e321b30bb 100644
--- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-hw100k-ibox/board/linker_scripts/link.lds
index 0f984bcea7..64f4be1e7a 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/linker_scripts/link.lds
@@ -46,7 +46,7 @@ SECTIONS
__rt_init_end = .;
. = ALIGN(4);
-
+
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-onenet-nbiot/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-onenet-nbiot/board/linker_scripts/link.lds
index 95185c5729..c96b01a1cf 100644
--- a/bsp/stm32/stm32f103-onenet-nbiot/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-onenet-nbiot/board/linker_scripts/link.lds
@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
- . = ALIGN(4);
+ . = ALIGN(4);
_etext = .;
} > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-yf-ufun/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-yf-ufun/board/linker_scripts/link.lds
index ee04854f39..b16b453a1e 100644
--- a/bsp/stm32/stm32f103-yf-ufun/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-yf-ufun/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f103-ys-f1pro/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-ys-f1pro/board/linker_scripts/link.lds
index 66c31ef7f8..64f4be1e7a 100644
--- a/bsp/stm32/stm32f103-ys-f1pro/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f103-ys-f1pro/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f107-uc-eval/board/linker_scripts/link.lds b/bsp/stm32/stm32f107-uc-eval/board/linker_scripts/link.lds
index c8ac6f430f..3a37529769 100644
--- a/bsp/stm32/stm32f107-uc-eval/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f107-uc-eval/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds
index 2f6329c65a..a810dd0cc9 100644
--- a/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds
@@ -77,7 +77,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -100,7 +100,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f302-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f302-st-nucleo/board/linker_scripts/link.lds
index 94abb757aa..39ec830ad7 100644
--- a/bsp/stm32/stm32f302-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f302-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f401-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f401-st-nucleo/board/linker_scripts/link.lds
index 58182b5efe..5ce1d786de 100644
--- a/bsp/stm32/stm32f401-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f401-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/linker_scripts/link.lds b/bsp/stm32/stm32f405-smdz-breadfruit/board/linker_scripts/link.lds
index b6b39bc08e..3c53046fe9 100644
--- a/bsp/stm32/stm32f405-smdz-breadfruit/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/linker_scripts/link.lds
@@ -93,7 +93,7 @@ SECTIONS
_edata = . ;
} >RAM1
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -116,7 +116,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM1
__bss_end = .;
diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds
index 087b672a56..e6d932fd7c 100644
--- a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds
index a00d6b74bd..224d1119a5 100644
--- a/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f407-st-discovery/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-st-discovery/board/linker_scripts/link.lds
index f1ee8938c7..4f8d01522a 100644
--- a/bsp/stm32/stm32f407-st-discovery/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f407-st-discovery/board/linker_scripts/link.lds
@@ -87,7 +87,7 @@ SECTIONS
_edata = . ;
} >RAM1
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -110,7 +110,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM1
__bss_end = .;
diff --git a/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.icf
index 90e7f8a9f5..45c8e20684 100644
--- a/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.lds
index 5b45860ae1..aeba68d589 100644
--- a/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.lds
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f411-atk-nano/board/linker_scripts/link.lds b/bsp/stm32/stm32f411-atk-nano/board/linker_scripts/link.lds
index 9ca9dba2e9..e2fa98f495 100644
--- a/bsp/stm32/stm32f411-atk-nano/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f411-atk-nano/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf
index 869a0842b7..4274ac64e6 100644
--- a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds
index 4787919c55..cd285981ae 100644
--- a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.icf b/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.icf
index 869a0842b7..4274ac64e6 100644
--- a/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.lds b/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.lds
index 4787919c55..cd285981ae 100644
--- a/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.lds
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.icf
index db383c18a1..4308d94d31 100644
--- a/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.lds
index d60a29c7ae..1da876e360 100644
--- a/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.lds
@@ -86,7 +86,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -109,7 +109,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f413-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f413-st-nucleo/board/linker_scripts/link.lds
index 1b8b1eb183..49685f2078 100644
--- a/bsp/stm32/stm32f413-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f413-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds
index 41e3b21bb8..a1d3475a84 100644
--- a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} > RAM1
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM1
__bss_end = .;
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/linker_scripts/link.lds b/bsp/stm32/stm32f429-armfly-v6/board/linker_scripts/link.lds
index 8ae9c8ca53..8884659bae 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f429-armfly-v6/board/linker_scripts/link.lds
@@ -93,7 +93,7 @@ SECTIONS
_edata = . ;
} >RAM1
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -116,7 +116,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM1
__bss_end = .;
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/linker_scripts/link.lds b/bsp/stm32/stm32f429-atk-apollo/board/linker_scripts/link.lds
index 5a43a6a0f8..45861b463b 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f429-atk-apollo/board/linker_scripts/link.lds
@@ -93,13 +93,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
-
+
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM1
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -122,7 +122,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM1
__bss_end = .;
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/linker_scripts/link.lds b/bsp/stm32/stm32f429-fire-challenger/board/linker_scripts/link.lds
index 8ae9c8ca53..8884659bae 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f429-fire-challenger/board/linker_scripts/link.lds
@@ -93,7 +93,7 @@ SECTIONS
_edata = . ;
} >RAM1
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -116,7 +116,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM1
__bss_end = .;
diff --git a/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds b/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds
index 4896d01f1f..052bc52b69 100644
--- a/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.icf
index 869a0842b7..4274ac64e6 100644
--- a/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.lds
index 1a228ba882..67337e873b 100644
--- a/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.lds
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f469-st-disco/board/linker_scripts/link.lds b/bsp/stm32/stm32f469-st-disco/board/linker_scripts/link.lds
index fe848340b6..036786ab6b 100644
--- a/bsp/stm32/stm32f469-st-disco/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f469-st-disco/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.icf b/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.icf
index 3ffc160fe5..f7b60c0847 100644
--- a/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.lds b/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.lds
index 90be2e87f2..14682f3d48 100644
--- a/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds
index 90be2e87f2..14682f3d48 100644
--- a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct
index 7a2a883cd3..e4ae202302 100644
--- a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct
+++ b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct
@@ -1,15 +1,15 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00200000 { ; load region size_region
- ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- RW_IRAM1 0x20020000 0x00080000 { ; RW data
- .ANY (+RW +ZI)
- }
-}
-
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00200000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20020000 0x00080000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf b/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf
index c3400bb59e..569b08edd4 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds b/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds
index a00d6b74bd..224d1119a5 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf
index e817969a9e..ed2b24a6a5 100644
--- a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds
index eca488ead4..7c446dcc54 100644
--- a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f767-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f767-st-nucleo/board/linker_scripts/link.lds
index 8672f3b672..fea3793464 100644
--- a/bsp/stm32/stm32f767-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f767-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32f769-st-disco/board/linker_scripts/link.lds b/bsp/stm32/stm32f769-st-disco/board/linker_scripts/link.lds
index 8672f3b672..fea3793464 100644
--- a/bsp/stm32/stm32f769-st-disco/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32f769-st-disco/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds
index 18c530241f..1a463ec86a 100644
--- a/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.icf
index fda72ef41f..b170e7fb2b 100644
--- a/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.lds
index 18c530241f..1a463ec86a 100644
--- a/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.icf
index 869a0842b7..4274ac64e6 100644
--- a/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.lds
index 1a228ba882..67337e873b 100644
--- a/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.lds
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.icf
index 869a0842b7..4274ac64e6 100644
--- a/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.lds
index 1a228ba882..67337e873b 100644
--- a/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.lds
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32h743-armfly-v7/board/linker_scripts/link.lds b/bsp/stm32/stm32h743-armfly-v7/board/linker_scripts/link.lds
index 9339c6af7c..904cb2b14d 100644
--- a/bsp/stm32/stm32h743-armfly-v7/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32h743-armfly-v7/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/linker_scripts/link.lds b/bsp/stm32/stm32h743-atk-apollo/board/linker_scripts/link.lds
index 9339c6af7c..904cb2b14d 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32h743-atk-apollo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32h743-openmv-h7plus/board/linker_scripts/link.lds b/bsp/stm32/stm32h743-openmv-h7plus/board/linker_scripts/link.lds
index 63af364fd0..02089a6f9b 100644
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM2
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM2
__bss_end = .;
diff --git a/bsp/stm32/stm32h743-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32h743-st-nucleo/board/linker_scripts/link.lds
index 9339c6af7c..904cb2b14d 100644
--- a/bsp/stm32/stm32h743-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32h743-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds
index 7ad7729d2c..45d6f7aaa5 100644
--- a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct
index 2866134d54..5381dfedfe 100644
--- a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct
+++ b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct
@@ -11,4 +11,4 @@ LR_IROM1 0x08000000 0x00100000 { ; load region size_region
RW_IRAM1 0x20000000 0x20020000{ ; RW data
.ANY (+RW +ZI)
}
-}
\ No newline at end of file
+}
diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/linker_scripts/link.lds b/bsp/stm32/stm32h750-armfly-h7-tool/board/linker_scripts/link.lds
index f3bfeab242..3ebf411f32 100644
--- a/bsp/stm32/stm32h750-armfly-h7-tool/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32h750-artpi/board/linker_scripts/link.lds b/bsp/stm32/stm32h750-artpi/board/linker_scripts/link.lds
index 0609f4d445..4daa75f9c1 100644
--- a/bsp/stm32/stm32h750-artpi/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32h750-artpi/board/linker_scripts/link.lds
@@ -113,7 +113,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -136,7 +136,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
@@ -149,7 +149,7 @@ SECTIONS
. = ALIGN(4);
__RxDecripSection_free__ = .;
} > RxDecripSection
-
+
.TxDecripSection (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
@@ -158,7 +158,7 @@ SECTIONS
. = ALIGN(4);
__TxDecripSection_free__ = .;
} > TxDecripSection
-
+
.RxArraySection (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
diff --git a/bsp/stm32/stm32h750-weact-ministm32h7xx/board/linker_scripts/link.lds b/bsp/stm32/stm32h750-weact-ministm32h7xx/board/linker_scripts/link.lds
index 2597ee2e73..b758e1db72 100644
--- a/bsp/stm32/stm32h750-weact-ministm32h7xx/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32h750-weact-ministm32h7xx/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds
index 4fde4762fa..246c835c6a 100644
--- a/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.icf
index fd40e5bf2b..08e1fabb0f 100644
--- a/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.icf
@@ -26,4 +26,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.lds
index ff393d1e71..77325e9337 100644
--- a/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds
index bc1bd87cdb..55ac83ee36 100644
--- a/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM1
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM1
__bss_end = .;
diff --git a/bsp/stm32/stm32l431-BearPi/board/linker_scripts/link.lds b/bsp/stm32/stm32l431-BearPi/board/linker_scripts/link.lds
index f659e99588..e38fca8efa 100644
--- a/bsp/stm32/stm32l431-BearPi/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l431-BearPi/board/linker_scripts/link.lds
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM2
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM2
__bss_end = .;
diff --git a/bsp/stm32/stm32l432-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l432-st-nucleo/board/linker_scripts/link.lds
index f659e99588..e38fca8efa 100644
--- a/bsp/stm32/stm32l432-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l432-st-nucleo/board/linker_scripts/link.lds
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM2
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM2
__bss_end = .;
diff --git a/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.icf b/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.icf
index 158e0ce45d..9da5204f84 100644
--- a/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.lds b/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.lds
index c8ac6f430f..3a37529769 100644
--- a/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32l433-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l433-st-nucleo/board/linker_scripts/link.lds
index f659e99588..e38fca8efa 100644
--- a/bsp/stm32/stm32l433-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l433-st-nucleo/board/linker_scripts/link.lds
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} >RAM2
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM2
__bss_end = .;
diff --git a/bsp/stm32/stm32l452-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l452-st-nucleo/board/linker_scripts/link.lds
index cb5dd4095e..280da426d3 100644
--- a/bsp/stm32/stm32l452-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l452-st-nucleo/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds
index 85311d6b2f..b648e8aef5 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM1
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM1
__bss_end = .;
diff --git a/bsp/stm32/stm32l475-st-discovery/board/linker_scripts/link.lds b/bsp/stm32/stm32l475-st-discovery/board/linker_scripts/link.lds
index 22076de870..ef680a75bd 100644
--- a/bsp/stm32/stm32l475-st-discovery/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l475-st-discovery/board/linker_scripts/link.lds
@@ -7,7 +7,7 @@ MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */
-
+
RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 32k /* 32K sram */
}
ENTRY(Reset_Handler)
@@ -55,7 +55,7 @@ SECTIONS
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
-
+
_etext = .;
} > ROM = 0
@@ -92,7 +92,7 @@ SECTIONS
_edata = . ;
} > RAM2
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -115,7 +115,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM2
__bss_end = .;
diff --git a/bsp/stm32/stm32l476-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l476-st-nucleo/board/linker_scripts/link.lds
index a6aca31dae..3c5e2c6498 100644
--- a/bsp/stm32/stm32l476-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l476-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM2
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM2
__bss_end = .;
diff --git a/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.icf b/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.icf
index 3ffc160fe5..f7b60c0847 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.icf
@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.lds b/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.lds
index b180b27ef9..935c151a01 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32l496-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l496-st-nucleo/board/linker_scripts/link.lds
index 0571d2142f..c41cd9b92f 100644
--- a/bsp/stm32/stm32l496-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l496-st-nucleo/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM1
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM1
__bss_end = .;
diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf
index 106c5e18d7..1567e30069 100644
--- a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf
@@ -4,14 +4,14 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x08200000;
-define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM1_end__ = 0x20030000;
-define symbol __ICFEDIT_region_RAM2_start__ = 0x20040000;
-define symbol __ICFEDIT_region_RAM2_end__ = 0x200A0000;
-define symbol __ICFEDIT_region_RAM3_start__ = 0x10000000;
-define symbol __ICFEDIT_region_RAM3_end__ = 0x10010000;
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x08200000;
+define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM1_end__ = 0x20030000;
+define symbol __ICFEDIT_region_RAM2_start__ = 0x20040000;
+define symbol __ICFEDIT_region_RAM2_end__ = 0x200A0000;
+define symbol __ICFEDIT_region_RAM3_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM3_end__ = 0x10010000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0800;
diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds
index c675b6f406..f4704af097 100644
--- a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds
@@ -40,7 +40,7 @@ SECTIONS
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
-
+
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
@@ -89,7 +89,7 @@ SECTIONS
_edata = . ;
} >RAM1
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -112,7 +112,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM1
__bss_end = .;
diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct
index 4ef96219c2..fabfaff8bf 100644
--- a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct
+++ b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct
@@ -2,16 +2,16 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
-LR_IROM1 0x08000000 0x00200000 { ; load region size_region
- ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
+LR_IROM1 0x08000000 0x00200000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
- RW_IRAM1 0x20000000 0x00030000 { ; RW data
- .ANY (+RW +ZI)
- }
+ RW_IRAM1 0x20000000 0x00030000 { ; RW data
+ .ANY (+RW +ZI)
+ }
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.lds b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.lds
index 55c0cd87ac..bf249b1f0b 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.lds
@@ -89,7 +89,7 @@ SECTIONS
_edata = . ;
} >RAM2
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -112,7 +112,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM2
__bss_end = .;
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct
index b8cea677e9..75aad35220 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct
+++ b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct
@@ -2,16 +2,16 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
-LR_IROM1 0x08000000 0x00200000 { ; load region size_region
- ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
+LR_IROM1 0x08000000 0x00200000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
- RW_IRAM1 0x20000000 0x00040000 { ; RW data
- .ANY (+RW +ZI)
- }
+ RW_IRAM1 0x20000000 0x00040000 { ; RW data
+ .ANY (+RW +ZI)
+ }
diff --git a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.icf b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.icf
index 1971067307..2e86c5bea4 100644
--- a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.icf
@@ -24,7 +24,7 @@ define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __IC
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]
- | mem:[from IRAM3_region_start to IRAM3_region_end ];
+ | mem:[from IRAM3_region_start to IRAM3_region_end ];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
@@ -42,4 +42,4 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in IROM_region { readonly };
-place in IRAM_region { readwrite, block CSTACK, block HEAP };
\ No newline at end of file
+place in IRAM_region { readwrite, block CSTACK, block HEAP };
diff --git a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.lds b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.lds
index f51f38fe55..5d7aba37c4 100644
--- a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.lds
@@ -88,7 +88,7 @@ SECTIONS
_edata = . ;
} >RAM2
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -111,7 +111,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM2
__bss_end = .;
diff --git a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.sct b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.sct
index 1789d52d63..2bfecb2c5d 100644
--- a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.sct
+++ b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.sct
@@ -2,16 +2,16 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
-LR_IROM1 0x08000000 0x00200000 { ; load region size_region
- ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
+LR_IROM1 0x08000000 0x00200000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
- RW_IRAM1 0x20000000 0x000A0000 { ; RW data
- .ANY (+RW +ZI)
- }
+ RW_IRAM1 0x20000000 0x000A0000 { ; RW data
+ .ANY (+RW +ZI)
+ }
diff --git a/bsp/stm32/stm32l552-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l552-st-nucleo/board/linker_scripts/link.lds
index 3950cbac38..4f3832bd9c 100644
--- a/bsp/stm32/stm32l552-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32l552-st-nucleo/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.lds b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.lds
index e407492c39..b9410db545 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct
index a64b8cc98b..5cbf7d3943 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct
@@ -1,27 +1,27 @@
-; *************************************************************
-; *** Scatter-Loading Description ***
-; *************************************************************
-
-LR_VECTORS 0x00000000 0x00000400 { ; load region size_region
- .isr_vector +0 {
- startup*.o (RESET, +First)
- }
-}
-
-LR_IROM1 0x10000000 0x00030000 { ; load region size_region
- ER_IROM1 0x10000000 0x00030000 { ; load address = execution address
- *(InRoot$$Sections)
- .ANY (+RO)
- .ANY (+XO)
- }
- RW_IRAM1 0x10030000 0x00010000 { ; RW data
- .ANY (+RW +ZI)
- }
-
-
-; ***** Create region for OPENAMP *****
-; *** These 4 lines can be commented if OPENAMP is not used *****
- .resource_table +0 ALIGN 4 { ; resource table
- *(.resource_table)
- } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP
-}
+; *************************************************************
+; *** Scatter-Loading Description ***
+; *************************************************************
+
+LR_VECTORS 0x00000000 0x00000400 { ; load region size_region
+ .isr_vector +0 {
+ startup*.o (RESET, +First)
+ }
+}
+
+LR_IROM1 0x10000000 0x00030000 { ; load region size_region
+ ER_IROM1 0x10000000 0x00030000 { ; load address = execution address
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x10030000 0x00010000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+
+; ***** Create region for OPENAMP *****
+; *** These 4 lines can be commented if OPENAMP is not used *****
+ .resource_table +0 ALIGN 4 { ; resource table
+ *(.resource_table)
+ } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP
+}
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds
index e407492c39..b9410db545 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds
@@ -91,7 +91,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -114,7 +114,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct
index a64b8cc98b..5cbf7d3943 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct
@@ -1,27 +1,27 @@
-; *************************************************************
-; *** Scatter-Loading Description ***
-; *************************************************************
-
-LR_VECTORS 0x00000000 0x00000400 { ; load region size_region
- .isr_vector +0 {
- startup*.o (RESET, +First)
- }
-}
-
-LR_IROM1 0x10000000 0x00030000 { ; load region size_region
- ER_IROM1 0x10000000 0x00030000 { ; load address = execution address
- *(InRoot$$Sections)
- .ANY (+RO)
- .ANY (+XO)
- }
- RW_IRAM1 0x10030000 0x00010000 { ; RW data
- .ANY (+RW +ZI)
- }
-
-
-; ***** Create region for OPENAMP *****
-; *** These 4 lines can be commented if OPENAMP is not used *****
- .resource_table +0 ALIGN 4 { ; resource table
- *(.resource_table)
- } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP
-}
+; *************************************************************
+; *** Scatter-Loading Description ***
+; *************************************************************
+
+LR_VECTORS 0x00000000 0x00000400 { ; load region size_region
+ .isr_vector +0 {
+ startup*.o (RESET, +First)
+ }
+}
+
+LR_IROM1 0x10000000 0x00030000 { ; load region size_region
+ ER_IROM1 0x10000000 0x00030000 { ; load address = execution address
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x10030000 0x00010000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+
+; ***** Create region for OPENAMP *****
+; *** These 4 lines can be commented if OPENAMP is not used *****
+ .resource_table +0 ALIGN 4 { ; resource table
+ *(.resource_table)
+ } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP
+}
diff --git a/bsp/stm32/stm32u575-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32u575-st-nucleo/board/linker_scripts/link.lds
index 3950cbac38..4f3832bd9c 100644
--- a/bsp/stm32/stm32u575-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32u575-st-nucleo/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds
index 85635b902d..60c099e0fa 100644
--- a/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
@@ -158,5 +158,5 @@ SECTIONS
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
-
+
}
diff --git a/bsp/synwit/swm320/drivers/linker_scripts/link.icf b/bsp/synwit/swm320/drivers/linker_scripts/link.icf
index 4d4eb64623..f87eef728c 100644
--- a/bsp/synwit/swm320/drivers/linker_scripts/link.icf
+++ b/bsp/synwit/swm320/drivers/linker_scripts/link.icf
@@ -59,4 +59,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in IROM_region { readonly };
place in EROM_region { readonly section application_specific_ro };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
-place in ERAM_region { readwrite section application_specific_rw };
\ No newline at end of file
+place in ERAM_region { readwrite section application_specific_rw };
diff --git a/bsp/synwit/swm320/drivers/linker_scripts/link.lds b/bsp/synwit/swm320/drivers/linker_scripts/link.lds
index 2f6896cfb3..bb543c2a48 100644
--- a/bsp/synwit/swm320/drivers/linker_scripts/link.lds
+++ b/bsp/synwit/swm320/drivers/linker_scripts/link.lds
@@ -73,7 +73,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -94,7 +94,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/synwit/swm341/drivers/linker_scripts/link.icf b/bsp/synwit/swm341/drivers/linker_scripts/link.icf
index 3bd6d6ff15..761d539e18 100644
--- a/bsp/synwit/swm341/drivers/linker_scripts/link.icf
+++ b/bsp/synwit/swm341/drivers/linker_scripts/link.icf
@@ -59,4 +59,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in IROM_region { readonly };
place in EROM_region { readonly section application_specific_ro };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
-place in ERAM_region { readwrite section application_specific_rw };
\ No newline at end of file
+place in ERAM_region { readwrite section application_specific_rw };
diff --git a/bsp/synwit/swm341/drivers/linker_scripts/link.lds b/bsp/synwit/swm341/drivers/linker_scripts/link.lds
index 7d24f5f96d..40458f1598 100644
--- a/bsp/synwit/swm341/drivers/linker_scripts/link.lds
+++ b/bsp/synwit/swm341/drivers/linker_scripts/link.lds
@@ -90,7 +90,7 @@ SECTIONS
_edata = . ;
} > RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Source/ARM/tae32f53xx_ac5_sram.sct b/bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Source/ARM/tae32f53xx_ac5_sram.sct
index 040fa5fe6c..493f8d99e1 100644
--- a/bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Source/ARM/tae32f53xx_ac5_sram.sct
+++ b/bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Source/ARM/tae32f53xx_ac5_sram.sct
@@ -80,16 +80,16 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
.ANY (+XO)
}
- RW_RAMA __RW_BASE __RW_SIZE { ; RWA data
+ RW_RAMA __RW_BASE __RW_SIZE { ; RWA data
*.o (SECTION_RAMA)
.ANY (+RW +ZI)
}
- RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region
+ RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region
*.o (SECTION_RAMB)
}
- RW_RAMC __RAMC_BASE __RAMC_SIZE { ; RWC region
+ RW_RAMC __RAMC_BASE __RAMC_SIZE { ; RWC region
*.o (SECTION_RAMC)
}
diff --git a/bsp/tae32f5300/board/linker_scripts/link.icf b/bsp/tae32f5300/board/linker_scripts/link.icf
index 3a80cf803b..17a41b11c9 100644
--- a/bsp/tae32f5300/board/linker_scripts/link.icf
+++ b/bsp/tae32f5300/board/linker_scripts/link.icf
@@ -51,7 +51,7 @@ define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to
| mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__]
| mem:[from __ICFEDIT_region_IRAM4_start__ to __ICFEDIT_region_IRAM4_end__]
| mem:[from __ICFEDIT_region_IRAM5_start__ to __ICFEDIT_region_IRAM5_end__]
- | mem:[from __ICFEDIT_region_IRAM6_start__ to __ICFEDIT_region_IRAM6_end__];
+ | mem:[from __ICFEDIT_region_IRAM6_start__ to __ICFEDIT_region_IRAM6_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
@@ -62,4 +62,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK, block HEAP };
\ No newline at end of file
+place in RAM_region { readwrite, last block CSTACK, block HEAP };
diff --git a/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct b/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct
index b41d86675c..b34e523c3e 100644
--- a/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct
+++ b/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct
@@ -16,7 +16,7 @@
/*--------------------- RAMCODE Section Configuration ------------------------
; RAMCODE Configuration
-; RAMCODE in which MCU
+; RAMCODE in which MCU
; <3=> TAE32F5300
; <2=> TAE32F5600
; RAMCODE Base Address is different in different MCUs
@@ -96,7 +96,7 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
.ANY (+RO)
.ANY (+XO)
}
-
+
#if __RW_CODE_SIZE > 0
RW_CODE __RW_CODE_BASE __RW_CODE_SIZE {
*.o (RAMCODE)
@@ -115,7 +115,7 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
-
+
RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region
*.o (SECTION_RAMB)
}
diff --git a/bsp/tkm32F499/drivers/linker_scripts/link.lds b/bsp/tkm32F499/drivers/linker_scripts/link.lds
index aad42bdb39..21222812c4 100644
--- a/bsp/tkm32F499/drivers/linker_scripts/link.lds
+++ b/bsp/tkm32F499/drivers/linker_scripts/link.lds
@@ -73,7 +73,7 @@ SECTIONS
_edata = . ;
} >DATA
- .stack :
+ .stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
@@ -94,7 +94,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > DATA
__bss_end = .;
diff --git a/bsp/tm4c123bsp/board/linker_scripts/link.icf b/bsp/tm4c123bsp/board/linker_scripts/link.icf
index 953c77e909..76d1f1a51f 100644
--- a/bsp/tm4c123bsp/board/linker_scripts/link.icf
+++ b/bsp/tm4c123bsp/board/linker_scripts/link.icf
@@ -4,20 +4,20 @@
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
-//
+//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
-//
+//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
-//
+//
// This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
//
//*****************************************************************************
diff --git a/bsp/tm4c123bsp/board/linker_scripts/link.sct b/bsp/tm4c123bsp/board/linker_scripts/link.sct
index 58f2ff6f66..fd90fe75ad 100644
--- a/bsp/tm4c123bsp/board/linker_scripts/link.sct
+++ b/bsp/tm4c123bsp/board/linker_scripts/link.sct
@@ -4,20 +4,20 @@
;
; Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
; Software License Agreement
-;
+;
; Texas Instruments (TI) is supplying this software for use solely and
; exclusively on TI's microcontroller products. The software is owned by
; TI and/or its suppliers, and is protected under applicable copyright
; laws. You may not combine this software with "viral" open-source
; software in order to form a larger program.
-;
+;
; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
; DAMAGES, FOR ANY REASON WHATSOEVER.
-;
+;
; This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
;
;******************************************************************************
diff --git a/bsp/tm4c129x/tm4c_rom.icf b/bsp/tm4c129x/tm4c_rom.icf
index 4bda7a154a..89084ba8a0 100644
--- a/bsp/tm4c129x/tm4c_rom.icf
+++ b/bsp/tm4c129x/tm4c_rom.icf
@@ -4,20 +4,20 @@
//
// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
-//
+//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
-//
+//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
-//
+//
// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package.
//
//*****************************************************************************
@@ -84,4 +84,4 @@ place in SRAM { readwrite, block HEAP };
keep { section FSymTab };
keep { section VSymTab };
-keep { section .rti_fn* };
\ No newline at end of file
+keep { section .rti_fn* };
diff --git a/bsp/tm4c129x/tm4c_rom.sct b/bsp/tm4c129x/tm4c_rom.sct
index 9162ff8c44..b3d09c3f51 100644
--- a/bsp/tm4c129x/tm4c_rom.sct
+++ b/bsp/tm4c129x/tm4c_rom.sct
@@ -4,20 +4,20 @@
;
; Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved.
; Software License Agreement
-;
+;
; Texas Instruments (TI) is supplying this software for use solely and
; exclusively on TI's microcontroller products. The software is owned by
; TI and/or its suppliers, and is protected under applicable copyright
; laws. You may not combine this software with "viral" open-source
; software in order to form a larger program.
-;
+;
; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
; DAMAGES, FOR ANY REASON WHATSOEVER.
-;
+;
; This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package.
;
;******************************************************************************
diff --git a/bsp/w60x/drivers/linker_scripts/link.icf b/bsp/w60x/drivers/linker_scripts/link.icf
index a3e861ed85..be8ea4df39 100644
--- a/bsp/w60x/drivers/linker_scripts/link.icf
+++ b/bsp/w60x/drivers/linker_scripts/link.icf
@@ -1,30 +1,30 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08010100;
-/*-Memory Regions-*/
-/* rom 959K */
-define symbol __ICFEDIT_region_ROM_start__ = 0x08010100;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
-/* ram 160k */
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20028000;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0xc00;
-define symbol __ICFEDIT_size_heap__ = 0x1A000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08010100;
+/*-Memory Regions-*/
+/* rom 959K */
+define symbol __ICFEDIT_region_ROM_start__ = 0x08010100;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+/* ram 160k */
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20028000;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0xc00;
+define symbol __ICFEDIT_size_heap__ = 0x1A000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/w60x/drivers/linker_scripts/link.lds b/bsp/w60x/drivers/linker_scripts/link.lds
index 81c8f5631b..88b389c8d8 100644
--- a/bsp/w60x/drivers/linker_scripts/link.lds
+++ b/bsp/w60x/drivers/linker_scripts/link.lds
@@ -1,5 +1,5 @@
-/* Linker script to configure memory regions.
- * Need modifying for a specific board.
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
* FLASH.ORIGIN: starting address of flash
* FLASH.LENGTH: length of flash
* RAM.ORIGIN: starting address of RAM bank 0
@@ -17,7 +17,7 @@ MEMORY
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
- *
+ *
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
@@ -61,7 +61,7 @@ SECTIONS
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
-
+
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
@@ -108,7 +108,7 @@ SECTIONS
KEEP(*(.eh_frame*))
} > FLASH
- .ARM.extab :
+ .ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
@@ -180,7 +180,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
- } > RAM
+ } > RAM
ASSERT(__StackTop <= 0x20028000, "stack address error")
}
diff --git a/bsp/w60x/drivers/linker_scripts/link.sct b/bsp/w60x/drivers/linker_scripts/link.sct
index 76ca106e6b..6e31c6ac7f 100644
--- a/bsp/w60x/drivers/linker_scripts/link.sct
+++ b/bsp/w60x/drivers/linker_scripts/link.sct
@@ -1,15 +1,15 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08010100 0x000EFEFF { ; load region size_region
- ER_IROM1 0x08010100 0x000EFEFF { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- .ANY (+XO)
- }
- RW_IRAM1 0x20000000 0x00028000 { ; RW data
- .ANY (+RW +ZI)
- }
-}
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08010100 0x000EFEFF { ; load region size_region
+ ER_IROM1 0x08010100 0x000EFEFF { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00028000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/bsp/wch/arm/ch32f103c8-core/board/linker_scripts/link.lds b/bsp/wch/arm/ch32f103c8-core/board/linker_scripts/link.lds
index 63e0f7e4c3..d0f4c6dafe 100644
--- a/bsp/wch/arm/ch32f103c8-core/board/linker_scripts/link.lds
+++ b/bsp/wch/arm/ch32f103c8-core/board/linker_scripts/link.lds
@@ -86,7 +86,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -109,7 +109,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/wch/arm/ch32f203r-evt/board/linker_scripts/link.lds b/bsp/wch/arm/ch32f203r-evt/board/linker_scripts/link.lds
index 0d5e7beafe..dd68dd192d 100644
--- a/bsp/wch/arm/ch32f203r-evt/board/linker_scripts/link.lds
+++ b/bsp/wch/arm/ch32f203r-evt/board/linker_scripts/link.lds
@@ -86,7 +86,7 @@ SECTIONS
_edata = . ;
} >RAM
- .stack :
+ .stack :
{
. = ALIGN(4);
_sstack = .;
@@ -109,7 +109,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
-
+
*(.bss.init)
} > RAM
__bss_end = .;
diff --git a/bsp/wch/risc-v/ch32v103r-evt/board/linker_scripts/link.lds b/bsp/wch/risc-v/ch32v103r-evt/board/linker_scripts/link.lds
index c81a03907b..431a6f55d5 100644
--- a/bsp/wch/risc-v/ch32v103r-evt/board/linker_scripts/link.lds
+++ b/bsp/wch/risc-v/ch32v103r-evt/board/linker_scripts/link.lds
@@ -1 +1,194 @@
-ENTRY( _start )
__stack_size = 2048;
PROVIDE( _stack_size = __stack_size );
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
}
SECTIONS
{
.init :
{
_sinit = .;
. = ALIGN(4);
KEEP(*(SORT_NONE(.init)))
. = ALIGN(4);
_einit = .;
} >FLASH AT>FLASH
.vector :
{
*(.vector);
. = ALIGN(64);
} >FLASH AT>FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t.*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
. = ALIGN(4);
} >FLASH AT>FLASH
.fini :
{
KEEP(*(SORT_NONE(.fini)))
. = ALIGN(4);
} >FLASH AT>FLASH
PROVIDE( _etext = . );
PROVIDE( _eitcm = . );
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH AT>FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH AT>FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH AT>FLASH
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH AT>FLASH
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >FLASH AT>FLASH
.dalign :
{
. = ALIGN(4);
PROVIDE(_data_vma = .);
} >RAM AT>FLASH
.dlalign :
{
. = ALIGN(4);
PROVIDE(_data_lma = .);
} >FLASH AT>FLASH
.data :
{
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(4);
PROVIDE( _edata = .);
} >RAM AT>FLASH
.bss :
{
. = ALIGN(4);
PROVIDE( _sbss = .);
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss*)
*(.gnu.linkonce.b.*)
*(COMMON*)
. = ALIGN(4);
PROVIDE( _ebss = .);
} >RAM AT>FLASH
PROVIDE( _end = _ebss);
PROVIDE( end = . );
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
{
PROVIDE( _heap_end = . );
. = ALIGN(4);
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
} >RAM
}
\ No newline at end of file
+ENTRY( _start )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
+
+SECTIONS
+{
+
+ .init :
+ {
+ _sinit = .;
+ . = ALIGN(4);
+ KEEP(*(SORT_NONE(.init)))
+ . = ALIGN(4);
+ _einit = .;
+ } >FLASH AT>FLASH
+
+ .vector :
+ {
+ *(.vector);
+ . = ALIGN(64);
+ } >FLASH AT>FLASH
+
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t.*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(4);
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(4);
+
+ /* section information for modules */
+ . = ALIGN(4);
+ __rtmsymtab_start = .;
+ KEEP(*(RTMSymTab))
+ __rtmsymtab_end = .;
+ . = ALIGN(4);
+
+ } >FLASH AT>FLASH
+
+ .fini :
+ {
+ KEEP(*(SORT_NONE(.fini)))
+ . = ALIGN(4);
+ } >FLASH AT>FLASH
+
+ PROVIDE( _etext = . );
+ PROVIDE( _eitcm = . );
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH AT>FLASH
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH AT>FLASH
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH AT>FLASH
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >FLASH AT>FLASH
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >FLASH AT>FLASH
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data_vma = .);
+ } >RAM AT>FLASH
+
+ .dlalign :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data_lma = .);
+ } >FLASH AT>FLASH
+
+ .data :
+ {
+ *(.gnu.linkonce.r.*)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.*)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ . = ALIGN(4);
+ PROVIDE( _edata = .);
+ } >RAM AT>FLASH
+
+ .bss :
+ {
+ . = ALIGN(4);
+ PROVIDE( _sbss = .);
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON*)
+ . = ALIGN(4);
+ PROVIDE( _ebss = .);
+ } >RAM AT>FLASH
+
+ PROVIDE( _end = _ebss);
+ PROVIDE( end = . );
+
+ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+ {
+ PROVIDE( _heap_end = . );
+ . = ALIGN(4);
+ PROVIDE(_susrstack = . );
+ . = . + __stack_size;
+ PROVIDE( _eusrstack = .);
+ } >RAM
+
+}
+
+
+
diff --git a/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds b/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds
index b0051ab14d..cc60a8caae 100644
--- a/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds
+++ b/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds
@@ -7,41 +7,41 @@ PROVIDE( _stack_size = __stack_size );
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
}
SECTIONS
{
- .init :
- {
- _sinit = .;
- . = ALIGN(4);
- KEEP(*(SORT_NONE(.init)))
- . = ALIGN(4);
- _einit = .;
- } >FLASH AT>FLASH
+ .init :
+ {
+ _sinit = .;
+ . = ALIGN(4);
+ KEEP(*(SORT_NONE(.init)))
+ . = ALIGN(4);
+ _einit = .;
+ } >FLASH AT>FLASH
.vector :
{
*(.vector);
- . = ALIGN(64);
+ . = ALIGN(64);
} >FLASH AT>FLASH
- .text :
- {
- . = ALIGN(4);
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
- *(.gnu.linkonce.t.*)
-
- /* section information for finsh shell */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t.*)
+
+ /* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
@@ -51,7 +51,7 @@ SECTIONS
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
-
+
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
@@ -64,129 +64,129 @@ SECTIONS
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
- . = ALIGN(4);
-
- } >FLASH AT>FLASH
-
- .fini :
- {
- KEEP(*(SORT_NONE(.fini)))
- . = ALIGN(4);
- } >FLASH AT>FLASH
-
- PROVIDE( _etext = . );
- PROVIDE( _eitcm = . );
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >FLASH AT>FLASH
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >FLASH AT>FLASH
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >FLASH AT>FLASH
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >FLASH AT>FLASH
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >FLASH AT>FLASH
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE(_data_vma = .);
- } >RAM AT>FLASH
-
- .dlalign :
- {
- . = ALIGN(4);
- PROVIDE(_data_lma = .);
- } >FLASH AT>FLASH
-
- .data :
- {
- *(.gnu.linkonce.r.*)
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.*)
- *(.sdata2.*)
- *(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- . = ALIGN(4);
- PROVIDE( _edata = .);
- } >RAM AT>FLASH
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE( _sbss = .);
- *(.sbss*)
+ . = ALIGN(4);
+
+ } >FLASH AT>FLASH
+
+ .fini :
+ {
+ KEEP(*(SORT_NONE(.fini)))
+ . = ALIGN(4);
+ } >FLASH AT>FLASH
+
+ PROVIDE( _etext = . );
+ PROVIDE( _eitcm = . );
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH AT>FLASH
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH AT>FLASH
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH AT>FLASH
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >FLASH AT>FLASH
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >FLASH AT>FLASH
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data_vma = .);
+ } >RAM AT>FLASH
+
+ .dlalign :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data_lma = .);
+ } >FLASH AT>FLASH
+
+ .data :
+ {
+ *(.gnu.linkonce.r.*)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.*)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ . = ALIGN(4);
+ PROVIDE( _edata = .);
+ } >RAM AT>FLASH
+
+ .bss :
+ {
+ . = ALIGN(4);
+ PROVIDE( _sbss = .);
+ *(.sbss*)
*(.gnu.linkonce.sb.*)
- *(.bss*)
- *(.gnu.linkonce.b.*)
- *(COMMON*)
- . = ALIGN(4);
- PROVIDE( _ebss = .);
- } >RAM AT>FLASH
+ *(.bss*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON*)
+ . = ALIGN(4);
+ PROVIDE( _ebss = .);
+ } >RAM AT>FLASH
- PROVIDE( _end = _ebss);
- PROVIDE( end = . );
+ PROVIDE( _end = _ebss);
+ PROVIDE( end = . );
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
{
- PROVIDE( _heap_end = . );
+ PROVIDE( _heap_end = . );
. = ALIGN(4);
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
- } >RAM
+ } >RAM
}
diff --git a/bsp/wh44b0/wh44b0_ram.lds b/bsp/wh44b0/wh44b0_ram.lds
index e40eaa3b28..f94069adc7 100644
--- a/bsp/wh44b0/wh44b0_ram.lds
+++ b/bsp/wh44b0/wh44b0_ram.lds
@@ -3,41 +3,41 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
- . = 0x0c000000;
-
- . = ALIGN(4);
- .text : {
- *(.init)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .nobss : { *(.nobss) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- __bss_end = .;
-
- /* stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_info 0 : { *(.debug_info) }
- .debug_line 0 : { *(.debug_line) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- .debug_aranges 0 : { *(.debug_aranges) }
-
- _end = .;
+ . = 0x0c000000;
+
+ . = ALIGN(4);
+ .text : {
+ *(.init)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .nobss : { *(.nobss) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ __bss_end = .;
+
+ /* stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+
+ _end = .;
}
diff --git a/bsp/wh44b0/wh44b0_rom.lds b/bsp/wh44b0/wh44b0_rom.lds
index 85e0c57027..f94069adc7 100644
--- a/bsp/wh44b0/wh44b0_rom.lds
+++ b/bsp/wh44b0/wh44b0_rom.lds
@@ -3,41 +3,41 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
- . = 0x0c000000;
+ . = 0x0c000000;
- . = ALIGN(4);
- .text : {
- *(.init)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .nobss : { *(.nobss) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- __bss_end = .;
-
- /* stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_info 0 : { *(.debug_info) }
- .debug_line 0 : { *(.debug_line) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- .debug_aranges 0 : { *(.debug_aranges) }
-
- _end = .;
+ . = ALIGN(4);
+ .text : {
+ *(.init)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .nobss : { *(.nobss) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ __bss_end = .;
+
+ /* stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+
+ _end = .;
}
diff --git a/bsp/x86/x86_ram.lds b/bsp/x86/x86_ram.lds
index 089d9973c4..6344f62bbf 100644
--- a/bsp/x86/x86_ram.lds
+++ b/bsp/x86/x86_ram.lds
@@ -21,7 +21,7 @@ SECTIONS
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
- . = ALIGN(4);
+ . = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab));
__rtmsymtab_end = .;
@@ -32,7 +32,7 @@ SECTIONS
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
}
-
+
. = ALIGN(4);
.rodata : { *(.rodata*) }
@@ -57,6 +57,6 @@ SECTIONS
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
-
+
_end = .;
}
diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds
index ab85fa4c13..e3b0df4d39 100644
--- a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds
+++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds
@@ -45,117 +45,117 @@ ENTRY(Reset_Handler)
SECTIONS
{
- .text :
- {
- *flash_start*.o
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
-
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
-
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
-
- . = ALIGN(4);
- __exidx_start = .;
-
- __etext = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- KEEP(*(.jcr*))
- . = ALIGN(4);
- /* All data end */
- __data_end__ = .;
-
- } > RAM
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start__ = .;
- *(.bss*)
- *(COMMON)
- . = ALIGN(4);
- __bss_end__ = .;
- } > RAM
-
- .heap (COPY):
- {
- __end__ = .;
- PROVIDE(end = .);
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+ .text :
+ {
+ *flash_start*.o
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+
+ . = ALIGN(4);
+ __exidx_start = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct
index 71ad394af9..40596eca14 100644
--- a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct
+++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct
@@ -11,22 +11,22 @@ LR_IROM1 0x00000000 0x0007fff { ; load region size_region
}
LR_IROM3 0x1000200 0x200{
- ER_IROM3 0x1000200 {
- flash_start.o (|.flash_start|,+RO)
- }
+ ER_IROM3 0x1000200 {
+ flash_start.o (|.flash_start|,+RO)
+ }
ER_IROM3_1 0x1000340 {
- startup.o (|.INIT_STACK_HEAP|,+RO)
- }
+ startup.o (|.INIT_STACK_HEAP|,+RO)
+ }
}
LR_IROM4 0x1000400 0x1000000{
- ER_IROM4 0x1000400 {
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- RW_IRAM1 0x00020000 0x010000 { ; RW data
- .ANY (+RW +ZI)
- }
+ ER_IROM4 0x1000400 {
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 0x00020000 0x010000 { ; RW data
+ .ANY (+RW +ZI)
+ }
}
--
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