diff --git a/bsp/CME_M7/CME_M7.sct b/bsp/CME_M7/CME_M7.sct index ece5e2a5ec0f932599e7311a13f708830b777baa..31364ac0a53e4c9eea5af8dba6cee48278b0c66f 100644 --- a/bsp/CME_M7/CME_M7.sct +++ b/bsp/CME_M7/CME_M7.sct @@ -1,22 +1,22 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -; load region size_region -LR_IROM1 (0) (1024 * 128) -{ - ; load address = execution address - ER_IROM1 (0) (1024 * 128) - { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; RW data - RW_IRAM1 0x20000000 (1024 * 48) - { - .ANY (+RW +ZI) - } -} - +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +; load region size_region +LR_IROM1 (0) (1024 * 128) +{ + ; load address = execution address + ER_IROM1 (0) (1024 * 128) + { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; RW data + RW_IRAM1 0x20000000 (1024 * 48) + { + .ANY (+RW +ZI) + } +} + diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index aebee8de3044607786653bf0c52753731a94acdf..a7264c63ac6209d1717fb2f73d2c2b0bd3130394 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -1,272 +1,272 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xxa_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x00002000 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00002000 - -; The size of the stack section at the end of CM0+ SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Public RAM -; This is an unprotected public RAM region, with the placed .cy_sharedmem section. -; This region is used to place objects that require full access from both cores. -; Uncomment the following lines, define the region size and uncomment placement of -; .cy_sharedmem section below. -; #define PUBLIC_RAM_SIZE %REGION_SIZE% -; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. - ;RW_IRAM2 PUBLIC_RAM_START UNINIT - ;{ - ; * (.cy_sharedmem) - ;} - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00200000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf index 08d924448dae92f7178e7a55ffa8eb1227c3de73..7480a1090623f27df38b4b5e704fd1e5e80fe1ab 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -1,253 +1,253 @@ -/******************************************************************************* -* \file cy8c6xxa_cm0plus.icf -* \version 2.91 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2021 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -/*-Sizes-*/ -if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol __ICFEDIT_size_cstack__ = 0x1000; -} else { - define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; -} -define symbol __ICFEDIT_size_proc_stack__ = 0x0; - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM0+ core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; - -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - - -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; - -/* Public RAM - * This is an unprotected public RAM region, with the placed .cy_sharedmem section. - * This region is used to place objects that require full access from both cores. - * Uncomment the following lines, define region size, and uncomment the placement of - * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__ - * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region. - */ -/* -define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; -*/ - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; -define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; -define block RO {first section .intvec, readonly}; - -define block cy_xip { section .cy_xip }; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application */ -".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; -place in IROM1_region { block RO }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -"cy_xip" : place at start of EROM1_region { block cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { readwrite }; -place at end of IRAM1_region { block HSTACK }; - -/* Public RAM - *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. - */ -/* -place at start of IRAM2_region { section .cy_sharedmem }; -*/ - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_app_header, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00200000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ +/******************************************************************************* +* \file cy8c6xxa_cm0plus.icf +* \version 2.91 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +/* Public RAM + * This is an unprotected public RAM region, with the placed .cy_sharedmem section. + * This region is used to place objects that require full access from both cores. + * Uncomment the following lines, define region size, and uncomment the placement of + * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__ + * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region. + */ +/* +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +*/ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM + *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. + */ +/* +place at start of IRAM2_region { section .cy_sharedmem }; +*/ + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 4c3b188cc94a79c3311e01d0843245caca73b379..edd6046930afbc8fe2fa859a7ec6522afd43c64e 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -1,277 +1,277 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08002000 -#define RAM_SIZE 0x000FD800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00200000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00200000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x000FD800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00200000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index fb4071c60dcc86c2cd7ee93a80785e67da21f747..14ea8bcbacf011049bb3859f00e91e227b8d501e 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,247 +1,247 @@ -/******************************************************************************* -* \file cy8c6xxa_cm4_dual.icf -* \version 2.91 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2021 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; - -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - - -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/*-Sizes-*/ -if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol __ICFEDIT_size_cstack__ = 0x1000; -} else { - define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; -} -define symbol __ICFEDIT_size_proc_stack__ = 0x0; - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} -/**** End of ICF editor section. ###ICF###*/ - -/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. - * More about CM0+ prebuilt images, see here: - * https://github.com/cypresssemiconductorco/psoc6cm0p - */ -/* The size of the Cortex-M0+ application image */ -define symbol FLASH_CM0P_SIZE = 0x2000; - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; -define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; -define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; -define block RO {first section .intvec, readonly}; - -define block cy_xip { section .cy_xip }; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application image */ -place at start of IROM1_region { block CM0P_RO }; - -/* Flash - Cortex-M4 application */ -place in IROM1_region { block RO }; - -/* Used for the digital signature of the secure application and the Bootloader SDK application. */ -".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -"cy_xip" : place at start of EROM1_region { block cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { readwrite }; -place at end of IRAM1_region { block HSTACK }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_m0p_image, - section .cy_app_signature, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00200000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ +/******************************************************************************* +* \file cy8c6xxa_cm4_dual.icf +* \version 2.91 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct index 425ce1da0b112a3c0ef414e38334775ce59d021a..88cb7751d578133a325b6902c55269bb97c60843 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct @@ -1,292 +1,292 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx4_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00040000 -#define __cy_memory_0_row_size 0x200 - - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct index ebe15e2a3b7b7ecc85188eac20d06cb172efd41b..cb14c283d35443743e429819f143c23afe1b5333 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct @@ -1,311 +1,311 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx5_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00080000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx5_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct index 42069ae16048b7b7737bf1f709d9d89fba8f8522..d47e3fd6b6d06944f25efc21a6179b5a70109c23 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct @@ -1,311 +1,311 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx6_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00080000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx6_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index 6fac0911a641ee1dee3ed7103453948aa32029c2..84f1e3d4f9580e0dab683aad2ac6a2c9525d1772 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -1,311 +1,311 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx7_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct index 116340f4a7893002ada6024406a8c31713a9a6e6..dd59dd6cf5e69371dfba519fdf285c594a361e48 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct @@ -1,311 +1,311 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx8_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx8_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index 396f39cbc48070efc7346f87f6c6b9bc766659d0..08ad870ec0b08b4ed200e3793ef3a4cbe21e234e 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -1,311 +1,311 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xxa_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00200000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct index cb46c0103f7dabe8c8b19610d61de6822c6dc247..efef939e8fd51cdcb10ca8f5a302e766e8389c74 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct @@ -1,288 +1,288 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx5_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00010000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08020000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0000C000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00070000 -#define __cy_memory_0_row_size 0x200 - - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00010000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08020000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0000C000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct index 0fc6b61c8fd29eacd3910797dacff736e4323ee6..d1a588245ae60d5804588d1b5549ce053c0decc3 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -1,307 +1,307 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx7_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00010000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08020000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0000C000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x000D0000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00010000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08020000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0000C000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct index b0b99a6d8d7a9619180d43276fa1fb9aa72bcfc4..4fb7a6ad9d58dd4583e92784598f29964fcde3ef 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -1,307 +1,307 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xxa_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00010000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x080E0000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0000C000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x001D0000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00010000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x080E0000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0000C000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct index 675831f8fd51a76503d9726ec2322abf3585fc1e..2a70bf9b48cce8d443d5080b4012b7f8e10922ed 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct @@ -1,295 +1,295 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx4_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00040000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0001D800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM MBED_ROM_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00040000 -#define __cy_memory_0_row_size 0x200 - - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00040000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct index 153d577ac26a18fe6ca6ef41626f187ea51e833f..8e15b545f04cb5b05e487deffc7c6b56cafce5f1 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct @@ -1,314 +1,314 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx5_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00080000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0003D800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM MBED_ROM_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00080000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx5_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00080000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0003D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct index f6403e6b38c6ae877a7b8a41447d06e05a6024fd..f89e92fe2c47b7591b399376a98b40a18e53ccce 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct @@ -1,314 +1,314 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx6_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00080000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0001D800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM MBED_ROM_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00080000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx6_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00080000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index a9c4ac0cbe18c2e42aa719f9a167ebd4c2a15dcf..3ca5d47fdba2a7c80f77532d2cd7d52d7f74dc01 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -1,314 +1,314 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00100000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00045800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM MBED_ROM_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00100000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00045800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct index 947c560a44af23e0507fe095c5ba2b726511f1fc..84ba02e7248b1c107437860380c277a0d2f81169 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct @@ -1,314 +1,314 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx8_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00100000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0007D800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM MBED_ROM_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx8_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00100000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0007D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 185f0cc4ef345aa2b6eb969a3981640e59830f5a..7148dc7deea1e6397b3a0f3224870f8ff156462a 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -1,314 +1,314 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00200000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000FD800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM MBED_ROM_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00200000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00200000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x000FD800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct index 2c54484d124432b67273ae54871f2e067776bdcf..0ae7ed09071df448ec2b76ad786ac689dd468d77 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct @@ -1,298 +1,298 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx5_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x10000 - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00030000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000800 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0001F800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00070000 -#define __cy_memory_0_row_size 0x200 - - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x10000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00030000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000800 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001F800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct index e589c96d3f1d9f26b291bdd17e65140fa2f1ac8e..593d74167c40a0e8f7ec99d8dc9b7ec552154810 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct @@ -1,317 +1,317 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx7_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x10000 - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00068000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000800 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0001F800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x000D0000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x10000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00068000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000800 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001F800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct index 349f7cdcff9d9faf8f03b01ed15f54b2c47bbe4a..510070751f514021099b29d062c6f3c663a58460 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct @@ -1,317 +1,317 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xxa_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x10000 - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x000E0000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000800 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000DF800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x001D0000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x10000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x000E0000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000800 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x000DF800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct index da8478fcd95c79377ff543dae4a59974f07f7421..20f93b9d31aad4c770fe04629b262dd6dca157b8 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct @@ -1,253 +1,253 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx4_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x00002000 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00002000 - -; The size of the stack section at the end of CM0+ SRAM -#define STACK_SIZE 0x00001000 - - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Public RAM -; This is an unprotected public RAM region, with the placed .cy_sharedmem section. -; This region is used to place objects that require full access from both cores. -; Uncomment the following lines, define the region size and uncomment placement of -; .cy_sharedmem section below. -; #define PUBLIC_RAM_SIZE %REGION_SIZE% -; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. - ;RW_IRAM2 PUBLIC_RAM_START UNINIT - ;{ - ; * (.cy_sharedmem) - ;} - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } -} - - - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00040000 -#define __cy_memory_0_row_size 0x200 - - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct index 796c29ab17992e787de23d92df062b111a04485b..f164926a12d810ecf253796a432ee492f0b8d00e 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct @@ -1,272 +1,272 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx5_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x00002000 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00002000 - -; The size of the stack section at the end of CM0+ SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Public RAM -; This is an unprotected public RAM region, with the placed .cy_sharedmem section. -; This region is used to place objects that require full access from both cores. -; Uncomment the following lines, define the region size and uncomment placement of -; .cy_sharedmem section below. -; #define PUBLIC_RAM_SIZE %REGION_SIZE% -; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. - ;RW_IRAM2 PUBLIC_RAM_START UNINIT - ;{ - ; * (.cy_sharedmem) - ;} - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00080000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx5_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct index 09e04730fa982fb2754dc51d17c860c27ce1482c..2ca1e091e84b217943dc57951b584147118c0f34 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct @@ -1,272 +1,272 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx6_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x00002000 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00002000 - -; The size of the stack section at the end of CM0+ SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Public RAM -; This is an unprotected public RAM region, with the placed .cy_sharedmem section. -; This region is used to place objects that require full access from both cores. -; Uncomment the following lines, define the region size and uncomment placement of -; .cy_sharedmem section below. -; #define PUBLIC_RAM_SIZE %REGION_SIZE% -; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. - ;RW_IRAM2 PUBLIC_RAM_START UNINIT - ;{ - ; * (.cy_sharedmem) - ;} - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00080000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx6_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index 7d9777abc4668a7d6246ff728ae6041160317484..c54c106ec1f6be10a8ca17893182c7f10a339285 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -1,272 +1,272 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx7_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x00002000 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00002000 - -; The size of the stack section at the end of CM0+ SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Public RAM -; This is an unprotected public RAM region, with the placed .cy_sharedmem section. -; This region is used to place objects that require full access from both cores. -; Uncomment the following lines, define the region size and uncomment placement of -; .cy_sharedmem section below. -; #define PUBLIC_RAM_SIZE %REGION_SIZE% -; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. - ;RW_IRAM2 PUBLIC_RAM_START UNINIT - ;{ - ; * (.cy_sharedmem) - ;} - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct index de1f303dae108a87e9b67a2c0fe87f9ce2ffdc8d..09ccbda21b387ae8116099cd2a1c347685199a05 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct @@ -1,272 +1,272 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx8_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x00002000 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00002000 - -; The size of the stack section at the end of CM0+ SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Public RAM -; This is an unprotected public RAM region, with the placed .cy_sharedmem section. -; This region is used to place objects that require full access from both cores. -; Uncomment the following lines, define the region size and uncomment placement of -; .cy_sharedmem section below. -; #define PUBLIC_RAM_SIZE %REGION_SIZE% -; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. - ;RW_IRAM2 PUBLIC_RAM_START UNINIT - ;{ - ; * (.cy_sharedmem) - ;} - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx8_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index aebee8de3044607786653bf0c52753731a94acdf..a7264c63ac6209d1717fb2f73d2c2b0bd3130394 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -1,272 +1,272 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xxa_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x00002000 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00002000 - -; The size of the stack section at the end of CM0+ SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Public RAM -; This is an unprotected public RAM region, with the placed .cy_sharedmem section. -; This region is used to place objects that require full access from both cores. -; Uncomment the following lines, define the region size and uncomment placement of -; .cy_sharedmem section below. -; #define PUBLIC_RAM_SIZE %REGION_SIZE% -; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. - ;RW_IRAM2 PUBLIC_RAM_START UNINIT - ;{ - ; * (.cy_sharedmem) - ;} - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00200000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct index ff156a114a1325e6942107f77f6d89248f26931e..453596df89eb47a0fe33b840dc260ddb5eaa713c 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct @@ -1,244 +1,244 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx5_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. -; RAM -#define RAM_START 0x08020000 -#define RAM_SIZE 0x0000C000 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00010000 - -; The size of the stack section at the end of CM0+ SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Public RAM -#define PUBLIC_RAM_SIZE 0x800 -#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) - -; Cortex-M0+ application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } -} - - - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00070000 -#define __cy_memory_0_row_size 0x200 - - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08020000 +#define RAM_SIZE 0x0000C000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00010000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +#define PUBLIC_RAM_SIZE 0x800 +#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct index 097000cb52541ef644df8903cfb1a836553531d9..d9de0fcef351baa09f22db4f5c4b7a91a13d3612 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -1,263 +1,263 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx7_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. -; RAM -#define RAM_START 0x08020000 -#define RAM_SIZE 0x0000C000 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00010000 - -; The size of the stack section at the end of CM0+ SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Public RAM -#define PUBLIC_RAM_SIZE 0x800 -#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) - -; Cortex-M0+ application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x000D0000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08020000 +#define RAM_SIZE 0x0000C000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00010000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +#define PUBLIC_RAM_SIZE 0x800 +#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct index 8c51598493d3fcb113ccaa2cc6f7ed0a933ac166..d44a8a70a6b023454109dde73d4f08e007e8d4e1 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -1,263 +1,263 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xxa_cm0plus.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. -; RAM -#define RAM_START 0x080E0000 -#define RAM_SIZE 0x0000C000 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00010000 - -; The size of the stack section at the end of CM0+ SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Public RAM -#define PUBLIC_RAM_SIZE 0x800 -#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) - -; Cortex-M0+ application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x001D0000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x080E0000 +#define RAM_SIZE 0x0000C000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00010000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +#define PUBLIC_RAM_SIZE 0x800 +#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf index 5e32a338e194ccd8c4ac56e1d43777737d5da41b..d6281143841356a3465b6b515c43be49532d68e8 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf @@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; -/* Public RAM +/* Public RAM * This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This region is used to place objects that require full access from both cores. * Uncomment the following lines, define region size, and uncomment the placement of @@ -198,7 +198,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram}; place in IRAM1_region { readwrite }; place at end of IRAM1_region { block HSTACK }; -/* Public RAM +/* Public RAM *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. */ /* diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf index 15f3f5feed9cd0945d8ff520a643f0fb0ff6a47d..95e65d84fa7e2ae1baa8f8a17862fd565dca3583 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf @@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; -/* Public RAM +/* Public RAM * This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This region is used to place objects that require full access from both cores. * Uncomment the following lines, define region size, and uncomment the placement of @@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram}; place in IRAM1_region { readwrite }; place at end of IRAM1_region { block HSTACK }; -/* Public RAM +/* Public RAM *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. */ /* diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf index b945bbdfc81a3910f0472244831976d46e90f392..f704bba22f2ff98a993ab9e7a1f15d2d651816ed 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf @@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; -/* Public RAM +/* Public RAM * This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This region is used to place objects that require full access from both cores. * Uncomment the following lines, define region size, and uncomment the placement of @@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram}; place in IRAM1_region { readwrite }; place at end of IRAM1_region { block HSTACK }; -/* Public RAM +/* Public RAM *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. */ /* diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index c53fc413f018df6ad1633553a079b05d9cbed329..41e5e75061d025344dd2d27c30831f3bf2d55f64 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; -/* Public RAM +/* Public RAM * This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This region is used to place objects that require full access from both cores. * Uncomment the following lines, define region size, and uncomment the placement of @@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram}; place in IRAM1_region { readwrite }; place at end of IRAM1_region { block HSTACK }; -/* Public RAM +/* Public RAM *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. */ /* diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf index 98af027cb85bf711450abf5be095fad3e0e72d7d..05ce3d70c332e26eaf935bc39039f83eb11a2b8b 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf @@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; -/* Public RAM +/* Public RAM * This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This region is used to place objects that require full access from both cores. * Uncomment the following lines, define region size, and uncomment the placement of @@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram}; place in IRAM1_region { readwrite }; place at end of IRAM1_region { block HSTACK }; -/* Public RAM +/* Public RAM *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. */ /* diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf index 57e88ec72a93cb411ad04b84ebd5162c59a8ba22..7480a1090623f27df38b4b5e704fd1e5e80fe1ab 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; -/* Public RAM +/* Public RAM * This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This region is used to place objects that require full access from both cores. * Uncomment the following lines, define region size, and uncomment the placement of @@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram}; place in IRAM1_region { readwrite }; place at end of IRAM1_region { block HSTACK }; -/* Public RAM +/* Public RAM *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. */ /* diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct index 6d18b843a8637976acc8ca8f35cf2d7286173196..bb0c7c0e7ef7678e507d1211a79ff053c1227552 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct @@ -1,240 +1,240 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx4_cm4.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x0001F780 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00040000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00040000 -#define __cy_memory_0_row_size 0x200 - - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm4.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x0001F780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00040000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct index 508cd4146cf039d54c91f82df8e6c7ac45f95872..bcfaaac2c5c2a3c02103c80f6b4a84ae243102c1 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct @@ -1,258 +1,258 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx4_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08002000 -#define RAM_SIZE 0x0001D800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00040000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00040000 -#define __cy_memory_0_row_size 0x200 - - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x0001D800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00040000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct index 65f379ce049bc27099fed0deaaffdab75b1bcd1e..2f6005ce9278aa23ac3490827c7bc0ad5b05f5ea 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct @@ -1,259 +1,259 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx5_cm4.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x0003F780 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00080000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00080000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx5_cm4.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x0003F780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct index c807911140ed82a7757433477c1c4d00cd494546..c6d41174defd8e4396e24ef509f805d1a48d0bb9 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct @@ -1,277 +1,277 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx5_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08002000 -#define RAM_SIZE 0x0003D800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00080000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00080000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx5_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x0003D800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct index ad7f999f35f1cdfe42ac9d4f847199bd83e85338..b238b17565ead8cfa4bc8d457e8352739efa1bdc 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct @@ -1,259 +1,259 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx6_cm4.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x0001F780 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00080000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00080000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx6_cm4.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x0001F780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct index 56fabc2e5eff7f42b9d54b063eb7b4588f497e27..aab696d6fabd48c2d70bd5c49bb05a362451590e 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct @@ -1,277 +1,277 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx6_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08002000 -#define RAM_SIZE 0x0001D800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00080000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00080000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx6_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x0001D800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct index 85129023af254e52a63803637f11c05d9df4b1a1..8e71321b07b92829a046dbb19a33ce185c3e5aa2 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct @@ -1,259 +1,259 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx7_cm4.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x00047780 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00100000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00047780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 5188f053df6be08b1153f2ba413c3b16ef1e6635..a4d7de18ab7a00afb72136e55dc5bdb6b719b4f4 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -1,277 +1,277 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08002000 -#define RAM_SIZE 0x00045800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00100000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x00045800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual_cm0p_bless.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual_cm0p_bless.sct index 615be1fea2eb775113b0d9196ea7525145e047a9..a6c1c5727aa715bb09423db5e24155b36e0106b8 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual_cm0p_bless.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual_cm0p_bless.sct @@ -1,280 +1,280 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx7_cm4_dual_cm0p_bless.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* This linker script is modified from cy8c6xx7_cm4_dual.sct for CM0P_BLESS image. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08003000 -#define RAM_SIZE 0x00044800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00100000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -; Size and start address of the Cortex-M0+ application image -FLASH_CM0P_SIZE = 0x20000; - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual_cm0p_bless.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* This linker script is modified from cy8c6xx7_cm4_dual.sct for CM0P_BLESS image. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08003000 +#define RAM_SIZE 0x00044800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +; Size and start address of the Cortex-M0+ application image +FLASH_CM0P_SIZE = 0x20000; + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct index 1ed7c95aee5144d4e56a6da7e7de8a556e4aa4c1..71e8ea7a5deba10b4eb08e299fa766b07db9bde8 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct @@ -1,259 +1,259 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx8_cm4.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x0007F780 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00100000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx8_cm4.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x0007F780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct index 21a4d64a4079c64fe99f3f67011f32a831517557..6974354f3f6b6efe4e0efbd907ac0a0d45c42adf 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct @@ -1,277 +1,277 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx8_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08002000 -#define RAM_SIZE 0x0007D800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00100000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx8_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x0007D800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct index 352f2984600e38cc194c8185f849c0979b313df6..777a4630e664200d145ad546de5268a9eb9cae3a 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct @@ -1,259 +1,259 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xxa_cm4.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x000FF780 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00200000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00200000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x000FF780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00200000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 4c3b188cc94a79c3311e01d0843245caca73b379..edd6046930afbc8fe2fa859a7ec6522afd43c64e 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -1,277 +1,277 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08002000 -#define RAM_SIZE 0x000FD800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00200000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00200000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x000FD800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00200000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct index f3eeddeb65211bb129293cecb6fccd22adc16666..df2a91a7f858f37b669e6848017616bce0189cf3 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct @@ -1,133 +1,133 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx5_cm4.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10020000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; RAM -#define RAM_START 0x08001800 -#define RAM_SIZE 0x0001E800 -; Flash -#define FLASH_START 0x10020000 -#define FLASH_SIZE 0x00020000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - - -; The following defines describe device specific memory regions and must not be changed. -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - - - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm4.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10020000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START 0x08001800 +#define RAM_SIZE 0x0001E800 +; Flash +#define FLASH_START 0x10020000 +#define FLASH_SIZE 0x00020000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + + + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct index 4e2826d45db8ecd648b9b4675c8a4e9af5954be8..1a2ed0c260d417b01b4f493bdb91ba775a812ad5 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct @@ -1,147 +1,147 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx5_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08000800 -#define RAM_SIZE 0x0001F800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00030000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The size of the Cortex-M0+ application image (including MCU boot header area) -#define FLASH_CM0P_SIZE 0x10000 - - -; The following defines describe device specific memory regions and must not be changed. -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - - -; Cortex-M0+ application flash image area -LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) -{ - .cy_m0p_image +0 - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08000800 +#define RAM_SIZE 0x0001F800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00030000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The size of the Cortex-M0+ application image (including MCU boot header area) +#define FLASH_CM0P_SIZE 0x10000 + + +; The following defines describe device specific memory regions and must not be changed. +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + + +; Cortex-M0+ application flash image area +LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct index 3c3398d9f0109265ae8a65819716a8c356b477e9..39753f8c16f9e395a00c5cdaaa000edcc4f3ad0a 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct @@ -1,148 +1,148 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx7_cm4.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10060000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; RAM -#define RAM_START 0x08001800 -#define RAM_SIZE 0x0001E800 -; Flash -#define FLASH_START 0x10060000 -#define FLASH_SIZE 0x00030000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - - - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm4.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10060000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START 0x08001800 +#define RAM_SIZE 0x0001E800 +; Flash +#define FLASH_START 0x10060000 +#define FLASH_SIZE 0x00030000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + + + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct index 8a319053dd085702820cc26d8e1c8b39ce8886ea..1088b3f2cfd258ec830b9b050ac3d23a7b314447 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct @@ -1,162 +1,162 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx7_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08000800 -#define RAM_SIZE 0x0001F800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00068000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The size of the Cortex-M0+ application image (including MCU boot header area) -#define FLASH_CM0P_SIZE 0x10000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - - -; Cortex-M0+ application flash image area -LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) -{ - .cy_m0p_image +0 - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08000800 +#define RAM_SIZE 0x0001F800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00068000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The size of the Cortex-M0+ application image (including MCU boot header area) +#define FLASH_CM0P_SIZE 0x10000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + + +; Cortex-M0+ application flash image area +LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct index 4e95b5e68beadc2a85f98e48d061d842d41fe749..eb2ab7a0488c72403f49fc1bcfa764657ca503fd 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct @@ -1,148 +1,148 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xxa_cm4.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x100E0000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; RAM -#define RAM_START 0x08001800 -#define RAM_SIZE 0x000DE800 -; Flash -#define FLASH_START 0x100E0000 -#define FLASH_SIZE 0x00070000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - - - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm4.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x100E0000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START 0x08001800 +#define RAM_SIZE 0x000DE800 +; Flash +#define FLASH_START 0x100E0000 +#define FLASH_SIZE 0x00070000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + + + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct index 55293df906955b279e4fc5c2b32eee85d21a9f90..e50d22c8eeffd179690ec798348880d72bd0de96 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct @@ -1,162 +1,162 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xxa_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08000800 -#define RAM_SIZE 0x000DF800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x000E0000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The size of the Cortex-M0+ application image (including MCU boot header area) -#define FLASH_CM0P_SIZE 0x10000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - - -; Cortex-M0+ application flash image area -LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) -{ - .cy_m0p_image +0 - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08000800 +#define RAM_SIZE 0x000DF800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x000E0000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The size of the Cortex-M0+ application image (including MCU boot header area) +#define FLASH_CM0P_SIZE 0x10000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + + +; Cortex-M0+ application flash image area +LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cys06xxa_cm4.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cys06xxa_cm4.sct index e5001ffa1e1b4474ad9e96a11e0d7251ed0f4934..ee4d7b3b646a443e42a8c3cd2f84ebf23f1719c1 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cys06xxa_cm4.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cys06xxa_cm4.sct @@ -1,148 +1,148 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cys06xxa_cm4.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10050000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; RAM -#define RAM_START 0x08030000 -#define RAM_SIZE 0x000B7000 -; Flash -#define FLASH_START 0x10050000 -#define FLASH_SIZE 0x0011C000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - - - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cys06xxa_cm4.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10050000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START 0x08030000 +#define RAM_SIZE 0x000B7000 +; Flash +#define FLASH_START 0x10050000 +#define FLASH_SIZE 0x0011C000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + + + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct index dc25deabc3ab5847bc051076a6a37ab05382a571..368da5ccf2ad664055c428677ee8429985cc80cc 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct @@ -1,159 +1,159 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 -march=armv8-m.main -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -/***************************************************************************//** -* \file cyw20829_ns_flash_cbus.sct -* \version 1.0.0 -* -* Linker file for the ARMCC compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point location starts at 0x0401e000. The valid -* application image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or -* an affiliate of Cypress Semiconductor Corporation. -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#define flash_start_addr_cbus 0x08000000 -#define ram_start_addr_sahb 0x20000000 -#define ram_start_addr_cbus 0x04000000 -#define ram_end_addr_sahb 0x20020000 - -#define app_code_offset_flash 0x00002200 -#define bootstrap_offset_ram 0x0001E000 - -; The size of the stack section at the end of CM33 SRAM -#define STACK_SIZE 0x00001000 - - -/* VMA for bootstrap Text */ -#define bootstrapText_vma ram_start_addr_cbus + bootstrap_offset_ram /* 0x0401E000 */ -/* Size of bootstrap section */ -#define bootstrapText_size 0x00002000 - -/* VMA for bootstrap Data */ -#define bootstrapRamVect_vma ram_start_addr_sahb + STACK_SIZE /* 0x20001000 */ - -/* VMA for flash */ -#define appText_vma flash_start_addr_cbus + app_code_offset_flash /* 0x08002200 */ - -/* Memory reserved for Bootstrap code and data */ -#define BOOTSTRAP_SIZE ram_end_addr_sahb - ram_start_addr_sahb - bootstrap_offset_ram; /* 0x00002000 */ - -; Cortex-M33 application flash area -LR_1 bootstrapText_vma BOOTSTRAP_SIZE -{ - bootstrap bootstrapText_vma bootstrapText_size - { - * (RESET, +FIRST) - * (InRoot$$Sections) - - ns_start_cyw20829.o (+RO) - ns_system_cyw20829.o (+RO) - - /* drivers */ - cy_device.o (+RO) - cy_btss.o (+RO) - cy_sysclk_v2.o (+RO) - cy_syspm_v2.o (+RO) - cy_sysint_v2.o (+RO) - cy_syslib*.o (+RO) - ppu_v1.o (+RO) - cy_mpc.o (+RO) - cy_pd_ppu.o (+RO) - *(.cy_l1func*) - } - -/* converting c-bus to sahb address */ -#define bootstrapData_vma AlignExpr((ImageLimit(bootstrap) - ram_start_addr_cbus) + ram_start_addr_sahb, 4) - - bootstrapData bootstrapData_vma ALIGN 4 - { - ns_start_cyw20829.o (+RW, +ZI) - ns_system_cyw20829.o (+RW, +ZI) - - /* drivers */ - cy_device.o (+RW, +ZI) - cy_btss.o (+RW, +ZI) - cy_sysclk_v2.o (+RW, +ZI) - cy_syspm_v2.o (+RW, +ZI) - cy_sysint_v2.o (+RW, +ZI) - cy_syslib*.o (+RW, +ZI) - ppu_v1.o (+RW, +ZI) - cy_mpc.o (+RW, +ZI) - cy_pd_ppu.o (+RW, +ZI) - } - - bootstrap_vector bootstrapRamVect_vma UNINIT - { - * (.bss.noinit.RESET_RAM, +FIRST) - } -} - -#define appTextRam_vma AlignExpr(ImageLimit( bootstrap_vector), 8) - -LR_2 appText_vma -{ - app appText_vma - { - * (+RO) - } - - appTextRam appTextRam_vma - { - * (.cy_ramfunc) - cy_smif.o (+RO) - cy_smif_memslot.o (+RO) - } - -#define appData_vma AlignExpr((ImageLimit(appTextRam) - ImageBase(appTextRam) + ImageLimit(bootstrap_vector)), 8) - - appData appData_vma - { - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - appData_noinit +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((ram_start_addr_sahb + bootstrap_offset_ram)-AlignExpr(ImageLimit(appData_noinit), 8)) - { - } - - ; Stack region growing down - ARM_LIB_STACK (ram_start_addr_sahb + STACK_SIZE) ALIGN 32 EMPTY -STACK_SIZE - { - } -} -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 -march=armv8-m.main +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +/***************************************************************************//** +* \file cyw20829_ns_flash_cbus.sct +* \version 1.0.0 +* +* Linker file for the ARMCC compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location starts at 0x0401e000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#define flash_start_addr_cbus 0x08000000 +#define ram_start_addr_sahb 0x20000000 +#define ram_start_addr_cbus 0x04000000 +#define ram_end_addr_sahb 0x20020000 + +#define app_code_offset_flash 0x00002200 +#define bootstrap_offset_ram 0x0001E000 + +; The size of the stack section at the end of CM33 SRAM +#define STACK_SIZE 0x00001000 + + +/* VMA for bootstrap Text */ +#define bootstrapText_vma ram_start_addr_cbus + bootstrap_offset_ram /* 0x0401E000 */ +/* Size of bootstrap section */ +#define bootstrapText_size 0x00002000 + +/* VMA for bootstrap Data */ +#define bootstrapRamVect_vma ram_start_addr_sahb + STACK_SIZE /* 0x20001000 */ + +/* VMA for flash */ +#define appText_vma flash_start_addr_cbus + app_code_offset_flash /* 0x08002200 */ + +/* Memory reserved for Bootstrap code and data */ +#define BOOTSTRAP_SIZE ram_end_addr_sahb - ram_start_addr_sahb - bootstrap_offset_ram; /* 0x00002000 */ + +; Cortex-M33 application flash area +LR_1 bootstrapText_vma BOOTSTRAP_SIZE +{ + bootstrap bootstrapText_vma bootstrapText_size + { + * (RESET, +FIRST) + * (InRoot$$Sections) + + ns_start_cyw20829.o (+RO) + ns_system_cyw20829.o (+RO) + + /* drivers */ + cy_device.o (+RO) + cy_btss.o (+RO) + cy_sysclk_v2.o (+RO) + cy_syspm_v2.o (+RO) + cy_sysint_v2.o (+RO) + cy_syslib*.o (+RO) + ppu_v1.o (+RO) + cy_mpc.o (+RO) + cy_pd_ppu.o (+RO) + *(.cy_l1func*) + } + +/* converting c-bus to sahb address */ +#define bootstrapData_vma AlignExpr((ImageLimit(bootstrap) - ram_start_addr_cbus) + ram_start_addr_sahb, 4) + + bootstrapData bootstrapData_vma ALIGN 4 + { + ns_start_cyw20829.o (+RW, +ZI) + ns_system_cyw20829.o (+RW, +ZI) + + /* drivers */ + cy_device.o (+RW, +ZI) + cy_btss.o (+RW, +ZI) + cy_sysclk_v2.o (+RW, +ZI) + cy_syspm_v2.o (+RW, +ZI) + cy_sysint_v2.o (+RW, +ZI) + cy_syslib*.o (+RW, +ZI) + ppu_v1.o (+RW, +ZI) + cy_mpc.o (+RW, +ZI) + cy_pd_ppu.o (+RW, +ZI) + } + + bootstrap_vector bootstrapRamVect_vma UNINIT + { + * (.bss.noinit.RESET_RAM, +FIRST) + } +} + +#define appTextRam_vma AlignExpr(ImageLimit( bootstrap_vector), 8) + +LR_2 appText_vma +{ + app appText_vma + { + * (+RO) + } + + appTextRam appTextRam_vma + { + * (.cy_ramfunc) + cy_smif.o (+RO) + cy_smif_memslot.o (+RO) + } + +#define appData_vma AlignExpr((ImageLimit(appTextRam) - ImageBase(appTextRam) + ImageLimit(bootstrap_vector)), 8) + + appData appData_vma + { + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + appData_noinit +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((ram_start_addr_sahb + bootstrap_offset_ram)-AlignExpr(ImageLimit(appData_noinit), 8)) + { + } + + ; Stack region growing down + ARM_LIB_STACK (ram_start_addr_sahb + STACK_SIZE) ALIGN 32 EMPTY -STACK_SIZE + { + } +} +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct index ffe5496c8be37bd77a344b0f4c2d771b185dfcc1..cfb1fa6a55e0ca635ca969c2bf9141517a204e72 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct @@ -1,163 +1,163 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyw20829_ns.sct -;* \version 1.0.0 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2020 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM33 core. -; RAM - -#define CODE_ROM_NS_CBUS_START 0x00000000 -#define CODE_ROM_NS_CBUS_SIZE 0x00010000 -#define CODE_SRAM0_NS_CBUS_START 0x04004200 -#define CODE_SRAM0_NS_CBUS_SIZE 0x0000E000 -#define CODE_XIP_NS_CBUS_START 0x08000000 -#define CODE_XIP_NS_CBUS_SIZE 0x08000000 - -#define DATA_ROM_NS_SAHB_START 0x00000000 -#define DATA_ROM_NS_SAHB_SIZE 0x00000000 -#define BSS_ROM_NS_SAHB_START 0x00000000 -#define BSS_ROM_NS_SAHB_SIZE 0x00000000 -#define DATA_SRAM0_NS_SAHB_START 0x20012200 -#define DATA_SRAM0_NS_SAHB_SIZE 0x0000DE00 -#define BSS_SRAM0_NS_SAHB_START 0x20000000 -#define BSS_SRAM0_NS_SAHB_SIZE 0x00000000 -#define DATA_XIP_NS_SAHB_START 0x60000000 -#define DATA_XIP_NS_SAHB_SIZE 0x00000000 -#define BSS_XIP_NS_SAHB_START 0x60000000 -#define BSS_XIP_NS_SAHB_SIZE 0x00000000 - - -/* -#define RAM_START 0x20004200 -#define RAM_SIZE 0x0001BE00 -*/ -#define RAM_START DATA_SRAM0_NS_SAHB_START -#define RAM_SIZE DATA_SRAM0_NS_SAHB_SIZE - -; Flash -/* -#define FLASH_START 0x60000000 -#define FLASH_SIZE 0x00010000 -*/ - -#define FLASH_START CODE_SRAM0_NS_CBUS_START -#define FLASH_SIZE CODE_SRAM0_NS_CBUS_SIZE - -; The size of the stack section at the end of CM33 SRAM -#define STACK_SIZE 0x00001000 - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000000 - -; The following defines describe device specific memory regions and must not be changed. - -; External memory -#define XIP_START CODE_XIP_NS_CBUS_START -#define XIP_SIZE CODE_XIP_NS_CBUS_SIZE - - -; Cortex-M33 application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (.bss.noinit.RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) ALIGN 32 EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyw20829_ns.sct +;* \version 1.0.0 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM33 core. +; RAM + +#define CODE_ROM_NS_CBUS_START 0x00000000 +#define CODE_ROM_NS_CBUS_SIZE 0x00010000 +#define CODE_SRAM0_NS_CBUS_START 0x04004200 +#define CODE_SRAM0_NS_CBUS_SIZE 0x0000E000 +#define CODE_XIP_NS_CBUS_START 0x08000000 +#define CODE_XIP_NS_CBUS_SIZE 0x08000000 + +#define DATA_ROM_NS_SAHB_START 0x00000000 +#define DATA_ROM_NS_SAHB_SIZE 0x00000000 +#define BSS_ROM_NS_SAHB_START 0x00000000 +#define BSS_ROM_NS_SAHB_SIZE 0x00000000 +#define DATA_SRAM0_NS_SAHB_START 0x20012200 +#define DATA_SRAM0_NS_SAHB_SIZE 0x0000DE00 +#define BSS_SRAM0_NS_SAHB_START 0x20000000 +#define BSS_SRAM0_NS_SAHB_SIZE 0x00000000 +#define DATA_XIP_NS_SAHB_START 0x60000000 +#define DATA_XIP_NS_SAHB_SIZE 0x00000000 +#define BSS_XIP_NS_SAHB_START 0x60000000 +#define BSS_XIP_NS_SAHB_SIZE 0x00000000 + + +/* +#define RAM_START 0x20004200 +#define RAM_SIZE 0x0001BE00 +*/ +#define RAM_START DATA_SRAM0_NS_SAHB_START +#define RAM_SIZE DATA_SRAM0_NS_SAHB_SIZE + +; Flash +/* +#define FLASH_START 0x60000000 +#define FLASH_SIZE 0x00010000 +*/ + +#define FLASH_START CODE_SRAM0_NS_CBUS_START +#define FLASH_SIZE CODE_SRAM0_NS_CBUS_SIZE + +; The size of the stack section at the end of CM33 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000000 + +; The following defines describe device specific memory regions and must not be changed. + +; External memory +#define XIP_START CODE_XIP_NS_CBUS_START +#define XIP_SIZE CODE_XIP_NS_CBUS_SIZE + + +; Cortex-M33 application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (.bss.noinit.RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) ALIGN 32 EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.icf b/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.icf index fb4071c60dcc86c2cd7ee93a80785e67da21f747..14ea8bcbacf011049bb3859f00e91e227b8d501e 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.icf +++ b/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.icf @@ -1,247 +1,247 @@ -/******************************************************************************* -* \file cy8c6xxa_cm4_dual.icf -* \version 2.91 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2021 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; - -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - - -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/*-Sizes-*/ -if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol __ICFEDIT_size_cstack__ = 0x1000; -} else { - define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; -} -define symbol __ICFEDIT_size_proc_stack__ = 0x0; - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} -/**** End of ICF editor section. ###ICF###*/ - -/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. - * More about CM0+ prebuilt images, see here: - * https://github.com/cypresssemiconductorco/psoc6cm0p - */ -/* The size of the Cortex-M0+ application image */ -define symbol FLASH_CM0P_SIZE = 0x2000; - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; -define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; -define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; -define block RO {first section .intvec, readonly}; - -define block cy_xip { section .cy_xip }; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application image */ -place at start of IROM1_region { block CM0P_RO }; - -/* Flash - Cortex-M4 application */ -place in IROM1_region { block RO }; - -/* Used for the digital signature of the secure application and the Bootloader SDK application. */ -".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -"cy_xip" : place at start of EROM1_region { block cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { readwrite }; -place at end of IRAM1_region { block HSTACK }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_m0p_image, - section .cy_app_signature, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00200000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ +/******************************************************************************* +* \file cy8c6xxa_cm4_dual.icf +* \version 2.91 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.sct b/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.sct index 4c3b188cc94a79c3311e01d0843245caca73b379..edd6046930afbc8fe2fa859a7ec6522afd43c64e 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.sct +++ b/bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.sct @@ -1,277 +1,277 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08002000 -#define RAM_SIZE 0x000FD800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00200000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00200000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x000FD800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00200000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.icf b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.icf index fb4071c60dcc86c2cd7ee93a80785e67da21f747..14ea8bcbacf011049bb3859f00e91e227b8d501e 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.icf +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.icf @@ -1,247 +1,247 @@ -/******************************************************************************* -* \file cy8c6xxa_cm4_dual.icf -* \version 2.91 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2021 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; - -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - - -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/*-Sizes-*/ -if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol __ICFEDIT_size_cstack__ = 0x1000; -} else { - define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; -} -define symbol __ICFEDIT_size_proc_stack__ = 0x0; - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} -/**** End of ICF editor section. ###ICF###*/ - -/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. - * More about CM0+ prebuilt images, see here: - * https://github.com/cypresssemiconductorco/psoc6cm0p - */ -/* The size of the Cortex-M0+ application image */ -define symbol FLASH_CM0P_SIZE = 0x2000; - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; -define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; -define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; -define block RO {first section .intvec, readonly}; - -define block cy_xip { section .cy_xip }; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application image */ -place at start of IROM1_region { block CM0P_RO }; - -/* Flash - Cortex-M4 application */ -place in IROM1_region { block RO }; - -/* Used for the digital signature of the secure application and the Bootloader SDK application. */ -".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -"cy_xip" : place at start of EROM1_region { block cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { readwrite }; -place at end of IRAM1_region { block HSTACK }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_m0p_image, - section .cy_app_signature, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00200000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ +/******************************************************************************* +* \file cy8c6xxa_cm4_dual.icf +* \version 2.91 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.sct b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.sct index 4c3b188cc94a79c3311e01d0843245caca73b379..edd6046930afbc8fe2fa859a7ec6522afd43c64e 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.sct +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.sct @@ -1,277 +1,277 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.91 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2021 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08002000 -#define RAM_SIZE 0x000FD800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00200000 - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -; More about CM0+ prebuilt images, see here: -; https://github.com/cypresssemiconductorco/psoc6cm0p -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00200000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x000FD800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00200000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 5af1eb206720af5358ae0010495d52c7c927df7f..e557eedf7c6790a6db7dc9a05628de2345532b9d 100644 --- a/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -1,274 +1,274 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.60 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START 0x08002000 -#define RAM_SIZE 0x00045800 -; Flash -#define FLASH_START 0x10000000 -#define FLASH_SIZE 0x00100000 - -; Size of the stack section at the end of CM4 SRAM -#define STACK_SIZE 0x00001000 - -; Size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM FLASH_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) - { - } - - ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - .cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.sct +;* \version 2.60 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x00045800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; Size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; Size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index e30133713a85ee0957db57ccaa674262a742e307..fd57bb7b51dc070a5e166fade80a17f82c38f502 100644 --- a/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,240 +1,240 @@ -/***************************************************************************//** -* \file cy8c6xx7_cm4_dual.icf -* \version 2.60 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - - -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/*-Sizes-*/ -if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol __ICFEDIT_size_cstack__ = 0x1000; -} else { - define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; -} -define symbol __ICFEDIT_size_proc_stack__ = 0x0; - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} -/**** End of ICF editor section. ###ICF###*/ - -/* Size of the Cortex-M0+ application image */ -define symbol FLASH_CM0P_SIZE = 0x2000; - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; -define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; -define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; -define block RO {first section .intvec, readonly}; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application image */ -place at start of IROM1_region { block CM0P_RO }; - -/* Flash - Cortex-M4 application */ -place in IROM1_region { block RO }; - -/* Used for the digital signature of the secure application and the Bootloader SDK application. */ -".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -".cy_xip" : place at start of EROM1_region { section .cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { readwrite }; -place at end of IRAM1_region { block HSTACK }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_m0p_image, - section .cy_app_signature, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00100000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.icf +* \version 2.60 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/Vango/v85xx/Target_FLASH.icf b/bsp/Vango/v85xx/Target_FLASH.icf index f10a7cb75eac5213679d46d61a945609d799184f..0ef8edebb562c8668408ad512ecfd8419a4a8b6c 100644 --- a/bsp/Vango/v85xx/Target_FLASH.icf +++ b/bsp/Vango/v85xx/Target_FLASH.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/acm32/acm32f0x0-nucleo/drivers/linker_scripts/link.icf b/bsp/acm32/acm32f0x0-nucleo/drivers/linker_scripts/link.icf index bf3975c7e7997ee8b39b25b756e0f29b0fe09e50..946d411c321eb68e6a75cae667f6b7b14fd1be00 100644 --- a/bsp/acm32/acm32f0x0-nucleo/drivers/linker_scripts/link.icf +++ b/bsp/acm32/acm32f0x0-nucleo/drivers/linker_scripts/link.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x0800; -define symbol __ICFEDIT_size_heap__ = 0x0000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; - -export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; - +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0800; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; + diff --git a/bsp/acm32/acm32f4xx-nucleo/drivers/linker_scripts/link.icf b/bsp/acm32/acm32f4xx-nucleo/drivers/linker_scripts/link.icf index 9b0aee84ff540784309339726d820c4ac97054f1..b80579514176d214cfec84d79869a6bcec99e75e 100644 --- a/bsp/acm32/acm32f4xx-nucleo/drivers/linker_scripts/link.icf +++ b/bsp/acm32/acm32f4xx-nucleo/drivers/linker_scripts/link.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x0800; -define symbol __ICFEDIT_size_heap__ = 0x0000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; - -export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; - +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0800; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; + diff --git a/bsp/airm2m/air105/board/linker_scripts/link.lds b/bsp/airm2m/air105/board/linker_scripts/link.lds index 9b49ab1c3f604bebc9fb213900632a31888fb115..e8f4b1da46bda5d14ff441eb341d418fd31de607 100644 --- a/bsp/airm2m/air105/board/linker_scripts/link.lds +++ b/bsp/airm2m/air105/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/airm2m/air32f103/board/linker_scripts/link.icf b/bsp/airm2m/air32f103/board/linker_scripts/link.icf index 5019b2d673757a3e293b6d91703fc49bfdb14b24..758734c181f70a0e9d2699f7234656dac62fb406 100644 --- a/bsp/airm2m/air32f103/board/linker_scripts/link.icf +++ b/bsp/airm2m/air32f103/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/airm2m/air32f103/board/linker_scripts/link.lds b/bsp/airm2m/air32f103/board/linker_scripts/link.lds index 644fe833143ebf0ee86629578c3eb2d11e334c62..5a45f64a27fc572776b338c8f9e227807882275d 100644 --- a/bsp/airm2m/air32f103/board/linker_scripts/link.lds +++ b/bsp/airm2m/air32f103/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/allwinner/d1/link.lds b/bsp/allwinner/d1/link.lds index a6784a00ff52ddd8b0aa912e1ea6dc5d2b5ed2d1..e6a3829fc8a83c960f94c9e9a00feb2042747f1c 100644 --- a/bsp/allwinner/d1/link.lds +++ b/bsp/allwinner/d1/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -38,7 +38,7 @@ SECTIONS . = ALIGN(8); - .text : + .text : { *(.text) /* remaining code */ *(.text.*) /* remaining code */ @@ -47,7 +47,7 @@ SECTIONS *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t*) - + /* section information for finsh shell */ . = ALIGN(8); __fsymtab_start = .; @@ -74,20 +74,20 @@ SECTIONS _etext = .; } > SRAM - .eh_frame_hdr : - { - *(.eh_frame_hdr) + .eh_frame_hdr : + { + *(.eh_frame_hdr) *(.eh_frame_entry) } > SRAM .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM . = ALIGN(8); - .data : + .data : { *(.data) *(.data.*) - + *(.data1) *(.data1.*) @@ -97,7 +97,7 @@ SECTIONS *(.sdata) *(.sdata.*) } > SRAM - + . = ALIGN(8); .ctors : { @@ -139,7 +139,7 @@ SECTIONS . = ALIGN(8); - .sbss : + .sbss : { __bss_start = .; *(.sbss) diff --git a/bsp/allwinner/d1/link_stacksize.lds b/bsp/allwinner/d1/link_stacksize.lds index 8685bc0f1c2d15f0a4bf11d75e743e5a61b16d95..14c2aad91f869fa1b69de7806d2c3f8f4f68116c 100644 --- a/bsp/allwinner/d1/link_stacksize.lds +++ b/bsp/allwinner/d1/link_stacksize.lds @@ -1 +1 @@ -__STACKSIZE__ = 16384; \ No newline at end of file +__STACKSIZE__ = 16384; diff --git a/bsp/allwinner/d1s/link.lds b/bsp/allwinner/d1s/link.lds index a9f838120e922c81efa540f8ebcc86be72cde1c2..5a8daa054b5686246a2004ec1e4a3d698b3b5219 100644 --- a/bsp/allwinner/d1s/link.lds +++ b/bsp/allwinner/d1s/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -38,7 +38,7 @@ SECTIONS . = ALIGN(8); - .text : + .text : { *(.text) /* remaining code */ *(.text.*) /* remaining code */ @@ -47,7 +47,7 @@ SECTIONS *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t*) - + /* section information for finsh shell */ . = ALIGN(8); __fsymtab_start = .; @@ -74,9 +74,9 @@ SECTIONS _etext = .; } > SRAM - .eh_frame_hdr : - { - *(.eh_frame_hdr) + .eh_frame_hdr : + { + *(.eh_frame_hdr) *(.eh_frame_entry) } > SRAM .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM @@ -85,11 +85,11 @@ SECTIONS __text_end = .; __text_size = __text_end - __text_start; - .data : + .data : { *(.data) *(.data.*) - + *(.data1) *(.data1.*) @@ -141,7 +141,7 @@ SECTIONS . = ALIGN(8); - .sbss : + .sbss : { __bss_start = .; *(.sbss) diff --git a/bsp/allwinner/d1s/link_stacksize.lds b/bsp/allwinner/d1s/link_stacksize.lds index 8685bc0f1c2d15f0a4bf11d75e743e5a61b16d95..14c2aad91f869fa1b69de7806d2c3f8f4f68116c 100644 --- a/bsp/allwinner/d1s/link_stacksize.lds +++ b/bsp/allwinner/d1s/link_stacksize.lds @@ -1 +1 @@ -__STACKSIZE__ = 16384; \ No newline at end of file +__STACKSIZE__ = 16384; diff --git a/bsp/allwinner_tina/link.lds b/bsp/allwinner_tina/link.lds index 8fb0e9e84d40e39be38357b5804551d470f880fd..7ce5caaa8a894094d4129543fe0023051dc838a8 100644 --- a/bsp/allwinner_tina/link.lds +++ b/bsp/allwinner_tina/link.lds @@ -4,7 +4,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x80000000; - + . = ALIGN(4); __text_start = .; .text : @@ -12,7 +12,7 @@ SECTIONS *(.vectors) *(.text) *(.text.*) - KEEP(*(.fini)) + KEEP(*(.fini)) /* section information for finsh shell */ . = ALIGN(4); @@ -47,18 +47,18 @@ SECTIONS .ctors : { PROVIDE(__ctors_start__ = .); - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - PROVIDE(__ctors_end__ = .); + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + PROVIDE(__ctors_end__ = .); } - .ARM.extab : + .ARM.extab : { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } + *(.ARM.extab* .gnu.linkonce.armextab.*) + } /* The .ARM.exidx section is used for C++ exception handling. */ /* .ARM.exidx is sorted, so has to go in its own output section. */ __exidx_start = .; @@ -70,15 +70,15 @@ SECTIONS _sidata = .; } __exidx_end = .; - + .dtors : { PROVIDE(__dtors_start__ = .); *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) PROVIDE(__dtors_end__ = .); } @@ -89,30 +89,30 @@ SECTIONS *(.data) *(.data.*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ *(.gnu.linkonce.d*) } diff --git a/bsp/amebaz/bootloader_symbol.icf b/bsp/amebaz/bootloader_symbol.icf index 092379e623f44eaa8ea2c545d45a044bc6db4aaf..1c6ce92b41cd14d2f7daa5b706eca6ea2b149482 100644 --- a/bsp/amebaz/bootloader_symbol.icf +++ b/bsp/amebaz/bootloader_symbol.icf @@ -1,13 +1,13 @@ -/* Bootloader symbol list */ -define exported symbol BOOT_FLASH_RDP_VALID = 0x08000123; -define exported symbol BOOT_FLASH_SetStatusReg = 0x080003f5; -define exported symbol BOOT_FLASH_Image1 = 0x0800043b; -define exported symbol IMAGE1$$Base = 0x10002001; -define exported symbol RamStartTable = 0x10002001; -define exported symbol RAM_IMG1_VALID_PATTEN = 0x10002019; -define exported symbol boot_export_symbol = 0x10002021; -define exported symbol BOOT_System_Init1 = 0x10002251; -define exported symbol BOOT_System_Init2 = 0x10002263; -define exported symbol BOOT_Swd_Off = 0x10002275; -define exported symbol boot_ram_end = 0x10002455; -define exported symbol IMAGE1$$Limit = 0x10002459; +/* Bootloader symbol list */ +define exported symbol BOOT_FLASH_RDP_VALID = 0x08000123; +define exported symbol BOOT_FLASH_SetStatusReg = 0x080003f5; +define exported symbol BOOT_FLASH_Image1 = 0x0800043b; +define exported symbol IMAGE1$$Base = 0x10002001; +define exported symbol RamStartTable = 0x10002001; +define exported symbol RAM_IMG1_VALID_PATTEN = 0x10002019; +define exported symbol boot_export_symbol = 0x10002021; +define exported symbol BOOT_System_Init1 = 0x10002251; +define exported symbol BOOT_System_Init2 = 0x10002263; +define exported symbol BOOT_Swd_Off = 0x10002275; +define exported symbol boot_ram_end = 0x10002455; +define exported symbol IMAGE1$$Limit = 0x10002459; diff --git a/bsp/amebaz/image2.icf b/bsp/amebaz/image2.icf index 3c5deadf70b479451a9ba23f62e06050dea3eeb3..5d8336184781b42d4153d808288c06920f1dfe56 100644 --- a/bsp/amebaz/image2.icf +++ b/bsp/amebaz/image2.icf @@ -9,24 +9,24 @@ include "rom_symbol_v01_iar.icf"; /**************************************** * Memory Regions * ****************************************/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; define symbol __ICFEDIT_region_ROMBSS_RAM_start__ = 0x10000000; -define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF; +define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF; define symbol __ICFEDIT_region_BOOTLOADER_RAM_start__ = 0x10002000; define symbol __ICFEDIT_region_BOOTLOADER_RAM_end__ = 0x10004FFF; -define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000; -define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1002FFFF; -define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000; -define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF; -define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000; -define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF; -define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000; -define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF; -define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20; -define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF; -define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20; -define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000; +define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1002FFFF; +define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000; +define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF; +define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000; +define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF; +define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000; +define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF; +define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20; +define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF; +define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20; +define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF; /**************************************** * Sizes * ****************************************/ @@ -68,16 +68,16 @@ keep { section .hal.rom.bss* }; keep { section .wlan_ram_map* }; keep { section .libc.ram.bss* }; keep { section .ssl_ram_map* }; -define block .hal.rom.bss with fixed order{ section .ram_vector_table1, +define block .hal.rom.bss with fixed order{ section .ram_vector_table1, section .ram_vector_table2, section .ram_vector_table3, section .hal.rom.bss*, section .wlan_ram_map*, section .libc.ram.bss*, - section .ssl_ram_map*, + section .ssl_ram_map*, }; define block ROM_BSS with fixed order { block .hal.rom.bss}; -place at start of ROM_BSS_region { readwrite, +place at start of ROM_BSS_region { readwrite, block ROM_BSS, }; /**************************************** @@ -86,21 +86,21 @@ place at start of ROM_BSS_region { readwrite, keep { section .image1.entry.data* }; keep { section .image1.validate.rodata* }; define block .ram_image1.entry with fixed order{section .image1.entry.data*, - section .image1.validate.rodata*, - }; + section .image1.validate.rodata*, + }; keep { section .boot.ram.text* }; keep { section .boot.rodata* }; define block .ram_image1.text with fixed order{section .boot.ram.text*, - section .boot.rodata*, - }; + section .boot.rodata*, + }; keep { section .boot.ram.data* }; define block .ram_image1.data with fixed order{section .boot.ram.data*, - }; + }; keep { section .boot.ram.bss* }; define block .ram_image1.bss with fixed order{section .boot.ram.bss*, - }; + }; define block IMAGE1 with fixed order { block .ram_image1.entry, block .ram_image1.text, block .ram_image1.data, block .ram_image1.bss}; -place at start of BOOT_RAM_region { readwrite, +place at start of BOOT_RAM_region { readwrite, block IMAGE1, }; /**************************************** @@ -109,39 +109,39 @@ place at start of BOOT_RAM_region { readwrite, keep { section .image2.entry.data* }; keep { section .image2.validate.rodata* }; define block .ram_image2.entry with fixed order{ section .image2.entry.data*, - section .image2.validate.rodata*, - }; + section .image2.validate.rodata*, + }; define block SHT$$PREINIT_ARRAY { preinit_array }; define block SHT$$INIT_ARRAY { init_array }; define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY, - block SHT$$INIT_ARRAY }; -define block .ram.data with fixed order{ section .data*, - section DATA, - section .iar.init_table, - section __DLIB_PERTHREAD, - block CPP_INIT, - section .mdns.data, - section .mdns.text - }; + block SHT$$INIT_ARRAY }; +define block .ram.data with fixed order{ section .data*, + section DATA, + section .iar.init_table, + section __DLIB_PERTHREAD, + block CPP_INIT, + section .mdns.data, + section .mdns.text + }; define block .ram.text with fixed order{ section .image2.ram.text*, - }; + }; define block IMAGE2 with fixed order { block .ram_image2.entry, - block .ram.data, - block .ram.text, - }; + block .ram.data, + block .ram.text, + }; define block .ram_image2.bss with fixed order{ section .bss*, section COMMON, }; define block .ram_image2.skb.bss with fixed order{ section .bdsram.data* }; define block .ram_heap.data with fixed order{ section .bfsram.data* }; -place in BD_RAM_region { readwrite, - block IMAGE2, - block .ram_image2.bss, - block .ram_image2.skb.bss, - block .ram_heap.data, - section .heap.stdlib, +place in BD_RAM_region { readwrite, + block IMAGE2, + block .ram_image2.bss, + block .ram_image2.skb.bss, + block .ram_heap.data, + section .heap.stdlib, last block HEAP, - }; + }; /**************************************** * XIP BOOT Section config * ****************************************/ @@ -149,8 +149,8 @@ keep { section .flashboot.text* }; define block .xip_image1.text with fixed order{ section .flashboot.text* }; define block Bootloader with fixed order { section LOADER }; place at start of XIP_BOOT_region { block Bootloader, - readwrite, - block .xip_image1.text }; + readwrite, + block .xip_image1.text }; /**************************************** * XIP OTA1 Section config * ****************************************/ @@ -158,30 +158,30 @@ keep { section FSymTab }; keep { section VSymTab }; keep { section .rti_fn* }; define block .xip_image2.text with fixed order{ section .img2_custom_signature*, - section .text*, - section .rodata*, - section .debug_trace, - section CODE, - section Veneer, // object startup.o, - section FSymTab, - section VSymTab, - section .rti_fn*, - }; -place at start of XIP_OTA1_region { readwrite, - block .xip_image2.text }; + section .text*, + section .rodata*, + section .debug_trace, + section CODE, + section Veneer, // object startup.o, + section FSymTab, + section VSymTab, + section .rti_fn*, + }; +place at start of XIP_OTA1_region { readwrite, + block .xip_image2.text }; /**************************************** * RDP Section config * ****************************************/ -keep { section .rdp.ram.text* }; -keep { section .rdp.ram.data* }; +keep { section .rdp.ram.text* }; +keep { section .rdp.ram.data* }; define block .RDP_RAM with fixed order { - section .rdp.ram.text*, - section .rdp.ram.data* }; + section .rdp.ram.text*, + section .rdp.ram.data* }; place at start of RDP_RAM_region{ - readwrite, - block .RDP_RAM }; -define exported symbol __ram_start_table_start__= 0x10002000; // use in rom -define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code -define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code + readwrite, + block .RDP_RAM }; +define exported symbol __ram_start_table_start__= 0x10002000; // use in rom +define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code +define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code define exported symbol __flash_text_start__= 0x0800b020; // needed by ram code -define exported symbol boot_export_symbol = 0x10002020; +define exported symbol boot_export_symbol = 0x10002020; diff --git a/bsp/amebaz/rom_symbol_v01_iar.icf b/bsp/amebaz/rom_symbol_v01_iar.icf index f4b2a14b606a87eba4e50487b88098e447a0de9b..96d8b35cce27878f887f9a555333a3e4b7cf9ec4 100644 --- a/bsp/amebaz/rom_symbol_v01_iar.icf +++ b/bsp/amebaz/rom_symbol_v01_iar.icf @@ -1,1424 +1,1424 @@ -define exported symbol __vectors_table = 0x0; -define exported symbol Reset_Handler = 0x101; -define exported symbol NMI_Handler = 0x115; -/*define exported symbol HardFault_Handler = 0x119;*/ -define exported symbol MemManage_Handler = 0x12d; -define exported symbol BusFault_Handler = 0x131; -define exported symbol UsageFault_Handler = 0x135; -define exported symbol VSprintf = 0x201; -define exported symbol DiagPrintf = 0x4dd; -define exported symbol DiagSPrintf = 0x509; -define exported symbol DiagSnPrintf = 0x535; -define exported symbol prvDiagPrintf = 0x7ed; -define exported symbol prvDiagSPrintf = 0x821; -define exported symbol UARTIMG_Write = 0x855; -define exported symbol UARTIMG_Download = 0x901; -define exported symbol _memcmp = 0x991; -define exported symbol _memcpy = 0x9c5; -define exported symbol _memset = 0xa7d; -define exported symbol DumpForOneBytes = 0xae9; -define exported symbol CmdRomHelp = 0xc69; -define exported symbol CmdDumpWord = 0xccd; -define exported symbol CmdWriteWord = 0xd7d; -define exported symbol CmdFlash = 0xdd1; -define exported symbol CmdEfuse = 0x12c1; -define exported symbol CmdDumpByte = 0x1775; -define exported symbol CmdDumpHalfWord = 0x17c9; -define exported symbol CmdWriteByte = 0x1881; -define exported symbol SramReadWriteCpy = 0x18c1; -define exported symbol SramReadWriteTest = 0x19f9; -define exported symbol CmdSRamTest = 0x1ac9; -define exported symbol GetRomCmdNum = 0x1b59; -define exported symbol Rand = 0x1b5d; -define exported symbol Rand_Arc4 = 0x1bdd; -define exported symbol RandBytes_Get = 0x1c0d; -define exported symbol Isspace = 0x1c59; -define exported symbol Strtoul = 0x1c6d; -define exported symbol ArrayInitialize = 0x1d15; -define exported symbol GetArgc = 0x1d29; -define exported symbol GetArgv = 0x1d55; -define exported symbol UartLogCmdExecute = 0x1db1; -define exported symbol UartLogShowBackSpace = 0x1e49; -define exported symbol UartLogRecallOldCmd = 0x1e7d; -define exported symbol UartLogHistoryCmd = 0x1eb1; -define exported symbol UartLogCmdChk = 0x1f2d; -define exported symbol UartLogIrqHandle = 0x2035; -define exported symbol RtlConsolInit = 0x2101; -define exported symbol RtlConsolTaskRom = 0x218d; -define exported symbol RtlExitConsol = 0x21b9; -define exported symbol RtlConsolRom = 0x2205; -define exported symbol BKUP_Write = 0x2249; -define exported symbol BKUP_Read = 0x226d; -define exported symbol BKUP_Set = 0x228d; -define exported symbol BKUP_Clear = 0x22b9; -define exported symbol NCO32K_Init = 0x22e9; -define exported symbol EXT32K_Cmd = 0x2349; -define exported symbol NCO8M_Init = 0x2365; -define exported symbol NCO8M_Cmd = 0x23bd; -define exported symbol ISO_Set = 0x23d9; -define exported symbol PLL0_Set = 0x23f1; -define exported symbol PLL1_Set = 0x2409; -define exported symbol PLL2_Set = 0x2421; -define exported symbol PLL3_Set = 0x2439; -define exported symbol XTAL0_Set = 0x2451; -define exported symbol XTAL1_Set = 0x2469; -define exported symbol XTAL2_Set = 0x2481; -define exported symbol XTAL_ClkGet = 0x2499; -define exported symbol CPU_ClkSet = 0x24b1; -define exported symbol CPU_ClkGet = 0x24c5; -define exported symbol OSC32K_Calibration = 0x24e5; -define exported symbol OSC32K_Cmd = 0x25f9; -define exported symbol OSC8M_Get = 0x2631; -define exported symbol rtl_cryptoEngine_SrcDesc_Show = 0x2641; -define exported symbol rtl_cryptoEngine_info = 0x27f1; -define exported symbol rtl_cryptoEngine_init = 0x2949; -define exported symbol rtl_crypto_md5_init = 0x2975; -define exported symbol rtl_crypto_md5_process = 0x29b1; -define exported symbol rtl_crypto_md5 = 0x2a09; -define exported symbol rtl_crypto_sha1_init = 0x2a2d; -define exported symbol rtl_crypto_sha1_process = 0x2a69; -define exported symbol rtl_crypto_sha1 = 0x2a9d; -define exported symbol rtl_crypto_sha2_init = 0x2ac1; -define exported symbol rtl_crypto_sha2_process = 0x2b15; -define exported symbol rtl_crypto_sha2 = 0x2b4d; -define exported symbol rtl_crypto_hmac_md5_init = 0x2b71; -define exported symbol rtl_crypto_hmac_md5_process = 0x2bd1; -define exported symbol rtl_crypto_hmac_md5 = 0x2c0d; -define exported symbol rtl_crypto_hmac_sha1_init = 0x2c31; -define exported symbol rtl_crypto_hmac_sha1_process = 0x2c91; -define exported symbol rtl_crypto_hmac_sha1 = 0x2cc9; -define exported symbol rtl_crypto_hmac_sha2_init = 0x2ced; -define exported symbol rtl_crypto_hmac_sha2_process = 0x2d65; -define exported symbol rtl_crypto_hmac_sha2 = 0x2da1; -define exported symbol rtl_crypto_aes_cbc_init = 0x2dc5; -define exported symbol rtl_crypto_aes_cbc_encrypt = 0x2dfd; -define exported symbol rtl_crypto_aes_cbc_decrypt = 0x2e45; -define exported symbol rtl_crypto_aes_ecb_init = 0x2e8d; -define exported symbol rtl_crypto_aes_ecb_encrypt = 0x2ec5; -define exported symbol rtl_crypto_aes_ecb_decrypt = 0x2ef5; -define exported symbol rtl_crypto_aes_ctr_init = 0x2f25; -define exported symbol rtl_crypto_aes_ctr_encrypt = 0x2f5d; -define exported symbol rtl_crypto_aes_ctr_decrypt = 0x2f99; -define exported symbol rtl_crypto_3des_cbc_init = 0x2fd5; -define exported symbol rtl_crypto_3des_cbc_encrypt = 0x300d; -define exported symbol rtl_crypto_3des_cbc_decrypt = 0x3055; -define exported symbol rtl_crypto_3des_ecb_init = 0x309d; -define exported symbol rtl_crypto_3des_ecb_encrypt = 0x30d5; -define exported symbol rtl_crypto_3des_ecb_decrypt = 0x311d; -define exported symbol rtl_crypto_des_cbc_init = 0x3165; -define exported symbol rtl_crypto_des_cbc_encrypt = 0x319d; -define exported symbol rtl_crypto_des_cbc_decrypt = 0x31f5; -define exported symbol rtl_crypto_des_ecb_init = 0x324d; -define exported symbol rtl_crypto_des_ecb_encrypt = 0x3285; -define exported symbol rtl_crypto_des_ecb_decrypt = 0x32dd; -define exported symbol SYSTIMER_Init = 0x3335; -define exported symbol SYSTIMER_TickGet = 0x33a1; -define exported symbol SYSTIMER_GetPassTime = 0x33c1; -define exported symbol DelayNop = 0x3401; -define exported symbol DelayUs = 0x3411; -define exported symbol DelayMs = 0x346d; -define exported symbol USOC_DongleSpecialCmd = 0x3481; -define exported symbol USOC_DongleCmd = 0x35d9; -define exported symbol USOC_DongleIsr = 0x35f9; -define exported symbol USOC_SIE_INTConfig = 0x3621; -define exported symbol USOC_SIE_INTClear = 0x3639; -define exported symbol USOC_PHY_Write = 0x3645; -define exported symbol USOC_PHY_Read = 0x3679; -define exported symbol USOC_PHY_Autoload = 0x36c1; -define exported symbol USOC_DongleInit = 0x37a5; -define exported symbol EFUSE_USER_Read = 0x386d; -define exported symbol EFUSE_USER1_Read = 0x3971; -define exported symbol EFUSE_USER2_Read = 0x397d; -define exported symbol EFUSE_USER3_Read = 0x3989; -define exported symbol EFUSE_RemainLength = 0x3995; -define exported symbol EFUSE_USER_Write = 0x3a21; -define exported symbol EFUSE_USER1_Write = 0x3bb1; -define exported symbol EFUSE_USER2_Write = 0x3bc1; -define exported symbol EFUSE_USER3_Write = 0x3bd1; -define exported symbol EFUSE_OTP_Read1B = 0x3be1; -define exported symbol EFUSE_OTP_Write1B = 0x3c01; -define exported symbol EFUSE_OTP_Read32B = 0x3c21; -define exported symbol EFUSE_OTP_Write32B = 0x3c4d; -define exported symbol EFUSE_RDP_EN = 0x3cad; -define exported symbol EFUSE_RDP_KEY = 0x3ccd; -define exported symbol EFUSE_OTF_KEY = 0x3cf9; -define exported symbol EFUSE_JTAG_OFF = 0x3d25; -define exported symbol PAD_DrvStrength = 0x3d45; -define exported symbol PAD_PullCtrl = 0x3d75; -define exported symbol Pinmux_Config = 0x3dc5; -define exported symbol Pinmux_ConfigGet = 0x3dfd; -define exported symbol Pinmux_Deinit = 0x3e19; -define exported symbol PINMUX_UART0_Ctrl = 0x3e39; -define exported symbol PINMUX_UART1_Ctrl = 0x3e81; -define exported symbol PINMUX_UARTLOG_Ctrl = 0x3ea9; -define exported symbol PINMUX_SPI0_Ctrl = 0x3ef9; -define exported symbol PINMUX_SPI1_Ctrl = 0x3f8d; -define exported symbol PINMUX_SPIF_Ctrl = 0x400d; -define exported symbol PINMUX_I2C0_Ctrl = 0x406d; -define exported symbol PINMUX_I2C1_Ctrl = 0x40e1; -define exported symbol PINMUX_SDIOD_Ctrl = 0x4151; -define exported symbol PINMUX_I2S0_Ctrl = 0x41e5; -define exported symbol PINMUX_SWD_Ctrl = 0x4265; -define exported symbol PINMUX_SWD_OFF = 0x42b5; -define exported symbol PINMUX_SWD_REG = 0x42d9; -define exported symbol PINMUX_Ctrl = 0x42fd; -define exported symbol SOCPS_BackupCPUClk = 0x4391; -define exported symbol SOCPS_RestoreCPUClk = 0x43b1; -define exported symbol SOCPS_BootFromPS = 0x43d1; -define exported symbol SOCPS_TrapPin = 0x43f1; -define exported symbol SOCPS_ANACKSel = 0x4411; -define exported symbol SOCPS_CLKCal = 0x442d; -define exported symbol SOCPS_SetWakeEvent = 0x4485; -define exported symbol SOCPS_ClearWakeEvent = 0x449d; -define exported symbol SOCPS_WakePinsCtrl = 0x44a9; -define exported symbol SOCPS_WakePinCtrl = 0x44d9; -define exported symbol SOCPS_WakePinClear = 0x4529; -define exported symbol SOCPS_GetANATimerParam = 0x4539; -define exported symbol SOCPS_SetANATimer = 0x4575; -define exported symbol SOCPS_SetReguWakepin = 0x45dd; -define exported symbol SOCPS_SetReguTimer = 0x4605; -define exported symbol SOCPS_PWROption = 0x46d9; -define exported symbol SOCPS_PWROptionExt = 0x46e5; -define exported symbol SOCPS_PWRMode = 0x46f9; -define exported symbol SOCPS_SNZMode = 0x4721; -define exported symbol SOCPS_DeepStandby = 0x473d; -define exported symbol SOCPS_DeepSleep = 0x4791; -define exported symbol SDIO_StructInit = 0x47d5; -define exported symbol SDIO_Init = 0x47f1; -define exported symbol SDIO_INTClear = 0x486d; -define exported symbol SDIO_INTConfig = 0x487d; -define exported symbol SDIO_RPWM1_Get = 0x4895; -define exported symbol SDIO_RPWM2_Get = 0x48a1; -define exported symbol SDIO_CPWM1_Set = 0x48ad; -define exported symbol SDIO_CPWM2_Set = 0x48c1; -define exported symbol SDIO_RXBD_RPTR_Get = 0x48dd; -define exported symbol SDIO_RXBD_WPTR_Set = 0x48e9; -define exported symbol SDIO_TXBD_WPTR_Get = 0x48f5; -define exported symbol SDIO_TXBD_RPTR_Set = 0x4901; -define exported symbol SDIO_DMA_Reset = 0x490d; -define exported symbol BOOT_ROM_Simulation = 0x4919; -define exported symbol USOC_BOOT_TXBD_Proc = 0x491d; -define exported symbol USOC_BOOT_Init = 0x4a3d; -define exported symbol USB_Boot_ROM = 0x4aa9; -define exported symbol USOC_CH_Cmd = 0x4b59; -define exported symbol USOC_Cmd = 0x4bb1; -define exported symbol USOC_PHY_Cmd = 0x4bf5; -define exported symbol USOC_MODE_Cfg = 0x4c09; -define exported symbol USOC_TXBD_SWIDX_Cfg = 0x4c25; -define exported symbol USOC_TXBD_SWIDX_Get = 0x4c2d; -define exported symbol USOC_TXBD_HWIDX_Get = 0x4c35; -define exported symbol USOC_RXBD_HWIDX_Get = 0x4c3d; -define exported symbol USOC_RXBD_SWIDX_Cfg = 0x4c45; -define exported symbol USOC_RXBD_SWIDX_Get = 0x4c4d; -define exported symbol USOC_StructInit = 0x4c55; -define exported symbol USOC_Init = 0x4c85; -define exported symbol USOC_SW_RST = 0x4d7d; -define exported symbol USOC_INTCfg = 0x4d91; -define exported symbol USOC_INTClr = 0x4d95; -define exported symbol USOC_INTGet = 0x4d9d; -define exported symbol USOC_MIT_Cfg = 0x4da1; -define exported symbol USOC_TXSTUCK_Cfg = 0x4dc5; -define exported symbol USOC_RXSTUCK_Cfg = 0x4de9; -define exported symbol USOC_POWER_On = 0x4e0d; -define exported symbol ADC_RXGDMA_Init = 0x4e9d; -define exported symbol ADC_SetAudio = 0x4f45; -define exported symbol ADC_SetAnalog = 0x4f61; -define exported symbol ADC_Cmd = 0x4fbd; -define exported symbol ADC_INTConfig = 0x5031; -define exported symbol ADC_SetOneShot = 0x5049; -define exported symbol ADC_SetComp = 0x50fd; -define exported symbol ADC_INTClear = 0x517d; -define exported symbol ADC_INTClearPendingBits = 0x5189; -define exported symbol ADC_GetISR = 0x5195; -define exported symbol ADC_Read = 0x51a1; -define exported symbol ADC_ReceiveBuf = 0x51ad; -define exported symbol ADC_InitStruct = 0x5205; -define exported symbol ADC_Init = 0x524d; -define exported symbol BOOT_ROM_ShowBuildInfo = 0x52ed; -define exported symbol BOOT_ROM_OTFCheck = 0x5335; -define exported symbol BOOT_ROM_InitFlash = 0x5345; -define exported symbol BOOT_ROM_FromFlash = 0x5405; -define exported symbol BOOT_ROM_InitUsb = 0x5511; -define exported symbol BOOT_ROM_Process = 0x553d; -define exported symbol BOOT_ROM_InitDebugFlg = 0x5605; -define exported symbol HalResetVsr = 0x5639; -define exported symbol Cache_Enable = 0x5811; -define exported symbol Cache_Flush = 0x5831; -define exported symbol Cache_Debug = 0x5851; -define exported symbol CRYPTO_AlignToBe32 = 0x58bd; -define exported symbol CRYPTO_MemDump = 0x58d5; -define exported symbol CRYPTO_GetAESKey = 0x599d; -define exported symbol CRYPTO_SetAESKey = 0x5cb5; -define exported symbol CRYPTO_SetSecurityMode = 0x5d29; -define exported symbol CRYPTO_Init = 0x5f5d; -define exported symbol CRYPTO_DeInit = 0x60b9; -define exported symbol CRYPTO_Reset = 0x6101; -define exported symbol CRYPTO_Process = 0x6129; -define exported symbol CRYPTO_CipherInit = 0x6a11; -define exported symbol CRYPTO_CipherEncrypt = 0x6a35; -define exported symbol CRYPTO_CipherDecrypt = 0x6a61; -define exported symbol CRYPTO_SetCheckSumEn = 0x6a95; -define exported symbol CRYPTO_GetCheckSumData = 0x6ab1; -define exported symbol LOGUART_StructInit = 0x6abd; -define exported symbol LOGUART_Init = 0x6ad5; -define exported symbol LOGUART_PutChar = 0x6b15; -define exported symbol LOGUART_GetChar = 0x6b49; -define exported symbol LOGUART_GetIMR = 0x6b65; -define exported symbol LOGUART_SetIMR = 0x6b71; -define exported symbol LOGUART_WaitBusy = 0x6b7d; -define exported symbol DIAG_UartInit = 0x6b9d; -define exported symbol DIAG_UartReInit = 0x6c25; -define exported symbol EFUSE_PowerSwitchROM = 0x6c49; -define exported symbol EFUSE_OneByteReadROM = 0x6d65; -define exported symbol EFUSE_OneByteWriteROM = 0x6e0d; -define exported symbol EFUSE_PG_Packet = 0x6e29; -define exported symbol EFUSE_LogicalMap_Read = 0x7091; -define exported symbol EFUSE_LogicalMap_Write = 0x71f5; -define exported symbol FLASH_SetSpiMode = 0x73dd; -define exported symbol FLASH_RxCmd = 0x7465; -define exported symbol FLASH_WaitBusy = 0x74cd; -define exported symbol FLASH_RxData = 0x754d; -define exported symbol FLASH_TxCmd = 0x75cd; -define exported symbol FLASH_WriteEn = 0x763d; -define exported symbol FLASH_TxData12B = 0x7661; -define exported symbol FLASH_SetStatus = 0x7735; -define exported symbol FLASH_Erase = 0x7755; -define exported symbol FLASH_DeepPowerDown = 0x77f5; -define exported symbol FLASH_SetStatusBits = 0x784d; -define exported symbol FLASH_Calibration = 0x791d; -define exported symbol FLASH_StructInit_Micron = 0x7a65; -define exported symbol FLASH_StructInit_MXIC = 0x7af5; -define exported symbol FLASH_StructInit_GD = 0x7b81; -define exported symbol FLASH_StructInit = 0x7c11; -define exported symbol FLASH_Init = 0x7ca1; -define exported symbol FLASH_ClockDiv = 0x7d15; -define exported symbol FLASH_CalibrationInit = 0x7d99; -define exported symbol FLASH_Calibration500MPSCmd = 0x7db1; -define exported symbol FLASH_CalibrationPhase = 0x7dcd; -define exported symbol FLASH_CalibrationPhaseIdx = 0x7e59; -define exported symbol FLASH_CalibrationNewCmd = 0x7e6d; -define exported symbol FLASH_CalibrationNew = 0x7ea9; -define exported symbol GDMA_StructInit = 0x80dd; -define exported symbol GDMA_SetLLP = 0x80f9; -define exported symbol GDMA_ClearINTPendingBit = 0x8191; -define exported symbol GDMA_ClearINT = 0x81d5; -define exported symbol GDMA_INTConfig = 0x8211; -define exported symbol GDMA_Cmd = 0x8259; -define exported symbol GDMA_Init = 0x828d; -define exported symbol GDMA_ChCleanAutoReload = 0x83c1; -define exported symbol GDMA_SetSrcAddr = 0x83f9; -define exported symbol GDMA_GetSrcAddr = 0x8411; -define exported symbol GDMA_GetDstAddr = 0x8429; -define exported symbol GDMA_SetDstAddr = 0x843d; -define exported symbol GDMA_SetBlkSize = 0x8459; -define exported symbol GDMA_GetBlkSize = 0x8489; -define exported symbol GDMA_ChnlRegister = 0x84a1; -define exported symbol GDMA_ChnlUnRegister = 0x8529; -define exported symbol GDMA_ChnlAlloc = 0x8591; -define exported symbol GDMA_ChnlFree = 0x8615; -define exported symbol GPIO_INTMode = 0x864d; -define exported symbol GPIO_INTConfig = 0x86e5; -define exported symbol GPIO_INTHandler = 0x8725; -define exported symbol GPIO_Direction = 0x8771; -define exported symbol GPIO_Init = 0x87a1; -define exported symbol GPIO_DeInit = 0x886d; -define exported symbol GPIO_ReadDataBit = 0x88c9; -define exported symbol GPIO_WriteBit = 0x88ed; -define exported symbol GPIO_PortDirection = 0x891d; -define exported symbol GPIO_PortRead = 0x893d; -define exported symbol GPIO_PortWrite = 0x894d; -define exported symbol GPIO_UserRegIrq = 0x8969; -define exported symbol I2C_StructInit = 0x899d; -define exported symbol I2C_SetSpeed = 0x89e5; -define exported symbol I2C_SetSlaveAddress = 0x8b3d; -define exported symbol I2C_CheckFlagState = 0x8b79; -define exported symbol I2C_INTConfig = 0x8bad; -define exported symbol I2C_ClearINT = 0x8be5; -define exported symbol I2C_ClearAllINT = 0x8c85; -define exported symbol I2C_Init = 0x8cad; -define exported symbol I2C_GetRawINT = 0x8dc9; -define exported symbol I2C_GetINT = 0x8df1; -define exported symbol I2C_MasterSendNullData = 0x8e19; -define exported symbol I2C_MasterSend = 0x8e65; -define exported symbol I2C_SlaveSend = 0x8ead; -define exported symbol I2C_ReceiveData = 0x8ed9; -define exported symbol I2C_MasterWrite = 0x8f05; -define exported symbol I2C_MasterReadDW = 0x8f89; -define exported symbol I2C_MasterRead = 0x9019; -define exported symbol I2C_SlaveWrite = 0x9089; -define exported symbol I2C_SlaveRead = 0x90f1; -define exported symbol I2C_MasterRepeatRead = 0x9141; -define exported symbol I2C_Cmd = 0x91c1; -define exported symbol I2C_PinMuxInit = 0x91fd; -define exported symbol I2C_PinMuxDeInit = 0x9255; -define exported symbol I2C_DMAControl = 0x92ad; -define exported symbol I2C_DmaMode1Config = 0x92e9; -define exported symbol I2C_DmaMode2Config = 0x9331; -define exported symbol I2C_TXGDMA_Init = 0x9375; -define exported symbol I2C_RXGDMA_Init = 0x9459; -define exported symbol I2C_Sleep_Cmd = 0x9521; -define exported symbol I2C_WakeUp = 0x95a1; -define exported symbol I2S_StructInit = 0x95e9; -define exported symbol I2S_Cmd = 0x9611; -define exported symbol I2S_TxDmaCmd = 0x962d; -define exported symbol I2S_RxDmaCmd = 0x9641; -define exported symbol I2S_INTConfig = 0x9655; -define exported symbol I2S_INTClear = 0x965d; -define exported symbol I2S_INTClearAll = 0x9665; -define exported symbol I2S_Init = 0x9671; -define exported symbol I2S_ISRGet = 0x97a9; -define exported symbol I2S_SetRate = 0x97b5; -define exported symbol I2S_SetWordLen = 0x9811; -define exported symbol I2S_SetChNum = 0x9839; -define exported symbol I2S_SetPageNum = 0x9861; -define exported symbol I2S_SetPageSize = 0x9895; -define exported symbol I2S_GetPageSize = 0x98a9; -define exported symbol I2S_SetDirection = 0x98b5; -define exported symbol I2S_SetDMABuf = 0x98dd; -define exported symbol I2S_TxPageBusy = 0x9905; -define exported symbol I2S_GetTxPage = 0x9911; -define exported symbol I2S_GetRxPage = 0x991d; -define exported symbol I2S_SetTxPageAddr = 0x9929; -define exported symbol I2S_GetTxPageAddr = 0x9939; -define exported symbol I2S_SetRxPageAddr = 0x9949; -define exported symbol I2S_GetRxPageAddr = 0x9959; -define exported symbol I2S_TxPageDMA_EN = 0x9969; -define exported symbol I2S_RxPageDMA_EN = 0x998d; -define exported symbol io_assert_failed = 0x99d9; -define exported symbol OTF_init = 0x99fd; -define exported symbol OTF_Cmd = 0x9a79; -define exported symbol OTF_Mask = 0x9a8d; -define exported symbol KEY_Request = 0x9add; -define exported symbol RDP_EN_Request = 0x9b21; -define exported symbol RCC_PeriphClockCmd = 0x9b65; -define exported symbol FUNC_HCI_COM = 0x9c95; -define exported symbol RTC_ByteToBcd2 = 0x9cad; -define exported symbol RTC_Bcd2ToByte = 0x9cc9; -define exported symbol RTC_ClokSource = 0x9cdd; -define exported symbol RTC_EnterInitMode = 0x9d19; -define exported symbol RTC_ExitInitMode = 0x9d51; -define exported symbol RTC_WaitForSynchro = 0x9d61; -define exported symbol RTC_BypassShadowCmd = 0x9da9; -define exported symbol RTC_StructInit = 0x9dd9; -define exported symbol RTC_Init = 0x9de5; -define exported symbol RTC_TimeStructInit = 0x9e7d; -define exported symbol RTC_SetTime = 0x9e8d; -define exported symbol RTC_GetTime = 0x9ff9; -define exported symbol RTC_SetAlarm = 0xa051; -define exported symbol RTC_AlarmStructInit = 0xa211; -define exported symbol RTC_GetAlarm = 0xa231; -define exported symbol RTC_AlarmCmd = 0xa2a1; -define exported symbol RTC_AlarmClear = 0xa2f5; -define exported symbol RTC_DayLightSavingConfig = 0xa305; -define exported symbol RTC_GetStoreOperation = 0xa355; -define exported symbol RTC_OutputConfig = 0xa365; -define exported symbol RTC_SmoothCalibConfig = 0xa39d; -define exported symbol SDIO_IsTimeout = 0xa459; -define exported symbol SDIOB_Init = 0xa481; -define exported symbol SDIOB_INTConfig = 0xa575; -define exported symbol SDIOB_DeInit = 0xa591; -define exported symbol SDIOB_H2C_WriteMem = 0xa5d9; -define exported symbol SDIOB_H2C_SetMem = 0xa605; -define exported symbol SDIOB_H2C_DataHandle = 0xa631; -define exported symbol SDIOB_H2C_DataReady = 0xa73d; -define exported symbol SDIOB_IRQ_Handler_BH = 0xa80d; -define exported symbol SDIOB_H2C_Task = 0xa8c9; -define exported symbol SDIO_Boot_Up = 0xa8e5; -define exported symbol SPI_DmaInit = 0xa91d; -define exported symbol SPI_DataHandle = 0xa9d1; -define exported symbol SPI_Boot_DmaRxIrqHandle = 0xaa01; -define exported symbol SPI_Boot_ROM = 0xaa5d; -define exported symbol SSI_StructInit = 0xabbd; -define exported symbol SSI_Cmd = 0xabf5; -define exported symbol SSI_INTConfig = 0xac09; -define exported symbol SSI_SetSclkPolarity = 0xac19; -define exported symbol SSI_SetSclkPhase = 0xac3d; -define exported symbol SSI_SetDataFrameSize = 0xac61; -define exported symbol SSI_SetReadLen = 0xac81; -define exported symbol SSI_SetBaudDiv = 0xacb1; -define exported symbol SSI_SetBaud = 0xaccd; -define exported symbol SSI_SetDmaEnable = 0xad2d; -define exported symbol SSI_SetDmaLevel = 0xad41; -define exported symbol SSI_SetIsrClean = 0xad49; -define exported symbol SSI_WriteData = 0xad65; -define exported symbol SSI_SetRxFifoLevel = 0xad6d; -define exported symbol SSI_SetTxFifoLevel = 0xad71; -define exported symbol SSI_ReadData = 0xad75; -define exported symbol SSI_GetRxCount = 0xad79; -define exported symbol SSI_GetTxCount = 0xad81; -define exported symbol SSI_GetStatus = 0xad89; -define exported symbol SSI_Writeable = 0xad8d; -define exported symbol SSI_Readable = 0xad9d; -define exported symbol SSI_GetDataFrameSize = 0xadad; -define exported symbol SSI_TXGDMA_Init = 0xadb9; -define exported symbol SSI_RXGDMA_Init = 0xaef9; -define exported symbol SSI_ReceiveData = 0xb021; -define exported symbol SSI_SendData = 0xb0b9; -define exported symbol SSI_Busy = 0xb165; -define exported symbol SSI_SetSlaveEnable = 0xb175; -define exported symbol SSI_Init = 0xb1ad; -define exported symbol SSI_GetIsr = 0xb235; -define exported symbol SSI_GetRawIsr = 0xb239; -define exported symbol SSI_GetSlaveEnable = 0xb23d; -define exported symbol SSI_PinmuxInit = 0xb241; -define exported symbol SSI_PinmuxDeInit = 0xb2a9; -define exported symbol SYSCFG0_Get = 0xb311; -define exported symbol SYSCFG0_CUTVersion = 0xb31d; -define exported symbol SYSCFG0_BDOption = 0xb32d; -define exported symbol SYSCFG1_Get = 0xb33d; -define exported symbol SYSCFG1_AutoLoadDone = 0xb349; -define exported symbol SYSCFG1_TRP_LDOMode = 0xb359; -define exported symbol SYSCFG1_TRP_UARTImage = 0xb369; -define exported symbol SYSCFG1_TRP_ICFG = 0xb37d; -define exported symbol SYSCFG2_Get = 0xb389; -define exported symbol SYSCFG2_ROMINFO_Get = 0xb395; -define exported symbol SYSCFG2_ROMINFO_Set = 0xb3a1; -define exported symbol RTIM_TimeBaseStructInit = 0xb3b5; -define exported symbol RTIM_Cmd = 0xb3cd; -define exported symbol RTIM_GetCount = 0xb42d; -define exported symbol RTIM_UpdateDisableConfig = 0xb475; -define exported symbol RTIM_ARRPreloadConfig = 0xb4c5; -define exported symbol RTIM_UpdateRequestConfig = 0xb515; -define exported symbol RTIM_PrescalerConfig = 0xb575; -define exported symbol RTIM_GenerateEvent = 0xb5a1; -define exported symbol RTIM_ChangePeriod = 0xb5f9; -define exported symbol RTIM_Reset = 0xb64d; -define exported symbol RTIM_CCStructInit = 0xb68d; -define exported symbol RTIM_CCxInit = 0xb6a1; -define exported symbol RTIM_CCRxMode = 0xb749; -define exported symbol RTIM_CCRxSet = 0xb785; -define exported symbol RTIM_CCRxGet = 0xb7dd; -define exported symbol RTIM_OCxPreloadConfig = 0xb80d; -define exported symbol RTIM_CCxPolarityConfig = 0xb85d; -define exported symbol RTIM_CCxCmd = 0xb8ad; -define exported symbol RTIM_SetOnePulseOutputMode = 0xb901; -define exported symbol RTIM_DMACmd = 0xb959; -define exported symbol RTIM_TXGDMA_Init = 0xb9a9; -define exported symbol RTIM_RXGDMA_Init = 0xba5d; -define exported symbol RTIM_INTConfig = 0xbb3d; -define exported symbol RTIM_INTClear = 0xbba9; -define exported symbol RTIM_TimeBaseInit = 0xbbed; -define exported symbol RTIM_DeInit = 0xbced; -define exported symbol RTIM_INTClearPendingBit = 0xbd41; -define exported symbol RTIM_GetFlagStatus = 0xbd81; -define exported symbol RTIM_GetINTStatus = 0xbded; -define exported symbol UART_DeInit = 0xbe61; -define exported symbol UART_StructInit = 0xbe69; -define exported symbol UART_BaudParaGet = 0xbe81; -define exported symbol UART_BaudParaGetFull = 0xbec9; -define exported symbol UART_SetBaud = 0xbf01; -define exported symbol UART_SetBaudExt = 0xbf71; -define exported symbol UART_SetRxLevel = 0xbfc1; -define exported symbol UART_RxCmd = 0xbfe9; -define exported symbol UART_Writable = 0xbffd; -define exported symbol UART_Readable = 0xc005; -define exported symbol UART_CharPut = 0xc00d; -define exported symbol UART_CharGet = 0xc011; -define exported symbol UART_ReceiveData = 0xc019; -define exported symbol UART_SendData = 0xc041; -define exported symbol UART_ReceiveDataTO = 0xc069; -define exported symbol UART_SendDataTO = 0xc0a9; -define exported symbol UART_RxByteCntClear = 0xc0e9; -define exported symbol UART_RxByteCntGet = 0xc0f5; -define exported symbol UART_BreakCtl = 0xc0fd; -define exported symbol UART_ClearRxFifo = 0xc111; -define exported symbol UART_Init = 0xc135; -define exported symbol UART_ClearTxFifo = 0xc1d1; -define exported symbol UART_INTConfig = 0xc1dd; -define exported symbol UART_IntStatus = 0xc1ed; -define exported symbol UART_ModemStatusGet = 0xc1f1; -define exported symbol UART_LineStatusGet = 0xc1f5; -define exported symbol UART_WaitBusy = 0xc1f9; -define exported symbol UART_PinMuxInit = 0xc221; -define exported symbol UART_PinMuxDeinit = 0xc289; -define exported symbol UART_TXDMAConfig = 0xc2f1; -define exported symbol UART_RXDMAConfig = 0xc301; -define exported symbol UART_TXDMACmd = 0xc315; -define exported symbol UART_RXDMACmd = 0xc329; -define exported symbol UART_TXGDMA_Init = 0xc33d; -define exported symbol UART_RXGDMA_Init = 0xc425; -define exported symbol UART_LPRxStructInit = 0xc501; -define exported symbol UART_LPRxInit = 0xc50d; -define exported symbol UART_LPRxBaudSet = 0xc575; -define exported symbol UART_LPRxMonitorCmd = 0xc5f1; -define exported symbol UART_LPRxpathSet = 0xc62d; -define exported symbol UART_LPRxIPClockSet = 0xc641; -define exported symbol UART_LPRxCmd = 0xc6b1; -define exported symbol UART_LPRxMonBaudCtrlRegGet = 0xc6c5; -define exported symbol UART_LPRxMonitorSatusGet = 0xc6c9; -define exported symbol UART_IrDAStructInit = 0xc6cd; -define exported symbol UART_IrDAInit = 0xc6e5; -define exported symbol UART_IrDACmd = 0xc7bd; -define exported symbol INT_SysOn = 0xc7d1; -define exported symbol INT_Wdg = 0xc811; -define exported symbol INT_Timer0 = 0xc855; -define exported symbol INT_Timer1 = 0xc899; -define exported symbol INT_Timer2 = 0xc8dd; -define exported symbol INT_Timer3 = 0xc921; -define exported symbol INT_SPI0 = 0xc965; -define exported symbol INT_GPIO = 0xc9a9; -define exported symbol INT_Uart0 = 0xc9ed; -define exported symbol INT_SPIFlash = 0xca31; -define exported symbol INT_Uart1 = 0xca75; -define exported symbol INT_Timer4 = 0xcab9; -define exported symbol INT_I2S0 = 0xcafd; -define exported symbol INT_Timer5 = 0xcb41; -define exported symbol INT_WlDma = 0xcb85; -define exported symbol INT_WlProtocol = 0xcbc9; -define exported symbol INT_IPSEC = 0xcc0d; -define exported symbol INT_SPI1 = 0xcc51; -define exported symbol INT_Peripheral = 0xcc95; -define exported symbol INT_Gdma0Ch0 = 0xccd9; -define exported symbol INT_Gdma0Ch1 = 0xcd1d; -define exported symbol INT_Gdma0Ch2 = 0xcd61; -define exported symbol INT_Gdma0Ch3 = 0xcda5; -define exported symbol INT_Gdma0Ch4 = 0xcde9; -define exported symbol INT_Gdma0Ch5 = 0xce2d; -define exported symbol INT_I2C0 = 0xce71; -define exported symbol INT_I2C1 = 0xceb5; -define exported symbol INT_Uartlog = 0xcef9; -define exported symbol INT_ADC = 0xcf3d; -define exported symbol INT_RDP = 0xcf81; -define exported symbol INT_RTC = 0xcfc5; -define exported symbol INT_Gdma1Ch0 = 0xd009; -define exported symbol INT_Gdma1Ch1 = 0xd051; -define exported symbol INT_Gdma1Ch2 = 0xd099; -define exported symbol INT_Gdma1Ch3 = 0xd0e1; -define exported symbol INT_Gdma1Ch4 = 0xd129; -define exported symbol INT_Gdma1Ch5 = 0xd171; -define exported symbol INT_USB = 0xd1b9; -define exported symbol INT_RXI300 = 0xd201; -define exported symbol INT_USB_SIE = 0xd249; -define exported symbol INT_SdioD = 0xd291; -define exported symbol INT_NMI = 0xd2d1; -define exported symbol INT_HardFault = 0xd305; -define exported symbol INT_MemManage = 0xd4b5; -define exported symbol INT_BusFault = 0xd4d5; -define exported symbol INT_UsageFault = 0xd4f5; -define exported symbol VECTOR_TableInit = 0xd515; -define exported symbol VECTOR_TableInitForOS = 0xd6c5; -define exported symbol VECTOR_IrqRegister = 0xd6d5; -define exported symbol VECTOR_IrqUnRegister = 0xd6f9; -define exported symbol VECTOR_IrqEn = 0xd715; -define exported symbol VECTOR_IrqDis = 0xd765; -define exported symbol WDG_Scalar = 0xd7a1; -define exported symbol WDG_Init = 0xd7e1; -define exported symbol WDG_IrqClear = 0xd7fd; -define exported symbol WDG_IrqInit = 0xd80d; -define exported symbol WDG_Cmd = 0xd83d; -define exported symbol WDG_Refresh = 0xd85d; -define exported symbol _strncpy = 0xd86d; -define exported symbol _strcpy = 0xd889; -define exported symbol prvStrCpy = 0xd899; -define exported symbol _strlen = 0xd8b1; -define exported symbol _strnlen = 0xd8c9; -define exported symbol prvStrLen = 0xd8fd; -define exported symbol _strcmp = 0xd919; -define exported symbol _strncmp = 0xd939; -define exported symbol prvStrCmp = 0xd985; -define exported symbol StrUpr = 0xd9b5; -define exported symbol prvAtoi = 0xd9d1; -define exported symbol prvStrtok = 0xda29; -define exported symbol prvStrStr = 0xda81; -define exported symbol _strsep = 0xdab9; -define exported symbol skip_spaces = 0xdaf5; -define exported symbol skip_atoi = 0xdb11; -define exported symbol _parse_integer_fixup_radix = 0xdb49; -define exported symbol _parse_integer = 0xdb9d; -define exported symbol simple_strtoull = 0xdc01; -define exported symbol simple_strtoll = 0xdc21; -define exported symbol simple_strtoul = 0xdc41; -define exported symbol simple_strtol = 0xdc49; -define exported symbol _vsscanf = 0xdc61; -define exported symbol _sscanf = 0xe1c9; -define exported symbol div_u64 = 0xe1e5; -define exported symbol div_s64 = 0xe1ed; -define exported symbol div_u64_rem = 0xe1f5; -define exported symbol div_s64_rem = 0xe205; -define exported symbol _strpbrk = 0xe215; -define exported symbol _strchr = 0xe241; -define exported symbol COMMPORT_GET_T = 0xe259; -define exported symbol COMMPORT_CLEAN_RX = 0xe289; -define exported symbol xModemDebugInit = 0xe2a5; -define exported symbol xModemDebug = 0xe2dd; -define exported symbol xModemInquiry = 0xe315; -define exported symbol xModemGetFirst = 0xe339; -define exported symbol xModemGetOthers = 0xe45d; -define exported symbol xModemRxFrame = 0xe691; -define exported symbol xModemHandshake = 0xe6d5; -define exported symbol xModemRxBuffer = 0xe945; -define exported symbol xmodem_log_close = 0xe9f5; -define exported symbol xmodem_log_open = 0xea01; -define exported symbol xmodem_uart_init = 0xea39; -define exported symbol xmodem_uart_deinit = 0xeb25; -define exported symbol xmodem_uart_port_init = 0xeb35; -define exported symbol xmodem_uart_port_deinit = 0xeb99; -define exported symbol xmodem_uart_readable = 0xebdd; -define exported symbol xmodem_uart_writable = 0xebf5; -define exported symbol xmodem_uart_getc = 0xec0d; -define exported symbol xmodem_uart_putc = 0xec35; -define exported symbol xmodem_uart_putdata = 0xec49; -define exported symbol aes_set_key = 0xec65; -define exported symbol aes_encrypt = 0xf021; -define exported symbol aes_decrypt = 0x10171; -define exported symbol AES_WRAP = 0x112b1; -define exported symbol AES_UnWRAP = 0x113fd; -define exported symbol crc32_get = 0x11549; -define exported symbol arc4_byte = 0x1157d; -define exported symbol rt_arc4_init = 0x115a5; -define exported symbol rt_arc4_crypt = 0x115e9; -define exported symbol rt_md5_init = 0x11df5; -define exported symbol rt_md5_append = 0x11e25; -define exported symbol rt_md5_final = 0x11ec9; -define exported symbol rt_md5_hmac = 0x11f21; -define exported symbol RC4 = 0x12061; -define exported symbol RC4_set_key = 0x1238d; -define exported symbol ROM_WIFI_ReadPowerValue = 0x1246d; -define exported symbol ROM_WIFI_EfuseParseTxPowerInfo = 0x1251d; -define exported symbol ROM_WIFI_8051Reset = 0x125c5; -define exported symbol ROM_WIFI_FWDownloadEnable = 0x125dd; -define exported symbol ROM_WIFI_BlockWrite = 0x12619; -define exported symbol ROM_WIFI_PageWrite = 0x12661; -define exported symbol ROM_WIFI_FillDummy = 0x12685; -define exported symbol ROM_WIFI_WriteFW = 0x126b1; -define exported symbol ROM_WIFI_FWFreeToGo = 0x1275d; -define exported symbol ROM_WIFI_InitLLTTable = 0x127f9; -define exported symbol ROM_WIFI_GetChnlGroup = 0x12879; -define exported symbol ROM_WIFI_BWMapping = 0x129f1; -define exported symbol ROM_WIFI_SCMapping = 0x12a19; -define exported symbol ROM_WIFI_FillTxdescSectype = 0x12a99; -define exported symbol ROM_WIFI_FillFakeTxdesc = 0x12ab9; -define exported symbol ROM_WIFI_32K_Cmd = 0x12b91; -define exported symbol ROM_WIFI_DISCONNECT = 0x12bc1; -define exported symbol ROM_WIFI_SET_TSF = 0x12bfd; -define exported symbol ROM_WIFI_BCN_FUNC = 0x12ca5; -define exported symbol ROM_WIFI_BSSID_SET = 0x12ccd; -define exported symbol ROM_WIFI_MACADDR_SET = 0x12d09; -define exported symbol ROM_WIFI_EnableInterrupt = 0x12d39; -define exported symbol ROM_WIFI_DisableInterrupt = 0x12d4d; -define exported symbol ROM_WIFI_RESUME_TxBeacon = 0x12d61; -define exported symbol ROM_WIFI_STOP_TXBeacon = 0x12d91; -define exported symbol ROM_WIFI_BCN_Interval = 0x12dc1; -define exported symbol ROM_WIFI_BCN_FUNC_Enable = 0x12dcd; -define exported symbol ROM_WIFI_INIT_BeaconParameters = 0x12de5; -define exported symbol ROM_WIFI_MEDIA_STATUS1 = 0x12e35; -define exported symbol ROM_WIFI_MEDIA_STATUS = 0x12e4d; -define exported symbol ROM_WIFI_SetBrateCfg = 0x12e61; -define exported symbol ROM_WIFI_BASIC_RATE = 0x12f69; -define exported symbol ROM_WIFI_CHECK_BSSID = 0x12fc9; -define exported symbol ROM_WIFI_RESP_SIFS = 0x12fe9; -define exported symbol ROM_WIFI_CAM_WRITE = 0x13001; -define exported symbol ROM_WIFI_ACM_CTRL = 0x13021; -define exported symbol ROM_WIFI_FIFO_CLEARN_UP = 0x13051; -define exported symbol ROM_WIFI_CHECK_TXBUF = 0x130b9; -define exported symbol ROM_WIFI_BCN_VALID = 0x130fd; -define exported symbol ROM_WIFI_PROMISC_Cmd = 0x13119; -define exported symbol ROM_WIFI_SetOpmodeAP = 0x13189; -define exported symbol ROM_WIFI_ReadChipVersion = 0x132a9; -define exported symbol ROM_WIFI_DumpChipInfo = 0x1330d; -define exported symbol ROM_WIFI_InitLxDma = 0x135b1; -define exported symbol ROM_WIFI_InitQueueReservedPage = 0x13671; -define exported symbol ROM_WIFI_InitTxBufferBoundary = 0x136f1; -define exported symbol ROM_WIFI_InitNormalChipRegPriority = 0x1373d; -define exported symbol ROM_WIFI_InitPageBoundary = 0x13789; -define exported symbol ROM_WIFI_InitTransferPageSize = 0x13795; -define exported symbol ROM_WIFI_InitDriverInfoSize = 0x137a1; -define exported symbol ROM_WIFI_InitNetworkType = 0x137ad; -define exported symbol ROM_WIFI_InitRCR = 0x137c5; -define exported symbol ROM_WIFI_InitAdaptiveCtrl = 0x13805; -define exported symbol ROM_WIFI_InitSIFS = 0x1383d; -define exported symbol ROM_WIFI_InitEDCA = 0x13865; -define exported symbol ROM_WIFI_InitRateFallback = 0x138a1; -define exported symbol ROM_WIFI_InitRetryFunction = 0x138c9; -define exported symbol ROM_WIFI_InitOperationMode = 0x138e5; -define exported symbol ROM_WIFI_InitBurstPktLen = 0x138f9; -define exported symbol phy_CalculateBitShift = 0x13905; -define exported symbol PHY_SetBBReg_8711B = 0x1391d; -define exported symbol PHY_QueryBBReg_8711B = 0x13921; -define exported symbol ROM_odm_QueryRxPwrPercentage = 0x13925; -define exported symbol ROM_odm_EVMdbToPercentage = 0x13931; -define exported symbol ROM_odm_SignalScaleMapping_8711B = 0x13935; -define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x13a11; -define exported symbol ROM_odm_SetEDCCAThreshold = 0x13d39; -define exported symbol ROM_odm_SetTRxMux = 0x13d61; -define exported symbol ROM_odm_SetCrystalCap = 0x13d89; -define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x13ded; -define exported symbol ROM_ODM_CfoTrackingReset = 0x13dfd; -define exported symbol ROM_odm_CfoTrackingFlow = 0x13e21; -define exported symbol rtw_get_bit_value_from_ieee_value = 0x14045; -define exported symbol rtw_is_cckrates_included = 0x14071; -define exported symbol rtw_is_cckratesonly_included = 0x140a5; -define exported symbol rtw_check_network_type = 0x140cd; -define exported symbol rtw_set_fixed_ie = 0x14155; -define exported symbol rtw_set_ie = 0x14175; -define exported symbol rtw_get_ie = 0x141a1; -define exported symbol rtw_set_supported_rate = 0x141b5; -define exported symbol rtw_get_rateset_len = 0x14229; -define exported symbol rtw_get_wpa_ie = 0x14245; -define exported symbol rtw_get_wpa2_ie = 0x142d1; -define exported symbol rtw_get_wpa_cipher_suite = 0x142e5; -define exported symbol rtw_get_wpa2_cipher_suite = 0x1434d; -define exported symbol rtw_parse_wpa_ie = 0x143b5; -define exported symbol rtw_parse_wpa2_ie = 0x14481; -define exported symbol rtw_get_sec_ie = 0x14535; -define exported symbol rtw_get_wps_ie = 0x145e5; -define exported symbol rtw_get_wps_attr = 0x14659; -define exported symbol rtw_get_wps_attr_content = 0x146f1; -define exported symbol rtw_ieee802_11_parse_elems = 0x14739; -define exported symbol str_2char2num = 0x14909; -define exported symbol key_2char2num = 0x14925; -define exported symbol convert_ip_addr = 0x1493d; -define exported symbol rom_psk_PasswordHash = 0x14a21; -define exported symbol rom_psk_CalcGTK = 0x14a59; -define exported symbol rom_psk_CalcPTK = 0x14ae9; -define exported symbol _htons_rom = 0x14bdd; -define exported symbol _ntohs_rom = 0x14be5; -define exported symbol _htonl_rom = 0x14bed; -define exported symbol _ntohl_rom = 0x14bf1; -define exported symbol Message_ReplayCounter_OC2LI = 0x14bf5; -define exported symbol Message_EqualReplayCounter = 0x14c35; -define exported symbol Message_SmallerEqualReplayCounter = 0x14c6d; -define exported symbol Message_LargerReplayCounter = 0x14cad; -define exported symbol Message_setReplayCounter = 0x14ce5; -define exported symbol INCLargeInteger = 0x14d15; -define exported symbol INCOctet16_INTEGER = 0x14d25; -define exported symbol INCOctet32_INTEGER = 0x14d8d; -define exported symbol SetEAPOL_KEYIV = 0x14df5; -define exported symbol CheckMIC = 0x14e89; -define exported symbol CalcMIC = 0x14f29; -define exported symbol DecWPA2KeyData_rom = 0x14f9d; -define exported symbol DecGTK = 0x15055; -define exported symbol GetRandomBuffer = 0x15119; -define exported symbol GenNonce = 0x15181; -define exported symbol ClientConstructEAPOL_2Of4Way = 0x151c5; -define exported symbol ClientConstructEAPOL_4Of4Way = 0x152cd; -define exported symbol ClientConstructEAPOL_2Of2Way = 0x1537d; -define exported symbol ClientConstructEAPOL_MICOf2Way = 0x15459; -define exported symbol psk_strip_rsn_pairwise = 0x1552d; -define exported symbol psk_strip_wpa_pairwise = 0x155c1; -define exported symbol wep_80211_encrypt = 0x1587d; -define exported symbol wep_80211_decrypt = 0x158e1; -define exported symbol tkip_micappendbyte = 0x15975; -define exported symbol rtw_secmicsetkey = 0x159b9; -define exported symbol rtw_secmicappend = 0x159f9; -define exported symbol rtw_secgetmic = 0x15a15; -define exported symbol rtw_seccalctkipmic = 0x15a89; -define exported symbol tkip_phase1 = 0x15b7d; -define exported symbol tkip_phase2 = 0x15ce5; -define exported symbol tkip_80211_encrypt = 0x15f01; -define exported symbol tkip_80211_decrypt = 0x15f91; -define exported symbol aes1_encrypt = 0x16055; -define exported symbol aesccmp_construct_mic_iv = 0x1625d; -define exported symbol aesccmp_construct_mic_header1 = 0x162b1; -define exported symbol aesccmp_construct_mic_header2 = 0x16321; -define exported symbol aesccmp_construct_ctr_preload = 0x163a5; -define exported symbol aes_80211_encrypt = 0x16429; -define exported symbol aes_80211_decrypt = 0x167f9; -define exported symbol cckrates_included = 0x16c39; -define exported symbol cckratesonly_included = 0x16c7d; -define exported symbol networktype_to_raid_ex_rom = 0x16ca9; -define exported symbol judge_network_type_rom = 0x16cf5; -define exported symbol ratetbl_val_2wifirate = 0x16d89; -define exported symbol is_basicrate_rom = 0x16d9d; -define exported symbol ratetbl2rateset_rom = 0x16dd5; -define exported symbol get_rate_set_rom = 0x16e3d; -define exported symbol UpdateBrateTbl_rom = 0x16e71; -define exported symbol UpdateBrateTblForSoftAP = 0x16ec9; -define exported symbol write_cam_rom = 0x16f0d; -define exported symbol HT_caps_handler_rom = 0x16fc1; -define exported symbol wifirate2_ratetbl_inx = 0x17015; -define exported symbol update_basic_rate = 0x170bd; -define exported symbol update_supported_rate = 0x170f5; -define exported symbol update_MCS_rate = 0x17125; -define exported symbol get_highest_rate_idx = 0x17131; -define exported symbol _sha1_process_message_block = 0x1714d; -define exported symbol _sha1_pad_message = 0x172d1; -define exported symbol rt_sha1_init = 0x1736d; -define exported symbol rt_sha1_update = 0x173b1; -define exported symbol rt_sha1_finish = 0x17429; -define exported symbol rt_hmac_sha1 = 0x17489; -define exported symbol rom_aes_128_cbc_encrypt = 0x175e5; -define exported symbol rom_aes_128_cbc_decrypt = 0x17669; -define exported symbol rom_rijndaelKeySetupEnc = 0x176ed; -define exported symbol rom_aes_decrypt_init = 0x177c1; -define exported symbol rom_aes_internal_decrypt = 0x17899; -define exported symbol rom_aes_decrypt_deinit = 0x17bdd; -define exported symbol rom_aes_encrypt_init = 0x17be9; -define exported symbol rom_aes_internal_encrypt = 0x17c01; -define exported symbol rom_aes_encrypt_deinit = 0x17f81; -define exported symbol bignum_init = 0x1963d; -define exported symbol bignum_deinit = 0x19665; -define exported symbol bignum_get_unsigned_bin_len = 0x19685; -define exported symbol bignum_get_unsigned_bin = 0x19689; -define exported symbol bignum_set_unsigned_bin = 0x19741; -define exported symbol bignum_cmp = 0x197f9; -define exported symbol bignum_cmp_d = 0x197fd; -define exported symbol bignum_add = 0x19825; -define exported symbol bignum_sub = 0x19835; -define exported symbol bignum_mul = 0x19845; -define exported symbol bignum_exptmod = 0x19855; -define exported symbol WPS_realloc = 0x19879; -define exported symbol os_zalloc = 0x198bd; -define exported symbol rom_hmac_sha256_vector = 0x198e1; -define exported symbol rom_hmac_sha256 = 0x199e1; -define exported symbol rom_sha256_vector = 0x19b3d; -define exported symbol CRYPTO_chacha_20 = 0x19d45; -define exported symbol rom_ed25519_gen_keypair = 0x1a1bd; -define exported symbol rom_ed25519_gen_signature = 0x1a1c1; -define exported symbol rom_ed25519_verify_signature = 0x1a1d9; -define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x1c4c9; -define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x1c8c1; -define exported symbol rom_ed25519_ge_p3_tobytes = 0x1d43d; -define exported symbol rom_ed25519_ge_scalarmult_base = 0x1d489; -define exported symbol rom_ed25519_ge_tobytes = 0x1d64d; -define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x1d699; -define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x1d6f1; -define exported symbol rom_ed25519_sc_muladd = 0x1d9e5; -define exported symbol rom_ed25519_sc_reduce = 0x24175; -define exported symbol rom_ed25519_crypto_sign_detached = 0x26c25; -define exported symbol CRYPTO_poly1305_init = 0x270dd; -define exported symbol CRYPTO_poly1305_update = 0x271b5; -define exported symbol CRYPTO_poly1305_finish = 0x27245; -define exported symbol rom_sha512_starts = 0x28511; -define exported symbol rom_sha512_update = 0x28659; -define exported symbol rom_sha512_finish = 0x28661; -define exported symbol rom_sha512 = 0x288a9; -define exported symbol rom_sha512_hmac_starts = 0x288e1; -define exported symbol rom_sha512_hmac_update = 0x289a5; -define exported symbol rom_sha512_hmac_finish = 0x289ad; -define exported symbol rom_sha512_hmac_reset = 0x289fd; -define exported symbol rom_sha512_hmac = 0x28a19; -define exported symbol rom_sha512_hkdf = 0x28a51; -define exported symbol aes_test_alignment_detection = 0x28b59; -define exported symbol aes_mode_reset = 0x28bbd; -define exported symbol aes_ecb_encrypt = 0x28bc9; -define exported symbol aes_ecb_decrypt = 0x28c05; -define exported symbol aes_cbc_encrypt = 0x28c41; -define exported symbol aes_cbc_decrypt = 0x28dad; -define exported symbol aes_cfb_encrypt = 0x28f49; -define exported symbol aes_cfb_decrypt = 0x2920d; -define exported symbol aes_ofb_crypt = 0x294d5; -define exported symbol aes_ctr_crypt = 0x29769; -define exported symbol aes_encrypt_key128 = 0x29a79; -define exported symbol aes_encrypt_key192 = 0x29a95; -define exported symbol aes_encrypt_key256 = 0x29ab1; -define exported symbol aes_encrypt_key = 0x29ad1; -define exported symbol aes_decrypt_key128 = 0x29b41; -define exported symbol aes_decrypt_key192 = 0x29b5d; -define exported symbol aes_decrypt_key256 = 0x29b79; -define exported symbol aes_decrypt_key = 0x29b99; -define exported symbol aes_init = 0x29c09; -define exported symbol curve25519_donna = 0x2a939; -define exported symbol __rtl_dtoa_r_v1_00 = 0x2b7f1; -define exported symbol __rtl_ltoa_v1_00 = 0x2c7f9; -define exported symbol __rtl_ultoa_v1_00 = 0x2c885; -define exported symbol __rtl_dtoi_v1_00 = 0x2c8ed; -define exported symbol __rtl_dtoi64_v1_00 = 0x2c96d; -define exported symbol __rtl_dtoui_v1_00 = 0x2ca09; -define exported symbol __rtl_ftol_v1_00 = 0x2ca11; -define exported symbol __rtl_itof_v1_00 = 0x2ca75; -define exported symbol __rtl_itod_v1_00 = 0x2cb05; -define exported symbol __rtl_i64tod_v1_00 = 0x2cb71; -define exported symbol __rtl_uitod_v1_00 = 0x2cc4d; -define exported symbol __rtl_ftod_v1_00 = 0x2cd29; -define exported symbol __rtl_dtof_v1_00 = 0x2cde1; -define exported symbol __rtl_uitof_v1_00 = 0x2ce75; -define exported symbol __rtl_fadd_v1_00 = 0x2cf59; -define exported symbol __rtl_fsub_v1_00 = 0x2d259; -define exported symbol __rtl_fmul_v1_00 = 0x2d565; -define exported symbol __rtl_fdiv_v1_00 = 0x2d695; -define exported symbol __rtl_dadd_v1_00 = 0x2d809; -define exported symbol __rtl_dsub_v1_00 = 0x2de49; -define exported symbol __rtl_dmul_v1_00 = 0x2e4a1; -define exported symbol __rtl_ddiv_v1_00 = 0x2e7dd; -define exported symbol __rtl_dcmpeq_v1_00 = 0x2ed71; -define exported symbol __rtl_dcmplt_v1_00 = 0x2eded; -define exported symbol __rtl_dcmpgt_v1_00 = 0x2ee85; -define exported symbol __rtl_dcmple_v1_00 = 0x2ef95; -define exported symbol __rtl_fcmplt_v1_00 = 0x2f0a9; -define exported symbol __rtl_fcmpgt_v1_00 = 0x2f105; -define exported symbol __rtl_fpclassifyd = 0x2f1ad; -define exported symbol __rtl_close_v1_00 = 0x2f205; -define exported symbol __rtl_fstat_v1_00 = 0x2f219; -define exported symbol __rtl_isatty_v1_00 = 0x2f22d; -define exported symbol __rtl_lseek_v1_00 = 0x2f23d; -define exported symbol __rtl_open_v1_00 = 0x2f251; -define exported symbol __rtl_read_v1_00 = 0x2f265; -define exported symbol __rtl_write_v1_00 = 0x2f279; -define exported symbol __rtl_sbrk_v1_00 = 0x2f28d; -define exported symbol __rom_mallocr_init_v1_00 = 0x2f29d; -define exported symbol __rtl_free_r_v1_00 = 0x2f309; -define exported symbol __rtl_malloc_r_v1_00 = 0x2f521; -define exported symbol __rtl_realloc_r_v1_00 = 0x2f9f5; -define exported symbol __rtl_memalign_r_v1_00 = 0x2fdb5; -define exported symbol __rtl_valloc_r_v1_00 = 0x2fe81; -define exported symbol __rtl_pvalloc_r_v1_00 = 0x2fe8d; -define exported symbol __rtl_calloc_r_v1_00 = 0x2fea1; -define exported symbol __rtl_cfree_r_v1_00 = 0x2ff05; -define exported symbol __rtl_cos_f32_v1_00 = 0x2ff15; -define exported symbol __rtl_sin_f32_v1_00 = 0x300e9; -define exported symbol __rtl_fabs_v1_00 = 0x302ad; -define exported symbol __rtl_fabsf_v1_00 = 0x302b5; -define exported symbol __rtl_memchr_v1_00 = 0x302bd; -define exported symbol __rtl_memcmp_v1_00 = 0x30351; -define exported symbol __rtl_memcpy_v1_00 = 0x303b5; -define exported symbol __rtl_memmove_v1_00 = 0x3045d; -define exported symbol __rtl_memset_v1_00 = 0x30525; -define exported symbol __rtl_Balloc_v1_00 = 0x3061d; -define exported symbol __rtl_Bfree_v1_00 = 0x3066d; -define exported symbol __rtl_i2b_v1_00 = 0x30681; -define exported symbol __rtl_multadd_v1_00 = 0x30695; -define exported symbol __rtl_mult_v1_00 = 0x30721; -define exported symbol __rtl_pow5mult_v1_00 = 0x30855; -define exported symbol __rtl_hi0bits_v1_00 = 0x308f5; -define exported symbol __rtl_d2b_v1_00 = 0x30935; -define exported symbol __rtl_lshift_v1_00 = 0x309ed; -define exported symbol __rtl_cmp_v1_00 = 0x30a99; -define exported symbol __rtl_diff_v1_00 = 0x30ae1; -define exported symbol __rtl_sread_v1_00 = 0x30bb5; -define exported symbol __rtl_seofread_v1_00 = 0x30c01; -define exported symbol __rtl_swrite_v1_00 = 0x30c05; -define exported symbol __rtl_sseek_v1_00 = 0x30c75; -define exported symbol __rtl_sclose_v1_00 = 0x30cc1; -define exported symbol __rtl_sbrk_r_v1_00 = 0x30ced; -define exported symbol __rtl_strcat_v1_00 = 0x30d15; -define exported symbol __rtl_strchr_v1_00 = 0x30d59; -define exported symbol __rtl_strcmp_v1_00 = 0x30e25; -define exported symbol __rtl_strcpy_v1_00 = 0x30e99; -define exported symbol __rtl_strlen_v1_00 = 0x30ee5; -define exported symbol __rtl_strncat_v1_00 = 0x30f39; -define exported symbol __rtl_strncmp_v1_00 = 0x30f95; -define exported symbol __rtl_strncpy_v1_00 = 0x3102d; -define exported symbol __rtl_strsep_v1_00 = 0x31095; -define exported symbol __rtl_strstr_v1_00 = 0x3136d; -define exported symbol __rtl_strtok_v1_00 = 0x315a5; -define exported symbol __rtl__strtok_r_v1_00 = 0x315b5; -define exported symbol __rtl_strtok_r_v1_00 = 0x31619; -define exported symbol __rtl_fflush_r_v1_00 = 0x31ae9; -define exported symbol __rtl_vfprintf_r_v1_00 = 0x31f99; -define exported symbol polarssl_aes_init = 0x335b9; -define exported symbol aes_free = 0x335c9; -define exported symbol aes_setkey_enc = 0x335dd; -define exported symbol aes_setkey_dec = 0x33829; -define exported symbol aes_crypt_ecb = 0x339a1; -define exported symbol aes_crypt_cbc = 0x343d1; -define exported symbol aes_crypt_cfb128 = 0x34649; -define exported symbol aes_crypt_cfb8 = 0x346c9; -define exported symbol aes_crypt_ctr = 0x3474d; -define exported symbol arc4_init = 0x347b1; -define exported symbol arc4_free = 0x347bd; -define exported symbol arc4_setup = 0x347d1; -define exported symbol arc4_crypt = 0x3481d; -define exported symbol asn1_get_len = 0x34861; -define exported symbol asn1_get_tag = 0x34901; -define exported symbol asn1_get_bool = 0x34929; -define exported symbol asn1_get_int = 0x3495d; -define exported symbol asn1_get_mpi = 0x349a9; -define exported symbol asn1_get_bitstring = 0x349d1; -define exported symbol asn1_get_bitstring_null = 0x34a19; -define exported symbol asn1_get_sequence_of = 0x34a4d; -define exported symbol asn1_get_alg = 0x34ad1; -define exported symbol asn1_get_alg_null = 0x34b65; -define exported symbol asn1_free_named_data = 0x34ba5; -define exported symbol asn1_free_named_data_list = 0x34bcd; -define exported symbol asn1_find_named_data = 0x34bf5; -define exported symbol asn1_write_len = 0x34c25; -define exported symbol asn1_write_tag = 0x34c8d; -define exported symbol asn1_write_raw_buffer = 0x34ca9; -define exported symbol asn1_write_mpi = 0x34ccd; -define exported symbol asn1_write_null = 0x34d41; -define exported symbol asn1_write_oid = 0x34d6d; -define exported symbol asn1_write_algorithm_identifier = 0x34dc5; -define exported symbol asn1_write_bool = 0x34e21; -define exported symbol asn1_write_int = 0x34e65; -define exported symbol asn1_write_printable_string = 0x34ecd; -define exported symbol asn1_write_ia5_string = 0x34f25; -define exported symbol asn1_write_bitstring = 0x34f7d; -define exported symbol asn1_write_octet_string = 0x34fe5; -define exported symbol asn1_store_named_data = 0x3503d; -define exported symbol base64_encode = 0x35111; -define exported symbol base64_decode = 0x3523d; -define exported symbol mpi_init = 0x35e09; -define exported symbol mpi_free = 0x35e19; -define exported symbol mpi_grow = 0x35e55; -define exported symbol mpi_shrink = 0x35e79; -define exported symbol mpi_copy = 0x35f21; -define exported symbol mpi_swap = 0x35fa1; -define exported symbol mpi_safe_cond_assign = 0x35fcd; -define exported symbol mpi_safe_cond_swap = 0x36069; -define exported symbol mpi_lset = 0x3610d; -define exported symbol mpi_get_bit = 0x3614d; -define exported symbol mpi_set_bit = 0x3616d; -define exported symbol mpi_lsb = 0x361d5; -define exported symbol mpi_msb = 0x36215; -define exported symbol mpi_size = 0x36261; -define exported symbol mpi_read_binary = 0x3626d; -define exported symbol mpi_write_binary = 0x362f9; -define exported symbol mpi_shift_l = 0x36341; -define exported symbol mpi_shift_r = 0x363f1; -define exported symbol mpi_cmp_abs = 0x36475; -define exported symbol mpi_cmp_mpi = 0x36619; -define exported symbol mpi_cmp_int = 0x366f1; -define exported symbol mpi_add_abs = 0x3671d; -define exported symbol mpi_sub_abs = 0x3680d; -define exported symbol mpi_add_mpi = 0x3689d; -define exported symbol mpi_sub_mpi = 0x368ed; -define exported symbol mpi_add_int = 0x3693d; -define exported symbol mpi_sub_int = 0x36969; -define exported symbol mpi_mul_mpi = 0x36995; -define exported symbol mpi_read_string = 0x36ac5; -define exported symbol mpi_mul_int = 0x36c45; -define exported symbol mpi_div_mpi = 0x36c61; -define exported symbol mpi_div_int = 0x370ed; -define exported symbol mpi_mod_mpi = 0x37119; -define exported symbol mpi_mod_int = 0x3717d; -define exported symbol mpi_write_string = 0x3722d; -define exported symbol mpi_exp_mod = 0x37395; -define exported symbol mpi_gcd = 0x37915; -define exported symbol mpi_fill_random = 0x37a39; -define exported symbol mpi_inv_mod = 0x37c4d; -define exported symbol mpi_is_prime = 0x37f15; -define exported symbol mpi_gen_prime = 0x37f71; -define exported symbol ctr_drbg_free = 0x38285; -define exported symbol ctr_drbg_set_prediction_resistance = 0x382a1; -define exported symbol ctr_drbg_set_entropy_len = 0x382a5; -define exported symbol ctr_drbg_set_reseed_interval = 0x382a9; -define exported symbol ctr_drbg_update = 0x382ad; -define exported symbol ctr_drbg_reseed = 0x382c9; -define exported symbol ctr_drbg_init_entropy_len = 0x38341; -define exported symbol ctr_drbg_init = 0x38399; -define exported symbol ctr_drbg_random_with_add = 0x383ad; -define exported symbol ctr_drbg_random = 0x38469; -define exported symbol des_init = 0x388a5; -define exported symbol des_free = 0x388b1; -define exported symbol des3_init = 0x388c5; -define exported symbol des3_free = 0x388d5; -define exported symbol des_key_set_parity = 0x388e9; -define exported symbol des_key_check_key_parity = 0x38909; -define exported symbol des_key_check_weak = 0x38939; -define exported symbol des_setkey_enc = 0x38965; -define exported symbol des_setkey_dec = 0x3898d; -define exported symbol des3_set2key_enc = 0x389d9; -define exported symbol des3_set2key_dec = 0x38a25; -define exported symbol des3_set3key_enc = 0x38a71; -define exported symbol des3_set3key_dec = 0x38ab1; -define exported symbol des_crypt_ecb = 0x38af1; -define exported symbol des_crypt_cbc = 0x38d09; -define exported symbol des3_crypt_ecb = 0x38f99; -define exported symbol des3_crypt_cbc = 0x39401; -define exported symbol dhm_init = 0x39729; -define exported symbol dhm_read_params = 0x39731; -define exported symbol dhm_make_params = 0x3978d; -define exported symbol dhm_read_public = 0x398c1; -define exported symbol dhm_make_public = 0x398e9; -define exported symbol dhm_calc_secret = 0x399ad; -define exported symbol dhm_free = 0x39ba1; -define exported symbol dhm_parse_dhm = 0x39c01; -define exported symbol ecdh_gen_public = 0x39cc5; -define exported symbol ecdh_compute_shared = 0x39cc9; -define exported symbol ecdh_init = 0x39d2d; -define exported symbol ecdh_free = 0x39d39; -define exported symbol ecdh_make_params = 0x39d81; -define exported symbol ecdh_read_params = 0x39e05; -define exported symbol ecdh_get_params = 0x39e2d; -define exported symbol ecdh_make_public = 0x39e79; -define exported symbol ecdh_read_public = 0x39ed1; -define exported symbol ecdh_calc_secret = 0x39f01; -define exported symbol ecdsa_sign = 0x3a041; -define exported symbol ecdsa_sign_det = 0x3a1c5; -define exported symbol ecdsa_verify = 0x3a2a9; -define exported symbol ecdsa_write_signature = 0x3a431; -define exported symbol ecdsa_write_signature_det = 0x3a46d; -define exported symbol ecdsa_read_signature = 0x3a4a5; -define exported symbol ecdsa_genkey = 0x3a531; -define exported symbol ecdsa_init = 0x3a565; -define exported symbol ecdsa_free = 0x3a591; -define exported symbol ecdsa_from_keypair = 0x3a5bd; -define exported symbol ecp_curve_list = 0x3aee5; -define exported symbol ecp_curve_info_from_grp_id = 0x3aeed; -define exported symbol ecp_curve_info_from_tls_id = 0x3af0d; -define exported symbol ecp_curve_info_from_name = 0x3af31; -define exported symbol ecp_point_init = 0x3af61; -define exported symbol ecp_group_init = 0x3af81; -define exported symbol ecp_keypair_init = 0x3af8d; -define exported symbol ecp_point_free = 0x3afb1; -define exported symbol ecp_group_free = 0x3afd1; -define exported symbol ecp_keypair_free = 0x3b03d; -define exported symbol ecp_copy = 0x3b05d; -define exported symbol ecp_group_copy = 0x3b08d; -define exported symbol ecp_set_zero = 0x3b095; -define exported symbol ecp_is_zero = 0x3ba61; -define exported symbol ecp_point_read_string = 0x3ba75; -define exported symbol ecp_point_write_binary = 0x3baa5; -define exported symbol ecp_point_read_binary = 0x3bb4d; -define exported symbol ecp_tls_read_point = 0x3bbc1; -define exported symbol ecp_tls_write_point = 0x3bbf5; -define exported symbol ecp_group_read_string = 0x3bc25; -define exported symbol ecp_tls_read_group = 0x3bc95; -define exported symbol ecp_tls_write_group = 0x3bcf1; -define exported symbol ecp_add = 0x3bd39; -define exported symbol ecp_sub = 0x3bd65; -define exported symbol ecp_check_pubkey = 0x3bddd; -define exported symbol ecp_check_privkey = 0x3bf8d; -define exported symbol ecp_mul = 0x3bff5; -define exported symbol ecp_gen_keypair = 0x3c565; -define exported symbol ecp_gen_key = 0x3c669; -define exported symbol ecp_use_known_dp = 0x3d741; -define exported symbol hmac_drbg_update = 0x3daa9; -define exported symbol hmac_drbg_init_buf = 0x3db41; -define exported symbol hmac_drbg_reseed = 0x3db91; -define exported symbol hmac_drbg_init = 0x3dc09; -define exported symbol hmac_drbg_set_prediction_resistance = 0x3dc81; -define exported symbol hmac_drbg_set_entropy_len = 0x3dc85; -define exported symbol hmac_drbg_set_reseed_interval = 0x3dc89; -define exported symbol hmac_drbg_random_with_add = 0x3dc8d; -define exported symbol hmac_drbg_random = 0x3dd4d; -define exported symbol hmac_drbg_free = 0x3dd61; -define exported symbol md_list = 0x3dd7d; -define exported symbol md_info_from_string = 0x3dd85; -define exported symbol md_info_from_type = 0x3de59; -define exported symbol md_init = 0x3de9d; -define exported symbol md_free = 0x3dea5; -define exported symbol md_init_ctx = 0x3dec5; -define exported symbol md_free_ctx = 0x3defd; -define exported symbol md_starts = 0x3df09; -define exported symbol md_update = 0x3df29; -define exported symbol md_finish = 0x3df49; -define exported symbol md = 0x3df69; -define exported symbol md_file = 0x3df89; -define exported symbol md_hmac_starts = 0x3dfa1; -define exported symbol md_hmac_update = 0x3dfc1; -define exported symbol md_hmac_finish = 0x3dfe1; -define exported symbol md_hmac_reset = 0x3e001; -define exported symbol md_hmac = 0x3e021; -define exported symbol md_process = 0x3e049; -define exported symbol md5_init = 0x3e301; -define exported symbol md5_free = 0x3e309; -define exported symbol md5_starts = 0x3e31d; -define exported symbol md5_process = 0x3e34d; -define exported symbol md5_update = 0x3ed51; -define exported symbol md5_finish = 0x3ed59; -define exported symbol md5 = 0x3ee11; -define exported symbol md5_hmac_starts = 0x3ee75; -define exported symbol md5_hmac_update = 0x3ef51; -define exported symbol md5_hmac_finish = 0x3ef59; -define exported symbol md5_hmac_reset = 0x3efbd; -define exported symbol md5_hmac = 0x3eff1; -define exported symbol oid_get_attr_short_name = 0x3f071; -define exported symbol oid_get_x509_ext_type = 0x3f0b1; -define exported symbol oid_get_extended_key_usage = 0x3f0f1; -define exported symbol oid_get_sig_alg_desc = 0x3f131; -define exported symbol oid_get_sig_alg = 0x3f149; -define exported symbol oid_get_oid_by_sig_alg = 0x3f169; -define exported symbol oid_get_pk_alg = 0x3f1a1; -define exported symbol oid_get_oid_by_pk_alg = 0x3f1e1; -define exported symbol oid_get_ec_grp = 0x3f219; -define exported symbol oid_get_oid_by_ec_grp = 0x3f259; -define exported symbol oid_get_cipher_alg = 0x3f291; -define exported symbol oid_get_md_alg = 0x3f2d1; -define exported symbol oid_get_oid_by_md = 0x3f311; -define exported symbol oid_get_pkcs12_pbe_alg = 0x3f349; -define exported symbol oid_get_numeric_string = 0x3f391; -define exported symbol pem_init = 0x3f649; -define exported symbol pem_read_buffer = 0x3f651; -define exported symbol pem_free = 0x3f955; -define exported symbol pem_write_buffer = 0x3f97d; -define exported symbol pk_init = 0x3fa81; -define exported symbol pk_free = 0x3fa8d; -define exported symbol pk_info_from_type = 0x3faad; -define exported symbol pk_init_ctx = 0x3fae1; -define exported symbol pk_init_ctx_rsa_alt = 0x3fb11; -define exported symbol pk_can_do = 0x3fb69; -define exported symbol pk_verify = 0x3fb79; -define exported symbol pk_verify_ext = 0x3fbc9; -define exported symbol pk_sign = 0x3fc8d; -define exported symbol pk_decrypt = 0x3fce9; -define exported symbol pk_encrypt = 0x3fd15; -define exported symbol pk_get_size = 0x3fd41; -define exported symbol pk_debug = 0x3fd51; -define exported symbol pk_get_name = 0x3fd79; -define exported symbol pk_get_type = 0x3fd8d; -define exported symbol pk_write_pubkey = 0x40181; -define exported symbol pk_write_pubkey_der = 0x40201; -define exported symbol pk_write_key_der = 0x402dd; -define exported symbol pk_write_pubkey_pem = 0x404f5; -define exported symbol pk_write_key_pem = 0x40545; -define exported symbol rsa_init = 0x4065d; -define exported symbol rsa_set_padding = 0x40679; -define exported symbol rsa_check_pubkey = 0x40685; -define exported symbol rsa_check_privkey = 0x406e1; -define exported symbol rsa_public = 0x409a5; -define exported symbol rsa_private = 0x40a25; -define exported symbol rsa_rsaes_oaep_encrypt = 0x40c29; -define exported symbol rsa_rsaes_pkcs1_v15_encrypt = 0x40d31; -define exported symbol rsa_pkcs1_encrypt = 0x40e19; -define exported symbol rsa_rsaes_oaep_decrypt = 0x40e59; -define exported symbol rsa_rsaes_pkcs1_v15_decrypt = 0x40fbd; -define exported symbol rsa_pkcs1_decrypt = 0x410c1; -define exported symbol rsa_rsassa_pss_sign = 0x4110d; -define exported symbol rsa_rsassa_pkcs1_v15_sign = 0x41271; -define exported symbol rsa_pkcs1_sign = 0x41389; -define exported symbol rsa_rsassa_pss_verify_ext = 0x413c9; -define exported symbol rsa_rsassa_pss_verify = 0x41575; -define exported symbol rsa_rsassa_pkcs1_v15_verify = 0x415a5; -define exported symbol rsa_pkcs1_verify = 0x41709; -define exported symbol rsa_free = 0x41765; -define exported symbol rsa_gen_key = 0x417d5; -define exported symbol rsa_copy = 0x4198d; -define exported symbol sha1_init = 0x41a9d; -define exported symbol sha1_free = 0x41aa5; -define exported symbol sha1_starts = 0x41ab9; -define exported symbol sha1_process = 0x41aed; -define exported symbol sha1_update = 0x42e15; -define exported symbol sha1_finish = 0x42e1d; -define exported symbol sha1 = 0x42ee5; -define exported symbol sha1_hmac_starts = 0x42f51; -define exported symbol sha1_hmac_update = 0x43039; -define exported symbol sha1_hmac_finish = 0x43041; -define exported symbol sha1_hmac_reset = 0x430b5; -define exported symbol sha1_hmac = 0x430f1; -define exported symbol sha256_init = 0x43139; -define exported symbol sha256_free = 0x43141; -define exported symbol sha256_starts = 0x43155; -define exported symbol sha256_process = 0x431e5; -define exported symbol sha256_update = 0x4513d; -define exported symbol sha256_finish = 0x45145; -define exported symbol sha256 = 0x4524d; -define exported symbol sha256_hmac_starts = 0x45325; -define exported symbol sha256_hmac_update = 0x45475; -define exported symbol sha256_hmac_finish = 0x4547d; -define exported symbol sha256_hmac_reset = 0x45569; -define exported symbol sha256_hmac = 0x45601; -define exported symbol sha512_init = 0x45651; -define exported symbol sha512_free = 0x4565d; -define exported symbol sha512_starts = 0x45671; -define exported symbol sha512_process = 0x457b9; -define exported symbol sha512_update = 0x46879; -define exported symbol sha512_finish = 0x46881; -define exported symbol sha512 = 0x46ac9; -define exported symbol sha512_hmac_starts = 0x46b11; -define exported symbol sha512_hmac_update = 0x46bd9; -define exported symbol sha512_hmac_finish = 0x46be1; -define exported symbol sha512_hmac_reset = 0x46c35; -define exported symbol sha512_hmac = 0x46c51; -define exported symbol UartLogRomCmdTable = 0x46ca0; -define exported symbol XTAL_CLK = 0x46e10; -define exported symbol CpkClkTbl_FPAG = 0x46e50; -define exported symbol CpkClkTbl_ASIC = 0x46e68; -define exported symbol ROM_IMG1_VALID_PATTEN = 0x46e90; -define exported symbol __AES_rcon = 0x46e98; -define exported symbol __AES_Te4 = 0x46ec0; -define exported symbol SpicCalibrationPattern = 0x472c0; -define exported symbol NEW_CALIBREATION_DIV = 0x472c8; -define exported symbol NEW_CALIBREATION_DATA = 0x472e4; -define exported symbol GDMA_IrqNum = 0x47344; -define exported symbol I2C_DEV_TABLE = 0x47350; -define exported symbol spi_clk_pin = 0x47370; -define exported symbol SPI_DEV_TABLE = 0x47374; -define exported symbol PWM_GDMA_HSx = 0x47394; -define exported symbol TIM_DMA_CCx = 0x473ac; -define exported symbol TIM_IT_CCx = 0x473c4; -define exported symbol TIMx = 0x473dc; -define exported symbol TIMx_irq = 0x473f4; -define exported symbol BAUDRATE_TABLE_40M = 0x4740c; -define exported symbol UART_DEV_TABLE = 0x475bc; -define exported symbol RTW_WPA_OUI_TYPE = 0x4b270; -define exported symbol WPA_CIPHER_SUITE_NONE = 0x4b274; -define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x4b278; -define exported symbol WPA_CIPHER_SUITE_TKIP = 0x4b27c; -define exported symbol WPA_CIPHER_SUITE_CCMP = 0x4b280; -define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x4b284; -define exported symbol RSN_CIPHER_SUITE_NONE = 0x4b288; -define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x4b28c; -define exported symbol RSN_CIPHER_SUITE_TKIP = 0x4b290; -define exported symbol RSN_CIPHER_SUITE_CCMP = 0x4b294; -define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x4b298; -define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x4b2a8; -define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x4b2ac; -define exported symbol RSN_VERSION_BSD = 0x4b2b0; -define exported symbol rom_e_rtw_msgp_str_ = 0x4b2b4; -define exported symbol rtw_basic_rate_mix = 0x4b9a8; -define exported symbol rtw_basic_rate_ofdm = 0x4b9b0; -define exported symbol rtw_basic_rate_cck = 0x4b9b4; -define exported symbol REALTEK_96B_IE = 0x4b9b8; -define exported symbol AIRGOCAP_OUI = 0x4b9c0; -define exported symbol REALTEK_OUI = 0x4b9c4; -define exported symbol RALINK_OUI = 0x4b9c8; -define exported symbol MARVELL_OUI = 0x4b9cc; -define exported symbol CISCO_OUI = 0x4b9d0; -define exported symbol BROADCOM_OUI3 = 0x4b9d4; -define exported symbol BROADCOM_OUI2 = 0x4b9d8; -define exported symbol BROADCOM_OUI1 = 0x4b9dc; -define exported symbol ARTHEROS_OUI2 = 0x4b9e0; -define exported symbol ARTHEROS_OUI1 = 0x4b9e4; -define exported symbol rom_wps_rcons = 0x4b9e8; -define exported symbol rom_wps_Te0 = 0x4b9f4; -define exported symbol rom_wps_Td4s = 0x4bdf4; -define exported symbol rom_wps_Td0 = 0x4bef4; -define exported symbol sha512_info = 0x5850c; -define exported symbol sha384_info = 0x5854c; -define exported symbol sha256_info = 0x5858c; -define exported symbol sha224_info = 0x585cc; -define exported symbol sha1_info = 0x5860c; -define exported symbol md5_info = 0x5864c; -define exported symbol rsa_alt_info = 0x58d28; -define exported symbol ecdsa_info = 0x58d54; -define exported symbol eckeydh_info = 0x58d80; -define exported symbol eckey_info = 0x58dac; -define exported symbol rsa_info = 0x58dd8; -define exported symbol __rom_bss_start__ = 0x10000000; -define exported symbol NewVectorTable = 0x10000000; -define exported symbol UserIrqFunTable = 0x10000100; -define exported symbol UserIrqDataTable = 0x10000200; -define exported symbol ConfigDebugClose = 0x10000300; -define exported symbol CfgSysDebugWarn = 0x10000304; -define exported symbol CfgSysDebugInfo = 0x10000308; -define exported symbol CfgSysDebugErr = 0x1000030c; -define exported symbol ConfigDebugWarn = 0x10000310; -define exported symbol ConfigDebugInfo = 0x10000314; -define exported symbol ConfigDebugErr = 0x10000318; -define exported symbol sector_addr = 0x1000031c; -define exported symbol _rtl_impure_ptr = 0x10000338; -define exported symbol ArgvArray = 0x1000033c; -define exported symbol pUartLogCtl = 0x10000364; -define exported symbol UartLogBuf = 0x10000368; -define exported symbol UartLogCtl = 0x100003e8; -define exported symbol UartLogHistoryBuf = 0x10000408; -define exported symbol NCO32K_Enable = 0x10000684; -define exported symbol g_rtl_cipherEngine = 0x100006a0; -define exported symbol DONGLE_InitStruct = 0x10000ba0; -define exported symbol EFUSE_MAP = 0x10000ba4; -define exported symbol USOC_BOOT_TXBD = 0x10000da4; -define exported symbol USOC_BOOT_RXBD = 0x10000db4; -define exported symbol USB_RXBuff = 0x10000dc4; -define exported symbol USB_TXBuff = 0x10000dcc; -define exported symbol ADC_AnaparAd = 0x10000dd4; -define exported symbol flash_init_para = 0x10000dec; -define exported symbol NEW_CALIBREATION_END = 0x10000e44; -define exported symbol GDMA_Reg = 0x10000e4c; -define exported symbol PortA_IrqHandler = 0x10000e50; -define exported symbol PortA_IrqData = 0x10000ed0; -define exported symbol IC_FS_SCL_HCNT_TRIM = 0x10000f50; -define exported symbol IC_FS_SCL_LCNT_TRIM = 0x10000f54; -define exported symbol I2C_SLAVEWRITE_PATCH = 0x10000f58; -define exported symbol i2s_cur_tx_page = 0x10000f5c; -define exported symbol i2s_cur_rx_page = 0x10000f60; -define exported symbol i2s_page_num = 0x10000f64; -define exported symbol i2s_txpage_entry = 0x10000f68; -define exported symbol i2s_rxpage_entry = 0x10000f78; -define exported symbol TXBDAddrAligned = 0x10000f88; -define exported symbol H2C_Buff = 0x10000f90; -define exported symbol SPI_RECV_Buff = 0x10000f94; -define exported symbol spi_boot_recv_done = 0x10000f98; -define exported symbol UART_StateRx = 0x10000f9c; -define exported symbol UART_StateTx = 0x10000fa8; -define exported symbol xMCtrl = 0x10000fb8; -define exported symbol XComUARTx = 0x10000fc4; -define exported symbol FalseAlmCnt = 0x10000fc8; -define exported symbol ROMInfo = 0x10001008; -define exported symbol DM_CfoTrack = 0x10001020; -define exported symbol rom_wlan_ram_map = 0x10001048; -define exported symbol rom_libgloss_ram_map = 0x10001050; -define exported symbol __rtl_errno = 0x100014b4; -define exported symbol rom_ssl_ram_map = 0x100014b8; -define exported symbol __rom_bss_end__ = 0x100014f8; +define exported symbol __vectors_table = 0x0; +define exported symbol Reset_Handler = 0x101; +define exported symbol NMI_Handler = 0x115; +/*define exported symbol HardFault_Handler = 0x119;*/ +define exported symbol MemManage_Handler = 0x12d; +define exported symbol BusFault_Handler = 0x131; +define exported symbol UsageFault_Handler = 0x135; +define exported symbol VSprintf = 0x201; +define exported symbol DiagPrintf = 0x4dd; +define exported symbol DiagSPrintf = 0x509; +define exported symbol DiagSnPrintf = 0x535; +define exported symbol prvDiagPrintf = 0x7ed; +define exported symbol prvDiagSPrintf = 0x821; +define exported symbol UARTIMG_Write = 0x855; +define exported symbol UARTIMG_Download = 0x901; +define exported symbol _memcmp = 0x991; +define exported symbol _memcpy = 0x9c5; +define exported symbol _memset = 0xa7d; +define exported symbol DumpForOneBytes = 0xae9; +define exported symbol CmdRomHelp = 0xc69; +define exported symbol CmdDumpWord = 0xccd; +define exported symbol CmdWriteWord = 0xd7d; +define exported symbol CmdFlash = 0xdd1; +define exported symbol CmdEfuse = 0x12c1; +define exported symbol CmdDumpByte = 0x1775; +define exported symbol CmdDumpHalfWord = 0x17c9; +define exported symbol CmdWriteByte = 0x1881; +define exported symbol SramReadWriteCpy = 0x18c1; +define exported symbol SramReadWriteTest = 0x19f9; +define exported symbol CmdSRamTest = 0x1ac9; +define exported symbol GetRomCmdNum = 0x1b59; +define exported symbol Rand = 0x1b5d; +define exported symbol Rand_Arc4 = 0x1bdd; +define exported symbol RandBytes_Get = 0x1c0d; +define exported symbol Isspace = 0x1c59; +define exported symbol Strtoul = 0x1c6d; +define exported symbol ArrayInitialize = 0x1d15; +define exported symbol GetArgc = 0x1d29; +define exported symbol GetArgv = 0x1d55; +define exported symbol UartLogCmdExecute = 0x1db1; +define exported symbol UartLogShowBackSpace = 0x1e49; +define exported symbol UartLogRecallOldCmd = 0x1e7d; +define exported symbol UartLogHistoryCmd = 0x1eb1; +define exported symbol UartLogCmdChk = 0x1f2d; +define exported symbol UartLogIrqHandle = 0x2035; +define exported symbol RtlConsolInit = 0x2101; +define exported symbol RtlConsolTaskRom = 0x218d; +define exported symbol RtlExitConsol = 0x21b9; +define exported symbol RtlConsolRom = 0x2205; +define exported symbol BKUP_Write = 0x2249; +define exported symbol BKUP_Read = 0x226d; +define exported symbol BKUP_Set = 0x228d; +define exported symbol BKUP_Clear = 0x22b9; +define exported symbol NCO32K_Init = 0x22e9; +define exported symbol EXT32K_Cmd = 0x2349; +define exported symbol NCO8M_Init = 0x2365; +define exported symbol NCO8M_Cmd = 0x23bd; +define exported symbol ISO_Set = 0x23d9; +define exported symbol PLL0_Set = 0x23f1; +define exported symbol PLL1_Set = 0x2409; +define exported symbol PLL2_Set = 0x2421; +define exported symbol PLL3_Set = 0x2439; +define exported symbol XTAL0_Set = 0x2451; +define exported symbol XTAL1_Set = 0x2469; +define exported symbol XTAL2_Set = 0x2481; +define exported symbol XTAL_ClkGet = 0x2499; +define exported symbol CPU_ClkSet = 0x24b1; +define exported symbol CPU_ClkGet = 0x24c5; +define exported symbol OSC32K_Calibration = 0x24e5; +define exported symbol OSC32K_Cmd = 0x25f9; +define exported symbol OSC8M_Get = 0x2631; +define exported symbol rtl_cryptoEngine_SrcDesc_Show = 0x2641; +define exported symbol rtl_cryptoEngine_info = 0x27f1; +define exported symbol rtl_cryptoEngine_init = 0x2949; +define exported symbol rtl_crypto_md5_init = 0x2975; +define exported symbol rtl_crypto_md5_process = 0x29b1; +define exported symbol rtl_crypto_md5 = 0x2a09; +define exported symbol rtl_crypto_sha1_init = 0x2a2d; +define exported symbol rtl_crypto_sha1_process = 0x2a69; +define exported symbol rtl_crypto_sha1 = 0x2a9d; +define exported symbol rtl_crypto_sha2_init = 0x2ac1; +define exported symbol rtl_crypto_sha2_process = 0x2b15; +define exported symbol rtl_crypto_sha2 = 0x2b4d; +define exported symbol rtl_crypto_hmac_md5_init = 0x2b71; +define exported symbol rtl_crypto_hmac_md5_process = 0x2bd1; +define exported symbol rtl_crypto_hmac_md5 = 0x2c0d; +define exported symbol rtl_crypto_hmac_sha1_init = 0x2c31; +define exported symbol rtl_crypto_hmac_sha1_process = 0x2c91; +define exported symbol rtl_crypto_hmac_sha1 = 0x2cc9; +define exported symbol rtl_crypto_hmac_sha2_init = 0x2ced; +define exported symbol rtl_crypto_hmac_sha2_process = 0x2d65; +define exported symbol rtl_crypto_hmac_sha2 = 0x2da1; +define exported symbol rtl_crypto_aes_cbc_init = 0x2dc5; +define exported symbol rtl_crypto_aes_cbc_encrypt = 0x2dfd; +define exported symbol rtl_crypto_aes_cbc_decrypt = 0x2e45; +define exported symbol rtl_crypto_aes_ecb_init = 0x2e8d; +define exported symbol rtl_crypto_aes_ecb_encrypt = 0x2ec5; +define exported symbol rtl_crypto_aes_ecb_decrypt = 0x2ef5; +define exported symbol rtl_crypto_aes_ctr_init = 0x2f25; +define exported symbol rtl_crypto_aes_ctr_encrypt = 0x2f5d; +define exported symbol rtl_crypto_aes_ctr_decrypt = 0x2f99; +define exported symbol rtl_crypto_3des_cbc_init = 0x2fd5; +define exported symbol rtl_crypto_3des_cbc_encrypt = 0x300d; +define exported symbol rtl_crypto_3des_cbc_decrypt = 0x3055; +define exported symbol rtl_crypto_3des_ecb_init = 0x309d; +define exported symbol rtl_crypto_3des_ecb_encrypt = 0x30d5; +define exported symbol rtl_crypto_3des_ecb_decrypt = 0x311d; +define exported symbol rtl_crypto_des_cbc_init = 0x3165; +define exported symbol rtl_crypto_des_cbc_encrypt = 0x319d; +define exported symbol rtl_crypto_des_cbc_decrypt = 0x31f5; +define exported symbol rtl_crypto_des_ecb_init = 0x324d; +define exported symbol rtl_crypto_des_ecb_encrypt = 0x3285; +define exported symbol rtl_crypto_des_ecb_decrypt = 0x32dd; +define exported symbol SYSTIMER_Init = 0x3335; +define exported symbol SYSTIMER_TickGet = 0x33a1; +define exported symbol SYSTIMER_GetPassTime = 0x33c1; +define exported symbol DelayNop = 0x3401; +define exported symbol DelayUs = 0x3411; +define exported symbol DelayMs = 0x346d; +define exported symbol USOC_DongleSpecialCmd = 0x3481; +define exported symbol USOC_DongleCmd = 0x35d9; +define exported symbol USOC_DongleIsr = 0x35f9; +define exported symbol USOC_SIE_INTConfig = 0x3621; +define exported symbol USOC_SIE_INTClear = 0x3639; +define exported symbol USOC_PHY_Write = 0x3645; +define exported symbol USOC_PHY_Read = 0x3679; +define exported symbol USOC_PHY_Autoload = 0x36c1; +define exported symbol USOC_DongleInit = 0x37a5; +define exported symbol EFUSE_USER_Read = 0x386d; +define exported symbol EFUSE_USER1_Read = 0x3971; +define exported symbol EFUSE_USER2_Read = 0x397d; +define exported symbol EFUSE_USER3_Read = 0x3989; +define exported symbol EFUSE_RemainLength = 0x3995; +define exported symbol EFUSE_USER_Write = 0x3a21; +define exported symbol EFUSE_USER1_Write = 0x3bb1; +define exported symbol EFUSE_USER2_Write = 0x3bc1; +define exported symbol EFUSE_USER3_Write = 0x3bd1; +define exported symbol EFUSE_OTP_Read1B = 0x3be1; +define exported symbol EFUSE_OTP_Write1B = 0x3c01; +define exported symbol EFUSE_OTP_Read32B = 0x3c21; +define exported symbol EFUSE_OTP_Write32B = 0x3c4d; +define exported symbol EFUSE_RDP_EN = 0x3cad; +define exported symbol EFUSE_RDP_KEY = 0x3ccd; +define exported symbol EFUSE_OTF_KEY = 0x3cf9; +define exported symbol EFUSE_JTAG_OFF = 0x3d25; +define exported symbol PAD_DrvStrength = 0x3d45; +define exported symbol PAD_PullCtrl = 0x3d75; +define exported symbol Pinmux_Config = 0x3dc5; +define exported symbol Pinmux_ConfigGet = 0x3dfd; +define exported symbol Pinmux_Deinit = 0x3e19; +define exported symbol PINMUX_UART0_Ctrl = 0x3e39; +define exported symbol PINMUX_UART1_Ctrl = 0x3e81; +define exported symbol PINMUX_UARTLOG_Ctrl = 0x3ea9; +define exported symbol PINMUX_SPI0_Ctrl = 0x3ef9; +define exported symbol PINMUX_SPI1_Ctrl = 0x3f8d; +define exported symbol PINMUX_SPIF_Ctrl = 0x400d; +define exported symbol PINMUX_I2C0_Ctrl = 0x406d; +define exported symbol PINMUX_I2C1_Ctrl = 0x40e1; +define exported symbol PINMUX_SDIOD_Ctrl = 0x4151; +define exported symbol PINMUX_I2S0_Ctrl = 0x41e5; +define exported symbol PINMUX_SWD_Ctrl = 0x4265; +define exported symbol PINMUX_SWD_OFF = 0x42b5; +define exported symbol PINMUX_SWD_REG = 0x42d9; +define exported symbol PINMUX_Ctrl = 0x42fd; +define exported symbol SOCPS_BackupCPUClk = 0x4391; +define exported symbol SOCPS_RestoreCPUClk = 0x43b1; +define exported symbol SOCPS_BootFromPS = 0x43d1; +define exported symbol SOCPS_TrapPin = 0x43f1; +define exported symbol SOCPS_ANACKSel = 0x4411; +define exported symbol SOCPS_CLKCal = 0x442d; +define exported symbol SOCPS_SetWakeEvent = 0x4485; +define exported symbol SOCPS_ClearWakeEvent = 0x449d; +define exported symbol SOCPS_WakePinsCtrl = 0x44a9; +define exported symbol SOCPS_WakePinCtrl = 0x44d9; +define exported symbol SOCPS_WakePinClear = 0x4529; +define exported symbol SOCPS_GetANATimerParam = 0x4539; +define exported symbol SOCPS_SetANATimer = 0x4575; +define exported symbol SOCPS_SetReguWakepin = 0x45dd; +define exported symbol SOCPS_SetReguTimer = 0x4605; +define exported symbol SOCPS_PWROption = 0x46d9; +define exported symbol SOCPS_PWROptionExt = 0x46e5; +define exported symbol SOCPS_PWRMode = 0x46f9; +define exported symbol SOCPS_SNZMode = 0x4721; +define exported symbol SOCPS_DeepStandby = 0x473d; +define exported symbol SOCPS_DeepSleep = 0x4791; +define exported symbol SDIO_StructInit = 0x47d5; +define exported symbol SDIO_Init = 0x47f1; +define exported symbol SDIO_INTClear = 0x486d; +define exported symbol SDIO_INTConfig = 0x487d; +define exported symbol SDIO_RPWM1_Get = 0x4895; +define exported symbol SDIO_RPWM2_Get = 0x48a1; +define exported symbol SDIO_CPWM1_Set = 0x48ad; +define exported symbol SDIO_CPWM2_Set = 0x48c1; +define exported symbol SDIO_RXBD_RPTR_Get = 0x48dd; +define exported symbol SDIO_RXBD_WPTR_Set = 0x48e9; +define exported symbol SDIO_TXBD_WPTR_Get = 0x48f5; +define exported symbol SDIO_TXBD_RPTR_Set = 0x4901; +define exported symbol SDIO_DMA_Reset = 0x490d; +define exported symbol BOOT_ROM_Simulation = 0x4919; +define exported symbol USOC_BOOT_TXBD_Proc = 0x491d; +define exported symbol USOC_BOOT_Init = 0x4a3d; +define exported symbol USB_Boot_ROM = 0x4aa9; +define exported symbol USOC_CH_Cmd = 0x4b59; +define exported symbol USOC_Cmd = 0x4bb1; +define exported symbol USOC_PHY_Cmd = 0x4bf5; +define exported symbol USOC_MODE_Cfg = 0x4c09; +define exported symbol USOC_TXBD_SWIDX_Cfg = 0x4c25; +define exported symbol USOC_TXBD_SWIDX_Get = 0x4c2d; +define exported symbol USOC_TXBD_HWIDX_Get = 0x4c35; +define exported symbol USOC_RXBD_HWIDX_Get = 0x4c3d; +define exported symbol USOC_RXBD_SWIDX_Cfg = 0x4c45; +define exported symbol USOC_RXBD_SWIDX_Get = 0x4c4d; +define exported symbol USOC_StructInit = 0x4c55; +define exported symbol USOC_Init = 0x4c85; +define exported symbol USOC_SW_RST = 0x4d7d; +define exported symbol USOC_INTCfg = 0x4d91; +define exported symbol USOC_INTClr = 0x4d95; +define exported symbol USOC_INTGet = 0x4d9d; +define exported symbol USOC_MIT_Cfg = 0x4da1; +define exported symbol USOC_TXSTUCK_Cfg = 0x4dc5; +define exported symbol USOC_RXSTUCK_Cfg = 0x4de9; +define exported symbol USOC_POWER_On = 0x4e0d; +define exported symbol ADC_RXGDMA_Init = 0x4e9d; +define exported symbol ADC_SetAudio = 0x4f45; +define exported symbol ADC_SetAnalog = 0x4f61; +define exported symbol ADC_Cmd = 0x4fbd; +define exported symbol ADC_INTConfig = 0x5031; +define exported symbol ADC_SetOneShot = 0x5049; +define exported symbol ADC_SetComp = 0x50fd; +define exported symbol ADC_INTClear = 0x517d; +define exported symbol ADC_INTClearPendingBits = 0x5189; +define exported symbol ADC_GetISR = 0x5195; +define exported symbol ADC_Read = 0x51a1; +define exported symbol ADC_ReceiveBuf = 0x51ad; +define exported symbol ADC_InitStruct = 0x5205; +define exported symbol ADC_Init = 0x524d; +define exported symbol BOOT_ROM_ShowBuildInfo = 0x52ed; +define exported symbol BOOT_ROM_OTFCheck = 0x5335; +define exported symbol BOOT_ROM_InitFlash = 0x5345; +define exported symbol BOOT_ROM_FromFlash = 0x5405; +define exported symbol BOOT_ROM_InitUsb = 0x5511; +define exported symbol BOOT_ROM_Process = 0x553d; +define exported symbol BOOT_ROM_InitDebugFlg = 0x5605; +define exported symbol HalResetVsr = 0x5639; +define exported symbol Cache_Enable = 0x5811; +define exported symbol Cache_Flush = 0x5831; +define exported symbol Cache_Debug = 0x5851; +define exported symbol CRYPTO_AlignToBe32 = 0x58bd; +define exported symbol CRYPTO_MemDump = 0x58d5; +define exported symbol CRYPTO_GetAESKey = 0x599d; +define exported symbol CRYPTO_SetAESKey = 0x5cb5; +define exported symbol CRYPTO_SetSecurityMode = 0x5d29; +define exported symbol CRYPTO_Init = 0x5f5d; +define exported symbol CRYPTO_DeInit = 0x60b9; +define exported symbol CRYPTO_Reset = 0x6101; +define exported symbol CRYPTO_Process = 0x6129; +define exported symbol CRYPTO_CipherInit = 0x6a11; +define exported symbol CRYPTO_CipherEncrypt = 0x6a35; +define exported symbol CRYPTO_CipherDecrypt = 0x6a61; +define exported symbol CRYPTO_SetCheckSumEn = 0x6a95; +define exported symbol CRYPTO_GetCheckSumData = 0x6ab1; +define exported symbol LOGUART_StructInit = 0x6abd; +define exported symbol LOGUART_Init = 0x6ad5; +define exported symbol LOGUART_PutChar = 0x6b15; +define exported symbol LOGUART_GetChar = 0x6b49; +define exported symbol LOGUART_GetIMR = 0x6b65; +define exported symbol LOGUART_SetIMR = 0x6b71; +define exported symbol LOGUART_WaitBusy = 0x6b7d; +define exported symbol DIAG_UartInit = 0x6b9d; +define exported symbol DIAG_UartReInit = 0x6c25; +define exported symbol EFUSE_PowerSwitchROM = 0x6c49; +define exported symbol EFUSE_OneByteReadROM = 0x6d65; +define exported symbol EFUSE_OneByteWriteROM = 0x6e0d; +define exported symbol EFUSE_PG_Packet = 0x6e29; +define exported symbol EFUSE_LogicalMap_Read = 0x7091; +define exported symbol EFUSE_LogicalMap_Write = 0x71f5; +define exported symbol FLASH_SetSpiMode = 0x73dd; +define exported symbol FLASH_RxCmd = 0x7465; +define exported symbol FLASH_WaitBusy = 0x74cd; +define exported symbol FLASH_RxData = 0x754d; +define exported symbol FLASH_TxCmd = 0x75cd; +define exported symbol FLASH_WriteEn = 0x763d; +define exported symbol FLASH_TxData12B = 0x7661; +define exported symbol FLASH_SetStatus = 0x7735; +define exported symbol FLASH_Erase = 0x7755; +define exported symbol FLASH_DeepPowerDown = 0x77f5; +define exported symbol FLASH_SetStatusBits = 0x784d; +define exported symbol FLASH_Calibration = 0x791d; +define exported symbol FLASH_StructInit_Micron = 0x7a65; +define exported symbol FLASH_StructInit_MXIC = 0x7af5; +define exported symbol FLASH_StructInit_GD = 0x7b81; +define exported symbol FLASH_StructInit = 0x7c11; +define exported symbol FLASH_Init = 0x7ca1; +define exported symbol FLASH_ClockDiv = 0x7d15; +define exported symbol FLASH_CalibrationInit = 0x7d99; +define exported symbol FLASH_Calibration500MPSCmd = 0x7db1; +define exported symbol FLASH_CalibrationPhase = 0x7dcd; +define exported symbol FLASH_CalibrationPhaseIdx = 0x7e59; +define exported symbol FLASH_CalibrationNewCmd = 0x7e6d; +define exported symbol FLASH_CalibrationNew = 0x7ea9; +define exported symbol GDMA_StructInit = 0x80dd; +define exported symbol GDMA_SetLLP = 0x80f9; +define exported symbol GDMA_ClearINTPendingBit = 0x8191; +define exported symbol GDMA_ClearINT = 0x81d5; +define exported symbol GDMA_INTConfig = 0x8211; +define exported symbol GDMA_Cmd = 0x8259; +define exported symbol GDMA_Init = 0x828d; +define exported symbol GDMA_ChCleanAutoReload = 0x83c1; +define exported symbol GDMA_SetSrcAddr = 0x83f9; +define exported symbol GDMA_GetSrcAddr = 0x8411; +define exported symbol GDMA_GetDstAddr = 0x8429; +define exported symbol GDMA_SetDstAddr = 0x843d; +define exported symbol GDMA_SetBlkSize = 0x8459; +define exported symbol GDMA_GetBlkSize = 0x8489; +define exported symbol GDMA_ChnlRegister = 0x84a1; +define exported symbol GDMA_ChnlUnRegister = 0x8529; +define exported symbol GDMA_ChnlAlloc = 0x8591; +define exported symbol GDMA_ChnlFree = 0x8615; +define exported symbol GPIO_INTMode = 0x864d; +define exported symbol GPIO_INTConfig = 0x86e5; +define exported symbol GPIO_INTHandler = 0x8725; +define exported symbol GPIO_Direction = 0x8771; +define exported symbol GPIO_Init = 0x87a1; +define exported symbol GPIO_DeInit = 0x886d; +define exported symbol GPIO_ReadDataBit = 0x88c9; +define exported symbol GPIO_WriteBit = 0x88ed; +define exported symbol GPIO_PortDirection = 0x891d; +define exported symbol GPIO_PortRead = 0x893d; +define exported symbol GPIO_PortWrite = 0x894d; +define exported symbol GPIO_UserRegIrq = 0x8969; +define exported symbol I2C_StructInit = 0x899d; +define exported symbol I2C_SetSpeed = 0x89e5; +define exported symbol I2C_SetSlaveAddress = 0x8b3d; +define exported symbol I2C_CheckFlagState = 0x8b79; +define exported symbol I2C_INTConfig = 0x8bad; +define exported symbol I2C_ClearINT = 0x8be5; +define exported symbol I2C_ClearAllINT = 0x8c85; +define exported symbol I2C_Init = 0x8cad; +define exported symbol I2C_GetRawINT = 0x8dc9; +define exported symbol I2C_GetINT = 0x8df1; +define exported symbol I2C_MasterSendNullData = 0x8e19; +define exported symbol I2C_MasterSend = 0x8e65; +define exported symbol I2C_SlaveSend = 0x8ead; +define exported symbol I2C_ReceiveData = 0x8ed9; +define exported symbol I2C_MasterWrite = 0x8f05; +define exported symbol I2C_MasterReadDW = 0x8f89; +define exported symbol I2C_MasterRead = 0x9019; +define exported symbol I2C_SlaveWrite = 0x9089; +define exported symbol I2C_SlaveRead = 0x90f1; +define exported symbol I2C_MasterRepeatRead = 0x9141; +define exported symbol I2C_Cmd = 0x91c1; +define exported symbol I2C_PinMuxInit = 0x91fd; +define exported symbol I2C_PinMuxDeInit = 0x9255; +define exported symbol I2C_DMAControl = 0x92ad; +define exported symbol I2C_DmaMode1Config = 0x92e9; +define exported symbol I2C_DmaMode2Config = 0x9331; +define exported symbol I2C_TXGDMA_Init = 0x9375; +define exported symbol I2C_RXGDMA_Init = 0x9459; +define exported symbol I2C_Sleep_Cmd = 0x9521; +define exported symbol I2C_WakeUp = 0x95a1; +define exported symbol I2S_StructInit = 0x95e9; +define exported symbol I2S_Cmd = 0x9611; +define exported symbol I2S_TxDmaCmd = 0x962d; +define exported symbol I2S_RxDmaCmd = 0x9641; +define exported symbol I2S_INTConfig = 0x9655; +define exported symbol I2S_INTClear = 0x965d; +define exported symbol I2S_INTClearAll = 0x9665; +define exported symbol I2S_Init = 0x9671; +define exported symbol I2S_ISRGet = 0x97a9; +define exported symbol I2S_SetRate = 0x97b5; +define exported symbol I2S_SetWordLen = 0x9811; +define exported symbol I2S_SetChNum = 0x9839; +define exported symbol I2S_SetPageNum = 0x9861; +define exported symbol I2S_SetPageSize = 0x9895; +define exported symbol I2S_GetPageSize = 0x98a9; +define exported symbol I2S_SetDirection = 0x98b5; +define exported symbol I2S_SetDMABuf = 0x98dd; +define exported symbol I2S_TxPageBusy = 0x9905; +define exported symbol I2S_GetTxPage = 0x9911; +define exported symbol I2S_GetRxPage = 0x991d; +define exported symbol I2S_SetTxPageAddr = 0x9929; +define exported symbol I2S_GetTxPageAddr = 0x9939; +define exported symbol I2S_SetRxPageAddr = 0x9949; +define exported symbol I2S_GetRxPageAddr = 0x9959; +define exported symbol I2S_TxPageDMA_EN = 0x9969; +define exported symbol I2S_RxPageDMA_EN = 0x998d; +define exported symbol io_assert_failed = 0x99d9; +define exported symbol OTF_init = 0x99fd; +define exported symbol OTF_Cmd = 0x9a79; +define exported symbol OTF_Mask = 0x9a8d; +define exported symbol KEY_Request = 0x9add; +define exported symbol RDP_EN_Request = 0x9b21; +define exported symbol RCC_PeriphClockCmd = 0x9b65; +define exported symbol FUNC_HCI_COM = 0x9c95; +define exported symbol RTC_ByteToBcd2 = 0x9cad; +define exported symbol RTC_Bcd2ToByte = 0x9cc9; +define exported symbol RTC_ClokSource = 0x9cdd; +define exported symbol RTC_EnterInitMode = 0x9d19; +define exported symbol RTC_ExitInitMode = 0x9d51; +define exported symbol RTC_WaitForSynchro = 0x9d61; +define exported symbol RTC_BypassShadowCmd = 0x9da9; +define exported symbol RTC_StructInit = 0x9dd9; +define exported symbol RTC_Init = 0x9de5; +define exported symbol RTC_TimeStructInit = 0x9e7d; +define exported symbol RTC_SetTime = 0x9e8d; +define exported symbol RTC_GetTime = 0x9ff9; +define exported symbol RTC_SetAlarm = 0xa051; +define exported symbol RTC_AlarmStructInit = 0xa211; +define exported symbol RTC_GetAlarm = 0xa231; +define exported symbol RTC_AlarmCmd = 0xa2a1; +define exported symbol RTC_AlarmClear = 0xa2f5; +define exported symbol RTC_DayLightSavingConfig = 0xa305; +define exported symbol RTC_GetStoreOperation = 0xa355; +define exported symbol RTC_OutputConfig = 0xa365; +define exported symbol RTC_SmoothCalibConfig = 0xa39d; +define exported symbol SDIO_IsTimeout = 0xa459; +define exported symbol SDIOB_Init = 0xa481; +define exported symbol SDIOB_INTConfig = 0xa575; +define exported symbol SDIOB_DeInit = 0xa591; +define exported symbol SDIOB_H2C_WriteMem = 0xa5d9; +define exported symbol SDIOB_H2C_SetMem = 0xa605; +define exported symbol SDIOB_H2C_DataHandle = 0xa631; +define exported symbol SDIOB_H2C_DataReady = 0xa73d; +define exported symbol SDIOB_IRQ_Handler_BH = 0xa80d; +define exported symbol SDIOB_H2C_Task = 0xa8c9; +define exported symbol SDIO_Boot_Up = 0xa8e5; +define exported symbol SPI_DmaInit = 0xa91d; +define exported symbol SPI_DataHandle = 0xa9d1; +define exported symbol SPI_Boot_DmaRxIrqHandle = 0xaa01; +define exported symbol SPI_Boot_ROM = 0xaa5d; +define exported symbol SSI_StructInit = 0xabbd; +define exported symbol SSI_Cmd = 0xabf5; +define exported symbol SSI_INTConfig = 0xac09; +define exported symbol SSI_SetSclkPolarity = 0xac19; +define exported symbol SSI_SetSclkPhase = 0xac3d; +define exported symbol SSI_SetDataFrameSize = 0xac61; +define exported symbol SSI_SetReadLen = 0xac81; +define exported symbol SSI_SetBaudDiv = 0xacb1; +define exported symbol SSI_SetBaud = 0xaccd; +define exported symbol SSI_SetDmaEnable = 0xad2d; +define exported symbol SSI_SetDmaLevel = 0xad41; +define exported symbol SSI_SetIsrClean = 0xad49; +define exported symbol SSI_WriteData = 0xad65; +define exported symbol SSI_SetRxFifoLevel = 0xad6d; +define exported symbol SSI_SetTxFifoLevel = 0xad71; +define exported symbol SSI_ReadData = 0xad75; +define exported symbol SSI_GetRxCount = 0xad79; +define exported symbol SSI_GetTxCount = 0xad81; +define exported symbol SSI_GetStatus = 0xad89; +define exported symbol SSI_Writeable = 0xad8d; +define exported symbol SSI_Readable = 0xad9d; +define exported symbol SSI_GetDataFrameSize = 0xadad; +define exported symbol SSI_TXGDMA_Init = 0xadb9; +define exported symbol SSI_RXGDMA_Init = 0xaef9; +define exported symbol SSI_ReceiveData = 0xb021; +define exported symbol SSI_SendData = 0xb0b9; +define exported symbol SSI_Busy = 0xb165; +define exported symbol SSI_SetSlaveEnable = 0xb175; +define exported symbol SSI_Init = 0xb1ad; +define exported symbol SSI_GetIsr = 0xb235; +define exported symbol SSI_GetRawIsr = 0xb239; +define exported symbol SSI_GetSlaveEnable = 0xb23d; +define exported symbol SSI_PinmuxInit = 0xb241; +define exported symbol SSI_PinmuxDeInit = 0xb2a9; +define exported symbol SYSCFG0_Get = 0xb311; +define exported symbol SYSCFG0_CUTVersion = 0xb31d; +define exported symbol SYSCFG0_BDOption = 0xb32d; +define exported symbol SYSCFG1_Get = 0xb33d; +define exported symbol SYSCFG1_AutoLoadDone = 0xb349; +define exported symbol SYSCFG1_TRP_LDOMode = 0xb359; +define exported symbol SYSCFG1_TRP_UARTImage = 0xb369; +define exported symbol SYSCFG1_TRP_ICFG = 0xb37d; +define exported symbol SYSCFG2_Get = 0xb389; +define exported symbol SYSCFG2_ROMINFO_Get = 0xb395; +define exported symbol SYSCFG2_ROMINFO_Set = 0xb3a1; +define exported symbol RTIM_TimeBaseStructInit = 0xb3b5; +define exported symbol RTIM_Cmd = 0xb3cd; +define exported symbol RTIM_GetCount = 0xb42d; +define exported symbol RTIM_UpdateDisableConfig = 0xb475; +define exported symbol RTIM_ARRPreloadConfig = 0xb4c5; +define exported symbol RTIM_UpdateRequestConfig = 0xb515; +define exported symbol RTIM_PrescalerConfig = 0xb575; +define exported symbol RTIM_GenerateEvent = 0xb5a1; +define exported symbol RTIM_ChangePeriod = 0xb5f9; +define exported symbol RTIM_Reset = 0xb64d; +define exported symbol RTIM_CCStructInit = 0xb68d; +define exported symbol RTIM_CCxInit = 0xb6a1; +define exported symbol RTIM_CCRxMode = 0xb749; +define exported symbol RTIM_CCRxSet = 0xb785; +define exported symbol RTIM_CCRxGet = 0xb7dd; +define exported symbol RTIM_OCxPreloadConfig = 0xb80d; +define exported symbol RTIM_CCxPolarityConfig = 0xb85d; +define exported symbol RTIM_CCxCmd = 0xb8ad; +define exported symbol RTIM_SetOnePulseOutputMode = 0xb901; +define exported symbol RTIM_DMACmd = 0xb959; +define exported symbol RTIM_TXGDMA_Init = 0xb9a9; +define exported symbol RTIM_RXGDMA_Init = 0xba5d; +define exported symbol RTIM_INTConfig = 0xbb3d; +define exported symbol RTIM_INTClear = 0xbba9; +define exported symbol RTIM_TimeBaseInit = 0xbbed; +define exported symbol RTIM_DeInit = 0xbced; +define exported symbol RTIM_INTClearPendingBit = 0xbd41; +define exported symbol RTIM_GetFlagStatus = 0xbd81; +define exported symbol RTIM_GetINTStatus = 0xbded; +define exported symbol UART_DeInit = 0xbe61; +define exported symbol UART_StructInit = 0xbe69; +define exported symbol UART_BaudParaGet = 0xbe81; +define exported symbol UART_BaudParaGetFull = 0xbec9; +define exported symbol UART_SetBaud = 0xbf01; +define exported symbol UART_SetBaudExt = 0xbf71; +define exported symbol UART_SetRxLevel = 0xbfc1; +define exported symbol UART_RxCmd = 0xbfe9; +define exported symbol UART_Writable = 0xbffd; +define exported symbol UART_Readable = 0xc005; +define exported symbol UART_CharPut = 0xc00d; +define exported symbol UART_CharGet = 0xc011; +define exported symbol UART_ReceiveData = 0xc019; +define exported symbol UART_SendData = 0xc041; +define exported symbol UART_ReceiveDataTO = 0xc069; +define exported symbol UART_SendDataTO = 0xc0a9; +define exported symbol UART_RxByteCntClear = 0xc0e9; +define exported symbol UART_RxByteCntGet = 0xc0f5; +define exported symbol UART_BreakCtl = 0xc0fd; +define exported symbol UART_ClearRxFifo = 0xc111; +define exported symbol UART_Init = 0xc135; +define exported symbol UART_ClearTxFifo = 0xc1d1; +define exported symbol UART_INTConfig = 0xc1dd; +define exported symbol UART_IntStatus = 0xc1ed; +define exported symbol UART_ModemStatusGet = 0xc1f1; +define exported symbol UART_LineStatusGet = 0xc1f5; +define exported symbol UART_WaitBusy = 0xc1f9; +define exported symbol UART_PinMuxInit = 0xc221; +define exported symbol UART_PinMuxDeinit = 0xc289; +define exported symbol UART_TXDMAConfig = 0xc2f1; +define exported symbol UART_RXDMAConfig = 0xc301; +define exported symbol UART_TXDMACmd = 0xc315; +define exported symbol UART_RXDMACmd = 0xc329; +define exported symbol UART_TXGDMA_Init = 0xc33d; +define exported symbol UART_RXGDMA_Init = 0xc425; +define exported symbol UART_LPRxStructInit = 0xc501; +define exported symbol UART_LPRxInit = 0xc50d; +define exported symbol UART_LPRxBaudSet = 0xc575; +define exported symbol UART_LPRxMonitorCmd = 0xc5f1; +define exported symbol UART_LPRxpathSet = 0xc62d; +define exported symbol UART_LPRxIPClockSet = 0xc641; +define exported symbol UART_LPRxCmd = 0xc6b1; +define exported symbol UART_LPRxMonBaudCtrlRegGet = 0xc6c5; +define exported symbol UART_LPRxMonitorSatusGet = 0xc6c9; +define exported symbol UART_IrDAStructInit = 0xc6cd; +define exported symbol UART_IrDAInit = 0xc6e5; +define exported symbol UART_IrDACmd = 0xc7bd; +define exported symbol INT_SysOn = 0xc7d1; +define exported symbol INT_Wdg = 0xc811; +define exported symbol INT_Timer0 = 0xc855; +define exported symbol INT_Timer1 = 0xc899; +define exported symbol INT_Timer2 = 0xc8dd; +define exported symbol INT_Timer3 = 0xc921; +define exported symbol INT_SPI0 = 0xc965; +define exported symbol INT_GPIO = 0xc9a9; +define exported symbol INT_Uart0 = 0xc9ed; +define exported symbol INT_SPIFlash = 0xca31; +define exported symbol INT_Uart1 = 0xca75; +define exported symbol INT_Timer4 = 0xcab9; +define exported symbol INT_I2S0 = 0xcafd; +define exported symbol INT_Timer5 = 0xcb41; +define exported symbol INT_WlDma = 0xcb85; +define exported symbol INT_WlProtocol = 0xcbc9; +define exported symbol INT_IPSEC = 0xcc0d; +define exported symbol INT_SPI1 = 0xcc51; +define exported symbol INT_Peripheral = 0xcc95; +define exported symbol INT_Gdma0Ch0 = 0xccd9; +define exported symbol INT_Gdma0Ch1 = 0xcd1d; +define exported symbol INT_Gdma0Ch2 = 0xcd61; +define exported symbol INT_Gdma0Ch3 = 0xcda5; +define exported symbol INT_Gdma0Ch4 = 0xcde9; +define exported symbol INT_Gdma0Ch5 = 0xce2d; +define exported symbol INT_I2C0 = 0xce71; +define exported symbol INT_I2C1 = 0xceb5; +define exported symbol INT_Uartlog = 0xcef9; +define exported symbol INT_ADC = 0xcf3d; +define exported symbol INT_RDP = 0xcf81; +define exported symbol INT_RTC = 0xcfc5; +define exported symbol INT_Gdma1Ch0 = 0xd009; +define exported symbol INT_Gdma1Ch1 = 0xd051; +define exported symbol INT_Gdma1Ch2 = 0xd099; +define exported symbol INT_Gdma1Ch3 = 0xd0e1; +define exported symbol INT_Gdma1Ch4 = 0xd129; +define exported symbol INT_Gdma1Ch5 = 0xd171; +define exported symbol INT_USB = 0xd1b9; +define exported symbol INT_RXI300 = 0xd201; +define exported symbol INT_USB_SIE = 0xd249; +define exported symbol INT_SdioD = 0xd291; +define exported symbol INT_NMI = 0xd2d1; +define exported symbol INT_HardFault = 0xd305; +define exported symbol INT_MemManage = 0xd4b5; +define exported symbol INT_BusFault = 0xd4d5; +define exported symbol INT_UsageFault = 0xd4f5; +define exported symbol VECTOR_TableInit = 0xd515; +define exported symbol VECTOR_TableInitForOS = 0xd6c5; +define exported symbol VECTOR_IrqRegister = 0xd6d5; +define exported symbol VECTOR_IrqUnRegister = 0xd6f9; +define exported symbol VECTOR_IrqEn = 0xd715; +define exported symbol VECTOR_IrqDis = 0xd765; +define exported symbol WDG_Scalar = 0xd7a1; +define exported symbol WDG_Init = 0xd7e1; +define exported symbol WDG_IrqClear = 0xd7fd; +define exported symbol WDG_IrqInit = 0xd80d; +define exported symbol WDG_Cmd = 0xd83d; +define exported symbol WDG_Refresh = 0xd85d; +define exported symbol _strncpy = 0xd86d; +define exported symbol _strcpy = 0xd889; +define exported symbol prvStrCpy = 0xd899; +define exported symbol _strlen = 0xd8b1; +define exported symbol _strnlen = 0xd8c9; +define exported symbol prvStrLen = 0xd8fd; +define exported symbol _strcmp = 0xd919; +define exported symbol _strncmp = 0xd939; +define exported symbol prvStrCmp = 0xd985; +define exported symbol StrUpr = 0xd9b5; +define exported symbol prvAtoi = 0xd9d1; +define exported symbol prvStrtok = 0xda29; +define exported symbol prvStrStr = 0xda81; +define exported symbol _strsep = 0xdab9; +define exported symbol skip_spaces = 0xdaf5; +define exported symbol skip_atoi = 0xdb11; +define exported symbol _parse_integer_fixup_radix = 0xdb49; +define exported symbol _parse_integer = 0xdb9d; +define exported symbol simple_strtoull = 0xdc01; +define exported symbol simple_strtoll = 0xdc21; +define exported symbol simple_strtoul = 0xdc41; +define exported symbol simple_strtol = 0xdc49; +define exported symbol _vsscanf = 0xdc61; +define exported symbol _sscanf = 0xe1c9; +define exported symbol div_u64 = 0xe1e5; +define exported symbol div_s64 = 0xe1ed; +define exported symbol div_u64_rem = 0xe1f5; +define exported symbol div_s64_rem = 0xe205; +define exported symbol _strpbrk = 0xe215; +define exported symbol _strchr = 0xe241; +define exported symbol COMMPORT_GET_T = 0xe259; +define exported symbol COMMPORT_CLEAN_RX = 0xe289; +define exported symbol xModemDebugInit = 0xe2a5; +define exported symbol xModemDebug = 0xe2dd; +define exported symbol xModemInquiry = 0xe315; +define exported symbol xModemGetFirst = 0xe339; +define exported symbol xModemGetOthers = 0xe45d; +define exported symbol xModemRxFrame = 0xe691; +define exported symbol xModemHandshake = 0xe6d5; +define exported symbol xModemRxBuffer = 0xe945; +define exported symbol xmodem_log_close = 0xe9f5; +define exported symbol xmodem_log_open = 0xea01; +define exported symbol xmodem_uart_init = 0xea39; +define exported symbol xmodem_uart_deinit = 0xeb25; +define exported symbol xmodem_uart_port_init = 0xeb35; +define exported symbol xmodem_uart_port_deinit = 0xeb99; +define exported symbol xmodem_uart_readable = 0xebdd; +define exported symbol xmodem_uart_writable = 0xebf5; +define exported symbol xmodem_uart_getc = 0xec0d; +define exported symbol xmodem_uart_putc = 0xec35; +define exported symbol xmodem_uart_putdata = 0xec49; +define exported symbol aes_set_key = 0xec65; +define exported symbol aes_encrypt = 0xf021; +define exported symbol aes_decrypt = 0x10171; +define exported symbol AES_WRAP = 0x112b1; +define exported symbol AES_UnWRAP = 0x113fd; +define exported symbol crc32_get = 0x11549; +define exported symbol arc4_byte = 0x1157d; +define exported symbol rt_arc4_init = 0x115a5; +define exported symbol rt_arc4_crypt = 0x115e9; +define exported symbol rt_md5_init = 0x11df5; +define exported symbol rt_md5_append = 0x11e25; +define exported symbol rt_md5_final = 0x11ec9; +define exported symbol rt_md5_hmac = 0x11f21; +define exported symbol RC4 = 0x12061; +define exported symbol RC4_set_key = 0x1238d; +define exported symbol ROM_WIFI_ReadPowerValue = 0x1246d; +define exported symbol ROM_WIFI_EfuseParseTxPowerInfo = 0x1251d; +define exported symbol ROM_WIFI_8051Reset = 0x125c5; +define exported symbol ROM_WIFI_FWDownloadEnable = 0x125dd; +define exported symbol ROM_WIFI_BlockWrite = 0x12619; +define exported symbol ROM_WIFI_PageWrite = 0x12661; +define exported symbol ROM_WIFI_FillDummy = 0x12685; +define exported symbol ROM_WIFI_WriteFW = 0x126b1; +define exported symbol ROM_WIFI_FWFreeToGo = 0x1275d; +define exported symbol ROM_WIFI_InitLLTTable = 0x127f9; +define exported symbol ROM_WIFI_GetChnlGroup = 0x12879; +define exported symbol ROM_WIFI_BWMapping = 0x129f1; +define exported symbol ROM_WIFI_SCMapping = 0x12a19; +define exported symbol ROM_WIFI_FillTxdescSectype = 0x12a99; +define exported symbol ROM_WIFI_FillFakeTxdesc = 0x12ab9; +define exported symbol ROM_WIFI_32K_Cmd = 0x12b91; +define exported symbol ROM_WIFI_DISCONNECT = 0x12bc1; +define exported symbol ROM_WIFI_SET_TSF = 0x12bfd; +define exported symbol ROM_WIFI_BCN_FUNC = 0x12ca5; +define exported symbol ROM_WIFI_BSSID_SET = 0x12ccd; +define exported symbol ROM_WIFI_MACADDR_SET = 0x12d09; +define exported symbol ROM_WIFI_EnableInterrupt = 0x12d39; +define exported symbol ROM_WIFI_DisableInterrupt = 0x12d4d; +define exported symbol ROM_WIFI_RESUME_TxBeacon = 0x12d61; +define exported symbol ROM_WIFI_STOP_TXBeacon = 0x12d91; +define exported symbol ROM_WIFI_BCN_Interval = 0x12dc1; +define exported symbol ROM_WIFI_BCN_FUNC_Enable = 0x12dcd; +define exported symbol ROM_WIFI_INIT_BeaconParameters = 0x12de5; +define exported symbol ROM_WIFI_MEDIA_STATUS1 = 0x12e35; +define exported symbol ROM_WIFI_MEDIA_STATUS = 0x12e4d; +define exported symbol ROM_WIFI_SetBrateCfg = 0x12e61; +define exported symbol ROM_WIFI_BASIC_RATE = 0x12f69; +define exported symbol ROM_WIFI_CHECK_BSSID = 0x12fc9; +define exported symbol ROM_WIFI_RESP_SIFS = 0x12fe9; +define exported symbol ROM_WIFI_CAM_WRITE = 0x13001; +define exported symbol ROM_WIFI_ACM_CTRL = 0x13021; +define exported symbol ROM_WIFI_FIFO_CLEARN_UP = 0x13051; +define exported symbol ROM_WIFI_CHECK_TXBUF = 0x130b9; +define exported symbol ROM_WIFI_BCN_VALID = 0x130fd; +define exported symbol ROM_WIFI_PROMISC_Cmd = 0x13119; +define exported symbol ROM_WIFI_SetOpmodeAP = 0x13189; +define exported symbol ROM_WIFI_ReadChipVersion = 0x132a9; +define exported symbol ROM_WIFI_DumpChipInfo = 0x1330d; +define exported symbol ROM_WIFI_InitLxDma = 0x135b1; +define exported symbol ROM_WIFI_InitQueueReservedPage = 0x13671; +define exported symbol ROM_WIFI_InitTxBufferBoundary = 0x136f1; +define exported symbol ROM_WIFI_InitNormalChipRegPriority = 0x1373d; +define exported symbol ROM_WIFI_InitPageBoundary = 0x13789; +define exported symbol ROM_WIFI_InitTransferPageSize = 0x13795; +define exported symbol ROM_WIFI_InitDriverInfoSize = 0x137a1; +define exported symbol ROM_WIFI_InitNetworkType = 0x137ad; +define exported symbol ROM_WIFI_InitRCR = 0x137c5; +define exported symbol ROM_WIFI_InitAdaptiveCtrl = 0x13805; +define exported symbol ROM_WIFI_InitSIFS = 0x1383d; +define exported symbol ROM_WIFI_InitEDCA = 0x13865; +define exported symbol ROM_WIFI_InitRateFallback = 0x138a1; +define exported symbol ROM_WIFI_InitRetryFunction = 0x138c9; +define exported symbol ROM_WIFI_InitOperationMode = 0x138e5; +define exported symbol ROM_WIFI_InitBurstPktLen = 0x138f9; +define exported symbol phy_CalculateBitShift = 0x13905; +define exported symbol PHY_SetBBReg_8711B = 0x1391d; +define exported symbol PHY_QueryBBReg_8711B = 0x13921; +define exported symbol ROM_odm_QueryRxPwrPercentage = 0x13925; +define exported symbol ROM_odm_EVMdbToPercentage = 0x13931; +define exported symbol ROM_odm_SignalScaleMapping_8711B = 0x13935; +define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x13a11; +define exported symbol ROM_odm_SetEDCCAThreshold = 0x13d39; +define exported symbol ROM_odm_SetTRxMux = 0x13d61; +define exported symbol ROM_odm_SetCrystalCap = 0x13d89; +define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x13ded; +define exported symbol ROM_ODM_CfoTrackingReset = 0x13dfd; +define exported symbol ROM_odm_CfoTrackingFlow = 0x13e21; +define exported symbol rtw_get_bit_value_from_ieee_value = 0x14045; +define exported symbol rtw_is_cckrates_included = 0x14071; +define exported symbol rtw_is_cckratesonly_included = 0x140a5; +define exported symbol rtw_check_network_type = 0x140cd; +define exported symbol rtw_set_fixed_ie = 0x14155; +define exported symbol rtw_set_ie = 0x14175; +define exported symbol rtw_get_ie = 0x141a1; +define exported symbol rtw_set_supported_rate = 0x141b5; +define exported symbol rtw_get_rateset_len = 0x14229; +define exported symbol rtw_get_wpa_ie = 0x14245; +define exported symbol rtw_get_wpa2_ie = 0x142d1; +define exported symbol rtw_get_wpa_cipher_suite = 0x142e5; +define exported symbol rtw_get_wpa2_cipher_suite = 0x1434d; +define exported symbol rtw_parse_wpa_ie = 0x143b5; +define exported symbol rtw_parse_wpa2_ie = 0x14481; +define exported symbol rtw_get_sec_ie = 0x14535; +define exported symbol rtw_get_wps_ie = 0x145e5; +define exported symbol rtw_get_wps_attr = 0x14659; +define exported symbol rtw_get_wps_attr_content = 0x146f1; +define exported symbol rtw_ieee802_11_parse_elems = 0x14739; +define exported symbol str_2char2num = 0x14909; +define exported symbol key_2char2num = 0x14925; +define exported symbol convert_ip_addr = 0x1493d; +define exported symbol rom_psk_PasswordHash = 0x14a21; +define exported symbol rom_psk_CalcGTK = 0x14a59; +define exported symbol rom_psk_CalcPTK = 0x14ae9; +define exported symbol _htons_rom = 0x14bdd; +define exported symbol _ntohs_rom = 0x14be5; +define exported symbol _htonl_rom = 0x14bed; +define exported symbol _ntohl_rom = 0x14bf1; +define exported symbol Message_ReplayCounter_OC2LI = 0x14bf5; +define exported symbol Message_EqualReplayCounter = 0x14c35; +define exported symbol Message_SmallerEqualReplayCounter = 0x14c6d; +define exported symbol Message_LargerReplayCounter = 0x14cad; +define exported symbol Message_setReplayCounter = 0x14ce5; +define exported symbol INCLargeInteger = 0x14d15; +define exported symbol INCOctet16_INTEGER = 0x14d25; +define exported symbol INCOctet32_INTEGER = 0x14d8d; +define exported symbol SetEAPOL_KEYIV = 0x14df5; +define exported symbol CheckMIC = 0x14e89; +define exported symbol CalcMIC = 0x14f29; +define exported symbol DecWPA2KeyData_rom = 0x14f9d; +define exported symbol DecGTK = 0x15055; +define exported symbol GetRandomBuffer = 0x15119; +define exported symbol GenNonce = 0x15181; +define exported symbol ClientConstructEAPOL_2Of4Way = 0x151c5; +define exported symbol ClientConstructEAPOL_4Of4Way = 0x152cd; +define exported symbol ClientConstructEAPOL_2Of2Way = 0x1537d; +define exported symbol ClientConstructEAPOL_MICOf2Way = 0x15459; +define exported symbol psk_strip_rsn_pairwise = 0x1552d; +define exported symbol psk_strip_wpa_pairwise = 0x155c1; +define exported symbol wep_80211_encrypt = 0x1587d; +define exported symbol wep_80211_decrypt = 0x158e1; +define exported symbol tkip_micappendbyte = 0x15975; +define exported symbol rtw_secmicsetkey = 0x159b9; +define exported symbol rtw_secmicappend = 0x159f9; +define exported symbol rtw_secgetmic = 0x15a15; +define exported symbol rtw_seccalctkipmic = 0x15a89; +define exported symbol tkip_phase1 = 0x15b7d; +define exported symbol tkip_phase2 = 0x15ce5; +define exported symbol tkip_80211_encrypt = 0x15f01; +define exported symbol tkip_80211_decrypt = 0x15f91; +define exported symbol aes1_encrypt = 0x16055; +define exported symbol aesccmp_construct_mic_iv = 0x1625d; +define exported symbol aesccmp_construct_mic_header1 = 0x162b1; +define exported symbol aesccmp_construct_mic_header2 = 0x16321; +define exported symbol aesccmp_construct_ctr_preload = 0x163a5; +define exported symbol aes_80211_encrypt = 0x16429; +define exported symbol aes_80211_decrypt = 0x167f9; +define exported symbol cckrates_included = 0x16c39; +define exported symbol cckratesonly_included = 0x16c7d; +define exported symbol networktype_to_raid_ex_rom = 0x16ca9; +define exported symbol judge_network_type_rom = 0x16cf5; +define exported symbol ratetbl_val_2wifirate = 0x16d89; +define exported symbol is_basicrate_rom = 0x16d9d; +define exported symbol ratetbl2rateset_rom = 0x16dd5; +define exported symbol get_rate_set_rom = 0x16e3d; +define exported symbol UpdateBrateTbl_rom = 0x16e71; +define exported symbol UpdateBrateTblForSoftAP = 0x16ec9; +define exported symbol write_cam_rom = 0x16f0d; +define exported symbol HT_caps_handler_rom = 0x16fc1; +define exported symbol wifirate2_ratetbl_inx = 0x17015; +define exported symbol update_basic_rate = 0x170bd; +define exported symbol update_supported_rate = 0x170f5; +define exported symbol update_MCS_rate = 0x17125; +define exported symbol get_highest_rate_idx = 0x17131; +define exported symbol _sha1_process_message_block = 0x1714d; +define exported symbol _sha1_pad_message = 0x172d1; +define exported symbol rt_sha1_init = 0x1736d; +define exported symbol rt_sha1_update = 0x173b1; +define exported symbol rt_sha1_finish = 0x17429; +define exported symbol rt_hmac_sha1 = 0x17489; +define exported symbol rom_aes_128_cbc_encrypt = 0x175e5; +define exported symbol rom_aes_128_cbc_decrypt = 0x17669; +define exported symbol rom_rijndaelKeySetupEnc = 0x176ed; +define exported symbol rom_aes_decrypt_init = 0x177c1; +define exported symbol rom_aes_internal_decrypt = 0x17899; +define exported symbol rom_aes_decrypt_deinit = 0x17bdd; +define exported symbol rom_aes_encrypt_init = 0x17be9; +define exported symbol rom_aes_internal_encrypt = 0x17c01; +define exported symbol rom_aes_encrypt_deinit = 0x17f81; +define exported symbol bignum_init = 0x1963d; +define exported symbol bignum_deinit = 0x19665; +define exported symbol bignum_get_unsigned_bin_len = 0x19685; +define exported symbol bignum_get_unsigned_bin = 0x19689; +define exported symbol bignum_set_unsigned_bin = 0x19741; +define exported symbol bignum_cmp = 0x197f9; +define exported symbol bignum_cmp_d = 0x197fd; +define exported symbol bignum_add = 0x19825; +define exported symbol bignum_sub = 0x19835; +define exported symbol bignum_mul = 0x19845; +define exported symbol bignum_exptmod = 0x19855; +define exported symbol WPS_realloc = 0x19879; +define exported symbol os_zalloc = 0x198bd; +define exported symbol rom_hmac_sha256_vector = 0x198e1; +define exported symbol rom_hmac_sha256 = 0x199e1; +define exported symbol rom_sha256_vector = 0x19b3d; +define exported symbol CRYPTO_chacha_20 = 0x19d45; +define exported symbol rom_ed25519_gen_keypair = 0x1a1bd; +define exported symbol rom_ed25519_gen_signature = 0x1a1c1; +define exported symbol rom_ed25519_verify_signature = 0x1a1d9; +define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x1c4c9; +define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x1c8c1; +define exported symbol rom_ed25519_ge_p3_tobytes = 0x1d43d; +define exported symbol rom_ed25519_ge_scalarmult_base = 0x1d489; +define exported symbol rom_ed25519_ge_tobytes = 0x1d64d; +define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x1d699; +define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x1d6f1; +define exported symbol rom_ed25519_sc_muladd = 0x1d9e5; +define exported symbol rom_ed25519_sc_reduce = 0x24175; +define exported symbol rom_ed25519_crypto_sign_detached = 0x26c25; +define exported symbol CRYPTO_poly1305_init = 0x270dd; +define exported symbol CRYPTO_poly1305_update = 0x271b5; +define exported symbol CRYPTO_poly1305_finish = 0x27245; +define exported symbol rom_sha512_starts = 0x28511; +define exported symbol rom_sha512_update = 0x28659; +define exported symbol rom_sha512_finish = 0x28661; +define exported symbol rom_sha512 = 0x288a9; +define exported symbol rom_sha512_hmac_starts = 0x288e1; +define exported symbol rom_sha512_hmac_update = 0x289a5; +define exported symbol rom_sha512_hmac_finish = 0x289ad; +define exported symbol rom_sha512_hmac_reset = 0x289fd; +define exported symbol rom_sha512_hmac = 0x28a19; +define exported symbol rom_sha512_hkdf = 0x28a51; +define exported symbol aes_test_alignment_detection = 0x28b59; +define exported symbol aes_mode_reset = 0x28bbd; +define exported symbol aes_ecb_encrypt = 0x28bc9; +define exported symbol aes_ecb_decrypt = 0x28c05; +define exported symbol aes_cbc_encrypt = 0x28c41; +define exported symbol aes_cbc_decrypt = 0x28dad; +define exported symbol aes_cfb_encrypt = 0x28f49; +define exported symbol aes_cfb_decrypt = 0x2920d; +define exported symbol aes_ofb_crypt = 0x294d5; +define exported symbol aes_ctr_crypt = 0x29769; +define exported symbol aes_encrypt_key128 = 0x29a79; +define exported symbol aes_encrypt_key192 = 0x29a95; +define exported symbol aes_encrypt_key256 = 0x29ab1; +define exported symbol aes_encrypt_key = 0x29ad1; +define exported symbol aes_decrypt_key128 = 0x29b41; +define exported symbol aes_decrypt_key192 = 0x29b5d; +define exported symbol aes_decrypt_key256 = 0x29b79; +define exported symbol aes_decrypt_key = 0x29b99; +define exported symbol aes_init = 0x29c09; +define exported symbol curve25519_donna = 0x2a939; +define exported symbol __rtl_dtoa_r_v1_00 = 0x2b7f1; +define exported symbol __rtl_ltoa_v1_00 = 0x2c7f9; +define exported symbol __rtl_ultoa_v1_00 = 0x2c885; +define exported symbol __rtl_dtoi_v1_00 = 0x2c8ed; +define exported symbol __rtl_dtoi64_v1_00 = 0x2c96d; +define exported symbol __rtl_dtoui_v1_00 = 0x2ca09; +define exported symbol __rtl_ftol_v1_00 = 0x2ca11; +define exported symbol __rtl_itof_v1_00 = 0x2ca75; +define exported symbol __rtl_itod_v1_00 = 0x2cb05; +define exported symbol __rtl_i64tod_v1_00 = 0x2cb71; +define exported symbol __rtl_uitod_v1_00 = 0x2cc4d; +define exported symbol __rtl_ftod_v1_00 = 0x2cd29; +define exported symbol __rtl_dtof_v1_00 = 0x2cde1; +define exported symbol __rtl_uitof_v1_00 = 0x2ce75; +define exported symbol __rtl_fadd_v1_00 = 0x2cf59; +define exported symbol __rtl_fsub_v1_00 = 0x2d259; +define exported symbol __rtl_fmul_v1_00 = 0x2d565; +define exported symbol __rtl_fdiv_v1_00 = 0x2d695; +define exported symbol __rtl_dadd_v1_00 = 0x2d809; +define exported symbol __rtl_dsub_v1_00 = 0x2de49; +define exported symbol __rtl_dmul_v1_00 = 0x2e4a1; +define exported symbol __rtl_ddiv_v1_00 = 0x2e7dd; +define exported symbol __rtl_dcmpeq_v1_00 = 0x2ed71; +define exported symbol __rtl_dcmplt_v1_00 = 0x2eded; +define exported symbol __rtl_dcmpgt_v1_00 = 0x2ee85; +define exported symbol __rtl_dcmple_v1_00 = 0x2ef95; +define exported symbol __rtl_fcmplt_v1_00 = 0x2f0a9; +define exported symbol __rtl_fcmpgt_v1_00 = 0x2f105; +define exported symbol __rtl_fpclassifyd = 0x2f1ad; +define exported symbol __rtl_close_v1_00 = 0x2f205; +define exported symbol __rtl_fstat_v1_00 = 0x2f219; +define exported symbol __rtl_isatty_v1_00 = 0x2f22d; +define exported symbol __rtl_lseek_v1_00 = 0x2f23d; +define exported symbol __rtl_open_v1_00 = 0x2f251; +define exported symbol __rtl_read_v1_00 = 0x2f265; +define exported symbol __rtl_write_v1_00 = 0x2f279; +define exported symbol __rtl_sbrk_v1_00 = 0x2f28d; +define exported symbol __rom_mallocr_init_v1_00 = 0x2f29d; +define exported symbol __rtl_free_r_v1_00 = 0x2f309; +define exported symbol __rtl_malloc_r_v1_00 = 0x2f521; +define exported symbol __rtl_realloc_r_v1_00 = 0x2f9f5; +define exported symbol __rtl_memalign_r_v1_00 = 0x2fdb5; +define exported symbol __rtl_valloc_r_v1_00 = 0x2fe81; +define exported symbol __rtl_pvalloc_r_v1_00 = 0x2fe8d; +define exported symbol __rtl_calloc_r_v1_00 = 0x2fea1; +define exported symbol __rtl_cfree_r_v1_00 = 0x2ff05; +define exported symbol __rtl_cos_f32_v1_00 = 0x2ff15; +define exported symbol __rtl_sin_f32_v1_00 = 0x300e9; +define exported symbol __rtl_fabs_v1_00 = 0x302ad; +define exported symbol __rtl_fabsf_v1_00 = 0x302b5; +define exported symbol __rtl_memchr_v1_00 = 0x302bd; +define exported symbol __rtl_memcmp_v1_00 = 0x30351; +define exported symbol __rtl_memcpy_v1_00 = 0x303b5; +define exported symbol __rtl_memmove_v1_00 = 0x3045d; +define exported symbol __rtl_memset_v1_00 = 0x30525; +define exported symbol __rtl_Balloc_v1_00 = 0x3061d; +define exported symbol __rtl_Bfree_v1_00 = 0x3066d; +define exported symbol __rtl_i2b_v1_00 = 0x30681; +define exported symbol __rtl_multadd_v1_00 = 0x30695; +define exported symbol __rtl_mult_v1_00 = 0x30721; +define exported symbol __rtl_pow5mult_v1_00 = 0x30855; +define exported symbol __rtl_hi0bits_v1_00 = 0x308f5; +define exported symbol __rtl_d2b_v1_00 = 0x30935; +define exported symbol __rtl_lshift_v1_00 = 0x309ed; +define exported symbol __rtl_cmp_v1_00 = 0x30a99; +define exported symbol __rtl_diff_v1_00 = 0x30ae1; +define exported symbol __rtl_sread_v1_00 = 0x30bb5; +define exported symbol __rtl_seofread_v1_00 = 0x30c01; +define exported symbol __rtl_swrite_v1_00 = 0x30c05; +define exported symbol __rtl_sseek_v1_00 = 0x30c75; +define exported symbol __rtl_sclose_v1_00 = 0x30cc1; +define exported symbol __rtl_sbrk_r_v1_00 = 0x30ced; +define exported symbol __rtl_strcat_v1_00 = 0x30d15; +define exported symbol __rtl_strchr_v1_00 = 0x30d59; +define exported symbol __rtl_strcmp_v1_00 = 0x30e25; +define exported symbol __rtl_strcpy_v1_00 = 0x30e99; +define exported symbol __rtl_strlen_v1_00 = 0x30ee5; +define exported symbol __rtl_strncat_v1_00 = 0x30f39; +define exported symbol __rtl_strncmp_v1_00 = 0x30f95; +define exported symbol __rtl_strncpy_v1_00 = 0x3102d; +define exported symbol __rtl_strsep_v1_00 = 0x31095; +define exported symbol __rtl_strstr_v1_00 = 0x3136d; +define exported symbol __rtl_strtok_v1_00 = 0x315a5; +define exported symbol __rtl__strtok_r_v1_00 = 0x315b5; +define exported symbol __rtl_strtok_r_v1_00 = 0x31619; +define exported symbol __rtl_fflush_r_v1_00 = 0x31ae9; +define exported symbol __rtl_vfprintf_r_v1_00 = 0x31f99; +define exported symbol polarssl_aes_init = 0x335b9; +define exported symbol aes_free = 0x335c9; +define exported symbol aes_setkey_enc = 0x335dd; +define exported symbol aes_setkey_dec = 0x33829; +define exported symbol aes_crypt_ecb = 0x339a1; +define exported symbol aes_crypt_cbc = 0x343d1; +define exported symbol aes_crypt_cfb128 = 0x34649; +define exported symbol aes_crypt_cfb8 = 0x346c9; +define exported symbol aes_crypt_ctr = 0x3474d; +define exported symbol arc4_init = 0x347b1; +define exported symbol arc4_free = 0x347bd; +define exported symbol arc4_setup = 0x347d1; +define exported symbol arc4_crypt = 0x3481d; +define exported symbol asn1_get_len = 0x34861; +define exported symbol asn1_get_tag = 0x34901; +define exported symbol asn1_get_bool = 0x34929; +define exported symbol asn1_get_int = 0x3495d; +define exported symbol asn1_get_mpi = 0x349a9; +define exported symbol asn1_get_bitstring = 0x349d1; +define exported symbol asn1_get_bitstring_null = 0x34a19; +define exported symbol asn1_get_sequence_of = 0x34a4d; +define exported symbol asn1_get_alg = 0x34ad1; +define exported symbol asn1_get_alg_null = 0x34b65; +define exported symbol asn1_free_named_data = 0x34ba5; +define exported symbol asn1_free_named_data_list = 0x34bcd; +define exported symbol asn1_find_named_data = 0x34bf5; +define exported symbol asn1_write_len = 0x34c25; +define exported symbol asn1_write_tag = 0x34c8d; +define exported symbol asn1_write_raw_buffer = 0x34ca9; +define exported symbol asn1_write_mpi = 0x34ccd; +define exported symbol asn1_write_null = 0x34d41; +define exported symbol asn1_write_oid = 0x34d6d; +define exported symbol asn1_write_algorithm_identifier = 0x34dc5; +define exported symbol asn1_write_bool = 0x34e21; +define exported symbol asn1_write_int = 0x34e65; +define exported symbol asn1_write_printable_string = 0x34ecd; +define exported symbol asn1_write_ia5_string = 0x34f25; +define exported symbol asn1_write_bitstring = 0x34f7d; +define exported symbol asn1_write_octet_string = 0x34fe5; +define exported symbol asn1_store_named_data = 0x3503d; +define exported symbol base64_encode = 0x35111; +define exported symbol base64_decode = 0x3523d; +define exported symbol mpi_init = 0x35e09; +define exported symbol mpi_free = 0x35e19; +define exported symbol mpi_grow = 0x35e55; +define exported symbol mpi_shrink = 0x35e79; +define exported symbol mpi_copy = 0x35f21; +define exported symbol mpi_swap = 0x35fa1; +define exported symbol mpi_safe_cond_assign = 0x35fcd; +define exported symbol mpi_safe_cond_swap = 0x36069; +define exported symbol mpi_lset = 0x3610d; +define exported symbol mpi_get_bit = 0x3614d; +define exported symbol mpi_set_bit = 0x3616d; +define exported symbol mpi_lsb = 0x361d5; +define exported symbol mpi_msb = 0x36215; +define exported symbol mpi_size = 0x36261; +define exported symbol mpi_read_binary = 0x3626d; +define exported symbol mpi_write_binary = 0x362f9; +define exported symbol mpi_shift_l = 0x36341; +define exported symbol mpi_shift_r = 0x363f1; +define exported symbol mpi_cmp_abs = 0x36475; +define exported symbol mpi_cmp_mpi = 0x36619; +define exported symbol mpi_cmp_int = 0x366f1; +define exported symbol mpi_add_abs = 0x3671d; +define exported symbol mpi_sub_abs = 0x3680d; +define exported symbol mpi_add_mpi = 0x3689d; +define exported symbol mpi_sub_mpi = 0x368ed; +define exported symbol mpi_add_int = 0x3693d; +define exported symbol mpi_sub_int = 0x36969; +define exported symbol mpi_mul_mpi = 0x36995; +define exported symbol mpi_read_string = 0x36ac5; +define exported symbol mpi_mul_int = 0x36c45; +define exported symbol mpi_div_mpi = 0x36c61; +define exported symbol mpi_div_int = 0x370ed; +define exported symbol mpi_mod_mpi = 0x37119; +define exported symbol mpi_mod_int = 0x3717d; +define exported symbol mpi_write_string = 0x3722d; +define exported symbol mpi_exp_mod = 0x37395; +define exported symbol mpi_gcd = 0x37915; +define exported symbol mpi_fill_random = 0x37a39; +define exported symbol mpi_inv_mod = 0x37c4d; +define exported symbol mpi_is_prime = 0x37f15; +define exported symbol mpi_gen_prime = 0x37f71; +define exported symbol ctr_drbg_free = 0x38285; +define exported symbol ctr_drbg_set_prediction_resistance = 0x382a1; +define exported symbol ctr_drbg_set_entropy_len = 0x382a5; +define exported symbol ctr_drbg_set_reseed_interval = 0x382a9; +define exported symbol ctr_drbg_update = 0x382ad; +define exported symbol ctr_drbg_reseed = 0x382c9; +define exported symbol ctr_drbg_init_entropy_len = 0x38341; +define exported symbol ctr_drbg_init = 0x38399; +define exported symbol ctr_drbg_random_with_add = 0x383ad; +define exported symbol ctr_drbg_random = 0x38469; +define exported symbol des_init = 0x388a5; +define exported symbol des_free = 0x388b1; +define exported symbol des3_init = 0x388c5; +define exported symbol des3_free = 0x388d5; +define exported symbol des_key_set_parity = 0x388e9; +define exported symbol des_key_check_key_parity = 0x38909; +define exported symbol des_key_check_weak = 0x38939; +define exported symbol des_setkey_enc = 0x38965; +define exported symbol des_setkey_dec = 0x3898d; +define exported symbol des3_set2key_enc = 0x389d9; +define exported symbol des3_set2key_dec = 0x38a25; +define exported symbol des3_set3key_enc = 0x38a71; +define exported symbol des3_set3key_dec = 0x38ab1; +define exported symbol des_crypt_ecb = 0x38af1; +define exported symbol des_crypt_cbc = 0x38d09; +define exported symbol des3_crypt_ecb = 0x38f99; +define exported symbol des3_crypt_cbc = 0x39401; +define exported symbol dhm_init = 0x39729; +define exported symbol dhm_read_params = 0x39731; +define exported symbol dhm_make_params = 0x3978d; +define exported symbol dhm_read_public = 0x398c1; +define exported symbol dhm_make_public = 0x398e9; +define exported symbol dhm_calc_secret = 0x399ad; +define exported symbol dhm_free = 0x39ba1; +define exported symbol dhm_parse_dhm = 0x39c01; +define exported symbol ecdh_gen_public = 0x39cc5; +define exported symbol ecdh_compute_shared = 0x39cc9; +define exported symbol ecdh_init = 0x39d2d; +define exported symbol ecdh_free = 0x39d39; +define exported symbol ecdh_make_params = 0x39d81; +define exported symbol ecdh_read_params = 0x39e05; +define exported symbol ecdh_get_params = 0x39e2d; +define exported symbol ecdh_make_public = 0x39e79; +define exported symbol ecdh_read_public = 0x39ed1; +define exported symbol ecdh_calc_secret = 0x39f01; +define exported symbol ecdsa_sign = 0x3a041; +define exported symbol ecdsa_sign_det = 0x3a1c5; +define exported symbol ecdsa_verify = 0x3a2a9; +define exported symbol ecdsa_write_signature = 0x3a431; +define exported symbol ecdsa_write_signature_det = 0x3a46d; +define exported symbol ecdsa_read_signature = 0x3a4a5; +define exported symbol ecdsa_genkey = 0x3a531; +define exported symbol ecdsa_init = 0x3a565; +define exported symbol ecdsa_free = 0x3a591; +define exported symbol ecdsa_from_keypair = 0x3a5bd; +define exported symbol ecp_curve_list = 0x3aee5; +define exported symbol ecp_curve_info_from_grp_id = 0x3aeed; +define exported symbol ecp_curve_info_from_tls_id = 0x3af0d; +define exported symbol ecp_curve_info_from_name = 0x3af31; +define exported symbol ecp_point_init = 0x3af61; +define exported symbol ecp_group_init = 0x3af81; +define exported symbol ecp_keypair_init = 0x3af8d; +define exported symbol ecp_point_free = 0x3afb1; +define exported symbol ecp_group_free = 0x3afd1; +define exported symbol ecp_keypair_free = 0x3b03d; +define exported symbol ecp_copy = 0x3b05d; +define exported symbol ecp_group_copy = 0x3b08d; +define exported symbol ecp_set_zero = 0x3b095; +define exported symbol ecp_is_zero = 0x3ba61; +define exported symbol ecp_point_read_string = 0x3ba75; +define exported symbol ecp_point_write_binary = 0x3baa5; +define exported symbol ecp_point_read_binary = 0x3bb4d; +define exported symbol ecp_tls_read_point = 0x3bbc1; +define exported symbol ecp_tls_write_point = 0x3bbf5; +define exported symbol ecp_group_read_string = 0x3bc25; +define exported symbol ecp_tls_read_group = 0x3bc95; +define exported symbol ecp_tls_write_group = 0x3bcf1; +define exported symbol ecp_add = 0x3bd39; +define exported symbol ecp_sub = 0x3bd65; +define exported symbol ecp_check_pubkey = 0x3bddd; +define exported symbol ecp_check_privkey = 0x3bf8d; +define exported symbol ecp_mul = 0x3bff5; +define exported symbol ecp_gen_keypair = 0x3c565; +define exported symbol ecp_gen_key = 0x3c669; +define exported symbol ecp_use_known_dp = 0x3d741; +define exported symbol hmac_drbg_update = 0x3daa9; +define exported symbol hmac_drbg_init_buf = 0x3db41; +define exported symbol hmac_drbg_reseed = 0x3db91; +define exported symbol hmac_drbg_init = 0x3dc09; +define exported symbol hmac_drbg_set_prediction_resistance = 0x3dc81; +define exported symbol hmac_drbg_set_entropy_len = 0x3dc85; +define exported symbol hmac_drbg_set_reseed_interval = 0x3dc89; +define exported symbol hmac_drbg_random_with_add = 0x3dc8d; +define exported symbol hmac_drbg_random = 0x3dd4d; +define exported symbol hmac_drbg_free = 0x3dd61; +define exported symbol md_list = 0x3dd7d; +define exported symbol md_info_from_string = 0x3dd85; +define exported symbol md_info_from_type = 0x3de59; +define exported symbol md_init = 0x3de9d; +define exported symbol md_free = 0x3dea5; +define exported symbol md_init_ctx = 0x3dec5; +define exported symbol md_free_ctx = 0x3defd; +define exported symbol md_starts = 0x3df09; +define exported symbol md_update = 0x3df29; +define exported symbol md_finish = 0x3df49; +define exported symbol md = 0x3df69; +define exported symbol md_file = 0x3df89; +define exported symbol md_hmac_starts = 0x3dfa1; +define exported symbol md_hmac_update = 0x3dfc1; +define exported symbol md_hmac_finish = 0x3dfe1; +define exported symbol md_hmac_reset = 0x3e001; +define exported symbol md_hmac = 0x3e021; +define exported symbol md_process = 0x3e049; +define exported symbol md5_init = 0x3e301; +define exported symbol md5_free = 0x3e309; +define exported symbol md5_starts = 0x3e31d; +define exported symbol md5_process = 0x3e34d; +define exported symbol md5_update = 0x3ed51; +define exported symbol md5_finish = 0x3ed59; +define exported symbol md5 = 0x3ee11; +define exported symbol md5_hmac_starts = 0x3ee75; +define exported symbol md5_hmac_update = 0x3ef51; +define exported symbol md5_hmac_finish = 0x3ef59; +define exported symbol md5_hmac_reset = 0x3efbd; +define exported symbol md5_hmac = 0x3eff1; +define exported symbol oid_get_attr_short_name = 0x3f071; +define exported symbol oid_get_x509_ext_type = 0x3f0b1; +define exported symbol oid_get_extended_key_usage = 0x3f0f1; +define exported symbol oid_get_sig_alg_desc = 0x3f131; +define exported symbol oid_get_sig_alg = 0x3f149; +define exported symbol oid_get_oid_by_sig_alg = 0x3f169; +define exported symbol oid_get_pk_alg = 0x3f1a1; +define exported symbol oid_get_oid_by_pk_alg = 0x3f1e1; +define exported symbol oid_get_ec_grp = 0x3f219; +define exported symbol oid_get_oid_by_ec_grp = 0x3f259; +define exported symbol oid_get_cipher_alg = 0x3f291; +define exported symbol oid_get_md_alg = 0x3f2d1; +define exported symbol oid_get_oid_by_md = 0x3f311; +define exported symbol oid_get_pkcs12_pbe_alg = 0x3f349; +define exported symbol oid_get_numeric_string = 0x3f391; +define exported symbol pem_init = 0x3f649; +define exported symbol pem_read_buffer = 0x3f651; +define exported symbol pem_free = 0x3f955; +define exported symbol pem_write_buffer = 0x3f97d; +define exported symbol pk_init = 0x3fa81; +define exported symbol pk_free = 0x3fa8d; +define exported symbol pk_info_from_type = 0x3faad; +define exported symbol pk_init_ctx = 0x3fae1; +define exported symbol pk_init_ctx_rsa_alt = 0x3fb11; +define exported symbol pk_can_do = 0x3fb69; +define exported symbol pk_verify = 0x3fb79; +define exported symbol pk_verify_ext = 0x3fbc9; +define exported symbol pk_sign = 0x3fc8d; +define exported symbol pk_decrypt = 0x3fce9; +define exported symbol pk_encrypt = 0x3fd15; +define exported symbol pk_get_size = 0x3fd41; +define exported symbol pk_debug = 0x3fd51; +define exported symbol pk_get_name = 0x3fd79; +define exported symbol pk_get_type = 0x3fd8d; +define exported symbol pk_write_pubkey = 0x40181; +define exported symbol pk_write_pubkey_der = 0x40201; +define exported symbol pk_write_key_der = 0x402dd; +define exported symbol pk_write_pubkey_pem = 0x404f5; +define exported symbol pk_write_key_pem = 0x40545; +define exported symbol rsa_init = 0x4065d; +define exported symbol rsa_set_padding = 0x40679; +define exported symbol rsa_check_pubkey = 0x40685; +define exported symbol rsa_check_privkey = 0x406e1; +define exported symbol rsa_public = 0x409a5; +define exported symbol rsa_private = 0x40a25; +define exported symbol rsa_rsaes_oaep_encrypt = 0x40c29; +define exported symbol rsa_rsaes_pkcs1_v15_encrypt = 0x40d31; +define exported symbol rsa_pkcs1_encrypt = 0x40e19; +define exported symbol rsa_rsaes_oaep_decrypt = 0x40e59; +define exported symbol rsa_rsaes_pkcs1_v15_decrypt = 0x40fbd; +define exported symbol rsa_pkcs1_decrypt = 0x410c1; +define exported symbol rsa_rsassa_pss_sign = 0x4110d; +define exported symbol rsa_rsassa_pkcs1_v15_sign = 0x41271; +define exported symbol rsa_pkcs1_sign = 0x41389; +define exported symbol rsa_rsassa_pss_verify_ext = 0x413c9; +define exported symbol rsa_rsassa_pss_verify = 0x41575; +define exported symbol rsa_rsassa_pkcs1_v15_verify = 0x415a5; +define exported symbol rsa_pkcs1_verify = 0x41709; +define exported symbol rsa_free = 0x41765; +define exported symbol rsa_gen_key = 0x417d5; +define exported symbol rsa_copy = 0x4198d; +define exported symbol sha1_init = 0x41a9d; +define exported symbol sha1_free = 0x41aa5; +define exported symbol sha1_starts = 0x41ab9; +define exported symbol sha1_process = 0x41aed; +define exported symbol sha1_update = 0x42e15; +define exported symbol sha1_finish = 0x42e1d; +define exported symbol sha1 = 0x42ee5; +define exported symbol sha1_hmac_starts = 0x42f51; +define exported symbol sha1_hmac_update = 0x43039; +define exported symbol sha1_hmac_finish = 0x43041; +define exported symbol sha1_hmac_reset = 0x430b5; +define exported symbol sha1_hmac = 0x430f1; +define exported symbol sha256_init = 0x43139; +define exported symbol sha256_free = 0x43141; +define exported symbol sha256_starts = 0x43155; +define exported symbol sha256_process = 0x431e5; +define exported symbol sha256_update = 0x4513d; +define exported symbol sha256_finish = 0x45145; +define exported symbol sha256 = 0x4524d; +define exported symbol sha256_hmac_starts = 0x45325; +define exported symbol sha256_hmac_update = 0x45475; +define exported symbol sha256_hmac_finish = 0x4547d; +define exported symbol sha256_hmac_reset = 0x45569; +define exported symbol sha256_hmac = 0x45601; +define exported symbol sha512_init = 0x45651; +define exported symbol sha512_free = 0x4565d; +define exported symbol sha512_starts = 0x45671; +define exported symbol sha512_process = 0x457b9; +define exported symbol sha512_update = 0x46879; +define exported symbol sha512_finish = 0x46881; +define exported symbol sha512 = 0x46ac9; +define exported symbol sha512_hmac_starts = 0x46b11; +define exported symbol sha512_hmac_update = 0x46bd9; +define exported symbol sha512_hmac_finish = 0x46be1; +define exported symbol sha512_hmac_reset = 0x46c35; +define exported symbol sha512_hmac = 0x46c51; +define exported symbol UartLogRomCmdTable = 0x46ca0; +define exported symbol XTAL_CLK = 0x46e10; +define exported symbol CpkClkTbl_FPAG = 0x46e50; +define exported symbol CpkClkTbl_ASIC = 0x46e68; +define exported symbol ROM_IMG1_VALID_PATTEN = 0x46e90; +define exported symbol __AES_rcon = 0x46e98; +define exported symbol __AES_Te4 = 0x46ec0; +define exported symbol SpicCalibrationPattern = 0x472c0; +define exported symbol NEW_CALIBREATION_DIV = 0x472c8; +define exported symbol NEW_CALIBREATION_DATA = 0x472e4; +define exported symbol GDMA_IrqNum = 0x47344; +define exported symbol I2C_DEV_TABLE = 0x47350; +define exported symbol spi_clk_pin = 0x47370; +define exported symbol SPI_DEV_TABLE = 0x47374; +define exported symbol PWM_GDMA_HSx = 0x47394; +define exported symbol TIM_DMA_CCx = 0x473ac; +define exported symbol TIM_IT_CCx = 0x473c4; +define exported symbol TIMx = 0x473dc; +define exported symbol TIMx_irq = 0x473f4; +define exported symbol BAUDRATE_TABLE_40M = 0x4740c; +define exported symbol UART_DEV_TABLE = 0x475bc; +define exported symbol RTW_WPA_OUI_TYPE = 0x4b270; +define exported symbol WPA_CIPHER_SUITE_NONE = 0x4b274; +define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x4b278; +define exported symbol WPA_CIPHER_SUITE_TKIP = 0x4b27c; +define exported symbol WPA_CIPHER_SUITE_CCMP = 0x4b280; +define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x4b284; +define exported symbol RSN_CIPHER_SUITE_NONE = 0x4b288; +define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x4b28c; +define exported symbol RSN_CIPHER_SUITE_TKIP = 0x4b290; +define exported symbol RSN_CIPHER_SUITE_CCMP = 0x4b294; +define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x4b298; +define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x4b2a8; +define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x4b2ac; +define exported symbol RSN_VERSION_BSD = 0x4b2b0; +define exported symbol rom_e_rtw_msgp_str_ = 0x4b2b4; +define exported symbol rtw_basic_rate_mix = 0x4b9a8; +define exported symbol rtw_basic_rate_ofdm = 0x4b9b0; +define exported symbol rtw_basic_rate_cck = 0x4b9b4; +define exported symbol REALTEK_96B_IE = 0x4b9b8; +define exported symbol AIRGOCAP_OUI = 0x4b9c0; +define exported symbol REALTEK_OUI = 0x4b9c4; +define exported symbol RALINK_OUI = 0x4b9c8; +define exported symbol MARVELL_OUI = 0x4b9cc; +define exported symbol CISCO_OUI = 0x4b9d0; +define exported symbol BROADCOM_OUI3 = 0x4b9d4; +define exported symbol BROADCOM_OUI2 = 0x4b9d8; +define exported symbol BROADCOM_OUI1 = 0x4b9dc; +define exported symbol ARTHEROS_OUI2 = 0x4b9e0; +define exported symbol ARTHEROS_OUI1 = 0x4b9e4; +define exported symbol rom_wps_rcons = 0x4b9e8; +define exported symbol rom_wps_Te0 = 0x4b9f4; +define exported symbol rom_wps_Td4s = 0x4bdf4; +define exported symbol rom_wps_Td0 = 0x4bef4; +define exported symbol sha512_info = 0x5850c; +define exported symbol sha384_info = 0x5854c; +define exported symbol sha256_info = 0x5858c; +define exported symbol sha224_info = 0x585cc; +define exported symbol sha1_info = 0x5860c; +define exported symbol md5_info = 0x5864c; +define exported symbol rsa_alt_info = 0x58d28; +define exported symbol ecdsa_info = 0x58d54; +define exported symbol eckeydh_info = 0x58d80; +define exported symbol eckey_info = 0x58dac; +define exported symbol rsa_info = 0x58dd8; +define exported symbol __rom_bss_start__ = 0x10000000; +define exported symbol NewVectorTable = 0x10000000; +define exported symbol UserIrqFunTable = 0x10000100; +define exported symbol UserIrqDataTable = 0x10000200; +define exported symbol ConfigDebugClose = 0x10000300; +define exported symbol CfgSysDebugWarn = 0x10000304; +define exported symbol CfgSysDebugInfo = 0x10000308; +define exported symbol CfgSysDebugErr = 0x1000030c; +define exported symbol ConfigDebugWarn = 0x10000310; +define exported symbol ConfigDebugInfo = 0x10000314; +define exported symbol ConfigDebugErr = 0x10000318; +define exported symbol sector_addr = 0x1000031c; +define exported symbol _rtl_impure_ptr = 0x10000338; +define exported symbol ArgvArray = 0x1000033c; +define exported symbol pUartLogCtl = 0x10000364; +define exported symbol UartLogBuf = 0x10000368; +define exported symbol UartLogCtl = 0x100003e8; +define exported symbol UartLogHistoryBuf = 0x10000408; +define exported symbol NCO32K_Enable = 0x10000684; +define exported symbol g_rtl_cipherEngine = 0x100006a0; +define exported symbol DONGLE_InitStruct = 0x10000ba0; +define exported symbol EFUSE_MAP = 0x10000ba4; +define exported symbol USOC_BOOT_TXBD = 0x10000da4; +define exported symbol USOC_BOOT_RXBD = 0x10000db4; +define exported symbol USB_RXBuff = 0x10000dc4; +define exported symbol USB_TXBuff = 0x10000dcc; +define exported symbol ADC_AnaparAd = 0x10000dd4; +define exported symbol flash_init_para = 0x10000dec; +define exported symbol NEW_CALIBREATION_END = 0x10000e44; +define exported symbol GDMA_Reg = 0x10000e4c; +define exported symbol PortA_IrqHandler = 0x10000e50; +define exported symbol PortA_IrqData = 0x10000ed0; +define exported symbol IC_FS_SCL_HCNT_TRIM = 0x10000f50; +define exported symbol IC_FS_SCL_LCNT_TRIM = 0x10000f54; +define exported symbol I2C_SLAVEWRITE_PATCH = 0x10000f58; +define exported symbol i2s_cur_tx_page = 0x10000f5c; +define exported symbol i2s_cur_rx_page = 0x10000f60; +define exported symbol i2s_page_num = 0x10000f64; +define exported symbol i2s_txpage_entry = 0x10000f68; +define exported symbol i2s_rxpage_entry = 0x10000f78; +define exported symbol TXBDAddrAligned = 0x10000f88; +define exported symbol H2C_Buff = 0x10000f90; +define exported symbol SPI_RECV_Buff = 0x10000f94; +define exported symbol spi_boot_recv_done = 0x10000f98; +define exported symbol UART_StateRx = 0x10000f9c; +define exported symbol UART_StateTx = 0x10000fa8; +define exported symbol xMCtrl = 0x10000fb8; +define exported symbol XComUARTx = 0x10000fc4; +define exported symbol FalseAlmCnt = 0x10000fc8; +define exported symbol ROMInfo = 0x10001008; +define exported symbol DM_CfoTrack = 0x10001020; +define exported symbol rom_wlan_ram_map = 0x10001048; +define exported symbol rom_libgloss_ram_map = 0x10001050; +define exported symbol __rtl_errno = 0x100014b4; +define exported symbol rom_ssl_ram_map = 0x100014b8; +define exported symbol __rom_bss_end__ = 0x100014f8; diff --git a/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds b/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds index 8f9c4fa1a814ab69b40175cf4989756ebe11cfef..b5adb02196c75d27c67c711ff49e192f71856d44 100644 --- a/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds +++ b/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds @@ -65,7 +65,7 @@ SECTIONS /* This is used by the startup in order to initialize the .data secion */ _sidata = .; - _start_address_init_data = .; + _start_address_init_data = .; } > ROM __exidx_end = .; @@ -76,7 +76,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _sdata = . ; - _start_address_data = .; + _start_address_data = .; *(.data) *(.data.*) @@ -91,21 +91,21 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; - _end_address_data = .; + _end_address_data = .; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; . = . + _system_stack_size; . = ALIGN(4); _estack = .; - _end_stack = .; + _end_stack = .; } >RAM __bss_start = .; - _start_address_bss = .; + _start_address_bss = .; .bss : { . = ALIGN(4); @@ -119,11 +119,11 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; - _end_address_bss = .; + _end_address_bss = .; _end = .; diff --git a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds index 5d1d12bbfb24d27b8aec0d29bb6bdb82bd960831..646a746d7cf5aad221627c4925793ed604b722e6 100644 --- a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds +++ b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds @@ -80,7 +80,7 @@ SECTIONS _end_address_data = .; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -102,7 +102,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/apm32/apm32f407ig-minibroard/board/linker_scripts/link.lds b/bsp/apm32/apm32f407ig-minibroard/board/linker_scripts/link.lds index 88364839a9574a79b9c10f20bbee5c602f346a92..c748aece1e042aea347d27a927eb93bb12ab1389 100644 --- a/bsp/apm32/apm32f407ig-minibroard/board/linker_scripts/link.lds +++ b/bsp/apm32/apm32f407ig-minibroard/board/linker_scripts/link.lds @@ -77,7 +77,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -98,7 +98,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/at32/at32f403a-start/board/linker_scripts/link.icf b/bsp/at32/at32f403a-start/board/linker_scripts/link.icf index 65c2bfc8b7c4abbd502aa79b25b00260475ba031..00f54e12f80cd885ab04aa13d17c4e37243a0325 100644 --- a/bsp/at32/at32f403a-start/board/linker_scripts/link.icf +++ b/bsp/at32/at32f403a-start/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/at32/at32f403a-start/board/linker_scripts/link.lds b/bsp/at32/at32f403a-start/board/linker_scripts/link.lds index 27269dd77ea51e0c09a48af982da401b1cacdc8b..cdf8ad639082ca078b184b88edc48be2ef33d0bf 100644 --- a/bsp/at32/at32f403a-start/board/linker_scripts/link.lds +++ b/bsp/at32/at32f403a-start/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/at32/at32f407-start/board/linker_scripts/link.icf b/bsp/at32/at32f407-start/board/linker_scripts/link.icf index 65c2bfc8b7c4abbd502aa79b25b00260475ba031..00f54e12f80cd885ab04aa13d17c4e37243a0325 100644 --- a/bsp/at32/at32f407-start/board/linker_scripts/link.icf +++ b/bsp/at32/at32f407-start/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/at32/at32f407-start/board/linker_scripts/link.lds b/bsp/at32/at32f407-start/board/linker_scripts/link.lds index 27269dd77ea51e0c09a48af982da401b1cacdc8b..cdf8ad639082ca078b184b88edc48be2ef33d0bf 100644 --- a/bsp/at32/at32f407-start/board/linker_scripts/link.lds +++ b/bsp/at32/at32f407-start/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/at32/at32f413-start/board/linker_scripts/link.icf b/bsp/at32/at32f413-start/board/linker_scripts/link.icf index e4ea2b34d4bb64105de8a0b1543d7edb06f400d2..4435360fce11866e697ef8bdc4d7f5626da28cbd 100644 --- a/bsp/at32/at32f413-start/board/linker_scripts/link.icf +++ b/bsp/at32/at32f413-start/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/at32/at32f413-start/board/linker_scripts/link.lds b/bsp/at32/at32f413-start/board/linker_scripts/link.lds index 3d755e4b430c1d94d8564fe53a967080256dc7c5..c9241466e6e681c5dcea0e7f583e2eb186f4e443 100644 --- a/bsp/at32/at32f413-start/board/linker_scripts/link.lds +++ b/bsp/at32/at32f413-start/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/at32/at32f415-start/board/linker_scripts/link.icf b/bsp/at32/at32f415-start/board/linker_scripts/link.icf index e4ea2b34d4bb64105de8a0b1543d7edb06f400d2..4435360fce11866e697ef8bdc4d7f5626da28cbd 100644 --- a/bsp/at32/at32f415-start/board/linker_scripts/link.icf +++ b/bsp/at32/at32f415-start/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/at32/at32f415-start/board/linker_scripts/link.lds b/bsp/at32/at32f415-start/board/linker_scripts/link.lds index 3d755e4b430c1d94d8564fe53a967080256dc7c5..c9241466e6e681c5dcea0e7f583e2eb186f4e443 100644 --- a/bsp/at32/at32f415-start/board/linker_scripts/link.lds +++ b/bsp/at32/at32f415-start/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/at32/at32f435-start/board/linker_scripts/link.icf b/bsp/at32/at32f435-start/board/linker_scripts/link.icf index 5db573c1089f33077dc26d46f1f2abf8ecd0c55d..03e77791cf229af4a4a5d09d3338c58565a5d535 100644 --- a/bsp/at32/at32f435-start/board/linker_scripts/link.icf +++ b/bsp/at32/at32f435-start/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/at32/at32f435-start/board/linker_scripts/link.lds b/bsp/at32/at32f435-start/board/linker_scripts/link.lds index 4fb708f97a1c00a55a80c005240d27998ac63905..e1780c00f485b1d350348103f1f27d4770bd8c0a 100644 --- a/bsp/at32/at32f435-start/board/linker_scripts/link.lds +++ b/bsp/at32/at32f435-start/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/at32/at32f437-start/board/linker_scripts/link.icf b/bsp/at32/at32f437-start/board/linker_scripts/link.icf index 5db573c1089f33077dc26d46f1f2abf8ecd0c55d..03e77791cf229af4a4a5d09d3338c58565a5d535 100644 --- a/bsp/at32/at32f437-start/board/linker_scripts/link.icf +++ b/bsp/at32/at32f437-start/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/at32/at32f437-start/board/linker_scripts/link.lds b/bsp/at32/at32f437-start/board/linker_scripts/link.lds index 4fb708f97a1c00a55a80c005240d27998ac63905..e1780c00f485b1d350348103f1f27d4770bd8c0a 100644 --- a/bsp/at32/at32f437-start/board/linker_scripts/link.lds +++ b/bsp/at32/at32f437-start/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf index 5c133472cbc9bbeb6031d1b321bf85ac7e091ce4..71df0ba7c27ccb89d6a04f44ebad72ba1bd6d5c0 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf index 4b5ba6a97b22734256f2e19a56e7bab87b623061..8a228f4a4c02117e9475ee6896a7f26abf747474 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf index 97734051a269b4742e85ebe2270f87586cfeac0e..af77afd57013e666e70f926dffe4f0213ab16c81 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf index 5c133472cbc9bbeb6031d1b321bf85ac7e091ce4..71df0ba7c27ccb89d6a04f44ebad72ba1bd6d5c0 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf index 4b5ba6a97b22734256f2e19a56e7bab87b623061..8a228f4a4c02117e9475ee6896a7f26abf747474 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xG.icf b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xG.icf index 97734051a269b4742e85ebe2270f87586cfeac0e..af77afd57013e666e70f926dffe4f0213ab16c81 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xG.icf +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xG.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413x8.icf b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413x8.icf index cd94ed669e0a417940c9d358250713e06ee6d19e..57b2d0d9bd6d31ffd3164051830d793d62b19979 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413x8.icf +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413x8.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xB.icf b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xB.icf index 912235b9c0ddfd0889d72c5767a4025ae5866ccc..8771dcbc344178a58b73ce9fb1994c0cbafd4ca6 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xB.icf +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xB.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xC.icf b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xC.icf index 0f25e9274433b0c22ed82a36f6f1f8f15296686d..b35733b78622573128a875831e69299a12fec326 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xC.icf +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F413xC.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415x8.icf b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415x8.icf index cd94ed669e0a417940c9d358250713e06ee6d19e..57b2d0d9bd6d31ffd3164051830d793d62b19979 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415x8.icf +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415x8.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xB.icf b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xB.icf index 912235b9c0ddfd0889d72c5767a4025ae5866ccc..8771dcbc344178a58b73ce9fb1994c0cbafd4ca6 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xB.icf +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xB.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xC.icf b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xC.icf index 0f25e9274433b0c22ed82a36f6f1f8f15296686d..b35733b78622573128a875831e69299a12fec326 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xC.icf +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F415xC.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xC.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xC.icf index e9b6bd1a08b647b6bf01db50df11d025a9b70e1d..72cf92a0d6ab4ce359beb8c544b22924214c048a 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xC.icf +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xC.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xG.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xG.icf index 690530ac82441d20b2c816edd43449cd2437bf87..f70f3d762f27bc0bcba323234016e3c61ba9c0f7 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xG.icf +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xG.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xM.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xM.icf index 398099a3df50684e0c936c690a12dd1b1080959a..2da95a07e06165dedf9d51338a8a14378a98c259 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xM.icf +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F435xM.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xC.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xC.icf index e9b6bd1a08b647b6bf01db50df11d025a9b70e1d..72cf92a0d6ab4ce359beb8c544b22924214c048a 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xC.icf +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xC.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xG.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xG.icf index 690530ac82441d20b2c816edd43449cd2437bf87..f70f3d762f27bc0bcba323234016e3c61ba9c0f7 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xG.icf +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xG.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xM.icf b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xM.icf index 398099a3df50684e0c936c690a12dd1b1080959a..2da95a07e06165dedf9d51338a8a14378a98c259 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xM.icf +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F437xM.icf @@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/avr32uc3b0/avr32elf_uc3b0256.lds b/bsp/avr32uc3b0/avr32elf_uc3b0256.lds index 3f4ff5705a730647eab256eb10e795ac724958b2..ee86add7a9f306b42821134794881155179cc847 100644 --- a/bsp/avr32uc3b0/avr32elf_uc3b0256.lds +++ b/bsp/avr32uc3b0/avr32elf_uc3b0256.lds @@ -1,6 +1,6 @@ /* Default linker script, for normal executables */ OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", - "elf32-avr32") + "elf32-avr32") OUTPUT_ARCH(avr32:uc) ENTRY(_start) SEARCH_DIR("/home/mingwbuild/mingwavr32/avr32/lib"); @@ -37,10 +37,10 @@ SECTIONS .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH - .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH - .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH - .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH - .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH @@ -85,15 +85,15 @@ SECTIONS .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH - .dalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH + .dalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH PROVIDE (_data = ORIGIN(CPUSRAM)); . = ORIGIN(CPUSRAM); /* Exception handling */ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH /* Thread Local Storage sections */ - .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH - .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM /* Ensure the __preinit_array_start label is properly aligned. We could instead move the label definition inside the section, but the linker would then create the section even if it turns out to @@ -145,7 +145,7 @@ SECTIONS SORT(CONSTRUCTORS) } >CPUSRAM AT>FLASH .data1 : { *(.data1) } >CPUSRAM AT>FLASH - .balign : { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH + .balign : { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH _edata = .; PROVIDE (edata = .); __bss_start = .; diff --git a/bsp/beaglebone/beaglebone_ram.icf b/bsp/beaglebone/beaglebone_ram.icf index dc894bc69f985c2cabba3a066129b454b397da36..d79a7691f73e8f5803a968233b10647561c2bc64 100644 --- a/bsp/beaglebone/beaglebone_ram.icf +++ b/bsp/beaglebone/beaglebone_ram.icf @@ -42,4 +42,4 @@ place at address mem :__ICFEDIT_intvec_start__ {readonly section .intvec}; place in ROM_region { readonly, block RTT_INIT_FUNC }; place in RAM_region { readwrite, block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, - block UND_STACK, block ABT_STACK, block HEAP }; \ No newline at end of file + block UND_STACK, block ABT_STACK, block HEAP }; diff --git a/bsp/beaglebone/beaglebone_ram.lds b/bsp/beaglebone/beaglebone_ram.lds index 5847cb08dd8d5a2dafe05b18a219f137ba855ec4..e5c76f420cee355454e432a0a5efeff253d86640 100644 --- a/bsp/beaglebone/beaglebone_ram.lds +++ b/bsp/beaglebone/beaglebone_ram.lds @@ -20,7 +20,7 @@ SECTIONS __vsymtab_start = .; KEEP(*(VSymTab)) __vsymtab_end = .; - . = ALIGN(4); + . = ALIGN(4); /* section information for modules */ . = ALIGN(4); diff --git a/bsp/bl808/m0/link_stacksize.lds b/bsp/bl808/m0/link_stacksize.lds index 1dd893422c2e9b079747bd857dec99880b056715..28438c7da176095056b52a2249bc20f7407466b9 100644 --- a/bsp/bl808/m0/link_stacksize.lds +++ b/bsp/bl808/m0/link_stacksize.lds @@ -1 +1 @@ -__STACKSIZE__ = 4096; \ No newline at end of file +__STACKSIZE__ = 4096; diff --git a/bsp/bm3803/bm3803.lds b/bsp/bm3803/bm3803.lds index e8984325c163f325550444185be416fc2f084a53..f7bce5908945e40360142f027e823f3ec63ffef9 100644 --- a/bsp/bm3803/bm3803.lds +++ b/bsp/bm3803/bm3803.lds @@ -19,7 +19,7 @@ SECTIONS __vsymtab_start = .; KEEP(*(VSymTab)) __vsymtab_end = .; - . = ALIGN(4); + . = ALIGN(4); /* section information for modules */ . = ALIGN(4); diff --git a/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf b/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf index d8055f6f83425ad47b95397dfb59db0bdab464e0..954163a26a1a8ddf4d2cf3988af87bdc7472c742 100644 --- a/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf +++ b/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf @@ -26,9 +26,9 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, last block HEAP }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, last block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/essemi/es32f369x/drivers/linker_scripts/link.icf b/bsp/essemi/es32f369x/drivers/linker_scripts/link.icf index 34d81247731e81b8f5d384fd1b94ee163a9cb61f..eb0c0f28dcb37e994b26322e3d419138b1622d2a 100644 --- a/bsp/essemi/es32f369x/drivers/linker_scripts/link.icf +++ b/bsp/essemi/es32f369x/drivers/linker_scripts/link.icf @@ -26,9 +26,9 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, last block HEAP }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, last block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/essemi/es32f369x/drivers/linker_scripts/link.lds b/bsp/essemi/es32f369x/drivers/linker_scripts/link.lds index 6843e2a21816a87c031fa7fcb4969531380b0984..44efde1e9075dd1f91615d5101b6928312dab433 100644 --- a/bsp/essemi/es32f369x/drivers/linker_scripts/link.lds +++ b/bsp/essemi/es32f369x/drivers/linker_scripts/link.lds @@ -104,7 +104,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -127,7 +127,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/frdm-k64f/MK64F.sct b/bsp/frdm-k64f/MK64F.sct index 4c91774b2d16596bb1a1a5e60abc232d522b6757..75920a0cd69f6c4ce8cb142721c4b24217a8ca83 100644 --- a/bsp/frdm-k64f/MK64F.sct +++ b/bsp/frdm-k64f/MK64F.sct @@ -1,14 +1,14 @@ - -LR_IROM1 0x00000000 0x100000 { ; load region size_region (1000k) - ER_IROM1 0x00000000 0x100000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198 - ; 0x40000 - 0x198 = 0x3FE68 - RW_IRAM2 0x20000000 0x30000 { - .ANY (+RW +ZI) - } -} - + +LR_IROM1 0x00000000 0x100000 { ; load region size_region (1000k) + ER_IROM1 0x00000000 0x100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198 + ; 0x40000 - 0x198 = 0x3FE68 + RW_IRAM2 0x20000000 0x30000 { + .ANY (+RW +ZI) + } +} + diff --git a/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.icf b/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.icf index 6d0177d0bb33c04f057a4b0f7694a448b6236426..7f352fc72a893b00394e27edf7ee973caf9d70d0 100644 --- a/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.icf +++ b/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.lds b/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.lds index bb905d06b11a9bf5bb15d45e14d2124c559ea888..2292c96e96474c82e228dcf5b52a3c56a966276c 100644 --- a/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.lds +++ b/bsp/ft32/ft32f072xb-starter/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf b/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf index 66b859d099a6ec9ac2bc2a50d847e31e547166e9..26e670978fbe4ac7632d989dab8e3f594e429be7 100644 --- a/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf +++ b/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/gd32/arm/gd32103c-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32103c-eval/board/linker_scripts/link.icf index c1b7bfa18206cfbe632c13362f84ce15a0823d1b..6edb095a6d03724dd52dd23e853256a387cfed50 100644 --- a/bsp/gd32/arm/gd32103c-eval/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32103c-eval/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32105c-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32105c-eval/board/linker_scripts/link.icf index 283881a7285ddd59f52fe022ea12cc95cd60082d..ce253de2382f191ef34c43a13b80884996d82d93 100644 --- a/bsp/gd32/arm/gd32105c-eval/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32105c-eval/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32105r-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32105r-start/board/linker_scripts/link.icf index 283881a7285ddd59f52fe022ea12cc95cd60082d..ce253de2382f191ef34c43a13b80884996d82d93 100644 --- a/bsp/gd32/arm/gd32105r-start/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32105r-start/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32107c-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32107c-eval/board/linker_scripts/link.icf index 283881a7285ddd59f52fe022ea12cc95cd60082d..ce253de2382f191ef34c43a13b80884996d82d93 100644 --- a/bsp/gd32/arm/gd32107c-eval/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32107c-eval/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32205r-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32205r-start/board/linker_scripts/link.icf index ac4747c3cb7b7cf8dcdc9e09d9b8611b1b581629..5bdf74aa6b8c4c0ce0a8a293c15eb086a4a06429 100644 --- a/bsp/gd32/arm/gd32205r-start/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32205r-start/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32207i-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32207i-eval/board/linker_scripts/link.icf index be287f2c06039db68458b899c59cb5c1cebfe584..7b6d8150f0311614963959861e36d997f78438cd 100644 --- a/bsp/gd32/arm/gd32207i-eval/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32207i-eval/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32303c-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32303c-start/board/linker_scripts/link.icf index 4dd2a2010e8e450c1ab498c988dd653aeea58192..654022e7670539692ef7a36df436582918e651fa 100644 --- a/bsp/gd32/arm/gd32303c-start/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32303c-start/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32303e-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32303e-eval/board/linker_scripts/link.icf index f68fd144251883e6da9c885ee98b760227ceff63..2b52bbb04cb9b514cf9c1959a28d9ca770e5d11c 100644 --- a/bsp/gd32/arm/gd32303e-eval/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32303e-eval/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32305r-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32305r-start/board/linker_scripts/link.icf index 283881a7285ddd59f52fe022ea12cc95cd60082d..ce253de2382f191ef34c43a13b80884996d82d93 100644 --- a/bsp/gd32/arm/gd32305r-start/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32305r-start/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32307e-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32307e-start/board/linker_scripts/link.icf index 498c2369e2d5beea10393ba99b13205ec573fda9..53523dab38a0695d42e67420f1d9d18ad2292ee7 100644 --- a/bsp/gd32/arm/gd32307e-start/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32307e-start/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32407v-start/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32407v-start/board/linker_scripts/link.icf index 2dd20cf186c4ce20af16015048d0ed80e668c85b..aab8be6e69faf713c3cbc1e480e8c86ee7e6f645 100644 --- a/bsp/gd32/arm/gd32407v-start/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32407v-start/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32450z-eval/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32450z-eval/board/linker_scripts/link.icf index c32661c11bfe22eb6741c0266cf88a6b65df0681..f6f2f033878e54e92afb849d2227e2c95165b2cb 100644 --- a/bsp/gd32/arm/gd32450z-eval/board/linker_scripts/link.icf +++ b/bsp/gd32/arm/gd32450z-eval/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x4.lds b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x4.lds index fe1d0befb600a5ae9e5b7f444758d295d4d894ec..ab9f7e99b84bd8c96458684f7496f179741db0b6 100644 --- a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x4.lds +++ b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x4.lds @@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" ) ENTRY( _start ) MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k - ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K -*/ +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k + ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K +*/ } @@ -23,18 +23,18 @@ SECTIONS .init : { KEEP (*(SORT_NONE(.init))) - } >flash AT>flash + } >flash AT>flash .ilalign : { . = ALIGN(4); PROVIDE( _ilm_lma = . ); - } >flash AT>flash + } >flash AT>flash .ialign : { PROVIDE( _ilm = . ); - } >flash AT>flash + } >flash AT>flash .text : { @@ -68,12 +68,12 @@ SECTIONS KEEP(*(RTMSymTab)) __rtmsymtab_end = .; - } >flash AT>flash + } >flash AT>flash .fini : { KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); @@ -87,7 +87,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash + } >flash AT>flash .init_array : { @@ -95,7 +95,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash + } >flash AT>flash .fini_array : { @@ -103,7 +103,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash + } >flash AT>flash .ctors : { @@ -125,7 +125,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } >flash AT>flash + } >flash AT>flash .dtors : { @@ -134,7 +134,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); PROVIDE( _eilm = . ); @@ -143,24 +143,24 @@ SECTIONS { . = ALIGN(4); PROVIDE( _data_lma = . ); - } >flash AT>flash + } >flash AT>flash .dalign : { . = ALIGN(4); PROVIDE( _data = . ); - } >ram AT>flash - - + } >ram AT>flash + + .data : { - *(.rdata) - + *(.rdata) + *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); + PROVIDE( __global_pointer$ = . + 0x800); *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); @@ -169,7 +169,7 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram AT>flash + } >ram AT>flash . = ALIGN(4); PROVIDE( _edata = . ); @@ -185,7 +185,7 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); - } >ram AT>ram + } >ram AT>ram . = ALIGN(8); PROVIDE( _end = . ); /*0X2000,0340*/ @@ -193,8 +193,8 @@ SECTIONS .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram } diff --git a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x6.lds b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x6.lds index 4aea1558d269e93aeced53d6a7d59c5007d24f30..b8e0bda6cc59c5d2ef2000bc8d2e72a8ac13cd35 100644 --- a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x6.lds +++ b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x6.lds @@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" ) ENTRY( _start ) MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k - ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K -*/ +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k + ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K +*/ } @@ -23,22 +23,22 @@ SECTIONS .init : { KEEP (*(SORT_NONE(.init))) - } >flash AT>flash + } >flash AT>flash .ilalign : { . = ALIGN(4); PROVIDE( _ilm_lma = . ); - } >flash AT>flash + } >flash AT>flash .ialign : { PROVIDE( _ilm = . ); - } >flash AT>flash + } >flash AT>flash .text : { - *(.rodata .rodata.*) + *(.rodata .rodata.*) *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.*) @@ -68,12 +68,12 @@ SECTIONS KEEP(*(RTMSymTab)) __rtmsymtab_end = .; - } >flash AT>flash + } >flash AT>flash .fini : { KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); @@ -87,7 +87,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash + } >flash AT>flash .init_array : { @@ -95,7 +95,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash + } >flash AT>flash .fini_array : { @@ -103,7 +103,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash + } >flash AT>flash .ctors : { @@ -125,7 +125,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } >flash AT>flash + } >flash AT>flash .dtors : { @@ -134,7 +134,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); PROVIDE( _eilm = . ); @@ -143,24 +143,24 @@ SECTIONS { . = ALIGN(4); PROVIDE( _data_lma = . ); - } >flash AT>flash + } >flash AT>flash .dalign : { . = ALIGN(4); PROVIDE( _data = . ); - } >ram AT>flash - - + } >ram AT>flash + + .data : { - *(.rdata) - + *(.rdata) + *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); + PROVIDE( __global_pointer$ = . + 0x800); *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); @@ -169,7 +169,7 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram AT>flash + } >ram AT>flash . = ALIGN(4); PROVIDE( _edata = . ); @@ -185,7 +185,7 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); - } >ram AT>ram + } >ram AT>ram . = ALIGN(8); PROVIDE( _end = . ); /*0X2000,0340*/ @@ -193,8 +193,8 @@ SECTIONS .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram } diff --git a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x8.lds b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x8.lds index daa03692327d6c77ad51e5487d3f3a322df97b7e..6dd171378ea872ee2bcabd313c634fa398bc0eee 100644 --- a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x8.lds +++ b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x8.lds @@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" ) ENTRY( _start ) MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k - ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K -*/ +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k + ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K +*/ } @@ -23,22 +23,22 @@ SECTIONS .init : { KEEP (*(SORT_NONE(.init))) - } >flash AT>flash + } >flash AT>flash .ilalign : { . = ALIGN(4); PROVIDE( _ilm_lma = . ); - } >flash AT>flash + } >flash AT>flash .ialign : { PROVIDE( _ilm = . ); - } >flash AT>flash + } >flash AT>flash .text : { - *(.rodata .rodata.*) + *(.rodata .rodata.*) *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.*) @@ -68,12 +68,12 @@ SECTIONS KEEP(*(RTMSymTab)) __rtmsymtab_end = .; - } >flash AT>flash + } >flash AT>flash .fini : { KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); @@ -87,7 +87,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash + } >flash AT>flash .init_array : { @@ -95,7 +95,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash + } >flash AT>flash .fini_array : { @@ -103,7 +103,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash + } >flash AT>flash .ctors : { @@ -125,7 +125,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } >flash AT>flash + } >flash AT>flash .dtors : { @@ -134,7 +134,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); PROVIDE( _eilm = . ); @@ -143,24 +143,24 @@ SECTIONS { . = ALIGN(4); PROVIDE( _data_lma = . ); - } >flash AT>flash + } >flash AT>flash .dalign : { . = ALIGN(4); PROVIDE( _data = . ); - } >ram AT>flash - - + } >ram AT>flash + + .data : { - *(.rdata) - + *(.rdata) + *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); + PROVIDE( __global_pointer$ = . + 0x800); *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); @@ -169,7 +169,7 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram AT>flash + } >ram AT>flash . = ALIGN(4); PROVIDE( _edata = . ); @@ -185,7 +185,7 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); - } >ram AT>ram + } >ram AT>ram . = ALIGN(8); PROVIDE( _end = . ); /*0X2000,0340*/ @@ -193,8 +193,8 @@ SECTIONS .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram } diff --git a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103xB.lds b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103xB.lds index 7651c00255f28c292554c404cb42cc4c18d46d46..00d45a99d8474ad631dc50b7e01adb9547f5457c 100644 --- a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103xB.lds +++ b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103xB.lds @@ -3,12 +3,12 @@ OUTPUT_ARCH( "riscv" ) ENTRY( _start ) MEMORY -{ - /* Run in FLASH */ +{ + /* Run in FLASH */ flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K - /* Run in RAM */ + /* Run in RAM */ /* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K */ @@ -23,22 +23,22 @@ SECTIONS .init : { KEEP (*(SORT_NONE(.init))) - } >flash AT>flash + } >flash AT>flash .ilalign : { . = ALIGN(4); PROVIDE( _ilm_lma = . ); - } >flash AT>flash + } >flash AT>flash .ialign : { PROVIDE( _ilm = . ); - } >flash AT>flash + } >flash AT>flash .text : { - *(.rodata .rodata.*) + *(.rodata .rodata.*) *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.*) @@ -67,12 +67,12 @@ SECTIONS __rtmsymtab_start = .; KEEP(*(RTMSymTab)) __rtmsymtab_end = .; - } >flash AT>flash + } >flash AT>flash .fini : { KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); @@ -86,7 +86,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash + } >flash AT>flash .init_array : { @@ -94,7 +94,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash + } >flash AT>flash .fini_array : { @@ -102,7 +102,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash + } >flash AT>flash .ctors : { @@ -124,7 +124,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } >flash AT>flash + } >flash AT>flash .dtors : { @@ -133,7 +133,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); PROVIDE( _eilm = . ); @@ -142,24 +142,24 @@ SECTIONS { . = ALIGN(4); PROVIDE( _data_lma = . ); - } >flash AT>flash + } >flash AT>flash .dalign : { . = ALIGN(4); PROVIDE( _data = . ); - } >ram AT>flash - - + } >ram AT>flash + + .data : { - *(.rdata) - + *(.rdata) + *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); + PROVIDE( __global_pointer$ = . + 0x800); *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); @@ -168,7 +168,7 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram AT>flash + } >ram AT>flash . = ALIGN(4); PROVIDE( _edata = . ); @@ -184,7 +184,7 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); - } >ram AT>ram + } >ram AT>ram . = ALIGN(8); PROVIDE( _end = . ); /*0X2000,0340*/ @@ -192,8 +192,8 @@ SECTIONS .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram } diff --git a/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf b/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf index d6665c3649fc1b5fe92d25e3d24cc59d8b888942..27790e419724b596c002c1ae3f57a3fde45d6d19 100644 --- a/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf +++ b/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf b/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf index d6665c3649fc1b5fe92d25e3d24cc59d8b888942..27790e419724b596c002c1ae3f57a3fde45d6d19 100644 --- a/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf +++ b/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32303e-eval/gd32_rom.icf b/bsp/gd32303e-eval/gd32_rom.icf index d6665c3649fc1b5fe92d25e3d24cc59d8b888942..27790e419724b596c002c1ae3f57a3fde45d6d19 100644 --- a/bsp/gd32303e-eval/gd32_rom.icf +++ b/bsp/gd32303e-eval/gd32_rom.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32350r-eval/gd32_rom.icf b/bsp/gd32350r-eval/gd32_rom.icf index 1741be6a715abe9150b82853f9afc884e55f974f..80461d6dfa101ec5999cd2740bed24c4e4661f2a 100644 --- a/bsp/gd32350r-eval/gd32_rom.icf +++ b/bsp/gd32350r-eval/gd32_rom.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32450z-eval/gd32_rom.icf b/bsp/gd32450z-eval/gd32_rom.icf index 1741be6a715abe9150b82853f9afc884e55f974f..80461d6dfa101ec5999cd2740bed24c4e4661f2a 100644 --- a/bsp/gd32450z-eval/gd32_rom.icf +++ b/bsp/gd32450z-eval/gd32_rom.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32e230k-start/gd32_rom.icf b/bsp/gd32e230k-start/gd32_rom.icf index d6665c3649fc1b5fe92d25e3d24cc59d8b888942..27790e419724b596c002c1ae3f57a3fde45d6d19 100644 --- a/bsp/gd32e230k-start/gd32_rom.icf +++ b/bsp/gd32e230k-start/gd32_rom.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds index fc3d331ede23b761b0e1a2b769b13b8d89f3b4e1..709ed76361d8010b38115cb808ad509f59672964 100644 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds +++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds @@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" ) ENTRY( _start ) MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k - ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K -*/ +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k + ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K +*/ } @@ -23,18 +23,18 @@ SECTIONS .init : { KEEP (*(SORT_NONE(.init))) - } >flash AT>flash + } >flash AT>flash .ilalign : { . = ALIGN(4); PROVIDE( _ilm_lma = . ); - } >flash AT>flash + } >flash AT>flash .ialign : { PROVIDE( _ilm = . ); - } >flash AT>flash + } >flash AT>flash .text : { @@ -43,12 +43,12 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) - } >flash AT>flash + } >flash AT>flash .fini : { KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); @@ -62,7 +62,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash + } >flash AT>flash .init_array : { @@ -70,7 +70,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash + } >flash AT>flash .fini_array : { @@ -78,7 +78,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash + } >flash AT>flash .ctors : { @@ -100,7 +100,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } >flash AT>flash + } >flash AT>flash .dtors : { @@ -109,7 +109,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); PROVIDE( _eilm = . ); @@ -118,24 +118,24 @@ SECTIONS { . = ALIGN(4); PROVIDE( _data_lma = . ); - } >flash AT>flash + } >flash AT>flash .dalign : { . = ALIGN(4); PROVIDE( _data = . ); - } >ram AT>flash - - + } >ram AT>flash + + .data : { - *(.rdata) - + *(.rdata) + *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); + PROVIDE( __global_pointer$ = . + 0x800); *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); @@ -144,7 +144,7 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram AT>flash + } >ram AT>flash . = ALIGN(4); PROVIDE( _edata = . ); @@ -160,7 +160,7 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); - } >ram AT>ram + } >ram AT>ram . = ALIGN(8); PROVIDE( _end = . ); /*0X2000,0340*/ @@ -168,8 +168,8 @@ SECTIONS .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram } diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds index 3cfe58ac5f164566e0eecb1534904f3a2b8c2aff..6d2e894d2857c835eaee13ebc6fef5eb4636111a 100644 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds +++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds @@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" ) ENTRY( _start ) MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k - ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K -*/ +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k + ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K +*/ } @@ -23,32 +23,32 @@ SECTIONS .init : { KEEP (*(SORT_NONE(.init))) - } >flash AT>flash + } >flash AT>flash .ilalign : { . = ALIGN(4); PROVIDE( _ilm_lma = . ); - } >flash AT>flash + } >flash AT>flash .ialign : { PROVIDE( _ilm = . ); - } >flash AT>flash + } >flash AT>flash .text : { - *(.rodata .rodata.*) + *(.rodata .rodata.*) *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) - } >flash AT>flash + } >flash AT>flash .fini : { KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); @@ -62,7 +62,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash + } >flash AT>flash .init_array : { @@ -70,7 +70,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash + } >flash AT>flash .fini_array : { @@ -78,7 +78,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash + } >flash AT>flash .ctors : { @@ -100,7 +100,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } >flash AT>flash + } >flash AT>flash .dtors : { @@ -109,7 +109,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); PROVIDE( _eilm = . ); @@ -118,24 +118,24 @@ SECTIONS { . = ALIGN(4); PROVIDE( _data_lma = . ); - } >flash AT>flash + } >flash AT>flash .dalign : { . = ALIGN(4); PROVIDE( _data = . ); - } >ram AT>flash - - + } >ram AT>flash + + .data : { - *(.rdata) - + *(.rdata) + *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); + PROVIDE( __global_pointer$ = . + 0x800); *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); @@ -144,7 +144,7 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram AT>flash + } >ram AT>flash . = ALIGN(4); PROVIDE( _edata = . ); @@ -160,7 +160,7 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); - } >ram AT>ram + } >ram AT>ram . = ALIGN(8); PROVIDE( _end = . ); /*0X2000,0340*/ @@ -168,8 +168,8 @@ SECTIONS .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram } diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds index a10769dc86755e1168c43706b70fb71b58e292e6..36563311b693f81aafe74b68570a0635c4a9ee69 100644 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds +++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds @@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" ) ENTRY( _start ) MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k - ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K -*/ +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k + ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K +*/ } @@ -23,32 +23,32 @@ SECTIONS .init : { KEEP (*(SORT_NONE(.init))) - } >flash AT>flash + } >flash AT>flash .ilalign : { . = ALIGN(4); PROVIDE( _ilm_lma = . ); - } >flash AT>flash + } >flash AT>flash .ialign : { PROVIDE( _ilm = . ); - } >flash AT>flash + } >flash AT>flash .text : { - *(.rodata .rodata.*) + *(.rodata .rodata.*) *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) - } >flash AT>flash + } >flash AT>flash .fini : { KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); @@ -62,7 +62,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash + } >flash AT>flash .init_array : { @@ -70,7 +70,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash + } >flash AT>flash .fini_array : { @@ -78,7 +78,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash + } >flash AT>flash .ctors : { @@ -100,7 +100,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } >flash AT>flash + } >flash AT>flash .dtors : { @@ -109,7 +109,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); PROVIDE( _eilm = . ); @@ -118,24 +118,24 @@ SECTIONS { . = ALIGN(4); PROVIDE( _data_lma = . ); - } >flash AT>flash + } >flash AT>flash .dalign : { . = ALIGN(4); PROVIDE( _data = . ); - } >ram AT>flash - - + } >ram AT>flash + + .data : { - *(.rdata) - + *(.rdata) + *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); + PROVIDE( __global_pointer$ = . + 0x800); *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); @@ -144,7 +144,7 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram AT>flash + } >ram AT>flash . = ALIGN(4); PROVIDE( _edata = . ); @@ -160,7 +160,7 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); - } >ram AT>ram + } >ram AT>ram . = ALIGN(8); PROVIDE( _end = . ); /*0X2000,0340*/ @@ -168,8 +168,8 @@ SECTIONS .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram } diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds index 45b93cf8ebf6be84206fd379b46f654750836152..3ea227b113d1ae4546e81ebb3c135198b3a6c4a1 100644 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds +++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds @@ -3,12 +3,12 @@ OUTPUT_ARCH( "riscv" ) ENTRY( _start ) MEMORY -{ - /* Run in FLASH */ +{ + /* Run in FLASH */ flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K - /* Run in RAM */ + /* Run in RAM */ /* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K */ @@ -23,27 +23,27 @@ SECTIONS .init : { KEEP (*(SORT_NONE(.init))) - } >flash AT>flash + } >flash AT>flash .ilalign : { . = ALIGN(4); PROVIDE( _ilm_lma = . ); - } >flash AT>flash + } >flash AT>flash .ialign : { PROVIDE( _ilm = . ); - } >flash AT>flash + } >flash AT>flash .text : { - *(.rodata .rodata.*) + *(.rodata .rodata.*) *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) - + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -54,7 +54,7 @@ SECTIONS KEEP(*(VSymTab)) __vsymtab_end = .; . = ALIGN(4); - + /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; @@ -67,12 +67,12 @@ SECTIONS __rtmsymtab_start = .; KEEP(*(RTMSymTab)) __rtmsymtab_end = .; - } >flash AT>flash + } >flash AT>flash .fini : { KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); @@ -86,7 +86,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash + } >flash AT>flash .init_array : { @@ -94,7 +94,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash + } >flash AT>flash .fini_array : { @@ -102,7 +102,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash + } >flash AT>flash .ctors : { @@ -124,7 +124,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } >flash AT>flash + } >flash AT>flash .dtors : { @@ -133,7 +133,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); PROVIDE( _eilm = . ); @@ -142,24 +142,24 @@ SECTIONS { . = ALIGN(4); PROVIDE( _data_lma = . ); - } >flash AT>flash + } >flash AT>flash .dalign : { . = ALIGN(4); PROVIDE( _data = . ); - } >ram AT>flash - - + } >ram AT>flash + + .data : { - *(.rdata) - + *(.rdata) + *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); + PROVIDE( __global_pointer$ = . + 0x800); *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); @@ -168,7 +168,7 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram AT>flash + } >ram AT>flash . = ALIGN(4); PROVIDE( _edata = . ); @@ -184,7 +184,7 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); - } >ram AT>ram + } >ram AT>ram . = ALIGN(8); PROVIDE( _end = . ); /*0X2000,0340*/ @@ -192,8 +192,8 @@ SECTIONS .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram } diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds index f273c1930d6e212d1a7e61edfe452e33b9e0a7c9..cfb0b88107151eaa30f35ae67808c3ba8f62bcc6 100644 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds +++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds @@ -3,15 +3,15 @@ OUTPUT_ARCH( "riscv" ) ENTRY( _start ) MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k - ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K -*/ +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k + ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K +*/ } @@ -23,39 +23,39 @@ SECTIONS .init : { KEEP (*(SORT_NONE(.init))) - } >flash AT>flash + } >flash AT>flash .ilalign : { . = ALIGN(4); PROVIDE( _ilm_lma = . ); - } >flash AT>flash + } >flash AT>flash .ialign : { PROVIDE( _ilm = . ); - } >flash AT>flash + } >flash AT>flash .PrgData ALIGN(0x08004000,4) : AT(ALIGN(0x08004000,4)) { - KEEP(*(.PrgData)) + KEEP(*(.PrgData)) } - + .text : { - *(.rodata .rodata.*) + *(.rodata .rodata.*) *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) *(.sdata2 .sdata2. *) - } >flash AT>flash + } >flash AT>flash + - .fini : { KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); @@ -69,7 +69,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash + } >flash AT>flash .init_array : { @@ -77,7 +77,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash + } >flash AT>flash .fini_array : { @@ -85,7 +85,7 @@ SECTIONS KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash + } >flash AT>flash .ctors : { @@ -107,7 +107,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } >flash AT>flash + } >flash AT>flash .dtors : { @@ -116,7 +116,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } >flash AT>flash + } >flash AT>flash . = ALIGN(4); PROVIDE( _eilm = . ); @@ -125,24 +125,24 @@ SECTIONS { . = ALIGN(4); PROVIDE( _data_lma = . ); - } >flash AT>flash + } >flash AT>flash .dalign : { . = ALIGN(4); PROVIDE( _data = . ); - } >ram AT>flash - - + } >ram AT>flash + + .data : { - *(.rdata) - + *(.rdata) + *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); + PROVIDE( __global_pointer$ = . + 0x800); *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); @@ -151,7 +151,7 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram AT>flash + } >ram AT>flash . = ALIGN(4); PROVIDE( _edata = . ); @@ -167,7 +167,7 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); - } >ram AT>ram + } >ram AT>ram . = ALIGN(8); PROVIDE( _end = . ); /*0X2000,0340*/ @@ -175,8 +175,8 @@ SECTIONS .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram } diff --git a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf index 3ac4e24e1827160ea0e7aaa1eedbdda674b4a132..315cad68eb6577ad1dd13dc7796a40b6cfe4aace 100644 --- a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf +++ b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf @@ -55,4 +55,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf index 3ee43c73cd40dfcff919a7bec87be2bc27e362ff..d4ab64ed605a49f53df8deae5d0d53d9063b9e63 100644 --- a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf +++ b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf @@ -47,4 +47,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf index 5f0edccc159b34335a62c33b26c59310964588e5..0ad9e89f73b82024fc298365a06f2e7c289accd8 100644 --- a/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf +++ b/bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf @@ -47,4 +47,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf index dcc0be6376b9406a6a4e45579ef37a71cff52172..502ad34f4156eee54b55283aa14cbf2de81a1297 100644 --- a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf @@ -53,4 +53,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf index e938594387b2025b34a36881e3594013f30e8dda..41073ed6b2901938e691389d3b3ba48114ae5ad8 100644 --- a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf @@ -47,4 +47,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf index 35a29c5fa18f2d2b4a6a275f496beb2e29d83ec9..8d2005dff40ef61aeb5a29905a3b96229bc25203 100644 --- a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf @@ -47,4 +47,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf index 73c070bfb5b807dc92be28afc2bc38b0e306744a..c1553e99ec38b6627cb6a28e475d6238cb382341 100644 --- a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf @@ -48,4 +48,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf index 159df7daa494b58138225e0deade1a99fb0f200c..23fbf9cbbf927db0a4df7e555b58c3a126df8467 100644 --- a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf @@ -50,4 +50,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in QSPI_region { readonly section .ex_rom }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf index 82734efbd660819882c573f894565f7c7c5e391d..4dec7d352ba32e0b5e180dc55f9d6dc828c43ac2 100644 --- a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf @@ -50,4 +50,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in QSPI_region { readonly section .ex_rom }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf index 73c070bfb5b807dc92be28afc2bc38b0e306744a..c1553e99ec38b6627cb6a28e475d6238cb382341 100644 --- a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf @@ -48,4 +48,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf index 735d43311ff0fd125aea781490fdfdabf2bbf1e0..393abcb073316fb86be3f578ca36ab542f6eea1a 100644 --- a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf @@ -48,4 +48,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf index b47254e04e679cb7c0da54b452a6e80b296a3f8e..f653427843e1dd4415712a665f91fe7de189b374 100644 --- a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf @@ -48,4 +48,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/hc32l136/board/linker_scripts/link.icf b/bsp/hc32l136/board/linker_scripts/link.icf index 719e8b673ce51c5e6cd38431e003d76f5d996dae..6907c5dc5b64eac393e9e2a93ed69b05410acfc1 100644 --- a/bsp/hc32l136/board/linker_scripts/link.icf +++ b/bsp/hc32l136/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/hc32l196/board/linker_scripts/link.lds b/bsp/hc32l196/board/linker_scripts/link.lds index fc5b6197af1c64a82ff7fa4fd4eae385381000e3..3b5c615c7a47904ac3434da83417f826a37bfcac 100644 --- a/bsp/hc32l196/board/linker_scripts/link.lds +++ b/bsp/hc32l196/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds index 90415e319a0ef05dc7db5c4acd3be1aff893cc6d..3cd31802737f740e81479f55f6d929633b88017b 100644 --- a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds +++ b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds @@ -30,7 +30,7 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) - + /* section information for finsh shell */ . = ALIGN(4); diff --git a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds index 54c102641e504d84919485609175ded99c08652a..c571a0f87690bfc6d5fa93a69931b6bc792eb187 100644 --- a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds +++ b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds @@ -1 +1 @@ -../coreplexip-e31-arty/flash.lds \ No newline at end of file +../coreplexip-e31-arty/flash.lds diff --git a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds index 7fbe10a3ea2ed41021381aa4940105a23e2c3c87..f7f33b8de2bd8b48e6cc54714d6e6024072a758c 100644 --- a/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds +++ b/bsp/hifive1/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds @@ -1 +1 @@ -../coreplexip-e31-arty/scratchpad.lds \ No newline at end of file +../coreplexip-e31-arty/scratchpad.lds diff --git a/bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds b/bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds index 6441ce598f221f1a5b3373fdebe7f4fe809d00aa..9661121ef7308ccaaf7e04ad457ad7a0824c6150 100644 --- a/bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds +++ b/bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds @@ -1 +1 @@ -../freedom-e300-hifive1/flash.lds \ No newline at end of file +../freedom-e300-hifive1/flash.lds diff --git a/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.icf b/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.icf index a40b9d422b241d20c40e01b463067f394998d3dc..a9511546b7a2bef31e503c654c70e62b77679e5e 100644 --- a/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.icf +++ b/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.lds b/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.lds index 90a0df7e4737330d9531ac816bc1e5d566db1012..88f67766bddfa1ded10399f2f8b81377f38fc806 100644 --- a/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.lds +++ b/bsp/hk32/hk32f030c8-mini/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf index 1e87e297e25cb0aecfc7284f17ecc926062115cc..846a935841c9c5ee5366ee331beeb35c5775af35 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf @@ -1,89 +1,89 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x0 size 128k]; /* ILM */ -define region DLM = [from 0x80000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 256k]; -define region SDRAM = [from 0x40000000 size _extram_size]; -define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM_SLV with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in DLM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack }; // Stack reserved block at the end -place at end of DLM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ +define region ILM = [from 0x0 size 128k]; /* ILM */ +define region DLM = [from 0x80000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 256k]; +define region SDRAM = [from 0x40000000 size _extram_size]; +define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM_SLV with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in DLM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack }; // Stack reserved block at the end +place at end of DLM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf index 75b1221ad9973e4680d2ef421735e72c1bffb294..e2e66adf50284bb1c642371addbf60d9c3845205 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf @@ -1,85 +1,85 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH ]; -define region AXI_SRAM = [from 0x1040000 size 768K]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order {symbol _start}; -keep { section .uf2_signature }; - -place at start of AXI_SRAM with fixed order { block vectors, block vectors_s }; -initialize by copy { block vectors, block vectors_s }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in SDRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SDRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH ]; +define region AXI_SRAM = [from 0x1040000 size 768K]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order {symbol _start}; +keep { section .uf2_signature }; + +place at start of AXI_SRAM with fixed order { block vectors, block vectors_s }; +initialize by copy { block vectors, block vectors_s }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in SDRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SDRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf index 3f5bc4fb5628677dc5e5f07ab3f8552ab7ae4bd1..99ca6bbe92148c6335b3dd6b8aef867e4f8bcef1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf @@ -1,98 +1,98 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x0 size 256K]; -define region DLM = [from 0x80000 size 256K]; -define region AXI_SRAM = [from 0x1080000 size 512K]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM with fixed order { block vectors, block vectors_s }; -initialize by copy { block vectors, block vectors_s }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM with auto order { block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in SDRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SDRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM = [from 0x0 size 256K]; +define region DLM = [from 0x80000 size 256K]; +define region AXI_SRAM = [from 0x1080000 size 512K]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM with fixed order { block vectors, block vectors_s }; +initialize by copy { block vectors, block vectors_s }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in AXI_SRAM with auto order { block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in SDRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SDRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf index 87188c823cb973a16c1739d3ddc645671c255355..9e99e1e75320f9bd604d8ac0c6c548627dd18968 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf @@ -1,87 +1,87 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0 size 128k]; /* ILM slave */ -define region DLM = [from 0x80000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order {symbol _start}; -keep { section .uf2_signature }; - -place at start of ILM with fixed order { block vectors, block vectors_s }; -initialize by copy { block vectors, block vectors_s }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in DLM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region ILM = [from 0 size 128k]; /* ILM slave */ +define region DLM = [from 0x80000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 256k]; +define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order {symbol _start}; +keep { section .uf2_signature }; + +place at start of ILM with fixed order { block vectors, block vectors_s }; +initialize by copy { block vectors, block vectors_s }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in DLM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf index eee3e8a6c2dd4117faace2d924a90d6adddc99d7..8ead4f2e241809f10a6d44841b0225b365b0d50c 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf @@ -1,98 +1,98 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0 size 128k]; /* ILM */ -define region DLM = [from 0x80000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM with fixed order { block vectors, block vectors_s }; -initialize by copy { block vectors, block vectors_s }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section - -place in DLM with auto order { block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM = [from 0 size 128k]; /* ILM */ +define region DLM = [from 0x80000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 256k]; +define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM with fixed order { block vectors, block vectors_s }; +initialize by copy { block vectors, block vectors_s }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section + +place in DLM with auto order { block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf index 94e0dae066b09eacf5c12af44bc019c6a7201f57..c6181821471b3ec084150b3150fb52c752ed486d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf @@ -1,78 +1,78 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0 size 128k]; /* ILM */ -define region RAM = [from 0x80000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x10C0000 size 256K]; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack = end of block stack + 1; -define block safe_stack with size = 512, readwrite access {}; -define exported symbol _stack_safe = end of block safe_stack + 1; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block framebuffer { section .framebuffer }; - - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -/* Explicit placement in AXI_SRAM */ -place in AXI_SRAM { block framebuffer }; - -place in RAM with auto order { section .fast, section .fast.*, // "ramfunc" section - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in RAM { block heap }; // Heap reserved block -place at end of RAM { block stack, block safe_stack }; // Stack reserved block at the end +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region ILM = [from 0 size 128k]; /* ILM */ +define region RAM = [from 0x80000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 256k]; +define region NONCACHEABLE_RAM = [from 0x10C0000 size 256K]; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack = end of block stack + 1; +define block safe_stack with size = 512, readwrite access {}; +define exported symbol _stack_safe = end of block safe_stack + 1; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block framebuffer { section .framebuffer }; + + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of ILM { symbol _start }; +place in ILM { block vectors, block vectors_s }; // Vector table section +place in ILM with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +/* Explicit placement in AXI_SRAM */ +place in AXI_SRAM { block framebuffer }; + +place in RAM with auto order { section .fast, section .fast.*, // "ramfunc" section + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in RAM { block heap }; // Heap reserved block +place at end of RAM { block stack, block safe_stack }; // Stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf index fd9b3a0a9d434d080a062c733032023c6ccb13ab..7e28e152c6c002f36cc71991abd2165cb26e9c8e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf @@ -1,89 +1,89 @@ -/* - * Copyright 2021-2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ -define region DLM = [from 0x80000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 768k]; -define region SDRAM = [from 0x40000000 size _extram_size]; -define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM_SLV with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM_SLV { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in DLM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack }; // Stack reserved block at the end -place at end of DLM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright 2021-2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ +define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ +define region DLM = [from 0x80000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 768k]; +define region SDRAM = [from 0x40000000 size _extram_size]; +define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM_SLV with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM_SLV { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in DLM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack }; // Stack reserved block at the end +place at end of DLM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf index 962c865fa6ad898d390a48a8f522c27b1bc7414b..854e22e2071fc2315cc8e7bb4b1429d8515e2ac3 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf @@ -1,85 +1,85 @@ -/* - * Copyright 2021-2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region AXI_SRAM = [from 0x1000000 size 2M]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order {symbol _start}; -keep { section .uf2_signature }; - -place at start of AXI_SRAM with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in SDRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SDRAM { block heap }; // Heap reserved block -place at end of SDRAM { block stack }; // Stack reserved block at the end -place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright 2021-2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region AXI_SRAM = [from 0x1000000 size 2M]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order {symbol _start}; +keep { section .uf2_signature }; + +place at start of AXI_SRAM with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in SDRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SDRAM { block heap }; // Heap reserved block +place at end of SDRAM { block stack }; // Stack reserved block at the end +place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf index da4cec78f1b2bc5713d8945d80eeacd9fc7f3741..23f6c2d9682580491d99ea42b60e9385d8b4e76a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf @@ -1,96 +1,96 @@ -/* - * Copyright 2021 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region AXI_SRAM = [from 0x1000000 size 2M]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; - -place at start of AXI_SRAM with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in SDRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SDRAM { block heap }; // Heap reserved block -place at end of SDRAM { block stack }; // Stack reserved block at the end -place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region AXI_SRAM = [from 0x1000000 size 2M]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start}; + +place at start of AXI_SRAM with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in SDRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SDRAM { block heap }; // Heap reserved block +place at end of SDRAM { block stack }; // Stack reserved block at the end +place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf index 0ecf3ae29290a0f4c43bdd7e9915679e9aa6049f..fe190a9225148bf803339817be4cc6a2f1fcd1ee 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf @@ -1,92 +1,92 @@ -/* - * Copyright 2021-2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ -define region DLM = [from 0x80000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 768k]; -define region SDRAM = [from 0x40000000 size _extram_size]; -define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order {symbol _start}; -keep { section .uf2_signature }; - -place at start of ILM_SLV with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM_SLV { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in DLM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack }; // Stack reserved block at the end -place at end of DLM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright 2021-2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ +define region DLM = [from 0x80000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 768k]; +define region SDRAM = [from 0x40000000 size _extram_size]; +define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order {symbol _start}; +keep { section .uf2_signature }; + +place at start of ILM_SLV with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM_SLV { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in DLM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack }; // Stack reserved block at the end +place at end of DLM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf index 4905f88846f70a5a35214290da498b2334a71234..273c6b0a38e104020c99ed13644e1caef0f08de0 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf @@ -1,103 +1,103 @@ -/* - * Copyright 2021 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ -define region DLM = [from 0x80000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 768k]; -define region SDRAM = [from 0x40000000 size _extram_size]; -define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM_SLV with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM_SLV { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in DLM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack }; // Stack reserved block at the end -place at end of DLM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ +define region DLM = [from 0x80000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 768k]; +define region SDRAM = [from 0x40000000 size _extram_size]; +define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM_SLV with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM_SLV { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in DLM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack }; // Stack reserved block at the end +place at end of DLM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf index 25e32ed3f7b9d23a0306903159319f111f9d2f93..28076234d26bddf8fd4d49754bfb4e4afe79f3ef 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf @@ -1,79 +1,79 @@ -/* - * Copyright 2021 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */ -define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */ -define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */ -define region NONCACHEABLE_RAM = [from 0x1140000 size 256K]; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack = end of block stack + 1; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block framebuffer { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; -define exported symbol _stack_safe = end of block safe_stack + 1; - - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of CORE0_LM_SLV { symbol _start }; -place in CORE0_LM_SLV { block vectors }; // Vector table section -place in CORE0_LM_SLV with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec, // Catch-all for (readonly) executable code (e.g. .text) - section .fast, section .fast.*, // "ramfunc" section - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -/* Explicit placement in AXI_SRAM */ -place in AXI_SRAM { block framebuffer }; - -place in AXI_SRAM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */ +define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */ +define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */ +define region NONCACHEABLE_RAM = [from 0x1140000 size 256K]; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack = end of block stack + 1; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block framebuffer { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; +define exported symbol _stack_safe = end of block safe_stack + 1; + + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of CORE0_LM_SLV { symbol _start }; +place in CORE0_LM_SLV { block vectors }; // Vector table section +place in CORE0_LM_SLV with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec, // Catch-all for (readonly) executable code (e.g. .text) + section .fast, section .fast.*, // "ramfunc" section + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +/* Explicit placement in AXI_SRAM */ +place in AXI_SRAM { block framebuffer }; + +place in AXI_SRAM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf index 600e3a16ca7abebc1e3242dcc1f32140f76bce62..e7617c78e7c1264f01652e93a78f2a5b58e888ca 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf @@ -1,79 +1,79 @@ -/* - * Copyright 2021 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */ -define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */ -define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */ -define region NONCACHEABLE_RAM = [from 0x1140000 size 256K]; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack = end of block stack + 1; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block framebuffer { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; -define exported symbol _stack_safe = end of block safe_stack + 1; - - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of CORE1_LM_SLV { symbol _start }; -place in CORE1_LM_SLV { block vectors }; // Vector table section -place in CORE1_LM_SLV with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec, // Catch-all for (readonly) executable code (e.g. .text) - section .fast, section .fast.*, // "ramfunc" section - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -/* Explicit placement in AXI_SRAM */ -place in AXI_SRAM { block framebuffer }; - -place in AXI_SRAM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */ +define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */ +define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */ +define region NONCACHEABLE_RAM = [from 0x1140000 size 256K]; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack = end of block stack + 1; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block framebuffer { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; +define exported symbol _stack_safe = end of block safe_stack + 1; + + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of CORE1_LM_SLV { symbol _start }; +place in CORE1_LM_SLV { block vectors }; // Vector table section +place in CORE1_LM_SLV with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec, // Catch-all for (readonly) executable code (e.g. .text) + section .fast, section .fast.*, // "ramfunc" section + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +/* Explicit placement in AXI_SRAM */ +place in AXI_SRAM { block framebuffer }; + +place in AXI_SRAM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf index 0f11aa45cb7ab37cc9c5cc9d352ac2363767cae8..1563925f19ff0a4fbb9da8373a004463d0020d36 100644 --- a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf +++ b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.icf @@ -1,127 +1,127 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x60002000; -define symbol m_interrupts_end = 0x600023FF; - -define symbol m_itcm_start = 0x00000000; -define symbol m_itcm_end = 0x0001FFFF; - -define symbol m_spiflash_start = 0x60002400; -define symbol m_spiflash_end = 0x7F7FFFFF; - -define symbol m_dtcm_start = 0x20000000; -define symbol m_dtcm_end = 0x2001FFFF;/* DTCM 128KB */ - -define symbol m_ocram_start = 0x20200000; -define symbol m_ocram_end = 0x2020FFFF;/* OCRAM 64KB */ - -define symbol m_sdram_start = 0x80000000; -define symbol m_sdram_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -define exported symbol m_boot_hdr_conf_start = 0x60000000; -define symbol m_boot_hdr_ivt_start = 0x60001000; -define symbol m_boot_hdr_boot_data_start = 0x60001020; -define symbol m_boot_hdr_dcd_data_start = 0x60001030; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; -define exported symbol __RTT_HEAP_END = m_dtcm_end; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_spiflash_start to m_spiflash_end]; - -define region ITCM_region = mem:[from m_itcm_start to m_itcm_end]; -define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end]; -define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; -define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw}; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; -place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; -place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; -place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; - -keep { section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; - -place in TEXT_region { readonly }; -place in DTCM_region { block RW }; -place in DTCM_region { block ZI }; -place in DTCM_region { last block HEAP }; -place in DTCM_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; \ No newline at end of file +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_end = 0x0001FFFF; + +define symbol m_spiflash_start = 0x60002400; +define symbol m_spiflash_end = 0x7F7FFFFF; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_end = 0x2001FFFF;/* DTCM 128KB */ + +define symbol m_ocram_start = 0x20200000; +define symbol m_ocram_end = 0x2020FFFF;/* OCRAM 64KB */ + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; +define exported symbol __RTT_HEAP_END = m_dtcm_end; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_spiflash_start to m_spiflash_end]; + +define region ITCM_region = mem:[from m_itcm_start to m_itcm_end]; +define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end]; +define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw}; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep { section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; +keep { section FSymTab }; +keep { section VSymTab }; +keep { section .rti_fn* }; + +place in TEXT_region { readonly }; +place in DTCM_region { block RW }; +place in DTCM_region { block ZI }; +place in DTCM_region { last block HEAP }; +place in DTCM_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds index 7ef0bb392ea0b49fb80476a3049a258d1fadadde..cf0b16b7b9804da8924fcbfcab81d885d95d763e 100644 --- a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.lds @@ -260,7 +260,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct index d6a1f800568d93c450140e00a1a3a32e9cd7fe1f..24ecc854aa2b6e7e0c6c345a749e8b8258723036 100644 --- a/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct @@ -1,134 +1,134 @@ -#! armcc -E -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_flash_config_start 0x60000000 -#define m_flash_config_size 0x00001000 - -#define m_ivt_start 0x60001000 -#define m_ivt_size 0x00001000 - -#define m_text_start 0x60002000 -#define m_text_size 0x007FE000 - -#define m_data_start 0x20000000 -#define m_data_size 0x00020000 - -#define m_ncache_start 0x81E00000 -#define m_ncache_size 0x00200000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x1000 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#include "../../rtconfig.h" -;BSP_USING_HYPERFLASH -#if (defined(BOARD_USING_QSPIFLASH)) -LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region -{ - RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address - { - * (.boot_hdr.conf, +FIRST) - } -} - -LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region -{ - RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address - { - * (.boot_hdr.ivt, +FIRST) - * (.boot_hdr.boot_data) - * (.boot_hdr.dcd_data) - } -} -#endif - -#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) - -; load region size_region -LR_IROM1 m_text_start m_text_size -{ - ER_IROM1 m_text_start m_text_size ; load address = execution address - { - * (RESET,+FIRST) - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up - ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down - RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} - - ; ncache RW data - RW_m_ncache m_ncache_start m_ncache_size - { - * (NonCacheable.init) - * (NonCacheable) - } - ITCM 0x400 0xFBFF { - ;drv_flexspi_hyper.o(+RO) - ;fsl_flexspi.o(+RO) - * (*CLOCK_DisableClock) - * (*CLOCK_ControlGate) - * (*CLOCK_EnableClock) - * (*CLOCK_SetDiv) - * (itcm) - } -} +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_text_start 0x60002000 +#define m_text_size 0x007FE000 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#include "../../rtconfig.h" +;BSP_USING_HYPERFLASH +#if (defined(BOARD_USING_QSPIFLASH)) +LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region +{ + RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address + { + * (.boot_hdr.conf, +FIRST) + } +} + +LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region +{ + RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address + { + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +} +#endif + +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) + +; load region size_region +LR_IROM1 m_text_start m_text_size +{ + ER_IROM1 m_text_start m_text_size ; load address = execution address + { + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} + + ; ncache RW data + RW_m_ncache m_ncache_start m_ncache_size + { + * (NonCacheable.init) + * (NonCacheable) + } + ITCM 0x400 0xFBFF { + ;drv_flexspi_hyper.o(+RO) + ;fsl_flexspi.o(+RO) + * (*CLOCK_DisableClock) + * (*CLOCK_ControlGate) + * (*CLOCK_EnableClock) + * (*CLOCK_SetDiv) + * (itcm) + } +} diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds index b8c229ae3cc7681902fc706b48ec7d4a1bb8f503..d21ddb6a790d637a2451a2da5c34648c0208ce35 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.lds @@ -261,7 +261,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct index 7200f9d4792bf976248173664aa5941422e874c8..ef0ddf80f32245d776e70bd48cd6ce10c168e23d 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1052-atk-commander/board/linker_scripts/link.sct @@ -76,27 +76,27 @@ #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) ; load region size_region -LR_IROM1 m_text_start m_text_size -{ +LR_IROM1 m_text_start m_text_size +{ ER_IROM1 m_text_start m_text_size ; load address = execution address - { + { * (RESET,+FIRST) * (InRoot$$Sections) .ANY (+RO) } - + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { + { .ANY (+RW +ZI) } - + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data - RW_m_ncache m_ncache_start m_ncache_size - { + RW_m_ncache m_ncache_start m_ncache_size + { * (NonCacheable.init) * (NonCacheable) } diff --git a/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds index f585fbced86fdde99559d0c55cb807b50db29825..1e11ddc014bc01a4de272ca47cd67faea422321a 100644 --- a/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds @@ -86,9 +86,9 @@ SECTIONS .ivt : AT(ivt_begin) { . = ALIGN(4); - KEEP(* (.boot_hdr.ivt)) /* ivt section */ - KEEP(* (.boot_hdr.boot_data)) /* boot section */ - KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ . = ALIGN(4); } > m_ivt @@ -278,7 +278,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_data - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds index b8c229ae3cc7681902fc706b48ec7d4a1bb8f503..d21ddb6a790d637a2451a2da5c34648c0208ce35 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.lds @@ -261,7 +261,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct index 654c165f02e00a5f8f8a4f349276b1f0e3216e58..9e7f6546d29570e652dacfbce16427f05f1312fc 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct @@ -77,58 +77,58 @@ #if (defined(BSP_USING_HYPERFLASH)) LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region -{ +{ RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address - { + { * (.boot_hdr.conf, +FIRST) - } + } } LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region -{ +{ RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address - { + { * (.boot_hdr.ivt, +FIRST) * (.boot_hdr.boot_data) * (.boot_hdr.dcd_data) - } + } } #endif #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) ; load region size_region -LR_IROM1 m_text_start m_text_size -{ +LR_IROM1 m_text_start m_text_size +{ ER_IROM1 m_text_start m_text_size ; load address = execution address - { + { * (RESET,+FIRST) * (InRoot$$Sections) .ANY (+RO) } - + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { + { .ANY (+RW +ZI) } - + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data - RW_m_ncache m_ncache_start m_ncache_size - { + RW_m_ncache m_ncache_start m_ncache_size + { * (NonCacheable.init) * (NonCacheable) } ITCM 0x400 0xFBFF { - ;drv_flexspi_hyper.o(+RO) - ;fsl_flexspi.o(+RO) - * (*CLOCK_DisableClock) - * (*CLOCK_ControlGate) - * (*CLOCK_EnableClock) - * (*CLOCK_SetDiv) - * (itcm) - } + ;drv_flexspi_hyper.o(+RO) + ;fsl_flexspi.o(+RO) + * (*CLOCK_DisableClock) + * (*CLOCK_ControlGate) + * (*CLOCK_EnableClock) + * (*CLOCK_SetDiv) + * (itcm) + } } diff --git a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds index b8c229ae3cc7681902fc706b48ec7d4a1bb8f503..d21ddb6a790d637a2451a2da5c34648c0208ce35 100644 --- a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds @@ -261,7 +261,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct index 7200f9d4792bf976248173664aa5941422e874c8..ef0ddf80f32245d776e70bd48cd6ce10c168e23d 100644 --- a/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct @@ -76,27 +76,27 @@ #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) ; load region size_region -LR_IROM1 m_text_start m_text_size -{ +LR_IROM1 m_text_start m_text_size +{ ER_IROM1 m_text_start m_text_size ; load address = execution address - { + { * (RESET,+FIRST) * (InRoot$$Sections) .ANY (+RO) } - + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { + { .ANY (+RW +ZI) } - + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data - RW_m_ncache m_ncache_start m_ncache_size - { + RW_m_ncache m_ncache_start m_ncache_size + { * (NonCacheable.init) * (NonCacheable) } diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds index 0691d0fe48e5d692ad00246c5ef0f1021d57e378..ab64f3ef3794709471e60ac0e204b41e3dcf84ee 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds @@ -268,7 +268,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_sdram - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds index 9942889d58e10bd05fbed69cb196c546fc5ace5d..169a2d310a9d75f6872c9b447886c72233e41f1a 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.lds @@ -268,7 +268,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct index f36201c200fd2748e477de0b7e10f324255fbdb5..d2a77d731917f419e17819fd4d45c771871d7a4f 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct @@ -86,48 +86,48 @@ #if (defined(BSP_USING_4MFLASH)) LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region -{ +{ RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address - { + { * (.boot_hdr.conf, +FIRST) - } + } } LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region -{ +{ RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address - { + { * (.boot_hdr.ivt, +FIRST) * (.boot_hdr.boot_data) * (.boot_hdr.dcd_data) - } + } } #endif #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) ; load region size_region -LR_IROM1 m_text_start m_text_size -{ +LR_IROM1 m_text_start m_text_size +{ ER_IROM1 m_text_start m_text_size ; load address = execution address - { + { * (RESET,+FIRST) * (InRoot$$Sections) .ANY (+RO) } - + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { + { .ANY (+RW +ZI) } - + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data RW_m_ncache m_ncache_start m_ncache_size - { + { * (NonCacheable.init) * (NonCacheable) } diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf index a3a39c47317e1c7b6725f86ab202ff02c16bb1fc..497e6285c5c046d57192a3941701c1aa9ca2fadb 100644 --- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf +++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor.icf @@ -1,93 +1,93 @@ -/* -** ################################################################### -** Processors: MIMXRT1021CAF4A -** MIMXRT1021CAG4A -** MIMXRT1021DAF5A -** MIMXRT1021DAG5A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 -** Version: rev. 0.1, 2017-06-06 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x60002000; -define symbol m_interrupts_end = 0x600023FF; - -define symbol m_text_start = 0x60002400; -define symbol m_text_end = 0x607FFFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2021FFFF; - -define exported symbol m_boot_hdr_conf_start = 0x60000000; -define symbol m_boot_hdr_ivt_start = 0x60001000; -define symbol m_boot_hdr_boot_data_start = 0x60001020; -define symbol m_boot_hdr_dcd_data_start = 0x60001030; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; -place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; -place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; -place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; - -keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; - -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in DATA_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; - +/* +** ################################################################### +** Processors: MIMXRT1021CAF4A +** MIMXRT1021CAG4A +** MIMXRT1021DAF5A +** MIMXRT1021DAG5A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 +** Version: rev. 0.1, 2017-06-06 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_text_start = 0x60002400; +define symbol m_text_end = 0x607FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2021FFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf index 5da51d70c607f41849c0e091a2cddd14256663d6..54b091e58f693e3039825373fd0150a7bff1d2f9 100644 --- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf +++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_flexspi_nor_sdram.icf @@ -1,101 +1,101 @@ -/* -** ################################################################### -** Processors: MIMXRT1021CAF4A -** MIMXRT1021CAG4A -** MIMXRT1021DAF5A -** MIMXRT1021DAG5A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 -** Version: rev. 0.1, 2017-06-06 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x60002000; -define symbol m_interrupts_end = 0x600023FF; - -define symbol m_text_start = 0x60002400; -define symbol m_text_end = 0x607FFFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2021FFFF; - -define symbol m_data3_start = 0x80000000; -define symbol m_data3_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -define exported symbol m_boot_hdr_conf_start = 0x60000000; -define symbol m_boot_hdr_ivt_start = 0x60001000; -define symbol m_boot_hdr_boot_data_start = 0x60001020; -define symbol m_boot_hdr_dcd_data_start = 0x60001030; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { first readwrite, section m_usb_dma_init_data }; -define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; -define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; -place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; -place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; -place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; - -keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; - -place in TEXT_region { readonly }; -place in DATA3_region { block RW }; -place in DATA3_region { block ZI }; -place in DATA3_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; - +/* +** ################################################################### +** Processors: MIMXRT1021CAF4A +** MIMXRT1021CAG4A +** MIMXRT1021DAF5A +** MIMXRT1021DAG5A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 +** Version: rev. 0.1, 2017-06-06 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_text_start = 0x60002400; +define symbol m_text_end = 0x607FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2021FFFF; + +define symbol m_data3_start = 0x80000000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +place in DATA3_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf index a835ba92c716195b058a867124256607c6e7423a..73a34d0385513e260510fd04bdf96f605a308b57 100644 --- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf +++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_ram.icf @@ -1,81 +1,81 @@ -/* -** ################################################################### -** Processors: MIMXRT1021CAF4A -** MIMXRT1021CAG4A -** MIMXRT1021DAF5A -** MIMXRT1021DAG5A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 -** Version: rev. 0.1, 2017-06-06 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; - -define symbol m_text_start = 0x00000400; -define symbol m_text_end = 0x0000FFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2021FFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in DATA_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; - +/* +** ################################################################### +** Processors: MIMXRT1021CAF4A +** MIMXRT1021CAG4A +** MIMXRT1021DAF5A +** MIMXRT1021DAG5A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 +** Version: rev. 0.1, 2017-06-06 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0000FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2021FFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf index c2056d3ddcd6a45b2b4bff8273604f848ac9329b..6788c317e23e65a6314cf11ed601886ebe5b1c3a 100644 --- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf +++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram.icf @@ -1,89 +1,89 @@ -/* -** ################################################################### -** Processors: MIMXRT1021CAF4A -** MIMXRT1021CAG4A -** MIMXRT1021DAF5A -** MIMXRT1021DAG5A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 -** Version: rev. 0.1, 2017-06-06 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; - -define symbol m_text_start = 0x00000400; -define symbol m_text_end = 0x0000FFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2021FFFF; - -define symbol m_data3_start = 0x80000000; -define symbol m_data3_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { first readwrite, section m_usb_dma_init_data }; -define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; -define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in DATA3_region { block RW }; -place in DATA3_region { block ZI }; -place in DATA3_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; - +/* +** ################################################################### +** Processors: MIMXRT1021CAF4A +** MIMXRT1021CAG4A +** MIMXRT1021DAF5A +** MIMXRT1021DAG5A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 +** Version: rev. 0.1, 2017-06-06 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0000FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2021FFFF; + +define symbol m_data3_start = 0x80000000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +place in DATA3_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf index b94c4e4939255225c5ea0e351d19612ecac29910..827d248639bc5d07274bbb260de70c6a0b932d0e 100644 --- a/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf +++ b/bsp/imxrt/libraries/MIMXRT1020/MIMXRT1021/iar/MIMXRT1021xxxxx_sdram_txt.icf @@ -1,89 +1,89 @@ -/* -** ################################################################### -** Processors: MIMXRT1021CAF4A -** MIMXRT1021CAG4A -** MIMXRT1021DAF5A -** MIMXRT1021DAG5A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 -** Version: rev. 0.1, 2017-06-06 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x80000000; -define symbol m_interrupts_end = 0x800003FF; - -define symbol m_text_start = 0x80000400; -define symbol m_text_end = 0x801FFFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2021FFFF; - -define symbol m_data3_start = 0x80200000; -define symbol m_data3_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__]; -define region DATA3_region = mem:[from m_data3_start to m_data3_end]; -define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { first readwrite, section m_usb_dma_init_data }; -define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; -define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in DATA2_region { block RW }; -place in DATA2_region { block ZI }; -place in DATA2_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; - +/* +** ################################################################### +** Processors: MIMXRT1021CAF4A +** MIMXRT1021CAG4A +** MIMXRT1021DAF5A +** MIMXRT1021DAG5A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1020RM Rev. 1RC, 05/2018 +** Version: rev. 0.1, 2017-06-06 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x80000000; +define symbol m_interrupts_end = 0x800003FF; + +define symbol m_text_start = 0x80000400; +define symbol m_text_end = 0x801FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2021FFFF; + +define symbol m_data3_start = 0x80200000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end]; +define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA2_region { block RW }; +place in DATA2_region { block ZI }; +place in DATA2_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds index a0a306f37044bf49785ff1f2ab9eb1874b27f1a7..d2f73ebaf09d0d19ffe34bb77485b50e895d8843 100644 --- a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds +++ b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds @@ -86,9 +86,9 @@ SECTIONS .ivt : AT(ivt_begin) { . = ALIGN(4); - KEEP(* (.boot_hdr.ivt)) /* ivt section */ - KEEP(* (.boot_hdr.boot_data)) /* boot section */ - KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ . = ALIGN(4); } > m_ivt @@ -278,7 +278,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_data - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds index 9942889d58e10bd05fbed69cb196c546fc5ace5d..169a2d310a9d75f6872c9b447886c72233e41f1a 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds @@ -268,7 +268,7 @@ SECTIONS stack_end = .; __StackTop = .; } > m_dtcm - + .RTT_HEAP : { heap_start = .; diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct index 7b7bf4fbba15cc583a6f326ca6a8eee92ee0f2d1..d179e6093f895dc45f2a339b9e794fda32e7bc56 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct @@ -84,48 +84,48 @@ #if (defined(BSP_USING_4MFLASH)) LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region -{ +{ RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address - { + { * (.boot_hdr.conf, +FIRST) - } + } } LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region -{ +{ RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address - { + { * (.boot_hdr.ivt, +FIRST) * (.boot_hdr.boot_data) * (.boot_hdr.dcd_data) - } + } } #endif #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) ; load region size_region -LR_IROM1 m_text_start m_text_size -{ +LR_IROM1 m_text_start m_text_size +{ ER_IROM1 m_text_start m_text_size ; load address = execution address - { + { * (RESET,+FIRST) * (InRoot$$Sections) .ANY (+RO) } - + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { + { .ANY (+RW +ZI) } - + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data - RW_m_ncache m_data2_start m_data2_size - { + RW_m_ncache m_data2_start m_data2_size + { * (NonCacheable.init) * (NonCacheable) } diff --git a/bsp/juicevm/link.lds b/bsp/juicevm/link.lds index b96558d7cd8cd00abd16482ba5ae10279391fe93..74d01910b00295e6a6a330188eb251431dfbe46d 100755 --- a/bsp/juicevm/link.lds +++ b/bsp/juicevm/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ SECTIONS . = ALIGN(8); - .text : + .text : { *(.text) /* remaining code */ *(.text.*) /* remaining code */ @@ -44,7 +44,7 @@ SECTIONS *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t*) - + /* section information for finsh shell */ . = ALIGN(8); __fsymtab_start = .; @@ -71,20 +71,20 @@ SECTIONS _etext = .; } > SRAM - .eh_frame_hdr : - { - *(.eh_frame_hdr) + .eh_frame_hdr : + { + *(.eh_frame_hdr) *(.eh_frame_entry) } > SRAM .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM . = ALIGN(8); - .data : + .data : { *(.data) *(.data.*) - + *(.data1) *(.data1.*) @@ -105,7 +105,7 @@ SECTIONS __stack = .; } > SRAM - .sbss : + .sbss : { __bss_start = .; *(.sbss) diff --git a/bsp/juicevm/link_stacksize.lds b/bsp/juicevm/link_stacksize.lds index 1dd893422c2e9b079747bd857dec99880b056715..28438c7da176095056b52a2249bc20f7407466b9 100755 --- a/bsp/juicevm/link_stacksize.lds +++ b/bsp/juicevm/link_stacksize.lds @@ -1 +1 @@ -__STACKSIZE__ = 4096; \ No newline at end of file +__STACKSIZE__ = 4096; diff --git a/bsp/k210/link.lds b/bsp/k210/link.lds index 60b39fb5f1ca00b4dd48d7ae8e16576b6df78429..f37579c2558c9160941b4218e48f7d813b9b1355 100644 --- a/bsp/k210/link.lds +++ b/bsp/k210/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ SECTIONS . = ALIGN(8); - .text : + .text : { *(.text) /* remaining code */ *(.text.*) /* remaining code */ @@ -55,8 +55,8 @@ SECTIONS KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - - + + /* section information for finsh shell */ . = ALIGN(8); __fsymtab_start = .; @@ -81,7 +81,7 @@ SECTIONS __spi_func_end = .; . = ALIGN(8); - + __rt_utest_tc_tab_start = .; KEEP(*(UtestTcTab)) __rt_utest_tc_tab_end = .; @@ -90,20 +90,20 @@ SECTIONS _etext = .; } > SRAM - .eh_frame_hdr : - { - *(.eh_frame_hdr) + .eh_frame_hdr : + { + *(.eh_frame_hdr) *(.eh_frame_entry) } > SRAM .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM . = ALIGN(8); - .data : + .data : { *(.data) *(.data.*) - + *(.data1) *(.data1.*) @@ -117,7 +117,7 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + } > SRAM /* stack for dual core */ @@ -133,7 +133,7 @@ SECTIONS __stack_cpu1 = .; } > SRAM - .sbss : + .sbss : { __bss_start = .; *(.sbss) diff --git a/bsp/k210/link_stacksize.lds b/bsp/k210/link_stacksize.lds index 1dd893422c2e9b079747bd857dec99880b056715..28438c7da176095056b52a2249bc20f7407466b9 100644 --- a/bsp/k210/link_stacksize.lds +++ b/bsp/k210/link_stacksize.lds @@ -1 +1 @@ -__STACKSIZE__ = 4096; \ No newline at end of file +__STACKSIZE__ = 4096; diff --git a/bsp/loongson/ls1bdev/ls1b_ram.lds b/bsp/loongson/ls1bdev/ls1b_ram.lds index a3419501c0da78a064793ff81d5e22dc04787785..f5543822fc5e1a6472d33341442b54b4e49f3ead 100644 --- a/bsp/loongson/ls1bdev/ls1b_ram.lds +++ b/bsp/loongson/ls1bdev/ls1b_ram.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/loongson/ls1cdev/ls1c_ram.lds b/bsp/loongson/ls1cdev/ls1c_ram.lds index aced32b90b8cb99f9f151a6aac2332745bd603f4..6318cc7909d30ca961c9ebc457850f50fe93b800 100644 --- a/bsp/loongson/ls1cdev/ls1c_ram.lds +++ b/bsp/loongson/ls1cdev/ls1c_ram.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/loongson/ls2kdev/ls2k_ram.lds b/bsp/loongson/ls2kdev/ls2k_ram.lds index 313a52969c5e6d58e31b90919f579caed8327e27..4d5ac94caf5c9800e1cde5787d2778c82ed19a6b 100644 --- a/bsp/loongson/ls2kdev/ls2k_ram.lds +++ b/bsp/loongson/ls2kdev/ls2k_ram.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ SECTIONS __ebase_end = .; start = .; *(.start); - . = ALIGN(4); + . = ALIGN(4); *(.text) *(.text.*) *(.rodata) @@ -54,26 +54,26 @@ SECTIONS __rt_utest_tc_tab_end = .; . = ALIGN(4); } - - .eh_frame_hdr : - { - *(.eh_frame_hdr) + + .eh_frame_hdr : + { + *(.eh_frame_hdr) *(.eh_frame_entry) } .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } . = ALIGN(4); - .data : + .data : { *(.data) *(.data.*) - + *(.data1) *(.data1.*) . = ALIGN(8); _gp = ABSOLUTE(.); /* Base of small data */ - + *(.sdata) *(.sdata.*) } @@ -103,7 +103,7 @@ SECTIONS _system_stack = .; } - .sbss : + .sbss : { __bss_start = .; *(.sbss) diff --git a/bsp/lpc1114/link.lds b/bsp/lpc1114/link.lds index 19d0a053cb8366bd0853605a8350070222b14819..90e5f47ed2e1b4b9fbcf9c2c9c933bceeb8281ed 100644 --- a/bsp/lpc1114/link.lds +++ b/bsp/lpc1114/link.lds @@ -74,7 +74,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -95,7 +95,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end__ = .; diff --git a/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf b/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf index 0e0dc6efcf43ba0b0d0de0e7ef57e3ed1351495a..7da727d4c7b98be6a62c22c1eea74124ba15f635 100644 --- a/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf +++ b/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; place in RAM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in AHB_RAM_region { section USB_RAM }; \ No newline at end of file +place in AHB_RAM_region { section USB_RAM }; diff --git a/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf b/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf index fba995217938e875da5c29c94163e642c864693e..e68e2b0a621f2b0486263b4176adce2baabb67fa 100644 --- a/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf +++ b/bsp/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf @@ -32,4 +32,4 @@ place at address mem:0x2FC { section CRPKEY }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in AHB_RAM_region { section USB_RAM }; \ No newline at end of file +place in AHB_RAM_region { section USB_RAM }; diff --git a/bsp/lpc2478/lpc2478_ram.lds b/bsp/lpc2478/lpc2478_ram.lds index 28e8cdd7f52a1d49530efc28195b369b1798d0db..d5c55a4ac5b9a5a8138fa672674299d46b79536e 100644 --- a/bsp/lpc2478/lpc2478_ram.lds +++ b/bsp/lpc2478/lpc2478_ram.lds @@ -3,7 +3,7 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0xa0000000; + . = 0xa0000000; __text_start = .; .text : @@ -17,14 +17,14 @@ SECTIONS __rodata_start = .; .rodata : { *(.rodata) *(.rodata.*) } __rodata_end = .; - - . = 0xa0100000; + + . = 0xa0100000; . = ALIGN(8); __data_start = .; - .data : - { - *(.data) - *(.data.*) + .data : + { + *(.data) + *(.data.*) } __data_end = .; @@ -44,32 +44,32 @@ SECTIONS __UndStack_start = __bss_end; .UndStack : { *(.UndStack) } __UndStack_end = ( __UndStack_start + 0x00000100 ); - + . = ALIGN(4); __IRQStack_start = __UndStack_end; .IRQStack : { *(.IRQStack) } __IRQStack_end = ( __IRQStack_start + 0x00000100 ); - + . = ALIGN(4); __FIQStack_start = __IRQStack_end; .FIQStack : { *(.FIQStack) } __FIQStack_end = ( __FIQStack_start + 0x00000100 ); - + . = ALIGN(4); __SVCStack_start = __FIQStack_end; .SVCStack : { *(.SVCStack) } __SVCStack_end = ( __SVCStack_start + 0x00000100 ); - + . = ALIGN(4); __ABTStack_start = __SVCStack_end; .ABTStack : { *(.ABTStack) } __ABTStack_end = ( __ABTStack_start + 0x00000100 ); - + . = ALIGN(4); __USRStack_start = __ABTStack_end; .USRStack : { *(.USRStack) } __USRStack_end = ( __USRStack_start + 0x00003B00 ); - + . = ALIGN(4); __Heap_start = __USRStack_end; .Heap : { *(.Heap) } diff --git a/bsp/lpc408x/drivers/linker_scripts/link.lds b/bsp/lpc408x/drivers/linker_scripts/link.lds index ddf10a2c20d6663368e17fa9488bd684aeb3a829..e9bfccfd748a09b9a61360b8cd19050521e9f94c 100644 --- a/bsp/lpc408x/drivers/linker_scripts/link.lds +++ b/bsp/lpc408x/drivers/linker_scripts/link.lds @@ -58,9 +58,9 @@ SECTIONS _etext = .; } > CODE = 0 - .ARM.extab : - { - *(.ARM.extab*) + .ARM.extab : + { + *(.ARM.extab*) } > CODE /* The .ARM.exidx section is used for C++ exception handling. */ @@ -98,7 +98,7 @@ SECTIONS _edata = . ; } > DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -118,7 +118,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; + _ebss = . ; *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf index 3eb7d6eeb89d986b24a7e5fe97184e2d739f3955..5ba71403bc321730a3da0c80467c1c9457924604 100644 --- a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf @@ -15,7 +15,7 @@ ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** All rights reserved. -** +** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted (subject to the limitations in the disclaimer below) provided ** that the following conditions are met: diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf index bc8768da3932d9490e97bf7cc7c8b3d24097a3cb..59cc28d9dee0e92af5b07fdc213d6a9f3e281e97 100644 --- a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf @@ -15,7 +15,7 @@ ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** All rights reserved. -** +** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted (subject to the limitations in the disclaimer below) provided ** that the following conditions are met: diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf index fb096f80b2ec43fd37242c5ff5f7c8b0bd2e40e6..b3385275000afabf0a50b95b3398a415784dc0e1 100644 --- a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf @@ -15,7 +15,7 @@ ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** All rights reserved. -** +** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted (subject to the limitations in the disclaimer below) provided ** that the following conditions are met: diff --git a/bsp/lpc54114-lite/drivers/linker_scripts/link.icf b/bsp/lpc54114-lite/drivers/linker_scripts/link.icf index b3f169d4a29c1c88c89fcb3eab424d7fadd0bc1c..36a0c47ec97cafc63caf3657130900f46b2370c8 100644 --- a/bsp/lpc54114-lite/drivers/linker_scripts/link.icf +++ b/bsp/lpc54114-lite/drivers/linker_scripts/link.icf @@ -15,7 +15,7 @@ ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** All rights reserved. -** +** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted (subject to the limitations in the disclaimer below) provided ** that the following conditions are met: diff --git a/bsp/lpc54114-lite/drivers/linker_scripts/link.lds b/bsp/lpc54114-lite/drivers/linker_scripts/link.lds index e1fb7acd66e7f57b43c9b8c361c3a5aa0e73830d..7158cf15633ca0cc8d42c587bd742e17b6bee860 100644 --- a/bsp/lpc54114-lite/drivers/linker_scripts/link.lds +++ b/bsp/lpc54114-lite/drivers/linker_scripts/link.lds @@ -14,7 +14,7 @@ ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** All rights reserved. -** +** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted (subject to the limitations in the disclaimer below) provided ** that the following conditions are met: @@ -243,7 +243,7 @@ SECTIONS } > m_data PROVIDE(heap_end = ORIGIN(m_data) + LENGTH(m_data)); - + /* Initializes stack on the end of block */ __StackTop = ORIGIN(m_data) + LENGTH(m_data); __StackLimit = __StackTop - STACK_SIZE; diff --git a/bsp/lpc54608-LPCXpresso/link.lds b/bsp/lpc54608-LPCXpresso/link.lds index 585e846084e706e60ff2cd21bf6434757b5e3cb9..799aa9e2a350b8eb8e527b1652172548a26d029d 100644 --- a/bsp/lpc54608-LPCXpresso/link.lds +++ b/bsp/lpc54608-LPCXpresso/link.lds @@ -45,7 +45,7 @@ SECTIONS . = ALIGN(4); /* section information for modules */ - + __rtmsymtab_start = .; KEEP(*(RTMSymTab)) __rtmsymtab_end = .; @@ -73,9 +73,9 @@ SECTIONS _etext = .; } > CODE = 0 - .ARM.extab : - { - *(.ARM.extab*) + .ARM.extab : + { + *(.ARM.extab*) } > CODE /* The .ARM.exidx section is used for C++ exception handling. */ @@ -113,7 +113,7 @@ SECTIONS _edata = . ; } > DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -133,7 +133,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; + _ebss = . ; *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf index 6be960151a97fc00e0e41bea5b3ab62d26d4b686..5d07ddcf8c60eea0bcbf69631d8ea75d0f532174 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf @@ -62,8 +62,8 @@ if (isdefinedsymbol(__use_shmem__)) { } /* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */ -define symbol m_veneer_table_start = 0x1000FE00; -define symbol m_veneer_table_size = 0x200; +define symbol m_veneer_table_start = 0x1000FE00; +define symbol m_veneer_table_size = 0x200; define symbol m_usb_sram_start = 0x50100000; define symbol m_usb_sram_end = 0x50103FFF; @@ -78,7 +78,7 @@ if (isdefinedsymbol(__use_shmem__)) { define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; } -define region VENEER_TABLE_region = mem:[from m_veneer_table_start to m_veneer_table_start + m_veneer_table_size - 1]; +define region VENEER_TABLE_region = mem:[from m_veneer_table_start to m_veneer_table_start + m_veneer_table_size - 1]; define block CSTACK with alignment = 8, size = __size_cstack__ { }; define block HEAP with alignment = 8, size = __size_heap__ { }; @@ -113,7 +113,7 @@ place in DATA_region { block RW }; place in DATA_region { block ZI }; place in DATA_region { last block HEAP }; place in CSTACK_region { block CSTACK }; -place in VENEER_TABLE_region { section Veneer$$CMSE }; +place in VENEER_TABLE_region { section Veneer$$CMSE }; if (isdefinedsymbol(__use_shmem__)) { place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; diff --git a/bsp/maxim/max32660-evsys/board/linker_scripts/link.lds b/bsp/maxim/max32660-evsys/board/linker_scripts/link.lds index 4736a8d23fa6a0aba3f794852f9c89a5e72bc7be..d2f37d7fdeba862382a98b6fc2ca742cb90f166c 100644 --- a/bsp/maxim/max32660-evsys/board/linker_scripts/link.lds +++ b/bsp/maxim/max32660-evsys/board/linker_scripts/link.lds @@ -19,7 +19,7 @@ SECTIONS { /* C++ Exception handling */ KEEP(*(.eh_frame*)) - + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -36,7 +36,7 @@ SECTIONS { __rt_init_start = .; KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; - + . = ALIGN(4); PROVIDE(__ctors_start__ = .); @@ -45,7 +45,7 @@ SECTIONS { PROVIDE(__ctors_end__ = .); . = ALIGN(4); - + _etext = .; } > FLASH diff --git a/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf index 892080e9f447e224e77fb115f53f0300fc120a86..094445f31f96dc265b21fc774fba55c1dc1732c0 100644 --- a/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf +++ b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf @@ -14,9 +14,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf index e6cc6d91d6174bb768479b5c80eebb33e23e2b10..e134e0fa18a242fa35fddab8ad765e9cd2ce4f51 100644 --- a/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf +++ b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf @@ -14,9 +14,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf b/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf index 5a1c3e3d18ee79a70c608ae06d8c39cac91a1afe..afe1b5b622bae4d771d41f4eef155b013a94f66a 100644 --- a/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf +++ b/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf @@ -14,9 +14,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf b/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf index 5f8d451acde25aa4213ff74079e0ecaf06bdef8c..b32871b6509220b8051e3a0cef43d60c5d49091a 100644 --- a/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf +++ b/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf @@ -14,9 +14,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/bsp/mini2440/rtthread-mini2440.sct b/bsp/mini2440/rtthread-mini2440.sct index 5b0c1d734cc3c181849efeb9b66042a3517af8a9..f55d975f1efa5c574d87a8212b8ca0b85377e93e 100644 --- a/bsp/mini2440/rtthread-mini2440.sct +++ b/bsp/mini2440/rtthread-mini2440.sct @@ -1,18 +1,18 @@ -LR_IROM1 0x30000000 0x1000000 { - ER_IROM1 0x30000000 0x00200000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 +0 { ; RW data - .ANY (+RW) - } - - ER_ZI +0 { ; ZI data - .ANY (+ZI) - } - - ER_MMU 0x33FF0000 EMPTY 0x00100000 { - } -} +LR_IROM1 0x30000000 0x1000000 { + ER_IROM1 0x30000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 +0 { ; RW data + .ANY (+RW) + } + + ER_ZI +0 { ; ZI data + .ANY (+ZI) + } + + ER_MMU 0x33FF0000 EMPTY 0x00100000 { + } +} diff --git a/bsp/mini4020/rtthread-mini4020.sct b/bsp/mini4020/rtthread-mini4020.sct index f491876a08f00010df03d23ac92e2ead51a62c6c..50f448280fd8f04071be8e56a9cde34c10236ffe 100644 --- a/bsp/mini4020/rtthread-mini4020.sct +++ b/bsp/mini4020/rtthread-mini4020.sct @@ -7,18 +7,18 @@ ; ************************************************************* -LR_ROM1 0x30000000 0x0FFD00 ; load region size_region - { - ER_ROM1 0x30000000 0x0FFD00 ; load address = execution address - { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_RAM1 0x30100000 0x100000 ; RW data - { - .ANY (+RW +ZI) - } +LR_ROM1 0x30000000 0x0FFD00 ; load region size_region + { + ER_ROM1 0x30000000 0x0FFD00 ; load address = execution address + { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_RAM1 0x30100000 0x100000 ; RW data + { + .ANY (+RW +ZI) + } } diff --git a/bsp/mipssim/mipssim_ram.lds b/bsp/mipssim/mipssim_ram.lds index 196b6e8e0254faef49127b8db1ac7215ddb486fd..98f11462c0e6541a03d9bd9ff67a10fc0b736121 100644 --- a/bsp/mipssim/mipssim_ram.lds +++ b/bsp/mipssim/mipssim_ram.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ SECTIONS __ebase_end = .; start = .; *(.start); - . = ALIGN(4); + . = ALIGN(4); *(.text) *(.text.*) *(.rodata) @@ -54,26 +54,26 @@ SECTIONS __rt_utest_tc_tab_end = .; . = ALIGN(4); } - - .eh_frame_hdr : - { - *(.eh_frame_hdr) + + .eh_frame_hdr : + { + *(.eh_frame_hdr) *(.eh_frame_entry) } .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } . = ALIGN(4); - .data : + .data : { *(.data) *(.data.*) - + *(.data1) *(.data1.*) . = ALIGN(8); _gp = ABSOLUTE(.); /* Base of small data */ - + *(.sdata) *(.sdata.*) } @@ -86,7 +86,7 @@ SECTIONS _system_stack = .; } - .sbss : + .sbss : { __bss_start = .; *(.sbss) diff --git a/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/iar/linker/mm32f3273g.icf b/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/iar/linker/mm32f3273g.icf index 92ab6c7b9342ecbd61d330889e7ae381186ae469..a462e968aef49876d49a07a8d64b7ed38c630c99 100644 --- a/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/iar/linker/mm32f3273g.icf +++ b/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/iar/linker/mm32f3273g.icf @@ -1,30 +1,30 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/mm32/mm32f3270-100ask-pitaya/board/linker_scripts/link.icf b/bsp/mm32/mm32f3270-100ask-pitaya/board/linker_scripts/link.icf index 92ab6c7b9342ecbd61d330889e7ae381186ae469..a462e968aef49876d49a07a8d64b7ed38c630c99 100644 --- a/bsp/mm32/mm32f3270-100ask-pitaya/board/linker_scripts/link.icf +++ b/bsp/mm32/mm32f3270-100ask-pitaya/board/linker_scripts/link.icf @@ -1,30 +1,30 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/mm32f103x/drivers/linker_scripts/link.lds b/bsp/mm32f103x/drivers/linker_scripts/link.lds index aad42bdb39019ecd51f4ddbd699bb834d2065881..21222812c4e87af98625224250034bd7dc8ac6a8 100644 --- a/bsp/mm32f103x/drivers/linker_scripts/link.lds +++ b/bsp/mm32f103x/drivers/linker_scripts/link.lds @@ -73,7 +73,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -94,7 +94,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/mm32f327x/drivers/linker_scripts/link.lds b/bsp/mm32f327x/drivers/linker_scripts/link.lds index aad42bdb39019ecd51f4ddbd699bb834d2065881..21222812c4e87af98625224250034bd7dc8ac6a8 100644 --- a/bsp/mm32f327x/drivers/linker_scripts/link.lds +++ b/bsp/mm32f327x/drivers/linker_scripts/link.lds @@ -73,7 +73,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -94,7 +94,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/mm32l07x/drivers/linker_scripts/link.lds b/bsp/mm32l07x/drivers/linker_scripts/link.lds index c7b5f1be0bcf3f40666565a468816015ca4aed61..1aea6643d921a68b9af475ca2b293ec8625030fb 100644 --- a/bsp/mm32l07x/drivers/linker_scripts/link.lds +++ b/bsp/mm32l07x/drivers/linker_scripts/link.lds @@ -73,7 +73,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -94,7 +94,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/mm32l3xx/drivers/linker_scripts/link.lds b/bsp/mm32l3xx/drivers/linker_scripts/link.lds index aad42bdb39019ecd51f4ddbd699bb834d2065881..21222812c4e87af98625224250034bd7dc8ac6a8 100644 --- a/bsp/mm32l3xx/drivers/linker_scripts/link.lds +++ b/bsp/mm32l3xx/drivers/linker_scripts/link.lds @@ -73,7 +73,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -94,7 +94,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.icf b/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.icf index 5cb78a4d65b3977c762374050b7b684423c172df..84dd3b35a119cd8e24f7897c7905d40d021480a3 100644 --- a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.icf +++ b/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.lds b/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.lds index d0355f22add6508054245b8556bdb0fc5913589e..9a8fd415ebd3a8855805809018b6043c017c39e6 100644 --- a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.lds +++ b/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.icf b/bsp/n32/n32g457qel-stb/board/linker_scripts/link.icf index 4f961659c1b67a619b8f08d59725bb75e9165039..0b160ea127d753be1c1990e1f4c31ee0e59152a7 100644 --- a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.icf +++ b/bsp/n32/n32g457qel-stb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.lds b/bsp/n32/n32g457qel-stb/board/linker_scripts/link.lds index caf3947f1a8215c0e74be4b5f38b3dc1de0c24d3..25f4bd25baa0dc8f4c206745f473e005aed798ac 100644 --- a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.lds +++ b/bsp/n32/n32g457qel-stb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.icf b/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.icf index 35a1d043e83e90444ff2fce0e26d1dd1e8117de4..473fd1b2af5cebd263f8356bc4f5c1a7be0ace0c 100644 --- a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.icf +++ b/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.lds b/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.lds index 6561a7249d47c3b4e39d5e479ad86f97bab50fdd..c64fe82311eec8f442105d6d54c5aeaa39c1e201 100644 --- a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.lds +++ b/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.icf b/bsp/n32/n32g45xml-stb/board/linker_scripts/link.icf index 4f961659c1b67a619b8f08d59725bb75e9165039..0b160ea127d753be1c1990e1f4c31ee0e59152a7 100644 --- a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.icf +++ b/bsp/n32/n32g45xml-stb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.lds b/bsp/n32/n32g45xml-stb/board/linker_scripts/link.lds index caf3947f1a8215c0e74be4b5f38b3dc1de0c24d3..25f4bd25baa0dc8f4c206745f473e005aed798ac 100644 --- a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.lds +++ b/bsp/n32/n32g45xml-stb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.icf b/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.icf index 4f961659c1b67a619b8f08d59725bb75e9165039..0b160ea127d753be1c1990e1f4c31ee0e59152a7 100644 --- a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.icf +++ b/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.lds b/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.lds index caf3947f1a8215c0e74be4b5f38b3dc1de0c24d3..25f4bd25baa0dc8f4c206745f473e005aed798ac 100644 --- a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.lds +++ b/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.icf b/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.icf index 4f961659c1b67a619b8f08d59725bb75e9165039..0b160ea127d753be1c1990e1f4c31ee0e59152a7 100644 --- a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.icf +++ b/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.lds b/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.lds index caf3947f1a8215c0e74be4b5f38b3dc1de0c24d3..25f4bd25baa0dc8f4c206745f473e005aed798ac 100644 --- a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.lds +++ b/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.icf b/bsp/n32/n32g4frml-stb/board/linker_scripts/link.icf index 4f961659c1b67a619b8f08d59725bb75e9165039..0b160ea127d753be1c1990e1f4c31ee0e59152a7 100644 --- a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.icf +++ b/bsp/n32/n32g4frml-stb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.lds b/bsp/n32/n32g4frml-stb/board/linker_scripts/link.lds index a96bb81398ae1945b6e3f841cdcc7ec87e59b5f1..2cb0afe87af26c6bcc4880f602e1c9f8a08f0ed8 100644 --- a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.lds +++ b/bsp/n32/n32g4frml-stb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.icf b/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.icf index 3228ad860ec24308e982405a462174eb73b8ca6a..d23ad8b48e842ec03db6ce788d1b87c8ac827573 100644 --- a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.icf +++ b/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.lds b/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.lds index b52bb21de03da52c6ecd49e62c22020c4394c748..27940ba15a8d05d61cfecd278b9bdc6eb0a14030 100644 --- a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.lds +++ b/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32l436-evb/board/linker_scripts/link.icf b/bsp/n32/n32l436-evb/board/linker_scripts/link.icf index 5cb78a4d65b3977c762374050b7b684423c172df..84dd3b35a119cd8e24f7897c7905d40d021480a3 100644 --- a/bsp/n32/n32l436-evb/board/linker_scripts/link.icf +++ b/bsp/n32/n32l436-evb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32l436-evb/board/linker_scripts/link.lds b/bsp/n32/n32l436-evb/board/linker_scripts/link.lds index c495e70a2a537f525137107c84e4083a3f68d55b..085daeeab94b4fb8d2a75306fbba3bd102b39a1c 100644 --- a/bsp/n32/n32l436-evb/board/linker_scripts/link.lds +++ b/bsp/n32/n32l436-evb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.icf b/bsp/n32/n32l43xml-stb/board/linker_scripts/link.icf index 5cb78a4d65b3977c762374050b7b684423c172df..84dd3b35a119cd8e24f7897c7905d40d021480a3 100644 --- a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.icf +++ b/bsp/n32/n32l43xml-stb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.lds b/bsp/n32/n32l43xml-stb/board/linker_scripts/link.lds index c495e70a2a537f525137107c84e4083a3f68d55b..085daeeab94b4fb8d2a75306fbba3bd102b39a1c 100644 --- a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.lds +++ b/bsp/n32/n32l43xml-stb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.icf b/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.icf index 5cb78a4d65b3977c762374050b7b684423c172df..84dd3b35a119cd8e24f7897c7905d40d021480a3 100644 --- a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.icf +++ b/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.lds b/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.lds index c495e70a2a537f525137107c84e4083a3f68d55b..085daeeab94b4fb8d2a75306fbba3bd102b39a1c 100644 --- a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.lds +++ b/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.icf b/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.icf index 6644872295f63abc63eba880a0f194d67db6619e..4ff561f605308cfbebe0131ff7013662e0a8b972 100644 --- a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.icf +++ b/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.icf @@ -36,5 +36,5 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; \ No newline at end of file + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.lds b/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.lds index 17a441e71117cc2c08124f9242b06c033642df19..9545672994a70dda26439013397e91347ae0cb54 100644 --- a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.lds +++ b/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.lds @@ -78,7 +78,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -99,7 +99,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds b/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds index 0865f5895317c3264a2bf2a81e5e42e2dec77604..5f69cf3a1434aec791ae43b2daf770d9c5fb316c 100755 --- a/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds b/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds index 2a0443924f94d34c59831ad9c53cdcc618c877fc..a97906e19fe90ac6b7d7827fbf1c63e1a418bbe9 100644 --- a/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds +++ b/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds @@ -38,7 +38,7 @@ SECTIONS *(.rodata*) KEEP(*(.eh_frame*)) - /* section information for finsh shell */ + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) @@ -121,7 +121,7 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM - + .heap (COPY): { __HeapBase = .; @@ -147,13 +147,13 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - + /* Check if text sections + data exceeds FLASH limit */ DataInitFlashUsed = __bss_start__ - __data_start__; CodeFlashUsed = __etext - ORIGIN(FLASH); TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") - + } diff --git a/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds b/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds index f4cf7ebbf7ac73cd83883caac5121d2168537113..ae7d91fb5e3d34ecabd745d3ce18e509a8c426c5 100644 --- a/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds +++ b/bsp/nrf5x/nrf52832/board/linker_scripts/link.lds @@ -49,7 +49,7 @@ SECTIONS __rtmsymtab_end = .; . = ALIGN(4); - + PROVIDE(__ctors_start__ = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds b/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds index e699e0079a3448c19202a3d34897230dea7d5d6c..e3fea7bd3a2211d5edd50bd22f6515399ee10e8a 100644 --- a/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds +++ b/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds @@ -38,7 +38,7 @@ SECTIONS *(.rodata*) KEEP(*(.eh_frame*)) - /* section information for finsh shell */ + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) @@ -121,7 +121,7 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM - + .heap (COPY): { __HeapBase = .; @@ -147,13 +147,13 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - + /* Check if text sections + data exceeds FLASH limit */ DataInitFlashUsed = __bss_start__ - __data_start__; CodeFlashUsed = __etext - ORIGIN(FLASH); TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") - + } diff --git a/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds b/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds index e699e0079a3448c19202a3d34897230dea7d5d6c..e3fea7bd3a2211d5edd50bd22f6515399ee10e8a 100644 --- a/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds +++ b/bsp/nrf5x/nrf52840/board/linker_scripts/link.lds @@ -38,7 +38,7 @@ SECTIONS *(.rodata*) KEEP(*(.eh_frame*)) - /* section information for finsh shell */ + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) @@ -121,7 +121,7 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM - + .heap (COPY): { __HeapBase = .; @@ -147,13 +147,13 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - + /* Check if text sections + data exceeds FLASH limit */ DataInitFlashUsed = __bss_start__ - __data_start__; CodeFlashUsed = __etext - ORIGIN(FLASH); TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") - + } diff --git a/bsp/nrf5x/nrf5340/board/linker_scripts/link.lds b/bsp/nrf5x/nrf5340/board/linker_scripts/link.lds index d7fcb7c7dcfecd91b41239f02f8218c4a3a37461..7f2592b31684f67bd479d3851a2212c24a32c27c 100644 --- a/bsp/nrf5x/nrf5340/board/linker_scripts/link.lds +++ b/bsp/nrf5x/nrf5340/board/linker_scripts/link.lds @@ -38,7 +38,7 @@ SECTIONS *(.rodata*) KEEP(*(.eh_frame*)) - /* section information for finsh shell */ + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) @@ -63,14 +63,14 @@ SECTIONS PROVIDE(__ctors_end__ = .); } > FLASH - - .nrf_queue : - { - PROVIDE(__start_nrf_queue = .); - KEEP(*(.nrf_balloc)) - PROVIDE(__stop_nrf_queue = .); - } > FLASH - + + .nrf_queue : + { + PROVIDE(__start_nrf_queue = .); + KEEP(*(.nrf_balloc)) + PROVIDE(__stop_nrf_queue = .); + } > FLASH + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) @@ -128,7 +128,7 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM - + .heap (COPY): { __HeapBase = .; @@ -154,13 +154,13 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - + /* Check if text sections + data exceeds FLASH limit */ DataInitFlashUsed = __bss_start__ - __data_start__; CodeFlashUsed = __etext - ORIGIN(FLASH); TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") - + } diff --git a/bsp/nuvoton/numaker-m032ki/linking_scripts/m031_flash.icf b/bsp/nuvoton/numaker-m032ki/linking_scripts/m031_flash.icf index 5c594d150f0e9895da5c01f74e708043d666e9a0..2b50d070dafcce93ce1d04c6a84fa460b559097a 100644 --- a/bsp/nuvoton/numaker-m032ki/linking_scripts/m031_flash.icf +++ b/bsp/nuvoton/numaker-m032ki/linking_scripts/m031_flash.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, block CSTACK }; \ No newline at end of file +place in RAM_region { readwrite, block CSTACK }; diff --git a/bsp/phytium/aarch32/link.lds b/bsp/phytium/aarch32/link.lds index d1acac738f221fdab0870c0b6d134de7d9ce09b5..0e7194b9eaafa788105c3d91873230030cbc2f61 100644 --- a/bsp/phytium/aarch32/link.lds +++ b/bsp/phytium/aarch32/link.lds @@ -12,7 +12,7 @@ SECTIONS *(.boot) . = ALIGN(64); - + *(.vectors) *(.text) *(.text.*) diff --git a/bsp/phytium/aarch64/link.lds b/bsp/phytium/aarch64/link.lds index 86bb78e88e1d32bfd7fbd81ffe6060059097a2d2..2e4b2ef10b9b5f3375a284ba0cd018efa6567c0c 100644 --- a/bsp/phytium/aarch64/link.lds +++ b/bsp/phytium/aarch64/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -108,7 +108,7 @@ SECTIONS PROVIDE(__heap_start = .); . = ALIGN(8); PROVIDE(end = .); - } + } _end = .; @@ -147,4 +147,4 @@ SECTIONS .debug_varnames 0 : { *(.debug_varnames) } } -__bss_size = SIZEOF(.bss); \ No newline at end of file +__bss_size = SIZEOF(.bss); diff --git a/bsp/qemu-virt64-riscv/link.lds b/bsp/qemu-virt64-riscv/link.lds index b0d6a6aed531b1ddc841a33fb171c827892840f0..a76fed4fa301f85151be11baee7a6639d9bea2f9 100644 --- a/bsp/qemu-virt64-riscv/link.lds +++ b/bsp/qemu-virt64-riscv/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,7 @@ SECTIONS . = ALIGN(8); - .text : + .text : { *(.text) /* remaining code */ *(.text.*) /* remaining code */ @@ -46,7 +46,7 @@ SECTIONS *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t*) - + /* section information for finsh shell */ . = ALIGN(8); __fsymtab_start = .; @@ -73,9 +73,9 @@ SECTIONS _etext = .; } > SRAM - .eh_frame_hdr : - { - *(.eh_frame_hdr) + .eh_frame_hdr : + { + *(.eh_frame_hdr) *(.eh_frame_entry) } > SRAM .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM @@ -84,11 +84,11 @@ SECTIONS __text_end = .; __text_size = __text_end - __text_start; - .data : + .data : { *(.data) *(.data.*) - + *(.data1) *(.data1.*) @@ -129,7 +129,7 @@ SECTIONS __stack_cpu1 = .; } > SRAM - .sbss : + .sbss : { __bss_start = .; *(.sbss) diff --git a/bsp/qemu-virt64-riscv/link_stacksize.lds b/bsp/qemu-virt64-riscv/link_stacksize.lds index 8685bc0f1c2d15f0a4bf11d75e743e5a61b16d95..14c2aad91f869fa1b69de7806d2c3f8f4f68116c 100644 --- a/bsp/qemu-virt64-riscv/link_stacksize.lds +++ b/bsp/qemu-virt64-riscv/link_stacksize.lds @@ -1 +1 @@ -__STACKSIZE__ = 16384; \ No newline at end of file +__STACKSIZE__ = 16384; diff --git a/bsp/raspberry-pi/raspi2/link.lds b/bsp/raspberry-pi/raspi2/link.lds index 71c92384faa403df8a6e6104adbef30941af3a5f..2ba97172e20b35a0ab4831af0fb5a3143fc81e8b 100644 --- a/bsp/raspberry-pi/raspi2/link.lds +++ b/bsp/raspberry-pi/raspi2/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/link.lds b/bsp/raspberry-pi/raspi3-32/link.lds index 71c92384faa403df8a6e6104adbef30941af3a5f..2ba97172e20b35a0ab4831af0fb5a3143fc81e8b 100644 --- a/bsp/raspberry-pi/raspi3-32/link.lds +++ b/bsp/raspberry-pi/raspi3-32/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/link.lds b/bsp/raspberry-pi/raspi3-64/link.lds index d03d0bd42ec587538fdee131ea4dc84b8a22054e..953be4c28b19fa21da9f9c175915572fa177f61a 100644 --- a/bsp/raspberry-pi/raspi3-64/link.lds +++ b/bsp/raspberry-pi/raspi3-64/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/link.lds b/bsp/raspberry-pi/raspi4-32/link.lds index 344c765acc094b695a4efbd21786ea0f94f4a3af..c1a5b9e1b1ad0cf7bc07cc96c43166299d521cd7 100644 --- a/bsp/raspberry-pi/raspi4-32/link.lds +++ b/bsp/raspberry-pi/raspi4-32/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-64/link.lds b/bsp/raspberry-pi/raspi4-64/link.lds index d03d0bd42ec587538fdee131ea4dc84b8a22054e..953be4c28b19fa21da9f9c175915572fa177f61a 100644 --- a/bsp/raspberry-pi/raspi4-64/link.lds +++ b/bsp/raspberry-pi/raspi4-64/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/rockchip/rk3568/link.lds b/bsp/rockchip/rk3568/link.lds index 6401f4a40dd1588fcfc064b5b30cd3cfc263a515..dd62ae35d0713a8b88ae45a7e57b9e0a6238f996 100644 --- a/bsp/rockchip/rk3568/link.lds +++ b/bsp/rockchip/rk3568/link.lds @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/rx/lnkr5f562n8.icf b/bsp/rx/lnkr5f562n8.icf index 38790c05d5d78e794b1eb31df5c63c5a09636de5..318aae8914ba42153ed1425d1cdee0842b08d6c1 100644 --- a/bsp/rx/lnkr5f562n8.icf +++ b/bsp/rx/lnkr5f562n8.icf @@ -34,17 +34,17 @@ place at address mem:0xFFFFFF80 { ro section .nmivec }; ro section .data24* }; "RAM24":place in RAM_region24 { rw section .data24* }; "ROM32":place in ROM_region32 { ro, - ro section FSymTab, - ro section VSymTab, - ro section .rti_fn*, - }; + ro section FSymTab, + ro section VSymTab, + ro section .rti_fn*, + }; "RAM32":place in RAM_region32 { rw, ro section D, ro section D_1, ro section D_2, block STACKS, - block HEAP, - }; + block HEAP, + }; "DATAFLASH":place in DATA_FLASH_region { ro section .dataflash* }; diff --git a/bsp/sam7x/sam7x_rom.sct b/bsp/sam7x/sam7x_rom.sct index 13999ef666ef16f936f8492e29a5ea27b5062fea..67809e950bebb6a95a6b09c3f80058ad82657414 100644 --- a/bsp/sam7x/sam7x_rom.sct +++ b/bsp/sam7x/sam7x_rom.sct @@ -1,15 +1,15 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00100000 0x00040000 { ; load region size_region - ER_IROM1 0x00100000 0x00040000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x00200000 0x00010000 { ; RW data - .ANY (+RW +ZI) - } -} - +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00100000 0x00040000 { ; load region size_region + ER_IROM1 0x00100000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x00200000 0x00010000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf index b7499054a933c19908bf5d4d24ab46419f3e32d7..477c3882bbcfe58721ea1b1ff1d3f13af76b8a6e 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_flash.icf @@ -1,79 +1,79 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD20E18 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - /** - * Support and FAQ: visit Atmel Support - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x2000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD20E18 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + /** + * Support and FAQ: visit Atmel Support + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x2000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf index ebe618f943bce6109d6d68b63ba0c18c6bbaa3f7..14979c650c2aa37938bfda9458894a464a2abf01 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20e18_sram.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD20E18 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - /** - * Support and FAQ: visit Atmel Support - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x2000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD20E18 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + /** + * Support and FAQ: visit Atmel Support + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x2000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf index bbbfad223e3f0357835d2227547ae2201854526f..9f340f2fda1b8593fc327487cb70b44d79aecef5 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_flash.icf @@ -1,79 +1,79 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD20G17U - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - /** - * Support and FAQ: visit Atmel Support - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x1000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD20G17U + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + /** + * Support and FAQ: visit Atmel Support + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf index 7118d0745b3822158b5a1e2696af8f31e4039712..fd0412701a37a0027567fd53a75803a2f5cb4e3b 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g17u_sram.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD20G17U - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - /** - * Support and FAQ: visit Atmel Support - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x1000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD20G17U + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + /** + * Support and FAQ: visit Atmel Support + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf index fdde4065aacb811dbd63d660b87596e2daef1400..0ea7273bc4d55bfa1c02093720311c4c94c7a7cf 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_flash.icf @@ -1,79 +1,79 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD20G18U - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - /** - * Support and FAQ: visit Atmel Support - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x2000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD20G18U + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + /** + * Support and FAQ: visit Atmel Support + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x2000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf index 9b9d2a518ba157ed7a6699c8a3d4298fccf63693..f0637d84d356251c43760a9498d4087fde77726f 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd20/iar/samd20g18u_sram.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD20G18U - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - /** - * Support and FAQ: visit Atmel Support - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x2000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD20G18U + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + /** + * Support and FAQ: visit Atmel Support + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x2000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf index c0f9fa5ce979d9ba9d498530a7641eb7ee1a5e58..ad32c4fc8a23b0a2e0e116c850c625b043e58f7c 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21E15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21E15B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf index a4cd4d17778ee916c61df8ec6b9c7b3a49326515..04a342f4a3553bb369bc952f0e6e9e04ff1fffb9 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15b_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21E15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21E15B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf index 1df26bf7e1ae23d3bfd47368fe3e0174bcf173f2..cb33811b179467f3d5e313a361c19df3ec6b952e 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21E15BU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21E15BU + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf index 998c94a680db8c1ebf9efcc72320f0c7787e5c13..1da3da45a588d0531998da10e02f8bd086d1f59f 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15bu_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21E15BU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21E15BU + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf index 8c7d6cdc1c67389fc26e82c96134f69d61c50e42..4750e7371c9db467162d6cab71b6ffdcab6c0a22 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21E15L - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21E15L + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf index 7bf9184da8cb0800e5590cfadd0861181c2ce974..893a4b9f56d02328190e0a806b2b154c90307a21 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e15l_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21E15L - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21E15L + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf index bb14fd7ef019611afdd7aa961542718bf826802e..319bc85ac99d1248327700f3caae4369408bc40c 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21E16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21E16B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf index f608892d1bacba34eacdd86ffc7481853c244b2d..819528491486842509746065109977090bb5bbbd 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16b_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21E16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21E16B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf index a0dfd304105ef25b913a78e79d085573690a3cd8..5b15689db5f6bfc5cf3ffa8a81edd7c03b420933 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21E16BU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21E16BU + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf index 1d49c0ed4ce289eeeb720cd7d5217daba612897e..0f68efa0dd078bbb1c9f6a697c8b7ba536ac1319 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16bu_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21E16BU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21E16BU + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf index 343b46fb3bfc37e420f4acff88cb7e657b13bf5d..c63dd3c6ed2a945b34334725589bd0b628aeb690 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21E16L - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21E16L + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf index cc2524f0c3a2918cac7487df17562e525165b12a..75619e7d36454f3853592cc3bb6eda7b41c74360 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e16l_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21E16L - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21E16L + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf index e0cd4f40ed4e0c15a5a40b84aaf1f0636f92acae..8497ded2e97ea532ebbd99940f845c34a5499bf0 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21E18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x2000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21E18A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x2000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf index a46e7c87d09fd15c55e5091f68444c1d076959b7..e3b59d9990a7dbf6f49fd1af3f9aa48b7d672c60 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21e18a_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21E18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x2000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21E18A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x2000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf index 4bba7c0c7a62ab880ea3f2e17eb342af76ce7b31..df519af26a91b6b970cb6c1e67b6a2c4d76460f8 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21G15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G15A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf index 2b42ca0d8f6d1b785379e3ed62f20f86a6f272d2..112262215f8c1390b3439f83f532f1a9f631bc51 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15a_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21G15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21G15A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf index c2ef3389e9e2951328567eef7aaa5bfa74386b7c..c71c51393c0c5b640719dfa89bb59180956679f0 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21G15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G15B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf index b8dbdaae9b49b8289e306c3055164176794454c7..0a70c80dcb9a7324ea90fea58ca6b150eb4a90d5 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15b_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21G15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21G15B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf index 161d96c2141d8e11f87d62d1a70f9383c5f8bc95..54f8578fd3723bce6c9698a43a6b7629562d49d4 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21G15L - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G15L + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf index fe382e12b61a9de5da4904f6c1c1aa2b8eba7c39..2cf0f8a3423e3f28d53ceb74b2104cdc40dc7a04 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g15l_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21G15L - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21G15L + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf index c5de64da26978bf6fdf0bdbe5e52f183477c88eb..b018c1ad7ead5ee3509c33221eea28002a38075c 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21G16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G16B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf index 22bb2eaa10ef764d7d252915935fe1f3c6249425..7f92977e71f54bafc9fc05473207e6590106bb77 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16b_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21G16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21G16B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf index a6807c1227aea6be5830d1e92aa04d30795ca985..ed480c4bad50106f48af11741a4e4b67c8c50316 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21G16L - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G16L + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf index e8b76d4dd5ecfc96cdc0edd292a4126b9f47d151..6180f15460b267e452876619cb91f35724166e77 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g16l_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21G16L - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21G16L + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf index 300b38d5638dc6af3a4d2ea4d07111b7ddefed42..3356435625b6f7c5390a22a3468c624a780d00d8 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21G17AU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x1000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G17AU + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf index c48c77daf96518c0b0189fb3d3340d5e43b3e938..a7c91496a167fd6b6013ddcfffff978a4c9338d9 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g17au_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21G17AU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x1000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21G17AU + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf index 403160016c153bc8081d8f2689a4234f7753a84a..b5fba1db04ee81a83c92569db6734620ce57cb5c 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21G18AU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x2000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G18AU + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x2000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf index 34bfdb06e49390b1065b673226e8be0a3c4edae6..19c6491b8765bd3b80e244ba36deb8d797cfb416 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21g18au_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21G18AU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x2000; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21G18AU + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x2000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf index 63eaab0f5531c0906ad922007dbaba7b10016bd4..3a7b1c926fe533a14360b1cdb63b5b846b3a4592 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21J15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21J15A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf index 778ea6dcef2d78ea633ff2d2e4fe0ef76785e74a..de97081778db7d3b6038df6a6bd60623bb7c2fc2 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15a_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21J15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21J15A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf index 82d992b66aef535352b5171f19e5a3fc66ef8426..231c466fe862ac003eb88281c68adfc59e53ede6 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21J15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21J15B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf index 49cf464df6287f0b6a5a75a916ded262e65e0ffa..468fae24c7440e625655d205c10dbfa7a0d94a4f 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j15b_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21J15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x400; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21J15B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf index d7f04148e8c697080fb437510adf8c064e49cc83..62894fe1f500c3b052b868cfac3bb49a4933c4bc 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_flash.icf @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21J16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21J16B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf index 05dfb6888acde444a574186fa6b8f51a0af3ac9d..f301ed86237614b20341203fb34b73e315827de9 100644 --- a/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf +++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/linker_scripts/samd21/iar/samd21j16b_sram.icf @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21J16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { - define symbol __ICFEDIT_size_cstack__ = 0x800; -} -if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { - define symbol __ICFEDIT_size_heap__ = 0x0; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing=none { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite }; -place at end of RAM_region { block CSTACK, block HEAP }; +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21J16B + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x800; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct index 3d214ad675c3d011af917e2e9fd6082f212ee511..50ab6f8dff7928b182912290ed53ef0f080acffd 100644 --- a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct +++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct @@ -1,7 +1,7 @@ ;******************************************************************************* ; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved. ; SmartFusion2 scatter file for debugging code executing in internal eSRAM. -; +; ; SVN $Revision: 7419 $ ; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $ ; @@ -23,7 +23,7 @@ ; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------ ; ; Example linker scripts use lowest practicl values so will work accross dev kits -; eNVM=256KB eRAM=64KB External memory = 64MB +; eNVM=256KB eRAM=64KB External memory = 64MB RAM_LOAD 0x20000000 0x10000 { @@ -35,10 +35,10 @@ RAM_LOAD 0x20000000 0x10000 .ANY (+RO) } ; Heap size is defined in startup_m2sxxx.s - ; Heap will be added after RW data in ER_RW unless explicitly + ; Heap will be added after RW data in ER_RW unless explicitly ; allocated a meemory region in .sct file ; Stack size is defined in startup_m2sxxx.s - ; Stack will be added after heap in ER_RW unless explicitly + ; Stack will be added after heap in ER_RW unless explicitly ; allocated a memory region in .sct file ; Second half of RAM allocated to RW data, heap and stack ER_RW 0x20008000 0x8000 diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct index e5663e79b5059ead9b030cf4a7c064101c66bc12..5c2fd504d85818423c1ba11c02c9284ef24b4df5 100644 --- a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct +++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct @@ -1,7 +1,7 @@ ;******************************************************************************* ; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved. ; SmartFusion2 scatter file for executing code in internal eNVM. -; +; ; SVN $Revision: 7419 $ ; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $ ; @@ -23,22 +23,22 @@ ; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------ ; ; Example linker scripts use lowest practicl values so will work accross dev kits -; eNVM=256KB eRAM=64KB External memory = 64MB +; eNVM=256KB eRAM=64KB External memory = 64MB -FLASH_LOAD 0x00000000 0x40000 +FLASH_LOAD 0x00000000 0x40000 { ; All R only code/data is located in ENVM ER_RO 0x00000000 0x40000 { - *.o (RESET, +First) + *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } ; Heap size is defined in startup_m2sxxx.s -; Heap will be added after RW data in ER_RW unless explicitly +; Heap will be added after RW data in ER_RW unless explicitly ; allocated a meemory region in .sct file ; Stack size is defined in startup_m2sxxx.s -; Stack will be added after heap in ER_RW unless explicitly +; Stack will be added after heap in ER_RW unless explicitly ; allocated a memory region in .sct file ER_RW 0x20000000 0x10000 { diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct index b2cb935927853bac46f4529885758be1661cc6eb..3f6ee574cd1a68d2cb6a7c74e2945abacc6fff36 100644 --- a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct +++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct @@ -1,7 +1,7 @@ ;******************************************************************************* ; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved. ; SmartFusion2 scatter file for debugging code executing in external MDDR. -; +; ; SVN $Revision: 7419 $ ; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $ ; @@ -23,7 +23,7 @@ ; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------ ; ; Example linker scripts use lowest practicl values so will work accross dev kits -; eNVM=256KB eRAM=64KB External memory = 64MB +; eNVM=256KB eRAM=64KB External memory = 64MB ; Extern RAM 64M in total ; allocate 1/2 to progam, 1/2 to variable data @@ -37,10 +37,10 @@ RAM_LOAD 0x00000000 0x04000000 .ANY (+RO) } ; Heap size is defined in startup_m2sxxx.s - ; Heap will be added after RW data in ER_RW unless explicitly + ; Heap will be added after RW data in ER_RW unless explicitly ; allocated a meemory region in .sct file ; Stack size is defined in startup_m2sxxx.s - ; Stack will be added after heap in ER_RW unless explicitly + ; Stack will be added after heap in ER_RW unless explicitly ; allocated a memory region in .sct file as is the case below STACKS 0x20000000 UNINIT { diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct index 3769a8cda3a6611b7da669181e92a24b5a0c9787..293a1e4bedd8e5be9065299a72d74b3b4868c20f 100644 --- a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct +++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct @@ -1,7 +1,7 @@ ;******************************************************************************* ; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved. ; SmartFusion2 scatter file for relocating code to external RAM. -; +; ; SVN $Revision: 7419 $ ; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $ ; @@ -23,7 +23,7 @@ ; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------ ; ; Example linker scripts use lowest practicl values so will work accross dev kits -; eNVM=256KB eRAM=64KB External memory = 64MB +; eNVM=256KB eRAM=64KB External memory = 64MB FLASH_LOAD 0x60000000 0x40000 { @@ -36,23 +36,23 @@ FLASH_LOAD 0x60000000 0x40000 system_m2sxxx.o sys_config.o low_level_init.o - sys_config_SERDESIF_?.o - mscc_post_hw_cfg_init.o - ecc_error_handler.o + sys_config_SERDESIF_?.o + mscc_post_hw_cfg_init.o + ecc_error_handler.o } - ; MDDR_RAM 0xA0000000 0x4000000 + ; MDDR_RAM 0xA0000000 0x4000000 ; -MDDR is mapped to address space from 0 on startup ; This allows the use of cache which is restriced to this area. ; Code is copied to RAM_EXEC space on startup by boot code. - RAM_EXEC 0x00000000 0x00040000 + RAM_EXEC 0x00000000 0x00040000 { .ANY (+RO) } ; Heap size is defined in startup_m2sxxx.s - ; Heap will be added after RW data in ER_RW unless explicitly + ; Heap will be added after RW data in ER_RW unless explicitly ; allocated a meemory region in .sct file ; Stack size is defined in startup_m2sxxx.s - ; Stack will be added after heap in ER_RW unless explicitly + ; Stack will be added after heap in ER_RW unless explicitly ; allocated a memory region in .sct file as is the case below STACKS 0x20000000 UNINIT { diff --git a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds index 90415e319a0ef05dc7db5c4acd3be1aff893cc6d..3cd31802737f740e81479f55f6d929633b88017b 100644 --- a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds +++ b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e31-arty/flash.lds @@ -30,7 +30,7 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) - + /* section information for finsh shell */ . = ALIGN(4); diff --git a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds index 54c102641e504d84919485609175ded99c08652a..c571a0f87690bfc6d5fa93a69931b6bc792eb187 100644 --- a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds +++ b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/flash.lds @@ -1 +1 @@ -../coreplexip-e31-arty/flash.lds \ No newline at end of file +../coreplexip-e31-arty/flash.lds diff --git a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds index 7fbe10a3ea2ed41021381aa4940105a23e2c3c87..f7f33b8de2bd8b48e6cc54714d6e6024072a758c 100644 --- a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds +++ b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/coreplexip-e51-arty/scratchpad.lds @@ -1 +1 @@ -../coreplexip-e31-arty/scratchpad.lds \ No newline at end of file +../coreplexip-e31-arty/scratchpad.lds diff --git a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds index 6441ce598f221f1a5b3373fdebe7f4fe809d00aa..9661121ef7308ccaaf7e04ad457ad7a0824c6150 100644 --- a/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds +++ b/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/freedom-e300-arty/flash.lds @@ -1 +1 @@ -../freedom-e300-hifive1/flash.lds \ No newline at end of file +../freedom-e300-hifive1/flash.lds diff --git a/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f091xc_sram.icf b/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f091xc_sram.icf index 3fb065139502d0318b83282ae399a0a316b6e291..15980fec4510f47c382d3f5d1d7178da5df092f3 100644 --- a/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f091xc_sram.icf +++ b/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f091xc_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f098xx_sram.icf b/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f098xx_sram.icf index 3fb065139502d0318b83282ae399a0a316b6e291..15980fec4510f47c382d3f5d1d7178da5df092f3 100644 --- a/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f098xx_sram.icf +++ b/bsp/stm32/libraries/STM32F0xx_HAL/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/linker/stm32f098xx_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf index 13405854d1e11b76969e4bff33fed1d35e7b7b34..7c0037531bcc77124be9164ff48508effafca9c4 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf index 1b5ef5a4b97330d2393719382e3436bb8ba95971..c39a043bae46c1e1169b3b61f812169054a10673 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf index eb2bb9d7d8ddfa451283a37ff35cc7bfa26c71ca..e48eda57673e1e5657d2efd8a128c4bedf8e6de5 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf index 90208d57df09fa7270f6f0835be6ad23c3169560..ed4fb445f7786f7c48b5aa74867d69f2791e4246 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf index 515e779c463e38f0c1c3a075e17ee0c59e2382a4..c49e25fa4035760143c03d6264d73f9dd86b92ad 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf index 6f209f2e358308fc325ccdfafa33845035acbb7d..16414a9a3ef032c7b8095c266493504bb331e110 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf index 5f1e44027f753e24a94fa1767d417747ab6c8b1e..7a80276f738d79f67dbee2d317aff4cd828e470b 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf index 13405854d1e11b76969e4bff33fed1d35e7b7b34..7c0037531bcc77124be9164ff48508effafca9c4 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf index 515e779c463e38f0c1c3a075e17ee0c59e2382a4..c49e25fa4035760143c03d6264d73f9dd86b92ad 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf index 515e779c463e38f0c1c3a075e17ee0c59e2382a4..c49e25fa4035760143c03d6264d73f9dd86b92ad 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf index 6f209f2e358308fc325ccdfafa33845035acbb7d..16414a9a3ef032c7b8095c266493504bb331e110 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf index dbfbec286e73cefa6bf6c0032e4a011e0a05ca11..1ff96727b23712f49f989b4dad1fcd6f49e8a040 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf index dbfbec286e73cefa6bf6c0032e4a011e0a05ca11..1ff96727b23712f49f989b4dad1fcd6f49e8a040 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf index 5f1e44027f753e24a94fa1767d417747ab6c8b1e..7a80276f738d79f67dbee2d317aff4cd828e470b 100644 --- a/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf +++ b/bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xc_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xc_flash.icf index b6029122d393c978b0b53d6576a6606bab4223ab..0d442b2807e41b0a83b653df090a4171bcfd6890 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xc_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xc_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xe_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xe_flash.icf index a071d017d938e2aef1d2eeca72c9c4134283f47c..213647e5d7a9954c4c1c86f6f398d22262e6952f 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xe_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f401xe_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f405xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f405xx_flash.icf index 88462334e27bee2e087ef8b66f8311d93fc3a8d1..1758878ffdd31f1a35b06e189c1caf15aa48d682 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f405xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f405xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f407xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f407xx_flash.icf index 88462334e27bee2e087ef8b66f8311d93fc3a8d1..1758878ffdd31f1a35b06e189c1caf15aa48d682 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f407xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f407xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410cx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410cx_flash.icf index 0758c01716b8b5c840871f2e20c3bde782823975..edad34cb66144094f754532d8e0d4899d9b95949 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410cx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410cx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410rx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410rx_flash.icf index 0758c01716b8b5c840871f2e20c3bde782823975..edad34cb66144094f754532d8e0d4899d9b95949 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410rx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410rx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410tx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410tx_flash.icf index 0758c01716b8b5c840871f2e20c3bde782823975..edad34cb66144094f754532d8e0d4899d9b95949 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410tx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f410tx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f411xe_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f411xe_flash.icf index 6c3a139ad9d38529c611b009378db22e2a85fb64..5209ada3aee68fae75321104947eb1027e6c39a1 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f411xe_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f411xe_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412cx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412cx_flash.icf index 6ef8277a43d4106df551bc3956a98b8c41054b35..5e592d0956fffe4f460274eaf00e2a586f167765 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412cx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412cx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412rx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412rx_flash.icf index 6ef8277a43d4106df551bc3956a98b8c41054b35..5e592d0956fffe4f460274eaf00e2a586f167765 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412rx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412rx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412vx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412vx_flash.icf index 6ef8277a43d4106df551bc3956a98b8c41054b35..5e592d0956fffe4f460274eaf00e2a586f167765 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412vx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412vx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412zx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412zx_flash.icf index 6ef8277a43d4106df551bc3956a98b8c41054b35..5e592d0956fffe4f460274eaf00e2a586f167765 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412zx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f412zx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f413xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f413xx_flash.icf index 068644aade22cb91ec0818a0986704d7acd6d42f..688e56519a1e69f0c0ff3e4d7d38d9a0f1e15583 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f413xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f413xx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f415xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f415xx_flash.icf index 88462334e27bee2e087ef8b66f8311d93fc3a8d1..1758878ffdd31f1a35b06e189c1caf15aa48d682 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f415xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f415xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f417xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f417xx_flash.icf index 88462334e27bee2e087ef8b66f8311d93fc3a8d1..1758878ffdd31f1a35b06e189c1caf15aa48d682 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f417xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f417xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f423xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f423xx_flash.icf index 068644aade22cb91ec0818a0986704d7acd6d42f..688e56519a1e69f0c0ff3e4d7d38d9a0f1e15583 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f423xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f423xx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_flash.icf index 8d2caf0218c19f5e50a38c4deb22f20353b2fbc2..509203dae0a29ee40c3a08b5662f304af29461e9 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_flash.icf index 8d2caf0218c19f5e50a38c4deb22f20353b2fbc2..509203dae0a29ee40c3a08b5662f304af29461e9 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_flash.icf index 8d2caf0218c19f5e50a38c4deb22f20353b2fbc2..509203dae0a29ee40c3a08b5662f304af29461e9 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f439xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f439xx_flash.icf index 8d2caf0218c19f5e50a38c4deb22f20353b2fbc2..509203dae0a29ee40c3a08b5662f304af29461e9 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f439xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f439xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f446xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f446xx_flash.icf index 6c3a139ad9d38529c611b009378db22e2a85fb64..5209ada3aee68fae75321104947eb1027e6c39a1 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f446xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f446xx_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f469xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f469xx_flash.icf index 8887acdc17e1560b11be175bb5aa8f9ba08a3c55..0a2d4db5998fd34fdad6f9ef60caf228a5e656f8 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f469xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f469xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f479xx_flash.icf b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f479xx_flash.icf index 8887acdc17e1560b11be175bb5aa8f9ba08a3c55..0a2d4db5998fd34fdad6f9ef60caf228a5e656f8 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f479xx_flash.icf +++ b/bsp/stm32/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f479xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf index e846ed657b5cbdd8f158f8caad9aadbd19b151c8..ba273774c65fd9df128f7e2f96a0babe61c6af78 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf index 6907b2ba2235fbad9cd3303e85e5119f5abe8c75..dcb8691c1cb1ac39c94f606a71a0c8894327d41e 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf index e846ed657b5cbdd8f158f8caad9aadbd19b151c8..ba273774c65fd9df128f7e2f96a0babe61c6af78 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf index 6907b2ba2235fbad9cd3303e85e5119f5abe8c75..dcb8691c1cb1ac39c94f606a71a0c8894327d41e 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_ITCM_flash.icf index 9195b7dc11b418bd4185f5613662b0993ab6a4c2..588364a9ca17661ca778058014b72ed3ca4a704d 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_flash.icf index 4fe13219622eab2bd2280e79c8aabaf314626371..75e56e2726918f6eef63002b6ec4ca4078a8dbe2 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f730xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf index e846ed657b5cbdd8f158f8caad9aadbd19b151c8..ba273774c65fd9df128f7e2f96a0babe61c6af78 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf index 6907b2ba2235fbad9cd3303e85e5119f5abe8c75..dcb8691c1cb1ac39c94f606a71a0c8894327d41e 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf index e846ed657b5cbdd8f158f8caad9aadbd19b151c8..ba273774c65fd9df128f7e2f96a0babe61c6af78 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf index 6907b2ba2235fbad9cd3303e85e5119f5abe8c75..dcb8691c1cb1ac39c94f606a71a0c8894327d41e 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf index d7482e4bffce71f56b83b6bfafd5a687f4af8058..df31425288520edc0478fa61c9640c6c242507e1 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf index 8c407835b996d3c3a23eaf4e9338a78cd6a105e3..b16979544bc5430b41e0fed7e7e77d6834a6a5a7 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf index d7482e4bffce71f56b83b6bfafd5a687f4af8058..df31425288520edc0478fa61c9640c6c242507e1 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf index 8c407835b996d3c3a23eaf4e9338a78cd6a105e3..b16979544bc5430b41e0fed7e7e77d6834a6a5a7 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_ITCM_flash.icf index 73781e04c6f44dd7f5ff93e459115f34343c2235..56039bd9c806ed73768befedfd38e685a6eb4cce 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_flash.icf index dc1d0dab086e7d7d7db496b219723e32b3083aff..2b2cefe0641968101f62cd65eb5eff390b49a550 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f750xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf index d7482e4bffce71f56b83b6bfafd5a687f4af8058..df31425288520edc0478fa61c9640c6c242507e1 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf index 8c407835b996d3c3a23eaf4e9338a78cd6a105e3..b16979544bc5430b41e0fed7e7e77d6834a6a5a7 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf index 4b64e00aaf8daebfcd47c60c72069f1aa01ff4e2..366561f53a9afac12ea65e0ea35408a166051dbb 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf index 909fe02b3a1a49c9d1db6e3f73e3e9277390d523..8e410e58e646442fd397bc2feda247650fdda99b 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf index 4b64e00aaf8daebfcd47c60c72069f1aa01ff4e2..366561f53a9afac12ea65e0ea35408a166051dbb 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf index 909fe02b3a1a49c9d1db6e3f73e3e9277390d523..8e410e58e646442fd397bc2feda247650fdda99b 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf index 4b64e00aaf8daebfcd47c60c72069f1aa01ff4e2..366561f53a9afac12ea65e0ea35408a166051dbb 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf index 909fe02b3a1a49c9d1db6e3f73e3e9277390d523..8e410e58e646442fd397bc2feda247650fdda99b 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf index 4b64e00aaf8daebfcd47c60c72069f1aa01ff4e2..366561f53a9afac12ea65e0ea35408a166051dbb 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf index 909fe02b3a1a49c9d1db6e3f73e3e9277390d523..8e410e58e646442fd397bc2feda247650fdda99b 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf index 4b64e00aaf8daebfcd47c60c72069f1aa01ff4e2..366561f53a9afac12ea65e0ea35408a166051dbb 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in ITCMRAM_region { }; \ No newline at end of file +place in ITCMRAM_region { }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf index 909fe02b3a1a49c9d1db6e3f73e3e9277390d523..8e410e58e646442fd397bc2feda247650fdda99b 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_flash.icf index ac19dec3da6d057380186663b1dc12ca40145ae4..397a960ef40cbcd7a7b689c4e3ab3cb8c2d2023b 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_flash.icf @@ -30,4 +30,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_sram.icf index b02c6b1489d3b48e0eebb71f356c7ccddc1a5c04..831df876064163589c1540d0d545a7fad52f7663 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_flash.icf index ac19dec3da6d057380186663b1dc12ca40145ae4..397a960ef40cbcd7a7b689c4e3ab3cb8c2d2023b 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_flash.icf @@ -30,4 +30,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_sram.icf index b02c6b1489d3b48e0eebb71f356c7ccddc1a5c04..831df876064163589c1540d0d545a7fad52f7663 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_flash.icf index ac19dec3da6d057380186663b1dc12ca40145ae4..397a960ef40cbcd7a7b689c4e3ab3cb8c2d2023b 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_flash.icf @@ -30,4 +30,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_sram.icf index b02c6b1489d3b48e0eebb71f356c7ccddc1a5c04..831df876064163589c1540d0d545a7fad52f7663 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_flash.icf index e37d1888f82e39c94af1672405c935fdfa841a03..ce8f039c383d227260dacc64a1ef083bcac3a076 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_flash.icf @@ -30,4 +30,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_sram.icf index d640cad32b862b26ff38d7979bf352966fecfc28..0c92b30afce9d4a117ee0dd9229d00619e888146 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_flash.icf index e37d1888f82e39c94af1672405c935fdfa841a03..ce8f039c383d227260dacc64a1ef083bcac3a076 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_flash.icf @@ -30,4 +30,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_sram.icf index d640cad32b862b26ff38d7979bf352966fecfc28..0c92b30afce9d4a117ee0dd9229d00619e888146 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_flash.icf index e37d1888f82e39c94af1672405c935fdfa841a03..ce8f039c383d227260dacc64a1ef083bcac3a076 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_flash.icf @@ -30,4 +30,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_sram.icf index d640cad32b862b26ff38d7979bf352966fecfc28..0c92b30afce9d4a117ee0dd9229d00619e888146 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_flash.icf index 687d9e51dc5a741f6ebd6cea79530f341274957b..d2657b8733629ac64d934afef0dd672209fe4726 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_flash.icf @@ -30,4 +30,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_sram.icf index ea3df3ff8727f2ee097a73b9f5cee24e577ef1d5..0d1b532169f2fb5aa46c897302b81d76308d37b0 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_flash.icf index 687d9e51dc5a741f6ebd6cea79530f341274957b..d2657b8733629ac64d934afef0dd672209fe4726 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_flash.icf @@ -30,4 +30,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_sram.icf index ea3df3ff8727f2ee097a73b9f5cee24e577ef1d5..0d1b532169f2fb5aa46c897302b81d76308d37b0 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_flash.icf index 687d9e51dc5a741f6ebd6cea79530f341274957b..d2657b8733629ac64d934afef0dd672209fe4726 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_flash.icf @@ -30,4 +30,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_sram.icf index 67dc6c1b99d1dd034d8f0df28fe5630b30fedf4f..3b8cf65d3a23af6c52aaa1a1954480630352152e 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_flash.icf index ee2ad5f713db752f25f8f61e19a11cd1545be252..34555c70e46b1643b71d0c5ad830b024e48298c5 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_flash.icf @@ -31,4 +31,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_sram.icf index 25c78d83a5464dc1c0a17bcc31a10a5e08786417..dceb24ccf8e55bc2cd75cbf546eec733be3c0fb8 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_flash.icf index ee2ad5f713db752f25f8f61e19a11cd1545be252..34555c70e46b1643b71d0c5ad830b024e48298c5 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_flash.icf @@ -31,4 +31,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_sram.icf index 25c78d83a5464dc1c0a17bcc31a10a5e08786417..dceb24ccf8e55bc2cd75cbf546eec733be3c0fb8 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_flash.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_flash.icf index ee2ad5f713db752f25f8f61e19a11cd1545be252..34555c70e46b1643b71d0c5ad830b024e48298c5 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_flash.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_flash.icf @@ -31,4 +31,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; \ No newline at end of file +export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_sram.icf b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_sram.icf index 25c78d83a5464dc1c0a17bcc31a10a5e08786417..dceb24ccf8e55bc2cd75cbf546eec733be3c0fb8 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_sram.icf +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf index d8ee3b29a0d1558636a547e04a594c003d18b5a1..120e408800c0c09bf8a63427fcbe2e1479ce2518 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf index c13609a56c9515da48f3d1c9341c19b8ededae07..786b5309fafb034504781ae2b324f604f345cdf2 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf index 36299129c29fd627563b733e66401eab98b30f28..6fac414de8e35da07c4978d08abf70ed0f3f8c48 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf index 36299129c29fd627563b733e66401eab98b30f28..6fac414de8e35da07c4978d08abf70ed0f3f8c48 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf index c13609a56c9515da48f3d1c9341c19b8ededae07..786b5309fafb034504781ae2b324f604f345cdf2 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf index 06dda3fb48a9090f6a1e1b51255387edb0e120ba..0a311b3b98a07f9b1c107398218333795a901a98 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf index 7e0c7663187b598c87f2d0f375717235f22dcdb1..25107b9c73b0735e9736ff80cd8f3effe5d964b0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf index 5700b38c90eadc4638805680a7d46e3707734e2a..a36d5107d7fd7218e182792d307593cc5c989ce0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf index 5700b38c90eadc4638805680a7d46e3707734e2a..a36d5107d7fd7218e182792d307593cc5c989ce0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf index 7e0c7663187b598c87f2d0f375717235f22dcdb1..25107b9c73b0735e9736ff80cd8f3effe5d964b0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf index d8ee3b29a0d1558636a547e04a594c003d18b5a1..120e408800c0c09bf8a63427fcbe2e1479ce2518 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf index c13609a56c9515da48f3d1c9341c19b8ededae07..786b5309fafb034504781ae2b324f604f345cdf2 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf index 36299129c29fd627563b733e66401eab98b30f28..6fac414de8e35da07c4978d08abf70ed0f3f8c48 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf index 36299129c29fd627563b733e66401eab98b30f28..6fac414de8e35da07c4978d08abf70ed0f3f8c48 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf index c13609a56c9515da48f3d1c9341c19b8ededae07..786b5309fafb034504781ae2b324f604f345cdf2 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf index 06dda3fb48a9090f6a1e1b51255387edb0e120ba..0a311b3b98a07f9b1c107398218333795a901a98 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf index 7e0c7663187b598c87f2d0f375717235f22dcdb1..25107b9c73b0735e9736ff80cd8f3effe5d964b0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf index 5700b38c90eadc4638805680a7d46e3707734e2a..a36d5107d7fd7218e182792d307593cc5c989ce0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf index 5700b38c90eadc4638805680a7d46e3707734e2a..a36d5107d7fd7218e182792d307593cc5c989ce0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf index 7e0c7663187b598c87f2d0f375717235f22dcdb1..25107b9c73b0735e9736ff80cd8f3effe5d964b0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf index bac75da3f61150db05f5a69230b0d73b4e9b2b48..775795c3ef918de7f14c7175fef28a5239ebffed 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf index 43d3b0e5dcb8575ab385d296443fb290fa7edc83..580ff62f6d9fb7e9f52fdf73a0c204327dcda7e5 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf index 8a239fda65382853a7365079bfb566105da9a90d..5e845c1ea80fdd6ae5d0ad04a76301dc863e15f4 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf index 8a239fda65382853a7365079bfb566105da9a90d..5e845c1ea80fdd6ae5d0ad04a76301dc863e15f4 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf index 43d3b0e5dcb8575ab385d296443fb290fa7edc83..580ff62f6d9fb7e9f52fdf73a0c204327dcda7e5 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf index bac75da3f61150db05f5a69230b0d73b4e9b2b48..775795c3ef918de7f14c7175fef28a5239ebffed 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf index 43d3b0e5dcb8575ab385d296443fb290fa7edc83..580ff62f6d9fb7e9f52fdf73a0c204327dcda7e5 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf index 8a239fda65382853a7365079bfb566105da9a90d..5e845c1ea80fdd6ae5d0ad04a76301dc863e15f4 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf index 8a239fda65382853a7365079bfb566105da9a90d..5e845c1ea80fdd6ae5d0ad04a76301dc863e15f4 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf index 43d3b0e5dcb8575ab385d296443fb290fa7edc83..580ff62f6d9fb7e9f52fdf73a0c204327dcda7e5 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf index 06dda3fb48a9090f6a1e1b51255387edb0e120ba..0a311b3b98a07f9b1c107398218333795a901a98 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf index 7e0c7663187b598c87f2d0f375717235f22dcdb1..25107b9c73b0735e9736ff80cd8f3effe5d964b0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf index 5700b38c90eadc4638805680a7d46e3707734e2a..a36d5107d7fd7218e182792d307593cc5c989ce0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf index 5700b38c90eadc4638805680a7d46e3707734e2a..a36d5107d7fd7218e182792d307593cc5c989ce0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf index 7e0c7663187b598c87f2d0f375717235f22dcdb1..25107b9c73b0735e9736ff80cd8f3effe5d964b0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf index 06dda3fb48a9090f6a1e1b51255387edb0e120ba..0a311b3b98a07f9b1c107398218333795a901a98 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf index 7e0c7663187b598c87f2d0f375717235f22dcdb1..25107b9c73b0735e9736ff80cd8f3effe5d964b0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf index 5700b38c90eadc4638805680a7d46e3707734e2a..a36d5107d7fd7218e182792d307593cc5c989ce0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf index 5700b38c90eadc4638805680a7d46e3707734e2a..a36d5107d7fd7218e182792d307593cc5c989ce0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf index 7e0c7663187b598c87f2d0f375717235f22dcdb1..25107b9c73b0735e9736ff80cd8f3effe5d964b0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf index 8181a07b57902e1f5b54498c181573582eb267c3..d220fad4a0fce590d9eb58db2cb819cd5fa39d7b 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf index 178e68833c93735e684e48eb5d57c29246c907a9..2f746c0de0ed44456498f532b9fb41947234746d 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf @@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf index 3ff287d162e98f028655be643cff8f52595961fb..9cdf4e896af512fed2d8998e500f93737bc2c161 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf @@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf index 90448efaa884cdbdbc724330f3f2107bd775a131..801b290542991ab006c663b4bf1fd6dbc859201d 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf @@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf index e9acc00ccd00c300b80509c0d181994507adcadd..4030ade19613ec7c528359dc7bdab30ae2d15c1e 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf index 97b074590e36a97bb4c9cb76ab9e5dbf4b1116e7..569b1b1f39554a26ae89463491a6d825b083dbc6 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf index 4580655b71528de1e26b650520aefefb188fe74f..ebec5e3d123b13227a77e849dbf6dd51bdeb3e54 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf index 7dbb925a5ca77ed60a5849a2423e326484854471..0a45c8f05d10294d7fb4be412a38cddbb36f9de0 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf index 178e68833c93735e684e48eb5d57c29246c907a9..2f746c0de0ed44456498f532b9fb41947234746d 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf @@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf index 2592f281f72a1a5e8ad4cfa5ad21a83e6725d9f0..b99ff58e2aba4452612df7d4ac9474c6c882af71 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf @@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf index b8aeb0e44abe3ae591cfa555d255f07851e7fb6d..f14c7979b7a556c9b45f38a7566ade14cbfa676f 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf @@ -34,4 +34,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf index e9acc00ccd00c300b80509c0d181994507adcadd..4030ade19613ec7c528359dc7bdab30ae2d15c1e 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf index fabf1a576e581fa60f47f2fdf780d75fbd757a98..acf62a20af5e0e66324fa417d06d3c1109e7cacc 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf index 40be3e00d91a3af705fcdf116dd02ffe873346fa..b882a4708df8196c1efd44f2923507e86bcf4f19 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf index d507b31e08c381dfba723f4a63ebe0dee4aebf14..26e370a4932613fa20ede354ae2b0805632f9642 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf index 43db630fe04222a7b04c01e2de19dc8e8673e3f5..1d13de71f006e18e7a8f769715c98f0f076cc0fc 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf index d8ee3b29a0d1558636a547e04a594c003d18b5a1..120e408800c0c09bf8a63427fcbe2e1479ce2518 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf index 60c963fe2b674c053a41ad0383dd058a55407c0e..55f2bd5c23b96e8b84e19daf66f9feebb4b1a2b8 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf index 06dda3fb48a9090f6a1e1b51255387edb0e120ba..0a311b3b98a07f9b1c107398218333795a901a98 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf index 77078ce679218b83b56af7a0037eb94fe06b89a6..1e146ebfb7202ca0a13689eeb33c5bb4557e9d0f 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf index 60c963fe2b674c053a41ad0383dd058a55407c0e..55f2bd5c23b96e8b84e19daf66f9feebb4b1a2b8 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf index d507b31e08c381dfba723f4a63ebe0dee4aebf14..26e370a4932613fa20ede354ae2b0805632f9642 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf index b743f61c92fa0e195721e27fc3ac3262998f6b3a..da01275fcc6acdaebd6c37df8a1adb05a68e5f8c 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf index 43db630fe04222a7b04c01e2de19dc8e8673e3f5..1d13de71f006e18e7a8f769715c98f0f076cc0fc 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf index d8ee3b29a0d1558636a547e04a594c003d18b5a1..120e408800c0c09bf8a63427fcbe2e1479ce2518 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf index 60c963fe2b674c053a41ad0383dd058a55407c0e..55f2bd5c23b96e8b84e19daf66f9feebb4b1a2b8 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf index 06dda3fb48a9090f6a1e1b51255387edb0e120ba..0a311b3b98a07f9b1c107398218333795a901a98 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf index 77078ce679218b83b56af7a0037eb94fe06b89a6..1e146ebfb7202ca0a13689eeb33c5bb4557e9d0f 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf index 60c963fe2b674c053a41ad0383dd058a55407c0e..55f2bd5c23b96e8b84e19daf66f9feebb4b1a2b8 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf index d507b31e08c381dfba723f4a63ebe0dee4aebf14..26e370a4932613fa20ede354ae2b0805632f9642 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf index b743f61c92fa0e195721e27fc3ac3262998f6b3a..da01275fcc6acdaebd6c37df8a1adb05a68e5f8c 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf index bac75da3f61150db05f5a69230b0d73b4e9b2b48..775795c3ef918de7f14c7175fef28a5239ebffed 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf index 1f0300f11147f94d9fa6d5d245a8da1726ebc180..29bdd062c2059ff8895729ecc314a96c9e5f02b2 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf index 7a1a38f7796562bda0610b5904cb4afdfc83efe5..4366e250782ab3fe8735402a7b6bed9265cb28bf 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf index d507b31e08c381dfba723f4a63ebe0dee4aebf14..26e370a4932613fa20ede354ae2b0805632f9642 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf index e9acc00ccd00c300b80509c0d181994507adcadd..4030ade19613ec7c528359dc7bdab30ae2d15c1e 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf index fabf1a576e581fa60f47f2fdf780d75fbd757a98..acf62a20af5e0e66324fa417d06d3c1109e7cacc 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf index 40be3e00d91a3af705fcdf116dd02ffe873346fa..b882a4708df8196c1efd44f2923507e86bcf4f19 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf index d507b31e08c381dfba723f4a63ebe0dee4aebf14..26e370a4932613fa20ede354ae2b0805632f9642 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf index 60c963fe2b674c053a41ad0383dd058a55407c0e..55f2bd5c23b96e8b84e19daf66f9feebb4b1a2b8 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf index 06dda3fb48a9090f6a1e1b51255387edb0e120ba..0a311b3b98a07f9b1c107398218333795a901a98 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf index 77078ce679218b83b56af7a0037eb94fe06b89a6..1e146ebfb7202ca0a13689eeb33c5bb4557e9d0f 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf index 60c963fe2b674c053a41ad0383dd058a55407c0e..55f2bd5c23b96e8b84e19daf66f9feebb4b1a2b8 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf index d507b31e08c381dfba723f4a63ebe0dee4aebf14..26e370a4932613fa20ede354ae2b0805632f9642 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf index b743f61c92fa0e195721e27fc3ac3262998f6b3a..da01275fcc6acdaebd6c37df8a1adb05a68e5f8c 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf index d134adadc0a0a84102edc781b2ca81d8bd0e06ff..6ba5b25337b6b4b34f42ad0b060329a7aeba7e22 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf index 60c963fe2b674c053a41ad0383dd058a55407c0e..55f2bd5c23b96e8b84e19daf66f9feebb4b1a2b8 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf index 06dda3fb48a9090f6a1e1b51255387edb0e120ba..0a311b3b98a07f9b1c107398218333795a901a98 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf index 77078ce679218b83b56af7a0037eb94fe06b89a6..1e146ebfb7202ca0a13689eeb33c5bb4557e9d0f 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf index 60c963fe2b674c053a41ad0383dd058a55407c0e..55f2bd5c23b96e8b84e19daf66f9feebb4b1a2b8 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf index d507b31e08c381dfba723f4a63ebe0dee4aebf14..26e370a4932613fa20ede354ae2b0805632f9642 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf index b743f61c92fa0e195721e27fc3ac3262998f6b3a..da01275fcc6acdaebd6c37df8a1adb05a68e5f8c 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf index 7baac68acc1780cbff9350cd8989126837eccfd3..a891cbe98a141e39e913bbcb26a8f4fd2be9600d 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf index bf367cc909344d5eb06082e48f171f919f21050b..eaab44260b6ae254caeb09bb015269d8e49e249c 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf index 01dbf5dddad71aaa4c57044aab738d13d9655856..2eb3e6c4ccf04727046ce1504c4c87dbdf5379cc 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf index 7baac68acc1780cbff9350cd8989126837eccfd3..a891cbe98a141e39e913bbcb26a8f4fd2be9600d 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf index bf367cc909344d5eb06082e48f171f919f21050b..eaab44260b6ae254caeb09bb015269d8e49e249c 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf index 7b7313f0ea8a88065ef86cb543aa6b25b867aab8..941b1c70b1dbe71da5430ab3de5ed98a32e56290 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf index 605b4a7069b4766701e6a1063a720c18541bd059..9eea96f46867778b364f422f41e5e274afbf9798 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf index 3f421269409d5b36334102e350579450e488c29c..b6e14a917e7061cdc611d319c0338f25428fbb54 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf index 335965b1464c0329cfc8855653ec1169bea17b2d..6206b5e26d0e7572b7243387ffa93e957e0eb49e 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf index 605b4a7069b4766701e6a1063a720c18541bd059..9eea96f46867778b364f422f41e5e274afbf9798 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf index 3f421269409d5b36334102e350579450e488c29c..b6e14a917e7061cdc611d319c0338f25428fbb54 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf index 335965b1464c0329cfc8855653ec1169bea17b2d..6206b5e26d0e7572b7243387ffa93e957e0eb49e 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf index e401b4cbbc13f8a5bb4a57253e0a16b01436fb42..d794d6840ead1f3f56f5922740499e638f5e56cf 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf index 8da98b181f521df65bf0c8bb8cee7178d1417f17..152d46c4b56af4f93c9eafe6ed3a123d48624f3a 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf index 17615f163854533c0abf4de701f3e587d672ca15..c191644931c84f0dcf637dc772be4ba48a6dba12 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf index e401b4cbbc13f8a5bb4a57253e0a16b01436fb42..d794d6840ead1f3f56f5922740499e638f5e56cf 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf index 8da98b181f521df65bf0c8bb8cee7178d1417f17..152d46c4b56af4f93c9eafe6ed3a123d48624f3a 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf index 17615f163854533c0abf4de701f3e587d672ca15..c191644931c84f0dcf637dc772be4ba48a6dba12 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf index 605b4a7069b4766701e6a1063a720c18541bd059..9eea96f46867778b364f422f41e5e274afbf9798 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf index 3f421269409d5b36334102e350579450e488c29c..b6e14a917e7061cdc611d319c0338f25428fbb54 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf index 335965b1464c0329cfc8855653ec1169bea17b2d..6206b5e26d0e7572b7243387ffa93e957e0eb49e 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf index 605b4a7069b4766701e6a1063a720c18541bd059..9eea96f46867778b364f422f41e5e274afbf9798 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf index 3f421269409d5b36334102e350579450e488c29c..b6e14a917e7061cdc611d319c0338f25428fbb54 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf index 335965b1464c0329cfc8855653ec1169bea17b2d..6206b5e26d0e7572b7243387ffa93e957e0eb49e 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf +++ b/bsp/stm32/libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf index 6961d18bb9251a9943adaaeb8d992546a7ab3713..df2b7016431b0aded3470722b0c33cf10d356e85 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x4_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf index dd1738f9bd124ddd8a7cb90fd92aa08c90291455..50f3429d492c18308789260390b07f0d0499f79a 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x6_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf index 5e6f04e19c33ffc2881ffbdf9de88a73fe66bd1c..5103af67a29d23a5bf64edb5ae76391600ffe2d1 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010x8_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf index 89ca0b8a162e4358a88d64046e21d1d844f08b9f..b736298384673670c5f13dbffaedf49f9787d5f6 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l010xb_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf index fe649baf1d1ecb5d3ddb8c19f163c72679f8b270..2c509140dbb4a195c377408ae3d96d4e295f9017 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf index b7bee2a287cfe584d5cc816e1db1f0102bfdfa3e..21e87f4cbc5f1ca415f029477dad29df656e7c4f 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l011xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf index fe649baf1d1ecb5d3ddb8c19f163c72679f8b270..2c509140dbb4a195c377408ae3d96d4e295f9017 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf index b7bee2a287cfe584d5cc816e1db1f0102bfdfa3e..21e87f4cbc5f1ca415f029477dad29df656e7c4f 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l021xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf index 2694412b5ae5076b7f308f4f3ed77b57ea9d917f..b23b63e7cdad68bff412cf28561e449737ec1943 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf index ab13a073d44f350660650c6a5c97a29216d99b3a..bdcd3702bbf93cda8aa9cb5a7a88d20d7028fdd1 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l031xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf index 2694412b5ae5076b7f308f4f3ed77b57ea9d917f..b23b63e7cdad68bff412cf28561e449737ec1943 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf index ab13a073d44f350660650c6a5c97a29216d99b3a..bdcd3702bbf93cda8aa9cb5a7a88d20d7028fdd1 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l041xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf index 58b6084015efb1f4afab52f71a3ef45d91dd0110..667bb404569ea96eb157ff56d4736806bff45446 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf index 70a8c3e32651414532fc0f28f2e2d2c5a575ab6c..42ede5c30356a9f1b193166eb24575504d771464 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l051xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf index 58b6084015efb1f4afab52f71a3ef45d91dd0110..667bb404569ea96eb157ff56d4736806bff45446 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf index 70a8c3e32651414532fc0f28f2e2d2c5a575ab6c..42ede5c30356a9f1b193166eb24575504d771464 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l052xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf index 58b6084015efb1f4afab52f71a3ef45d91dd0110..667bb404569ea96eb157ff56d4736806bff45446 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf index 70a8c3e32651414532fc0f28f2e2d2c5a575ab6c..42ede5c30356a9f1b193166eb24575504d771464 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l053xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf index 58b6084015efb1f4afab52f71a3ef45d91dd0110..667bb404569ea96eb157ff56d4736806bff45446 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf index 70a8c3e32651414532fc0f28f2e2d2c5a575ab6c..42ede5c30356a9f1b193166eb24575504d771464 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l061xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf index 58b6084015efb1f4afab52f71a3ef45d91dd0110..667bb404569ea96eb157ff56d4736806bff45446 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf index 70a8c3e32651414532fc0f28f2e2d2c5a575ab6c..42ede5c30356a9f1b193166eb24575504d771464 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l062xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf index 58b6084015efb1f4afab52f71a3ef45d91dd0110..667bb404569ea96eb157ff56d4736806bff45446 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf index 70a8c3e32651414532fc0f28f2e2d2c5a575ab6c..42ede5c30356a9f1b193166eb24575504d771464 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l063xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf index 650aa680a0831f100421ab7bf4e79c789d32b7dc..7b89f73b85527dc54f6bac425aaa114692bf14b5 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf index c2699c75b26180d82a9129a799b95b0470cd1f84..48b9fe84ceaf150220ab5e58ad7a593b97f3b5aa 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l071xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf index 650aa680a0831f100421ab7bf4e79c789d32b7dc..7b89f73b85527dc54f6bac425aaa114692bf14b5 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf index c2699c75b26180d82a9129a799b95b0470cd1f84..48b9fe84ceaf150220ab5e58ad7a593b97f3b5aa 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l072xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf index 650aa680a0831f100421ab7bf4e79c789d32b7dc..7b89f73b85527dc54f6bac425aaa114692bf14b5 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf index c2699c75b26180d82a9129a799b95b0470cd1f84..48b9fe84ceaf150220ab5e58ad7a593b97f3b5aa 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l073xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf index 650aa680a0831f100421ab7bf4e79c789d32b7dc..7b89f73b85527dc54f6bac425aaa114692bf14b5 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf index c2699c75b26180d82a9129a799b95b0470cd1f84..48b9fe84ceaf150220ab5e58ad7a593b97f3b5aa 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l081xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf index 650aa680a0831f100421ab7bf4e79c789d32b7dc..7b89f73b85527dc54f6bac425aaa114692bf14b5 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf index c2699c75b26180d82a9129a799b95b0470cd1f84..48b9fe84ceaf150220ab5e58ad7a593b97f3b5aa 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l082xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf index 650aa680a0831f100421ab7bf4e79c789d32b7dc..7b89f73b85527dc54f6bac425aaa114692bf14b5 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf index c2699c75b26180d82a9129a799b95b0470cd1f84..48b9fe84ceaf150220ab5e58ad7a593b97f3b5aa 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf +++ b/bsp/stm32/libraries/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/linker/stm32l083xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf index bf73f0830315e5e887e000f327cee6f0511fe539..60a65a36610a4bdfd9bbf7419baa42f307b171d9 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf index 3ab8d539bf756c0a1f47a957425d868f48b6fe0c..31816211d0f9dbde8ced69684a052cd69f71ed86 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf index 43b2852bbb9716a7dff10424bc727e295bf9c0b1..ef5c3783033edd1516a23f103cc6c8eccfbc1e4c 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf index 100be96c76d6c03b18d7979f7056ee90f830cc6d..10206dc0169e06adba6afb22326b6dbd0d6023be 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf index 43e70adc739f6d455ed9a4bab2e4f5ae3e545dae..172bc663bdcbb34082b28f537a29a7318e3fb7ed 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf index 100be96c76d6c03b18d7979f7056ee90f830cc6d..10206dc0169e06adba6afb22326b6dbd0d6023be 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf index 43b2852bbb9716a7dff10424bc727e295bf9c0b1..ef5c3783033edd1516a23f103cc6c8eccfbc1e4c 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf index 100be96c76d6c03b18d7979f7056ee90f830cc6d..10206dc0169e06adba6afb22326b6dbd0d6023be 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf index a54a4cc82382fd7dd1c215c2a5cb6b95a68d0ebe..bc51d1f07fe353c9bc4e12ea32c446086988f151 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf index a5549107949253a970be3e344e5672fe5a61393d..2374f5c85a33b7d9428f351eb469596b0dda2fa4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf index 008afe1f434be6c993af195fe140c4d12208faf3..8bc6a84fb5076f3092760db389a2a77f9676c897 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf index a5549107949253a970be3e344e5672fe5a61393d..2374f5c85a33b7d9428f351eb469596b0dda2fa4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf index 008afe1f434be6c993af195fe140c4d12208faf3..8bc6a84fb5076f3092760db389a2a77f9676c897 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf index a5549107949253a970be3e344e5672fe5a61393d..2374f5c85a33b7d9428f351eb469596b0dda2fa4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf index e243b7a1ac3caa8e44149b732f60f82cfcfcee74..5d0c798639562b48bed46ac73cd35d30eef5b990 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf index c9c03d05ecfae65129e5dde3b80d7e8c8657c38a..d332a4b46e661b6abecf55ed5f63a98389383aa8 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf index 2fc629bd24e1e61652bed8b16c8945beb6350b32..60ae633020b86a4ec9ad4277199f4653bb1a196d 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf @@ -17,7 +17,7 @@ define symbol __ICFEDIT_size_heap__ = 0x000; define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] | +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] | mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf index c9c03d05ecfae65129e5dde3b80d7e8c8657c38a..d332a4b46e661b6abecf55ed5f63a98389383aa8 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf index 7f75472ad06c47185ca4819abb1d818e7835f6b0..c9e97b1955a9e8a774197858a63adfe12cf866f4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf index f3adea524f444b7eeddcb7e76f43dbd0e117e71f..3ee399dc17017316ed15b436170ca66ab1a72478 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf index 43b2852bbb9716a7dff10424bc727e295bf9c0b1..ef5c3783033edd1516a23f103cc6c8eccfbc1e4c 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf index 100be96c76d6c03b18d7979f7056ee90f830cc6d..10206dc0169e06adba6afb22326b6dbd0d6023be 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf index a54a4cc82382fd7dd1c215c2a5cb6b95a68d0ebe..bc51d1f07fe353c9bc4e12ea32c446086988f151 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf index a5549107949253a970be3e344e5672fe5a61393d..2374f5c85a33b7d9428f351eb469596b0dda2fa4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf index 008afe1f434be6c993af195fe140c4d12208faf3..8bc6a84fb5076f3092760db389a2a77f9676c897 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf index a5549107949253a970be3e344e5672fe5a61393d..2374f5c85a33b7d9428f351eb469596b0dda2fa4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf index 008afe1f434be6c993af195fe140c4d12208faf3..8bc6a84fb5076f3092760db389a2a77f9676c897 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf index a5549107949253a970be3e344e5672fe5a61393d..2374f5c85a33b7d9428f351eb469596b0dda2fa4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf index ecba53e43bf377003d7032a1b698ae3e4423f6c4..3aeec61d41c3f407777f15173897925dcfa06809 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf index c9c03d05ecfae65129e5dde3b80d7e8c8657c38a..d332a4b46e661b6abecf55ed5f63a98389383aa8 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf index 2fc629bd24e1e61652bed8b16c8945beb6350b32..60ae633020b86a4ec9ad4277199f4653bb1a196d 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf @@ -17,7 +17,7 @@ define symbol __ICFEDIT_size_heap__ = 0x000; define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] | +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] | mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf index c9c03d05ecfae65129e5dde3b80d7e8c8657c38a..d332a4b46e661b6abecf55ed5f63a98389383aa8 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf index 7f75472ad06c47185ca4819abb1d818e7835f6b0..c9e97b1955a9e8a774197858a63adfe12cf866f4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf index f3adea524f444b7eeddcb7e76f43dbd0e117e71f..3ee399dc17017316ed15b436170ca66ab1a72478 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf index 008afe1f434be6c993af195fe140c4d12208faf3..8bc6a84fb5076f3092760db389a2a77f9676c897 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf index a5549107949253a970be3e344e5672fe5a61393d..2374f5c85a33b7d9428f351eb469596b0dda2fa4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf index 008afe1f434be6c993af195fe140c4d12208faf3..8bc6a84fb5076f3092760db389a2a77f9676c897 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf index a5549107949253a970be3e344e5672fe5a61393d..2374f5c85a33b7d9428f351eb469596b0dda2fa4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf index e243b7a1ac3caa8e44149b732f60f82cfcfcee74..5d0c798639562b48bed46ac73cd35d30eef5b990 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf index c9c03d05ecfae65129e5dde3b80d7e8c8657c38a..d332a4b46e661b6abecf55ed5f63a98389383aa8 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf index 2fc629bd24e1e61652bed8b16c8945beb6350b32..60ae633020b86a4ec9ad4277199f4653bb1a196d 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf @@ -17,7 +17,7 @@ define symbol __ICFEDIT_size_heap__ = 0x000; define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] | +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] | mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; @@ -31,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf index c9c03d05ecfae65129e5dde3b80d7e8c8657c38a..d332a4b46e661b6abecf55ed5f63a98389383aa8 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf index 7f75472ad06c47185ca4819abb1d818e7835f6b0..c9e97b1955a9e8a774197858a63adfe12cf866f4 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf index f3adea524f444b7eeddcb7e76f43dbd0e117e71f..3ee399dc17017316ed15b436170ca66ab1a72478 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf +++ b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_flash.icf index 88e7323450d648395e9b6ca7f1eafcefa09a3b79..635f4e2c844ff14a8c83009b3eec8b8c797fe262 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_sram.icf index 2901494ad26e85bf9ecb02181834295aae1bfa55..6c253f80521ed25586fb0761445e6afec58467b5 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l412xx_sram.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_flash.icf index 88e7323450d648395e9b6ca7f1eafcefa09a3b79..635f4e2c844ff14a8c83009b3eec8b8c797fe262 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_sram.icf index 2901494ad26e85bf9ecb02181834295aae1bfa55..6c253f80521ed25586fb0761445e6afec58467b5 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l422xx_sram.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_flash.icf index d17c136af55325916fe3e0b0220704ce0d3d7f75..0fbb6c66c4d6b46d4a7167517c6666949a63aefe 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_flash.icf @@ -36,6 +36,6 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in SRAM1_region { }; +place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_sram.icf index b2f947087c378fe3ca2d88d0042f5b400d111936..90fb7264f6dd3b0fc2125cb58a82a1f3eb559036 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l431xx_sram.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_flash.icf index d17c136af55325916fe3e0b0220704ce0d3d7f75..0fbb6c66c4d6b46d4a7167517c6666949a63aefe 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_flash.icf @@ -36,6 +36,6 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in SRAM1_region { }; +place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_sram.icf index b2f947087c378fe3ca2d88d0042f5b400d111936..90fb7264f6dd3b0fc2125cb58a82a1f3eb559036 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l432xx_sram.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_flash.icf index d17c136af55325916fe3e0b0220704ce0d3d7f75..0fbb6c66c4d6b46d4a7167517c6666949a63aefe 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_flash.icf @@ -36,6 +36,6 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in SRAM1_region { }; +place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_sram.icf index b2f947087c378fe3ca2d88d0042f5b400d111936..90fb7264f6dd3b0fc2125cb58a82a1f3eb559036 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l433xx_sram.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_flash.icf index d17c136af55325916fe3e0b0220704ce0d3d7f75..0fbb6c66c4d6b46d4a7167517c6666949a63aefe 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_flash.icf @@ -36,6 +36,6 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in SRAM1_region { }; +place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_sram.icf index b2f947087c378fe3ca2d88d0042f5b400d111936..90fb7264f6dd3b0fc2125cb58a82a1f3eb559036 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l442xx_sram.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_flash.icf index d17c136af55325916fe3e0b0220704ce0d3d7f75..0fbb6c66c4d6b46d4a7167517c6666949a63aefe 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_flash.icf @@ -36,6 +36,6 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in SRAM1_region { }; +place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_sram.icf index b2f947087c378fe3ca2d88d0042f5b400d111936..90fb7264f6dd3b0fc2125cb58a82a1f3eb559036 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l443xx_sram.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l451xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l451xx_sram.icf index ee8e4cd5eb85ea337f1ff5aac2729edb76e8340b..8189bff5972a906f8cf9e129455651f80095f8b0 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l451xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l451xx_sram.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l452xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l452xx_sram.icf index ee8e4cd5eb85ea337f1ff5aac2729edb76e8340b..8189bff5972a906f8cf9e129455651f80095f8b0 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l452xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l452xx_sram.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l462xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l462xx_sram.icf index ee8e4cd5eb85ea337f1ff5aac2729edb76e8340b..8189bff5972a906f8cf9e129455651f80095f8b0 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l462xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l462xx_sram.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_flash.icf index 8377a517656112d55aa39ed73dfc3932f1d3cd45..b4894e4c23e7ddfe37bbf9427b0d46e4f8729f59 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_sram.icf index f024509d5708559c3e591172a6190462c1004c3d..3a7c24140f74364f7dc32b1939ffac2a7c566471 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l471xx_sram.icf @@ -38,4 +38,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_flash.icf index 8377a517656112d55aa39ed73dfc3932f1d3cd45..b4894e4c23e7ddfe37bbf9427b0d46e4f8729f59 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_sram.icf index f024509d5708559c3e591172a6190462c1004c3d..3a7c24140f74364f7dc32b1939ffac2a7c566471 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l475xx_sram.icf @@ -38,4 +38,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_flash.icf index 8377a517656112d55aa39ed73dfc3932f1d3cd45..b4894e4c23e7ddfe37bbf9427b0d46e4f8729f59 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_sram.icf index f024509d5708559c3e591172a6190462c1004c3d..3a7c24140f74364f7dc32b1939ffac2a7c566471 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l476xx_sram.icf @@ -38,4 +38,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_flash.icf index 8377a517656112d55aa39ed73dfc3932f1d3cd45..b4894e4c23e7ddfe37bbf9427b0d46e4f8729f59 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_sram.icf index f024509d5708559c3e591172a6190462c1004c3d..3a7c24140f74364f7dc32b1939ffac2a7c566471 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l485xx_sram.icf @@ -38,4 +38,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_flash.icf index 8377a517656112d55aa39ed73dfc3932f1d3cd45..b4894e4c23e7ddfe37bbf9427b0d46e4f8729f59 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_sram.icf index f024509d5708559c3e591172a6190462c1004c3d..3a7c24140f74364f7dc32b1939ffac2a7c566471 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l486xx_sram.icf @@ -38,4 +38,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { }; diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_flash.icf index 3bba337e33fcec6e9d598729893f2e5d604f1947..2f6d9b243b92070ec9112f52446dfaecb34a0876 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_sram.icf index e2e2316a99bc84d7315b292416103fcfba0456b9..e4f0b87d42c094389fe08da4291cb358381c3821 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l496xx_sram.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_flash.icf index 3bba337e33fcec6e9d598729893f2e5d604f1947..2f6d9b243b92070ec9112f52446dfaecb34a0876 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_sram.icf index e2e2316a99bc84d7315b292416103fcfba0456b9..e4f0b87d42c094389fe08da4291cb358381c3821 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4a6xx_sram.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_flash.icf index 03830346f44f10df49bb0310dd3a8f07fefc0099..4a853f0633c3e701d77122cdc924ae3a2604a625 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_flash.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_sram.icf index 3d87dba0732c16c72ae370354ca752e719d91a06..da3001d86863d5019c0b0b9b9552aa0f6654a05f 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4p5xx_sram.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_flash.icf index 03830346f44f10df49bb0310dd3a8f07fefc0099..4a853f0633c3e701d77122cdc924ae3a2604a625 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_flash.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_sram.icf index 3d87dba0732c16c72ae370354ca752e719d91a06..da3001d86863d5019c0b0b9b9552aa0f6654a05f 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4q5xx_sram.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_flash.icf index 65c554a3a83a3255b8ae86bfdb5d35093e81f934..ab7bb5ebe13468be9c3ffcaaa402fab500d634b5 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_flash.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_sram.icf index 387363a7502fe47521400f3c11d01d58ffcb0139..b8a1f9eb92a91caa9e0fc39751e513e2e9367877 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r5xx_sram.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_flash.icf index 65c554a3a83a3255b8ae86bfdb5d35093e81f934..ab7bb5ebe13468be9c3ffcaaa402fab500d634b5 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_flash.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_sram.icf index 387363a7502fe47521400f3c11d01d58ffcb0139..b8a1f9eb92a91caa9e0fc39751e513e2e9367877 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r7xx_sram.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_flash.icf index 65c554a3a83a3255b8ae86bfdb5d35093e81f934..ab7bb5ebe13468be9c3ffcaaa402fab500d634b5 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_flash.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_sram.icf index 387363a7502fe47521400f3c11d01d58ffcb0139..b8a1f9eb92a91caa9e0fc39751e513e2e9367877 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4r9xx_sram.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_flash.icf index 65c554a3a83a3255b8ae86bfdb5d35093e81f934..ab7bb5ebe13468be9c3ffcaaa402fab500d634b5 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_flash.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_sram.icf index 387363a7502fe47521400f3c11d01d58ffcb0139..b8a1f9eb92a91caa9e0fc39751e513e2e9367877 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s5xx_sram.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_flash.icf index 65c554a3a83a3255b8ae86bfdb5d35093e81f934..ab7bb5ebe13468be9c3ffcaaa402fab500d634b5 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_flash.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_sram.icf index 387363a7502fe47521400f3c11d01d58ffcb0139..b8a1f9eb92a91caa9e0fc39751e513e2e9367877 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s7xx_sram.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_flash.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_flash.icf index 65c554a3a83a3255b8ae86bfdb5d35093e81f934..ab7bb5ebe13468be9c3ffcaaa402fab500d634b5 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_flash.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_flash.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_sram.icf b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_sram.icf index 387363a7502fe47521400f3c11d01d58ffcb0139..b8a1f9eb92a91caa9e0fc39751e513e2e9367877 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_sram.icf +++ b/bsp/stm32/libraries/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/linker/stm32l4s9xx_sram.icf @@ -42,4 +42,4 @@ place in RAM_region { readwrite, place in SRAM1_region { }; place in SRAM2_region { }; place in SRAM3_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash.icf b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash.icf index d5b6e6e15a4cb1cdb6f1ab59184c39bec51194e7..d49d1059ce1b5fd5498ce268992bff282ada207f 100644 --- a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash.icf +++ b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash.icf b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash.icf index 0d533dbf06bba403ddecff2b6fca02ec20f9c624..e043d72a771cf340c839fca8b1a4213da50885bf 100644 --- a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash.icf +++ b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram.icf b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram.icf index 7318e194976283b9178934d1d4b59d64e39af765..800415c14c08ec4b82d6b112983e8272dcb66891 100644 --- a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram.icf +++ b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in RAM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash.icf b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash.icf index 0d533dbf06bba403ddecff2b6fca02ec20f9c624..e043d72a771cf340c839fca8b1a4213da50885bf 100644 --- a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash.icf +++ b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash.icf @@ -38,4 +38,4 @@ place in RAM_region { readwrite, block CSTACK, block HEAP }; place in SRAM1_region { }; place in SRAM2_region { }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram.icf b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram.icf index 7318e194976283b9178934d1d4b59d64e39af765..800415c14c08ec4b82d6b112983e8272dcb66891 100644 --- a/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram.icf +++ b/bsp/stm32/libraries/STM32L5xx_HAL/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram.icf @@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in RAM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf index bd36226b63cf98d7b1d5a69ed8992f80ef20f95c..eaf022c15429f4dd93497bc04618cd790d202c71 100644 --- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf +++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf @@ -37,4 +37,4 @@ do not initialize { section .noinit}; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in text_region { readonly }; place in data_region { readwrite, - block CSTACK, block HEAP}; \ No newline at end of file + block CSTACK, block HEAP}; diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf index 61c66cb76c881715cc28259fd31524f30ccf0c1c..efdecc1199c0f76fc354fbbe7d23aa1d34e53c69 100644 --- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf +++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf @@ -37,4 +37,4 @@ do not initialize { section .noinit}; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in text_region { readonly }; place in data_region { readwrite, - block CSTACK, block HEAP}; \ No newline at end of file + block CSTACK, block HEAP}; diff --git a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_flash.icf b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_flash.icf index bf0e8001492f536479cffb7a5466339a3a730abb..21c8d9a48aa06bb244ba155de1eaf4f8208b1b71 100644 --- a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_flash.icf +++ b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_flash.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram.icf b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram.icf index ddf2f772a09baa52060a0536e3b4d835f2585981..28df48f0e12b84733d4e8300b7bf524f3eeea772 100644 --- a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram.icf +++ b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram_ns.icf b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram_ns.icf index 395e0680335c1c2da9a5ecfb2be991aa38bdfb28..96c8d2b1a02bc97de072c573f6bdb841d728086a 100644 --- a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram_ns.icf +++ b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u575xx_sram_ns.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram.icf b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram.icf index ddf2f772a09baa52060a0536e3b4d835f2585981..28df48f0e12b84733d4e8300b7bf524f3eeea772 100644 --- a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram.icf +++ b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram_ns.icf b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram_ns.icf index 395e0680335c1c2da9a5ecfb2be991aa38bdfb28..96c8d2b1a02bc97de072c573f6bdb841d728086a 100644 --- a/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram_ns.icf +++ b/bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/iar/linker/stm32u585xx_sram_ns.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; - \ No newline at end of file + diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_flash_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_flash_cm4.icf index e9cc1dd3aefee41ac661052769a400afea83c1fb..a2c29f599a2609d27200d6e509d3b64fd33ef1af 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_flash_cm4.icf +++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_flash_cm4.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in RAM_SHARED_region { first section MAPPING_TABLE}; place in RAM_SHARED_region { section MB_MEM1}; -place in RAM_SHARED_region { section MB_MEM2}; \ No newline at end of file +place in RAM_SHARED_region { section MB_MEM2}; diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_sram_cm4.icf index f56ca8007ab4cce15cfda914925a7400dda70a11..e70f49f0df292d2eb861ba66e37078fb50a6bbe5 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_sram_cm4.icf +++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb10xx_sram_cm4.icf @@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_flash_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_flash_cm4.icf index e9cc1dd3aefee41ac661052769a400afea83c1fb..a2c29f599a2609d27200d6e509d3b64fd33ef1af 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_flash_cm4.icf +++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_flash_cm4.icf @@ -37,4 +37,4 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in RAM_SHARED_region { first section MAPPING_TABLE}; place in RAM_SHARED_region { section MB_MEM1}; -place in RAM_SHARED_region { section MB_MEM2}; \ No newline at end of file +place in RAM_SHARED_region { section MB_MEM2}; diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_sram_cm4.icf index f56ca8007ab4cce15cfda914925a7400dda70a11..e70f49f0df292d2eb861ba66e37078fb50a6bbe5 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_sram_cm4.icf +++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb15xx_sram_cm4.icf @@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf index ffb2da76dcb0d000c9bc4b45aab36630c2ba89df..a21a5ebd824731c967a9f4d160d69e4c4f021de2 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf +++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf @@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf index ffb2da76dcb0d000c9bc4b45aab36630c2ba89df..a21a5ebd824731c967a9f4d160d69e4c4f021de2 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf +++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf @@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb50xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb50xx_sram_cm4.icf index c7a00ef6a76feecd1b5ad4e478cb56621afb00e3..4643ea1b34b6fc85740b94df4fbae126314009d8 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb50xx_sram_cm4.icf +++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb50xx_sram_cm4.icf @@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb55xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb55xx_sram_cm4.icf index 360f4eb57dbea9ac71e333eec874674dbcb32cd8..beccb31d51049b1ff2bec8ef04801c36e8b93a4c 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb55xx_sram_cm4.icf +++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb55xx_sram_cm4.icf @@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf index 360f4eb57dbea9ac71e333eec874674dbcb32cd8..beccb31d51049b1ff2bec8ef04801c36e8b93a4c 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf +++ b/bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf @@ -36,4 +36,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm0plus.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm0plus.icf index cd3c90193b135eb020bca25def893147db97e7c2..92958bea2bba303eaa70fc3c523bfc112ad6a83c 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm0plus.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm0plus.icf @@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in RAM2_region { }; \ No newline at end of file +place in RAM2_region { }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm4.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm4.icf index e07c1ad667afff1e7a45c89d0424ddcce81772cf..058f058152dbabafa6b6d6e48616eecaefaf967e 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm4.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm4.icf @@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in RAM2_region { }; \ No newline at end of file +place in RAM2_region { }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm0plus.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm0plus.icf index 7fa21e5c3968ffb69f426da4d4f1a9d0283908c2..029f54665528d97879836009090a0c6ab7743684 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm0plus.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm0plus.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm0plus.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm0plus.icf index 8bdef4aea8f52556a0bcfd323ab521886b9b2c77..703e6948e52d79f2e4ea69638a5784d5d3aaff7a 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm0plus.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm0plus.icf @@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in RAM2_region { }; \ No newline at end of file +place in RAM2_region { }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm4.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm4.icf index e07c1ad667afff1e7a45c89d0424ddcce81772cf..058f058152dbabafa6b6d6e48616eecaefaf967e 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm4.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm4.icf @@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in RAM2_region { }; \ No newline at end of file +place in RAM2_region { }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm0plus.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm0plus.icf index 7fa21e5c3968ffb69f426da4d4f1a9d0283908c2..029f54665528d97879836009090a0c6ab7743684 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm0plus.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm0plus.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm4.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm4.icf index bfb4b542112f1777af59632fe7db05072ac62794..97de5deaaeb7e8f8f6dbcfe91cd3095618b6ddd4 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm4.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm4.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_flash.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_flash.icf index 927b92a6c799dbc37f97687c8efa52365fe6654d..5a03913be1c1d9f94c639c5d24974b33394fd39f 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_flash.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_flash.icf @@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in RAM2_region { }; \ No newline at end of file +place in RAM2_region { }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_sram.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_sram.icf index 8b109fa87efd713cfa0f3ddcfe5290c3fa923ab0..79387b77fc9a1cdb7703b50c723f5dcad21a893b 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_sram.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_sram.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_flash.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_flash.icf index 927b92a6c799dbc37f97687c8efa52365fe6654d..5a03913be1c1d9f94c639c5d24974b33394fd39f 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_flash.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_flash.icf @@ -37,4 +37,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; -place in RAM2_region { }; \ No newline at end of file +place in RAM2_region { }; diff --git a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_sram.icf b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_sram.icf index 8b109fa87efd713cfa0f3ddcfe5290c3fa923ab0..79387b77fc9a1cdb7703b50c723f5dcad21a893b 100644 --- a/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_sram.icf +++ b/bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_sram.icf @@ -32,4 +32,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/templates/stm32f0xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f0xx/board/linker_scripts/link.lds index 22d7036562fd07855a9010c0daed40f6c9151a5a..2549f2660f2e82017ed540f96c21045dc7a3772b 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32f0xx/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f10x/board/linker_scripts/link.lds index 3832982688375e731007dff21d3475529253a937..5a45f64a27fc572776b338c8f9e227807882275d 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32f10x/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32f2xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f2xx/board/linker_scripts/link.lds index fb9ea9b609f2635d7b9d2d299933c9f46c8add9f..cfa0efbe098f0536545cb42882de30e0d7063b4f 100644 --- a/bsp/stm32/libraries/templates/stm32f2xx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32f2xx/board/linker_scripts/link.lds @@ -77,7 +77,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -100,7 +100,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32f3xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f3xx/board/linker_scripts/link.lds index 94abb757aad6715c4c50e55d3d95f88947241e6a..39ec830ad74b9f4502404e80ff2c199c503536aa 100644 --- a/bsp/stm32/libraries/templates/stm32f3xx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32f3xx/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f4xx/board/linker_scripts/link.lds index a00d6b74bd7a99cfef72476d4c1e8c631ff226ed..224d1119a5638573d06086e0005e6d29aa5aaffe 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32f7xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32f7xx/board/linker_scripts/link.lds index a00d6b74bd7a99cfef72476d4c1e8c631ff226ed..224d1119a5638573d06086e0005e6d29aa5aaffe 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32f7xx/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32h7xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32h7xx/board/linker_scripts/link.lds index 9339c6af7cf71e74820ca1c07f8e0c77b68b281d..904cb2b14d37a75aa0f97ca83b7829a1c858316d 100644 --- a/bsp/stm32/libraries/templates/stm32h7xx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32h7xx/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32l1xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32l1xx/board/linker_scripts/link.lds index 9a0a7ef44ede9c33e6a8f85ebaeb0864baa7d6df..1cb995953a7e7c92adc8d1763169415b0669fe5b 100644 --- a/bsp/stm32/libraries/templates/stm32l1xx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32l1xx/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32l4xx/board/linker_scripts/link.lds index 3950cbac386c2422b764dd05febdd957fe47d5c9..4f3832bd9c53431bc8cc6b7069a577660f99d09c 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32l5xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32l5xx/board/linker_scripts/link.lds index 3950cbac386c2422b764dd05febdd957fe47d5c9..4f3832bd9c53431bc8cc6b7069a577660f99d09c 100644 --- a/bsp/stm32/libraries/templates/stm32l5xx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32l5xx/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.lds index e407492c390d23db4d0d359ec504ef5989e33565..b9410db545efc86b126d1f48276995393f4a8715 100644 --- a/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.sct b/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.sct index df7bcadf06fce1a7dda0f09fecdbc2818e79fbca..630576f580ac4d0dcd05f8884d9cf0b927df4b23 100644 --- a/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.sct +++ b/bsp/stm32/libraries/templates/stm32mp1xx/board/linker_scripts/link.sct @@ -1,35 +1,35 @@ -; ************************************************************* -; *** Scatter-Loading Description *** -; ************************************************************* - -LR_VECTORS 0x00000000 0x00000400 { ; load region size_region - .isr_vector +0 { - startup*.o (RESET, +First) - } -} - -LR_IROM1 0x10000000 0x00020000 { ; load region size_region - ER_IROM1 0x10000000 0x00020000 { ; load address = execution address - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - RW_IRAM1 0x10020000 0x00050000 { ; RW data - .ANY (+RW +ZI) - } -; RW_IRAM2 0x10020000 0x00020000 { ; RW data -; .ANY (+RW +ZI) -; } -; RW_IRAM3 0x10040000 0x00010000 { ; RW data -; .ANY (+RW +ZI) -; } -; RW_IRAM4 0x10050000 0x00010000 { ; RW data -; .ANY (+RW +ZI) -; } -; ***** To uncomment these 4 lines if OPENAMP used ***** -; *** Create region for OPENAMP *** - .resource_table +0 ALIGN 4 { ; resource table - *(.resource_table) - } - __OpenAMP_SHMEM__ 0x10050000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP -} +; ************************************************************* +; *** Scatter-Loading Description *** +; ************************************************************* + +LR_VECTORS 0x00000000 0x00000400 { ; load region size_region + .isr_vector +0 { + startup*.o (RESET, +First) + } +} + +LR_IROM1 0x10000000 0x00020000 { ; load region size_region + ER_IROM1 0x10000000 0x00020000 { ; load address = execution address + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x10020000 0x00050000 { ; RW data + .ANY (+RW +ZI) + } +; RW_IRAM2 0x10020000 0x00020000 { ; RW data +; .ANY (+RW +ZI) +; } +; RW_IRAM3 0x10040000 0x00010000 { ; RW data +; .ANY (+RW +ZI) +; } +; RW_IRAM4 0x10050000 0x00010000 { ; RW data +; .ANY (+RW +ZI) +; } +; ***** To uncomment these 4 lines if OPENAMP used ***** +; *** Create region for OPENAMP *** + .resource_table +0 ALIGN 4 { ; resource table + *(.resource_table) + } + __OpenAMP_SHMEM__ 0x10050000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP +} diff --git a/bsp/stm32/libraries/templates/stm32wbxx/board/linker_scripts/link.lds b/bsp/stm32/libraries/templates/stm32wbxx/board/linker_scripts/link.lds index 6afe5ee48436971fbd234716b264a032c6e963eb..77137ed7549391253a9e5e3458d7476d7012a69b 100644 --- a/bsp/stm32/libraries/templates/stm32wbxx/board/linker_scripts/link.lds +++ b/bsp/stm32/libraries/templates/stm32wbxx/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf index 6d0177d0bb33c04f057a4b0f7694a448b6236426..7f352fc72a893b00394e27edf7ee973caf9d70d0 100644 --- a/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.lds index bb905d06b11a9bf5bb15d45e14d2124c559ea888..2292c96e96474c82e228dcf5b52a3c56a966276c 100644 --- a/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.icf index f63d18876613ee25ddbc1619c672b6b488a3e397..e897e945c10035dd99da9bb8a2887712f8f9a9c8 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.lds index bac6b71c30b24ff6f93b753fd1f9eff226733441..463b33c098ae5458b3ef2d189cca34aabc8182f6 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f091-st-nucleo/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.lds index cc7da7d507cb35e07c20df455778b147309b118c..1e321b30bb4a2ac5be8913a20f501e1e0a390556 100644 --- a/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.sct b/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.sct index f64b03c9410b91f1249bb75a1377dfd5838eeb8a..6930ff4b5084181ef1534768f512c4530daf26d5 100644 --- a/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32f103-100ask-mini/board/linker_scripts/link.sct @@ -1,15 +1,15 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00010000 { ; load region size_region - ER_IROM1 0x08000000 0x00010000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00005000 { ; RW data - .ANY (+RW +ZI) - } -} - +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00010000 { ; load region size_region + ER_IROM1 0x08000000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00005000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.lds index 66c31ef7f86393ab5e53b811952c8a14ffd352c2..64f4be1e7a009ea296407e67649013b2881dab55 100644 --- a/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.sct b/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.sct index d500431408b0a76e67fb21d06aa458a2f4f7985d..0835abf43e781cddf45207f6fad946f12221105a 100644 --- a/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32f103-100ask-pro/board/linker_scripts/link.sct @@ -1,15 +1,15 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00080000 { ; load region size_region - ER_IROM1 0x08000000 0x00080000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00010000 { ; RW data - .ANY (+RW +ZI) - } -} - +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00010000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.icf b/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.icf index 5019b2d673757a3e293b6d91703fc49bfdb14b24..758734c181f70a0e9d2699f7234656dac62fb406 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.lds index 644fe833143ebf0ee86629578c3eb2d11e334c62..5a45f64a27fc572776b338c8f9e227807882275d 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-atk-nano/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-atk-warshipv3/board/linker_scripts/link.lds index 66c31ef7f86393ab5e53b811952c8a14ffd352c2..64f4be1e7a009ea296407e67649013b2881dab55 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.lds index 3832982688375e731007dff21d3475529253a937..5a45f64a27fc572776b338c8f9e227807882275d 100644 --- a/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.sct b/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.sct index c26b647ebfddc192a1814a6c017671314fcc61a4..f67cd68761e812f27e537c403f9d3af7b4cdeb5d 100644 --- a/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32f103-blue-pill/board/linker_scripts/link.sct @@ -1,15 +1,15 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00020000 { ; load region size_region - ER_IROM1 0x08000000 0x00020000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00005000 { ; RW data - .ANY (+RW +ZI) - } -} - +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00020000 { ; load region size_region + ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00005000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-dofly-M3S/board/linker_scripts/link.lds index 66c31ef7f86393ab5e53b811952c8a14ffd352c2..64f4be1e7a009ea296407e67649013b2881dab55 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-dofly-M3S/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.icf b/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.icf index 6f5c19b1a084d89f427a59afbd9718a561ddc21e..6569a9cfc6a2bec9bc767c358fa478e32aaa1054 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.lds index 9c7d04da7740580b9885096e1cd036b06b6955ca..99c745fe4c189bb6a7e0fa1b4a44b9aeb07b5231 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-dofly-lyc8/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.icf b/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.icf index 2b7eabee471435384149408b9ec6fb49d625232c..c1d6615d89abe7cc5a0552cf991461bcf327fe55 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.lds index deb1086a6e9606893a64529336aa60b0bab7c9eb..64f4be1e7a009ea296407e67649013b2881dab55 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/linker_scripts/link.lds @@ -51,9 +51,9 @@ SECTIONS KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - + . = ALIGN(4); - + _etext = .; } > ROM = 0 @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-gizwits-gokitv21/board/linker_scripts/link.lds index cc7da7d507cb35e07c20df455778b147309b118c..1e321b30bb4a2ac5be8913a20f501e1e0a390556 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-hw100k-ibox/board/linker_scripts/link.lds index 0f984bcea70396e0661759d25a3ad6dead1f2014..64f4be1e7a009ea296407e67649013b2881dab55 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/linker_scripts/link.lds @@ -46,7 +46,7 @@ SECTIONS __rt_init_end = .; . = ALIGN(4); - + PROVIDE(__ctors_start__ = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-onenet-nbiot/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-onenet-nbiot/board/linker_scripts/link.lds index 95185c57290d39748c89f2dba500c003f9502455..c96b01a1cf29219d589ab2f2fb9a08161e9ff839 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-onenet-nbiot/board/linker_scripts/link.lds @@ -52,7 +52,7 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); - . = ALIGN(4); + . = ALIGN(4); _etext = .; } > ROM = 0 @@ -84,13 +84,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-yf-ufun/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-yf-ufun/board/linker_scripts/link.lds index ee04854f398400a84d6515699fcce195ed7b2769..b16b453a1eb4d28c91b38a715ece56053bf5f44e 100644 --- a/bsp/stm32/stm32f103-yf-ufun/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-yf-ufun/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f103-ys-f1pro/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-ys-f1pro/board/linker_scripts/link.lds index 66c31ef7f86393ab5e53b811952c8a14ffd352c2..64f4be1e7a009ea296407e67649013b2881dab55 100644 --- a/bsp/stm32/stm32f103-ys-f1pro/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f103-ys-f1pro/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f107-uc-eval/board/linker_scripts/link.lds b/bsp/stm32/stm32f107-uc-eval/board/linker_scripts/link.lds index c8ac6f430fbdc155edad007b37ec5d026609d6c0..3a375297696e1c577c8568b1ff7e4cec75c616e2 100644 --- a/bsp/stm32/stm32f107-uc-eval/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f107-uc-eval/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds index 2f6329c65a9afce5ba6673ba25d39d4c4b0fd6ed..a810dd0cc9681c90c5806a0533944bdb5d16f577 100644 --- a/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds @@ -77,7 +77,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -100,7 +100,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f302-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f302-st-nucleo/board/linker_scripts/link.lds index 94abb757aad6715c4c50e55d3d95f88947241e6a..39ec830ad74b9f4502404e80ff2c199c503536aa 100644 --- a/bsp/stm32/stm32f302-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f302-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f401-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f401-st-nucleo/board/linker_scripts/link.lds index 58182b5efe5f1cc79e7f2b67e3d06143c41b4d1a..5ce1d786dee487314b3afd647d243a14ad04f5ad 100644 --- a/bsp/stm32/stm32f401-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f401-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/linker_scripts/link.lds b/bsp/stm32/stm32f405-smdz-breadfruit/board/linker_scripts/link.lds index b6b39bc08ed435e12407eebd2538ec92d4e40f05..3c53046fe99b1386ee8b6d78901c64743daea6d0 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/linker_scripts/link.lds @@ -93,7 +93,7 @@ SECTIONS _edata = . ; } >RAM1 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -116,7 +116,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM1 __bss_end = .; diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds index 087b672a5622853253b456ea333b6e3c06636b49..e6d932fd7c99ba8a4333a783242c5fb752e2d911 100644 --- a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds index a00d6b74bd7a99cfef72476d4c1e8c631ff226ed..224d1119a5638573d06086e0005e6d29aa5aaffe 100644 --- a/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f407-robomaster-c/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f407-st-discovery/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-st-discovery/board/linker_scripts/link.lds index f1ee8938c76b2d539bbdfbd4791aadc23eecdd73..4f8d01522a4619bdb902b3ac937c6e6ddb1f4c0a 100644 --- a/bsp/stm32/stm32f407-st-discovery/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f407-st-discovery/board/linker_scripts/link.lds @@ -87,7 +87,7 @@ SECTIONS _edata = . ; } >RAM1 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM1 __bss_end = .; diff --git a/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.icf index 90e7f8a9f5d2928a3b38a65517dc59dd09e419d2..45c8e206841e08f2bedfd4646ae407f078f1eaef 100644 --- a/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.lds index 5b45860ae12d4fba218911734839d952b5275c95..aeba68d589298befcd97fca935b144ee7201a653 100644 --- a/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f410-st-nucleo/board/linker_scripts/link.lds @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f411-atk-nano/board/linker_scripts/link.lds b/bsp/stm32/stm32f411-atk-nano/board/linker_scripts/link.lds index 9ca9dba2e935e0990a7ca2efe3c3078ac44c3618..e2fa98f495e3623091a2001fa707bdd014c3c717 100644 --- a/bsp/stm32/stm32f411-atk-nano/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f411-atk-nano/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf index 869a0842b73a293d6852b0f0047560b18141a0a3..4274ac64e6ca0b7a0f9f901fd014536a94ed42fe 100644 --- a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds index 4787919c55b42a352a4e8dceb11d132c615f9a3b..cd285981aed330f0cd71554ee52d833dfc38671a 100644 --- a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.icf b/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.icf index 869a0842b73a293d6852b0f0047560b18141a0a3..4274ac64e6ca0b7a0f9f901fd014536a94ed42fe 100644 --- a/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.lds b/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.lds index 4787919c55b42a352a4e8dceb11d132c615f9a3b..cd285981aed330f0cd71554ee52d833dfc38671a 100644 --- a/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f411-weact-blackpill/board/linker_scripts/link.lds @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.icf index db383c18a1f3a80eb57216aa7ee47414f8bfc288..4308d94d319a58085be442706b198613934eec76 100644 --- a/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.lds index d60a29c7ae045d007371b8debe7b992a87067ad3..1da876e360fff4573d84360fe9d86604ec42cdf9 100644 --- a/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f412-st-nucleo/board/linker_scripts/link.lds @@ -86,7 +86,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f413-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f413-st-nucleo/board/linker_scripts/link.lds index 1b8b1eb183f6441fe2a72bef41f9bdc2587ead54..49685f20780a8e2eddeb6b820f3e6619392dff27 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f413-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds index 41e3b21bb8031ed63937407ef18df1980a8dcfe5..a1d3475a846acde29df9b0f01d592a755360dac9 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } > RAM1 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM1 __bss_end = .; diff --git a/bsp/stm32/stm32f429-armfly-v6/board/linker_scripts/link.lds b/bsp/stm32/stm32f429-armfly-v6/board/linker_scripts/link.lds index 8ae9c8ca533f6b302219eee073a144d14d106a42..8884659baeee6790fd68e40f91a48e9aa64e41f3 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f429-armfly-v6/board/linker_scripts/link.lds @@ -93,7 +93,7 @@ SECTIONS _edata = . ; } >RAM1 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -116,7 +116,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM1 __bss_end = .; diff --git a/bsp/stm32/stm32f429-atk-apollo/board/linker_scripts/link.lds b/bsp/stm32/stm32f429-atk-apollo/board/linker_scripts/link.lds index 5a43a6a0f864efc8319e415c8ba301548ed2f74b..45861b463b713165b2e7349eeb586030e7e73ca6 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f429-atk-apollo/board/linker_scripts/link.lds @@ -93,13 +93,13 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - + . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM1 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -122,7 +122,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM1 __bss_end = .; diff --git a/bsp/stm32/stm32f429-fire-challenger/board/linker_scripts/link.lds b/bsp/stm32/stm32f429-fire-challenger/board/linker_scripts/link.lds index 8ae9c8ca533f6b302219eee073a144d14d106a42..8884659baeee6790fd68e40f91a48e9aa64e41f3 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f429-fire-challenger/board/linker_scripts/link.lds @@ -93,7 +93,7 @@ SECTIONS _edata = . ; } >RAM1 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -116,7 +116,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM1 __bss_end = .; diff --git a/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds b/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds index 4896d01f1f0d0d2df7ca7c5033aa34ecd91070e7..052bc52b6972b13d283ab0c8fa5e072561121d0f 100644 --- a/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.icf index 869a0842b73a293d6852b0f0047560b18141a0a3..4274ac64e6ca0b7a0f9f901fd014536a94ed42fe 100644 --- a/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.lds index 1a228ba8827826283e88b18410826796003d8da8..67337e873b1285d66d4cb3385f7b6388976a2166 100644 --- a/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f446-st-nucleo/board/linker_scripts/link.lds @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f469-st-disco/board/linker_scripts/link.lds b/bsp/stm32/stm32f469-st-disco/board/linker_scripts/link.lds index fe848340b66c59c108a189cdc1cc1a144abe6461..036786ab6b82a3c2ab96f842a5945a9e851fce55 100644 --- a/bsp/stm32/stm32f469-st-disco/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f469-st-disco/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.icf b/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.icf index 3ffc160fe54cbb7517eddde8afa952c6ec100f4f..f7b60c0847516e991bb8a94af92188b35e9472ae 100644 --- a/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.lds b/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.lds index 90be2e87f2c8565c07a36b47e8e721ee407001c3..14682f3d48980648a2585d551d45926c8563591a 100644 --- a/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f746-st-disco/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds index 90be2e87f2c8565c07a36b47e8e721ee407001c3..14682f3d48980648a2585d551d45926c8563591a 100644 --- a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct index 7a2a883cd35a3a1c418605ca1fcc7d26c1d3a09c..e4ae20230250fc18d221031b754bf50fbd5103bb 100644 --- a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct @@ -1,15 +1,15 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00200000 { ; load region size_region - ER_IROM1 0x08000000 0x00200000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20020000 0x00080000 { ; RW data - .ANY (+RW +ZI) - } -} - +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00200000 { ; load region size_region + ER_IROM1 0x08000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20020000 0x00080000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf b/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf index c3400bb59edaa8d6b3c4e09c55c96de4f878c9eb..569b08edd498b550608d28cbe2bb2aa1ac1c04e4 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds b/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds index a00d6b74bd7a99cfef72476d4c1e8c631ff226ed..224d1119a5638573d06086e0005e6d29aa5aaffe 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf index e817969a9e6372045be917b11029b1c371328225..ed2b24a6a576cfafb337e4ae04c7543c3549124a 100644 --- a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds index eca488ead422efb069319e100576661a414ec8ed..7c446dcc54b24d54eac6615a79a4c8f4b48f4c82 100644 --- a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f767-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f767-st-nucleo/board/linker_scripts/link.lds index 8672f3b67224c5a859ee277939f9393a1b276d7d..fea3793464c4bce8aa1bb825df46f86ccfce2929 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f767-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32f769-st-disco/board/linker_scripts/link.lds b/bsp/stm32/stm32f769-st-disco/board/linker_scripts/link.lds index 8672f3b67224c5a859ee277939f9393a1b276d7d..fea3793464c4bce8aa1bb825df46f86ccfce2929 100644 --- a/bsp/stm32/stm32f769-st-disco/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f769-st-disco/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds index 18c530241f6bc5a9833c532757319a77e7852c5d..1a463ec86a51468e055b78c0684816d25ec5f94b 100644 --- a/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.icf index fda72ef41f1d1f3ceb4c767a5b734e2136c0ace3..b170e7fb2b8663d4712683b2e238a9599c8b2bdc 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.lds index 18c530241f6bc5a9833c532757319a77e7852c5d..1a463ec86a51468e055b78c0684816d25ec5f94b 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32g071-st-nucleo/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.icf index 869a0842b73a293d6852b0f0047560b18141a0a3..4274ac64e6ca0b7a0f9f901fd014536a94ed42fe 100644 --- a/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.lds index 1a228ba8827826283e88b18410826796003d8da8..67337e873b1285d66d4cb3385f7b6388976a2166 100644 --- a/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32g431-st-nucleo/board/linker_scripts/link.lds @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.icf index 869a0842b73a293d6852b0f0047560b18141a0a3..4274ac64e6ca0b7a0f9f901fd014536a94ed42fe 100644 --- a/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.lds index 1a228ba8827826283e88b18410826796003d8da8..67337e873b1285d66d4cb3385f7b6388976a2166 100644 --- a/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32g474-st-nucleo/board/linker_scripts/link.lds @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32h743-armfly-v7/board/linker_scripts/link.lds b/bsp/stm32/stm32h743-armfly-v7/board/linker_scripts/link.lds index 9339c6af7cf71e74820ca1c07f8e0c77b68b281d..904cb2b14d37a75aa0f97ca83b7829a1c858316d 100644 --- a/bsp/stm32/stm32h743-armfly-v7/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32h743-armfly-v7/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32h743-atk-apollo/board/linker_scripts/link.lds b/bsp/stm32/stm32h743-atk-apollo/board/linker_scripts/link.lds index 9339c6af7cf71e74820ca1c07f8e0c77b68b281d..904cb2b14d37a75aa0f97ca83b7829a1c858316d 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32h743-atk-apollo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32h743-openmv-h7plus/board/linker_scripts/link.lds b/bsp/stm32/stm32h743-openmv-h7plus/board/linker_scripts/link.lds index 63af364fd03e89cb9eec6396c6206bca5a5bd316..02089a6f9b1d6e8daae3fab75668bd85a68f5544 100644 --- a/bsp/stm32/stm32h743-openmv-h7plus/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32h743-openmv-h7plus/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM2 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM2 __bss_end = .; diff --git a/bsp/stm32/stm32h743-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32h743-st-nucleo/board/linker_scripts/link.lds index 9339c6af7cf71e74820ca1c07f8e0c77b68b281d..904cb2b14d37a75aa0f97ca83b7829a1c858316d 100644 --- a/bsp/stm32/stm32h743-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32h743-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds index 7ad7729d2c5ae04c96283170b06a096721b4eb57..45d6f7aaa5d813876db38881135719b0a6acfe4c 100644 --- a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct index 2866134d54d278a5d3ed8685f5ac823f22395b7b..5381dfedfe1e2dbe85612c8d49928a17d33d4d88 100644 --- a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct @@ -11,4 +11,4 @@ LR_IROM1 0x08000000 0x00100000 { ; load region size_region RW_IRAM1 0x20000000 0x20020000{ ; RW data .ANY (+RW +ZI) } -} \ No newline at end of file +} diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/linker_scripts/link.lds b/bsp/stm32/stm32h750-armfly-h7-tool/board/linker_scripts/link.lds index f3bfeab24218c44f530164c58ef256580f42befe..3ebf411f326bcd0ff88d8d9f22e65e32340d2840 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32h750-artpi/board/linker_scripts/link.lds b/bsp/stm32/stm32h750-artpi/board/linker_scripts/link.lds index 0609f4d44532daba94641180df37b5e5b7813d04..4daa75f9c1a352ce1f83f6413186204c1a21c876 100644 --- a/bsp/stm32/stm32h750-artpi/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32h750-artpi/board/linker_scripts/link.lds @@ -113,7 +113,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -136,7 +136,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; @@ -149,7 +149,7 @@ SECTIONS . = ALIGN(4); __RxDecripSection_free__ = .; } > RxDecripSection - + .TxDecripSection (NOLOAD) : ALIGN(4) { . = ALIGN(4); @@ -158,7 +158,7 @@ SECTIONS . = ALIGN(4); __TxDecripSection_free__ = .; } > TxDecripSection - + .RxArraySection (NOLOAD) : ALIGN(4) { . = ALIGN(4); diff --git a/bsp/stm32/stm32h750-weact-ministm32h7xx/board/linker_scripts/link.lds b/bsp/stm32/stm32h750-weact-ministm32h7xx/board/linker_scripts/link.lds index 2597ee2e73fcdce1a5f568ec7e3e96a952803b2a..b758e1db72f7550c023a64b98582fe55c42491de 100644 --- a/bsp/stm32/stm32h750-weact-ministm32h7xx/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32h750-weact-ministm32h7xx/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds index 4fde4762faeff23e58b0ed3bcc19eb7b4c30f22c..246c835c6ac37807eb39c5738e104f44cf78f460 100644 --- a/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.icf index fd40e5bf2bb81f5ff7dc510e5c128f62b8456bc8..08e1fabb0f96f1a00375b2801adfcfa0274fb4a2 100644 --- a/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.icf @@ -26,4 +26,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.lds index ff393d1e71c59cf0f6627505775a195ff8ba68b9..77325e9337ce4675e8686e8444ffb32cf1f7b306 100644 --- a/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l053-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds index bc1bd87cdb8534f9171f57a001fc54914ab73eb2..55ac83ee36fcbea0cbc8d40999d061be197d70b7 100644 --- a/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM1 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM1 __bss_end = .; diff --git a/bsp/stm32/stm32l431-BearPi/board/linker_scripts/link.lds b/bsp/stm32/stm32l431-BearPi/board/linker_scripts/link.lds index f659e995884778af62e06bc145c5586710e655e6..e38fca8efa1ca6836c48b03fb5c79048b0726a96 100644 --- a/bsp/stm32/stm32l431-BearPi/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l431-BearPi/board/linker_scripts/link.lds @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM2 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM2 __bss_end = .; diff --git a/bsp/stm32/stm32l432-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l432-st-nucleo/board/linker_scripts/link.lds index f659e995884778af62e06bc145c5586710e655e6..e38fca8efa1ca6836c48b03fb5c79048b0726a96 100644 --- a/bsp/stm32/stm32l432-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l432-st-nucleo/board/linker_scripts/link.lds @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM2 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM2 __bss_end = .; diff --git a/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.icf b/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.icf index 158e0ce45de53e3f2f4af32c708a492df2825a22..9da5204f840191b6a37aadcb2da1ead24462fdc6 100644 --- a/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.lds b/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.lds index c8ac6f430fbdc155edad007b37ec5d026609d6c0..3a375297696e1c577c8568b1ff7e4cec75c616e2 100644 --- a/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l433-ali-startkit/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32l433-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l433-st-nucleo/board/linker_scripts/link.lds index f659e995884778af62e06bc145c5586710e655e6..e38fca8efa1ca6836c48b03fb5c79048b0726a96 100644 --- a/bsp/stm32/stm32l433-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l433-st-nucleo/board/linker_scripts/link.lds @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } >RAM2 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM2 __bss_end = .; diff --git a/bsp/stm32/stm32l452-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l452-st-nucleo/board/linker_scripts/link.lds index cb5dd4095edf46afaa0d9c341a3378f44533a9ed..280da426d3d5d3b4dbb150bf697405127478c321 100644 --- a/bsp/stm32/stm32l452-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l452-st-nucleo/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds index 85311d6b2ff4ef6fa3cd142a4d0d7074aaeda682..b648e8aef58c2017e9d39d9cac28b6586e0aea8d 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM1 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM1 __bss_end = .; diff --git a/bsp/stm32/stm32l475-st-discovery/board/linker_scripts/link.lds b/bsp/stm32/stm32l475-st-discovery/board/linker_scripts/link.lds index 22076de870ddf1132c6ba616c0d931d8efdac53d..ef680a75bd8a152b3b94688e2ce2d02a5d938f8b 100644 --- a/bsp/stm32/stm32l475-st-discovery/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l475-st-discovery/board/linker_scripts/link.lds @@ -7,7 +7,7 @@ MEMORY { ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */ - + RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 32k /* 32K sram */ } ENTRY(Reset_Handler) @@ -55,7 +55,7 @@ SECTIONS PROVIDE(__ctors_end__ = .); . = ALIGN(4); - + _etext = .; } > ROM = 0 @@ -92,7 +92,7 @@ SECTIONS _edata = . ; } > RAM2 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -115,7 +115,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM2 __bss_end = .; diff --git a/bsp/stm32/stm32l476-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l476-st-nucleo/board/linker_scripts/link.lds index a6aca31dae4929ed31a93a1d220641ef8c8b6b84..3c5e2c6498c23aac8eb090d7d26599a92391ee81 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l476-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM2 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM2 __bss_end = .; diff --git a/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.icf b/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.icf index 3ffc160fe54cbb7517eddde8afa952c6ec100f4f..f7b60c0847516e991bb8a94af92188b35e9472ae 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.lds b/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.lds index b180b27ef9c2c6672dc21b8d43e2c487f2703230..935c151a0103c74fb085a951d3f543db8a78ca21 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l496-ali-developer/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32l496-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l496-st-nucleo/board/linker_scripts/link.lds index 0571d2142fb4860a244c67dfd753f867c3998b90..c41cd9b92fdeae35f874e90b0d12de6774366546 100644 --- a/bsp/stm32/stm32l496-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l496-st-nucleo/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM1 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM1 __bss_end = .; diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf index 106c5e18d79d814ebe67b1d71eb5949c221fc4f2..1567e3006993e359da05a8d8bc35ba4c604c2135 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf @@ -4,14 +4,14 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x08000000; /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x08200000; -define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM1_end__ = 0x20030000; -define symbol __ICFEDIT_region_RAM2_start__ = 0x20040000; -define symbol __ICFEDIT_region_RAM2_end__ = 0x200A0000; -define symbol __ICFEDIT_region_RAM3_start__ = 0x10000000; -define symbol __ICFEDIT_region_RAM3_end__ = 0x10010000; +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x08200000; +define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM1_end__ = 0x20030000; +define symbol __ICFEDIT_region_RAM2_start__ = 0x20040000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x200A0000; +define symbol __ICFEDIT_region_RAM3_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM3_end__ = 0x10010000; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x0800; diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds index c675b6f406cf4ecbada96a2542d8852add686826..f4704af097ad2679abde4fa2a00af66624b1a881 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds @@ -40,7 +40,7 @@ SECTIONS __vsymtab_start = .; KEEP(*(VSymTab)) __vsymtab_end = .; - + /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; @@ -89,7 +89,7 @@ SECTIONS _edata = . ; } >RAM1 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -112,7 +112,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM1 __bss_end = .; diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct index 4ef96219c296469d8a1017ecc3444f06f163ae2b..fabfaff8bfb4942fcf28e55579c5cf88726bd07b 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct @@ -2,16 +2,16 @@ ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* -LR_IROM1 0x08000000 0x00200000 { ; load region size_region - ER_IROM1 0x08000000 0x00200000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } +LR_IROM1 0x08000000 0x00200000 { ; load region size_region + ER_IROM1 0x08000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } - RW_IRAM1 0x20000000 0x00030000 { ; RW data - .ANY (+RW +ZI) - } + RW_IRAM1 0x20000000 0x00030000 { ; RW data + .ANY (+RW +ZI) + } diff --git a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.lds b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.lds index 55c0cd87ac8c199e829348017e8011c3e7bff7b2..bf249b1f0b129cd0085c580aa25dbf4ecff252d1 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.lds @@ -89,7 +89,7 @@ SECTIONS _edata = . ; } >RAM2 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -112,7 +112,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM2 __bss_end = .; diff --git a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct index b8cea677e911e0e6e22895b6f8f9a86bbfe6cb91..75aad352202c632ed343305983a20ee70c8c3206 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct @@ -2,16 +2,16 @@ ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* -LR_IROM1 0x08000000 0x00200000 { ; load region size_region - ER_IROM1 0x08000000 0x00200000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } +LR_IROM1 0x08000000 0x00200000 { ; load region size_region + ER_IROM1 0x08000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } - RW_IRAM1 0x20000000 0x00040000 { ; RW data - .ANY (+RW +ZI) - } + RW_IRAM1 0x20000000 0x00040000 { ; RW data + .ANY (+RW +ZI) + } diff --git a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.icf b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.icf index 19710673072bb88a70ba8165b51840a518349928..2e86c5bea4da27213a477f8e2bd1b869dd25650a 100644 --- a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.icf @@ -24,7 +24,7 @@ define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __IC define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__] - | mem:[from IRAM3_region_start to IRAM3_region_end ]; + | mem:[from IRAM3_region_start to IRAM3_region_end ]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; @@ -42,4 +42,4 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in IROM_region { readonly }; -place in IRAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file +place in IRAM_region { readwrite, block CSTACK, block HEAP }; diff --git a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.lds b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.lds index f51f38fe554c110d0d07467d7bde17995cc01ce4..5d7aba37c4197c477b9a3896e7fcc19c77c239da 100644 --- a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.lds @@ -88,7 +88,7 @@ SECTIONS _edata = . ; } >RAM2 - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -111,7 +111,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM2 __bss_end = .; diff --git a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.sct b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.sct index 1789d52d637426f4f3c6dced6592d80ff703fc66..2bfecb2c5d81ac2595f00dad0401e0fe1a7e1176 100644 --- a/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.sct @@ -2,16 +2,16 @@ ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* -LR_IROM1 0x08000000 0x00200000 { ; load region size_region - ER_IROM1 0x08000000 0x00200000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } +LR_IROM1 0x08000000 0x00200000 { ; load region size_region + ER_IROM1 0x08000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } - RW_IRAM1 0x20000000 0x000A0000 { ; RW data - .ANY (+RW +ZI) - } + RW_IRAM1 0x20000000 0x000A0000 { ; RW data + .ANY (+RW +ZI) + } diff --git a/bsp/stm32/stm32l552-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l552-st-nucleo/board/linker_scripts/link.lds index 3950cbac386c2422b764dd05febdd957fe47d5c9..4f3832bd9c53431bc8cc6b7069a577660f99d09c 100644 --- a/bsp/stm32/stm32l552-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32l552-st-nucleo/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.lds b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.lds index e407492c390d23db4d0d359ec504ef5989e33565..b9410db545efc86b126d1f48276995393f4a8715 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct index a64b8cc98bb9ea684db11b9627312ff99e8c06be..5cbf7d39430fd2c6880656652b83e1334a522df9 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct @@ -1,27 +1,27 @@ -; ************************************************************* -; *** Scatter-Loading Description *** -; ************************************************************* - -LR_VECTORS 0x00000000 0x00000400 { ; load region size_region - .isr_vector +0 { - startup*.o (RESET, +First) - } -} - -LR_IROM1 0x10000000 0x00030000 { ; load region size_region - ER_IROM1 0x10000000 0x00030000 { ; load address = execution address - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - RW_IRAM1 0x10030000 0x00010000 { ; RW data - .ANY (+RW +ZI) - } - - -; ***** Create region for OPENAMP ***** -; *** These 4 lines can be commented if OPENAMP is not used ***** - .resource_table +0 ALIGN 4 { ; resource table - *(.resource_table) - } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP -} +; ************************************************************* +; *** Scatter-Loading Description *** +; ************************************************************* + +LR_VECTORS 0x00000000 0x00000400 { ; load region size_region + .isr_vector +0 { + startup*.o (RESET, +First) + } +} + +LR_IROM1 0x10000000 0x00030000 { ; load region size_region + ER_IROM1 0x10000000 0x00030000 { ; load address = execution address + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x10030000 0x00010000 { ; RW data + .ANY (+RW +ZI) + } + + +; ***** Create region for OPENAMP ***** +; *** These 4 lines can be commented if OPENAMP is not used ***** + .resource_table +0 ALIGN 4 { ; resource table + *(.resource_table) + } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP +} diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds index e407492c390d23db4d0d359ec504ef5989e33565..b9410db545efc86b126d1f48276995393f4a8715 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds @@ -91,7 +91,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct index a64b8cc98bb9ea684db11b9627312ff99e8c06be..5cbf7d39430fd2c6880656652b83e1334a522df9 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct @@ -1,27 +1,27 @@ -; ************************************************************* -; *** Scatter-Loading Description *** -; ************************************************************* - -LR_VECTORS 0x00000000 0x00000400 { ; load region size_region - .isr_vector +0 { - startup*.o (RESET, +First) - } -} - -LR_IROM1 0x10000000 0x00030000 { ; load region size_region - ER_IROM1 0x10000000 0x00030000 { ; load address = execution address - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - RW_IRAM1 0x10030000 0x00010000 { ; RW data - .ANY (+RW +ZI) - } - - -; ***** Create region for OPENAMP ***** -; *** These 4 lines can be commented if OPENAMP is not used ***** - .resource_table +0 ALIGN 4 { ; resource table - *(.resource_table) - } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP -} +; ************************************************************* +; *** Scatter-Loading Description *** +; ************************************************************* + +LR_VECTORS 0x00000000 0x00000400 { ; load region size_region + .isr_vector +0 { + startup*.o (RESET, +First) + } +} + +LR_IROM1 0x10000000 0x00030000 { ; load region size_region + ER_IROM1 0x10000000 0x00030000 { ; load address = execution address + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x10030000 0x00010000 { ; RW data + .ANY (+RW +ZI) + } + + +; ***** Create region for OPENAMP ***** +; *** These 4 lines can be commented if OPENAMP is not used ***** + .resource_table +0 ALIGN 4 { ; resource table + *(.resource_table) + } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP +} diff --git a/bsp/stm32/stm32u575-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32u575-st-nucleo/board/linker_scripts/link.lds index 3950cbac386c2422b764dd05febdd957fe47d5c9..4f3832bd9c53431bc8cc6b7069a577660f99d09c 100644 --- a/bsp/stm32/stm32u575-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32u575-st-nucleo/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds index 85635b902d50740d6ce8025e46a053a20f5c96a2..60c099e0fa828567dfd762d94dd33dda1f94449b 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; @@ -158,5 +158,5 @@ SECTIONS MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED - + } diff --git a/bsp/synwit/swm320/drivers/linker_scripts/link.icf b/bsp/synwit/swm320/drivers/linker_scripts/link.icf index 4d4eb646235816e2f84be5d89f1faba1e60b9bf6..f87eef728c0dbc504c6bac63e1ea1053d521587b 100644 --- a/bsp/synwit/swm320/drivers/linker_scripts/link.icf +++ b/bsp/synwit/swm320/drivers/linker_scripts/link.icf @@ -59,4 +59,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in IROM_region { readonly }; place in EROM_region { readonly section application_specific_ro }; place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; -place in ERAM_region { readwrite section application_specific_rw }; \ No newline at end of file +place in ERAM_region { readwrite section application_specific_rw }; diff --git a/bsp/synwit/swm320/drivers/linker_scripts/link.lds b/bsp/synwit/swm320/drivers/linker_scripts/link.lds index 2f6896cfb34b2f7c8e6396132584b7da95d093cc..bb543c2a48b8d41feeaee9b4bf6f2ded98eb3a63 100644 --- a/bsp/synwit/swm320/drivers/linker_scripts/link.lds +++ b/bsp/synwit/swm320/drivers/linker_scripts/link.lds @@ -73,7 +73,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -94,7 +94,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/synwit/swm341/drivers/linker_scripts/link.icf b/bsp/synwit/swm341/drivers/linker_scripts/link.icf index 3bd6d6ff15aa5c6eea4deb459db82ec6ef60dae1..761d539e180199aaeba61ef37d5559417aa31e59 100644 --- a/bsp/synwit/swm341/drivers/linker_scripts/link.icf +++ b/bsp/synwit/swm341/drivers/linker_scripts/link.icf @@ -59,4 +59,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in IROM_region { readonly }; place in EROM_region { readonly section application_specific_ro }; place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; -place in ERAM_region { readwrite section application_specific_rw }; \ No newline at end of file +place in ERAM_region { readwrite section application_specific_rw }; diff --git a/bsp/synwit/swm341/drivers/linker_scripts/link.lds b/bsp/synwit/swm341/drivers/linker_scripts/link.lds index 7d24f5f96d164b6ee3beab04f89df9118443a01b..40458f1598fcdc6de93d46cd16486cd1a0f8b7d7 100644 --- a/bsp/synwit/swm341/drivers/linker_scripts/link.lds +++ b/bsp/synwit/swm341/drivers/linker_scripts/link.lds @@ -90,7 +90,7 @@ SECTIONS _edata = . ; } > RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Source/ARM/tae32f53xx_ac5_sram.sct b/bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Source/ARM/tae32f53xx_ac5_sram.sct index 040fa5fe6c147472f116f7cec268b41352510f35..493f8d99e11c68aa6206b848d9c70728406bd61b 100644 --- a/bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Source/ARM/tae32f53xx_ac5_sram.sct +++ b/bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Source/ARM/tae32f53xx_ac5_sram.sct @@ -80,16 +80,16 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region .ANY (+XO) } - RW_RAMA __RW_BASE __RW_SIZE { ; RWA data + RW_RAMA __RW_BASE __RW_SIZE { ; RWA data *.o (SECTION_RAMA) .ANY (+RW +ZI) } - RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region + RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region *.o (SECTION_RAMB) } - RW_RAMC __RAMC_BASE __RAMC_SIZE { ; RWC region + RW_RAMC __RAMC_BASE __RAMC_SIZE { ; RWC region *.o (SECTION_RAMC) } diff --git a/bsp/tae32f5300/board/linker_scripts/link.icf b/bsp/tae32f5300/board/linker_scripts/link.icf index 3a80cf803bfe898866f520431e200b3bc53c446b..17a41b11c9a7f6a876f2b8a8834d393b390d95da 100644 --- a/bsp/tae32f5300/board/linker_scripts/link.icf +++ b/bsp/tae32f5300/board/linker_scripts/link.icf @@ -51,7 +51,7 @@ define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to | mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__] | mem:[from __ICFEDIT_region_IRAM4_start__ to __ICFEDIT_region_IRAM4_end__] | mem:[from __ICFEDIT_region_IRAM5_start__ to __ICFEDIT_region_IRAM5_end__] - | mem:[from __ICFEDIT_region_IRAM6_start__ to __ICFEDIT_region_IRAM6_end__]; + | mem:[from __ICFEDIT_region_IRAM6_start__ to __ICFEDIT_region_IRAM6_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; @@ -62,4 +62,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK, block HEAP }; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK, block HEAP }; diff --git a/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct b/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct index b41d86675c45c01bef9e8fa54d9910785820141f..b34e523c3e02b429b19cfe5ff19ce0a622c6bb6c 100644 --- a/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct +++ b/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct @@ -16,7 +16,7 @@ /*--------------------- RAMCODE Section Configuration ------------------------ ; RAMCODE Configuration -; RAMCODE in which MCU +; RAMCODE in which MCU ; <3=> TAE32F5300 ; <2=> TAE32F5600 ; RAMCODE Base Address is different in different MCUs @@ -96,7 +96,7 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region .ANY (+RO) .ANY (+XO) } - + #if __RW_CODE_SIZE > 0 RW_CODE __RW_CODE_BASE __RW_CODE_SIZE { *.o (RAMCODE) @@ -115,7 +115,7 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } - + RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region *.o (SECTION_RAMB) } diff --git a/bsp/tkm32F499/drivers/linker_scripts/link.lds b/bsp/tkm32F499/drivers/linker_scripts/link.lds index aad42bdb39019ecd51f4ddbd699bb834d2065881..21222812c4e87af98625224250034bd7dc8ac6a8 100644 --- a/bsp/tkm32F499/drivers/linker_scripts/link.lds +++ b/bsp/tkm32F499/drivers/linker_scripts/link.lds @@ -73,7 +73,7 @@ SECTIONS _edata = . ; } >DATA - .stack : + .stack : { . = . + _system_stack_size; . = ALIGN(4); @@ -94,7 +94,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > DATA __bss_end = .; diff --git a/bsp/tm4c123bsp/board/linker_scripts/link.icf b/bsp/tm4c123bsp/board/linker_scripts/link.icf index 953c77e9098454a0d86936573220f04fea2e8f02..76d1f1a51f8258bba59b1c1040d101f3f02b9662 100644 --- a/bsp/tm4c123bsp/board/linker_scripts/link.icf +++ b/bsp/tm4c123bsp/board/linker_scripts/link.icf @@ -4,20 +4,20 @@ // // Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Texas Instruments (TI) is supplying this software for use solely and // exclusively on TI's microcontroller products. The software is owned by // TI and/or its suppliers, and is protected under applicable copyright // laws. You may not combine this software with "viral" open-source // software in order to form a larger program. -// +// // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. -// +// // This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package. // //***************************************************************************** diff --git a/bsp/tm4c123bsp/board/linker_scripts/link.sct b/bsp/tm4c123bsp/board/linker_scripts/link.sct index 58f2ff6f661b65cd9a17f5400b98b205a942d6d7..fd90fe75adc1bd7d5c64c8c1f5d25dd17552c414 100644 --- a/bsp/tm4c123bsp/board/linker_scripts/link.sct +++ b/bsp/tm4c123bsp/board/linker_scripts/link.sct @@ -4,20 +4,20 @@ ; ; Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. ; Software License Agreement -; +; ; Texas Instruments (TI) is supplying this software for use solely and ; exclusively on TI's microcontroller products. The software is owned by ; TI and/or its suppliers, and is protected under applicable copyright ; laws. You may not combine this software with "viral" open-source ; software in order to form a larger program. -; +; ; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. ; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT ; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY ; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL ; DAMAGES, FOR ANY REASON WHATSOEVER. -; +; ; This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package. ; ;****************************************************************************** diff --git a/bsp/tm4c129x/tm4c_rom.icf b/bsp/tm4c129x/tm4c_rom.icf index 4bda7a154a4612fa8614cdb2ab52b9943fe26eb0..89084ba8a06df85104deeae3cfa2f0a1a92ebc0f 100644 --- a/bsp/tm4c129x/tm4c_rom.icf +++ b/bsp/tm4c129x/tm4c_rom.icf @@ -4,20 +4,20 @@ // // Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement -// +// // Texas Instruments (TI) is supplying this software for use solely and // exclusively on TI's microcontroller products. The software is owned by // TI and/or its suppliers, and is protected under applicable copyright // laws. You may not combine this software with "viral" open-source // software in order to form a larger program. -// +// // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. -// +// // This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. // //***************************************************************************** @@ -84,4 +84,4 @@ place in SRAM { readwrite, block HEAP }; keep { section FSymTab }; keep { section VSymTab }; -keep { section .rti_fn* }; \ No newline at end of file +keep { section .rti_fn* }; diff --git a/bsp/tm4c129x/tm4c_rom.sct b/bsp/tm4c129x/tm4c_rom.sct index 9162ff8c44f7ec2a80c2f8ad2520e3bff89419b3..b3d09c3f511b442d76af92fa1e09cc190cc548d7 100644 --- a/bsp/tm4c129x/tm4c_rom.sct +++ b/bsp/tm4c129x/tm4c_rom.sct @@ -4,20 +4,20 @@ ; ; Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. ; Software License Agreement -; +; ; Texas Instruments (TI) is supplying this software for use solely and ; exclusively on TI's microcontroller products. The software is owned by ; TI and/or its suppliers, and is protected under applicable copyright ; laws. You may not combine this software with "viral" open-source ; software in order to form a larger program. -; +; ; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. ; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT ; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY ; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL ; DAMAGES, FOR ANY REASON WHATSOEVER. -; +; ; This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. ; ;****************************************************************************** diff --git a/bsp/w60x/drivers/linker_scripts/link.icf b/bsp/w60x/drivers/linker_scripts/link.icf index a3e861ed85d248caeb6e91e9f83c3a6f8e34a8df..be8ea4df39fcec714d6e74ae849cff99e1e94956 100644 --- a/bsp/w60x/drivers/linker_scripts/link.icf +++ b/bsp/w60x/drivers/linker_scripts/link.icf @@ -1,30 +1,30 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08010100; -/*-Memory Regions-*/ -/* rom 959K */ -define symbol __ICFEDIT_region_ROM_start__ = 0x08010100; -define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; -/* ram 160k */ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20028000; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0xc00; -define symbol __ICFEDIT_size_heap__ = 0x1A000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08010100; +/*-Memory Regions-*/ +/* rom 959K */ +define symbol __ICFEDIT_region_ROM_start__ = 0x08010100; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +/* ram 160k */ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20028000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0xc00; +define symbol __ICFEDIT_size_heap__ = 0x1A000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/w60x/drivers/linker_scripts/link.lds b/bsp/w60x/drivers/linker_scripts/link.lds index 81c8f5631b8ae0f0cbe1d8fba08d3e3ebe699898..88b389c8d8202f15ae8d11ad64457f5881da6669 100644 --- a/bsp/w60x/drivers/linker_scripts/link.lds +++ b/bsp/w60x/drivers/linker_scripts/link.lds @@ -1,5 +1,5 @@ -/* Linker script to configure memory regions. - * Need modifying for a specific board. +/* Linker script to configure memory regions. + * Need modifying for a specific board. * FLASH.ORIGIN: starting address of flash * FLASH.LENGTH: length of flash * RAM.ORIGIN: starting address of RAM bank 0 @@ -17,7 +17,7 @@ MEMORY * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler - * + * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end @@ -61,7 +61,7 @@ SECTIONS *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t*) - + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -108,7 +108,7 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - .ARM.extab : + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH @@ -180,7 +180,7 @@ SECTIONS *(COMMON) . = ALIGN(4); __bss_end__ = .; - } > RAM + } > RAM ASSERT(__StackTop <= 0x20028000, "stack address error") } diff --git a/bsp/w60x/drivers/linker_scripts/link.sct b/bsp/w60x/drivers/linker_scripts/link.sct index 76ca106e6bfde8cafddfac324a2928a5fbaf37b4..6e31c6ac7fad0ee5c8b32c5a4d1c01c28d8dd952 100644 --- a/bsp/w60x/drivers/linker_scripts/link.sct +++ b/bsp/w60x/drivers/linker_scripts/link.sct @@ -1,15 +1,15 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08010100 0x000EFEFF { ; load region size_region - ER_IROM1 0x08010100 0x000EFEFF { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - RW_IRAM1 0x20000000 0x00028000 { ; RW data - .ANY (+RW +ZI) - } -} +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08010100 0x000EFEFF { ; load region size_region + ER_IROM1 0x08010100 0x000EFEFF { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00028000 { ; RW data + .ANY (+RW +ZI) + } +} diff --git a/bsp/wch/arm/ch32f103c8-core/board/linker_scripts/link.lds b/bsp/wch/arm/ch32f103c8-core/board/linker_scripts/link.lds index 63e0f7e4c389472f83d2b6771ea54dc08bd269f1..d0f4c6dafe3d472d919372878c0db6e65304dc23 100644 --- a/bsp/wch/arm/ch32f103c8-core/board/linker_scripts/link.lds +++ b/bsp/wch/arm/ch32f103c8-core/board/linker_scripts/link.lds @@ -86,7 +86,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/wch/arm/ch32f203r-evt/board/linker_scripts/link.lds b/bsp/wch/arm/ch32f203r-evt/board/linker_scripts/link.lds index 0d5e7beafe11e0a3adfeb88f675c17da1255f076..dd68dd192dea6f303744211cd2fb684b26375cc6 100644 --- a/bsp/wch/arm/ch32f203r-evt/board/linker_scripts/link.lds +++ b/bsp/wch/arm/ch32f203r-evt/board/linker_scripts/link.lds @@ -86,7 +86,7 @@ SECTIONS _edata = . ; } >RAM - .stack : + .stack : { . = ALIGN(4); _sstack = .; @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; - + *(.bss.init) } > RAM __bss_end = .; diff --git a/bsp/wch/risc-v/ch32v103r-evt/board/linker_scripts/link.lds b/bsp/wch/risc-v/ch32v103r-evt/board/linker_scripts/link.lds index c81a03907bed9d98513dfb008164d1a679457068..431a6f55d5aed54771b54b2ee0d5e46a9dda59d4 100644 --- a/bsp/wch/risc-v/ch32v103r-evt/board/linker_scripts/link.lds +++ b/bsp/wch/risc-v/ch32v103r-evt/board/linker_scripts/link.lds @@ -1 +1,194 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t.*) /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) __fsymtab_end = .; . = ALIGN(4); __vsymtab_start = .; KEEP(*(VSymTab)) __vsymtab_end = .; . = ALIGN(4); /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; . = ALIGN(4); /* section information for modules */ . = ALIGN(4); __rtmsymtab_start = .; KEEP(*(RTMSymTab)) __rtmsymtab_end = .; . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t.*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + . = ALIGN(4); + + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds b/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds index b0051ab14d944d11e31fe4cb352191cb1a88300b..cc60a8caaede0965970c54a1c73e00f50d9f0cd6 100644 --- a/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds +++ b/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds @@ -7,41 +7,41 @@ PROVIDE( _stack_size = __stack_size ); MEMORY { - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { - .init : - { - _sinit = .; - . = ALIGN(4); - KEEP(*(SORT_NONE(.init))) - . = ALIGN(4); - _einit = .; - } >FLASH AT>FLASH + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH .vector : { *(.vector); - . = ALIGN(64); + . = ALIGN(64); } >FLASH AT>FLASH - .text : - { - . = ALIGN(4); - *(.text) - *(.text.*) - *(.rodata) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t.*) - - /* section information for finsh shell */ + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t.*) + + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) @@ -51,7 +51,7 @@ SECTIONS KEEP(*(VSymTab)) __vsymtab_end = .; . = ALIGN(4); - + /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; @@ -64,129 +64,129 @@ SECTIONS __rtmsymtab_start = .; KEEP(*(RTMSymTab)) __rtmsymtab_end = .; - . = ALIGN(4); - - } >FLASH AT>FLASH - - .fini : - { - KEEP(*(SORT_NONE(.fini))) - . = ALIGN(4); - } >FLASH AT>FLASH - - PROVIDE( _etext = . ); - PROVIDE( _eitcm = . ); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH AT>FLASH - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH AT>FLASH - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH AT>FLASH - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >FLASH AT>FLASH - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >FLASH AT>FLASH - - .dalign : - { - . = ALIGN(4); - PROVIDE(_data_vma = .); - } >RAM AT>FLASH - - .dlalign : - { - . = ALIGN(4); - PROVIDE(_data_lma = .); - } >FLASH AT>FLASH - - .data : - { - *(.gnu.linkonce.r.*) - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800 ); - *(.sdata .sdata.*) - *(.sdata2.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - . = ALIGN(4); - PROVIDE( _edata = .); - } >RAM AT>FLASH - - .bss : - { - . = ALIGN(4); - PROVIDE( _sbss = .); - *(.sbss*) + . = ALIGN(4); + + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) *(.gnu.linkonce.sb.*) - *(.bss*) - *(.gnu.linkonce.b.*) - *(COMMON*) - . = ALIGN(4); - PROVIDE( _ebss = .); - } >RAM AT>FLASH + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH - PROVIDE( _end = _ebss); - PROVIDE( end = . ); + PROVIDE( _end = _ebss); + PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { - PROVIDE( _heap_end = . ); + PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); - } >RAM + } >RAM } diff --git a/bsp/wh44b0/wh44b0_ram.lds b/bsp/wh44b0/wh44b0_ram.lds index e40eaa3b28a86426bab29660bb73f86548ab2d40..f94069adc747e75c9f2b67e8121b8c1ba2127aed 100644 --- a/bsp/wh44b0/wh44b0_ram.lds +++ b/bsp/wh44b0/wh44b0_ram.lds @@ -3,41 +3,41 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x0c000000; - - . = ALIGN(4); - .text : { - *(.init) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .nobss : { *(.nobss) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - __bss_end = .; - - /* stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } - - _end = .; + . = 0x0c000000; + + . = ALIGN(4); + .text : { + *(.init) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .nobss : { *(.nobss) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; + + /* stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _end = .; } diff --git a/bsp/wh44b0/wh44b0_rom.lds b/bsp/wh44b0/wh44b0_rom.lds index 85e0c5702754160b2b7092b166cbf3d259689267..f94069adc747e75c9f2b67e8121b8c1ba2127aed 100644 --- a/bsp/wh44b0/wh44b0_rom.lds +++ b/bsp/wh44b0/wh44b0_rom.lds @@ -3,41 +3,41 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x0c000000; + . = 0x0c000000; - . = ALIGN(4); - .text : { - *(.init) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .nobss : { *(.nobss) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - __bss_end = .; - - /* stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } - - _end = .; + . = ALIGN(4); + .text : { + *(.init) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .nobss : { *(.nobss) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; + + /* stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _end = .; } diff --git a/bsp/x86/x86_ram.lds b/bsp/x86/x86_ram.lds index 089d9973c4db401e3bdb4901928c3e75dc9733bf..6344f62bbf7845f5a0195a3af2256f1acfa77358 100644 --- a/bsp/x86/x86_ram.lds +++ b/bsp/x86/x86_ram.lds @@ -21,7 +21,7 @@ SECTIONS __vsymtab_start = .; KEEP(*(VSymTab)) __vsymtab_end = .; - . = ALIGN(4); + . = ALIGN(4); __rtmsymtab_start = .; KEEP(*(RTMSymTab)); __rtmsymtab_end = .; @@ -32,7 +32,7 @@ SECTIONS KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; } - + . = ALIGN(4); .rodata : { *(.rodata*) } @@ -57,6 +57,6 @@ SECTIONS .debug_line 0 : { *(.debug_line) } .debug_pubnames 0 : { *(.debug_pubnames) } .debug_aranges 0 : { *(.debug_aranges) } - + _end = .; } diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds index ab85fa4c134a6980fba6d1c59dfc8ea9d753c6eb..e3b0df4d3939392f61ebc17686d9a56e6a9e5a0c 100644 --- a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds +++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds @@ -45,117 +45,117 @@ ENTRY(Reset_Handler) SECTIONS { - .text : - { - *flash_start*.o - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - - . = ALIGN(4); - __exidx_start = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + .text : + { + *flash_start*.o + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + + . = ALIGN(4); + __exidx_start = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct index 71ad394af91a86eacdefe048fcfbf5175b9c935a..40596eca1441045ce3d10e2760f5f6299e34f95a 100644 --- a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct +++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct @@ -11,22 +11,22 @@ LR_IROM1 0x00000000 0x0007fff { ; load region size_region } LR_IROM3 0x1000200 0x200{ - ER_IROM3 0x1000200 { - flash_start.o (|.flash_start|,+RO) - } + ER_IROM3 0x1000200 { + flash_start.o (|.flash_start|,+RO) + } ER_IROM3_1 0x1000340 { - startup.o (|.INIT_STACK_HEAP|,+RO) - } + startup.o (|.INIT_STACK_HEAP|,+RO) + } } LR_IROM4 0x1000400 0x1000000{ - ER_IROM4 0x1000400 { - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 0x00020000 0x010000 { ; RW data - .ANY (+RW +ZI) - } + ER_IROM4 0x1000400 { + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 0x00020000 0x010000 { ; RW data + .ANY (+RW +ZI) + } }