From 2e8375dd126775d0aa328685efe316577ea5009c Mon Sep 17 00:00:00 2001 From: tangweikang Date: Thu, 18 Jun 2020 19:22:38 +0800 Subject: [PATCH] =?UTF-8?q?[bsp][stm32][drv=5Fsdio.c]=20=20adapt=20stm32f2?= =?UTF-8?q?=20series=20|=20=E9=80=82=E9=85=8D=20stm32f2=20=E7=B3=BB?= =?UTF-8?q?=E5=88=97?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32/libraries/HAL_Drivers/drv_sdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c index 61387f24ef..290c89e159 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c @@ -852,7 +852,7 @@ int rt_hw_sdio_init(void) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ SET_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc); tmpreg = READ_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc); -#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F2) SET_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc); /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc); -- GitLab